Motorola TMS320C6711D User Manual

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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
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Excellent-Price/Performance Floating-Point  
Digital Signal Processor (DSP):  
TMS320C6711D  
− Eight 32-Bit Instructions/Cycle  
− 167-, 200-, 250-MHz Clock Rates  
− 6-, 5-, 4-ns Instruction Cycle Time  
− 1000, 1200, 1500 MFLOPS  
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32-Bit External Memory Interface (EMIF)  
− Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
− Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
− 256M-Byte Total Addressable External  
Memory Space  
Advanced Very Long Instruction Word  
(VLIW) C67xDSP Core  
− Eight Highly Independent Functional  
Units:  
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16-Bit Host-Port Interface (HPI)  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− ST-Bus-Switching Compatible  
− Up to 256 Channels Each  
− AC97-Compatible  
− Four ALUs (Floating- and Fixed-Point)  
− Two ALUs (Fixed-Point)  
− Two Multipliers (Floating- and  
Fixed-Point)  
− Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
− Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
Two 32-Bit General-Purpose Timers  
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Flexible Software Configurable PLL-Based  
Clock Generator Module  
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Instruction Set Features  
− Hardware Support for IEEE  
Single-Precision and Double-Precision  
Instructions  
− Byte-Addressable (8-, 16-, 32-Bit Data)  
− 8-Bit Overflow Protection  
− Saturation  
− Bit-Field Extract, Set, Clear  
− Bit-Counting  
− Normalization  
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A Dedicated General-Purpose Input/Output  
(GPIO) Module With 5 Pins  
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
272-Pin Ball Grid Array (BGA) Package  
(GDP and ZDP Suffixes)  
CMOS Technology  
− 0.13-µm/6-Level Copper Metal Process  
3.3-V I/O, 1.4-V Internal (−250)  
L1/L2 Memory Architecture  
− 32K-Bit (4K-Byte) L1P Program Cache  
(Direct Mapped)  
− 32K-Bit (4K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
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3.3-V I/O, 1.20-V Internal  
− 512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache  
(Flexible Data/Program Allocation)  
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Device Configuration  
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot  
− Endianness: Little Endian, Big Endian  
Enhanced Direct-Memory-Access (EDMA)  
Controller (16 Independent Channels)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C67x and C67x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
These values are compatible with existing 1.26V designs.  
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Copyright 2005, Texas Instruments Incorporated  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
REVISION HISTORY  
The TMS320C6711D device-specific documentation has been split from TMS320C6711, TMS320C6711B,  
TMS320C6711C, TMS320C6711D Floating−Point Digital Signal Processors, literature number SPRS088N, into a  
separate Data Sheet, literature number SPRS292. It also highlights technical changes made to SPRS292 to gen-  
erate SPRS292A; these changes are marked by “[Revision A]” in the Revision History table below.  
Scope: Updated information on McBSP and JTAG for clarification. Changed Pin Description for A12 and B11  
(Revisions SPRS292 and SPRS292A). Updated Nomenclature figure by adding device−specific information for  
the ZDP package. Updated Characteristics of the Processor table with device−specific information (footnote) for  
the ZDP package  
TI Recommends for new designs that the following pins be configured as such:  
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Pin A12 connected directly to CV  
(core power)  
DD  
Pin B11 connected directly to V (ground)  
ss  
PAGE(S)  
NO.  
ADDITIONS/CHANGES/DELETIONS  
Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:  
Removed “CE1 width 32−bit” from Functional Description for “00” in HD[4:3](BOOTMODE) Configuration Pin  
Terminal Functions, Resets and Interrupts section:  
Updated IPU/IPD for RESET Signal Name from “IPU” to “−−”  
Terminal Functions, Host Port Interface section:  
Removed “CE1 width 32−bit” from Description for “00” in Bootmode HD[4:3]  
Terminal Functions, Reserved for Test section:  
Updated Description for RSV Signal Name, A12 GDP/ZDP  
Updated Description for RSV Signal Name, B11 GDP/ZDP  
Terminal Functions, Reserved for Test section:  
Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended”) − [Revision A]  
Updated/changed Description for RSV Signal Name, B11 GDP (to “recommended”) − [Revision A]  
Device Support, device and development-support tool nomenclature:  
Updated figure for clarity  
Device Support, documentation support section:  
Updated paragraphs for clarity  
IEEE 1149.1 JTAG Compatibility Statement section:  
Updated/added paragraphs for clarity  
Recommended Operating Conditions:  
Added V  
Added V  
Maximum voltage during overshoot row and associated footnote  
Maximum voltage during undershoot row and associated footnote  
OS,  
US,  
Parameter Measurement Information:  
AC transient rise/fall time specifications section:  
Added AC Transient Specification Rise Time figure  
Added AC Transient Specification Fall Time figure  
MULTICHANNEL BUFFERED SERIAL PORT TIMING:  
switching characteristics over recommended operating conditions for McBSP section:  
Updated McBSP Timings figure for clarification  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
GDP and ZDP BGA packages (bottom view)  
GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGES  
(BOTTOM VIEW)  
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The ZDP mechanical package designator represents the version of the GDP package with lead−free balls. For more detailed information, see  
the Mechanical Data section of this document.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
description  
The TMS320C67xDSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D  
devices ) compose the floating-point DSP family in the TMS320C6000DSP platform. The C6711, C6711B,  
C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word  
(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for  
multichannel and multifunction applications.  
With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of  
200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective  
solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational  
flexibility of high-speed controllers and the numerical capability of array processors. This processor has  
32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight  
functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point  
multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.  
The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip  
peripherals.  
The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of  
peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache  
(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory  
space that is shared between program and data space. L2 memory can be configured as mapped memory,  
cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs),  
two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)  
capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.  
The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer  
to simplify programming and scheduling, and a Windowsdebugger interface for visibility into source code  
execution.  
TMS320C6000 is a trademark of Texas Instruments.  
Windows is a registered trademark of the Microsoft Corporation.  
Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated  
as C6711D or 11D.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
device characteristics  
Table 1 provides an overview of the C6711D DSP. The table shows significant features of the device, including  
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more  
details on the C6000DSP device part numbers and part numbering, see Figure 5.  
Table 1. Characteristics of the C6711D Processor  
INTERNAL CLOCK  
SOURCE  
C6711D  
FLOATING-POINT DSP  
HARDWARE FEATURES  
ECLKIN  
EMIF  
SYSCLK3 or ECLKIN  
CPU clock frequency  
CPU/2 clock frequency  
SYSCLK2  
1
1
EDMA  
HPI  
1
Peripherals  
CPU/2 clock frequency  
SYSCLK2  
McBSPs  
32-Bit Timers  
2
2
CPU/4 clock frequency  
1/2 of SYSCLK2  
SYSCLK2  
GPIO Module  
Size (Bytes)  
1
72K  
4K-Byte (4KB) L1 Program  
(L1P) Cache  
4KB L1 Data (L1D) Cache  
64KB Unified Mapped  
RAM/Cache (L2)  
On-Chip Memory  
Organization  
CPU ID+  
CPU Rev ID  
Control Status Register (CSR.[31:16])  
MHz  
0x0203  
Frequency  
167, 200, 250  
4 ns (C6711DGDP-250)  
5 ns (C6711DGDP−200  
and C6711DZDP−200)  
6 ns (C6711DGDPA−167  
and C6711DZDPA−167)  
Cycle Time  
ns  
1.20  
Core (V)  
1.4 (−250)  
Voltage  
I/O (V)  
3.3  
PLL Options  
CLKIN frequency multiplier  
Prescaler  
Multiplier  
Postscaler  
/1, /2, /3, ..., /32  
x4, x5, x6, ..., x25  
/1, /2, /3, ..., /32  
Clock Generator Options  
272-Pin BGA  
(GDP and ZDP)  
BGA Package  
27 x 27 mm  
§
Process Technology  
Product Status  
µm  
0.13 µm  
Product Preview (PP)  
Advance Information (AI)  
Production Data (PD)  
PD  
These values are compatible with existing 1.26−V designs.  
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include testing of all parameters.  
§
The ZDP package devices are supported in the same speed grades as the GDP package devices (available upon request).  
C6000 is a trademark of Texas Instruments.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
device compatibility  
The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set;  
thus, making new system designs easier and providing faster time to market. The following list summarizes the  
device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices:  
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The C6211 and C6211B devices have a fixed-point C62x CPU, while the C6711, C6711B, C6711C, and  
C6711D devices have a floating-point C67x CPU.  
The C6211/C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended  
temperature device that also runs at -150 MHz), while the C6711/C6711B device runs at -150 and -100 MHz  
(with a C6711BGFNA extended temperature device that also runs at -100 MHz) and the C6711C and  
C6711D devices run at -200 clock speed (with a C6711CGDPA and C6711DGDPA extended temperature  
devices that also run at -167 MHz).  
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The C6211/C6211B, C6711-100, and C6711B devices have a core voltage of 1.8 V, the C6711-150 device  
core voltage is 1.9 V, and the C6711C and C6711D devices operate with a core voltage of 1.20 V.  
There are several enhancements and features that are only available on the C6711C and C6711D devices,  
such as: the CLKOUT3 signal, a software programmable PLL and PLL Controller, and a GPIO peripheral  
module. The C6711D device also has additional enhancements such as: EMIF Big Endian mode  
correctness EMIFBE and the L1D requestor priority to L2 bit [“P” bit] in the cache configuration (CCFG)  
register.  
For more detailed discussion on the migration of a C6211, C6211B, C6711, C6711B device to a TMS320C6711C  
device, see the Migrating from TMS320C6211B/6711B to TMS320C6711C application report (literature number  
SPRA837).  
For a more detailed discussion on the similarities/differences between the C6211 and C6711 devices, see the  
How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the  
TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively).  
This value is compatible with existing 1.26V designs.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
functional block and CPU (DSP core) diagram  
Digital Signal Processor  
SDRAM  
External  
SBSRAM  
32  
Memory  
Interface  
(EMIF)  
L1P Cache  
Direct Mapped  
4K Bytes Total  
SRAM  
ROM/FLASH  
I/O Devices  
Timer 0  
Timer 1  
C6000CPU (DSP Core)  
Instruction Fetch  
Control  
Registers  
Multichannel  
Buffered  
Serial Port 1  
(McBSP1)  
L2  
Instruction Dispatch  
Instruction Decode  
Memory  
4 Banks  
64K Bytes  
Total  
Control  
Logic  
Framing Chips:  
H.100, MVIP,  
SCSA, T1, E1  
AC97 Devices,  
SPI Devices,  
Codecs  
Enhanced  
DMA  
Controller  
(16 channel)  
Data Path A  
A Register File  
Data Path B  
Test  
B Register File  
In-Circuit  
Emulation  
Multichannel  
Buffered  
Serial Port 0  
(McBSP0)  
Interrupt  
Control  
.L1 .S1 .M1 .D1  
.D2 .M2 .S2 .L2  
Host Port  
Interface  
(HPI)  
16  
L1D Cache  
2-Way Set  
Associative  
Interrupt  
Selector  
4K Bytes Total  
Power-Down  
Logic  
Boot  
Configuration  
PLL  
GPIO  
In addition to fixed-point instructions, these functional units execute floating-point instructions.  
The device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider).  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
CPU (DSP core) description  
The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit  
instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by  
which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit  
of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous  
instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch  
packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute  
packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.  
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains  
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files  
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along  
with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and  
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that  
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which  
the two sets of functional units can access data from the register files on the opposite side. While register access  
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,  
register access using the register file across the CPU supports one read and one write per cycle.  
The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight  
functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two  
functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a  
total of 128 bits per cycle.  
Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers  
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data  
transfers between the register files and the memory. The data address driven by the .D units allows data  
addresses generated from one register file to be used to load or store data to or from the other register file. The  
C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes  
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some  
registers, however, are singled out to support specific addressing or to hold the condition for conditional  
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.  
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results  
available every clock cycle.  
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.  
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least  
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous  
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,  
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the  
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of  
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet  
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one  
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch  
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units  
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit  
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store  
instructions are byte-, half-word, or word-addressable.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
CPU (DSP core) description (continued)  
src1  
.L1  
src2  
dst  
8
8
long dst  
long src  
8
32  
32  
LD1 32 MSB  
ST1  
Register  
File A  
(A0−A15)  
long src  
long dst  
dst  
8
Data Path A  
.S1  
src1  
src2  
dst  
.M1  
src1  
src2  
LD1 32 LSB  
DA1  
dst  
src1  
src2  
.D1  
2X  
1X  
src2  
src1  
dst  
DA2  
.D2  
.M2  
LD2 32 LSB  
src2  
src1  
dst  
src2  
Register  
File B  
(B0−B15)  
src1  
dst  
.S2  
Data Path B  
8
8
long dst  
long src  
8
32  
32  
LD2 32 MSB  
ST2  
long src  
long dst  
dst  
8
.L2  
src2  
src1  
Control  
Register File  
In addition to fixed-point instructions, these functional units execute floating-point instructions.  
Figure 1. TMS320C67xCPU (DSP Core) Data Paths  
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memory map summary  
Table 2 shows the memory map address ranges of the device. Internal memory is always located at address  
0 and can be used as both program and data memory. The configuration registers for the common peripherals  
are located at the same hex address ranges. The external memory address ranges in the device begin at the  
address location 0x8000 0000.  
Table 2. TMS320C6711D Memory Map Summary  
MEMORY BLOCK DESCRIPTION  
Internal RAM (L2)  
BLOCK SIZE (BYTES)  
HEX ADDRESS RANGE  
0000 0000 – 0000 FFFF  
0001 0000 – 017F FFFF  
0180 0000 – 0183 FFFF  
0184 0000 – 0187 FFFF  
0188 0000 – 018B FFFF  
018C 0000 – 018F FFFF  
0190 0000 – 0193 FFFF  
0194 0000 – 0197 FFFF  
0198 0000 – 019B FFFF  
019C 0000 – 019C 01FF  
019C 0200 – 019C 0203  
019C 0204 – 019F FFFF  
01A0 0000 – 01A3 FFFF  
01A4 0000 – 01AF FFFF  
01B0 0000 – 01B0 3FFF  
01B0 4000 – 01B7 BFFF  
01B7 C000 – 01B7 DFFF  
01B7 E000 – 01FF FFFF  
0200 0000 – 0200 0033  
0200 0034 – 2FFF FFFF  
3000 0000 – 33FF FFFF  
3400 0000 – 37FF FFFF  
3800 0000 – 3BFF FFFF  
3C00 0000 – 7FFF FFFF  
8000 0000 – 8FFF FFFF  
9000 0000 – 9FFF FFFF  
A000 0000 – AFFF FFFF  
B000 0000 – BFFF FFFF  
C000 0000 – FFFF FFFF  
64K  
24M – 64K  
256K  
256K  
256K  
256K  
256K  
256K  
256K  
512  
Reserved  
External Memory Interface (EMIF) Registers  
L2 Registers  
HPI Registers  
McBSP 0 Registers  
McBSP 1 Registers  
Timer 0 Registers  
Timer 1 Registers  
Interrupt Selector Registers  
Device Configuration Registers  
Reserved  
4
256K − 516  
256K  
768K  
16K  
EDMA RAM and EDMA Registers  
Reserved  
GPIO Registers  
Reserved  
480K  
8K  
PLL Controller Registers  
Reserved  
4M + 520K  
52  
QDMA Registers  
Reserved  
736M – 52  
64M  
McBSP 0 Data/Peripheral Data Bus  
McBSP 1 Data/Peripheral Data Bus  
Reserved  
64M  
64M  
Reserved  
1G + 64M  
256M  
256M  
256M  
256M  
1G  
EMIF CE0  
EMIF CE1  
EMIF CE2  
EMIF CE3  
Reserved  
The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of  
addressable memory, additional general-purpose output pin or external logic is required.  
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peripheral register descriptions  
Table 3 through Table 14 identify the peripheral registers for the device by their register names, acronyms, and  
hex address or hex address range. For more detailed information on the register contents, bit names, and their  
descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview  
Reference Guide (literature number SPRU190).  
Table 3. EMIF Registers  
HEX ADDRESS RANGE  
0180 0000  
ACRONYM  
GBLCTL  
CECTL1  
CECTL0  
REGISTER NAME  
EMIF global control  
EMIF CE1 space control  
EMIF CE0 space control  
Reserved  
0180 0004  
0180 0008  
0180 000C  
0180 0010  
CECTL2  
CECTL3  
SDCTL  
SDTIM  
SDEXT  
EMIF CE2 space control  
EMIF CE3 space control  
EMIF SDRAM control  
EMIF SDRAM refresh control  
EMIF SDRAM extension  
Reserved  
0180 0014  
0180 0018  
0180 001C  
0180 0020  
0180 0024 − 0183 FFFF  
Table 4. L2 Cache Registers  
HEX ADDRESS RANGE  
0184 0000  
ACRONYM  
CCFG  
REGISTER NAME  
Cache configuration register  
0184 4000  
L2WBAR  
L2WWC  
L2WIBAR  
L2WIWC  
L1PIBAR  
L1PIWC  
L1DWIBAR  
L1DWIWC  
L2WB  
L2 writeback base address register  
0184 4004  
L2 writeback word count register  
0184 4010  
L2 writeback-invalidate base address register  
L2 writeback-invalidate word count register  
L1P invalidate base address register  
0184 4014  
0184 4020  
0184 4024  
L1P invalidate word count register  
0184 4030  
L1D writeback-invalidate base address register  
L1D writeback-invalidate word count register  
L2 writeback all register  
0184 4034  
0184 5000  
0184 5004  
L2WBINV  
MAR0  
L2 writeback-invalidate all register  
0184 8200  
Controls CE0 range 8000 0000 − 80FF FFFF  
Controls CE0 range 8100 0000 − 81FF FFFF  
Controls CE0 range 8200 0000 − 82FF FFFF  
Controls CE0 range 8300 0000 − 83FF FFFF  
Controls CE1 range 9000 0000 − 90FF FFFF  
Controls CE1 range 9100 0000 − 91FF FFFF  
Controls CE1 range 9200 0000 − 92FF FFFF  
Controls CE1 range 9300 0000 − 93FF FFFF  
Controls CE2 range A000 0000 − A0FF FFFF  
Controls CE2 range A100 0000 − A1FF FFFF  
Controls CE2 range A200 0000 − A2FF FFFF  
Controls CE2 range A300 0000 − A3FF FFFF  
Controls CE3 range B000 0000 − B0FF FFFF  
Controls CE3 range B100 0000 − B1FF FFFF  
Controls CE3 range B200 0000 − B2FF FFFF  
Controls CE3 range B300 0000 − B3FF FFFF  
Reserved  
0184 8204  
MAR1  
0184 8208  
MAR2  
0184 820C  
0184 8240  
MAR3  
MAR4  
0184 8244  
MAR5  
0184 8248  
MAR6  
0184 824C  
0184 8280  
MAR7  
MAR8  
0184 8284  
MAR9  
0184 8288  
MAR10  
MAR11  
MAR12  
MAR13  
MAR14  
MAR15  
0184 828C  
0184 82C0  
0184 82C4  
0184 82C8  
0184 82CC  
0184 82D0 − 0187 FFFF  
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peripheral register descriptions (continued)  
Table 5. Interrupt Selector Registers  
HEX ADDRESS RANGE  
ACRONYM  
REGISTER NAME  
COMMENTS  
Selects which interrupts drive CPU interrupts 10−15  
(INT10−INT15)  
019C 0000  
MUXH  
Interrupt multiplexer high  
Interrupt multiplexer low  
Selects which interrupts drive CPU interrupts 4−9  
(INT04−INT09)  
019C 0004  
MUXL  
Sets the polarity of the external interrupts  
(EXT_INT4−EXT_INT7)  
019C 0008  
EXTPOL  
External interrupt polarity  
Reserved  
019C 000C − 019F FFFF  
Table 6. Device Registers  
HEX ADDRESS RANGE  
019C 0200  
ACRONYM  
DEVCFG  
REGISTER DESCRIPTION  
This register allows the user control of the EMIF input  
clock source. For more detailed information on the  
device configuration register, see the Device  
Configurations section of this data sheet.  
Device Configuration  
Reserved  
019C 0204 − 019F FFFF  
Identifies which CPU and defines the silicon revision of  
the CPU. This register also offers the user control of  
device operation.  
For more detailed information on the CPU Control  
Status Register, see the CPU CSR Register  
Description section of this data sheet.  
N/A  
CSR  
CPU Control Status Register  
Table 7. EDMA Parameter RAM  
HEX ADDRESS RANGE  
01A0 0000 − 01A0 0017  
01A0 0018 − 01A0 002F  
01A0 0030 − 01A0 0047  
01A0 0048 − 01A0 005F  
01A0 0060 − 01A0 0077  
01A0 0078 − 01A0 008F  
01A0 0090 − 01A0 00A7  
01A0 00A8 − 01A0 00BF  
01A0 00C0 − 01A0 00D7  
01A0 00D8 − 01A0 00EF  
01A0 00F0 − 01A0 00107  
01A0 0108 − 01A0 011F  
01A0 0120 − 01A0 0137  
01A0 0138 − 01A0 014F  
01A0 0150 − 01A0 0167  
01A0 0168 − 01A0 017F  
01A0 0180 − 01A0 0197  
01A0 0198 − 01A0 01AF  
...  
ACRONYM  
REGISTER NAME  
Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event  
Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event  
Reload/link parameters for Event 0−15  
Reload/link parameters for Event 0−15  
...  
01A0 07E0 − 01A0 07F7  
01A0 07F8 − 01A0 07FF  
Reload/link parameters for Event 0−15  
Scratch pad area (2 words)  
The device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.  
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peripheral register descriptions (continued)  
For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2.  
31  
0
EDMA Parameter  
Word 0  
Word 1  
Word 2  
Word 3  
Word 4  
Word 5  
EDMA Channel Options Parameter (OPT)  
EDMA Channel Source Address (SRC)  
OPT  
SRC  
CNT  
DST  
IDX  
Array/Frame Count (FRMCNT)  
Element Count (ELECNT)  
EDMA Channel Destination Address (DST)  
Array/Frame Index (FRMIDX)  
Element Count Reload (ELERLD)  
Element Index (ELEIDX)  
Link Address (LINK)  
RLD  
Figure 2. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event  
Table 8. EDMA Registers  
HEX ADDRESS RANGE  
01A0 0800 − 01A0 FEFC  
01A0 FF00  
ACRONYM  
REGISTER NAME  
Reserved  
ESEL0  
ESEL1  
EDMA event selector 0  
EDMA event selector 1  
Reserved  
01A0 FF04  
01A0 FF08 − 01A0 FF0B  
01A0 FF0C  
ESEL3  
EDMA event selector 3  
Reserved  
01A0 FF1F − 01A0 FFDC  
01A0 FFE0  
PQSR  
CIPR  
CIER  
CCER  
ER  
Priority queue status register  
Channel interrupt pending register  
Channel interrupt enable register  
Channel chain enable register  
Event register  
01A0 FFE4  
01A0 FFE8  
01A0 FFEC  
01A0 FFF0  
01A0 FFF4  
EER  
ECR  
ESR  
Event enable register  
Event clear register  
Event set register  
01A0 FFF8  
01A0 FFFC  
01A1 0000 − 01A3 FFFF  
Reserved  
Table 9. Quick DMA (QDMA) and Pseudo Registers  
HEX ADDRESS RANGE  
0200 0000  
ACRONYM  
QOPT  
QSRC  
QCNT  
QDST  
QIDX  
REGISTER NAME  
QDMA options parameter register  
QDMA source address register  
QDMA frame count register  
QDMA destination address register  
QDMA index register  
0200 0004  
0200 0008  
0200 000C  
0200 0010  
0200 0014 − 0200 001C  
0200 0020  
Reserved  
QSOPT  
QSSRC  
QSCNT  
QSDST  
QSIDX  
QDMA pseudo options register  
0200 0024  
QDMA pseudo source address register  
QDMA pseudo frame count register  
QDMA pseudo destination address register  
QDMA pseudo index register  
0200 0028  
0200 002C  
0200 0030  
All the QDMA and Pseudo registers are write-accessible only  
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peripheral register descriptions (continued)  
Table 10. PLL Controller Registers  
HEX ADDRESS RANGE  
01B7 C000  
ACRONYM  
PLLPID  
REGISTER NAME  
Peripheral identification register (PID) [0x00010801 for PLL Controller]  
Reserved  
01B7 C004 − 01B7 C0FF  
01B7 C100  
PLLCSR  
PLL control/status register  
Reserved  
01B7 C104 − 01B7 C10F  
01B7 C110  
PLLM  
PLL multiplier control register  
PLL controller divider 0 register  
PLL controller divider 1 register  
PLL controller divider 2 register  
PLL controller divider 3 register  
Oscillator divider 1 register  
Reserved  
01B7 C114  
PLLDIV0  
PLLDIV1  
PLLDIV2  
PLLDIV3  
OSCDIV1  
01B7 C118  
01B7 C11C  
01B7 C120  
01B7 C124  
01B7 C128 − 01B7 DFFF  
Table 11. GPIO Registers  
HEX ADDRESS RANGE  
01B0 0000  
ACRONYM  
GPEN  
GPDIR  
GPVAL  
REGISTER NAME  
GPIO enable register  
GPIO direction register  
GPIO value register  
01B0 0004  
01B0 0008  
01B0 000C  
Reserved  
01B0 0010  
GPDH  
GPHM  
GPDL  
GPLM  
GPGC  
GPPOL  
GPIO delta high register  
GPIO high mask register  
GPIO delta low register  
GPIO low mask register  
GPIO global control register  
GPIO interrupt polarity register  
Reserved  
01B0 0014  
01B0 0018  
01B0 001C  
01B0 0020  
01B0 0024  
01B0 0028 − 01B0 3FFF  
Table 12. HPI Registers  
HEX ADDRESS RANGE  
ACRONYM  
HPID  
HPIA  
REGISTER NAME  
HPI data register  
COMMENTS  
Host read/write access only  
HPI address register  
HPI control register  
Reserved  
Host read/write access only  
0188 0000  
HPIC  
Both Host/CPU read/write access  
0188 0001 − 018B FFFF  
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peripheral register descriptions (continued)  
Table 13. Timer 0 and Timer 1 Registers  
HEX ADDRESS RANGE  
ACRONYM  
REGISTER NAME  
COMMENTS  
TIMER 0  
TIMER 1  
Determines the operating  
mode of the timer, monitors the  
timer status, and controls the  
function of the TOUT pin.  
0194 0000  
0194 0004  
0198 0000  
CTLx  
Timer x control register  
Timer x period register  
Contains the number of timer  
input clock cycles to count.  
This number controls the  
TSTAT signal frequency.  
0198 0004  
PRDx  
Contains the current value of  
the incrementing counter.  
0194 0008  
0198 0008  
CNTx  
Timer x counter register  
Reserved  
0194 000C − 0197 FFFF  
0198 000C − 019B FFFF  
Table 14. McBSP0 and McBSP1 Registers  
HEX ADDRESS RANGE  
ACRONYM  
REGISTER DESCRIPTION  
McBSP0  
McBSP1  
McBSPx data receive register via Configuration Bus  
018C 0000  
0190 0000  
DRRx  
The CPU and EDMA controller can only read this register;  
they cannot write to it.  
3000 0000 − 33FF FFFF  
018C 0004  
3400 0000 − 37FF FFFF  
0190 0004  
DRRx  
DXRx  
DXRx  
SPCRx  
RCRx  
XCRx  
SRGRx  
MCRx  
RCERx  
XCERx  
PCRx  
McBSPx data receive register via Peripheral Data Bus  
McBSPx data transmit register via Configuration Bus  
McBSPx data transmit register via Peripheral Data Bus  
McBSPx serial port control register  
McBSPx receive control register  
3000 0000 − 33FF FFFF  
018C 0008  
3400 0000 − 37FF FFFF  
0190 0008  
018C 000C  
0190 000C  
018C 0010  
0190 0010  
McBSPx transmit control register  
018C 0014  
0190 0014  
McBSPx sample rate generator register  
McBSPx multichannel control register  
McBSPx receive channel enable register  
McBSPx transmit channel enable register  
McBSPx pin control register  
018C 0018  
0190 0018  
018C 001C  
0190 001C  
018C 0020  
0190 0020  
018C 0024  
0190 0024  
018C 0028 − 018F FFFF  
0190 0028 − 0193 FFFF  
Reserved  
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signal groups description  
CLKIN  
RESET  
NMI  
CLKOUT3  
EXT_INT7  
EXT_INT6  
EXT_INT5  
EXT_INT4  
Reset and  
Interrupts  
Clock/PLL  
CLKOUT2  
CLKMODE0  
PLLHV  
TMS  
TDO  
TDI  
RSV  
RSV  
RSV  
TCK  
IEEE Standard  
1149.1  
(JTAG)  
Emulation  
TRST  
EMU0  
EMU1  
EMU2  
EMU3  
EMU4  
EMU5  
Reserved  
RSV  
RSV  
RSV  
Control/Status  
HPI  
(Host-Port Interface)  
16  
HD[15:0]  
Data  
HAS  
HCNTL0  
HCNTL1  
HR/W  
HCS  
HDS1  
HDS2  
HRDY  
HINT  
Register Select  
Control  
Half-Word  
Select  
HHWIL  
For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin. Default function is CLKOUT2. To use this pin as GPIO, the  
GP2EN bit in the GPEN register and the GP2DIR bit in the GPDIR register must be properly configured.  
For this device, the external interrupts (EXT_INT[7−4]) go through the general-purpose input/output (GPIO) module. When used  
as interrupt inputs, the GP[7−4] pins must be configured as inputs (via the GPDIR register) and enabled (via the GPEN register)  
in addition to enabling the interrupts in the interrupt enable register (IER).  
Figure 3. CPU (DSP Core) and Peripheral Signals  
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signal groups description (continued)  
32  
ED[31:0]  
Data  
ECLKIN  
ECLKOUT  
Memory  
Control  
ARE/SDCAS/SSADS  
CE3  
CE2  
CE1  
CE0  
AOE/SDRAS/SSOE  
AWE/SDWE/SSWE  
ARDY  
Memory Map  
Space Select  
20  
EA[21:2]  
Address  
HOLD  
HOLDA  
Bus  
Arbitration  
BE3  
BE2  
BE1  
BE0  
BUSREQ  
Byte Enables  
EMIF  
(External Memory Interface)  
TOUT1  
TINP1  
TOUT0  
TINP0  
Timer 1  
Timer 0  
Timers  
McBSP1  
Transmit  
McBSP0  
Transmit  
CLKX1  
FSX1  
DX1  
CLKX0  
FSX0  
DX0  
CLKR1  
FSR1  
DR1  
CLKR0  
FSR0  
DR0  
Receive  
Clock  
Receive  
Clock  
CLKS1  
CLKS0  
McBSPs  
(Multichannel Buffered Serial Ports)  
For proper device operation, these pins must be externally pulled up with a 10-kresistor.  
Figure 4. Peripheral Signals  
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signal groups description (continued)  
GP[7](EXT_INT7)  
GP[6](EXT_INT6)  
GP[5](EXT_INT5)  
GP[4](EXT_INT4)  
GPIO  
CLKOUT2/GP[2]  
General-Purpose Input/Output (GPIO) Port  
Figure 4. Peripheral Signals (Continued)  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
DEVICE CONFIGURATIONS  
On this device, bootmode and certain device configurations/peripheral selections are determined at device  
reset. Also, other device configurations (e.g., EMIF input clock source) are software-configurable via the device  
configurations register (DEVCFG) [address location 0x019C0200] after device reset.  
device configurations at device reset  
Table 15 describes the C6711D device configuration pins, which are set up via internal or external  
pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12) and CLKMODE0 pin. These  
configuration pins must be in the desired state until reset is released.  
For proper device operation, do not oppose the internal pulldowns/pullups in the HD [14, 13, 11:9, 7, 1, 0] pins  
with the external pullups/pulldowns or by driving them at reset.  
For more details on these device configuration pins, see the Terminal Functions table of this data sheet.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
Table 15. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0)  
CONFIGURATION  
PIN  
GDP/ZDP  
FUNCTIONAL DESCRIPTION  
EMIF Big Endian mode correctness (EMIFBE)  
0
1
The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of  
the endianess mode (Little/Big Endian).  
In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be present on the  
ED[7:0] side of the bus.  
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present on the  
ED[31:24] side of the bus [default].  
HD12  
C15  
EMIF Big Endian mode correctness is not supported on the C6711/11B/11C device.  
This new functionality does not affect systems using the current default value of HD12=1. For  
more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode  
Correctness portion of this data sheet.  
Device Endian mode (LEND)  
HD8  
B17  
0
1
System operates in Big Endian mode  
System operates in Little Endian mode (default)  
Bootmode Configuration Pins (BOOTMODE)  
00 – HPI boot/Emulation boot  
01 – CE1 width 8-bit, Asynchronous external ROM boot with default  
timings (default mode)  
HD[4:3]  
(BOOTMODE)  
10 − CE1 width 16-bit, Asynchronous external ROM boot with default  
C19, C20  
timings  
11 − CE1 width 32-bit, Asynchronous external ROM boot with default  
timings  
For more detailed information on these bootmode configurations, see the bootmode section of  
this data sheet.  
Clock generator input clock source select  
0
1
Reserved. Do not use.  
CLKIN square wave [default]  
CLKMODE0  
C4  
For proper device operation, this pin must be either left unconnected or externally pulled up  
with a 1-kresistor.  
All other HD pins or HD [15:13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs or IPDs). For proper device operation of the HD [14, 13, 11:9, 7,  
1, 0], do not oppose these pins with external pullups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during  
reset.  
To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-kΩ  
pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
DEVICE CONFIGURATIONS (CONTINUED)  
DEVCFG register description  
The device configuration register (DEVCFG) allows the user control of the EMIF input clock source for the  
device. For more detailed information on the DEVCFG register control bits, see Table 16 and Table 17.  
Table 16. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF]  
31  
15  
16  
Reserved  
RW-0  
4
5
3
0
Reserved  
EKSRC  
R/W-0  
Reserved  
RW-0  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Do not write non-zero values to these bit locations.  
Table 17. Device Configuration (DEVCFG) Register Selection Bit Descriptions  
BIT #  
NAME  
DESCRIPTION  
31:5  
Reserved  
Reserved. Do not write non-zero values to these bit locations.  
EMIF input clock source bit.  
Determines which clock signal is used as the EMIF input clock.  
4
EKSRC  
0
1
=
=
SYSCLK3 (from the clock generator) is the EMIF input clock source (default)  
ECLKIN external pin is the EMIF input clock source  
3:0  
Reserved  
Reserved. Do not write non-zero values to these bit locations.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
TERMINAL FUNCTIONS  
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with  
the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal  
pullup/pulldown resistors and a functional pin description. For more detailed information on device  
configuration, see the Device Configurations section of this data sheet.  
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Terminal Functions  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
CLOCK/PLL  
CLKIN  
A3  
I
IPD  
IPD  
Clock Input  
For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin.  
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock  
generator) or this pin can be programmed as GP[2] (I/O/Z).  
CLKOUT2  
(/GP0[2])  
Y12  
O/Z  
When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register  
(GBLCTL) controls the CLKOUT2 pin (All devices).  
CLK2EN = 0:  
CLK2EN = 1:  
CLKOUT2 is disabled  
CLKOUT2 enabled to clock [default]  
CLKOUT3  
CLKMODE0  
PLLHV  
D10  
C4  
O
I
IPD  
IPU  
Clock output programmable by OSCDIV1 register in the PLL controller.  
Clock generator input clock source select  
0
1
Reserved. Do not use.  
CLKIN square wave [default]  
For proper device operation, this pin must be either left unconnected or externally pulled up with  
a 1-kresistor.  
C5  
A
Analog power (3.3 V) for PLL  
JTAG EMULATION  
TMS  
TDO  
TDI  
B7  
A8  
A7  
A6  
I
IPU  
IPU  
IPU  
IPU  
JTAG test-port mode select  
JTAG test-port data out  
JTAG test-port data in  
JTAG test-port clock  
O/Z  
I
I
TCK  
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1  
JTAG Compatibility Statement section of this data sheet.  
§
TRST  
B6  
I
IPD  
EMU5  
EMU4  
EMU3  
B12  
C11  
B10  
I/O/Z  
I/O/Z  
I/O/Z  
IPU  
IPU  
IPU  
Emulation pin 5. Reserved for future use, leave unconnected.  
Emulation pin 4. Reserved for future use, leave unconnected.  
Emulation pin 3. Reserved for future use, leave unconnected.  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-kΩ  
pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.  
§
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
JTAG EMULATION (CONTINUED)  
EMU2  
D3  
I/O/Z  
IPU  
Emulation pin 2. Reserved for future use, leave unconnected.  
For Emulation and normal operation, no external pullup/pulldown resistors are necessary. How-  
ever for the Boundary Scan operation, pull down the EMU1 and EMU0 pins with a dedicated  
1-kresistor.  
Emulation [1:0] pins.  
Select the device functional mode of operation  
EMU[1:0]  
Operation  
00  
01  
10  
11  
Boundary Scan/Functional Mode (see Note)  
Reserved  
Reserved  
Emulation/Functional Mode [default] (see the IEEE 1149.1  
JTAG Compatibility Statement section of this data sheet)  
EMU1  
EMU0  
B9  
D9  
I/O/Z  
IPU  
The DSP can be placed in Functional mode when the EMU[1:0] pins are  
configured for either Boundary Scan or Emulation.  
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the  
internal pulldown (IPD) on the TRST signal must not be opposed in order to  
operate in Functional mode.  
For the Boundary Scan mode drive EMU[1:0] and RESET pins low.  
RESETS AND INTERRUPTS  
Device reset. When using Boundary Scan mode on the device, drive the EMU[1:0] and RESET  
RESET  
NMI  
A13  
C13  
I
I
−−  
pins low.  
This pin does not have an IPU on this device.  
Nonmaskable interrupt  
Edge-driven (rising edge)  
IPD  
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is  
recommended that the NMI pin be grounded versus relying on the IPD.  
EXT_INT7  
EXT_INT6  
EXT_INT5  
EXT_INT4  
E3  
D2  
C1  
C2  
General-purpose input/output pins (I/O/Z) which also function as external  
interrupts  
Edge-driven  
I
IPU  
Polarity independently selected via the External Interrupt Polarity Register  
bits (EXTPOL.[3:0]), in addition to the GPIO registers.  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
HOST-PORT INTERFACE (HPI)  
HINT  
J20  
G19  
G18  
H20  
G20  
O
I
IPU  
IPU  
IPU  
IPU  
IPU  
Host interrupt (from DSP to host)  
HCNTL1  
HCNTL0  
HHWIL  
HR/W  
Host control − selects between control, address, or data registers  
Host control − selects between control, address, or data registers  
Host half-word select − first or second half-word (not necessarily high or low order)  
I
I
I
Host read or write select  
Host-port data  
HD15  
B14  
C14  
A15  
C15  
A16  
B16  
C16  
B17  
A18  
C17  
B18  
C19  
C20  
D18  
D20  
E20  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPD  
IPU  
IPU  
IPU  
IPU  
Used for transfer of data, address, and control  
Also controls initialization of DSP modes at reset via pullup/pulldown resistors  
− Device Endian mode (HD8)  
§
§
§
HD14  
HD13  
HD12  
HD11  
HD10  
HD9  
0
1
Big Endian  
Little Endian  
EMIF Big Endian mode correctness (EMIFBE) (HD12)  
0
The EMIF data will always be presented on the ED[7:0] side of the bus,  
regardless of the endianess mode (Little/Big Endian).  
In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be  
present on the ED[7:0] side of the bus.  
1
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present  
on the ED[31:24] side of the bus [default].  
§
HD8  
HD7  
HD6  
HD5  
HD4  
HD3  
HD2  
HD1  
HD0  
This new functionality does not affect systems using the curent default value of HD12=1. For  
more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode  
Correctness portion of this data sheet.  
I/O/Z  
− Bootmode (HD[4:3])  
00 –  
01 −  
HPI boot/Emulation boot  
CE1 width 8-bit, Asynchronous external ROM boot with default timings  
(default mode)  
§
§
10 −  
11 −  
CE1 width 16-bit, Asynchronous external ROM boot with default timings  
CE1 width 32-bit, Asynchronous external ROM boot with default timings  
Other HD pins (HD [15:13, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs/IPDs). For proper de-  
vice operation of the HD[14, 13, 11:9, 7, 1, 0], do not oppose these pins with external IPUs/IPDs  
at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.  
For more details, see the Device Configurations section of this data sheet.  
HAS  
HCS  
E18  
F20  
I
I
IPU  
IPU  
Host address strobe  
Host chip select  
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY  
HDS1  
HDS2  
E19  
F18  
I
I
IPU  
IPU  
Host data strobe 1  
Host data strobe 2  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-kΩ  
pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.  
§
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY (CONTINUED)  
HRDY  
H19  
V6  
O
IPD  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
IPU  
Host ready (from DSP to host)  
CE3  
CE2  
CE1  
CE0  
BE3  
BE2  
BE1  
BE0  
O/Z  
O/Z  
O/Z  
O/Z  
O/Z  
O/Z  
O/Z  
O/Z  
Memory space enables  
W6  
W18  
V17  
V5  
Enabled by bits 28 through 31 of the word address  
Only one asserted during any external data access  
Byte-enable control  
Y4  
Decoded from the two lowest bits of the internal address  
Byte-write enables for most types of memory  
Can be directly connected to SDRAM read and write mask signal (SDQM)  
U19  
V20  
EMIF − BUS ARBITRATION  
HOLDA  
HOLD  
J18  
J17  
J19  
O
I
IPU  
IPU  
IPU  
Hold-request-acknowledge to the host  
Hold request from the host  
Bus request output  
BUSREQ  
O
EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL  
ECLKIN  
Y11  
I
IPD  
External EMIF input clock source  
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5])  
EKSRC = 0  
ECLKOUT is based on the internal SYSCLK3 signal  
from the clock generator (default).  
EKSRC = 1  
ECLKOUT is based on the the external EMIF input clock  
source pin (ECLKIN)  
ECLKOUT  
Y10  
O/Z  
IPD  
EKEN = 0  
EKEN = 1  
ECLKOUT held low  
ECLKOUT enabled to clock (default)  
ARE/SDCAS/  
SSADS  
V11  
O/Z  
O/Z  
IPU  
IPU  
Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe  
Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable  
AOE/SDRAS/  
SSOE  
W10  
AWE/SDWE/  
SSWE  
V12  
Y5  
O/Z  
I
IPU  
IPU  
Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable  
Asynchronous memory ready input  
ARDY  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
EMIF − ADDRESS  
EA21  
U18  
Y18  
W17  
Y16  
V16  
Y15  
W15  
Y14  
W14  
V14  
W13  
V10  
Y9  
EA20  
EA19  
EA18  
EA17  
EA16  
EA15  
EA14  
EA13  
EA12  
EA11  
EA10  
EA9  
O/Z  
IPU  
EMIF external address  
EA8  
V9  
EA7  
Y8  
EA6  
W8  
V8  
EA5  
EA4  
W7  
V7  
EA3  
EA2  
Y6  
EMIF − DATA  
ED31  
ED30  
ED29  
ED28  
ED27  
ED26  
ED25  
ED24  
ED23  
ED22  
ED21  
ED20  
ED19  
N3  
P3  
P2  
P1  
R2  
R3  
T2  
T1  
U3  
U1  
U2  
V1  
V2  
I/O/Z  
IPU  
External data  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
EMIF − DATA (CONTINUED)  
ED18  
Y3  
W4  
ED17  
ED16  
ED15  
ED14  
ED13  
ED12  
ED11  
ED10  
ED9  
V4  
T19  
T20  
T18  
R20  
R19  
P20  
P18  
N20  
N19  
N18  
M20  
M19  
L19  
L18  
K19  
K18  
I/O/Z  
IPU  
External data  
ED8  
ED7  
ED6  
ED5  
ED4  
ED3  
ED2  
ED1  
ED0  
TIMER 1  
TOUT1  
TINP1  
F1  
F2  
O
I
IPD  
IPD  
Timer 1 or general-purpose output  
Timer 1 or general-purpose input  
TIMER 0  
TOUT0  
TINP0  
G1  
G2  
O
I
IPD  
IPD  
Timer 0 or general-purpose output  
Timer 0 or general-purpose input  
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)  
External clock source (as opposed to internal)  
On the device, this pin does not have an internal pulldown (IPD). For proper device opera-  
tion, the CLKS1 pin should either be driven externally at all times or be pulled up with a 10-kΩ  
resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at  
CLKS1  
E1  
I
IPD  
times, a 10-kpullup resistor may be desirable even when an external device is driving the  
pin.  
CLKR1  
CLKX1  
M1  
L3  
I/O/Z  
I/O/Z  
IPD  
IPD  
Receive clock  
Transmit clock  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) (CONTINUED)  
Receive data  
On this device, this pin does not have an internal pullup (IPU). For proper device operation,  
the DR1 pin should either be driven externally at all times or be pulled up with a 10-kresis-  
tor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a  
10-kpullup resistor may be desirable even when an external device is driving the pin.  
DR1  
DX1  
M2  
I
IPU  
L2  
M3  
L1  
O/Z  
I/O/Z  
I/O/Z  
IPU  
IPD  
IPD  
Transmit data  
FSR1  
FSX1  
Receive frame sync  
Transmit frame sync  
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)  
CLKS0  
CLKR0  
CLKX0  
DR0  
K3  
H3  
G3  
J1  
I
IPD  
IPD  
IPD  
IPU  
IPU  
IPD  
IPD  
External clock source (as opposed to internal)  
Receive clock  
I/O/Z  
I/O/Z  
I
Transmit clock  
Receive data  
DX0  
H2  
J3  
O/Z  
I/O/Z  
I/O/Z  
Transmit data  
FSR0  
FSX0  
Receive frame sync  
Transmit frame sync  
H1  
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) MODULE  
For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin.  
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal  
from the clock generator) or this pin can be programmed as GP[2] (I/O/Z).  
CLKOUT2/  
GP[2]  
Y12  
I/O/Z  
IPD  
When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control  
register (GBLCTL) controls the CLKOUT2 pin (All devices).  
CLK2EN = 0:  
CLK2EN = 1:  
CLKOUT2 is disabled  
CLKOUT2 enabled to clock [default]  
GP[7](EXT_INT7)  
GP[6](EXT_INT6)  
GP[5](EXT_INT5)  
GP[4](EXT_INT4)  
E3  
D2  
C1  
C2  
General-purpose input/output pins (I/O/Z) which also function as external  
interrupts  
Edge-driven  
I/O/Z  
IPU  
Polarity independently selected via the External Interrupt Polarity Register  
bits (EXTPOL.[3:0]), in addition to the GPIO registers.  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
IPD/  
IPU  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
RESERVED FOR TEST  
Reserved (leave unconnected, do not connect to power or ground).  
On this device, this pin does not have an IPU.  
RSV  
C12  
IPU  
On this device, this pin does not have an IPU. For proper device operation, the D12 pin must  
be externally pulled down with a 10-kresistor.  
RSV  
RSV  
RSV  
D12  
A5  
IPU  
IPU  
Reserved (leave unconnected, do not connect to power or ground)  
Reserved. For proper device operation, this pin must be externally pulled up with a 10-kΩ  
resistor.  
N2  
Reserved. For proper device operation, this pin must be externally pulled up with a 10-kΩ  
resistor.  
RSV  
N1  
RSV  
RSV  
B5  
D7  
Reserved (leave unconnected, do not connect to power or ground)  
IPD  
Reserved (leave unconnected, do not connect to power or ground)  
Reserved. [For new designs, it is recommended that this pin be connected directly to CV  
(core power). For old designs, this can be left unconnected.  
DD  
RSV  
RSV  
A12  
B11  
Reserved [For new designs, it is recommended that this pin be connected directly to V  
(ground). For old designs, this pin can be left unconnected.  
ss  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors  
no greater than 4.4 kand 2.0 k, respectively.]  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
SUPPLY VOLTAGE PINS  
A17  
B3  
B8  
B13  
C10  
D1  
D16  
D19  
F3  
H18  
J2  
M18  
R1  
3.3-V supply voltage  
(see the power-supply decoupling portion of this data sheet)  
R18  
T3  
DV  
S
DD  
U5  
U7  
U12  
U16  
V13  
V15  
V19  
W3  
W9  
W12  
Y7  
Y17  
A4  
A9  
A10  
B2  
B19  
C3  
1.4-V supply voltage (-250)  
1.20-V supply voltage [See Note]  
CV  
S
DD  
(see the power-supply decoupling portion of this data sheet)  
C7  
C18  
D5  
Note: This value is compatible with existing 1.26−V designs.  
D6  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
SUPPLY VOLTAGE PINS (CONTINUED)  
D11  
D14  
D15  
F4  
F17  
K1  
K4  
K17  
L4  
1.4-V supply voltage (-250)  
1.20-V supply voltage [See Note]  
(see the power-supply decoupling portion of this data sheet)  
L17  
L20  
R4  
CV  
S
DD  
R17  
U6  
U10  
U11  
U14  
U15  
V3  
V18  
W2  
W19  
Note: This value is compatible with existing 1.26−V designs.  
GROUND PINS  
A1  
A2  
A11  
A14  
A19  
A20  
B1  
B4  
V
SS  
GND  
Ground pins  
B15  
B20  
C6  
C8  
C9  
D4  
D8  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
GROUND PINS (CONTINUED)  
D13  
D17  
E2  
E4  
E17  
F19  
G4  
G17  
H4  
H17  
J4  
J9  
J10  
J11  
J12  
K2  
K9  
K10  
K11  
K12  
K20  
L9  
#
Ground pins  
The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as  
both electrical grounds and thermal relief (thermal dissipation).  
V
SS  
GND  
L10  
L11  
L12  
M4  
M9  
M10  
M11  
M12  
M17  
N4  
N17  
P4  
P17  
P19  
T4  
T17  
#
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
Shaded pin numbers denote the center thermal balls for the GDP package.  
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Terminal Functions (Continued)  
PIN  
NO.  
SIGNAL  
NAME  
TYPE  
DESCRIPTION  
GDP/  
ZDP  
GROUND PINS (CONTINUED)  
U4  
U8  
U9  
U13  
U17  
U20  
W1  
W5  
V
SS  
GND  
Ground pins  
W11  
W16  
W20  
Y1  
Y2  
Y13  
Y19  
Y20  
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)  
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development support  
TI offers an extensive line of development tools for the TMS320C6000DSP platform, including tools to  
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully  
integrate and debug software and hardware modules.  
The following products support development of C6000DSP-based applications:  
Software Development Tools:  
Code Composer StudioIntegrated Development Environment (IDE): including Editor  
C/C++/Assembly Code Generation, and Debug plus additional development tools  
Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software  
needed to support any DSP application.  
Hardware Development Tools:  
Extended Development System (XDS) Emulator (supports C6000DSP multiprocessor system debug)  
EVM (Evaluation Module)  
For a complete listing of development-support tools for the TMS320C6000DSP platform, visit the Texas  
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For  
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.  
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.  
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device support  
device and development-support tool nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP  
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS.  
(e.g., TMS320C6711DGDP250). Texas Instruments recommends two of three possible prefix designators for  
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from  
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).  
Device development evolutionary flow:  
TMX  
TMP  
TMS  
Experimental device that is not necessarily representative of the final device’s electrical  
specifications.  
Final silicon die that conforms to the device’s electrical specifications but has not completed  
quality and reliability verification.  
Fully qualified production device.  
Support tool development evolutionary flow:  
TMDX  
Development-support product that has not yet completed Texas Instruments internal qualification  
testing.  
TMDS  
Fully qualified development-support product.  
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:  
“Developmental product is intended for internal evaluation purposes.”  
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability  
of the device have been demonstrated fully. TI’s standard warranty applies.  
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system because their  
expected end-use failure rate still is undefined. Only qualified production devices are to be used.  
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type  
(for example, GDP), the temperature range (for example, blank is the default commercial temperature range  
and A is the extended temperature range), and the device speed range in megahertz (for example, -167 is  
167 MHz).  
The ZDP package, like the GDP package, is a 272-ball plastic BGA only with Pb-free balls. For device part  
numbers and further ordering information for TMS320C6711D in the GDP and ZDP package types, see the TI  
website (http://www.ti.com) or contact your TI sales representative.  
TMS320 is a trademark of Texas Instruments.  
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device and development-support tool nomenclature (continued)  
(
)
TMS 320  
C 6711D GDP  
250  
PREFIX  
TMX= Experimental device  
TMP= Prototype device  
DEVICE SPEED RANGE  
TMS= Qualified device  
167 MHz  
200 MHz  
250 MHz  
SMJ = MIL-PRF-38535, QML  
SM = High Rel (non-38535)  
DEVICE FAMILY  
32 or 320 = TMS320DSP family  
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)  
Blank = 0°C to 90°C, commercial temperature  
A
=
−40°C to 105°C, extended temperature  
TECHNOLOGY  
C = CMOS  
†‡§  
PACKAGE TYPE  
GDP = 272-pin plastic BGA  
ZDP = 272-pin plastic BGA, with Pb-free soldered balls  
DEVICE  
C6711D  
BGA  
=
Ball Grid Array  
The ZDP mechanical package designator represents the version of the GDP with Pb−Free soldered balls. The ZDP package devices  
are supported in the same speed grades as the GDP package devices (available upon request).  
For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this document or the  
TI website (www.ti.com).  
§
Figure 5. TMS320C6711D DSP Device Nomenclature  
MicroStar BGA and PowerPAD are trademarks of Texas Instruments.  
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documentation support  
Extensive documentation supports all TMS320DSP family generations of devices from product  
announcement through applications development. The types of documentation available include: data sheets,  
such as this document, with design specifications; complete user’s reference guides for all devices and tools;  
technical briefs; development-support tools; on-line help; and hardware and software applications. The  
following is a brief, descriptive list of support documentation specific to the C6000DSP devices:  
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the  
C6000CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.  
The TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG  
peripherals available on the C6000DSP platform of devices. This document also includes a table listing the  
peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated  
peripheral documents. These C6711D peripherals, except the PLL, are similar to the peripherals on the  
TMS320C6711 and TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral  
information, and in some cases, where indicated, see the TMS320C6711 (C6711 or TMS320C67xor C67x)  
peripheral information, and in some cases, where indicated, see the C64x information in the C6000 PRG  
TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide  
C6711D devices.  
TMS320C62x/TMS320C67xdevices, associated development tools, and third-party support.  
TheMigrating from TMS320C6211B/6711B to TMS320C6711C application report (literature number SPRA837)  
describes the differences and issues of interest related to migration from the Texas Instruments TMS320C6211,  
TMS320C6211B, TMS320C6711, and TMS320C6711B devices, GFN packages, to the TMS320C6711C  
device, GDP package.  
The TMS320C6711/TMS320C6711B/TMS320C6711C/TMS320C6711D Digital Signal Processors Silicon  
Errata (C6711 Silicon Revisions 1.0, 1.2, and 1.3; C6711B Silicon Revisions 2.0 and 2.1; and C6711C Silicon  
Revision 1.1; and C6711D Silicon Revision 2.0) [literature number SPRZ173K or later] categorizes and  
describes the known exceptions to the functional specifications and usage notes for the TMS320C6711,  
TMS320C6711B, TMS320C6711C, and TMS320C6711D DSP devices.  
The TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number  
TMS320C6712D, and TMS320C6711D DSP devices.  
properly use IBIS models to attain accurate timing analysis for a given system.  
The tools support documentation is electronically available within the Code Composer StudioIntegrated  
Development Environment (IDE). For a complete listing of C6000DSP latest documentation, visit the Texas  
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).  
See the Worldwide Web URL for the application reports How To Begin Development Today with the  
TMS320C6211 DSP (literature number SPRA474) and How To Begin Development with the TMS320C6711  
and C6711 C6000DSP devices.  
TMS320C62x is a trademark of Texas Instruments.  
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CPU CSR register description  
The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the  
status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the  
endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 6 and  
Table 18 identify the bit fields in the CPU CSR register.  
For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals  
Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set  
Reference Guide (literature number SPRU189).  
31  
24 23  
16  
CPU ID  
R-0x02  
REVISION ID  
R-0x03  
15  
10  
9
8
7
6
5 4  
2
1
0
PWRD  
R/W-0  
SAT  
R/C-0  
EN  
PCC  
R/W-0  
DCC  
PGIE  
GIE  
R-1  
R/W-0  
R/W-0 R/W-0  
Legend: R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after  
reset, C = Clearable by the MVC instruction  
Figure 6. CPU Control Status Register (CPU CSR)  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
CPU CSR register description (continued)  
Table 18. CPU CSR Register Bit Field Description  
BIT #  
NAME  
DESCRIPTION  
CPU ID + REV ID. Read only.  
Identifies which CPU is used and defines the silicon revision of the CPU.  
31:24  
CPU ID  
23:16  
15:10  
REVISION ID  
PWRD  
CPU ID + REVISION ID (31:16) are combined for a value of 0x0203  
Control power-down modes. The values are always read as zero.  
000000  
001001  
010001  
011010  
011100  
Others  
=
=
=
=
=
=
no power-down (default)  
PD1, wake-up by an enabled interrupt  
PD1, wake-up by an enabled or not enabled interrupt  
PD2, wake-up by a device reset  
PD3, wake-up by a device reset  
Reserved  
Saturate bit.  
Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can  
be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC  
instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after  
a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.  
9
SAT  
Endian bit. This bit is read-only.  
Depicts the device endian mode.  
8
EN  
0
1
=
=
Big Endian mode.  
Little Endian mode [default].  
Program Cache control mode.  
L1D, Level 1 Program Cache  
7:5  
4:2  
PCC  
DCC  
000/010  
=
Cache Enabled / Cache accessed and updated on reads.  
All other PCC values reserved.  
Data Cache control mode.  
L1D, Level 1 Data Cache  
000/010  
=
Cache Enabled / 2-Way Cache  
All other DCC values reserved  
Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is  
taken. Allows for proper nesting of interrupts.  
1
0
PGIE  
GIE  
0
1
=
=
Previous GIE value is 0. (default)  
Previous GIE value is 1.  
Global interrupt enable bit.  
Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).  
0
1
=
=
Disables all interrupts (except the reset interrupt and NMI) [default]  
Enables all interrupts (except the reset interrupt and NMI)  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
cache configuration (CCFG) register description  
The device includes an enhancement to the cache configuration (CCFG) register. A “P” bit (CCFG.31) allows  
the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC) over  
accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers,  
which move data to or from the L2 memory. While the EDMA normally has no issue accessing L2 memory due  
to the high hit rates on the L1D memory system, there are pathological cases where certain CPU behavior could  
block the EDMA from accessing the L2 memory for long enough to cause a missed deadline when transferring  
data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit to “1” because the  
EDMA will assume a higher priority than the L1D memory system when accessing L2 memory.  
For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory  
accesses blocked, see the TMS320C6711/TMS320C6711B/TMS320C6711C/TMS320C6711D Digital Signal  
Processors Silicon Errata (literature number SPRZ173K or later).  
7
31  
30  
10  
9
8
3
2
0
P
Reserved  
R-x  
IP  
ID  
Reserved  
R-0 0000  
L2MODE  
R/W-000  
R/W-0  
W-0  
W-0  
Legend: R = Readable; R/W = Readable/Writeable; -n = value after reset; -x = undefined value after reset  
Figure 7. Cache Configuration Register (CCFG)  
Table 19. CCFG Register Bit Field Description  
BIT #  
31  
NAME  
DESCRIPTION  
L1D requestor priority to L2 bit.  
P
Reserved  
IP  
P
P
=
=
0: L1D requests to L2 higher priority than TC requests  
1: TC requests to L2 higher priority than L1D requests  
30:10  
9
Reserved. Read-only, writes have no effect.  
Invalidate L1P bit.  
0
1
=
=
Normal L1P operation  
All L1P lines are invalidated  
Invalidate L1D bit.  
8
ID  
0
1
=
=
Normal L1D operation  
All L1D lines are invalidated  
7:3  
Reserved  
Reserved. Read-only, writes have no effect.  
L2 operation mode bits (L2MODE).  
000b = L2 Cache disabled (All SRAM mode) [64K SRAM]  
001b = 1-way Cache (16K L2 Cache) / [48K SRAM]  
010b = 2-way Cache (32K L2 Cache) / [32K SRAM]  
2:0  
L2MODE  
011b  
111b  
=
=
3-way Cache (48K L2 Cache) / [16K SRAM]  
4-way Cache (64K L2 Cache) / [no SRAM]  
All others Reserved  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
interrupt sources and interrupt selector  
The C67x DSP core on the device supports 16 prioritized interrupts, which are listed in Table 20. The highest  
priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are  
non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed  
in Table 20. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 21  
(Interrupt Selector). Table 21 lists the selector value corresponding to each of the alternate interrupt sources.  
The selector choice for interrupts 4−15 is made by programming the corresponding fields (listed in Table 20)  
in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers.  
Table 20. DSP Interrupts  
Table 21. Interrupt Selector  
INTERRUPT  
SELECTOR  
CONTROL  
REGISTER  
DEFAULT  
SELECTOR  
VALUE  
INTERRUPT  
SELECTOR  
VALUE  
DSP  
INTERRUPT  
NUMBER  
DEFAULT  
INTERRUPT  
EVENT  
INTERRUPT  
EVENT  
MODULE  
(BINARY)  
(BINARY)  
INT_00  
INT_01  
INT_02  
INT_03  
INT_04  
INT_05  
INT_06  
INT_07  
INT_08  
INT_09  
INT_10  
INT_11  
INT_12  
INT_13  
INT_14  
INT_15  
RESET  
NMI  
00000  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
10000  
DSPINT  
TINT0  
TINT1  
SDINT  
HPI  
Timer 0  
Timer 1  
EMIF  
Reserved  
Reserved  
MUXL[4:0]  
MUXL[9:5]  
MUXL[14:10]  
MUXL[20:16]  
MUXL[25:21]  
MUXL[30:26]  
MUXH[4:0]  
MUXH[9:5]  
MUXH[14:10]  
MUXH[20:16]  
MUXH[25:21]  
MUXH[30:26]  
00100  
00101  
00110  
00111  
01000  
01001  
00011  
01010  
01011  
00000  
00001  
00010  
GPINT4  
GPINT5  
GPINT6  
GPINT7  
GPINT4  
GPINT5  
GPINT6  
GPINT7  
GPIO  
GPIO  
GPIO  
GPIO  
EDMAINT  
EMUDTDMA  
SDINT  
EDMAINT  
EMUDTDMA  
EMURTDXRX  
EMURTDXTX  
XINT0  
EDMA  
Emulation  
Emulation  
Emulation  
McBSP0  
McBSP0  
McBSP1  
McBSP1  
GPIO  
EMURTDXRX  
EMURTDXTX  
DSPINT  
RINT0  
TINT0  
XINT1  
TINT1  
RINT1  
GPINT0  
Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins  
GP[4](EXT_INT4), GP[5](EXT_INT5), GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx  
with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO  
module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction  
Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more  
information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide  
(literature number SPRU584).  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
EDMA module and EDMA selector  
The C67x EDMA for the device also supports up to 16 EDMA channels. Four of the sixteen channels (channels  
8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. On  
the device, the user, through the EDMA selector registers, can control the EDMA channels servicing peripheral  
devices.  
The EDMA selector registers are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and  
0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA  
channels. Each EDMA event has an assigned EDMA selector code (see Table 23). By loading each EVTSELx  
register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA  
channel. Table 22 lists the default EDMA selector value for each EDMA channel.  
See Table 24 and Table 25 for the EDMA Event Selector registers and their associated bit descriptions.  
Table 22. EDMA Channels  
Table 23. EDMA Selector  
EDMA  
DEFAULT  
SELECTOR  
VALUE  
DEFAULT  
EDMA  
EVENT  
EDMA  
SELECTOR  
CODE (BINARY)  
EDMA  
CHANNEL  
EDMA  
EVENT  
SELECTOR  
CONTROL  
REGISTER  
MODULE  
(BINARY)  
0
1
ESEL0[5:0]  
ESEL0[13:8]  
ESEL0[21:16]  
ESEL0[29:24]  
ESEL1[5:0]  
ESEL1[13:8]  
ESEL1[21:16]  
ESEL1[29:24]  
000000  
000001  
000010  
000011  
000100  
000101  
000110  
000111  
DSPINT  
TINT0  
TINT1  
SDINT  
000000  
000001  
000010  
000011  
DSPINT  
TINT0  
TINT1  
SDINT  
HPI  
TIMER0  
TIMER1  
EMIF  
2
3
4
GPINT4  
GPINT5  
GPINT6  
GPINT7  
000100  
000101  
000110  
GPINT4  
GPINT5  
GPINT6  
GPINT7  
GPIO  
5
GPIO  
6
GPIO  
7
000111  
GPIO  
8
TCC8 (Chaining)  
TCC9 (Chaining)  
TCC10 (Chaining)  
TCC11 (Chaining)  
XEVT0  
001000  
001001  
001010  
001011  
Reserved  
9
Reserved  
Reserved  
10  
11  
12  
13  
14  
15  
GPINT2  
GPIO  
ESEL3[5:0]  
ESEL3[13:8]  
ESEL3[21:16]  
ESEL3[29:24]  
001100  
001101  
001110  
001111  
001100  
XEVT0  
REVT0  
XEVT1  
REVT1  
McBSP0  
McBSP0  
McBSP1  
McBSP1  
REVT0  
001101  
XEVT1  
001110  
REVT1  
001111  
010000−111111  
Reserved  
The GPINT[4−7] interrupt events are sourced from the GPIO module via the external interrupt capable GP[4−7] pins.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
EDMA module and EDMA selector (continued)  
Table 24. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3)  
ESEL0 Register (0x01A0 FF00)  
30  
31  
29  
28 27  
24 23  
22 21  
20 19  
16  
0
Reserved  
R−0  
EVTSEL3  
R/W−00 0011b  
Reserved  
R−0  
EVTSEL2  
R/W−00 0010b  
3
14  
15  
13  
12 11  
8
7
6
5
4
Reserved  
R−0  
EVTSEL1  
Reserved  
R−0  
EVTSEL0  
R/W−00 0000b  
R/W−00 0001b  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
ESEL1 Register (0x01A0 FF04)  
30  
31  
29  
13  
28 27  
24 23  
22 21  
20 19  
16  
0
Reserved  
R−0  
EVTSEL7  
R/W−00 0111b  
Reserved  
R−0  
EVTSEL6  
R/W−00 0110b  
3
14  
15  
12 11  
8
7
6
5
4
Reserved  
R−0  
EVTSEL5  
Reserved  
R−0  
EVTSEL4  
R/W−00 0100b  
R/W−00 0101b  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
ESEL3 Register (0x01A0 FF0C)  
30  
31  
29  
13  
28 27  
24 23  
22 21  
20 19  
16  
0
Reserved  
R−0  
EVTSEL15  
R/W−00 1111b  
Reserved  
R−0  
EVTSEL14  
R/W−00 1110b  
3
14  
15  
12 11  
8
7
6
5
4
Reserved  
R−0  
EVTSEL13  
Reserved  
R−0  
EVTSEL12  
R/W−00 1100b  
R/W−00 1101b  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
Table 25. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description  
BIT #  
NAME  
DESCRIPTION  
31:30  
23:22  
15:14  
7:6  
Reserved  
Reserved. Read-only, writes have no effect.  
EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels.  
The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These  
EVTSELx fields are user−selectable. By configuring the EVTSELx fields to the EDMA selector value  
of the desired EDMA sync event number (see Table 23), users can map any EDMA event to the  
EDMA channel.  
29:24  
21:16  
13:8  
5:0  
EVTSELx  
For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then  
channel 15 is triggered by Timer0 TINT0 events.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PLL and PLL controller  
The device includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and four  
dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts  
of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other peripherals).  
Figure 8 illustrates the PLL, the PLL controller, and the clock generator logic.  
PLLHV  
+3.3 V  
EMI filter  
C1  
C2  
10 µF 0.1 µF  
CLKMODE0  
CLKIN  
PLLOUT  
PLLREF  
DIVIDER D0  
/1, /2,  
..., /32  
PLLEN (PLL_CSR.[0])  
1
0
PLL  
x4 to x25  
DIVIDER D1  
1
0
ENA  
Reserved  
CLKOUT3  
/1, /2,  
SYSCLK1  
(DSP Core)  
..., /32  
ENA  
D1EN (PLLDIV1.[15])  
D0EN (PLLDIV0.[15])  
DIVIDER D2  
/1, /2,  
SYSCLK2  
(Peripherals)  
..., /32  
OSCDIV1  
D2EN (PLLDIV2.[15])  
ENA  
/1, /2,  
..., /32  
For Use  
in System  
DIVIDER D3  
ENA  
/1, /2,  
..., /32  
OD1EN (OSCDIV1.[15])  
SYSCLK3  
ENA  
D3EN (PLLDIV3.[15])  
ECLKIN  
(EMIF Clock Input)  
EKSRC Bit  
1
0
(DEVCFG.[4])  
EMIF  
C6711D DSP  
ECLKOUT  
Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.  
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67xDSP device as possible. For the best  
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or  
components other than the ones shown.  
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI  
Filter).  
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV  
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.  
.
DD  
Figure 8. PLL and Clock Generator Logic  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PLL and PLL controller (continued)  
The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order  
for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time  
value, see Table 26. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL  
out of reset, but still bypassed) to when the PLLEN bit can be safely changed to “1” (switching from bypass to  
the PLL path), see Table 26 and Figure 8.  
Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For  
the PLL Lock Time values, see Table 26.  
Table 26. PLL Lock and Reset Times  
MIN  
TYP  
MAX  
UNIT  
µs  
PLL Lock Time  
PLL Reset Time  
75  
187.5  
125  
ns  
Table 27 shows the device’s CLKOUT signals, how they are derived and by what register control bits, and the  
default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram (Figure 8).  
Table 27. CLKOUT Signals, Default Settings, and Control  
CLOCK OUTPUT  
SIGNAL NAME  
DEFAULT SETTING  
(ENABLED or DISABLED)  
CONTROL  
BIT(s) (Register)  
DESCRIPTION  
D2EN = 1 (PLLDIV2.[15])  
CK2EN = 1 (EMIF GBLCTL.[3])  
CLKOUT2  
CLKOUT3  
ON (ENABLED)  
ON (ENABLED)  
SYSCLK2 selected [default]  
OD1EN = 1 (OSCDIV1.[15])  
Derived from CLKIN  
SYSCLK3 selected [default].  
ON (ENABLED);  
derived from SYSCLK3  
EKSRC = 0 (DEVCFG.[4])  
EKEN = 1 (EMIF GBLCTL.[5])  
To select ECLKIN as source:  
EKSRC = 1 (DEVCFG.[4]) and  
EKEN = 1 (EMIF GBLCTL.[5])  
ECLKOUT  
This input clock is directly available as an internal high-frequency clock source that may be divided down by  
a programmable divider OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.  
Figure 8 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then  
multiplied up by a factor of x4, x5, x6, and so on, up to x25.  
Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference  
clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may  
be divided down from this high-frequency clock (each with a unique divider) . For example, with a 40-MHz input,  
if the PLL output is configured for 400 MHz, the DSP core may be operated at 200 MHz (/2) while the EMIF may  
be configured to operate at a rate of 75 MHz (/6). Note that there is a specific minimum and maximum reference  
clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 8, as well as for the DSP core,  
peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints  
(certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported).  
See Table 28 for the PLL clocks input and output frequency ranges.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PLL and PLL controller (continued)  
†‡  
Table 28. PLL Clock Frequency Ranges  
GDPA−167, ZDPA-167  
GDP-200, ZDP−200  
CLOCK SIGNAL  
UNIT  
MIN  
12  
MAX  
100  
PLLREF (PLLEN = 1)  
PLLOUT  
MHz  
MHz  
MHz  
MHz  
140  
600  
SYSCLK1  
Device Speed (DSP Core)  
100  
SYSCLK3 (EKSRC = 0)  
SYSCLK2 rate must be exactly half of SYSCLK1.  
Also see the electrical specification (timing requirements and switching characteristics parameters) in the Input  
and Output Clocks section of this data sheet.  
The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip  
as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 8, PLL and Clock Generator  
Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register.  
The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured  
via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL  
multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough  
time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP  
Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233).  
SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed  
to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be  
programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 8).  
During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output  
clocks, see Figure 8), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to  
ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1  
and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be  
programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the  
divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed  
before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final  
SYSCLK2 rate must be exactly half of the SYSCLK1 rate.  
Note that Divider D1 and Divider D2 must always be enabled (i.e., D1EN and D2EN bits are set to “1” in the  
PLLDIV1 and PLLDIV2 registers).  
The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be used  
to directly access the PLL Controller registers.  
For detailed information on the clock generator (PLL Controller registers) and their associated software bit  
descriptions, see Table 29 through Table 32.  
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PLL and PLL controller (continued)  
PLLCSR Register (0x01B7 C100)  
28 27  
24 23  
20 19  
31  
16  
0
Reserved  
R−0  
5
15  
12 11  
8
7
6
4
3
2
1
Reserved  
R−0  
STABLE  
R−x  
Reserved  
R−0  
PLLRST  
RW−1  
Reserved  
R/W−0  
PLLPWRDN  
R/W−0b  
PLLEN  
RW−0  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
Table 29. PLL Control/Status Register (PLLCSR)  
BIT #  
NAME  
DESCRIPTION  
31:7  
Reserved  
Reserved. Read-only, writes have no effect.  
Oscillator Input Stable. This bit indicates if the OSCIN/CLKIN input has stabilized.  
6
5:4  
3
STABLE  
Reserved  
PLLRST  
0
1
OSCIN/CLKIN input not yet stable. Oscillator counter is not finished counting (default).  
OSCIN/CLKIN input stable.  
Reserved. Read-only, writes have no effect.  
Asserts RESET to PLL  
0
1
PLL Reset Released.  
PLL Reset Asserted (default).  
2
Reserved  
PLLPWRDN  
Reserved. The user must write a “0” to this bit.  
Select PLL Power Down  
1
0
1
PLL Operational (default).  
PLL Placed in Power-Down State.  
PLL Mode Enable  
0
Bypass Mode (default). PLL disabled.  
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down  
directly from input reference clock.  
0
PLLEN  
1
PLL Enabled.  
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down  
from PLL output.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PLL and PLL controller (continued)  
PLLM Register (0x01B7 C110)  
28 27  
24 23  
20 19  
31  
16  
0
Reserved  
R−0  
15  
12 11  
8
7
6
5
4
3
2
1
Reserved  
R−0  
PLLM  
R/W−0 0111  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
Table 30. PLL Multiplier Control Register (PLLM)  
BIT #  
NAME  
DESCRIPTION  
Reserved. Read-only, writes have no effect.  
PLL multiply mode [default is x7 (0 0111)].  
31:5  
Reserved  
00000  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Reserved  
Reserved  
Reserved  
Reserved  
x4  
x5  
x6  
x7  
x8  
x9  
x10  
x11  
x12  
x13  
x14  
x15  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
x16  
x17  
x18  
x19  
x20  
x21  
x22  
x23  
4:0  
PLLM  
x24  
x25  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
PLLM select values 00000 through 00011 and 11010 through 11111 are not supported.  
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PLL and PLL controller (continued)  
PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers  
(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively)  
28 27  
12 11  
24 23  
20 19  
31  
16  
0
Reserved  
R−0  
7
14  
15  
8
5
4
3
2
1
DxEN  
R/W−1  
Reserved  
R−0  
PLLDIVx  
R/W−x xxxx  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.  
CAUTION:  
D1, and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.  
Table 31. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,  
D2, and D3)  
BIT #  
NAME  
DESCRIPTION  
Reserved. Read-only, writes have no effect.  
Divider Dx Enable (where x denotes 0 through 3).  
31:16  
Reserved  
0
1
Divider x Disabled. No clock output.  
Divider x Enabled (default).  
15  
DxEN  
These divider-enable bits are device-specific and must be set to 1 to enable.  
14:5  
Reserved  
Reserved. Read-only, writes have no effect.  
PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,  
/2, and /2, respectively].  
00000  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
/1  
/2  
/3  
/4  
/5  
/6  
/7  
/8  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
/17  
/18  
/19  
/20  
/21  
/22  
/23  
/24  
/25  
/26  
/27  
/28  
/29  
/30  
/31  
/32  
4:0  
PLLDIVx  
/9  
/10  
/11  
/12  
/13  
/14  
/15  
/16  
Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example,  
if D1 is set to /2, then D2 must be set to /4.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PLL and PLL controller (continued)  
OSCDIV1 Register (0x01B7 C124)  
28 27  
24 23  
20 19  
31  
16  
0
Reserved  
R−0  
7
14  
15  
12 11  
8
5
4
3
2
1
OD1EN  
R/W−1  
Reserved  
R−0  
OSCDIV1  
R/W−0 0111  
Legend: R = Read only, R/W = Read/Write; -n = value after reset  
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through  
the PLL path.  
Table 32. Oscillator Divider 1 Register (OSCDIV1)  
BIT #  
NAME  
DESCRIPTION  
Reserved. Read-only, writes have no effect.  
Oscillator Divider 1 Enable.  
31:16  
Reserved  
15  
OD1EN  
0
1
Oscillator Divider 1 Disabled.  
Oscillator Divider 1 Enabled (default).  
14:5  
Reserved  
Reserved. Read-only, writes have no effect.  
Oscillator Divider 1 Ratio [default is /8 (0 0111)].  
00000  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
/1  
/2  
/3  
/4  
/5  
/6  
/7  
/8  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
11110  
11111  
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
/17  
/18  
/19  
/20  
/21  
/22  
/23  
/24  
/25  
/26  
/27  
/28  
/29  
/30  
/31  
/32  
4:0  
OSCDIV1  
/9  
/10  
/11  
/12  
/13  
/14  
/15  
/16  
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general-purpose input/output (GPIO)  
To use the GP[7:4, 2] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and  
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.  
GPxEN =  
GPxDIR =  
GPxDIR =  
1
0
1
GP[x] pin is enabled  
GP[x] pin is an input  
GP[x] pin is an output  
where “x” represents one of the 7 through 4, or 2 GPIO pins  
Figure 9 shows the GPIO enable bits in the GPEN register for the device. To use any of the GPx pins as  
general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default  
values are device-specific, so refer to Figure 9 for the C6711D default configuration.  
31  
24 23  
Reserved  
R-0  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
GP7  
EN  
GP6  
EN  
GP5  
EN  
GP4  
EN  
GP2  
EN  
Reserved  
R/W-0  
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0  
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset  
Figure 9. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]  
Figure 10 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is  
an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By  
default, all the GPIO pins are configured as input pins.  
31  
24 23  
Reserved  
R-0  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
GP7  
DIR  
GP6  
DIR  
GP5  
DIR  
GP4  
DIR  
GP2  
DIR  
Reserved  
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0  
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset  
Figure 10. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]  
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP  
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).  
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power-down mode logic  
Figure 11 shows the power-down mode logic on the device.  
CLKOUT2  
Internal Clock Tree  
Clock  
Distribution  
and Dividers  
PD1  
PD2  
IFR  
Power-  
Clock  
PLL  
Internal  
Peripherals  
IER  
Down  
Logic  
CSR  
PWRD  
CPU  
PD3  
TMS320C6711D  
CLKIN  
RESET  
External input clocks, with the exception of CLKOUT3 and CLKIN, are not gated by the power-down mode logic.  
Figure 11. Power-Down Mode Logic  
triggering, wake-up, and effects  
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)  
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 12 and described in Table 33.  
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when  
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU  
and Instruction Set Reference Guide (literature number SPRU189).  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
31  
16  
15  
14  
13  
12  
PD3  
R/W-0  
11  
10  
9
8
0
Enable or  
Non-Enabled  
Interrupt Wake  
Enabled  
Interrupt Wake  
Reserved  
R/W-0  
PD2  
PD1  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
7
Legend: R/W−x = Read/write reset value  
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other  
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).  
Figure 12. PWRD Field of the CSR Register  
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the  
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account  
for this delay.  
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1  
took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first,  
then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt,  
the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the  
interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon  
PD1 mode termination by an enabled interrupt.  
PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes.  
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Table 33. Characteristics of the Power-Down Modes  
PRWD FIELD  
(BITS 15−10)  
POWER-DOWN  
WAKE-UP METHOD  
EFFECT ON CHIP’S OPERATION  
MODE  
000000  
001001  
No power-down  
CPU halted (except for the interrupt logic)  
PD1  
Wake by an enabled interrupt  
Power-down mode blocks the internal clock inputs at the  
boundary of the CPU, preventing most of the CPU’s logic from  
switching. During PD1, EDMA transactions can proceed  
between peripherals and internal memory.  
Wake by an enabled or  
non-enabled interrupt  
010001  
011010  
PD1  
Output clock from PLL is halted, stopping the internal clock  
structure from switching and resulting in the entire chip being  
halted. All register and internal RAM contents are preserved. All  
functional I/O “freeze” in the last state when the PLL clock is  
turned off.  
PD2  
Wake by a device reset  
Input clock to the PLL stops generating clocks. All register and  
internal RAM contents are preserved. All functional I/O “freeze” in  
the last state when the PLL clock is turned off. Following reset, the  
PLL needs time to re-lock, just as it does following power-up.  
Wake-up from PD3 takes longer than wake-up from PD2 because  
the PLL needs to be re-locked, just as it does following power-up.  
PD3  
011100  
Wake by a device reset  
All others  
Reserved  
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or  
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,  
peripherals will not operate according to specifications.  
The device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit in the  
PLLCSR register. With this enhanced functionality come some additional considerations when entering  
power-down modes.  
The power-down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the device. However,  
if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input (CLKIN).  
Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective.  
Make sure that the PLL is enabled by writing a “1” to PLLEN bit (PLLCSR.0) before writing to either PD3  
(CSR.11) or PD2 (CSR.10) to enter a power-down mode.  
power-supply sequencing  
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,  
systems should be designed to ensure that neither supply is powered up for extended periods of time  
(>1 second) if the other supply is below the proper operating voltage.  
system-level design considerations  
System-level design considerations, such as bus contention, may require supply sequencing to be  
implemented. The core supply should be powered up prior to (and powered down after) the I/O buffers. This  
is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus,  
preventing bus contention with other chips on the board.  
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power-supply design considerations  
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O  
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 13).  
I/O Supply  
DV  
DD  
Schottky  
Diode  
C6000  
DSP  
Core Supply  
CV  
DD  
V
SS  
GND  
Figure 13. Schottky Diode Diagram  
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize  
inductance and resistance in the power delivery path. Additionally, when designing for high-performance  
applications utilizing the C6000platform of DSPs, the PC board should include separate power planes for  
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.  
power-supply decoupling  
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible  
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps — 30 for the core supply  
and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP  
to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a  
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,  
therefore physically smaller capacitors should be used while maintaining the largest available capacitance  
value. As with the selection of any component, verification of capacitor availability over the product’s production  
lifetime needs to be considered.  
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IEEE 1149.1 JTAG compatibility statement  
The TMS320C6711D DSP requires that both TRST and RESET resets be asserted upon power up to be  
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both  
resets are required for proper operation.  
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected  
after TRST is asserted.  
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the  
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface  
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG  
controller to debug the DSP or exercise the DSP’s boundary scan functionality.  
The TMS320C6711D DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always  
be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this  
pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some  
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.  
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive  
TRST high before attempting any emulation or boundary scan operations.  
Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1  
and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For  
more detailed information, see the terminal functions section of this data sheet.  
Note: The DESIGN−WARNING section of the TMS320C6711D BSDL file contains information and constraints  
regarding proper device operation while in Boundary Scan Mode.  
For more detailed information on the C6711D JTAG emulation, see the TMS320C6000 DSP Designing for JTAG  
Emulation Reference Guide (literature number SPRU641).  
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EMIF device speed  
The maximum EMIF speed on the device is 100 MHz. TI recommends utilizing I/O buffer information  
specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given  
board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using  
IBIS Models for Timing Analysis application report (literature number SPRA839).  
For ease of design evaluation, Table 34 contains IBIS simulation results showing the maximum EMIF-SDRAM  
interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be  
performed to verify that all AC timings are met for the specified board layout. Other configurations are also  
possible, but again, timing analysis must be done to verify proper AC timings.  
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see  
the Terminal Functions table for the EMIF output signals).  
Table 34. Example Boards and Maximum EMIF Speed  
BOARD CONFIGURATION  
MAXIMUM ACHIEVABLE  
SDRAM SPEED GRADE  
EMIF-SDRAM  
INTERFACE SPEED  
EMIF INTERFACE  
COMPONENTS  
TYPE  
BOARD TRACE  
143 MHz 32-bit SDRAM (−7)  
166 MHz 32-bit SDRAM (−6)  
100 MHz  
For short traces, SDRAM data  
output hold time on these  
SDRAM speed grades cannot  
meet EMIF input hold time  
requirement (see NOTE 1).  
1 to 3-inch traces with proper  
termination resistors;  
Trace impedance ~ 50 Ω  
1-Load  
Short Traces  
One bank of one  
32-Bit SDRAM  
183 MHz 32-bit SDRAM (−55)  
200 MHz 32-bit SDRAM (−5)  
125 MHz 16-bit SDRAM (−8E)  
133 MHz 16-bit SDRAM (−75)  
143 MHz 16-bit SDRAM (−7E)  
167 MHz 16-bit SDRAM (−6A)  
167 MHz 16-bit SDRAM (−6)  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
1.2 to 3 inches from EMIF to  
each load, with proper  
termination resistors;  
2-Loads  
Short Traces  
One bank of two  
16-Bit SDRAMs  
Trace impedance ~ 78 Ω  
For short traces, EMIF cannot  
meet SDRAM input hold  
125 MHz 16-bit SDRAM (−8E)  
requirement (see NOTE 1).  
1.2 to 3 inches from EMIF to  
each load, with proper  
termination resistors;  
133 MHz 16-bit SDRAM (−75)  
143 MHz 16-bit SDRAM (−7E)  
167 MHz 16-bit SDRAM (−6A)  
100 MHz  
100 MHz  
100 MHz  
One bank of two  
32-Bit SDRAMs  
One bank of buffer  
3-Loads  
Short Traces  
Trace impedance ~ 78 Ω  
For short traces, EMIF cannot  
meet SDRAM input hold  
167 MHz 16-bit SDRAM (−6)  
requirement (see NOTE 1).  
143 MHz 32-bit SDRAM (−7)  
166 MHz 32-bit SDRAM (−6)  
183 MHz 32-bit SDRAM (−55)  
83 MHz  
83 MHz  
83 MHz  
One bank of one  
32-Bit SDRAM  
One bank of one  
32-Bit SBSRAM  
One bank of buffer  
3-Loads  
Long Traces  
4 to 7 inches from EMIF;  
Trace impedance ~ 63 Ω  
SDRAM data output hold time  
cannot meet EMIF input hold  
requirement (see NOTE 1).  
200 MHz 32-bit SDRAM (−5)  
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing  
requirements can be met for the particular system.  
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EMIF big endian mode correctness  
The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For  
the device, Little Endian is the default setting.  
The HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to change the  
EMIF data placement on the EMIF bus.  
When using the default setting of HD12 = 1, the EMIF will present 8-bit and 16-bit data on the ED[7:0] side of  
the bus if using Little Endian mode (HD8 = 1) and to the ED[31:24] side of the bus if using Big Endian mode.  
Figure 14 shows the mapping of 16-bit and 8-bit devices with EMIF endianness correction.  
EMIF DATA LINES (PINS) WHERE DATA PRESENT  
ED[31:24] (BE3)  
ED[23:16] (BE2)  
32-Bit Device in Any Endianness Mode  
16-Bit Device in Big Endianness Mode 16-Bit Device in Little Endianness Mode  
ED[15:8] (BE1)  
ED[7:0] (BE0)  
8-Bit Device in Big  
Endianness Mode  
8-Bit Device in Little Endianness Mode  
Figure 14. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1)  
When HD12 = 0, enabling EMIF endianness correction, the EMIF will present 8-bit and 16-bit data on the ED[7:0]  
side of the bus, regardless of the endianess mode (see Figure 15).  
EMIF DATA LINES (PINS) WHERE DATA PRESENT  
ED[31:24] (BE3)  
ED[23:16] (BE2)  
32-Bit Device in Any Endianness Mode  
16-Bit Device in Any Endianness Mode  
8-Bit Device in Any Endianness Mode  
ED[15:8] (BE1)  
ED[7:0] (BE0)  
Figure 15. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0)  
This new endianness correction functionality does not affect systems using the default value of HD12=1.  
This new feature does not affect systems operating in Little Endian mode.  
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bootmode  
The C67xdevice resets using the active-low signal RESET and the internal reset signal. While RESET is low,  
the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state.  
Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of the  
internal reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts  
the processor running with the prescribed device configuration and boot mode.  
The device has three types of boot modes:  
D
Host boot  
If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of  
the device is released. During this period, an external host can initialize the CPU’s memory space as  
necessary through the host interface, including internal configuration registers, such as those that control  
the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the  
DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration  
logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT  
condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT  
brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written  
to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is  
out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.  
D
D
Emulation boot  
Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to  
set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not  
been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,  
the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU  
prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.  
EMIF boot (using default ROM timings)  
Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to  
address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should  
be stored in the endian format that the system is using. The boot process also lets you choose the width of  
the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to  
form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a  
single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is  
released from the “stalled” state and start running from address 0.  
reset  
A hardware reset (RESET) is required to place the DSP into a known good state out of power−up. The RESET  
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages  
have reached their proper operating conditions. As a best practice, reset should be held low during power−up.  
Prior to deasserting RESET (low−to−high transition), the core and I/O voltages should be at their proper  
operating conditions and CLKIN should also be running at the correct frequency.  
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absolute maximum ratings over operating case temperature range (unless otherwise noted)  
Supply voltage range, CV  
Supply voltage range, DV  
Input voltage range  
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V  
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V  
DD  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV  
+ 0.5 V  
+ 0.5 V  
DD  
DD  
Output voltage range  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV  
Operating case temperature ranges, T  
(default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C  
C
(A version) [C6711DGDPA and C6711DZDPA] . . . −40_C to105_C  
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 2: All voltage values are with respect to V  
SS  
.
recommended operating conditions  
MIN NOM  
1.33 1.4  
MAX UNIT  
−250 only  
1.47  
1.32  
3.47  
0
V
V
V
V
CV  
DV  
Supply voltage, Core  
DD  
DD  
§
1.14  
§
1.20  
Supply voltage, I/O  
Supply ground  
3.13  
3.3  
0
V
SS  
0
2
2
All signals except CLKS1, DR1, and RESET  
CLKS1, DR1, and RESET  
V
High-level input voltage  
Low-level input voltage  
V
V
IH  
IL  
All signals except CLKS1, DR1, and RESET  
CLKS1, DR1, and RESET  
0.8  
V
0.3*DV  
DD  
–8  
All signals except ECLKOUT, CLKOUT2, CLKS1, and  
DR1  
I
High-level output current  
mA  
mA  
OH  
OL  
ECLKOUT and CLKOUT2  
–16  
8
All signals except ECLKOUT, CLKOUT2, CLKS1, and  
DR1  
I
Low-level output current  
ECLKOUT and CLKOUT2  
CLKS1 and DR1  
16  
3
mA  
mA  
Operating case  
temperature  
T
C
Default  
0
90  
_C  
#
V
V
Maximum voltage during overshoot (See Figure 19)  
Maximum voltage during undershoot (See Figure 20)  
Operating case  
4
V
V
OS  
#
−0.7  
US  
T
C
A version (C6711DGDPA and C6711DZDPA)  
–40  
105  
_C  
temperature  
The core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither  
supply is powered up for an extended period of time if the other supply is below the proper operating voltage.  
These values are compatible with existing 1.26−V designs.  
Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models.  
The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.  
§
#
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electrical characteristics over recommended ranges of supply voltage and operating case  
temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
High-level output  
voltage  
All signals except CLKS1 and  
DR1  
V
DV  
= MIN, I  
OH  
= MAX  
2.4  
V
OH  
OL  
DD  
DD  
All signals except CLKS1 and  
DR1  
0.4  
0.4  
170  
10  
Low-level output  
voltage  
V
DV  
= MIN, I  
OL  
= MAX  
V
CLKS1 and DR1  
All signals except CLKS1 and  
DR1  
uA  
uA  
uA  
uA  
I
I
Input current  
V = V  
I SS  
to DV  
DD  
I
CLKS1 and DR1  
All signals except CLKS1 and  
DR1  
170  
10  
Off-state output  
current  
V
O
= DV  
or 0 V  
OZ  
DD  
CLKS1 and DR1  
GDP, CV  
CPU clock = 250 MHz  
= 1.4-V,  
DD  
810  
560  
GDP/ZDP, CV  
1.26-V, CPU clock =  
200 MHz  
=
DD  
I
I
Core supply current  
mA  
DD2V  
GDPA/ZDPA, CV  
1.26-V, CPU clock =  
167 MHz  
=
DD  
475  
75  
DV  
= 3.3-V, EMIF  
DD  
speed = 100 MHz  
I/O supply current  
mA  
DD3V  
C
C
Input capacitance  
7
7
pF  
pF  
i
Output capacitance  
o
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.  
For this device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF.  
This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity  
operations. The high/low-DSP-activity models are defined as follows:  
High-DSP-Activity Model:  
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;  
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]  
McBSP: 2 channels at E1 rate  
Timers: 2 timers at maximum rate  
Low-DSP-Activity Model:  
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;  
L2/EMIF EDMA: None]  
McBSP: 2 channels at E1 rate  
Timers: 2 timers at maximum rate  
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power  
Consumption Summary application report (literature number SPRA889A).  
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PARAMETER MEASUREMENT INFORMATION  
Tester Pin Electronics  
Data Sheet Timing Reference Point  
42 Ω  
3.5 nH  
Output  
Under  
Test  
Transmission Line  
Z0 = 50 Ω  
(see note)  
Device Pin  
(see note)  
4.0 pF  
1.85 pF  
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects  
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.  
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from  
the data sheet timings.  
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.  
Figure 16. Test Load Circuit for AC Timing Measurements  
signal transition levels  
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.  
V
ref  
= 1.5 V  
Figure 17. Input and Output Voltage Reference Levels for AC Timing Measurements  
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, and  
IL  
IH  
V
MAX and V  
MIN for output clocks.  
OL  
OH  
V
ref  
= V MIN (or V  
IH OH  
MIN)  
V
ref  
= V MAX (or V  
IL OL  
MAX)  
Figure 18. Rise and Fall Transition Time Voltage Reference Levels  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PARAMETER MEASUREMENT INFORMATION (CONTINUED)  
AC transient rise/fall time specifications  
Figure 19 and Figure 20 show the AC transient specifications for Rise and Fall Time. For device-specific  
information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.  
t = 0.3 t (max)  
c
V
OS  
(max)  
Minimum  
Risetime  
V
IH  
(min)  
Waveform  
Valid Region  
Ground  
Figure 19. AC Transient Specification Rise Time  
t
c
= the peripheral cycle time.  
t = 0.3 t (max)  
c
V
IL  
(max)  
V
US  
(max)  
Ground  
Figure 20. AC Transient Specification Fall Time  
t
c
= the peripheral cycle time.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
PARAMETER MEASUREMENT INFORMATION (CONTINUED)  
timing parameters and board routing analysis  
The timing parameter values specified in this data sheet do not include delays by board routings. As a good  
board design practice, such delays must always be taken into account. Timing values may be adjusted by  
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification  
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate  
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature  
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing  
differences.  
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and  
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,  
but also tends to improve the input hold time margins (see Table 35 and Figure 21).  
Figure 21 represents a general transfer between the DSP and an external device. The figure also represents  
board route delays and how they are perceived by the DSP and the external device.  
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)  
Table 35. Board-Level Timings Example (see Figure 21)  
NO.  
1
DESCRIPTION  
Clock route delay  
2
Minimum DSP hold time  
3
Minimum DSP setup time  
External device hold time requirement  
External device setup time requirement  
Control signal route delay  
External device hold time  
4
5
6
7
8
External device access time  
DSP hold time requirement  
DSP setup time requirement  
Data route delay  
9
10  
11  
ECLKOUT  
(Output from DSP)  
1
ECLKOUT  
(Input to External Device)  
2
3
Control Signals  
(Output from DSP)  
4
5
6
Control Signals  
(Input to External Device)  
7
8
Data Signals  
(Output from External Device)  
9
10  
11  
Data Signals  
(Input to DSP)  
† Control signals include data for Writes.  
‡ Data signals are generated during Reads from an external device.  
Figure 21. Board-Level Input/Output Timings  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
INPUT AND OUTPUT CLOCKS  
†‡§  
timing requirements for CLKIN  
(see Figure 22)  
GDPA-167, ZDPA−167  
–200  
BYPASS MODE  
(PLLEN = 0)  
PLL MODE  
(PLLEN = 1)  
BYPASS MODE  
(PLLEN = 0)  
PLL MODE  
(PLLEN = 1)  
NO.  
UNIT  
MIN  
6
MAX  
MIN  
6.7  
MAX  
MIN  
5
MAX  
MIN  
6.7  
MAX  
1
2
3
4
t
t
t
t
Cycle time, CLKIN  
83.3  
83.3  
ns  
ns  
ns  
ns  
c(CLKIN)  
w(CLKINH)  
w(CLKINL)  
t(CLKIN)  
Pulse duration, CLKIN high  
Pulse duration, CLKIN low  
Transition time, CLKIN  
0.4C  
0.4C  
0.4C  
0.4C  
0.4C  
0.4C  
0.4C  
0.4C  
5
5
5
5
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.  
C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.  
See the PLL and PLL controller section of this data sheet.  
IL  
IH  
†‡§  
timing requirements for CLKIN  
(see Figure 22)  
–250  
PLL MODE  
(PLLEN = 1)  
BYPASS MODE  
(PLLEN = 0)  
NO.  
UNIT  
MIN  
4
MAX  
MIN  
6.7  
MAX  
1
2
3
4
t
t
t
t
Cycle time, CLKIN  
83.3  
ns  
ns  
ns  
ns  
c(CLKIN)  
w(CLKINH)  
w(CLKINL)  
t(CLKIN)  
Pulse duration, CLKIN high  
Pulse duration, CLKIN low  
Transition time, CLKIN  
0.4C  
0.4C  
0.4C  
0.4C  
5
5
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.  
C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.  
See the PLL and PLL controller section of this data sheet.  
IL  
IH  
1
4
2
CLKIN  
3
4
Figure 22. CLKIN Timings  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
INPUT AND OUTPUT CLOCKS (CONTINUED)  
†‡  
switching characteristics over recommended operating conditions for CLKOUT2  
(see Figure 23)  
GDPA-167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
MIN  
C2 − 0.8  
MAX  
1
2
3
4
t
t
t
t
Cycle time, CLKOUT2  
C2 + 0.8  
ns  
ns  
ns  
ns  
c(CKO2)  
w(CKO2H)  
w(CKO2L)  
t(CKO2)  
Pulse duration, CLKOUT2 high  
Pulse duration, CLKOUT2 low  
Transition time, CLKOUT2  
(C2/2) − 0.8 (C2/2) + 0.8  
(C2/2) − 0.8 (C2/2) + 0.8  
2
The reference points for the rise and fall transitions are measured at V  
C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period  
MAX and V MIN.  
OH  
OL  
divide-by-2.  
1
4
2
CLKOUT2  
3
4
Figure 23. CLKOUT2 Timings  
†§  
switching characteristics over recommended operating conditions for CLKOUT3  
(see Figure 24)  
GDPA-167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
MIN  
C3 − 0.9  
MAX  
1
2
3
4
5
t
t
t
t
Cycle time, CLKOUT3  
C3 + 0.9  
ns  
ns  
ns  
ns  
ns  
c(CKO3)  
w(CKO3H)  
w(CKO3L)  
t(CKO3)  
Pulse duration, CLKOUT3 high  
Pulse duration, CLKOUT3 low  
Transition time, CLKOUT3  
(C3/2) − 0.9 (C3/2) + 0.9  
(C3/2) − 0.9 (C3/2) + 0.9  
3
t
Delay time, CLKIN high to CLKOUT3 valid  
1.5  
7.5  
d(CLKINH-CKO3V)  
The reference points for the rise and fall transitions are measured at V  
OL  
MAX and V MIN.  
OH  
C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register. For more details, see  
PLL and PLL controller.  
CLKIN  
5
1
5
4
3
CLKOUT3  
2
4
NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.  
Figure 24. CLKOUT3 Timings  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
INPUT AND OUTPUT CLOCKS (CONTINUED)  
timing requirements for ECLKIN (see Figure 25)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
10  
MAX  
1
2
3
4
t
t
t
t
Cycle time, ECLKIN  
ns  
ns  
ns  
ns  
c(EKI)  
Pulse duration, ECLKIN high  
Pulse duration, ECLKIN low  
Transition time, ECLKIN  
4.5  
4.5  
w(EKIH)  
w(EKIL)  
t(EKI)  
3
The reference points for the rise and fall transitions are measured at V MAX and V MIN.  
IL IH  
1
4
2
ECLKIN  
3
4
Figure 25. ECLKIN Timings  
‡§¶  
switching characteristics over recommended operating conditions for ECLKOUT  
(see Figure 26)  
GDPA-167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
MIN  
MAX  
1
2
3
4
5
6
t
t
t
t
Cycle time, ECLKOUT  
E − 0.9  
E + 0.9  
ns  
ns  
ns  
ns  
ns  
ns  
c(EKO)  
Pulse duration, ECLKOUT high  
EH − 0.9 EH + 0.9  
EL − 0.9 EL + 0.9  
2
w(EKOH)  
w(EKOL)  
t(EKO)  
Pulse duration, ECLKOUT low  
Transition time, ECLKOUT  
t
Delay time, ECLKIN high to ECLKOUT high  
Delay time, ECLKIN low to ECLKOUT low  
1
1
6.5  
6.5  
d(EKIH-EKOH)  
t
d(EKIL-EKOL)  
§
The reference points for the rise and fall transitions are measured at V  
E = ECLKIN period in ns  
EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.  
MAX and V MIN.  
OH  
OL  
ECLKIN  
6
1
4
4
2
5
3
ECLKOUT  
Figure 26. ECLKOUT Timings  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
ASYNCHRONOUS MEMORY TIMING  
†‡§  
timing requirements for asynchronous memory cycles  
(see Figure 27−Figure 28)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
6.5  
1
MAX  
3
4
6
7
t
t
t
t
Setup time, EDx valid before ARE high  
Hold time, EDx valid after ARE high  
ns  
ns  
ns  
ns  
su(EDV-AREH)  
h(AREH-EDV)  
su(ARDY-EKOH)  
h(EKOH-ARDY)  
Setup time, ARDY valid before ECLKOUT high  
Hold time, ARDY valid after ECLKOUT high  
3
2.3  
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in  
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide  
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.  
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are  
programmed via the EMIF CE space control registers.  
E = ECLKOUT period in ns  
switching characteristics over recommended operating conditions for asynchronous memory  
†‡§  
cycles  
(see Figure 27–Figure 28)  
GDPA-167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
MIN  
MAX  
1
2
t
t
t
t
t
t
Output setup time, select signals valid to ARE low  
Output hold time, ARE high to select signals invalid  
Delay time, ECLKOUT high to ARE valid  
RS*E − 1.7  
ns  
ns  
ns  
ns  
ns  
ns  
osu(SELV-AREL)  
oh(AREH-SELIV)  
d(EKOH-AREV)  
osu(SELV-AWEL)  
oh(AWEH-SELIV)  
d(EKOH-AWEV)  
RH*E − 1.7  
1.5  
5
7
7
8
Output setup time, select signals valid to AWE low  
Output hold time, AWE high to select signals and EDx invalid  
Delay time, ECLKOUT high to AWE valid  
WS*E − 1.7  
WH*E − 1.7  
1.5  
9
10  
(WS−1)*E −  
1.7  
11  
t
Output setup time, ED valid to AWE low  
ns  
osu(EDV-AWEL)  
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are  
programmed via the EMIF CE space control registers.  
§
E = ECLKOUT period in ns  
Select signals include: CEx, BE[3:0], EA[21:2], and AOE.  
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)  
Setup = 2  
Strobe = 3  
Not Ready  
Hold = 2  
ECLKOUT  
CEx  
1
1
1
2
2
2
BE[3:0]  
EA[21:2]  
BE  
Address  
3
4
ED[31:0]  
1
5
2
5
Read Data  
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
AWE/SDWE/SSWE  
7
7
6
6
ARDY  
AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,  
respectively, during asynchronous memory accesses.  
Figure 27. Asynchronous Memory Read Timing  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
ASYNCHRONOUS MEMORY TIMING (CONTINUED)  
Setup = 2  
Hold = 2  
Strobe = 3  
Not Ready  
ECLKOUT  
CEx  
8
8
8
9
9
9
9
BE[3:0]  
BE  
EA[21:2]  
ED[31:0]  
Address  
Write Data  
11  
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
10  
10  
AWE/SDWE/SSWE  
7
7
6
6
ARDY  
AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,  
respectively, during asynchronous memory accesses.  
Figure 28. Asynchronous Memory Write Timing  
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SYNCHRONOUS-BURST MEMORY TIMING  
timing requirements for synchronous-burst SRAM cycles (see Figure 29)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
1.5  
MAX  
6
7
t
Setup time, read EDx valid before ECLKOUT high  
Hold time, read EDx valid after ECLKOUT high  
ns  
ns  
su(EDV-EKOH)  
t
2.5  
h(EKOH-EDV)  
The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but  
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.  
switching characteristics over recommended operating conditions for synchronous-burst SRAM  
†‡  
cycles (see Figure 29 and Figure 30)  
GDPA-167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
1
2
t
Delay time, ECLKOUT high to CEx valid  
1.2  
1.2  
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(EKOH-CEV)  
t
Delay time, ECLKOUT high to BEx valid  
d(EKOH-BEV)  
3
t
Delay time, ECLKOUT high to BEx invalid  
Delay time, ECLKOUT high to EAx valid  
d(EKOH-BEIV)  
4
t
7
d(EKOH-EAV)  
5
t
Delay time, ECLKOUT high to EAx invalid  
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid  
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid  
Delay time, ECLKOUT high to EDx valid  
1.2  
1.2  
1.2  
d(EKOH-EAIV)  
8
t
7
7
7
d(EKOH-ADSV)  
9
t
d(EKOH-OEV)  
10  
11  
12  
t
d(EKOH-EDV)  
t
Delay time, ECLKOUT high to EDx invalid  
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid  
1.2  
1.2  
d(EKOH-EDIV)  
t
7
d(EKOH-WEV)  
The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but  
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.  
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM  
accesses.  
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SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)  
ECLKOUT  
1
1
CEx  
2
3
BE1  
BE2  
BE3  
EA  
BE4  
7
BE[3:0]  
4
5
EA[21:2]  
ED[31:0]  
6
Q1  
Q2  
Q3  
Q4  
8
8
ARE/SDCAS/SSADS  
9
9
AOE/SDRAS/SSOE  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM  
accesses.  
Figure 29. SBSRAM Read Timing  
ECLKOUT  
1
2
1
3
CEx  
BE[3:0]  
BE1  
BE2  
Q2  
BE3  
5
BE4  
Q4  
4
EA[21:2]  
ED[31:0]  
EA  
10  
11  
12  
Q1  
Q3  
8
8
ARE/SDCAS/SSADS  
AOE/SDRAS/SSOE  
12  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM  
accesses.  
Figure 30. SBSRAM Write Timing  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
SYNCHRONOUS DRAM TIMING  
timing requirements for synchronous DRAM cycles (see Figure 31)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
1.5  
MAX  
6
7
t
t
Setup time, read EDx valid before ECLKOUT high  
Hold time, read EDx valid after ECLKOUT high  
ns  
ns  
su(EDV-EKOH)  
2.5  
h(EKOH-EDV)  
The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random  
bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.  
switching characteristics over recommended operating conditions for synchronous DRAM  
†‡  
cycles (see Figure 31−Figure 37)  
GDPA-167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
1
2
t
t
t
t
t
Delay time, ECLKOUT high to CEx valid  
1.5  
1.5  
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(EKOH-CEV)  
d(EKOH-BEV)  
d(EKOH-BEIV)  
d(EKOH-EAV)  
d(EKOH-EAIV)  
Delay time, ECLKOUT high to BEx valid  
3
Delay time, ECLKOUT high to BEx invalid  
Delay time, ECLKOUT high to EAx valid  
4
7
5
Delay time, ECLKOUT high to EAx invalid  
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid  
Delay time, ECLKOUT high to EDx valid  
1.5  
1.5  
8
t
7
7
d(EKOH-CASV)  
9
t
d(EKOH-EDV)  
d(EKOH-EDIV)  
d(EKOH-WEV)  
d(EKOH-RAS)  
10  
11  
12  
t
t
t
Delay time, ECLKOUT high to EDx invalid  
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid  
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid  
1.5  
1.5  
1.5  
7
7
The SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random  
bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
READ  
ECLKOUT  
CEx  
1
4
1
2
3
BE[3:0]  
BE1  
BE2  
BE3  
BE4  
5
5
5
Bank  
EA[21:13]  
EA[11:2]  
4
Column  
4
EA12  
6
7
ED[31:0]  
D1  
D2  
D3  
D4  
AOE/SDRAS/SSOE  
8
8
ARE/SDCAS/SSADS  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 31. SDRAM Read Command (CAS Latency 3)  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
WRITE  
ECLKOUT  
CEx  
1
2
4
4
4
9
2
4
5
5
5
9
3
BE[3:0]  
BE1  
Bank  
BE2  
BE3  
BE4  
EA[21:13]  
Column  
EA[11:2]  
EA12  
10  
ED[31:0]  
D1  
D2  
D3  
D4  
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
8
8
11  
11  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 32. SDRAM Write Command  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
ACTV  
ECLKOUT  
1
1
CEx  
BE[3:0]  
4
5
5
5
Bank Activate  
EA[21:13]  
EA[11:2]  
4
Row Address  
4
Row Address  
EA12  
ED[31:0]  
12  
12  
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 33. SDRAM ACTV Command  
DCAB  
ECLKOUT  
1
1
CEx  
BE[3:0]  
EA[21:13, 11:2]  
4
12  
11  
5
12  
11  
EA12  
ED[31:0]  
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 34. SDRAM DCAB Command  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
DEAC  
ECLKOUT  
1
1
CEx  
BE[3:0]  
4
5
EA[21:13]  
EA[11:2]  
Bank  
4
5
EA12  
ED[31:0]  
12  
11  
12  
11  
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 35. SDRAM DEAC Command  
REFR  
ECLKOUT  
1
1
CEx  
BE[3:0]  
EA[21:2]  
EA12  
ED[31:0]  
12  
8
12  
8
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 36. SDRAM REFR Command  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
SYNCHRONOUS DRAM TIMING (CONTINUED)  
MRS  
ECLKOUT  
1
1
5
CEx  
BE[3:0]  
4
EA[21:2]  
ED[31:0]  
MRS value  
12  
8
12  
8
AOE/SDRAS/SSOE  
ARE/SDCAS/SSADS  
11  
11  
AWE/SDWE/SSWE  
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM  
accesses.  
Figure 37. SDRAM MRS Command  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
HOLD/HOLDA TIMING  
timing requirements for the HOLD/HOLDA cycles (see Figure 38)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN MAX  
3
t
Hold time, HOLD low after HOLDA low  
E
ns  
h(HOLDAL-HOLDL)  
E = ECLKIN period in ns  
†‡  
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles  
(see Figure 38)  
GDPA-167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
§
1
2
4
5
t
Delay time, HOLD low to EMIF Bus high impedance  
Delay time, EMIF Bus high impedance to HOLDA low  
Delay time, HOLD high to EMIF Bus low impedance  
Delay time, EMIF Bus low impedance to HOLDA high  
2E  
0
ns  
ns  
ns  
ns  
d(HOLDL-EMHZ)  
t
2E  
7E  
2E  
d(EMHZ-HOLDAL)  
t
2E  
0
d(HOLDH-EMLZ)  
t
d(EMLZ-HOLDAH)  
§
E = ECLKIN period in ns  
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.  
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay  
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.  
External Requestor  
DSP Owns Bus  
DSP Owns Bus  
Owns Bus  
3
HOLD  
2
5
HOLDA  
1
4
EMIF Bus  
C67x  
C67x  
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.  
Figure 38. HOLD/HOLDA Timing  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
BUSREQ TIMING  
switching characteristics over recommended operating conditions for the BUSREQ cycles  
(see Figure 39)  
GDPA-167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
1.5  
MAX  
1
t
Delay time, ECLKOUT high to BUSREQ valid  
7.2  
ns  
d(EKOH-BUSRV)  
ECLKOUT  
BUSREQ  
1
1
Figure 39. BUSREQ Timing  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
RESET TIMING  
†‡  
timing requirements for reset (see Figure 40)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
100  
2P  
MAX  
1
t
t
t
Pulse duration, RESET  
ns  
ns  
ns  
w(RST)  
su(HD)  
h(HD)  
§
13  
14  
Setup time, HD boot configuration bits valid before RESET high  
§
Hold time, HD boot configuration bits valid after RESET high  
2P  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
The PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change the PLL mode in  
software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Software-Programmable Phase-Lock Loop (PLL)  
Controller Reference Guide (literature number SPRU233).  
The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits  
consist of: HD[8, 4:3].  
§
switching characteristics over recommended operating conditions during reset (see Figure 40)  
GDPA-167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
Delay time, external RESET high to internal reset  
high and all signal groups valid  
512 x CLKIN  
period  
2
t
CLKMODE0 = 1  
ns  
d(RSTH-ZV)  
#||  
3
4
t
t
t
t
t
t
t
t
t
t
Delay time, RESET low to ECLKOUT high impedance  
Delay time, RESET high to ECLKOUT valid  
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(RSTL-ECKOL)  
d(RSTH-ECKOV)  
d(RSTL-CKO2IV)  
d(RSTH-CKO2V)  
d(RSTL-CKO3L)  
d(RSTH-CKO3V)  
d(RSTL-EMIFZHZ)  
d(RSTL-EMIFLIV)  
d(RSTL-Z1HZ)  
6P  
6P  
6P  
5
Delay time, RESET low to CLKOUT2 high impedance  
Delay time, RESET high to CLKOUT2 valid  
6
7
Delay time, RESET low to CLKOUT3 low  
8
Delay time, RESET high to CLKOUT3 valid  
||  
9
Delay time, RESET low to EMIF Z group high impedance  
0
0
0
0
||  
Delay time, RESET low to EMIF low group (BUSREQ) invalid  
10  
11  
12  
||  
Delay time, RESET low to Z group 1 high impedance  
Delay time, RESET low to Z group 2 high impedance  
||  
d(RSTL-Z2HZ)  
P = 1/CPU clock frequency in ns.  
Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For  
example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while  
internal reset is asserted.  
#
||  
The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET  
is deasserted, the actual delay time may vary.  
EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and  
HOLDA  
EMIF low group consists of: BUSREQ  
Z group 1 consists of:  
Z group 2 consists of:  
CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.  
All other HPI and GPIO signals  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
RESET TIMING (CONTINUED)  
Phase 1  
Phase 2  
Phase 3  
CLKIN  
ECLKIN  
1
RESET  
2
Internal Reset  
Internal SYSCLK1  
Internal SYSCLK2  
Internal SYSCLK3  
3
5
4
6
ECLKOUT  
CLKOUT2  
CLKOUT3  
7
8
9
2
2
EMIF Z Group  
10  
EMIF Low Group  
11  
12  
2
Z Group  
Z Group 2  
14  
13  
Boot and Device  
Configuration Pins‡  
EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and  
HOLDA  
EMIF low group consists of: BUSREQ  
Z group 1 consists of:  
Z group 2 consists of:  
CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.  
All other HPI and GPIO signals  
Boot and device configurations consist of: HD[8, 4:3].  
Figure 40. Reset Timing  
Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN  
frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.  
Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal  
clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency  
divide-by-8.  
Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are  
running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN  
frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock  
source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin  
(when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.  
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005  
EXTERNAL INTERRUPT TIMING  
timing requirements for external interrupts (see Figure 41)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
2P  
4P  
2P  
4P  
MAX  
Width of the NMI interrupt pulse low  
ns  
ns  
ns  
ns  
1
2
t
t
w(ILOW)  
Width of the EXT_INT interrupt pulse low  
Width of the NMI interrupt pulse high  
Width of the EXT_INT interrupt pulse high  
w(IHIGH)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
2
1
EXT_INT, NMI  
Figure 41. External/NMI Interrupt Timing  
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SPRS292 − OCTOBER 2005  
HOST-PORT INTERFACE TIMING  
†‡  
timing requirements for host-port interface cycles (see Figure 42, Figure 43, Figure 44, and  
Figure 45)  
GDPA−167  
ZDPA−167  
−200  
−250  
NO.  
UNIT  
MIN  
MAX  
§
1
2
t
Setup time, select signals valid before HSTROBE low  
5
4
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
su(SELV-HSTBL)  
§
t
Hold time, select signals valid after HSTROBE low  
h(HSTBL-SELV)  
Pulse duration, HSTROBE low (host read access)  
Pulse duration, HSTROBE low (host write access)  
Pulse duration, HSTROBE high between consecutive accesses  
4P  
4P  
4P  
5
3
t
w(HSTBL)  
4
t
t
t
w(HSTBH)  
§
10  
11  
12  
13  
Setup time, select signals valid before HAS low  
su(SELV-HASL)  
h(HASL-SELV)  
§
Hold time, select signals valid after HAS low  
3
t
Setup time, host data valid before HSTROBE high  
Hold time, host data valid after HSTROBE high  
5
su(HDV-HSTBH)  
t
3
h(HSTBH-HDV)  
Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until  
HRDY is active (low); otherwise, HPI writes will not complete properly.  
14  
t
2
ns  
h(HRDYL-HSTBL)  
18  
19  
t
Setup time, HAS low before HSTROBE low  
Hold time, HAS low after HSTROBE low  
2
2
ns  
ns  
su(HASL-HSTBL)  
t
h(HSTBL-HASL)  
§
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
Select signals include: HCNTL[1:0], HR/W, and HHWIL.  
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SPRS292 − OCTOBER 2005  
HOST-PORT INTERFACE TIMING (CONTINUED)  
switching characteristics over recommended operating conditions during host-port interface  
†‡  
cycles (see Figure 42, Figure 43, Figure 44, and Figure 45)  
GDPA−167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN MAX  
§
5
6
7
t
Delay time, HCS to HRDY  
1
3
2
12  
12  
ns  
ns  
ns  
d(HCS-HRDY)  
t
Delay time, HSTROBE low to HRDY high  
d(HSTBL-HRDYH)  
t
Delay time, HSTROBE low to HD low impedance for an HPI read  
d(HSTBL-HDLZ)  
8
t
Delay time, HD valid to HRDY low  
2P − 4  
ns  
ns  
ns  
ns  
ns  
d(HDV-HRDYL)  
9
t
Output hold time, HD valid after HSTROBE high  
Delay time, HSTROBE high to HD high impedance  
Delay time, HSTROBE low to HD valid  
3
3
3
3
12  
12  
oh(HSTBH-HDV)  
15  
16  
17  
t
d(HSTBH-HDHZ)  
t
12.5  
12  
d(HSTBL-HDV)  
#
Delay time, HSTROBE high to HRDY high  
t
d(HSTBH-HRDYH)  
§
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy  
completing a previous HPID write or READ with autoincrement.  
#
This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the  
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads  
the requested data into HPID.  
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write  
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.  
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SPRS292 − OCTOBER 2005  
HOST-PORT INTERFACE TIMING (CONTINUED)  
HAS  
HCNTL[1:0]  
HR/W  
1
1
1
1
2
2
2
2
2
2
1
1
HHWIL  
4
3
3
HSTROBE  
HCS  
15  
9
15  
9
7
16  
HD[15:0] (output)  
HRDY (case 1)  
HRDY (case 2)  
5
5
1st halfword  
2nd halfword  
5
8
8
17  
17  
6
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
Figure 42. HPI Read Timing (HAS Not Used, Tied High)  
HAS  
19  
11  
19  
11  
10  
10  
10  
10  
HCNTL[1:0]  
HR/W  
11  
11  
11  
11  
10  
10  
HHWIL  
4
3
HSTROBE  
18  
18  
HCS  
15  
15  
7
9
16  
9
17  
17  
HD[15:0] (output)  
HRDY (case 1)  
HRDY (case 2)  
1st half-word  
2nd half-word  
5
8
8
5
5
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.  
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
Figure 43. HPI Read Timing (HAS Used)  
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SPRS292 − OCTOBER 2005  
HOST-PORT INTERFACE TIMING (CONTINUED)  
HAS  
HCNTL[1:0]  
HR/W  
1
1
2
2
2
2
3
1
1
1
1
2
2
HHWIL  
3
4
14  
HSTROBE  
HCS  
HD[15:0] (input)  
HRDY  
12  
12  
13  
2nd halfword  
13  
17  
1st halfword  
5
5
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
Figure 44. HPI Write Timing (HAS Not Used, Tied High)  
HAS  
19  
11  
19  
11  
11  
11  
10  
10  
10  
10  
10  
10  
HCNTL[1:0]  
HR/W  
11  
11  
HHWIL  
3
4
14  
HSTROBE  
18  
12  
18  
HCS  
HD[15:0] (input)  
HRDY  
12  
13  
13  
1st half-word  
2nd half-word  
5
5
17  
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.  
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
Figure 45. HPI Write Timing (HAS Used)  
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SPRS292 − OCTOBER 2005  
MULTICHANNEL BUFFERED SERIAL PORT TIMING  
†‡  
timing requirements for McBSP (see Figure 46)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
MAX  
§
2
3
t
t
Cycle time, CLKR/X  
CLKR/X ext  
CLKR/X ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
2P  
ns  
ns  
c(CKRX)  
Pulse duration, CLKR/X high or CLKR/X low  
0.5*t 1  
c(CKRX)  
w(CKRX)  
9
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low  
Hold time, external FSR high after CLKR low  
Setup time, DR valid before CLKR low  
ns  
ns  
ns  
ns  
ns  
ns  
su(FRH-CKRL)  
h(CKRL-FRH)  
su(DRV-CKRL)  
h(CKRL-DRV)  
su(FXH-CKXL)  
h(CKXL-FXH)  
1
6
3
8
0
3
4
9
1
6
3
7
8
Hold time, DR valid after CLKR low  
10  
11  
Setup time, external FSX high before CLKX low  
Hold time, external FSX high after CLKX low  
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for  
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;  
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The  
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle  
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum  
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =  
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port  
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0)  
in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.  
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
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SPRS292 − OCTOBER 2005  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
switching characteristics over recommended operating conditions for McBSP (see Figure 46)  
GDPA−167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from  
CLKS input  
1
t
1.8  
10  
ns  
d(CKSH-CKRXH)  
§¶  
2
3
4
t
t
t
Cycle time, CLKR/X  
CLKR/X int  
CLKR/X int  
CLKR int  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
2P  
ns  
ns  
ns  
c(CKRX)  
#
#
Pulse duration, CLKR/X high or CLKR/X low  
Delay time, CLKR high to internal FSR valid  
C − 1  
C + 1  
w(CKRX)  
−2  
−2  
2
3
3
9
4
d(CKRH-FRV)  
9
t
t
t
Delay time, CLKX high to internal FSX valid  
ns  
ns  
ns  
d(CKXH-FXV)  
dis(CKXH-DXHZ)  
d(CKXH-DXV)  
−1  
1.5  
Disable time, DX high impedance following last data bit from  
CLKX high  
12  
13  
10  
||  
||  
−3.2 + D1  
0.5 + D1  
4 + D2  
10+ D2  
Delay time, CLKX high to DX valid  
Delay time, FSX high to DX valid  
||  
||  
FSX int  
FSX ext  
−1  
2
7.5  
14  
t
ns  
d(FXH-DXV)  
ONLY applies when in data  
delay 0 (XDATDLY = 00b) mode  
11.5  
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.  
Minimum delay times also represent minimum output hold times.  
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.  
The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for  
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 200-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;  
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The  
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle  
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 15 ns as the minimum  
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =  
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port  
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM  
= 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.  
C = H or L  
#
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).  
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
If DXENA = 0, then D1 = D2 = 0  
||  
If DXENA = 1, then D1 = 2P, D2 = 4P  
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SPRS292 − OCTOBER 2005  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
CLKS  
1
2
3
3
CLKR  
4
4
FSR (int)  
5
6
FSR (ext)  
DR  
7
8
Bit(n-1)  
(n-2)  
(n-3)  
2
3
3
CLKX  
9
FSX (int)  
11  
10  
FSX (ext)  
FSX (XDATDLY=00b)  
13  
(n-2)  
13  
14  
13  
12  
Bit 0  
DX  
Bit(n-1)  
(n-3)  
Figure 46. McBSP Timings  
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SPRS292 − OCTOBER 2005  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
timing requirements for FSR when GSYNC = 1 (see Figure 47)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
4
MAX  
1
2
t
t
Setup time, FSR high before CLKS high  
Hold time, FSR high after CLKS high  
ns  
ns  
su(FRH-CKSH)  
4
h(CKSH-FRH)  
CLKS  
1
2
FSR external  
CLKR/X (no need to resync)  
CLKR/X (needs resync)  
Figure 47. FSR Timing When GSYNC = 1  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 48)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX low  
Hold time, DR valid after CLKX low  
2 − 6P  
5 + 12P  
ns  
ns  
su(DRV-CKXL)  
h(CKXL-DRV)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
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SPRS292 − OCTOBER 2005  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
switching characteristics over recommended operating conditions for McBSP as SPI master or  
†‡  
slave: CLKSTP = 10b, CLKXP = 0 (see Figure 48)  
GDPA−167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
Hold time, FSX low  
after CLKX low  
1
t
T − 2 T + 3  
L − 2 L + 3  
ns  
h(CKXL-FXL)  
#
2
3
t
t
Delay time, FSX low to CLKX high  
ns  
ns  
d(FXL-CKXH)  
Delay time, CLKX high to DX valid  
−3  
4
6P + 2 10P + 17  
d(CKXH-DXV)  
Disable time, DX high impedance following last data bit from  
CLKX low  
6
t
L − 2 L + 3  
ns  
dis(CKXL-DXHZ)  
Disable time, DX high impedance following last data bit from  
FSX high  
7
8
t
2P + 3  
4P + 2  
6P + 17  
8P + 17  
ns  
ns  
dis(FXH-DXHZ)  
t
Delay time, FSX low to DX valid  
d(FXL-DXV)  
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
CLKX  
1
2
8
FSX  
7
6
3
DX  
DR  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
4
5
Bit 0  
(n-2)  
(n-3)  
(n-4)  
Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0  
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SPRS292 − OCTOBER 2005  
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 49)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
2 − 6P  
ns  
ns  
su(DRV-CKXH)  
5 + 12P  
h(CKXH-DRV)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
#
switching characteristics over recommended operating conditions for McBSP as SPI master or  
†‡  
slave: CLKSTP = 11b, CLKXP = 0 (see Figure 49)  
GDPA−167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
§
MASTER  
SLAVE  
MIN  
MIN  
MAX  
MAX  
Hold time, FSX low after CLKX  
low  
1
t
L − 2  
L + 3  
ns  
h(CKXL-FXL)  
#
2
3
t
t
Delay time, FSX low to CLKX high  
T − 2  
−3  
T + 3  
4
ns  
ns  
d(FXL-CKXH)  
Delay time, CLKX low to DX valid  
6P + 2  
6P + 3  
10P + 17  
10P + 17  
d(CKXL-DXV)  
Disable time, DX high  
impedance following last data bit  
from CLKX low  
6
t
−2  
4
ns  
ns  
dis(CKXL-DXHZ)  
d(FXL-DXV)  
7
t
Delay time, FSX low to DX valid  
H − 2  
H + 6.5  
4P + 2  
8P + 17  
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)  
CLKX  
FSX  
DX  
1
2
7
6
3
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-3)  
(n-4)  
4
5
DR  
Bit 0  
(n-2)  
(n-4)  
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0  
†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 50)  
GDPA-167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
2 − 6P  
ns  
ns  
su(DRV-CKXH)  
5 + 12P  
h(CKXH-DRV)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
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switching characteristics over recommended operating conditions for McBSP as SPI master or  
†‡  
slave: CLKSTP = 10b, CLKXP = 1 (see Figure 50)  
GDPA−167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
§
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
Hold time, FSX low  
after CLKX high  
1
t
T − 2 T + 3  
H − 2 H + 3  
ns  
h(CKXH-FXL)  
#
2
3
t
t
Delay time, FSX low to CLKX low  
ns  
ns  
d(FXL-CKXL)  
Delay time, CLKX low to DX valid  
−3  
4
6P + 2 10P + 17  
d(CKXL-DXV)  
Disable time, DX high impedance following last data bit from  
CLKX high  
6
t
H − 2 H + 3  
ns  
dis(CKXH-DXHZ)  
Disable time, DX high impedance following last data bit from FSX  
high  
7
8
t
2P + 3  
4P + 2  
6P + 17  
8P + 17  
ns  
ns  
dis(FXH-DXHZ)  
t
Delay time, FSX low to DX valid  
d(FXL-DXV)  
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
CLKX  
1
2
8
FSX  
7
6
3
DX  
DR  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
4
5
Bit 0  
(n-2)  
(n-3)  
(n-4)  
Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1  
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†‡  
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 51)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MASTER  
SLAVE  
MIN MAX  
MIN  
12  
4
MAX  
4
5
t
t
Setup time, DR valid before CLKX high  
Hold time, DR valid after CLKX high  
2 − 6P  
ns  
ns  
su(DRV-CKXH)  
5 + 12P  
h(CKXH-DRV)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
switching characteristics over recommended operating conditions for McBSP as SPI master or  
†‡  
slave: CLKSTP = 11b, CLKXP = 1 (see Figure 51)  
GDPA−167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
§
MASTER  
SLAVE  
MIN MAX  
MIN  
H − 2  
T − 2  
−3  
MAX  
H + 3  
T + 3  
4
1
2
3
t
t
t
Hold time, FSX low after CLKX high  
ns  
ns  
ns  
h(CKXH-FXL)  
d(FXL-CKXL)  
d(CKXH-DXV)  
#
Delay time, FSX low to CLKX low  
Delay time, CLKX high to DX valid  
6P + 2 10P + 17  
6P + 3 10P + 17  
Disable time, DX high impedance following last data bit from  
CLKX high  
6
7
t
−2  
4
ns  
ns  
dis(CKXH-DXHZ)  
t
Delay time, FSX low to DX valid  
L − 2 L + 6.5  
4P + 2  
8P + 17  
d(FXL-DXV)  
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)  
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
T = CLKX period = (1 + CLKGDV) * S  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero  
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX  
and FSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP  
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP  
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock  
(CLKX).  
CLKX  
1
2
FSX  
DX  
7
6
3
Bit 0  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-2)  
(n-3)  
(n-4)  
4
5
DR  
(n-2)  
(n-3)  
(n-4)  
Figure 51. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1  
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TIMER TIMING  
timing requirements for timer inputs (see Figure 52)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
2P  
MAX  
1
2
t
t
Pulse duration, TINP high  
Pulse duration, TINP low  
ns  
ns  
w(TINPH)  
2P  
w(TINPL)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
switching characteristics over recommended operating conditions for timer outputs  
(see Figure 52)  
GDPA−167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
MIN  
4P − 3  
4P − 3  
MAX  
3
4
t
t
Pulse duration, TOUT high  
Pulse duration, TOUT low  
ns  
ns  
w(TOUTH)  
w(TOUTL)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
2
1
TINPx  
4
3
TOUTx  
Figure 52. Timer Timing  
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING  
†‡  
timing requirements for GPIO inputs (see Figure 53)  
GDPA−167  
ZDPA−167  
−200  
−250  
NO.  
UNIT  
MIN  
MAX  
1
2
t
t
Pulse duration, GPIx high  
Pulse duration, GPIx low  
4P  
4P  
ns  
ns  
w(GPIH)  
w(GPIL)  
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx  
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access  
the GPIO register through the CFGBUS.  
†§  
switching characteristics over recommended operating conditions for GPIO outputs  
(see Figure 53)  
GDPA−167  
ZDPA−167  
−200  
−250  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
3
4
t
t
Pulse duration, GPOx high  
Pulse duration, GPOx low  
12P − 3  
12P − 3  
ns  
ns  
w(GPOH)  
w(GPOL)  
§
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.  
The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles; therefore, the minimum  
GPOx pulse width is 12P.  
2
1
GPIx  
4
3
GPOx  
Figure 53. GPIO Port Timing  
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JTAG TEST-PORT TIMING  
timing requirements for JTAG test port (see Figure 54)  
GDPA−167  
ZDPA−167  
−200  
NO.  
UNIT  
−250  
MIN  
35  
10  
7
MAX  
1
3
4
t
t
t
Cycle time, TCK  
ns  
ns  
ns  
c(TCK)  
Setup time, TDI/TMS/TRST valid before TCK high  
Hold time, TDI/TMS/TRST valid after TCK high  
su(TDIV-TCKH)  
h(TCKH-TDIV)  
switching characteristics over recommended operating conditions for JTAG test port  
(see Figure 54)  
GDPA−167  
ZDPA−167  
−200  
NO.  
PARAMETER  
UNIT  
−250  
MIN  
MAX  
15  
2
t
Delay time, TCK low to TDO valid  
0
ns  
d(TCKL-TDOV)  
1
TCK  
TDO  
2
2
4
3
TDI/TMS/TRST  
Figure 54. JTAG Test-Port Timing  
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MECHANICAL DATA  
package thermal resistance characteristics  
The following tables show the thermal resistance characteristics for the GDP and ZDP mechanical packages.  
thermal resistance characteristics (S-PBGA package) for GDP  
NO  
°C/W  
Air Flow (m/s)  
Two Signals, Two Planes (4-Layer Board)  
1
RΘ  
Junction-to-case  
9.7  
N/A  
JC  
2
3
4
5
6
7
8
9
Psi  
Junction-to-package top  
Junction-to-board  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-board  
1.5  
19  
22  
21  
20  
19  
18  
16  
0.0  
N/A  
0.0  
0.5  
1.0  
2.0  
4.0  
0.0  
JT  
RΘ  
RΘ  
RΘ  
RΘ  
RΘ  
RΘ  
JB  
JA  
JA  
JA  
JA  
JA  
JB  
Psi  
m/s = meters per second  
thermal resistance characteristics (S-PBGA package) for ZDP  
NO  
°C/W  
Air Flow (m/s)  
Two Signals, Two Planes (4-Layer Board)  
1
RΘ  
Junction-to-case  
9.7  
N/A  
JC  
2
3
4
5
6
7
8
9
Psi  
Junction-to-package top  
Junction-to-board  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-free air  
Junction-to-board  
1.5  
19  
22  
21  
20  
19  
18  
16  
0.0  
N/A  
0.0  
0.5  
1.0  
2.0  
4.0  
0.0  
JT  
RΘ  
RΘ  
RΘ  
RΘ  
RΘ  
RΘ  
JB  
JA  
JA  
JA  
JA  
JA  
JB  
Psi  
m/s = meters per second  
packaging information  
The following packaging information and addendum reflect the most current released data available for the  
designated device(s). This data is subject to change without notice and without revision of this document.  
103  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
14-Nov-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
BGA  
BGA  
BGA  
Drawing  
TMS320C6711DGDP200  
TMS320C6711DGDP250  
TMS320C6711DZDP200  
ACTIVE  
ACTIVE  
ACTIVE  
GDP  
272  
272  
272  
40  
1
TBD  
TBD  
SNPB  
SNPB  
Level-3-220C-168HR  
Level-3-220C-168HR  
Level-3-260C-168HR  
GDP  
ZDP  
40  
Pb-Free  
(RoHS)  
SNAGCU  
TMS32C6711DGDPA167  
ACTIVE  
BGA  
GDP  
272  
40  
TBD  
SNPB  
Level-3-220C-168HR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MPBG274 – MAY 2002  
GDP (S–PBGA–N272)  
PLASTIC BALL GRID ARRAY  
27,20  
26,80  
24,20  
23,80  
SQ  
SQ  
24,13 TYP  
1,27  
0,635  
Y
W
V
U
T
R
P
N
M
L
1,27  
K
J
H
G
F
0,635  
A1 Corner  
E
D
C
B
A
1
3
5
7
8
9
11 13 15 17 19  
10 12 14 16 18 20  
2
4
6
1,22  
1,12  
Bottom View  
2,57 MAX  
Seating Plane  
0,15  
0,90  
0,60  
0,65  
0,57  
0,10  
0,70  
0,50  
4204396/A 04/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MO-151  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPBG276 – MAY 2002  
ZDP (S–PBGA–N272)  
PLASTIC BALL GRID ARRAY  
27,20  
26,80  
24,20  
23,80  
SQ  
SQ  
24,13 TYP  
1,27  
0,635  
Y
W
V
U
T
R
P
N
M
L
1,27  
K
J
H
G
F
0,635  
A1 Corner  
E
D
C
B
A
1
3
5
7
8
9
11 13 15 17 19  
10 12 14 16 18 20  
2
4
6
1,22  
1,12  
Bottom View  
2,57 MAX  
Seating Plane  
0,15  
0,90  
0,60  
0,65  
0,57  
0,10  
0,70  
0,50  
4204398/A 04/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MO-151  
D. This package is lead-free.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
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