Intel Pentium G2010 2 80 Ghz Processor BX80637G2010 User Manual

Desktop 3rd Generation Intel

Core™ Processor Family, Desktop

Intel Pentium Processor Family,

and Desktop Intel Celeron

Processor Family

Datasheet – Volume 1 of 2

November 2013

Document Number: 326764-008



Contents

Introductio n ..............................................................................................................9

1.1

Processor Feature Details ................................................................................... 11

1.1.1 Supported Technologies .......................................................................... 11

Interfaces ........................................................................................................ 11

1.2.1 System Memory Suppor t ......................................................................... 11

1.2.2 PCI Express* ......................................................................................... 12

1.2.3 Direct Media Interface (DMI).................................................................... 14

1.2.4 Platform Environment Control Interface (PECI )........................................... 14

1.2.5 Processor Graphic s ................................................................................. 14

1.2

1.2.6 Intel Flexible Display Interface (Intel FDI)............................................. 15

Power Management Support ............................................................................... 15

1.3.1 Processor Core....................................................................................... 15

1.3.2 Syste m ................................................................................................. 15

1.3.3 Memory Controller.................................................................................. 15

1.3.4 PCI Express* ......................................................................................... 16

1.3.5 Direct Media Interface (DMI).................................................................... 16

1.3.6 Processor Graphics Controller (GT) ........................................................... 16

1.3.7 Thermal Management Support ................................................................. 16

Processor SKU Definitions................................................................................... 16

Packag e ........................................................................................................... 17

Processor Compatibilit y ...................................................................................... 18

Terminology ..................................................................................................... 19

1.4

Interfaces ................................................................................................................ 23

2.1

System Memory Interface .................................................................................. 23

2.1.1 System Memory Technology Supporte d ..................................................... 23

2.1.2 System Memory Timing Support............................................................... 24

2.1.3 System Memory Organization Modes......................................................... 25

2.1.3.1 Single-Channel Mode................................................................. 25

2.1.3.2 Dual-Channel Mode – Intel Flex Memory Technology Mode ........... 25

2.1.4 Rules for Populating Memory Slot s ............................................................ 26

2.1.5 Technology Enhancements of Intel Fast Memory Access (Intel FMA).......... 27

2.1.5.1 Just-in-Time Command Scheduling.............................................. 27

2.1.5.2 Command Overlap .................................................................... 27

2.1.5.3 Out-of-Order Schedulin g ............................................................ 27

2.1.6 Data Scrambling .................................................................................... 27

2.1.7 DDR3 Reference Voltage Generation ......................................................... 27

PCI Express* Interface....................................................................................... 28

2.2.1 PCI Express* Architecture ....................................................................... 28

2.2.1.1 Transaction Layer ..................................................................... 29

2.2.1.2 Data Link Layer ........................................................................ 29

2.2.1.3 Physical Layer .......................................................................... 29

2.2.2 PCI Express* Configuration Mechanism ..................................................... 30

2.2.3 PCI Express* Port................................................................................... 31

2.2.3.1 PCI Express* Lanes Connection .................................................. 31

Direct Media Interface (DMI)............................................................................... 32

2.3.1 DMI Error Flow....................................................................................... 32

2.3.2 Processor / PCH Compatibility Assumptions................................................ 32

2.3.3 DMI Link Down ...................................................................................... 32

Processor Graphics Controller (GT) ...................................................................... 33

2.2

2.3

2.4

Datasheet, Volume 1

2.4.1 3D and Video Engines for Graphics Processing ............................................33

2.4.1.1 3D Engine Execution Unit s ..........................................................33

2.4.1.2 3D Pipelin e ...............................................................................34

2.4.1.3 Video Engine ............................................................................34

2.4.1.4 2D Engine ................................................................................35

2.4.2 Processor Graphics Display ......................................................................36

2.4.2.1 Display Planes ..........................................................................36

2.4.2.2 Display Pipes ............................................................................37

2.4.2.3 Display Ports ............................................................................37

2.4.3 Intel Flexible Display Interface (Intel FDI) .............................................37

2.4.4 Multi Graphics Controllers Multi-Monitor Suppor t .........................................37

Platform Environment Control Interface (PECI) ......................................................38

Interface Clocking..............................................................................................38

2.6.1 Internal Clocking Requirements ................................................................38

2.5

2.6

Technologies ............................................................................................................39

3.1

Intel Virtualization Technology (Intel VT )..........................................................39

3.1.1 Intel Virtualization Technology (Intel VT) for 

IA-32, Intel 64 and Intel Architecture 

(Intel VT-x) Objective s ..........................................................................39

3.1.2 Intel Virtualization Technology (Intel VT) for 

IA-32, Intel 64 and Intel Architecture 

(Intel VT-x) Features ............................................................................40

3.1.3 Intel Virtualization Technology (Intel VT) for Directed 

I/O (Intel VT-d) Objectives ....................................................................40

3.1.4 Intel Virtualization Technology (Intel VT) for Directed 

I/O (Intel VT-d) Feature s .......................................................................41

3.1.5 Intel Virtualization Technology (Intel VT) for Directed 

I/O (Intel VT-d) Features Not Supported..................................................41

3.2

3.3

3.4

Intel Trusted Execution Technology (Intel TXT) .................................................42

Intel Hyper-Threading Technology (Intel HT Technology )....................................42

Intel Turbo Boost Technolog y ............................................................................43

3.4.1 Intel Turbo Boost Technology Frequency..................................................43

3.4.2 Intel Turbo Boost Technology Graphics Frequency.....................................43

Intel Advanced Vector Extensions (Intel AVX)....................................................44

3.5

3.6

Security and Cryptography Technologie s ...............................................................44

3.6.1 Intel Advanced Encryption Standard New Instructions (Intel AES-NI) ........44

3.6.2 PCLMULQDQ Instruction ..........................................................................44

3.6.3 RDRAND Instructio n ................................................................................45

3.7

3.8

3.9

Intel 64 Architecture x2APIC.............................................................................45

Supervisor Mode Execution Protection (SMEP) .......................................................46

Power Aware Interrupt Routing (PAIR)..................................................................46

Power Management .................................................................................................47

4.1

Advanced Configuration and Power Interface

(ACPI) States Supported.....................................................................................48

4.1.1 System States........................................................................................48

4.1.2 Processor Core / Package Idle States.........................................................48

4.1.3 Integrated Memory Controller State s .........................................................48

4.1.4 PCI Express* Link States .........................................................................49

4.1.5 Direct Media Interface (DMI) States ..........................................................49

4.1.6 Processor Graphics Controller States .........................................................49

4.1.7 Interface State Combinations ...................................................................49

Processor Core Power Managemen t ......................................................................50

4.2

4.2.1 Enhanced Intel SpeedStep Technology ..................................................50

4.2.2 Low-Power Idle States.............................................................................50

4.2.3 Requesting Low-Power Idle States ............................................................52

Datasheet, Volume 1



4.2.4 Core C-states ........................................................................................ 52

4.2.4.1 Core C0 State........................................................................... 52

4.2.4.2 Core C1 / C1E Stat e .................................................................. 53

4.2.4.3 Core C3 State........................................................................... 53

4.2.4.4 Core C6 State........................................................................... 53

4.2.4.5 C-State Auto-Demotion ............................................................. 53

4.2.5 Package C-State s ................................................................................... 54

4.2.5.1 Package C 0 .............................................................................. 55

4.2.5.2 Package C1/C1E ....................................................................... 55

4.2.5.3 Package C3 State...................................................................... 56

4.2.5.4 Package C6 State...................................................................... 56

Integrated Memory Controller (IMC) Power Management ........................................ 56

4.3.1 Disabling Unused System Memory Outputs ................................................ 56

4.3.2 DRAM Power Management and Initializatio n ............................................... 57

4.3.2.1 Initialization Role of CK E ............................................................ 58

4.3.2.2 Conditional Self-Refresh ............................................................ 58

4.3.2.3 Dynamic Power Down Operation ................................................. 59

4.3.2.4 DRAM I/O Power Managemen t .................................................... 59

4.3.3 DDR Electrical Power Gating (EPG) ........................................................... 59

PCI Express* Power Managemen t ........................................................................ 60

DMI Power Management..................................................................................... 60

Graphics Power Management .............................................................................. 60

4.6.1 Intel Rapid Memory Power Management (Intel RMPM) 

(also known as CxSR)............................................................................. 60

4.6.2 Intel Graphics Performance Modulation Technology (Intel GPMT).............. 60

4.6.3 Graphics Render C-Stat e ......................................................................... 60

4.6.4 Intel Smart 2D Display Technology (Intel S2DDT) .................................. 61

4.6.5 Intel Graphics Dynamic Frequency.......................................................... 61

4.7

Graphics Thermal Power Managemen t .................................................................. 61

Thermal Managemen t .............................................................................................. 63

Signal Description ................................................................................................... 65

System Memory Interface Signals........................................................................ 66

Memory Reference and Compensation Signal s ....................................................... 67

Reset and Miscellaneous Signal s .......................................................................... 68

PCI Express*-based Interface Signals .................................................................. 69

Intel Flexible Display (Intel FDI) Interface Signals ............................................. 69

Direct Media Interface (DMI) Signals.................................................................... 70

Phase Lock Loop (PLL) Signals ............................................................................ 70

Test Access Points (TAP) Signals ......................................................................... 70

Error and Thermal Protection Signals ................................................................... 71

6.10 Power Sequencing Signals .................................................................................. 72

6.11 Processor Power Signal s ..................................................................................... 73

6.12 Sense Signals ................................................................................................... 73

6.13 Ground and Non-Critical to Function (NCTF) Signal s ............................................... 74

6.14 Processor Internal Pull-Up / Pull-Down Resistors.................................................... 74

Electrical Specification s ........................................................................................... 75

7.1

7.2

Power and Ground Lands.................................................................................... 75

Decoupling Guideline s ........................................................................................ 75

7.2.1 Voltage Rail Decoupling........................................................................... 75

Processor Clocking (BCLK[0], BCLK#[0]).............................................................. 76

7.3.1 Phase Lock Loop (PLL) Power Supply......................................................... 76

VCC Voltage Identification (VID).......................................................................... 76

System Agent (SA) V VID................................................................................ 80

Reserved or Unused Signals................................................................................ 80

Datasheet, Volume 1

7.7

7.8

7.9

Signal Groups ...................................................................................................80

Test Access Port (TAP) Connection .......................................................................82

Storage Conditions Specifications.........................................................................83

7.10 DC Specification s ...............................................................................................84

7.10.1 Voltage and Current Specification s ............................................................84

7.11 Platform Environmental Control Interface (PECI) DC Specification s ...........................90

7.11.1 PECI Bus Architecture..............................................................................90

7.11.2 DC Characteristics ..................................................................................91

7.11.3 Input Device Hysteresi s ...........................................................................91

Processor Land and Signal Information ....................................................................93

8.1

Processor Land Assignments ...............................................................................93

DDR Data Swizzling ................................................................................................1 09

Figures

1-1 Desktop Processor Platform......................................................................................10

1-2 Desktop Processor Compatibility Diagram ..................................................................18

2-1 Intel Flex Memory Technology Operation .................................................................26

2-2 PCI Express* Layering Diagra m ................................................................................28

2-3 Packet Flow Through the Layers ...............................................................................29

2-4 PCI Express* Related Register Structures in the Processor ...........................................30

2-5 PCI Express* Typical Operation 16 Lanes Mapping ......................................................31

2-6 Processor Graphics Controller Unit Block Diagram .......................................................33

2-7 Processor Display Block Diagram ..............................................................................36

4-1 Processor Power States ...........................................................................................47

4-2 Idle Power Management Breakdown of the Processor Core s ..........................................51

4-3 Thread and Core C-State Entry and Exit.....................................................................51

4-4 Package C-State Entry and Exit ................................................................................55

7-1 Example for PECI Host-Clients Connection..................................................................90

7-2 Input Device Hysteresi s ...........................................................................................91

8-1 LGA Socket Land Map..............................................................................................94

Tables

1-1 Desktop 3rd Generation Intel Core™ Processor Family, Desktop Intel



Pentium Processor Family, and Desktop Intel Celeron Processor Family SKUs...........16

1-2 Terminology...........................................................................................................19

2-1 Processor DIMM Support Summary by Product ...........................................................23

2-2 Supported UDIMM Module Configurations...................................................................24

2-3 Supported SO-DIMM Module Configurations (AIO Only)................................................24

2-4 System Memory Timing Suppor t ...............................................................................25

2-5 Reference Clock......................................................................................................38

4-1 System States........................................................................................................48

4-2 Processor Core / Package State Support ....................................................................48

4-3 Integrated Memory Controller State s .........................................................................48

4-4 PCI Express* Link States .........................................................................................49

4-5 Direct Media Interface (DMI) States ..........................................................................49

4-6 Processor Graphics Controller States .........................................................................49

4-7 G, S, and C State Combinations................................................................................49

4-8 Coordination of Thread Power States at the Core Level ................................................51

4-9 P_LVLx to MWAIT Conversio n ...................................................................................52

4-10 Coordination of Core Power States at the Package Level ..............................................54

6-1 Signal Description Buffer Types ................................................................................65

Datasheet, Volume 1



6-2 Memory Channel A Signals ...................................................................................... 66

6-3 Memory Channel B Signals ...................................................................................... 67

6-4 Memory Reference and Compensation....................................................................... 67

6-5 Reset and Miscellaneous Signals............................................................................... 68

6-6 PCI Express* Graphics Interface Signals.................................................................... 69

6-7 Intel Flexible Display (Intel FDI) Interface............................................................. 69

6-8 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interfac e ....................... 70

6-9 Phase Lock Loop (PLL) Signals ................................................................................. 70

6-10 Test Access Points (TAP) Signals .............................................................................. 70

6-11 Error and Thermal Protection Signals ........................................................................ 71

6-12 Power Sequencing Signal s ....................................................................................... 72

6-13 Processor Power Signals.......................................................................................... 73

6-14 Sense Signal s ........................................................................................................ 73

6-15 Ground and Non-Critical to Function (NCTF) Signal s .................................................... 74

6-16 Processor Internal Pull-Up / Pull-Down Resistors......................................................... 74

7-1 VR 12.0 Voltage Identification Definition.................................................................... 77

7-2 Signal Groups 1 ..................................................................................................... 81

7-3 Storage Condition Ratings ....................................................................................... 83

7-4 Processor Core Active and Idle Mode DC Voltage and Current Specification s ................... 84

7-5 Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications........... 86

7-6 Processor Graphics VID based (V

) Supply DC Voltage and Current Specifications........ 87

AXG

7-7 DDR3 Signal Group DC Specifications........................................................................ 87

7-8 Control Sideband and TAP Signal Group DC Specifications ........................................... 89

7-9 PCI Express* DC Specifications ................................................................................ 89

7-10 PECI DC Electrical Limits ......................................................................................... 91

8-1 Processor Land List by Land Name............................................................................ 95

9-1 DDR Data Swizzling Table – Channel A .................................................................... 110

9-2 DDR Data Swizzling table – Channel B .................................................................... 111

Datasheet, Volume 1

Revision History

Revision

Number

Description

Revision Date

001

• Initial release

April 2012

June 2012

• Added Desktop 3rd Generation Intel^®Core™ i5-3470T, i5-3470, i5-3470S,

i5-3475S, i5-3570, i5-3570S processors

002

003

• Updated Section 1.2.2, PCI Express*

• Updated Section 2.1.1, System Memory Technology Supported

June 2012

• Updated Table 7-4, “Processor Core Active and Idle Mode DC Voltage and

Current Specifications”. Added 65 W to 2011C.

• Minor edits throughout for clarity

• Added Intel Pentium G2120 and G2100T processors

• Added Desktop 3rd Generation Intel^®Core™ i3-3220, i3-3220T, i3-3225, i3-

3240, i3-3240T, i5-3330, i5-3330S, i5-3335S, i5-3350P processors

004

September 2012

• Added Desktop 3rd Generation Intel^®Core™ i3-3210 processor

• Added Desktop Intel^®Pentium^®G2130, G2020, G2020T, G2010 processor

• Added Desktop Intel^®Celeron^®G1620, G1610, G1610T processor

• Added Desktop 3rd Generation Intel^®Core™ i3-3250, i3-3250T, i3-3245

processor

• Added Desktop Intel^®Pentium^®G2140, G2120T, G2030, G2030T processor

005

006

January 2013

June 2013

• Added Desktop 3rd Generation Intel^®Core™ i5-3340, i5-3340S processor

• Added Desktop Intel^®Celeron^®G1630, G1620, G1620T processor

007

008

September 2013

November 2013

• Added Desktop Intel Pentium Processor A1018

§ §

Datasheet, Volume 1

Introduction

1 Introduction

The Desktop 3rd Generation Intel Core™ processor family, Desktop Intel Pentium

processor family, and Desktop Intel Celeron processor family are the next

generation of 64-bit, multi-core processors built on 22-nanometer process technology.

The processors are designed for a two-chip platform. The two-chip platform consists of

a processor and a Platform Controller Hub (PCH) and enables higher performance,

lower cost, easier validation, and improved x-y footprint. The processor includes an

Integrated Display Engine, Processor Graphics, PCI Express ports, and an Integrated

Memory Controller. The processor is designed for desktop platforms. The processor

offers either 6 or 16 graphic execution units (EUs). The number of EU engines

supported may vary between processor SKUs. The processor is offered in an 1155-land

LGA package (H2). Figure 1-1 shows an example desktop platform block diagram.

The Datasheet provides DC specifications, pinout and signal definitions, interface

functional descriptions, and additional feature information pertinent to the

implementation and operation of the processor on its respective platform.

Note:

Throughout this document, the Intel 6 / 7 Series Chipset Platform Controller Hub may

be referred to as “PCH”.

Throughout this document, the Desktop 3rd Generation Intel Core™ processor family,

Desktop Intel Pentium processor family, and Desktop Intel Celeron processor

family may be referred to simply as “processor”.

Note:

Throughout this document, the Desktop 3rd Generation Intel Core™ processor family,

Desktop Intel Pentium processor family, and Desktop Intel Celeron processor

family refer to the processor SKUs listed in T a ble 1-1.

Note:

Some processor features are not available on all platforms. Refer to the processor

specification update for details.

The term “DT” refers to desktop platforms.

Datasheet, Volume 1

Introduction

Figure 1-1. Desktop Processor Platform

PCI Express* 3.0

1 x16 or 2x8

DDR3

PECI

Discrete

Graphics (PEG)

Intel^®

Processor

Intel^®

Displ

ay Inter

face

Flexible

DMI2 x4

Serial ATA

Intel^®

Management

Engine

Digital Display x 3

Analog CRT

USB 2.0 / USB 3.0¹

Intel^®HD Audio

Intel^®6/7 Series

Chipset Families

SPI Flash x 2

FWH

SMBUS 2.0

SPI

Controller Link 1

PCI Express*

WiFi / WiMax

LPC

8 PCI Express* 2.0

x1 Ports

Gigabit

Network Connection

Super I/O

(5 GT/s)

GPIO

Note:

1. USB 3.0 is supported on the Intel^®7 Series Chipset family only.

Datasheet, Volume 1

Introduction

1.1

Processor Feature Details

• Four or two execution cores

• A 32-KB instruction and 32-KB data first-level cache (L1) for each core

• A 256-KB shared instruction / data second-level cache (L2) for each core

• Up to 8-MB shared instruction / data third-level cache (L3), shared among all cores

1.1.1

Supported Technologies

• Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d)

• Intel Virtualization Technology (Intel VT) for IA-32, Intel 64 and Intel

Architecture (Intel VT-x)

Intel Active Management Technology (Intel AMT) 8.0

• Intel Trusted Execution Technology (Intel TXT)

• Intel Streaming SIMD Extensions 4.1 (Intel SSE4.1)

• Intel Streaming SIMD Extensions 4.2 (Intel SSE4.2)

• Intel Hyper-Threading Technology (Intel HT Technology)

• Intel 64 Architecture

• Execute Disable Bit

• Intel Turbo Boost Technology

• Intel Advanced Vector Extensions (Intel AVX)

• Intel Advanced Encryption Standard New Instructions (Intel AES-NI)

• PCLMULQDQ Instruction

• RDRAND instruction for random number generation

• SMEP – Supervisor Mode Execution Protection

• PAIR – Power Aware Interrupt Routing

1.2

Interfaces

1.2.1

System Memory Support

• Two channels of DDR3 Unbuffered Dual In-Line Memory Modules (UDIMM) or DDR3

Unbuffered Small Outline Dual In-Line Memory Modules (SO-DIMM) with a

maximum of two DIMMs per channel

• Single-channel and dual-channel memory organization modes

• Data burst length of eight for all memory organization modes

• Memory DDR3 data transfer rates of 1333 MT/s and 1600 MT/s. The DDR3 data

transfer rates supported by the processor is dependent on the PCH SKU in the

target platform:

— Desktop PCH platforms support 1333 MT/s and 1600 MT/s for One DIMM and

Two DIMMs per channel

— All In One platforms (AIO) support 1333 MT/s and 1600 MT/s for One DIMM

and Two DIMMs per channel

• 64-bit wide channels

• System Memory Interface I/O Voltage of 1.5 V

• DDR3 and DDR3L DIMMs/DRAMs running at 1.5 V

• No support for DDR3L DIMMs/DRAMS running at 1.35 V

Datasheet, Volume 1

Introduction

• Support memory configurations that mix DDR3 DIMMs/DRAMs with DDR3L

DIMMs/DRAMs running at 1.5 V

• The type of the DIMM modules supported by the processor is dependent on the PCH

SKU in the target platform:

— Desktop PCH platforms support non-ECC UDIMMs only

— All In One platforms (AIO) support SO-DIMMs

• Theoretical Maximum Memory Bandwidth:

— 10.6 GB/s in single-channel mode or 21.3 GB/s in dual-channel mode assuming

DDR3 1333 MT/s

— 12.8 GB/s in single-channel mode or 25.6 GB/s in dual-channel mode assuming

DDR3 1600 MT/s

• Processor on-die Reference Voltage (VREF) generation for both DDR3 Read

(RDVREF) and Write (VREFDQ)

• 1Gb, 2Gb, and 4Gb DDR3 DRAM device technologies are supported

— Using 4Gb DRAM device technologies, the largest memory capacity possible is

32 GB, assuming Dual Channel Mode with four x8 dual ranked DIMM memory

configuration

• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank

devices)

• Command launch modes of 1N/2N

• On-Die Termination (ODT)

• Asynchronous ODT

• Intel Fast Memory Access (Intel FMA):

— Just-in-Time Command Scheduling

— Command Overlap

— Out-of-Order Scheduling

1.2.2

PCI Express*

• The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI

Express Base Specification, Revision 3.0, including support for 8.0 GT/s transfer

speeds.

• Processor with Desktop PCH Supports (may vary depending on PCH SKUs)

• PCI Express* supported configurations in desktop products

Configuration

Organization

Desktop

1x8

2x4

Graphics, I/O

2x8

Graphics, I/O

1x16

• The port may negotiate down to narrower widths

— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode

• 2.5 GT/s, 5.0 GT/s and 8.0 GT/s PCI Express* frequencies are supported

• Gen1 Raw bit-rate on the data pins Gen 2 Raw bit-rate on the data pins of 5.0 GT/s,

resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used

Datasheet, Volume 1

Introduction

to transmit data across this interface. This also does not account for packet

overhead and link maintenance.

• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction

simultaneously, for an aggregate of 16 GB/s when x16 Gen 2

• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per

pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.

This also does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on the interface of 16 GB/s in each direction

simultaneously, for an aggregate of 32 GB/s when x16 Gen 3

• Hierarchical PCI-compliant configuration mechanism for downstream devices

• Traditional PCI style traffic (asynchronous snooped, PCI ordering)

• PCI Express* extended configuration space. The first 256 bytes of configuration

space aliases directly to the PCI Compatibility configuration space. The remaining

portion of the fixed 4-KB block of memory-mapped space above that (starting at

100h) is known as extended configuration space.

• PCI Express* Enhanced Access Mechanism. Accessing the device configuration

space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset

• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)

• Peer segment destination posted write traffic (no peer-to-peer read traffic) in

Virtual Channel 0:

— DMI -> PCI Express* Port 0

• 64-bit downstream address format; however, the processor never generates an

address above 64 GB (Bits 63:36 will always be zeros)

• 64-bit upstream address format; however, the processor responds to upstream

read transactions to addresses above 64 GB (addresses where any of Bits 63:36

are nonzero) with an Unsupported Request response. Upstream write transactions

to addresses above 64 GB will be dropped.

• Re-issues Configuration cycles that have been previously completed with the

Configuration Retry status

• PCI Express* reference clock is 100-MHz differential clock

• Power Management Event (PME) functions

• Dynamic width capability

• Message Signaled Interrupt (MSI and MSI-X) messages

• Polarity inversion

Note:

The processor does not support PCI Express* Hot-Plug.

Datasheet, Volume 1

Introduction

1.2.3

Direct Media Interface (DMI)

• DMI 2.0 support

• Four lanes in each direction

• 5 GT/s point-to-point DMI interface to PCH is supported

• Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per pair of

500 MB/s given the 8b/10b encoding used to transmit data across this interface.

Does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on interface of 2 GB/s in each direction

simultaneously, for an aggregate of 4 GB/s when DMI x4

• Shares 100-MHz PCI Express* reference clock

• 64-bit downstream address format; however, the processor never generates an

address above 64 GB (Bits 63:36 will always be zeros)

• 64-bit upstream address format, but the processor responds to upstream read

transactions to addresses above 64 GB (addresses where any of Bits 63:36 are

nonzero) with an Unsupported Request response. Upstream write transactions to

addresses above 64 GB will be dropped.

• Supports the following traffic types to or from the PCH:

— DMI -> DRAM

— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)

— Processor core -> DMI

• APIC and MSI interrupt messaging support:

— Message Signaled Interrupt (MSI and MSI-X) messages

• Downstream SMI, SCI and SERR error indication

• Legacy support for ISA regime protocol (PHOLD / PHOLDA) required for parallel

port DMA, floppy drive, and LPC bus masters

• DC coupling – no capacitors between the processor and the PCH

• Polarity inversion

• PCH end-to-end lane reversal across the link

• Supports Half Swing “low-power / low-voltage”

1.2.4

1.2.5

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a

PECI client (the processor) and a PECI master. The processor supports the PECI 3.0

Specification.

Processor Graphics

• The Processor Graphics contains a refresh of the seventh generation graphics core

enabling substantial gains in performance and lower power consumption. Up to

16 EU support.

• Next Generation Intel Clear Video Technology HD Support is a collection of video

playback and enhancement features that improve the end user’s viewing

experience

— Encode / transcode HD content

— Playback of high definition content including Blu-ray Disc*

— Superior image quality with sharper, more colorful images

— Playback of Blu-ray Disc* S3D content using HDMI* (V.1.4 with 3D)

Datasheet, Volume 1

Introduction

• DirectX* Video Acceleration (DXVA) support for accelerating video processing

— Full AVC/VC1/MPEG2 HW Decode

• Advanced Scheduler 2.0, 1.0, XPDM support

• Windows* 7, Windows* XP, OSX, Linux OS Support

• DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support

• OpenGL* 3.0 support

• Switchable Graphics support on Desktop AIO platforms with MxM solutions only

1.2.6

Intel Flexible Display Interface (Intel FDI)

• For SKUs with graphics, carries display traffic from the Processor Graphics in the

processor to the legacy display connectors in the PCH

• Based on DisplayPort standard

• The two Intel FDI links are capable of being configured to support three

independent channels, one for each display pipeline

• There are two Intel FDI channels, each one consists of four unidirectional

downstream differential transmitter pairs:

— Scalable down to 3X, 2X, or 1X based on actual display bandwidth

requirements

— Fixed frequency 2.7 GT/s data rate

• Two sideband signals for display synchronization:

— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)

• One Interrupt signal used for various interrupts from the PCH:

— FDI_INT signal shared by both Intel FDI Links

• PCH supports end-to-end lane reversal across both links

• Common 100-MHz reference clock

1.3

Power Management Support

1.3.1

Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states:

— C0, C1, C1E, C3, C6

• Enhanced Intel SpeedStep Technology

1.3.2

1.3.3

System

• S0, S3, S4, S5

Memory Controller

• Conditional self-refresh (Intel Rapid Memory Power Management (Intel RMPM))

• Dynamic power down

1.3.4

PCI Express*

• L0s and L1 ASPM power management capability

Datasheet, Volume 1

Introduction

1.3.5

1.3.6

Direct Media Interface (DMI)

• L0s and L1 ASPM power management capability

Processor Graphics Controller (GT)

• Intel Rapid Memory Power Management (Intel RMPM) – CxSR

• Intel Graphics Performance Modulation Technology (Intel GPMT)

• Intel Smart 2D Display Technology (Intel S2DDT)

• Graphics Render C-State (RC6)

1.3.7

Thermal Management Support

• Digital Thermal Sensor

• Intel Adaptive Thermal Monitor

• THERMTRIP# and PROCHOT# support

• On-Demand Mode

• Memory Thermal Throttling

• External Thermal Sensor (TS-on-DIMM and TS-on-Board)

• Render Thermal Throttling

• Fan speed control with DTS

1.4

Processor SKU Definitions

Table 1-1.

Desktop 3rd Generation Intel Core™ Processor Family, Desktop Intel



Pentium Processor Family, and Desktop Intel Celeron Processor Family

SKUs (Sheet 1 of 2)

Processor

Number

TDP

(W)

IA LFM

Frequency

jMAX

(°C)

IA Frequency range

GT Frequency range

i7-3770T

i7-3770S

i7-3770K

i7-3770

1600 MHz

2.5 GHz up to 3.7 GHz

3.1 GHz up to 3.9 GHz

3.5 GHz up to 3.9 GHz

3.4 GHz up to 3.9 GHz

2.3 GHz up to 3.3 GHz

3.1 GHz up to 3.8 GHz

3.4 GHz up to 3.8 GHz

3 GHz up to 3.7 GHz

3.3 GHz up to 3.7 GHz

2.9 GHz up to 3.6 GHz

3.2 GHz up to 3.6 GHz

2.8 GHz up to 3.5 GHz

3.1 GHz up to 3.5 GHz

3.1 GHZ up to 3.3 GHZ

650 MHz up to 1150 MHz

650 MHz up to 1100 MHz

650 MHz up to 1100 MHz,

650 MHz up to 1100 MHz

N/A

103

105

i5-3570T

i5-3570S

i5-3570K

i5-3570

103

105

103

105

103

i5-3550S

i5-3550

i5-3475S

i5-3470S

i5-3470T

i5-3470

105

103

105

i5-3450S

i5-3450

i5-3350P

i5-3340

650 MHz up to 1050 MHz

Datasheet, Volume 1

Introduction

Table 1-1.

Desktop 3rd Generation Intel Core™ Processor Family, Desktop Intel



Pentium Processor Family, and Desktop Intel Celeron Processor Family

SKUs (Sheet 2 of 2)

Processor

Number

TDP

(W)

IA LFM

Frequency

jMAX

(°C)

IA Frequency range

GT Frequency range

i5-3340S

i5-3335S

i5-3330S

i3-3250T

i3-3250

i3-3245

i5-3330

i3-3240T

i3-3240

i3-3225

i3-3220T

i3-3220

i3-3210

G2140

1600 MHz

3.0 GHZ up to 3.3 GHZ

2.7 GHz up to 3.2 GHz

N/A

650 MHz up to 1050 MHz

650 MHZ up to 1.05 GHZ

650 MHz up to 1050 MHz

650 MHZ up to 1050 MHz

650 MHz up to 1 GHz

103

N/A

105

N/A

3 GHz up to 3.2 GHz

Up to 3.0 GHz

Up to 3.4 GHz

Up to 3.3 GHz

Up to 2.8 GHz

Up to 3.3 GHz

Up to 3.2 GHz

N/A

105

G2130

Up to 3.2 GHz

N/A

G2120T

G2120

3.1 GHZ

105

G2100T

G2030T

G2030

2.6 GHZ

N/A

105

G2020

2.9 GHZ

G2020T

G2010

2.5 GHZ

2.8 GHZ

105

G1630

2.8 GHZ

G1620

2.7 GHZ

G1620T

G1610

2.4 GHZ

2.6 GHZ

105

G1610T

A1018

2.3 GHZ

2.1 GHz

105

1.5

Package

The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip

Chip Land Grid Array (FCLGA 1155). See the Desktop 3rd Generation Intel Core™

Processor Family, Desktop Intel Pentium Processor Family, Desktop Intel Celeron

Processor Family, and LGA1155 Socket Thermal / Mechanical Specifications and Design

Guidelines for complete details on the package.

Datasheet, Volume 1

Introduction

1.6

Processor Compatibility

The Desktop 3rd Generation Intel Core™ processor family, Desktop Intel Pentium

processor family, Desktop Intel Celeron processor Family has specific platform

requirements that differentiate it from a 2nd Generation Intel Core™ processor family

Desktop, Intel Pentium processor family Desktop, Intel Celeron processor Family

Desktop processor. Platforms intending to support both processor families need to

address the platform compatibility requirements detailed in Figure 1-2.

Figure 1-2. Desktop Processor Compatibility Diagram

VCCIO

VDDQ

VCore

VAXG

VCCSA

*VAXG: 2 ph required for

some of the SKUs

2 x 330 µF

2 x 330 µF +

1 placeholder

DDR3

PEG AC Decoupling

PEG Gen 1,2 – 100 nF

PEG Gen 1,2,3 – 220 nF

G2_Core: 1.5 V

G3_Core: 1.5 V

G2_Core: 1.05 V

G3_Core: 1.05 V

G2_Core: 0.925 V

G3_Core: 0.925 V

Processor

VCCSA_VID

G2_Core: ‘0’

G3_Core: ‘0’

VCCIO_SEL#

G2_Core: ‘1’

G3_Core: ‘1’

PROC_SELECT#

G2_Core: ‘1’

G3_Core: ‘0’

Controls DMI

And FDI

termination

PCH

DF_TVS

Notes:

G2_Core = 2nd Generation Intel Core™ processor family Desktop, Intel Pentium processor

family Desktop, Intel Celeron processor family Desktop,

G3_Core = Desktop 3rd Generation Intel Core™ processor family, Desktop Intel Pentium

processor, Desktop Intel Celeron processor family

Datasheet, Volume 1

Introduction

1.7

Terminology

Table 1-2.

Terminology (Sheet 1 of 3)

Term

Description

Advanced Configuration and Power Interface

ACPI

ADB

Automatic Display Brightness

Active Power Down

APD

ASPM

BGA

Active State Power Management

Ball Grid Array

BLT

Block Level Transfer

CLTT

Closed Loop Thermal Throttling

Cathode Ray Tube

CRT

cTDP

DDDR3L-RS

DDR3

DDR3L

DMA

Configurable Thermal Design Power

DDR3L Reduced Standby Power

Third-generation Double Data Rate SDRAM memory technology

DDR3 Low Voltage

Direct Memory Access

DMI

Direct Media Interface

DisplayPort*

DPST

DTS

Display Power Savings Technology

Digital Thermal Sensor

Embedded Controller

ECC

Error Correction Code

eDP*

Embedded DisplayPort*

Enhanced Intel

SpeedStep

Technology

Technology that provides power management capabilities to laptops.

EPG

Electrical Power Gating

Execution Unit

The Execute Disable bit allows memory to be marked as executable or non-executable,

when combined with a supporting operating system. If code attempts to run in non-

executable memory the processor raises an error to the operating system. This feature

can prevent some classes of viruses or worms that exploit buffer overrun

Execute Disable Bit

vulnerabilities and can thus help improve the overall security of the system. See the

Intel 64 and IA-32 Architectures Software Developer's Manuals for more detailed

information.

HDMI*

HFM

High Definition Multimedia Interface

High Frequency Mode

IMC

Integrated Memory Controller

Intel 64 Technology 64-bit memory extensions to the IA-32 architecture

Intel DPST

Intel Display Power Saving Technology

Intel FDI

Intel Flexible Display Interface

Intel TXT

Intel Trusted Execution Technology

Processor virtualization which when used in conjunction with Virtual Machine Monitor

software enables multiple, robust independent software environments inside a single

platform.

Intel Virtualization

Technology

Datasheet, Volume 1

Introduction

Table 1-2.

Terminology (Sheet 2 of 3)

Term

Description

Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware

assist, under system software (Virtual Machine Manager or operating system) control,

for enabling I/O device virtualization. Intel VT-d also brings robust security by

providing protection from errant DMAs by using DMA remapping, a key feature of Intel

VT-d.

Intel VT-d

IOV

ISA

I/O Virtualization

Industry Standard Architecture. This is a legacy computer bus standard for IBM PC

compatible computers.

ITPM

LCD

LFM

LPC

Integrated Trusted Platform Module

Liquid Crystal Display

Low Frequency Mode

Low Pin Count

LPM

Low Power Mode

Low Voltage Differential Signaling. A high speed, low power data transmission

standard used for display connections to LCD panels.

LVDS

MLE

MSI

Measured Launched Environment

Message Signaled Interrupt

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical

reserved, so the loss of the solder joint continuity at end of life conditions will not

affect the overall product functionality.

NCTF

ODT

On-Die Termination

PAIR

Power Aware Interrupt Routing

Platform Controller Hub. The chipset with centralized platform capabilities including the

main I/O interfaces along with display connectivity, audio features, power

management, manageability, security and storage features.

PCH

PECI

PEG

Platform Environment Control Interface.

PCI Express* Graphics. External Graphics using PCI Express* Architecture. A high-

speed serial interface whose configuration is software compatible with the existing PCI

specifications.

PGA

Pin Grid Array

PLL

Phase Lock Loop

PME

Power Management Event

Precharged Power Down

PPD

Processor

The 64-bit, single-core or multi-core component (package).

The term “processor core” refers to Si die itself that can contain multiple execution

cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache.

All execution cores share the L3 cache.

Processor Core

Processor Graphics

Intel Processor Graphics

A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These

devices are usually, but not always, mounted on a single side of a SO-DIMM.

Rank

SCI

System Control Interrupt. Used in ACPI protocol.

Intel SDRRS

Technology

Intel Seamless Display Refresh Rate Switching Technology

SMEP

Supervisor Mode Execution Protection

Datasheet, Volume 1

Introduction

Table 1-2.

Terminology (Sheet 3 of 3)

Term

Description

A non-operational state. The processor may be installed in a platform, in a tray, or

loose. Processors may be sealed in packaging or exposed to free air. Under these

conditions, processor landings should not be connected to any supply voltages, have

any I/Os biased or receive any clocks. Upon exposure to “free air” (that is, unsealed

packaging or a device removed from packaging material) the processor must be

handled in accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

Storage Conditions

SVID

TAC

TAP

TCC

TDC

TDP

TLP

Serial Voltage IDentification interface

Thermal Averaging Constant

Test Access Point

Thermal Control Circuit

Thermal Design Current

Thermal Design Power

Transaction Layer Packet

Graphics core power supply

Processor core power supply

High Frequency I/O logic power supply

PLL power supply

AXG

CCIO

CCPLL

System Agent (memory controller, DMI, PCIe controllers, and display engine) power

supply

CCSA

DDQ

DDR3 power supply

VGA

VID

VLD

VLW

Video Graphics Array

Voltage Identification

Variable Length Decoding

Virtual Legacy Wire

Voltage Regulator

Processor ground

VTS

Virtual Temperature Sensor

Refers to a Link or Port with one Physical Lane.

Refers to a Link or Port with sixteen Physical Lanes.

Refers to a Link or Port with four Physical Lanes.

Refers to a Link or Port with eight Physical Lanes.

x16

Datasheet, Volume 1

Introduction

1.8

Related Documents

Document Number /

Document

Location

Desktop 3rd Generation Intel Core™ Processor Family, Desktop Intel

Pentium Processor Family, and Desktop Intel Celeron Processor Family

Datasheet, Volume 2

326765

Desktop 3rd Generation Intel Core™ Processor Family, Desktop Intel

Pentium Processor Family, and Desktop Intel Celeron Processor Family

Specification Update

326766

Desktop 3rd Generation Intel Core™ Processor Family, Desktop Intel

Pentium Processor Family, Desktop Intel Celeron Processor Family, and

LGA1155 Socket Thermal / Mechanical Specifications and Design Guidelines

326767

Advanced Configuration and Power Interface Specification 3.0

PCI Local Bus Specification 3.0

http://www.acpi.info/

http://www.pcisig.com/speci

fications

PCI Express* Base Specification 2.0

DDR3 SDRAM Specification

DisplayPort* Specification

http://www.pcisig.com

http://www.jedec.org

http://www.vesa.org

Intel 64 and IA-32 Architectures Software Developer's Manuals

http://www.intel.com/produ

cts/processor/manuals/inde

x.htm

Volume 1: Basic Architecture

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

Note: Contact your Intel representative for the latest revision of this item.

§ §

Datasheet, Volume 1

Interfaces

2 Interfaces

This chapter describes the interfaces supported by the processor.

2.1

System Memory Interface

2.1.1

System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3 / DDR3L protocols with two

independent, 64-bit wide channels, each accessing one or two DIMMs. The type of

memory supported by the processor is dependant on the PCH SKU in the target

platform. Refer to Chapter 1 for supported memory configuration details.

Note:

The processor supports only JEDEC approved memory modules and devices.

The IMC supports a maximum of two DIMMs per channel; thus, allowing up to four

device ranks per channel.

Note:

The supported memory interface frequencies and number of DIMMs per channel are

SKU dependent.

Table 2-1.

Processor DIMM Support Summary by Product

Processor

cores

DIMMper

channel

Package

DIMM type

SO-DIMM

UDIMM

DDR3

DDR3L at 1.5 V

1 DPC

2 DPC

1 DPC

2 DPC

1333/1600

1333,1600

1333/1600

Dual Core,

Quad Core

uLGA

Dual Core,

Quad Core

uLGA

Note: There is no support for DDR3L DIMMs/DRAMS running at 1.35 V.

• DDR3 / DDR3L at 1.5 V Data Transfer Rates

— 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)

• DDR3 / DDR3L at 1.5 V SO-DIMM Modules

— Raw Card A – Dual Ranked x16 unbuffered non-ECC

— Raw Card B – Single Ranked x8 unbuffered non-ECC

— Raw Card C – Single Ranked x16 unbuffered non-ECC

— Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC

• Desktop platform DDR3/DDR3L at 1.5 V UDIMM Modules

— Raw Card A – Single Ranked x8 unbuffered non-ECC

— Raw Card B – Dual Ranked x8 unbuffered non-ECC

— Raw Card C – Single Ranked x16 unbuffered non-ECC

Note:

The processor supports memory configurations that mix DDR3 DIMMs / DRAMs with

DDR3L DIMMs / DRAMs running at 1.5 V.

Datasheet, Volume 1

Interfaces

Table 2-2.

Supported UDIMM Module Configurations

# of

Physical

Device

Ranks

# of

Raw

Card

Version

DRAM

Device

Technology

# of

DRAM

Devices

DIMM

Capacity

DRAM

Organization

Row/Col Banks Page

Address Inside

Bits

Size

DRAM

Desktop Platforms:

Unbuffered/Non-ECC Supported DIMM Module Configurations

1 GB

2 GB

4 GB

2 GB

4 GB

8 GB

1 GB

1 Gb

2 Gb

4 Gb

1 Gb

2 Gb

4 Gb

2 Gb

128 M X 8

128 M X 16

512 M X 8

128 M X 8

256 M X 8

512 M X 8

128 M X 16

14/10

1510

15/10

14/10

15/10

16/10

14/10

16K

Note:

DIMM module support is based on availability and is subject to change.

Table 2-3.

Supported SO-DIMM Module Configurations (AIO Only)

# of

Row/Col

Address

Bits

# of

Raw

Card

Version

DRAM

Device

Technology

# of

DRAM

Devices

DIMM

Capacity

DRAM

Organization

Physical

Device

Ranks

Banks

Inside

DRAM

Page

Size

2 GB

4 GB

1 GB

2 GB

4 GB

1 GB

2 GB

4 GB

8 GB

2 Gb

4 Gb

1 Gb

2 Gb

4 Gb

2 Gb

4 Gb

1 Gb

2 Gb

4 Gb

128 M x 16

256 M x 16

128 M x 8

256 M x 8

512 M x 8

128 M x 16

256 M x 16

128 M x 8

256 M x 8

512 M x 8

14/10

15/10

14/10

15/10

16/10

14/10

15/10

14/10

15/10

16/ 10

Note:

System memory configurations are based on availability and are subject to change.

2.1.2

System Memory Timing Support

The IMC supports the following Speed Bins, CAS Write Latency (CWL), and command

signal mode timings on the main memory interface:

• tCL = CAS Latency

• tRCD = Activate Command to READ or WRITE Command delay

• tRP = PRECHARGE Command Period

• CWL = CAS Write Latency

• Command Signal modes = 1N indicates a new command may be issued every clock

and 2N indicates a new command may be issued every 2 clocks. Command launch

mode programming depends on the transfer rate and memory configuration.

Datasheet, Volume 1

Interfaces

Table 2-4.

System Memory Timing Support

Transfer

tCL

tRCD

(tCK)

tRP

(tCK)

CWL

(tCK)

CMD

Mode

Segment

Rate

DPC

Notes

(tCK)

(MT/s)

1N/2N

1333

1600

Desktop

1N/2N

1333

1600

AIO

1N/2N

Note:

1. System memory timing support is based on availability and is subject to change.

2.1.3

2.1.3.1

2.1.3.2

System Memory Organization Modes

The IMC supports two memory organization modes, single-channel and dual-channel.

Depending upon how the DIMM Modules are populated in each memory channel, a

number of different configurations can exist.

Single-Channel Mode

In this mode, all memory cycles are directed to a single-channel. Single-channel mode

is used when either Channel A or Channel B DIMM connectors are populated in any

order, but not both.

Dual-Channel Mode – Intel Flex Memory Technology Mode

The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a

symmetric and a asymmetric zone. The symmetric zone starts at the lowest address in

each channel and is contiguous until the asymmetric zone begins or until the top

address of the channel with the smaller capacity is reached. In this mode, the system

runs with one zone of dual-channel mode and one zone of single-channel mode,

simultaneously, across the whole memory array.

Note:

Channels A and B can be mapped for physical channel 0 and 1 respectively or vice

versa; however, channel A size must be greater or equal to channel B size.

Datasheet, Volume 1

Interfaces

Figure 2-1. Intel Flex Memory Technology Operation

T O M

N o n in terleaved

access

D u al chan n el

in terleaved access

C H A

C H B

C H A and C H B can be configured to be physical channels 0 or 1

B – The largest physical m em ory am ount of the sm aller size m em ory m odule

C – T he rem aining physical m em ory am ount of the larger size m em ory m odule

2.1.3.2.1

Dual-Channel Symmetric Mode

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum

performance on real world applications. Addresses are ping-ponged between the

channels after each cache line (64-byte boundary). If there are two requests, and the

second request is to an address on the opposite channel from the first, that request can

be sent before data from the first request has returned. If two consecutive cache lines

are requested, both may be retrieved simultaneously, since they are ensured to be on

opposite channels. Use Dual-Channel Symmetric mode when both Channel A and

Channel B DIMM connectors are populated in any order, with the total amount of

memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary

between the dual channel zone and the single channel zone is the top of memory, the

IMC operates completely in Dual-Channel Symmetric mode.

Note:

The DRAM device technology and width may vary from one channel to the other.

2.1.4

Rules for Populating Memory Slots

In all System Memory Organization Modes, the frequency and latency timings of the

system memory is the lowest supported frequency and slowest supported latency

timings of all memory DIMM modules placed in the system, as determined through the

SPD registers.

Note:

In a Two DIMM Per Channel (2DPC) daisy chain layout memory configuration, the

furthest DIMM from the processor of any given channel must always be populated first.

Datasheet, Volume 1

Interfaces

2.1.5

Technology Enhancements of Intel Fast Memory Access

(Intel FMA)

The following sections describe the Just-in-Time Scheduling, Command Overlap, and

Out-of-Order Scheduling Intel FMA technology enhancements.

2.1.5.1

Just-in-Time Command Scheduling

The memory controller has an advanced command scheduler where all pending

requests are examined simultaneously to determine the most efficient request to be

issued next. The most efficient request is picked from all pending requests and issued

to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,

instead of having all memory access requests go individually through an arbitration

mechanism forcing requests to be executed one at a time, they can be started without

interfering with the current request allowing for concurrent issuing of requests. This

allows for optimized bandwidth and reduced latency while maintaining appropriate

command spacing to meet system memory protocol.

2.1.5.2

2.1.5.3

Command Overlap

Command Overlap allows the insertion of the DRAM commands between the Activate,

Precharge, and Read/Write commands normally used, as long as the inserted

commands do not affect the currently executing command. Multiple commands can be

issued in an overlapping manner, increasing the efficiency of system memory protocol.

Out-of-Order Scheduling

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,

the IMC continuously monitors pending requests to system memory for the best use of

bandwidth and reduction of latency. If there are multiple requests to the same open

page, these requests would be launched in a back to back manner to make optimum

use of the open memory page. This ability to reorder requests on the fly allows the IMC

to further reduce latency and increase bandwidth efficiency.

2.1.6

2.1.7

Data Scrambling

The memory controller incorporates a DDR3 Data Scrambling feature to minimize the

impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the

data bus. Past experience has demonstrated that traffic on the data bus is not random.

Rather, it can have energy concentrated at specific spectral harmonics creating high

di/dt that is generally limited by data patterns that excite resonance between the

package inductance and on die capacitances. As a result the memory controller uses a

data scrambling feature to create pseudo-random patterns on the DDR3 data bus to

reduce the impact of any excessive di/dt.

DDR3 Reference Voltage Generation

The processor memory controller has the capability of generating the DDR3 Reference

Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The

generated VREF can be changed in small steps, and an optimum VREF value is

determined for both during a cold boot through advanced DDR3 training procedures in

order to provide the best voltage and signal margins.

Datasheet, Volume 1

Interfaces

2.2

PCI Express* Interface

This section describes the PCI Express interface capabilities of the processor. See the

PCI Express Base Specification for details of PCI Express.

The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1

for details.

2.2.1

PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing

applications and drivers may operate unchanged.

The PCI Express configuration uses standard mechanisms as defined in the PCI

Plug-and-Play specification. The processor external graphics ports support Gen 3 speed

as well. At 8 GT/s, Gen 3 operation results in twice as much bandwidth per lane as

compared to Gen 2 operation. The 16-lane PCI Express* graphics port can operate at

either 2.5 GT/s, 5 GT/s, or 8 GT/s.

PCI Express* Gen 3 uses a 128/130b encoding scheme, eliminating nearly all of the

overhead of the 8b/10b encoding scheme used in Gen 1 and Gen 2 operation.

The PCI Express architecture is specified in three layers – Transaction Layer, Data Link

Layer, and Physical Layer. The partitioning in the component is not necessarily along

these same boundaries. Refer to Figure 2-2 for the PCI Express layering diagram.

Figure 2-2. PCI Express* Layering Diagram

Transaction

Data Link

Physical

Logical Sub-block

Electrical Sub-block

PCI Express uses packets to communicate information between components. Packets

are formed in the Transaction and Data Link Layers to carry the information from the

transmitting component to the receiving component. As the transmitted packets flow

through the other layers, they are extended with additional information necessary to

handle packets at those layers. At the receiving side, the reverse process occurs and

packets get transformed from their Physical Layer representation to the Data Link

Layer representation and finally (for Transaction Layer Packets) to the form that can be

processed by the Transaction Layer of the receiving device.

Datasheet, Volume 1

Interfaces

Figure 2-3. Packet Flow Through the Layers

Sequence

Number

Framing

Header

Data

ECRC

LCRC

Framing

Transaction Layer

Data Link Layer

Physical Layer

2.2.1.1

2.2.1.2

Transaction Layer

The upper layer of the PCI Express* architecture is the Transaction Layer. The

Transaction Layer's primary responsibility is the assembly and disassembly of

Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as

read and write, as well as certain types of events. The Transaction Layer also manages

flow control of TLPs.

Data Link Layer

The middle layer in the PCI Express stack, the Data Link Layer, serves as an

intermediate stage between the Transaction Layer and the Physical Layer.

Responsibilities of Data Link Layer include link management, error detection, and error

correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the

Transaction Layer, calculates and applies data protection code and TLP sequence

number, and submits them to Physical Layer for transmission across the Link. The

receiving Data Link Layer is responsible for checking the integrity of received TLPs and

for submitting them to the Transaction Layer for further processing. On detection of TLP

error(s), this layer is responsible for requesting retransmission of TLPs until information

is correctly received, or the Link is determined to have failed. The Data Link Layer also

generates and consumes packets which are used for Link management functions.

2.2.1.3

Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and

input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), clock recovery

circuits and impedance matching circuitry. It also includes logical functions related to

interface initialization and maintenance. The Physical Layer exchanges data with the

Data Link Layer in an implementation-specific format, and is responsible for converting

this to an appropriate serialized format and transmitting it across the PCI Express Link

at a frequency and width compatible with the remote device.

Datasheet, Volume 1

Interfaces

2.2.2

PCI Express* Configuration Mechanism

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge

structure.

Figure 2-4. PCI Express* Related Register Structures in the Processor

PCI-PCI Bridge

representing

root PCI

Express* ports

(Device 1 and

Device 6)

PCI Compatible

Host Bridge

Device

PCI

Express*

Device

PEG0

(Device 0)

DMI

PCI Express extends the configuration space to 4096 bytes per-device/function, as

compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express

configuration space is divided into a PCI-compatible region (that consists of the first

256 bytes of a logical device's configuration space) and an extended PCI Express region

(that consists of the remaining configuration space). The PCI-compatible region can be

accessed using either the mechanisms defined in the PCI specification or using the

enhanced PCI Express configuration access mechanism described in the PCI Express

Enhanced Configuration Mechanism section.

The PCI Express Host Bridge is required to translate the memory-mapped PCI Express

configuration space accesses from the host processor to PCI Express configuration

cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is

recommended that system software access the enhanced configuration space using

32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for

details of both the PCI-compatible and PCI Express Enhanced configuration

mechanisms and transaction rules.

Datasheet, Volume 1

Interfaces

2.2.3

PCI Express* Port

The PCI Express interface on the processor is a single, 16-lane (x16) port that can also

be configured at narrower widths. The PCI Express port is being designed to be

compliant with the PCI Express Base Specification, Revision 3.0.

2.2.3.1

PCI Express* Lanes Connection

Figure 2-5 demonstrates the PCIe lanes mapping.

Figure 2-5. PCI Express* Typical Operation 16 Lanes Mapping

Lane 0

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Lane 9

Lane 10

Lane 11

Lane 12

Lane 13

Lane 14

Lane 15

Datasheet, Volume 1

Interfaces

2.3

Direct Media Interface (DMI)

Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI

2.0 is supported.

Note:

Only DMI x4 configuration is supported.

2.3.1

DMI Error Flow

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or

GPE. Any DMI related SERR activity is associated with Device 0.

2.3.2

2.3.3

Processor / PCH Compatibility Assumptions

The processor is compatible with the Intel 7 Series Chipset PCH products.

DMI Link Down

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to

data link down, after the link was up, then the DMI link hangs the system by not

allowing the link to retrain to prevent data corruption. This link behavior is controlled

by the PCH.

Downstream transactions that had been successfully transmitted across the link prior

to the link going down may be processed as normal. No completions from downstream,

non-posted transactions are returned upstream over the DMI link after a link down

event.

Datasheet, Volume 1

Interfaces

2.4

Processor Graphics Controller (GT)

New Graphics Engine Architecture includes 3D compute elements, Multi-format

hardware assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior

high definition playback, video quality, and improved 3D performance and Media.

The Display Engine handles delivering the pixels to the screen, and is the primary

channel interface for display memory accesses and “PCI-like” traffic in and out.

Figure 2-6. Processor Graphics Controller Unit Block Diagram

VS/GS

Setup/Rasterize

Hierachical Z

Vertex

Fetch

Hardware Clipper

Unified Execution Unit Array

Texture

Unit

Pixel

Backend

Additional Post Processing

Multi-Format Decode/Encode

Full MPEG2, VC1, AVC Decode

Fixed Function Post Processing

Full AVC Encode

Partial MPEG2, VC1 Encode

2.4.1

3D and Video Engines for Graphics Processing

The 3D graphics pipeline architecture simultaneously operates on different primitives or

on different portions of the same primitive. All the cores are fully programmable,

increasing the versatility of the 3D Engine. The Gen 7.0 3D engine provides the

following performance and power-management enhancements:

• Up to 16 Execution units (EUs)

• Hierarchal-Z

• Video quality enhancements

2.4.1.1

3D Engine Execution Units

• Supports up to 16 EUs. The EUs perform 128-bit wide execution per clock

• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel

processing

Datasheet, Volume 1

Interfaces

2.4.1.2

3D Pipeline

2.4.1.2.1

Vertex Fetch (VF) Stage

The VF stage executes 3DPRIMITIVE commands. Some enhancements have been

included to better support legacy D3D APIs as well as SGI OpenGL*.

2.4.1.2.2

2.4.1.2.3

Vertex Shader (VS) Stage

The VS stage performs shading of vertices output by the VF function. The VS unit

produces an output vertex reference for every input vertex reference received from the

VF unit, in the order received.

Geometry Shader (GS) Stage

The GS stage receives inputs from the VS stage. Compiled application-provided GS

programs, specifying an algorithm to convert the vertices of an input object into some

output primitives. For example, a GS shader may convert lines of a line strip into

polygons representing a corresponding segment of a blade of grass centered on the

line. Or it could use adjacency information to detect silhouette edges of triangles and

output polygons extruding out from the edges.

2.4.1.2.4

2.4.1.2.5

2.4.1.2.6

Clip Stage

The Clip stage performs general processing on incoming 3D objects. However, it also

includes specialized logic to perform a Clip Test function on incoming objects. The Clip

Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming

vertices, and accepts/rejects 3D objects based on its Clip algorithm.

Strips and Fans (SF) Stage

The SF stage performs setup operations required to rasterize 3D objects. The outputs

from the SF stage to the Windower stage contain implementation-specific information

required for the rasterization of objects and also supports clipping of primitives to some

extent.

Windower/IZ (WIZ) Stage

The WIZ unit performs an early depth test, which removes failing pixels and eliminates

unnecessary processing overhead.

The Windower uses the parameters provided by the SF unit in the object-specific

rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of

pixels. The Windower is also capable of performing dithering, whereby the illusion of a

higher resolution when using low-bpp channels in color buffers is possible. Color

dithering diffuses the sharp color bands seen on smooth-shaded objects.

2.4.1.3

Video Engine

The video engine is part of the Intel Processor Graphics for image processing, play-

back and transcode of Video applications. The Processor Graphics video engine has a

dedicated fixed hardware pipe-line for high quality decode and encode of media

content. This engine supports Full hardware acceleration for decode of AVC/H.264, 

VC-1 and MPEG -2 contents along with encode of MPEG-2 and AVC/H.264 apart from

various video processing features. The new Processor Graphics Video engine adds

support for processing features such as frame rate conversion, image stabilization, and

gamut conversion.

Datasheet, Volume 1

Interfaces

2.4.1.4

2D Engine

The Display Engine fetches the raw data from the memory, puts the data into a stream,

converts the data into raw pixels, organizes pixels into images, blends different planes

into a single image, encodes the data, and sends the data out to the display device.

The Display Engine executes its functions with the help of three main functional blocks

– Planes, Pipes, and Ports, except for eDP. The Planes and Pipes are in the processor

while the Ports reside in the PCH. Intel FDI connects the display engine in the processor

with the Ports in the PCH. The 2D Engine adds a new display pipe C that enables

support for three simultaneous and concurrent display configurations.

2.4.1.4.1

2.4.1.4.2

Processor Graphics Registers

The 2D registers consists of original VGA registers and others to support graphics

modes that have color depths, resolutions, and hardware acceleration features that go

beyond the original VGA standard.

Logical 128-Bit Fixed BLT and 256 Fill Engine

This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The

128-bit BLT engine provides hardware acceleration of block transfers of pixel data for

many common Windows operations. The BLT engine can be used for the following:

• Move rectangular blocks of data between memory locations

• Data alignment

• To perform logical operations (raster ops)

The rectangular block of data does not change, as it is transferred between memory

locations. The allowable memory transfers are between cacheable system memory and

frame buffer memory, frame buffer memory and frame buffer memory, and within

system memory. Data to be transferred can consist of regions of memory, patterns, or

solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per

pixel.

The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs

can be either opaque or transparent. Opaque transfers move the data specified to the

destination. Transparent transfers compare destination color to source color and write

according to the mode of transparency selected.

Data is horizontally and vertically aligned at the destination. If the destination for the

BLT overlaps with the source memory location, the BLT engine specifies which area in

memory to begin the BLT transfer. Hardware is included for all 256 raster operations

(source, pattern, and destination) defined by Microsoft, including transparent BLT.

The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting

software to set up instruction buffers and use batch processing. The BLT engine can

perform hardware clipping during BLTs.

Datasheet, Volume 1

Interfaces

2.4.2

Processor Graphics Display

The Processor Graphics controller display pipe can be broken down into three

components:

• Display Planes

• Display Pipes

• DisplayPort* and Intel FDI

Figure 2-7. Processor Display Block Diagram

VGA

Pipe A

Plane

Panel

Fitting

Transcoder

Memory

Host

FDI 0

(Tx side)

Interface

(Outside of

Display

Pipe B

Plane

Panel

Fitting

Transcoder

Cross

Point

Mux

Engine)

FDI 1

(Tx side)

Pipe C

Plane

Panel

Fitting

Transcoder

2.4.2.1

Display Planes

A display plane is a single displayed surface in memory and contains one image

(desktop, cursor, overlay). It is the portion of the display hardware logic that defines

the format and location of a rectangular region of memory that can be displayed on

display output device and delivers that data to a display pipe. This is clocked by the

Core Display Clock.

2.4.2.1.1

Primary Planes A, B, and C

Planes A, B, and C are the main display planes and are associated with Pipes A, B, and

C respectively.

2.4.2.1.2

2.4.2.1.3

Sprite A, B, and C

Sprite A and Sprite B are planes optimized for video decode, and are associated with

Planes A and B respectively. Sprite A and B are also double-buffered.

Cursors A, B, and C

Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,

and are associated with Planes A and B respectively. These planes support resolutions

up to 256 x 256 each.

2.4.2.1.4

Video Graphics Array (VGA)

VGA is used for boot, safe mode, legacy games, and so on. It can be changed by an

application without operating system/driver notification, due to legacy requirements.

Datasheet, Volume 1

Interfaces

2.4.2.2

Display Pipes

The display pipe blends and synchronizes pixel data received from one or more display

planes and adds the timing of the display output device upon which the image is

displayed.

The display pipes A, B, and C operate independently of each other at the rate of 1 pixel

per clock. They can attach to any of the display ports. Each pipe sends display data to

eDP* or to the PCH over the Intel Flexible Display Interface (Intel FDI).

2.4.2.3

Display Ports

The display ports consist of output logic and pins that transmit the display data to the

associated encoding logic and send the data to the display device (that is, LVDS,

HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are

now repartitioned and driven from the PCH. Refer to the PCH datasheet for more details

on display port support.

2.4.3

Intel Flexible Display Interface (Intel FDI)

Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display

traffic from the Processor Graphics controller to the PCH display I/Os. Intel FDI

supports two or three independent channels – one for pipe A, one for pipe B, and one

for Pipe C.

Channels A and B have a maximum of four transmit (Tx) differential pairs used for

transporting pixel and framing data from the display engine in two display

configurations. In three display configurations Channel A has 4 transmit (Tx)

differential pairs while Channel B and C have two transmit (Tx) differential pairs.

• Each channel has four transmit (Tx) differential pairs used for transporting pixel

and framing data from the display engine

• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS

signaling)

• One display interrupt line input (1-V CMOS signaling)

• Intel FDI may dynamically scale down to 2X or 1X based on actual display

bandwidth requirements

• Common 100-MHz reference clock

• Each channel transports at a rate of 2.7 Gbps

• PCH supports end-to-end lane reversal across both channels (no reversal support

required in the processor)

2.4.4

Multi Graphics Controllers Multi-Monitor Support

The processor supports simultaneous use of the Processor Graphics Controller (GT) and

a x16 PCI Express* Graphics (PEG) device.

The processor supports a maximum of 2 displays connected to the PEG card in parallel

with up to 2 displays connected to the processor and PCH.

Note:

When supporting Multi Graphics Multi Monitors, “drag and drop” between monitors and

the 2x8 PEG is not supported.

Datasheet, Volume 1

Interfaces

2.5

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a

PECI client (processor) and a PECI master. The processor implements a PECI interface

to:

• Allow communication of processor thermal and other information to the PECI

master.

• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

2.6

Interface Clocking

2.6.1

Internal Clocking Requirements

Table 2-5.

Reference Clock

Reference Input Clock

BCLK[0]/BCLK#[0]

Input Frequency

100 MHz

Associated PLL

Processor/Memory/Graphics/PCIe/DMI/FDI

§ §

Datasheet, Volume 1

Technologies

3 Technologies

This chapter provides a high-level description of Intel technologies implemented in the

processor.

The implementation of the features may vary between the processor SKUs.

Details on the different technologies of Intel processors and other relevant external

notes are located at the Intel technology web site: http://www.intel.com/technology/.

3.1

Intel^®Virtualization Technology (Intel^®VT)

Intel Virtualization Technology (Intel VT) makes a single system appear as multiple

independent systems to software. This allows multiple, independent operating systems

to run simultaneously on a single system. Intel VT comprises technology components

to support virtualization of platforms based on Intel architecture microprocessors and

chipsets. Intel Virtualization Technology for IA-32, Intel 64 and Intel Architecture

(Intel VT-x) added hardware support in the processor to improve the virtualization

performance and robustness. Intel Virtualization Technology for Directed I/O (Intel VT-

d) adds chipset hardware implementation to support and improve I/O virtualization

performance and robustness.

Intel VT-x specifications and functional descriptions are included in the Intel 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:

http://www.intel.com/products/processor/manuals/index.htm

Other Intel VT documents can be referenced at:

http://www.intel.com/technology/virtualization/index.htm

3.1.1

Intel Virtualization Technology (Intel VT) for

IA-32, Intel 64 and Intel Architecture 

(Intel VT-x) Objectives

Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual

Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable

virtualized platform. By using Intel VT-x, a VMM is:

• Robust: VMMs no longer need to use paravirtualization or binary translation. This

means that they will be able to run off-the-shelf operating systems and applications

without any special steps.

• Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86

processors.

• More reliable: Due to the hardware support, VMMs can now be smaller, less

complex, and more efficient. This improves reliability and availability and reduces

the potential for software conflicts.

• More secure: The use of hardware transitions in the VMM strengthens the isolation

of VMs and further prevents corruption of one VM from affecting others on the

same system.

Datasheet, Volume 1

Technologies

3.1.2

Intel Virtualization Technology (Intel VT) for

IA-32, Intel 64 and Intel Architecture 

(Intel VT-x) Features

The processor core supports the following Intel VT-x features:

• Extended Page Tables (EPT)

— EPT is hardware assisted page table virtualization

— It eliminates VM exits from guest operating system to the VMM for shadow

page-table maintenance

• Virtual Processor IDs (VPID)

— Ability to assign a VM ID to tag processor core hardware structures (such as

TLBs)

— This avoids flushes on VM transitions to give a lower-cost VM transition time

and an overall reduction in virtualization overhead

• Guest Preemption Timer

— Mechanism for a VMM to preempt the execution of a guest operating system

after an amount of time specified by the VMM. The VMM sets a timer value

before entering a guest.

— The feature aids VMM developers in flexibility and Quality of Service (QoS)

guarantees

• Descriptor-Table Exiting

— Descriptor-table exiting allows a VMM to protect a guest operating system from

internal (malicious software based) attack by preventing relocation of key

system data structures like IDT (interrupt descriptor table), GDT (global

descriptor table), LDT (local descriptor table), and TSS (task segment selector)

— A VMM using this feature can intercept (by a VM exit) attempts to relocate

these data structures and prevent them from being tampered by malicious

software

3.1.3

Intel Virtualization Technology (Intel VT) for Directed

I/O (Intel VT-d) Objectives

The key Intel VT-d objectives are domain-based isolation and hardware-based

virtualization. A domain can be abstractly defined as an isolated environment in a

platform to which a subset of host physical memory is allocated. Virtualization allows

for the creation of one or more partitions on a single system. This could be multiple

partitions in the same operating system, or there can be multiple operating system

instances running on the same system – offering benefits such as system

consolidation, legacy migration, activity partitioning, or security.

Datasheet, Volume 1

Technologies

3.1.4

Intel Virtualization Technology (Intel VT) for Directed

I/O (Intel VT-d) Features

The processor supports the following Intel VT-d features:

• Memory controller and processor graphics comply with Intel VT-d 1.2 specification

• Two VT-d DMA remap engines:

— iGFX DMA remap engine

— DMI / PEG

• Support for root entry, context entry, and default context

• 39-bit guest physical address and host physical address widths

• Support for 4K page sizes only

• Support for register-based fault recording only (for single entry only) and support

for MSI interrupts for faults

• Support for both leaf and non-leaf caching

• Support for boot protection of default page table

• Support for non-caching of invalid page table entries

• Support for hardware based flushing of translated but pending writes and pending

reads, on IOTLB invalidation

• Support for page-selective IOTLB invalidation

• MSI cycles (MemWr to address FEEx_xxxxh) not translated

— Translation faults result in cycle forwarding to VBIOS region (byte enables

masked for writes). Returned data may be bogus for internal agents, PEG / DMI

interfaces return unsupported request status.

• Interrupt Remapping is supported

• Queued invalidation is supported

• VT-d translation bypass address range is supported (Pass Through)

Note:

Intel VT-d Technology may not be available on all SKUs.

3.1.5

Intel Virtualization Technology (Intel VT) for Directed

I/O (Intel VT-d) Features Not Supported

The following features are not supported by the processor with Intel VT-d:

• No support for PCIe* endpoint caching (ATS)

• No support for Intel VT-d read prefetching / snarfing (that is, translations within a

cacheline are not stored in an internal buffer for reuse for subsequent translations)

• No support for advance fault reporting

• No support for super pages

• No support for Intel VT-d translation bypass address range (such usage models

need to be resolved with VMM help in setting up the page tables correctly)

Datasheet, Volume 1

Technologies

3.2

Intel^®Trusted Execution Technology (Intel^®TXT)

Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements

that provide the building blocks for creating trusted platforms.

The Intel TXT platform helps to provide the authenticity of the controlling environment

such that those wishing to rely on the platform can make an appropriate trust decision.

The Intel TXT platform determines the identity of the controlling environment by

accurately measuring and verifying the controlling software.

Another aspect of the trust decision is the ability of the platform to resist attempts to

change the controlling environment. The Intel TXT platform will resist attempts by

software processes to change the controlling environment or bypass the bounds set by

the controlling environment.

Intel TXT is a set of extensions designed to provide a measured and controlled launch

of system software that will then establish a protected environment for itself and any

additional software that it may execute.

These extensions enhance two areas:

• The launching of the Measured Launched Environment (MLE)

• The protection of the MLE from potential corruption

The enhanced platform provides these launch and control interfaces using Safer Mode

Extensions (SMX).

The SMX interface includes the following functions:

• Measured / Verified launch of the MLE

• Mechanisms to ensure the above measurement is protected and stored in a secure

location

• Protection mechanisms that allow the MLE to control attempts to modify itself

For more information, refer to the Intel TXT Measured Launched Environment

Developer’s Guide in http://www.intel.com/content/www/us/en/software-

developers/intel-txt-software-development-guide.html.

3.3

Intel^®Hyper-Threading Technology (Intel^®HT

Technology)

The processor supports Intel Hyper-Threading Technology (Intel HT Technology)

that allows an execution core to function as two logical processors. While some

execution resources such as caches, execution units, and buses are shared, each

logical processor has its own architectural state with its own set of general-purpose

registers and control registers. This feature must be enabled using the BIOS and

requires operating system support.

Intel recommends enabling Intel HT Technology with Microsoft Windows 7*, Microsoft

Windows Vista*, Microsoft Windows* XP Professional / Windows* XP Home, and

disabling Intel HT Technology using the BIOS for all previous versions of Windows

operating systems. For more information on Intel HT Technology, see

http://www.intel.com/technology/platform-technology/hyper-threading/.

Datasheet, Volume 1

Technologies

3.4

Intel^®Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor core to

opportunistically and automatically run faster than its rated operating frequency/render

clock if it is operating below power, temperature, and current limits. The Intel Turbo

Boost Technology feature is designed to increase performance of both multi-threaded

and single-threaded workloads. Maximum frequency is dependant on the SKU and

number of active cores. No special hardware support is necessary for Intel Turbo Boost

Technology. BIOS and the operating system can enable or disable Intel Turbo Boost

Technology. Intel Turbo Boost Technology will increase the ratio of application power to

TDP. Thus, thermal solutions and platform cooling that are designed to less than

thermal design guidance might experience thermal and performance issues since more

applications will tend to run at the maximum power limit for significant periods of time.

Note:

Intel Turbo Boost Technology may not be available on all SKUs.

3.4.1

Intel Turbo Boost Technology Frequency

The processor’s rated frequency assumes that all execution cores are running an

application at the thermal design power (TDP). However, under typical operation, not

all cores are active. Therefore most applications are consuming less than the TDP at the

rated frequency. To take advantage of the available thermal headroom, the active cores

can increase their operating frequency.

To determine the highest performance frequency amongst active cores, the processor

takes the following into consideration:

• The number of cores operating in the C0 state

• The estimated current consumption

• The estimated power consumption

• The temperature

Any of these factors can affect the maximum frequency for a given workload. If the

power, current, or thermal limit is reached, the processor will automatically reduce the

frequency to stay with its TDP limit.

Note:

Intel Turbo Boost Technology processor frequencies are only active if the operating

system is requesting the P0 state. For more information on P-states and C-states, refer

to Chapter 4.

3.4.2

Intel Turbo Boost Technology Graphics Frequency

Graphics render frequency is selected by the processor dynamically based on graphics

workload demand. The processor can optimize both processor and Processor Graphics

performance by managing power for the overall package. For the integrated graphics,

this allows an increase in the render core frequency and increased graphics

performance for graphics intensive workloads. In addition, during processor intensive

workloads when the graphics power is low, the processor core can increase its

frequency higher within the package power limit. Enabling Intel Turbo Boost Technology

will maximize the performance of the processor core and the graphics render frequency

within the specified package power levels.

Datasheet, Volume 1

Technologies

3.5

Intel^®Advanced Vector Extensions (Intel^®AVX)

Intel Advanced Vector Extensions (Intel AVX) is the latest expansion of the Intel

instruction set. It extends the Intel Streaming SIMD Extensions (Intel SSE) from 128-

bit vectors to 256-bit vectors. Intel AVX addresses the continued need for vector

floating-point performance in mainstream scientific and engineering numerical

applications, visual processing, recognition, data-mining / synthesis, gaming, physics,

cryptography and other application areas.

The enhancement in Intel AVX allows for improved performance due to wider vectors,

new extensible syntax, and rich functionality including the ability to better manage,

rearrange, and sort data. In the processor, new instructions were added to allow

graphics, media and imaging applications to speed up the processing of large amount

of data by reducing the memory bandwidth and footprint. The new instructions convert

operands between single-precision floating point values and half-precision (16 bit)

floating point values.

For more information on Intel AVX, see http://www.intel.com/software/avx.

3.6

Security and Cryptography Technologies

3.6.1

Intel Advanced Encryption Standard New Instructions

(Intel AES-NI)

The processor supports Intel Advanced Encryption Standard New Instructions (Intel

AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that

enable fast and secure data encryption and decryption based on the Advanced

Encryption Standard (AES). Intel AES-NI are valuable for a wide range of cryptographic

applications, for example: applications that perform bulk encryption / decryption,

authentication, random number generation, and authenticated encryption. AES is

broadly accepted as the standard for both government and industry applications, and is

widely deployed in various protocols.

AES-NI consists of six Intel SSE instructions. Four instructions, namely AESENC,

AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and

decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key

expansion procedure. Together, these instructions provide a full hardware for support

AES, offering security, high performance, and a great deal of flexibility.

3.6.2

PCLMULQDQ Instruction

The processor supports the carry-less multiplication instruction, PCLMULQDQ.

PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the

128-bit carry-less multiplication of two, 64-bit operands without generating and

propagating carries. Carry-less multiplication is an essential processing component of

several cryptographic systems and standards. Hence, accelerating carry-less

multiplication can significantly contribute to achieving high speed secure computing

and communication.

Datasheet, Volume 1

Technologies

3.6.3

RDRAND Instruction

The processor introduces a software visible random number generation mechanism

supported by a high quality entropy source. This capability will be made available to

programmers through the new RDRAND instruction. The resultant random number

generation capability is designed to comply with existing industry standards in this

regard (ANSI X9.82 and NIST SP 800-90).

Some possible usages of the new RDRAND instruction include cryptographic key

generation as used in a variety of applications including communication, digital

signatures, secure storage, and so on.

3.7

Intel^®64 Architecture x2APIC

The Intel x2APIC architecture extends the xAPIC architecture that provides key

mechanism for interrupt delivery. This extension is intended primarily to increase

processor addressability.

Specifically, x2APIC:

• Retains all key elements of compatibility to the xAPIC architecture:

— delivery modes

— interrupt and processor priorities

— interrupt sources

— interrupt destination types

• Provides extensions to scale processor addressability for both the logical and

physical destination modes

• Adds new features to enhance performance of interrupt delivery

• Reduces complexity of logical destination mode interrupt delivery on link based

architectures

The key enhancements provided by the x2APIC architecture over xAPIC are the

following:

• Support for two modes of operation to provide backward compatibility and

extensibility for future platform innovations:

— In xAPIC compatibility mode, APIC registers are accessed through memory

mapped interface to a 4 KB page, identical to the xAPIC architecture.

— In x2APIC mode, APIC registers are accessed through Model Specific Register

(MSR) interfaces. In this mode, the x2APIC architecture provides significantly

increased processor addressability and some enhancements on interrupt

delivery.

• Increased range of processor addressability in x2APIC mode:

— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt

processor addressability up to 4 GB-1 processors in physical destination mode.

A processor implementation of x2APIC architecture can support fewer than

32 bits in a software transparent fashion.

— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC

ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID

within the cluster. Consequently, ((2^20) -16) processors can be addressed in

logical destination mode. Processor implementations can support fewer than

16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic

fashion.

Datasheet, Volume 1

Technologies

• More efficient MSR interface to access APIC registers.

— To enhance inter-processor and self directed interrupt delivery as well as the

ability to virtualize the local APIC, the APIC register set can be accessed only

through MSR based interfaces in the x2APIC mode. The Memory Mapped IO

(MMIO) interface used by xAPIC is not supported in the x2APIC mode.

• The semantics for accessing APIC registers have been revised to simplify the

programming of frequently-used APIC registers by system software. Specifically

the software semantics for using the Interrupt Command Register (ICR) and End Of

Interrupt (EOI) registers have been modified to allow for more efficient delivery

and dispatching of interrupts.

The x2APIC extensions are made available to system software by enabling the local

x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating

system and a new BIOS are both needed, with special support for the x2APIC mode.

The x2APIC architecture provides backward compatibility to the xAPIC architecture and

forward extendibility for future Intel platform innovations.

Note:

Intel x2APIC technology may not be available on all SKUs.

For more information, refer to the Intel 64 Architecture x2APIC specification at

http://www.intel.com/products/processor/manuals/

3.8

Supervisor Mode Execution Protection (SMEP)

The processor introduces a new mechanism that provides next level of system

protection by blocking malicious software attacks from user mode code when the

system is running in the highest privilege level.

This technology helps to protect from virus attacks and unwanted code to harm the

system.

For more information, please refer to the Intel 64 and IA-32 Architectures Software

Developer’s Manual, Volume 3A (see Section 1.8, “Related Documents” on page 22).

3.9

Power Aware Interrupt Routing (PAIR)

The processor added enhanced power-performance technology which routes interrupts

to threads or cores based on their sleep states. For example concerning energy

savings, it routes the interrupt to the active cores without waking the deep idle cores.

For Performance, it routes the interrupt to the idle (C1) cores without interrupting the

already heavily loaded cores. This enhancement is mostly beneficial for high interrupt

scenarios like Gigabit LAN, WLAN peripherals, and so on.

§ §

Datasheet, Volume 1

Power Management

4 Power Management

This chapter provides information on the following power management topics:

• Advanced Configuration and Power Interface (ACPI) States

• Processor Core

• Integrated Memory Controller (IMC)

• PCI Express*

• Direct Media Interface (DMI)

• Processor Graphics Controller

Figure 4-1. Processor Power States

G0 – Working

S0 – CPU Fully powered on

C0 – Active mode

C1 – Auto halt

C1E – Auto halt, low freq, low voltage

C3 – L1/L2 caches flush, clocks off

C6 – save core states before shutdown

G1 – Sleeping

S3 cold – Sleep – Suspend To Ram (STR)

S4 – Hibernate – Suspend To Disk (STD),

Wakeup on PCH

S5 – Soft Off – no power,

Wakeup on PCH

G3 – Mechanical Off

Note: Power states availability may vary between the different SKUs.

Datasheet, Volume 1

Power Management

4.1

Advanced Configuration and Power Interface

(ACPI) States Supported

The ACPI states supported by the processor are described in this section.

4.1.1

System States

Table 4-1.

System States

State

Description

G0/S0

Full On

Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the

processor).

G1/S3-Cold

G1/S4

G2/S5

Suspend-to-Disk (STD). All power lost (except wakeup on PCH).

Soft off. All power lost (except wakeup on PCH). Total reboot.

Mechanical off. All power removed from system.

4.1.2

Processor Core / Package Idle States

Table 4-2.

Processor Core / Package State Support

State

Description

Active mode, processor executing code

AutoHALT state

C1E

AutoHALT state with lowest frequency and voltage operating point

Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache

to the L3 shared cache. Clocks are shut off to each core

Execution cores in this state save their architectural state before removing core

voltage

4.1.3

Integrated Memory Controller States

Table 4-3.

Integrated Memory Controller States

State

Description

Power up

Pre-charge Power Down

Active Power Down

Self-Refresh

CKE asserted. Active mode.

CKE de-asserted (not self-refresh) with all banks closed

CKE de-asserted (not self-refresh) with minimum one bank active

CKE de-asserted using device self-refresh

Datasheet, Volume 1

Power Management

4.1.4

PCI Express* Link States

Table 4-4.

PCI Express* Link States

State

Description

L0s

Full on – Active transfer state.

First Active Power Management low power state – Low exit latency

Lowest Active Power Management – Longer exit latency

Lowest power state (power-off) – Longest exit latency

4.1.5

Direct Media Interface (DMI) States

Table 4-5.

Direct Media Interface (DMI) States

State

Description

L0s

Full on – Active transfer state

First Active Power Management low power state – Low exit latency

Lowest Active Power Management – Longer exit latency

Lowest power state (power-off) – Longest exit latency

4.1.6

Processor Graphics Controller States

Table 4-6.

Processor Graphics Controller States

State

Description

Full on, display active

Power-off

D3 Cold

4.1.7

Interface State Combinations

Table 4-7.

G, S, and C State Combinations

Processor

Package

Global (G)

State

Sleep

(S) State

Processor

State

System Clocks

Description

C1/C1E

Full On

Auto-Halt

Deep Sleep

Full On

Auto-Halt

Deep Sleep

Deep Power

Down

Deep Power Down

Power off

Off, except RTC

Power off

Suspend to RAM

Suspend to Disk

Soft Off

Hard off

Datasheet, Volume 1

Power Management

4.2

Processor Core Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s

frequency and core voltage based on workload. Each frequency and voltage operating

point is defined by ACPI as a P-state. When the processor is not executing code, it is

idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power

C-states have longer entry and exit latencies.

4.2.1

Enhanced Intel SpeedStep Technology

The following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple frequency and voltage points for optimal performance and power

efficiency. These operating points are known as P-states.

• Frequency selection is software controlled by writing to processor MSRs. The

voltage is optimized based on the selected frequency and the number of active

processor cores.

— If the target frequency is higher than the current frequency, V is ramped up

in steps to an optimized voltage. This voltage is signaled by the SVID bus to the

voltage regulator. Once the voltage is established, the PLL locks on to the

target frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

target frequency, then transitions to a lower voltage by signaling the target

voltage on SVID bus.

— All active processor cores share the same frequency and voltage. In a multi-

core processor, the highest frequency P-state requested amongst all active

cores is selected.

— Software-requested transitions are accepted at any time. If a previous

transition is in progress, the new transition is deferred until the previous

transition is completed.

• The processor controls voltage ramp rates internally to ensure glitch-free

transitions.

• Because there is low transition latency between P-states, a significant number of

transitions per-second are possible.

4.2.2

Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power.

More power savings actions are taken for numerically higher C-states. However, higher

C-states have longer exit and entry latencies. Resolution of C-states occur at the

thread, processor core, and processor package level. Thread-level C-states are

available if Intel HT Technology is enabled.

Caution:

Long term reliability cannot be assured unless all the Low Power Idle States are

enabled.

Datasheet, Volume 1

Power Management

Figure 4-2. Idle Power Management Breakdown of the Processor Cores

Thread 0 Thread 1

Core 0 State

Core 1 State

Processor Package State

Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.

Figure 4-3. Thread and Core C-State Entry and Exit

MWAIT(C1), HLT

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

MWAIT(C3),

P_LV2 I/O Read

C1E

While individual threads can request low power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

Table 4-8.

Coordination of Thread Power States at the Core Level

Thread 1

Processor Core

C-State

Thread 0

Note: If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher.

Datasheet, Volume 1

Power Management

4.2.3

Requesting Low-Power Idle States

The primary software interfaces for requesting low power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, software may make C-state requests using the legacy method of I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

method of requesting C-states provides legacy support for operating systems that

initiate C-state transitions using I/O reads.

To seamless support of legacy operating systems, P_LVLx I/O reads are converted

within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads

do not directly result in I/O reads to the system. The feature, known as I/O MWAIT

redirection, must be enabled in the BIOS.

Note:

The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read

interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in

T a ble 4-9.

Table 4-9.

P_LVLx to MWAIT Conversion

P_LVLx

MWAIT(Cx)

Notes

P_LVL2

P_LVL3

MWAIT(C3)

MWAIT(C6)

C6. No sub-states allowed.

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict

the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any

P_LVLx reads outside of this range does not cause an I/O redirection to an MWAIT(Cx)-

like request. They fall through like a normal I/O instruction.

Note:

When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The

MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O

redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on

an interrupt even if interrupts are masked by EFLAGS.IF.

4.2.4

Core C-states

The following are general rules for all core C-states, unless specified otherwise:

• A core C-State is determined by the lowest numerical thread state (such as Thread

0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See

T a ble 4-7.

• A core transitions to C0 state when:

— An interrupt occurs

— There is an access to the monitored address if the state was entered using an

MWAIT instruction

• For core C1/C1E, core C3, and core C6, an interrupt directed toward a single thread

wakes only that thread. However, since both threads are no longer at the same

core C-state, the core resolves to C0.

• A system reset re-initializes all processor cores

4.2.4.1

Core C0 State

The normal operating state of a core where code is being executed.

Datasheet, Volume 1

Power Management

4.2.4.2

Core C1 / C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or

MWAIT(C1/C1E) instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal

state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software

Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other

threads. For more information on C1E, see “Package C1/C1E”.

4.2.4.3

Core C3 State

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to

the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its

L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while

maintaining its architectural state. All core clocks are stopped at this point. Because the

core’s caches are flushed, the processor does not wake any core that is in the C3 state

when either a snoop is detected or when another core accesses cacheable memory.

4.2.4.4

4.2.4.5

Core C6 State

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an

MWAIT(C6) instruction. Before entering core C6, the core will save its architectural

state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero

volts. During exit, the core is powered on and its architectural state is restored.

C-State Auto-Demotion

In general, deeper C-states such as C6 have long latencies and have higher energy

entry / exit costs. The resulting performance and energy penalties become significant

when the entry / exit frequency of a deeper C-state is high. Therefore, incorrect or

inefficient usage of deeper C-states have a negative impact on idle power. To increase

residency and improve idle power in deeper C-states, the processor supports C-state

auto-demotion.

There are two C-State auto-demotion options:

• C6 to C3

• C6/C3 To C1

The decision to demote a core from C6 to C3 or C3/C6to C1 is based on each core’s

immediate residency history. Upon each core C6 request, the core C-state is demoted

to C3 or C1 until a sufficient amount of residency has been established. At that point, a

core is allowed to go into C3/C6. Each option can be run concurrently or individually.

This feature is disabled by default. BIOS must enable it in the

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by

this register.

Datasheet, Volume 1

Power Management

4.2.5

Package C-States

The processor supports C0, C1/C1E, C3, and C6 power states. The following is a

summary of the general rules for package C-state entry. These apply to all package C-

states unless specified otherwise:

• A package C-state request is determined by the lowest numerical core C-state

amongst all cores.

• A package C-state is automatically resolved by the processor depending on the

core idle power states and the status of the platform components.

— Each core can be at a lower idle power state than the package if the platform

does not grant the processor permission to enter a requested package C-state.

— The platform may allow additional power savings to be realized in the

processor.

— For package C-states, the processor is not required to enter C0 before entering

any other C-state.

The processor exits a package C-state when a break event is detected. Depending on

the type of break event, the processor does the following:

• If a core break event is received, the target core is activated and the break event

message is forwarded to the target core.

— If the break event is not masked, the target core enters the core C0 state and

the processor enters package C0.

• If the break event was due to a memory access or snoop request.

— But the platform did not request to keep the processor in a higher package C-

state, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or snoop

request is serviced and the package remains in the higher power C-state.

T a ble 4-10 shows package C-state resolution for a dual-core processor. Figure 4-4

summarizes package C-state transitions.

Table 4-10. Coordination of Core Power States at the Package Level

Core 1

Package C-State

Core 0

Note: If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.

Datasheet, Volume 1

Power Management

Figure 4-4. Package C-State Entry and Exit

4.2.5.1

4.2.5.2

Package C0

Package C0 is the normal operating state for the processor. The processor remains in

the normal state when at least one of its cores is in the C0 or C1 state or when the

platform has not granted permission to the processor to go into a low power state.

Individual cores may be in lower power idle states while the package is in C0.

Package C1/C1E

No additional power reduction actions are taken in the package C1 state. However, if

the C1E sub-state is enabled, the processor automatically transitions to the lowest

supported core clock frequency, followed by a reduction in voltage.

The package enters the C1 low power state when:

• At least one core is in the C1 state

• The other cores are in a C1 or lower power state

The package enters the C1E state when:

• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint

• All cores are in a power state lower that C1/C1E but the package low power state is

limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR

• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is

enabled in IA32_MISC_ENABLES

No notification to the system occurs upon entry to C1/C1E.

Datasheet, Volume 1

Power Management

4.2.5.3

Package C3 State

A processor enters the package C3 low power state when:

• At least one core is in the C3 state

• The other cores are in a C3 or lower power state, and the processor has been

granted permission by the platform

• The platform has not granted a request to a package C6 state but has allowed a

package C6 state

In package C3-state, the L3 shared cache is valid.

4.2.5.4

Package C6 State

A processor enters the package C6 low power state when:

• At least one core is in the C6 state

• The other cores are in a C6 or lower power state and the processor has been

granted permission by the platform

In package C6 state, all cores have saved their architectural state and have had their

core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable

in this state. The processor remains in package C6 state as long as any part of the L3

cache is active.

4.3

Integrated Memory Controller (IMC) Power

Management

The main memory is power managed during normal operation and in low-power ACPI

Cx states.

4.3.1

Disabling Unused System Memory Outputs

Any System Memory (SM) interface signal that goes to a memory module connector in

which it is not connected to any actual memory devices (such as SO-DIMM connector is

unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM

signals are:

• Reduced power consumption

• Reduced possible overshoot/undershoot signal quality issues seen by the processor

I/O buffer receivers caused by reflections from potentially un-terminated

transmission lines

When a given rank is not populated, the corresponding chip select and CKE signals are

not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are

not populated. This is due to the fact that when CKE is tri-stated with a SO-DIMM

present, the SO-DIMM is not ensured to maintain data integrity.

SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows

must be assumed to be populated.

Datasheet, Volume 1

Power Management

4.3.2

DRAM Power Management and Initialization

The processor implements extensive support for power management on the SDRAM

interface. There are four SDRAM operations associated with the Clock Enable (CKE)

signals that the SDRAM controller supports. The processor drives four CKE pins to

perform these operations.

The CKE is one means of power saving. When CKE is off, the internal DDR clock is

disabled and the DDR power is reduced. The power-saving differs according to the

selected mode and the DDR type used. For more information, refer to the IDD table in

the DDR specification.

The DDR defines 3 levels of power down that differ in power saving and in wakeup

time:

1. Active power down (APD): This mode is entered if there are open pages when de-

asserting CKE. In this mode the open pages are retained. Power-saving in this

mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this

mode is defined by tXP – small number of cycles.

2. Precharged power down (PPD): This mode is entered if all banks in DDR are

precharged when de-asserting CKE. Power-saving in this mode is intermediate –

better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.

Exiting this mode is defined by tXP. The difference relative to APD mode is that

when waking-up in PPD mode, all page-buffers are empty.

3. DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this mode is

the best among all power modes. Power consumption is defined by IDD2P1. Exiting

this mode is defined by tXP and tXPDLL (10–20 according to the DDR type) until

first data transfer is allowed.

The processor supports 6 different types of power down. The different modes are the

power down modes supported by DDR3 and combinations of these. The type of CKE

power down is defined by configuration. The options are as follows:

1. No power down

2. APD: The rank enters power down as soon as the idle-timer expires, independent of

the bank status

3. PPD: When idle timer expires, the MC sends PRE-all to rank and then enters power

down

4. DLL-off: Same as option 2 but DDR is configured to DLL-off

5. APD, change to PPD (APD-PPD): Begins as option 1, and when all page-close timers

of the rank are expired, it wakes the rank, issues PRE-all, and returns to PPD.

6. APD, change to DLL-off (APD_DLLoff): Begins as option 1, and when all page-close

timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to

DLL-off power down.

The CKE is determined per rank, when it is inactive. Each rank has an idle counter. The

idle counter starts counting as soon as the rank has no accesses, and if it expires, the

rank may enter power down while no new transactions to the rank arrive to queues.

The idle counter begins counting at the last incoming transaction arrival.

Datasheet, Volume 1

Power Management

It is important to understand that since the power down decision is per rank, the MC

can find a lot of opportunities to power down ranks, even while running memory

intensive applications; savings may be significant (up to a few Watts, depending on

DDR configuration). This becomes more significant when each channel is populated

with more ranks.

Selection of power modes should be according to power performance or thermal trade-

offs of a given system:

• When trying to achieve maximum performance and power or thermal consideration

is a non-issue, use no power down.

• In a system that tries to minimize power-consumption, try to use the deepest

power down mode possible – DLL-off or APD_DLLoff.

• In high-performance systems with dense packaging (that is, tricky thermal design)

the power down mode should be considered in order to reduce the heating and

avoid DDR throttling caused by the heating.

Control of the power-mode through CRB-BIOS: BIOS selects by default no-power

down.

Another control is the idle timer expiration count. This is set through PM_PDWN_config

bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the IMC will have

more opportunities to put DDR in power down. The minimum recommended value for

this register is 15. There is no BIOS hook to set this register. Customers who choose to

change the value of this register can do it by changing the BIOS. For experiments, this

Note:

In APD, APD-PPD, and APD-DLLoff there is no point in setting the idle counter in the

same range of page-close idle timer.

Another option associated with CKE power down is the S_DLL-off. When this option is

enabled, the SBR I/O slave DLLs go off when all channel ranks are in power down. (Do

not confuse it with the DLL-off mode, in which the DDR DLLs are off). This mode

requires an I/O slave DLL wakeup time be defined.

4.3.2.1

Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that has its level recognized

(other than the DDR3 reset pin) once power is applied. The signal must be driven LOW

by the DDR controller to make sure the SDRAM components float DQ and DQS during

power-up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a

configuration register. Using this method, CKE is ensured to remain inactive for much

longer than the specified 200 s after power and clocks to SDRAM devices are stable.

4.3.2.2

Conditional Self-Refresh

Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory

into self-refresh in the package C3 and C6 low-power states. Intel RMPM functionality

depends on graphics/display state (relevant only when processor graphics is being

used), as well as memory traffic patterns generated by other connected I/O devices.

When entering the S3 - Suspend-to-RAM (STR) state or S0 conditional self-refresh, the

processor core flushes pending cycles and then enters all SDRAM ranks into self

refresh. the CKE signals remain LOW so the SDRAM devices perform self-refresh.

Datasheet, Volume 1

Power Management

The target behavior is to enter self-refresh for the package C3 and C6 states as long as

there are no memory requests to service.

4.3.2.3

Dynamic Power Down Operation

Dynamic power down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power down state.

The processor core controller can be configured to put the devices in active power down

(CKE de-assertion with open pages) or precharge power down (CKE de-assertion with

all pages closed). Precharge power down provides greater power savings but has a

bigger performance impact, since all pages will first be closed before putting the

devices in power down mode.

If dynamic power down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of refresh.

4.3.2.4

DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.

Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-

DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the

input receiver (differential sense-amp) should be disabled, and any DLL circuitry

related ONLY to unused signals should be disabled. The input path must be gated to

prevent spurious results due to noise on the unused signals (typically handled

automatically when input receiver is disabled).

4.3.3

DDR Electrical Power Gating (EPG)

The DDR I/O of the processor supports on-die Electrical Power Gating (DDR-EPG)

during normal operation (S0 mode) while the processor is at package C3 or deeper

power state.

During EPG, the V

internal voltage rail will be powered down, while V

and the

CCIO

DDQ

un-gated V

will stay powered on.

CCIO

The processor will transition in and out of DDR EPG mode on an as needed basis

without any external pins or signals.

There is no change to the signals driven by the processor to the DIMMs during DDR IO

EPG mode.

During EPG mode, all the DDR IO logic will be powered down, except for the Physical

Control registers that are powered by the un-gated V

power supply.

CCIO

Unlike S3 exit, at DDR EPG exit, the DDR will not go through training mode. Rather, it

will use the previous training information retained in the physical control registers and

will immediately resume normal operation.

Datasheet, Volume 1

Power Management

4.4

PCI Express* Power Management

• Active power management support using L0s and L1 states.

• All inputs and outputs disabled in L2/L3 Ready state.

Note:

PCIe* interface does not support Hot-Plug.

An increase in power consumption may be observed when PCIe Active State Power

Management (ASPM) capabilities are disabled.

4.5

DMI Power Management

• Active power management support using L0s/L1 state.

4.6

Graphics Power Management

4.6.1

Intel Rapid Memory Power Management (Intel RMPM) 

(also known as CxSR)

The Intel Rapid Memory Power Management (Intel RMPM) puts rows of memory into

self-refresh mode during C3/C6 to allow the system to remain in the lower power states

longer. Processors routinely save power during runtime conditions by entering the C3,

C6 state. Intel RMPM is an indirect method of power saving that can have a significant

effect on the system as a whole.

4.6.2

Intel Graphics Performance Modulation Technology

(Intel GPMT)

Intel Graphics Power Modulation Technology (Intel GPMT) is a method for saving

power in the graphics adapter while continuing to display and process data in the

adapter. This method will switch the render frequency and/or render voltage

dynamically between higher and lower power states supported on the platform based

on render engine workload.

In products where Intel Graphics Dynamic Frequency (also known as Turbo Boost

Technology) is supported and enabled, the functionality of Intel GPMT will be

maintained by Intel Graphics Dynamic Frequency (also known as Turbo Boost

Technology).

4.6.3

Graphics Render C-State

Render C-State (RC6) is a technique designed to optimize the average power to the

graphics render engine during times of idleness of the render engine. Render C-state is

entered when the graphics render engine, blitter engine and the video engine have no

workload being currently worked on and no outstanding graphics memory transactions.

When the idleness condition is met then the Processor Graphics will program the VR

into a low voltage state (~0 V) through the SVID bus.

Caution:

Long term reliability cannot be assured unless all the Low Power Idle States are

enabled.

Datasheet, Volume 1

Power Management

4.6.4

Intel Smart 2D Display Technology (Intel S2DDT)

Intel S2DDT reduces display refresh memory traffic by reducing memory reads

required for display refresh. Power consumption is reduced by less accesses to the IMC.

S2DDT is only enabled in single pipe mode.

Intel S2DDT is most effective with:

• Display images well suited to compression, such as text windows, slide shows, and

so on. Poor examples are 3D games.

• Static screens such as screens with significant portions of the background showing

2D applications, processor benchmarks, and so on, or conditions when the

processor is idle. Poor examples are full-screen 3D games and benchmarks that flip

the display image at or near display refresh rates.

4.6.5

Intel Graphics Dynamic Frequency

Intel Graphics Dynamic Frequency Technology is the ability of the processor and

graphics cores to opportunistically increase frequency and/or voltage above the

ensured processor and graphics frequency for the given part. Intel Graphics Dynamic

Frequency Technology is a performance feature that makes use of unused package

power and thermals to increase application performance. The increase in frequency is

determined by how much power and thermal budget is available in the package, and

the application demand for additional processor or graphics performance. The

processor core control is maintained by an embedded controller. The graphics driver

dynamically adjusts between P-States to maintain optimal performance, power, and

thermals.

4.7

Graphics Thermal Power Management

See Section 4.6 for all graphics thermal power management-related features.

§ §

Datasheet, Volume 1

Power Management

Datasheet, Volume 1

Thermal Management

5 Thermal Management

For thermal specifications and design guidelines refer to the Desktop 3rd Generation

Intel Core™ Processor Family, Desktop Intel Pentium Processor, Desktop Intel

Celeron Processor, and LGA1155 Socket Thermal and Mechanical Specifications and

Design Guidelines.

§ §

Datasheet, Volume 1

Thermal Management

Datasheet, Volume 1

Signal Description

6 Signal Description

This chapter describes the processor signals. They are arranged in functional groups

according to their associated interface or category. The following notations are used to

describe the signal type.

Notations

Signal Type

Input Signal

Output Signal

I/O

Bi-directional Input/Output Signal

The signal description also includes the type of buffer used for the particular signal

(see T a ble 6-1).

Table 6-1.

Signal Description Buffer Types

Signal

Description

PCI Express* interface signals. These signals are compatible with PCI Express* 3.0

Signalling Environment AC Specifications and are AC coupled. The buffers are not 

3.3-V tolerant. Refer to the PCIe specification.

PCI Express*

Direct Media Interface signals. These signals are compatible with PCI Express* 2.0

Signaling Environment AC Specifications, but are DC coupled. The buffers are not 

3.3-V tolerant.

DMI

CMOS

DDR3

CMOS buffers.

DDR3 buffers: 1.5-V tolerant

Analog reference or output. May be used as a threshold voltage or for buffer

compensation

Ref

Voltage reference signal

Asynchronous

Signal has no timing relationship with any reference clock.

Note:

1. Qualifier for a buffer type.

Datasheet, Volume 1

Signal Description

6.1

System Memory Interface Signals

Table 6-2.

Memory Channel A Signals

Direction/

Buffer Type

Signal Name

Description

Bank Select: These signals define which banks are selected within

DDR3

SA_BS[2:0]

SA_WE#

each SDRAM rank.

Write Enable Control Signal: This signal is used with SA_RAS# and

SA_CAS# (along with SA_CS#) to define the SDRAM Commands.

DDR3

RAS Control Signal: This signal is used with SA_CAS# and SA_WE#

DDR3

SA_RAS#

SA_CAS#

(along with SA_CS#) to define the SRAM Commands.

CAS Control Signal: This signal is used with SA_RAS# and SA_WE#

(along with SA_CS#) to define the SRAM Commands.

DDR3

Data Strobes: SA_DQS[8:0] and its complement signal group make

up a differential strobe pair. The data is captured at the crossing point

of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write

transactions.

I/O

DDR3

SA_DQS[8:0]

SA_DQS#[8:0]

Data Bus: Channel A data signal interface to the SDRAM data bus.

I/O

DDR3

SA_DQ[63:0]

SA_MA[15:0]

Memory Address: These signals are used to provide the multiplexed

row and column address to the SDRAM.

DDR3

SDRAM Differential Clock: Channel A SDRAM Differential clock signal

pair. The crossing of the positive edge of SA_CK and the negative edge

of its complement SA_CK# are used to sample the command and

control signals on the SDRAM.

SA_CK[3:0]

SA_CK#[3:0]

DDR3

Clock Enable: (1 per rank). These signals are used to:

•

Initialize the SDRAMs during power-up.

Power down SDRAM ranks.

Place all SDRAM ranks into and out of self-refresh during STR.

DDR3

SA_CKE[3:0]

Chip Select: (1 per rank). These signals are used to select particular

SDRAM components during the active state. There is one Chip Select

for each SDRAM rank.

DDR3

SA_CS#[3:0]

SA_ODT[3:0]

On Die Termination: Active Termination Control.

DDR3

Datasheet, Volume 1

Signal Description

Table 6-3.

Memory Channel B Signals

Direction/

Buffer Type

Signal Name

Description

Bank Select: These signals define which banks are selected within

each SDRAM rank.

DDR3

SB_BS[2:0]

SB_WE#

Write Enable Control Signal: This signal is used with SB_RAS# and

SB_CAS# (along with SB_CS#) to define the SDRAM Commands.

DDR3

RAS Control Signal: This signal is used with SB_CAS# and SB_WE#

DDR3

SB_RAS#

SB_CAS#

(along with SB_CS#) to define the SRAM Commands.

CAS Control Signal: This signal is used with SB_RAS# and SB_WE#

(along with SB_CS#) to define the SRAM Commands.

DDR3

Data Strobes: SB_DQS[8:0] and its complement signal group make

up a differential strobe pair. The data is captured at the crossing point

of SB_DQS[8:0] and its SB_DQS#[8:0] during read and write

transactions.

I/O

DDR3

SB_DQS[8:0]

SB_DQS#[8:0]

Data Bus: Channel B data signal interface to the SDRAM data bus.

I/O

DDR3

SB_DQ[63:0]

SB_MA[15:0]

Memory Address: These signals are used to provide the multiplexed

row and column address to the SDRAM.

DDR3

SDRAM Differential Clock: Channel B SDRAM Differential clock

signal pair. The crossing of the positive edge of SB_CK and the

negative edge of its complement SB_CK# are used to sample the

command and control signals on the SDRAM.

SB_CK[3:0]

SB_CK#[3:0]

DDR3

Clock Enable: (1 per rank) These signals are used to:

•

Initialize the SDRAMs during power-up.

Power down SDRAM ranks.

Place all SDRAM ranks into and out of self-refresh during STR.

DDR3

SB_CKE[3:0]

Chip Select: (1 per rank). These signals are used to select particular

SDRAM components during the active state. There is one Chip Select

for each SDRAM rank.

DDR3

SB_CS#[3:0]

SB_ODT[3:0]

On Die Termination: Active Termination Control.

DDR3

6.2

Memory Reference and Compensation Signals

Table 6-4.

Memory Reference and Compensation

Direction/

Buffer Type

Signal Name

Description

DDR3 Reference Voltage: This signal is used as a reference

voltage to the DDR3 controller.

SM_VREF

Memory Channel A/B DIMM DQ Voltage Reference: These

output pins are connected to the DIMMs, and are programmed to

have a reference voltage with optimized margin.

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

The nominal source impedance for these pins is 150

The step size is 7.7 mV for DDR3 (with no load).

Datasheet, Volume 1

Signal Description

6.3

Reset and Miscellaneous Signals

Table 6-5.

Reset and Miscellaneous Signals

Direction/

Buffer Type

Signal Name

Description

Configuration Signals:

The CFG signals have a default value of '1' if not terminated on the

board.

•

CFG[1:0]: Reserved configuration lane. A test point may be

placed on the board for this lane.

•

CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

— 1 = Normal operation

— 0 = Lane numbers reversed

•

CFG[3]: PCI Express* Static x4 Lane Numbering Reversal.

— 1 = Normal operation

— 0 = Lane numbers reversed

CFG[17:0]

CMOS

•

CFG[4]: Reserved configuration lane. A test point may be

placed on the board for this lane.

CFG[6:5]: PCI Express* Bifurcation:

Note 1

— 00 = 1 x8, 2 x4 PCI Express*

— 01 = reserved

— 10 = 2 x8 PCI Express*

— 11 = 1 x16 PCI Express*

•

CFG[17:7]: Reserved configuration lanes. A test point may be

placed on the board for these pins.

FC signals are signals that are available for compatibility with other

processors. A test point may be placed on the board for these pins.

FC_x

Power Management Sync: A sideband signal to communicate

PM_SYNC

RESET#

power management status from the platform to the processor.

CMOS

Platform Reset pin driven by the PCH.

CMOS

Reserved: All signals that are RSVD and RSVD_NCTF must be left

unconnected on the board.

No Connect

RSVD

RSVD_NCTF

Non-Critical to

Function

DDR3 DRAM Reset: Reset signal from processor to DRAM devices.

One common to all channels.

CMOS

SM_DRAMRST#

Note:

1. PCIe* bifurcation support varies with the processor and PCH SKUs used.

Datasheet, Volume 1

Signal Description

6.4

PCI Express*-based Interface Signals

Table 6-6.

PCI Express* Graphics Interface Signals

Direction/

Buffer Type

Signal Name

Description

PCI Express* Input Current Compensation

PCI Express* Current Compensation

PCI Express* Resistance Compensation

PCI Express* Receive Differential Pair

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX[15:0]

PEG_RX#[15:0]

PE_RX[3:0]

PCI Express*

PE_RX#[3:0]

PEG_TX[15:0]

PCI Express* Transmit Differential Pair

PEG_TX#[15:0]

PE_TX[3:0]

PCI Express*

PE_TX#[3:0]

Note:

PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] signals are only used for platforms that support

20 PCIe lanes. These signals are reserved on Desktop 3rd Generation Intel Core™ i7/i5 processors,

Desktop Intel Pentium processors and Desktop Intel Celeron processors.

6.5

Intel^®Flexible Display (Intel^®FDI) Interface

Signals

Table 6-7.

Intel Flexible Display (Intel FDI) Interface

Direction/

Buffer Type

Signal Name

Description

Intel Flexible Display Interface Frame Sync: Pipe A

FDI0_FSYNC[0]

FDI0_LSYNC[0]

CMOS

Intel Flexible Display Interface Line Sync: Pipe A

CMOS

FDI_TX[7:0]

Intel Flexible Display Interface Transmit Differential

Pairs

FDI_TX#[7:0]

FDI

Intel Flexible Display Interface Frame Sync: Pipe B and C

FDI1_FSYNC[1]

FDI1_LSYNC[1]

CMOS

Intel Flexible Display Interface Line Sync: Pipe B and C

CMOS

Intel Flexible Display Interface Hot-Plug Interrupt

FDI_INT

Asynchronous

CMOS

Datasheet, Volume 1

Signal Description

6.6

Direct Media Interface (DMI) Signals

Table 6-8.

Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface

Direction/

Buffer Type

Signal Name

Description

DMI_RX[3:0]

DMI_RX#[3:0]

DMI Input from PCH: Direct Media Interface receive

differential pair.

DMI

DMI_TX[3:0]

DMI_TX#[3:0]

DMI Output to PCH: Direct Media Interface transmit

differential pair.

DMI

6.7

Phase Lock Loop (PLL) Signals

Table 6-9.

Phase Lock Loop (PLL) Signals

Direction/

Buffer Type

Signal Name

Description

BCLK

Differential bus clock input to the processor

BCLK#

Diff Clk

6.8

Test Access Points (TAP) Signals

Table 6-10. Test Access Points (TAP) Signals

Direction/

Buffer Type

Signal Name

Description

Breakpoint and Performance Monitor Signals: These signals

are outputs from the processor that indicate the status of

breakpoints and programmable counters used for monitoring

processor performance.

I/O

CMOS

BPM#[7:0]

BCLK_ITP

BCLK_ITP#

These signals are connected in parallel to the top side debug

probe to enable debug capacities.

DBR# is used only in systems where no debug port is

implemented on the system board. DBR# is used by a debug

port interposer so that an in-target probe can drive system

reset.

DBR#

PRDY# is a processor output used by debug tools to determine

processor debug readiness.

PRDY#

PREQ#

TCK

Asynchronous

CMOS

PREQ# is used by debug tools to request debug operation of the

processor.

Asynchronous

CMOS

Test Clock: This signal provides the clock input for the

processor Test Bus (also known as the Test Access Port). TCK

must be driven low or allowed to float during power on Reset.

CMOS

Test Data In: This signal transfers serial test data into the

processor. TDI provides the serial input needed for JTAG

specification support.

TDI

CMOS

Test Data Out: This signal transfers serial test data out of the

processor. TDO provides the serial output needed for JTAG

specification support.

TDO

Open Drain

Test Mode Select: A JTAG specification support signal used by

debug tools.

TMS

CMOS

Test Reset: This signal resets the Test Access Port (TAP) logic.

TRST# must be driven low during power on Reset.

TRST#

CMOS

Datasheet, Volume 1

Signal Description

6.9

Error and Thermal Protection Signals

Table 6-11. Error and Thermal Protection Signals

Direction/

Buffer Type

Signal Name

Description

Catastrophic Error: This signal indicates that the system has

experienced a catastrophic error and cannot continue to operate.

The processor will set this for non-recoverable machine check

errors or other unrecoverable internal errors.

On the processor, CATERR# is used for signaling the following

types of errors:

CMOS

CATERR#

•

Legacy MCERRs – CATERR# is asserted for 16 BCLKs.

Legacy IERRs – CATERR# remains asserted until warm or

cold reset.

PECI (Platform Environment Control Interface): A serial

sideband interface to the processor, it is used primarily for

thermal, power, and error management.

I/O

PECI

Asynchronous

Processor Hot: PROCHOT# goes active when the processor

temperature monitoring sensor(s) detects that the processor has

reached its maximum safe operating temperature. This indicates

that the processor Thermal Control Circuit (TCC) has been

activated, if enabled. This signal can also be driven to the

processor to activate the TCC.

CMOS Input/

Open-Drain

Output

PROCHOT#

Note: Toggling PROCHOT# more than once in 1.5 ms period

will result in constant Pn state of the processor.

Thermal Trip: The processor protects itself from catastrophic

overheating by use of an internal thermal sensor. This sensor is

set well above the normal operating temperature to ensure that

there are no false trips. The processor will stop all execution

when the junction temperature exceeds approximately 130 °C.

This is signaled to the system by the THERMTRIP# signal.

THERMTRIP#

Asynchronous

CMOS

Datasheet, Volume 1

Signal Description

6.10

Power Sequencing Signals

Table 6-12. Power Sequencing Signals

Direction/

Buffer Type

Signal Name

Description

SM_DRAMPWROK Processor Input: Connects to PCH

DRAMPWROK.

SM_DRAMPWROK

UNCOREPWRGOOD

Asynchronous

CMOS

The processor requires this input signal to be a clean indication

that the V

, V

, and V

, power supplies are

CCSA

CCIO

AXG

DDQ

stable and within specifications. This requirement applies

regardless of the S-state of the processor. 'Clean' implies that

the signal will remain low (capable of sinking leakage current),

without glitches, from the time that the power supplies are

turned on until they come within specification. The signal must

then transition monotonically to a high state. This is connected

to the PCH PROCPWRGD signal.

Asynchronous

CMOS

SKTOCC# (Socket Occupied) : This signal is pulled down

directly (0 Ohms) on the processor package to the ground.

There is no connection to the processor silicon for this signal.

System board designers may use this signal to determine if the

processor is present.

SKTOCC#

Processor Select: This signal is an output that indicates if the

processor used is 2nd Generation Intel Core™ processor family

desktop, Intel Pentium processor family desktop, Intel

Celeron processor family desktop or Desktop 3rd Generation

Intel Core™ processor family, Desktop Intel Pentium

processor family, Desktop Intel Celeron processor family .

For 2nd Generation Intel Core™ processor family desktop,

PROC_SEL

Intel Pentium processor family desktop, Intel Celeron

processor family desktop, the output will be high.

For Desktop 3rd Generation Intel Core™ processor family,

Desktop Intel Pentium processor family, Desktop Intel

Celeron processor family, the output will be low.

Voltage selection for VCCIO: This output signal was initially

intended to select the I/O voltage depending on the processor

being used.

Since the V

voltage is the same for 2nd Generation Intel

CCIO

Core™ processor family desktop, Intel Pentium processor

family desktop, Intel Celeron processor family desktop and

Desktop 3rd Generation Intel Core™ processor family, Desktop

VCCIO_SEL

Intel Pentium processor family, Desktop Intel Celeron

processor family, the usage of this pin was changed as follows:

The pin is configured on the package to be same as 2nd

Generation Intel Core™ processor family desktop, Intel

Pentium processor family desktop, Intel Celeron processor

family desktop . This pin must be pulled high on the

motherboard, when using a dual rail voltage regulator.

Datasheet, Volume 1

Signal Description

6.11

Processor Power Signals

Table 6-13. Processor Power Signals

Direction/

Buffer Type

Signal Name

Description

VCC

Processor core power rail.

Processor power for I/O.

Ref

VCCIO

VDDQ

Processor I/O supply voltage for DDR3.

Graphics core power supply.

VCCAXG

VCCPLL

VCCSA

VCCPLL provides isolated power for internal processor PLLs.

System Agent power supply.

VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal

serial synchronous interface used to transfer power

management information between the processor and the

voltage regulator controllers. This serial VID interface replaces

the parallel VID interface on previous processors.

VIDSOUT

VIDSCLK

VIDALERT#

CMOS I/ OD O

OD O

CMOS I

Voltage selection for VCCSA:

CMOS

VCCSA_VID

Note:

1. The VCCSA_VID can toggle at most once in 500 uS; The slew rate of VCCSA_VID is 1 V/nS.

6.12

Sense Signals

Table 6-14. Sense Signals

Direction/

Buffer Type

Signal Name

Description

VCC_SENSE and VSS_SENSE provide an isolated, low

impedance connection to the processor core voltage and

ground. They can be used to sense or measure voltage near the

silicon.

VCC_SENSE

VSS_SENSE

Analog

VAXG_SENSE and VSSAXG_SENSE provide an isolated, low

VAXG_SENSE

VSSAXG_SENSE

impedance connection to the V

voltage and ground. They

AXG

Analog

can be used to sense or measure voltage near the silicon.

VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated, low

impedance connection to the processor VCCIO voltage and

ground. They can be used to sense or measure voltage near the

silicon.

VCCIO_SENSE

VSS_SENSE_VCCIO

Analog

VCCSA_SENSE provide an isolated, low impedance connection

to the processor system agent voltage. It can be used to sense

or measure voltage near the silicon.

VCCSA_SENSE

Analog

Datasheet, Volume 1

Signal Description

6.13

Ground and Non-Critical to Function (NCTF)

Signals

Table 6-15. Ground and Non-Critical to Function (NCTF) Signals

Direction/

Buffer Type

Signal Name

Description

VSS

Processor ground node

GND

Non-Critical to Function: These signals are for package

mechanical reliability.

VSS_NCTF (BGA Only)

6.14

Processor Internal Pull-Up / Pull-Down Resistors

Table 6-16. Processor Internal Pull-Up / Pull-Down Resistors

Signal Name

Pull-Up / Pull-Down

Rail

Value

BPM[7:0]

PRDY#

PREQ#

TCK

Pull Up

Pull Down

Pull Up

VCCIO

VSS

65–165 

5–15 k

TDI

VCCIO

TMS

TRST#

CFG[17:0]

§ §

Datasheet, Volume 1

Electrical Specifications

7 Electrical Specifications

7.1

Power and Ground Lands

The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground)

inputs for on-chip power distribution. All power lands must be connected to their

respective processor power planes, while all VSS lands must be connected to the

system ground plane. Use of multiple power and ground planes is recommended to

reduce I*R drop. The VCC and VCCAXG lands must be supplied with the voltage

determined by the processor Serial Voltage IDentification (SVID) interface. A new

serial VID interface is implemented on the processor. T a ble 7-1 specifies the voltage

level for the various VIDs.

7.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is

capable of generating large current swings between low- and full-power states. This

may cause voltages on power planes to sag below their minimum values, if bulk

decoupling is not adequate. Larger bulk storage (C_BULK), such as electrolytic capacitors,

supply current during longer lasting changes in current demand (for example, coming

out of an idle condition). Similarly, capacitors act as a storage well for current when

entering an idle condition from a running condition. To keep voltages within

specification, output decoupling must be properly designed.

Caution:

Design the board to ensure that the voltage provided to the processor remains within

the specifications listed in T a ble 7-4. Failure to do so can result in timing violations or

reduced lifetime of the processor.

7.2.1

Voltage Rail Decoupling

The voltage regulator solution needs to provide:

• bulk capacitance with low effective series resistance (ESR)

• a low interconnect resistance from the regulator to the socket

• bulk decoupling to compensate for large current swings generated during poweron,

or low-power idle state entry/exit

The power delivery solution must ensure that the voltage and current specifications are

met, as defined in T a ble 7-4.

Datasheet, Volume 1

Electrical Specifications

7.3

Processor Clocking (BCLK[0], BCLK#[0])

The processor uses a differential clock to generate the processor core operating

frequency, memory controller frequency, system agent frequencies, and other internal

clocks. The processor core frequency is determined by multiplying the processor core

ratio by the BCLK frequency. Clock multiplying within the processor is provided by an

internal phase locked loop (PLL) that requires a constant frequency input, with

exceptions for Spread Spectrum Clocking (SSC).

The processor’s maximum non-turbo core frequency is configured during power-on

reset by using its manufacturing default value. This value is the highest non-turbo core

multiplier at which the processor can operate. If lower maximum speeds are desired,

the appropriate ratio can be configured using the FLEX_RATIO MSR.

7.3.1

Phase Lock Loop (PLL) Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to T a ble 7-5 for DC

specifications.

7.4

V_CCVoltage Identification (VID)

The processor uses three signals for the serial voltage identification interface to support

automatic selection of voltages. T a ble 7-1 specifies the voltage level corresponding to

the eight bit VID value transmitted over serial VID. A ‘1’ in this table refers to a high

voltage level and a ‘0’ refers to a low voltage level. If the voltage regulation circuit

cannot supply the voltage that is requested, the voltage regulator must disable itself.

VID signals are CMOS push/pull drivers. Refer to T a ble 7-8 for the DC specifications for

these signals. The VID codes will change due to temperature and/or current load

changes to minimize the power of the part. A voltage range is provided in T a ble 7-4.

The specifications are set so that one voltage regulator can operate with all supported

frequencies.

Individual processor VID values may be set during manufacturing so that two devices

at the same core frequency may have different default VID settings. This is shown in

the VID range values in T a ble 7-4. The processor provides the ability to operate while

transitioning to an adjacent VID and its associated voltage. This will represent a DC

shift in the loadline.

Note:

At condition outside functional operation condition limits, neither functionality nor long

term reliability can be expected. If a device is returned to conditions within functional

operation limits after having been subjected to conditions outside these limits, but

within the absolute maximum and minimum ratings, the device may be functional, but

with its lifetime degraded on exposure to conditions exceeding the functional operation

condition limits.

Datasheet, Volume 1

Electrical Specifications

Table 7-1.

VR 12.0 Voltage Identification Definition (Sheet 1 of 3)

VID VID VID VID VID VID VID VID

HEX

CC_MAX

0.00000

0.25000

0.25500

0.26000

0.26500

0.27000

0.27500

0.28000

0.28500

0.29000

0.29500

0.30000

0.30500

0.31000

0.31500

0.32000

0.32500

0.33000

0.33500

0.34000

0.34500

0.35000

0.35500

0.36000

0.36500

0.37000

0.37500

0.38000

0.38500

0.39000

0.39500

0.40000

0.40500

0.41000

0.41500

0.42000

0.42500

0.43000

0.43500

0.44000

0.44500

0.45000

0.45500

0.46000

0.46500

0.47000

0.88500

0.89000

0.89500

0.90000

0.90500

0.91000

0.91500

0.92000

0.92500

0.93000

0.93500

0.94000

0.94500

0.95000

0.95500

0.96000

0.96500

0.97000

0.97500

0.98000

0.98500

0.99000

0.99500

1.00000

1.00500

1.01000

1.01500

1.02000

1.02500

1.03000

1.03500

1.04000

1.04500

1.05000

1.05500

1.06000

1.06500

1.07000

1.07500

1.08000

1.08500

1.09000

1.09500

1.10000

1.10500

1.11000

Datasheet, Volume 1

Electrical Specifications

Table 7-1.

VR 12.0 Voltage Identification Definition (Sheet 2 of 3)

VID VID VID VID VID VID VID VID

HEX

CC_MAX

0.47500

0.48000

0.48500

0.49000

0.49500

0.50000

0.50500

0.51000

0.51500

0.52000

0.52500

0.53000

0.53500

0.54000

0.54500

0.55000

0.55500

0.56000

0.56500

0.57000

0.57500

0.58000

0.58500

0.59000

0.59500

0.60000

0.60500

0.61000

0.61500

0.62000

0.62500

0.63000

0.63500

0.64000

0.64500

0.65000

0.65500

0.66000

0.66500

0.67000

0.67500

0.68000

0.68500

0.69000

0.69500

0.70000

0.70500

1.11500

1.12000

1.12500

1.13000

1.13500

1.14000

1.14500

1.15000

1.15500

1.16000

1.16500

1.17000

1.17500

1.18000

1.18500

1.19000

1.19500

1.20000

1.20500

1.21000

1.21500

1.22000

1.22500

1.23000

1.23500

1.24000

1.24500

1.25000

1.25500

1.26000

1.26500

1.27000

1.27500

1.28000

1.28500

1.29000

1.29500

1.30000

1.30500

1.31000

1.31500

1.32000

1.32500

1.33000

1.33500

1.34000

1.34500

Datasheet, Volume 1

Electrical Specifications

Table 7-1.

VR 12.0 Voltage Identification Definition (Sheet 3 of 3)

VID VID VID VID VID VID VID VID

HEX

CC_MAX

0.71000

0.71500

0.72000

0.72500

0.73000

0.73500

0.74000

0.74500

0.75000

0.75500

0.76000

0.76500

0.77000

0.77500

0.78000

0.78500

0.79000

0.79500

0.80000

0.80500

0.81000

0.81500

0.82000

0.82500

0.83000

0.83500

0.84000

0.84500

0.85000

0.85500

0.86000

0.86500

0.87000

0.87500

0.88000

1.35000

1.35500

1.36000

1.36500

1.37000

1.37500

1.38000

1.38500

1.39000

1.39500

1.40000

1.40500

1.41000

1.41500

1.42000

1.42500

1.43000

1.43500

1.44000

1.44500

1.45000

1.45500

1.46000

1.46500

1.47000

1.47500

1.48000

1.48500

1.49000

1.49500

1.50000

1.50500

1.51000

1.51500

1.52000

Datasheet, Volume 1

Electrical Specifications

7.5

7.6

System Agent (SA) V_CCVID

The V

is configured by the processor output land VCCSA_VID. VCCSA_VID output

CCSA

default logic state is low for 2nd generation and 3rd generation Desktop Core

processors, and configures V to 0.925 V.

CCSA

Reserved or Unused Signals

The following are the general types of reserved (RSVD) signals and connection

guidelines:

• RSVD – these signals should not be connected.

• RSVD_TP – these signals must be routed to a test point. Failure to route these

signal to test points will restrict Intel’s ability to assist in platform debug.

• RSVD_NCTF – these signals are non-critical to function and may be left un-

connected.

Arbitrary connection of these signals to V , V

, V

V , or

CCIO

DDQ

CCPLL

CCSA, AXG, SS

to any other signal (including each other) may result in component malfunction or

incompatibility with future processors. See Chapter 8 for a land listing of the processor

and the location of all reserved signals.

For reliable operation, always connect unused inputs or bi-directional signals to an

appropriate signal level. Unused active high inputs should be connected through a

resistor to ground (V ). Unused outputs maybe left unconnected; however, this may

interfere with some Test Access Port (TAP) functions, complicate debug probing, and

prevent boundary scan testing. A resistor must be used when tying bi-directional

signals to power or ground. When tying any signal to power or ground, a resistor will

also allow for system testability. For details, see T a ble 7-8.

7.7

Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in T a ble 7-2. The

buffer type indicates which signaling technology and specifications apply to the signals.

All the differential signals and selected DDR3 and Control Sideband signals have On-Die

Termination (ODT) resistors. There are some signals that do not have ODT and need to

be terminated on the board.

Datasheet, Volume 1

Electrical Specifications

Table 7-2.

Signal Groups (Sheet 1 of 2)

Signal Group

Type

Signals

System Reference Clock

Differential

CMOS Input

BCLK[0], BCLK#[0]

DDR3 Reference Clocks

Differential

SA_CK[3:0], SA_CK#[3:0]

SB_CK[3:0], SB_CK#[3:0]

DDR3 Output

DDR3 Command Signals

SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#

SA_WE#, SB_WE#

SA_MA[15:0], SB_MA[15:0]

SA_BS[2:0], SB_BS[2:0]

SM_DRAMRST#

Single Ended

SA_CS#[3:0], SB_CS#[3:0]

SA_ODT[3:0], SB_ODT[3:0]

SA_CKE[3:0], SB_CKE[3:0]

DDR3 Data Signals

Single ended

Differential

DDR3 Bi-directional

SA_DQ[63:0], SB_DQ[63:0]

SA_DQS[8:0], SA_DQS#[8:0]

SB_DQS[8:0], SB_DQS#[8:0]

TAP (ITP/XDP)

Single Ended

CMOS Input

TCK, TDI, TMS, TRST#

TDO

CMOS Output

Asynchronous CMOS Output

TAPPWRGOOD

Control Sideband

Single Ended

CMOS Input

CFG[17:0]

PROCHOT#

Asynchronous CMOS/Open

Drain Bi-directional

Single Ended

Asynchronous CMOS Output

Asynchronous CMOS Input

Asynchronous Bi-directional

THERMTRIP#, CATERR#

SM_DRAMPWROK, UNCOREPWRGOOD ,

PM_SYNC, RESET#

PECI

CMOS Input

Open Drain Output

Bi-directional

VIDALERT#

VIDSCLK

VIDSOUT

Single Ended

Power/Ground/Other

Power

VCC, VCC_NCTF, VCCIO, VCCPLL, VDDQ, VCCAXG

VSS

Ground

No Connect and test point

RSVD, RSVD_NCTF, RSVD_TP, FC_x

VCC_SENSE, VSS_SENSE, VCCIO_SENSE,

VSS_SENSE_VCCIO, VAXG_SENSE,

VSSAXG_SENSE

Sense Points

Other

SKTOCC#, DBR#

Datasheet, Volume 1

Electrical Specifications

Table 7-2.

Signal Groups (Sheet 2 of 2)

Signal Group

Type

Signals

PCI Express*

PEG_RX[15:0], PEG_RX#[15:0],

PE_RX[3:0] , PE_RX#[3:0]

Differential

PCI Express Input

PEG_TX[15:0], PEG_TX#[15:0],

PCI Express Output

Analog Input

PE_TX[3:0] , PE_TX#[3:0]

Single Ended

PEG_ICOMP0, PEG_COMPI, PEG_RCOMP0

DMI

Differential

DMI Input

DMI_RX[3:0], DMI_RX#[3:0]

DMI_TX[3:0], DMI_TX#[3:0]

DMI Output

Intel FDI

Single Ended

Differential

FDI Input

FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INT

FDI_TX[7:0], FDI_TX#[7:0]

FDI Output

Analog Input

Single Ended

FDI_COMPIO, FDI_ICOMPO

Notes:

Refer to Chapter 8 for signal description details.

SA and SB refer to DDR3 Channel A and DDR3 Channel B.

The maximum rise/fall time of UNCOREPWRGOOD is 20 ns.

PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] signals are only used for platforms that support

20 PCIe* lanes. These signals are reserved on Desktop 3rd Generation Intel Core™ i7/i5 processors.

Note:

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for

at least 10 BCLKs with maximum T /T

of 6 ns in order for the processor to

rise fall

recognize the proper signal state. See Section 7.10 for the DC specifications.

7.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)

logic, Intel recommends the processor be first in the TAP chain, followed by any other

components within the system. A translation buffer should be used to connect to the

rest of the chain unless one of the other components is capable of accepting an input of

the appropriate voltage. Two copies of each signal may be required with each driving a

different voltage level.

The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.6-

2003 standards. A small portion of the I/O lands may support only one of those

standards.

Datasheet, Volume 1

Electrical Specifications

7.9

Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity to

which the device is exposed to while being stored in a moisture barrier bag. The

specified storage conditions are for component level prior to board attach.

T a ble 7-3 specifies absolute maximum and minimum storage temperature limits that

represent the maximum or minimum device condition beyond which damage, latent or

otherwise, may occur. The table also specifies sustained storage temperature, relative

humidity, and time-duration limits. These limits specify the maximum or minimum

device storage conditions for a sustained period of time. Failure to adhere to the

following specifications can affect long term reliability of the processors conditions

outside sustained limits, but within absolute maximum and minimum ratings, quality

and reliability may be affected.

Table 7-3.

Storage Condition Ratings

Symbol

Parameter

Min

Max

Notes

The non-operating device storage temperature.

Damage (latent or otherwise) may occur when

exceeded for any length of time.

-25 °C

125 °C

1, 2, 3, 4

absolute storage

The ambient storage temperature (in shipping

media) for a sustained period of time

-5 °C

40 °C

85 °C

5, 6

sustained storage

The ambient storage temperature (in shipping

media) for a short period of time.

-20 °C

short term storage

The maximum device storage relative humidity

for a sustained period of time.

60% at 24 °C

6, 7

sustained storage

A prolonged or extended period of time; typically

associated with customer shelf life.

Time

0 Months

0 hours

30 Months

72 hours

sustained storage

Time

Notes:

A short-period of time;

short term storage

Refers to a component device that is not assembled in a board or socket and is not electrically connected to

a voltage reference or I/O signal.

Specified temperatures are not to exceed values based on data collected. Exceptions for surface mount

reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.

applies to the unassembled component only and does not apply to the shipping media,

absolute storage

moisture barrier bags, or desiccant.

Component product device storage temperature qualification methods may follow JESD22-A119 (low temp)

and JESD22-A103 (high temp) standards when applicable for volatile memory.

Intel branded products are specified and certified to meet the following temperature and humidity limits

that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50%

to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits

are not specified for non-Intel branded boards.

The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture

sensitive devices removed from the moisture barrier bag.

Nominal temperature and humidity conditions and durations are given and tested within the constraints

imposed by T

and customer shelf life in applicable Intel boxes and bags.

sustained storage

Datasheet, Volume 1

Electrical Specifications

7.10

DC Specifications

The processor DC specifications in this section are defined at the processor

pads, unless noted otherwise. See Chapter 8 for the processor land listings and

Chapter 6 for signal definitions. Voltage and current specifications are detailed in

T a ble 7-4, T a ble 7-5, and T a ble 7-6.

The DC specifications for the DDR3 signals are listed in T a ble 7-7 Control Sideband and

Test Access Port (TAP) are listed in T a ble 7-8.

T a ble 7-4 through T a ble 7-6 list the DC specifications for the processor and are valid

only while meeting the thermal specifications (as specified in the Thermal / Mechanical

Specifications and Guidelines), clock frequency, and input voltages. Care should be

taken to read all notes associated with each parameter.

7.10.1

Voltage and Current Specifications

Note:

Noise measurements on SENSE lands for all voltage supplies should be made with a 

20-MHz bandwidth oscilloscope.

Table 7-4.

Processor Core Active and Idle Mode DC Voltage and Current Specifications

(Sheet 1 of 2)

Symbol

Parameter

Min

Typ

Max

Unit

Note

VID

VID Range

Loadline Slope

0.2500

—

1.5200

1.7

m

2, 4, 5

2011D, 2011C, 2011B (processors with

77 W, 65 W, 55 W, 45 W TDP)

VCC

Tolerance Band

2011D, 2011C, 2011B (processors with

77 W, 65 W, 55 W, 45 W TDP)

2, 4, 5,

TOB

PS0

PS1

PS2

±16

±13

±11.5

Ripple:

2011D, 2011C, 2011B (processors with

77 W, 65 W, 55 W, 45 W TDP)

2, 4, 5,

Ripple

PS0

PS1

PS2

±7

±10

-10/+25

Loadline Slope 2011A (processors

2, 4, 5,

2.9

m

VCC

with 35 W TDP)

Tolerance Band

2011A (processors with 35 W TDP)

2, 4, 5,

6, 7

TOB

PS0

PS1

PS2

±19

±11.5

Ripple:

2011A (processors with 35 W TDP)

2, 4, 5,

6, 7

Ripple

PS0

PS1

PS2

±10

-10/+25

Default V voltage for initial power up

—

112

CC,BOOT

2011D I (processors with 77 W, TDP)

—

2011C I (processors with 55 W TDP)

Datasheet, Volume 1

Electrical Specifications

Table 7-4.

Processor Core Active and Idle Mode DC Voltage and Current Specifications

(Sheet 2 of 2)

Symbol

Parameter

2011B I (processors with 45 W TDP)

Min

Typ

Max

Unit

Note

—

2011A I (processors with 35 W TDP)

2011D Sustained I (processors with

—

CC_TDC

77 W, TDP)

2011C Sustained I (processors with

55 W TDP)

2011B Sustained I (processors with

45 W TDP)

2011A Sustained I (processors with

35 W TDP)

Notes:

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. This

differs from the VID employed by the processor during a power management event (Adaptive Thermal

Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the

socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum

impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external

noise from the system is not coupled into the oscilloscope probe.

ICC_MAX specification is based on the V loadline at worst case (highest) tolerance and ripple.

The V specifications represent static and transient limits.

The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage

regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and

VSS_SENSE lands.

PSx refers to the voltage regulator power state as set by the SVID protocol.

2011A (processors with 35 W TDP) loadline slope, TOB, and ripple specifications allow for a cost reduced

voltage regulator for boards supporting only the 2011A (processors with 35 W TDP). 2011A (processors

with 35 W TDP) processors may also use the loadline slope, TOB, and ripple specifications for 2011D,

2011C, and 2011B.

Datasheet, Volume 1

Electrical Specifications

Table 7-5.

Processor System Agent I/O Buffer Supply DC Voltage and Current

Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Note

Voltage for the system agent

0.879

0.925

0.971

CCSA

Processor I/O supply voltage for

DDR3

—

1.5

—

DDQ

DC= ±3%

AC= ±2%

AC+DC= ±5%

TOL

Tolerance

DDQ

PLL supply voltage (DC + AC

specification)

1.71

1.8

1.89

CCPLL

Processor I/O supply voltage for

other than DDR3

-2/-3%

1.05

—

+2/+3%

8.8

CCIO

Current for the system agent

—

Sustained current for the system

agent

—

8.2

SA_TDC

Processor I/O supply current for

DDR3

—

4.75

DDQ

Processor I/O supply sustained

current for DDR3

DDQ_TDC

Processor I/O supply standby

current for DDR3

DDQ_STANDBY

PLL supply current

—

1.5

0.93

8.5

CC_VCCPLL

PLL sustained supply current

Processor I/O supply current

CC_VCCPLL_TDC

CC_VCCIO

Processor I/O supply sustained

current

—

8.5

CC_VCCIO_TDC

Notes:

VCCSA must be provided using a separate voltage source and not be connected to V . This specification is

measured at VCCSA_SENSE.

±5% total. Minimum of ±2% DC and 3% AC at the sense point. di/dt = 50 A/us with 150 ns step.

Datasheet, Volume 1

Electrical Specifications

Table 7-6.

Processor Graphics VID based (V

Specifications

) Supply DC Voltage and Current

AXG

Symbol

Parameter

GFX_VID Range for V

Min

Typ

Max

Unit

Note

GFX_VID

AXG

0.2500

—

1.5200

Range

V Loadline Slope

AXG

4.1

m

2, 3

AXG

Tolerance Band

TOB

PS0, PS1

PS2

11.5

2, 3, 4

AXG

Ripple:

PS0

±10

-10/+15

Ripple

AXG

PS1

PS2

Current for Processor Graphics

core

—

Sustained current for Processor

Graphics core

—

AXG_TDC

Notes:

is VID based rail.

AXG

The V

and V

loadlines represent static and transient limits.

AXG_MIN

AXG_MAX

The loadlines specify voltage limits at the die measured at the VAXG_SENSE and VSSAXG_SENSE lands.

Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG_SENSE

and VSSAXG_SENSE lands.

PSx refers to the voltage regulator power state as set by the SVID protocol.

Each processor is programmed with a maximum valid voltage identification value (VID) that is set at

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

such that two processors at the same frequency may have different settings within the VID range. This

differs from the VID employed by the processor during a power management event (Adaptive Thermal

Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

Table 7-7.

DDR3 Signal Group DC Specifications (Sheet 1 of 2)

1,7

Symbol

Parameter

Min

Typ

Max

Units Notes

Input Low Voltage

SM_VREF

– 0.1

—

2, 4, 9

Input High Voltage

SM_VREF

+ 0.1

—

3, 9

Input Low Voltage

(SM_DRAMPWROK)

*0.55

DDQ

—

– 0.1

Input High Voltage

(SM_DRAMPWROK)

*0.55

DDQ

—

+ 0.1

Output Low Voltage

/ 2)* (R

DDQ

—

4, 6

/(R +R

))

TERM

Output High Voltage

- ((V

/ 2)*

DDQ



(R /(R +R ))

TERM

DDR3 Data Buffer pull-

up Resistance

28.6

ON_UP(DQ)

ON_DN(DQ)

DDR3 Data Buffer pull-

down Resistance

28.6

DDR3 On-die

termination equivalent

resistance for data

signals



ODT(DQ)

ODT(DC)

DDR3 On-die

termination DC working

point (driver set to

receive mode)

0.4*V

0.5*V

0.6*V

DDQ

Datasheet, Volume 1

Electrical Specifications

Table 7-7.

DDR3 Signal Group DC Specifications (Sheet 2 of 2)

1,7

Symbol

Parameter

Min

Typ

Max

Units Notes

DDR3 Clock Buffer pull-

up Resistance



5, 10

ON_UP(CK)

DDR3 Clock Buffer pull-

down Resistance

ON_DN(CK)

DDR3 Command Buffer

pull-up Resistance

ON_UP(CMD)

DDR3 Command Buffer

pull-down Resistance

ON_DN(CMD)

DDR3 Control Buffer

pull-up Resistance

ON_UP(CTL)

DDR3 Control Buffer

pull-down Resistance

ON_DN(CTL)

Input Leakage Current

(DQ, CK)

0.2*V

0.8*V

± 0.75

± 0.55

± 0.9

—

DDQ

± 1.4

Input Leakage Current

(CMD, CTL)

0.2*V

0.8*V

± 0.85

± 0.65

± 1.10

± 1.65

DDQ

value.

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

and V

may experience excursions above V

. However, input signal drivers must comply with the

DDQ

signal quality specifications.

This is the pull-up/pull-down driver resistance.

is the termination on the DIMM and in not controlled by the processor.

TERM

The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.

SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over V

must be monotonic.

* 0.55 ±200 mV and the edge

DDQ

10.

SM_VREF is defined as V

DDQ

tolerance is preliminary and might be subject to change.

Datasheet, Volume 1

Electrical Specifications

Table 7-8.

Control Sideband and TAP Signal Group DC Specifications

Symbol

Parameter

Input Low Voltage

Min

Max

* 0.3

CCIO

Units

Notes

—

Input High Voltage

Output Low Voltage

Output High Voltage

Buffer on Resistance

Input Leakage Current

* 0.7

—

2, 4

CCIO

—

V * 0.1

CCIO

* 0.9

—

2, 4

CCIO

—



A

±200

Notes:

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

The V referred to in these specifications refers to instantaneous V

CCIO

For V between “0” V and V

. Measured when the driver is tri-stated.

CCIO

and V

may experience excursions above V . However, input signal drivers must comply with the

CCIO

signal quality specifications.

Table 7-9.

PCI Express* DC Specifications

Symbol

Parameter

Min

Typ

Max

Units

Notes

DC Differential Tx Impedance (Gen 1

Only)

—

120



TX-DIFF-DC

DC Differential Tx Impedance (Gen 2

and Gen 3)

—

120



DC Common Mode Rx Impedance

3, 4

RX-DC

DC Differential Rx Impedance (Gen 1

Only)

120

RX-DIFF-DC

PEG_ICOMPO Comp Resistance

PEG_ICOMPI Comp Resistance

24.75

25.25



5, 6

PEG_RCOMPO Comp Resistance

Notes:

Refer to the PCI Express Base Specification for more details.

Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.

DC impedance limits are needed to ensure Receiver detect.

The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to

ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately

and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50  ±20%) must be within the

specified range by the time Detect is entered.

COMP resistance must be provided on the system board with 1% resistors.

PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor. Intel allows using 24.9  1% resistors.

Datasheet, Volume 1

Electrical Specifications

7.11

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between

Intel processors and chipset components to external thermal monitoring devices. The

processor contains a Digital Thermal Sensor (DTS) that reports a relative die

temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

Temperature sensors located throughout the die are implemented as analog-to-digital

converters calibrated at the factory. PECI provides an interface for external devices to

read the DTS temperature for thermal management and fan speed control. More

detailed information may be found in the Platform Environment Control Interface

(PECI) Specification.

7.11.1

PECI Bus Architecture

The PECI architecture based on wired OR bus which the clients (as processor PECI)

can pull up high (with strong drive).

The idle state on the bus is near zero.

Figure 7-1 demonstrates PECI design and connectivity, while the host/originator can be

3rd party PECI host, and one of the PECI clients is the processor PECI device.

Figure 7-1. Example for PECI Host-Clients Connection

V_TT

PECI

C_PECI

<10 pF / Node

Host / Originator

PECI Client

Additional PECI

Clients

Datasheet, Volume 1

Electrical Specifications

7.11.2

DC Characteristics

The PECI interface operates at a nominal voltage set by V

. The DC electrical

CCIO

specifications shown in T a ble 7-10 are used with devices normally operating from a

interface supply. V nominal levels will vary between processor families. All

CCIO

PECI devices will operate at the V

level determined by the processor installed in the

CCIO

system. For specific nominal V

levels, refer to T a ble 7-5.

CCIO

Table 7-10. PECI DC Electrical Limits

Symbol

Definition and Conditions

Min

Max

Units

Notes

Output resistance



Rup

Input Voltage Range

Hysteresis

-0.15

hysteresis

CCIO

0.1 * V

N/A

CCIO

Negative-Edge Threshold Voltage

Positive-Edge Threshold Voltage

Bus Capacitance per Node

Pad Capacitance

0.275 * V

0.500 * V

0.725 * V

CCIO

0.550 * V

CCIO

N/A

0.7

—

bus

Cpad

1.8

Ileak000

Ileak025

Ileak050

Ileak075

Ileak100

leakage current at 0V

0.6

leakage current at 0.25*V

—

0.4

CCIO

leakage current at 0.50*V

leakage current at 0.75*V

—

0.2

—

0.13

0.10

leakage current at V

—

CCIO

Notes:

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

CCIO

The leakage specification applies to powered devices on the PECI bus.

The PECI buffer internal pull up resistance measured at 0.75*V

CCIO.

7.11.3

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design.

Figure 7-2. Input Device Hysteresis

V_TTD

Maximum V_P

PECI High Range

Minimum V_P

Maximum V_N

Minimum

Hysteresis Signal Range

Valid Input

Minimum V_N

PECI Ground

PECI Low Range

§ §

Datasheet, Volume 1

Electrical Specifications

Datasheet, Volume 1

Processor Land and Signal Information

8 Processor Land and Signal

Information

8.1

Processor Land Assignments

The processor land map is shown in Figure 8-1. T a ble 8-1 provides a listing of all

processor lands ordered alphabetically by land name.

Note:

SA_ECC_CB[7:0] and SB_ECC_CB[7:0] Lands are RSVD on Desktop 3rd Generation

Intel Core™ i7/i5 processors.

PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] Lands are RSVD on Desktop

3rd Generation Intel Core™ i7/i5 processors, Desktop Intel Pentium processors, and

Desktop Intel Celeron processors.

Datasheet, Volume 1

Processor Land and Signal Information

Figure 8-1. LGA Socket Land Map

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

BCLK_ITP

BCLK_ITP#

BCLK[0]

C40

D40

Diff Clk

GTL

DMI_TX#[3]

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

FDI_COMPIO

FDI_FSYNC[0]

FDI_FSYNC[1]

FDI_ICOMPO

FDI_INT

AA8

AH1

AH4

AE2

AC5

AE5

AE1

AG3

AC4

AE4

AC8

AC2

AD2

AD4

AD7

AE7

AF3

AG2

AC7

AC3

AD1

AD3

AD6

AE8

AF2

AG1

A38

AU40

AW38

DMI

Analog

CMOS

Analog

CMOS

FDI

BCLK#[0]

BPM#[0]

BPM#[1]

BPM#[2]

BPM#[3]

BPM#[4]

BPM#[5]

BPM#[6]

BPM#[7]

CATERR#

CFG[0]

H40

H38

G38

G40

G39

F38

E40

F40

E37

H36

J36

J37

K36

L36

N35

L37

M36

J38

L35

M38

N36

N38

N39

N37

N40

G37

G36

E39

I/O

GTL

FDI_LSYNC[0]

FDI_LSYNC[1]

FDI_TX[0]

FDI_TX[1]

FDI_TX[2]

FDI_TX[3]

FDI_TX[4]

FDI_TX[5]

FDI_TX[6]

FDI_TX[7]

FDI_TX#[0]

FDI_TX#[1]

FDI_TX#[2]

FDI_TX#[3]

FDI_TX#[4]

FDI_TX#[5]

FDI_TX#[6]

FDI_TX#[7]

NCTF

GTL

FDI

GTL

FDI

CMOS

Async CMOS

DMI

FDI

CFG[1]

FDI

CFG[2]

FDI

CFG[3]

FDI

CFG[4]

FDI

CFG[5]

FDI

CFG[6]

FDI

CFG[7]

FDI

CFG[8]

FDI

CFG[9]

FDI

CFG[10]

FDI

CFG[11]

FDI

CFG[12]

FDI

CFG[13]

CFG[14]

NCTF

CFG[15]

NCTF

CFG[16]

NCTF

CFG[17]

NCTF

DBR#

PE_RX[0]

PCI Express

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

DMI_RX[3]

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

DMI_RX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

DMI_TX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

PE_RX[1]

DMI

PE_RX[2]

DMI

PE_RX[3]

AA4

DMI

PE_RX#[0]

PE_RX#[1]

PE_RX#[2]

PE_RX#[3]

PE_TX[0]

DMI

AA5

DMI

PE_TX[1]

DMI

PE_TX[2]

DMI

PE_TX[3]

AA7

DMI

PE_TX#[0]

PE_TX#[1]

PE_TX#[2]

PE_TX#[3]

DMI

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

PEG_TX[11]

Land # Buffer Type

Dir.

PECI

J35

Async

I/O

PCI Express

CMOS

PEG_COMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_RX#[0]

PEG_RX#[1]

PEG_RX#[2]

PEG_RX#[3]

PEG_RX#[4]

PEG_RX#[5]

PEG_RX#[6]

PEG_RX#[7]

PEG_RX#[8]

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

Analog

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_TX#[11]

PEG_TX#[12]

PEG_TX#[13]

PEG_TX#[14]

PEG_TX#[15]

PM_SYNC

PRDY#

Analog

B11

D12

C10

E10

PCI Express

C14

E13

G13

F11

J13

B12

D11

E38

K38

K40

K32

H34

F36

AB6

AB7

AD37

AE6

AF4

AG4

AJ11

AJ29

AJ30

AJ31

AN20

AP20

AT11

AT14

AU10

AV34

AW34

AY10

C38

C39

Async GTL

N/A

PREQ#

PROC_SEL

PROCHOT#

RESET#

I/O

Async GTL

CMOS

RSVD

C13

E14

G14

F12

J14

RSVD

G10

RSVD

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

RSVD

D38

SA_CS#[1]

SA_CS#[2]

SA_CS#[3]

SA_DQ[0]

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

SA_DQ[4]

SA_DQ[5]

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_DQ[20]

SA_DQ[21]

SA_DQ[22]

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

SA_DQ[32]

SA_DQ[33]

SA_DQ[34]

SA_DQ[35]

SA_DQ[36]

SA_DQ[37]

SA_DQ[38]

SA_DQ[39]

SA_DQ[40]

SA_DQ[41]

SA_DQ[42]

SA_DQ[43]

AV32

AW30

AU33

AJ3

DDR3

RSVD

J33

I/O

RSVD

J34

AJ4

RSVD

AL3

RSVD

K34

AL4

RSVD

AJ2

RSVD

L31

AJ1

RSVD

L33

AL2

RSVD

L34

AL1

RSVD

AN1

AN4

AR3

RSVD

M34

N33

N34

P35

RSVD

AR4

RSVD

AN2

AN3

AR2

RSVD

P37

RSVD

P39

RSVD

R34

AR1

RSVD

R36

AV2

RSVD

R38

AW3

AV5

RSVD

R40

RSVD

J31

AW5

AU2

AU3

AU5

AY5

RSVD

AD34

AD35

K31

RSVD

RSVD_NCTF

SA_BS[0]

SA_BS[1]

SA_BS[2]

SA_CAS#

SA_CK[0]

SA_CK[1]

SA_CK[2]

SA_CK[3]

SA_CK#[0]

SA_CK#[1]

SA_CK#[2]

SA_CK#[3]

SA_CKE[0]

SA_CKE[1]

SA_CKE[2]

SA_CKE[3]

SA_CS#[0]

AV1

AW2

AY3

AY7

AU7

AV9

B39

AY29

AW28

AV20

AV30

AY25

AU24

AW27

AV26

AW25

AU25

AY27

AW26

AV19

AT19

AU18

AV18

AU29

DDR3

AU9

AV7

AW7

AW9

AY9

AU35

AW37

AU39

AU36

AW35

AY36

AU38

AU37

AR40

AR37

AN38

AN37

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

SA_MA[1]

Land # Buffer Type

Dir.

SA_DQ[44]

SA_DQ[45]

SA_DQ[46]

SA_DQ[47]

SA_DQ[48]

SA_DQ[49]

SA_DQ[50]

SA_DQ[51]

SA_DQ[52]

SA_DQ[53]

SA_DQ[54]

SA_DQ[55]

SA_DQ[56]

SA_DQ[57]

SA_DQ[58]

SA_DQ[59]

SA_DQ[60]

SA_DQ[61]

SA_DQ[62]

SA_DQ[63]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_DQS[8]

SA_DQS#[0]

SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

SA_DQS#[5]

SA_DQS#[6]

SA_DQS#[7]

SA_DQS#[8]

SA_ECC_CB[0]

SA_ECC_CB[1]

SA_ECC_CB[2]

SA_ECC_CB[3]

SA_ECC_CB[4]

SA_ECC_CB[5]

SA_ECC_CB[6]

SA_ECC_CB[7]

SA_MA[0]

AR39

AR38

AN39

AN40

AL40

AL37

AJ38

AJ37

AL39

AL38

AJ39

AJ40

AG40

AG37

AE38

AE37

AG39

AG38

AE39

AE40

AK3

DDR3

I/O

AY24

AW24

AW23

AV23

AT24

AT23

AU22

AV22

AT22

AV28

AU21

AT21

AW32

AU20

AT20

AV31

AU32

AU30

AW33

AU28

AW29

AP23

AM24

AW17

AK25

AL21

AL20

AL23

AP21

AL22

AK20

AM22

AN21

AU16

AY15

AW15

AV15

AN25

AN26

AL25

AT26

AG7

DDR3

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_MA[11]

SA_MA[12]

SA_MA[13]

SA_MA[14]

SA_MA[15]

SA_ODT[0]

SA_ODT[1]

SA_ODT[2]

SA_ODT[3]

SA_RAS#

SA_WE#

AP3

SB_BS[0]

SB_BS[1]

SB_BS[2]

SB_CAS#

SB_CK[0]

SB_CK[1]

SB_CK[2]

SB_CK[3]

SB_CK#[0]

SB_CK#[1]

SB_CK#[2]

SB_CK#[3]

SB_CKE[0]

SB_CKE[1]

SB_CKE[2]

SB_CKE[3]

SB_CS#[0]

SB_CS#[1]

SB_CS#[2]

SB_CS#[3]

SB_DQ[0]

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

AW4

AV8

AV37

AP38

AK38

AF38

AV13

AK2

AP2

AV4

AW8

AV36

AP39

AK39

AF39

AV12

AU12

AU14

AW13

AY13

AU13

AU11

AY12

AW12

AV27

I/O

AG8

AJ9

AJ8

AG5

AG6

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

SB_DQ[6]

AJ6

AJ7

DDR3

I/O

SB_DQ[53]

SB_DQ[54]

SB_DQ[55]

SB_DQ[56]

SB_DQ[57]

SB_DQ[58]

SB_DQ[59]

SB_DQ[60]

SB_DQ[61]

SB_DQ[62]

SB_DQ[63]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_DQS[8]

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

SB_DQS#[8]

SB_ECC_CB[0]

SB_ECC_CB[1]

SB_ECC_CB[2]

SB_ECC_CB[3]

SB_ECC_CB[4]

SB_ECC_CB[5]

SB_ECC_CB[6]

SB_ECC_CB[7]

SB_MA[0]

AL31

AM35

AL34

AH35

AH34

AE34

AE35

AJ35

AJ34

AF33

AF35

AH7

DDR3

I/O

SB_DQ[7]

SB_DQ[8]

AL7

SB_DQ[9]

AM7

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

SB_DQ[32]

SB_DQ[33]

SB_DQ[34]

SB_DQ[35]

SB_DQ[36]

SB_DQ[37]

SB_DQ[38]

SB_DQ[39]

SB_DQ[40]

SB_DQ[41]

SB_DQ[42]

SB_DQ[43]

SB_DQ[44]

SB_DQ[45]

SB_DQ[46]

SB_DQ[47]

SB_DQ[48]

SB_DQ[49]

SB_DQ[50]

SB_DQ[51]

SB_DQ[52]

AM10

AL10

AL6

AM6

AL9

AM9

AP7

AR7

AP10

AR10

AP6

AM8

AR8

AN13

AN29

AP33

AL33

AG35

AN16

AH6

AR6

AP9

AR9

AM12

AM13

AR13

AP13

AL12

AL13

AR12

AP12

AR28

AR29

AL28

AL29

AP28

AP29

AM28

AM29

AP32

AP31

AP35

AP34

AR32

AR31

AR35

AR34

AM32

AM31

AL35

AL32

AM34

AL8

AP8

AN12

AN28

AR33

AM33

AG34

AN15

AL16

AM16

AP16

AR16

AL15

AM15

AR15

AP15

AK24

AM20

AM19

AK18

AP19

AP18

AM18

AL18

AN18

AY17

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

SB_MA[10]

SB_MA[11]

SB_MA[12]

SB_MA[13]

SB_MA[14]

SB_MA[15]

SB_ODT[0]

SB_ODT[1]

SB_ODT[2]

SB_ODT[3]

SB_RAS#

SB_WE#

SKTOCC#

SM_DRAMPWROK

SM_DRAMRST#

SM_VREF

TCK

AN23

AU17

AT18

AR26

AY16

AV16

AL26

AP26

AM26

AK26

AP24

AR25

AJ33

AJ19

AW18

AJ22

M40

L40

DDR3

Analog

Async CMOS

DDR3

Analog

TAP

VCC

C19

C21

C22

C24

C25

C27

C28

C30

C31

C33

C34

C36

D13

D14

D15

D16

D18

D19

D21

D22

D24

D25

D27

D28

D30

D31

D33

D34

D35

D36

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E35

F15

F16

PWR

TDI

TAP

TDO

L39

TAP

THERMTRIP#

TMS

G35

L38

Asynch CMOS

TAP

TRST#

UNCOREPWRGOOD

VCC

J39

TAP

J40

Async CMOS

PWR

A12

VCC

A13

PWR

VCC

A14

PWR

VCC

A15

PWR

VCC

A16

PWR

VCC

A18

PWR

VCC

A24

PWR

VCC

A25

PWR

VCC

A27

PWR

VCC

A28

PWR

VCC

B15

PWR

VCC

B16

PWR

VCC

B18

PWR

VCC

B24

PWR

VCC

B25

PWR

VCC

B27

PWR

VCC

B28

PWR

VCC

B30

PWR

VCC

B31

PWR

VCC

B33

PWR

VCC

B34

PWR

VCC

C15

PWR

VCC

C16

PWR

VCC

C18

PWR

100

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

VCC

F18

F19

F21

F22

F24

F25

F27

F28

F30

F31

F32

F33

F34

G15

G16

G18

G19

G21

G22

G24

G25

G27

G28

G30

G31

G32

G33

H13

H14

H15

H16

H18

H19

H21

H22

H24

H25

H27

H28

H30

H31

H32

J12

PWR

VCC

J21

J22

PWR

Analog

PWR

VCC

J24

VCC

J25

VCC

J27

VCC

J28

VCC

J30

VCC

K15

K16

K18

K19

K21

K22

K24

K25

K27

K28

K30

L13

L14

L15

L16

L18

L19

L21

L22

L24

L25

L27

L28

L30

M14

M15

M16

M18

M19

M21

M22

M24

M25

M27

M28

M30

A36

AB33

AB34

AB35

VCC

J15

VCC_SENSE

VCCAXG

J16

J18

J19

Datasheet, Volume 1

101

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

VCCIO

Land # Buffer Type

Dir.

VCCAXG

VCCAXG_SENSE

VCCIO

AB36

AB37

AB38

AB39

AB40

AC33

AC34

AC35

AC36

AC37

AC38

AC39

AC40

T33

PWR

Analog

PWR

AG33

AJ16

AJ17

AJ26

AJ28

AJ32

AK15

AK17

AK19

AK21

AK23

AK27

AK29

AK30

PWR

N/A

VCCIO

VCCIO_SEL

VCCIO_SENSE

VCCPLL

VCCSA

T34

T35

D10

T36

T37

T38

T39

T40

U33

U34

U35

U36

U37

U38

U39

U40

W33

W34

W35

W36

W37

W38

Y33

M13

Y34

Y35

Y36

Y37

Y38

P33

AB4

AK11

AK12

H10

H11

H12

L32

Analog

PWR

A11

VCCIO

AA3

AB8

AF8

VCCIO

102

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

VCCSA

VCCSA_SENSE

VCCSA_VID

VDDQ

VIDALERT#

VIDSCLK

VIDSOUT

VSS

J10

K10

PWR

Analog

CMOS

PWR

CMOS

GND

VSS

AA6

AB5

GND

K11

AC1

L11

AC6

L12

AD33

AD36

AD38

AD39

AD40

AD5

M10

M11

M12

P34

AJ13

AJ14

AJ20

AJ23

AJ24

AR20

AR21

AR22

AR23

AR24

AU19

AU23

AU27

AU31

AV21

AV24

AV25

AV29

AV33

AW31

AY23

AY26

AY28

A37

AD8

AE3

AE33

AE36

AF1

AF34

AF36

AF37

AF40

AF5

AF6

AF7

AG36

AH2

AH3

AH33

AH36

AH37

AH38

AH39

AH40

AH5

AH8

AJ12

AJ15

AJ18

AJ21

AJ25

AJ27

AJ36

AJ5

C37

B37

I/O

A17

VSS

A23

VSS

A26

VSS

A29

VSS

A35

VSS

AA33

AA34

AA35

AA36

AA37

AA38

AK1

VSS

AK10

AK13

AK14

AK16

AK22

VSS

Datasheet, Volume 1

103

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

VSS

AK28

AK31

AK32

AK33

AK34

AK35

AK36

AK37

AK4

GND

VSS

AN22

AN24

AN27

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN5

GND

AK40

AK5

AK6

AN6

AK7

AN7

AK8

AN8

AK9

AN9

AL11

AL14

AL17

AL19

AL24

AL27

AL30

AL36

AL5

AP1

AP11

AP14

AP17

AP22

AP25

AP27

AP30

AP36

AP37

AP4

AM1

AM11

AM14

AM17

AM2

AP40

AP5

AR11

AR14

AR17

AR18

AR19

AR27

AR30

AR36

AR5

AM21

AM23

AM25

AM27

AM3

AM30

AM36

AM37

AM38

AM39

AM4

AT1

AT10

AT12

AT13

AT15

AT16

AT17

AT2

AM40

AM5

AN10

AN11

AN14

AN17

AN19

AT25

AT27

104

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

VSS

AT28

AT29

AT3

GND

VSS

AY8

B10

B13

B14

B17

B23

B26

B29

B32

B35

B38

GND

AT30

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38

AT39

AT4

C11

C12

C17

C20

C23

C26

C29

C32

C35

AT40

AT5

AT6

AT7

AT8

AT9

AU1

AU15

AU26

AU34

AU4

D17

AU6

D20

D23

D26

D29

D32

D37

D39

AU8

AV10

AV11

AV14

AV17

AV3

AV35

AV38

AV6

AW10

AW11

AW14

AW16

AW36

AW6

AY11

AY14

AY18

AY35

AY4

E11

E12

E17

E20

E23

E26

E29

E32

E36

AY6

Datasheet, Volume 1

105

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

Land Name

Land # Buffer Type

Dir.

VSS

F10

F13

F14

F17

GND

VSS

K12

K13

K14

K17

GND

F20

F23

F26

F29

F35

F37

F39

K20

K23

K26

K29

K33

K35

K37

K39

G11

G12

G17

G20

G23

G26

G29

G34

L10

L17

L20

L23

L26

L29

M17

M20

M23

M26

M29

M33

M35

M37

M39

H17

H20

H23

H26

H29

H33

H35

H37

H39

J11

J17

J20

J23

J26

J29

J32

P36

P38

P40

R33

R35

R37

106

Datasheet, Volume 1

Processor Land and Signal Information

Table 8-1.

Processor Land List by

Land Name

Land # Buffer Type

Dir.

VSS

R39

GND

Analog

VSS

V33

V34

V35

V36

V37

V38

V39

V40

VSS

VSS_NCTF

VSS_SENSE

VSSAXG_SENSE

VSSIO_SENSE

AV39

AY37

B36

M32

AB3

§ §

Datasheet, Volume 1

107

Processor Land and Signal Information

108

Datasheet, Volume 1

DDR Data Swizzling

9 DDR Data Swizzling

To achieve better memory performance and timing, Intel Design performed DDR Data

pin swizzling that allows a better use of the product across different platforms.

Swizzling has no effect on functional operation and is invisible to the operating

system/software.

However, during debug, swizzling needs to be taken into consideration. Therefore,

swizzling information is presented in this chapter. When placing a DIMM logic analyzer,

the design engineer must pay attention to the swizzling table in order to be able to

debug memory efficiently.

Datasheet, Volume 1

109

DDR Data Swizzling

Table 9-1.

DDR Data Swizzling

Table – Channel A

Table 9-1.

DDR Data Swizzling

Table – Channel A

Land Name

Land #

MC Land Name

Land Name

Land #

MC Land Name

SA_DQ[0]

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

SA_DQ[4]

SA_DQ[5]

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_DQ[20]

SA_DQ[21]

SA_DQ[22]

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

SA_DQ[32]

SA_DQ[33]

SA_DQ[34]

SA_DQ[35]

SA_DQ[36]

SA_DQ[37]

SA_DQ[38]

SA_DQ[39]

AJ3

AJ4

DQ06

DQ05

DQ01

DQ00

DQ04

DQ07

DQ02

DQ03

DQ15

DQ12

DQ08

DQ09

DQ14

DQ13

DQ10

DQ11

DQ21

DQ20

DQ16

DQ19

DQ23

DQ22

DQ18

DQ17

DQ28

DQ30

DQ27

DQ26

DQ31

DQ29

DQ24

DQ25

DQ36

DQ37

DQ32

DQ33

DQ38

DQ39

DQ35

DQ34

SA_DQ[40]

SA_DQ[41]

SA_DQ[42]

SA_DQ[43]

SA_DQ[44]

SA_DQ[45]

SA_DQ[46]

SA_DQ[47]

SA_DQ[48]

SA_DQ[49]

SA_DQ[50]

SA_DQ[51]

SA_DQ[52]

SA_DQ[53]

SA_DQ[54]

SA_DQ[55]

SA_DQ[56]

SA_DQ[57]

SA_DQ[58]

SA_DQ[59]

SA_DQ[60]

SA_DQ[61]

SA_DQ[62]

SA_DQ[63]

SA_DQ[64]

SA_DQ[65]

SA_DQ[66]

SA_DQ[67]

SA_DQ[68]

SA_DQ[69]

SA_DQ[70]

SA_DQ[71]

AR40

AR37

AN38

AN37

AR39

AR38

AN39

AN40

AL40

AL37

AJ38

AJ37

AL39

AL38

AJ39

AJ40

AG40

AG37

AE38

AE37

AG39

AG38

AE39

AE40

AU12

AU14

AW13

AY13

AU13

AU11

AY12

AW12

DQ44

DQ45

DQ43

DQ42

DQ46

DQ47

DQ40

DQ41

DQ52

DQ55

DQ51

DQ50

DQ54

DQ53

DQ48

DQ49

DQ61

DQ63

DQ59

DQ58

DQ62

DQ60

DQ57

DQ56

DQ71

DQ66

DQ67

DQ65

DQ70

DQ69

DQ64

DQ68

AL3

AL4

AJ2

AJ1

AL2

AL1

AN1

AN4

AR3

AR4

AN2

AN3

AR2

AR1

AV2

AW3

AV5

AW5

AU2

AU3

AU5

AY5

AY7

AU7

AV9

AU9

AV7

AW7

AW9

AY9

AU35

AW37

AU39

AU36

AW35

AY36

AU38

AU37

110

Datasheet, Volume 1



DDR Data Swizzling

Table 9-2.

DDR Data Swizzling

table – Channel B

Table 9-2.

DDR Data Swizzling

table – Channel B

Land Name

Land #

MC Land Name

Land Name

Land #

MC Land Name

SB_DQ[0]

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SB_DQ[7]

SB_DQ[8]

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

SB_DQ[32]

SB_DQ[33]

SB_DQ[34]

SB_DQ[35]

SB_DQ[36]

SB_DQ[37]

SB_DQ[38]

SB_DQ[39]

AG7

AG8

DQ04

DQ05

DQ02

DQ03

DQ07

DQ06

DQ00

DQ01

DQ12

DQ13

DQ08

DQ10

DQ15

DQ14

DQ11

DQ09

DQ20

DQ21

DQ18

DQ16

DQ22

DQ23

DQ19

DQ17

DQ30

DQ24

DQ26

DQ27

DQ31

DQ25

DQ28

DQ29

DQ39

DQ37

DQ33

DQ34

DQ38

DQ36

DQ35

DQ32

SB_DQ[40]

SB_DQ[41]

SB_DQ[42]

SB_DQ[43]

SB_DQ[44]

SB_DQ[45]

SB_DQ[46]

SB_DQ[47]

SB_DQ[48]

SB_DQ[49]

SB_DQ[50]

SB_DQ[51]

SB_DQ[52]

SB_DQ[53]

SB_DQ[54]

SB_DQ[55]

SB_DQ[56]

SB_DQ[57]

SB_DQ[58]

SB_DQ[59]

SB_DQ[60]

SB_DQ[61]

SB_DQ[62]

SB_DQ[63]

SB_DQ[64]

SB_DQ[65]

SB_DQ[66]

SB_DQ[67]

SB_DQ[68]

SB_DQ[69]

SB_DQ[70]

SB_DQ[71]

AP32

AP31

AP35

AP34

AR32

AR31

AR35

AR34

AM32

AM31

AL35

AL32

AM34

AL31

AM35

AL34

AH35

AH34

AE34

AE35

AJ35

AJ34

AF33

AF35

AL16

AM16

AP16

AR16

AL15

AM15

AR15

AP15

DQ43

DQ44

DQ42

DQ40

DQ47

DQ45

DQ41

DQ46

DQ52

DQ55

DQ50

DQ53

DQ51

DQ54

DQ48

DQ49

DQ60

DQ61

DQ58

DQ56

DQ62

DQ63

DQ57

DQ59

DQ66

DQ64

DQ68

DQ69

DQ67

DQ65

DQ70

DQ71

AJ9

AJ8

AG5

AG6

AJ6

AJ7

AL7

AM7

AM10

AL10

AL6

AM6

AL9

AM9

AP7

AR7

AP10

AR10

AP6

AR6

AP9

AR9

AM12

AM13

AR13

AP13

AL12

AL13

AR12

AP12

AR28

AR29

AL28

AL29

AP28

AP29

AM28

AM29

§ §

Datasheet, Volume 1

111

DDR Data Swizzling

112

Datasheet, Volume 1

Intel D845EPT2 User Manual
Jenn Air JGC8430BDB User Manual
JVC AV 21L11 AV 21L31 AV 25L31 AV 29L31 AV 21L31B AV 25L31B AV 29L31B User Manual
JVC AV 2107YE User Manual
Mitsubishi Electronics CK 35308 User Manual
Philips 21PT5457 User Manual
Philips 28PW6332 User Manual
Philips 160EL1 User Manual
Philips 190PS User Manual
Philips Brilliance 150P2E User Manual