Intel Computer Hardware IXP43X User Manual

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Intel IXP43X Product Line of  
Network Processors  
Hardware Design Guidelines  
April 2007  
Document Number: 316844; Revision: 001US  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
3.13.2 Clock Oscillator ...................................................................................... 50  
3.13.3 Recommendations for Crystal Selection..................................................... 51  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
7.3.3.2 Data and Control Groups............................................................82  
9
USB Host Down Stream Interface Example...................................................................35  
10 UTOPIA Interface Example.........................................................................................40  
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31 DDR - Write Preamble/Postamble Duration.................................................................. 77  
33 DDRII Data and Control Simulation Results: DQ and DQS signals ................................... 83  
34 DDRII Command Simulation Results: ADDRESS signals................................................. 84  
27 Supported DDRI 16-bit SDRAM Configurations ............................................................. 73  
28 Supported DDRII 16-bit SDRAM Configurations............................................................ 74  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Revision History  
Date  
Revision  
Description  
April 2007  
001  
Initial release  
§ §  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
1.0  
Introduction  
This design guide provides recommendations for hardware and system designers who  
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are developing with the Intel IXP43X Product Line of Network Processors. This  
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document should be used in conjunction with the Intel IXP43X Product Line of  
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Network Processors Datasheet and sample schematics provided for the Intel IXP435  
Multi-Service Residential Gateway Reference Platform.  
Design recommendations are necessary to meet the timing and signal quality  
specifications. The guidelines recommended in this document are based on experience  
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and simulation work done at Intel while developing the Intel IXP435 Multi-Service  
Residential Gateway Reference Platform. These recommendations are subject to  
change.  
Note:  
This document discusses all features supported on the IXP43X product line of network  
processors. A subset of these features is supported by certain processors in the IXP43X  
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network processors, such as the Intel IXP432 Network Processor. Refer to the Intel  
IXP43X Product Line of Network Processors Datasheet for detailed information on  
various features listed by processor.  
1.1  
Content Overview  
Chapter Name  
Description  
Conventions used in this manual and related documentation  
System architectural block diagram and system memory map  
Chapter 2.0, “System Architecture”  
Graphical representation of most common peripheral interfaces  
General PCB design practice and layer stack-up description  
Chapter 4.0, “General PCB Guide”  
More specific layout and routing recommendations for board  
designers  
Considerations”  
Board-design recommendations when implementing PCI  
interface  
Board-design recommendations when implementing  
DDRII/I memory interface  
Chapter 7.0, “DDRII / DDRI SDRAM”  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
1.2  
Related Documentation  
The reader of this design guide should also be familiar with the material and concept  
presented in the following documents:  
Title  
Document #  
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Intel IXP43X Product Line of Network Processors Datasheet  
316842  
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Intel IXP43X Product Line of Network Processors Developer’s  
316843  
316845  
Manual  
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Intel IXP43X Product Line of Network Processors: Migrating from  
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the Intel IXP42X Product Line  
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Intel IXP400 Software Programmer’s Guide  
252539  
273795  
273473  
__  
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Intel IXP400 Software Specification Update  
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Intel XScale™ Core Developer’s Manual  
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Intel StrataFlash Embedded Memory (P30) Application Note  
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Intel XScale Microarchitecture Technical Summary  
Double Data Rate (DDR) SDRAM Specification, 2004; JEDEC Solid  
State Technology Association  
JESD79D  
IEEE 802.3 Specification  
N/A  
N/A  
N/A  
N/A  
PCI Local Bus Specification, Rev. 2.2  
Universal Serial Bus Specification, Revision 2.0  
UTOPIA Level 2 Specification, Revision 1.0  
1.3  
Table 1 lists the acronyms and abbreviations used in this guide.  
Table 1.  
List of Acronyms and Abbreviations (Sheet 1 of 2)  
Term  
Explanation  
AHB  
APB  
ATM  
DDR  
EMI  
GPIO  
HSS  
IP  
Advanced High-Performance Bus  
Advanced Peripheral Bus  
Asynchronous Transfer Mode  
Double Data Rate  
Electro-Magnetic Interference  
General Purpose Input/Output  
High Speed Serial  
Internet Protocol  
ISA  
LAN  
MII  
Instruction Set Architecture  
Local Area Network  
Media-Independent Interface  
Network Processor Engine  
Printed Circuit Board  
NPE  
PCB  
PCI  
Peripheral Component Interface  
Physical Layer Interface  
Phase-Locked Loop  
PHY  
PLL  
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Table 1.  
List of Acronyms and Abbreviations (Sheet 2 of 2)  
Term  
Explanation  
PMU  
SME  
SSP  
Performance Monitoring Unit  
Small-to-Medium Enterprise  
Synchronous Serial Protocol  
UART  
USB  
VTT  
Universal Asynchronous Receiver-Transmitter  
Universal Serial Bus  
Termination Voltage Supply  
1.4  
Overview  
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The Intel IXP43X Product Line of Network Processors is a highly integrated device,  
capable of interfacing with most common industry standard peripherals, required for  
high-performance control applications.  
Note:  
This document discusses all features supported on the IXP43X network processors.  
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Refer to the Intel IXP43X Product Line of Network Processors Datasheet for details on  
feature support listed by processor.  
Some of the key features of the IXP43X network processors, when used as a  
single-chip solution for embedded applications are as follows:  
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*
• Intel XScale Processor (compliant with Intel StrongARM architecture) up to 667  
MHz  
• 32-bit PCI interface Master/Target 33 MHz  
Two Universal Serial Bus (USB) V2.0 Host Controller  
• DDRI-266 SDRAM or DDRII-400 SDRAM—  
— Support for 16 MB, minimum for DDR II/I, 32 MB minimum for DDRII-400;  
1 GB, maximum for DDR II/I, 512 MBs maximum for DDRII-400  
— User-enabled ECC.  
• 16bit Data / 24bit Address Expansion Bus Interface  
• One UART interface  
Two NPEs  
• UTOPIA Level 2 Interface  
• Synchronous Serial Port Interface (SSP)  
• One High-Speed Serial Port Interfaces (HSS)  
Note 1  
• Network interfaces that can be configured in the following manner:  
Two MII interfaces  
— One MII interface + 1 UTOPIA Level 2 interface  
Note 1  
• MII interfaces are:  
— 802.3 MII interfaces  
— Single MDIO interface to control the MII interfaces  
Note 1  
• UTOPIA Level 2 Interface is:  
— Eight-bit interface  
— Up to 33-MHz clock speed  
— Five transmit and five receive address lines  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
• 16 GPIO (General Purpose Input Output)  
• Packaging  
— 460-pin PBGA  
— 31 mm by 31 mm  
— Commercial temperature (0° to 70° C)  
— Lead free support  
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Refer to the Intel IXP43X Product Line of Network Processors Datasheet for complete  
feature list and block diagram description.  
Note:  
1. This feature requires Intel-supplied software. To determine if this feature is enabled  
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in a particular software release, refer to the Intel IXP400 Software Programmer’s  
Guide.  
A block diagram of all major internal hardware components of IXP43X network  
processors is shown in Figure 1. The illustration also shows how the components  
interface with each other through the various bus interfaces such as the North AHB,  
South AHB, and APB.  
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Figure 1.  
Intel IXP435 Network Processor Block Diagram  
HSS  
UTOPIA 2/ MII  
NPE A  
NPE C  
North AHB133. 32 MHz x32bits  
MII  
AES/ 3DES/  
DES/  
SHA/ MD-5  
North AHB  
Arbiter  
SSP  
High Speed  
UART  
921 Kbaud  
16 GPIO  
GPIO  
16/ 32 BITS  
+ ECC  
AHB  
Slave /  
APB  
Interrupt  
Controller  
DDR 266 /  
DDRII 400  
DDRII/ I MEMORY  
CONTROLLER  
UNIT  
QUEUE  
MANAGER  
AHB/ AHB  
BRIDGE  
Master  
BRIDGE  
266/ 400  
IBPMU  
Timers  
South AHB133. 32 MHz x32 bits  
South AHB  
Arbiter  
USB Port  
USB Port  
HOST  
CONTROLLER  
VERSION2.0  
EXPANSION  
BUS Controller  
8/16 bit 80MHz  
PCI  
HOST  
CONTROLLER  
VERSION 2.0  
CONTROLLER  
32 bit 33 MHz  
XScale Processor  
32 KB I - CACHE  
32KB D - CACHE  
UTMI  
UTMI  
2KB MINI D- CACHE  
266/400/533/667 MHz  
2.0 PHY  
2. 0 PHY  
Bus Arbiters  
Slave Only  
Master on South AHB  
Master on North AHB  
AHB Slave APB Master  
/
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Note:  
Figure 1 shows the Intel IXP435 Network Processor. For details on feature and SKU  
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support listed by processor, see the Intel IXP43X Product Line of Network Processors  
Datasheet.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
1.5  
Typical Applications  
• SOHO-Small Business/Residential  
• Modular Router  
• Wireless Gateway(802.11a/b/g)  
• Network-Attached Storage  
• Wired/Wireless RFID Readers  
• Digital Media Adapter  
• Digital Media Player  
• VoIP Router  
• Video Phone  
• Secure Gateway/Router  
• Network Printer  
• Wireless Media Gateway  
• IP Set Top box  
§ §  
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2.0  
System Architecture  
2.1  
System Architecture Description  
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The Intel IXP43X Product Line of Network Processors is a multifunction processor that  
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integrates the Intel XScale Processor (ARM* architecture compliant) with highly  
integrated peripheral controllers and network processor engines.  
The processor is a highly integrated design, manufactured with Intel’s 0.13-µm  
production semiconductor process technology. This process technology, along with  
numerous, dedicated function peripheral interfaces and many features with the Intel  
XScale processor, addresses the needs of many system applications and helps reduce  
system costs. The processors can be configured to meet many system application and  
Figure 2 illustrates one of the many applications for which the IXP43X network  
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processors can be implemented. For detailed functional description, see the Intel  
IXP43X Product Line of Network Processors Developer’s Manual.  
2.2  
System Memory Map  
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Refer to the Intel IXP43X Product Line of Network Processors Developer’s Manual for  
a complete memory map and register description of each individual module.  
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Figure 2.  
Example: Intel IXP43X Product Line of Network Processors System Block  
Diagram  
JTAG  
Header  
Flash  
32 Mbyte  
CB[7:0]  
D[31:0]  
BA[1:0]  
A[13:0]  
DDRII/I  
CS_N0  
SDRAM  
Max 1 Gbyte  
D[15:0]  
A[23:0]  
RAS, CAS, WE, CS,CLK  
Board  
Configuration  
Reset Logic  
SSP  
SLIC/CODEC or  
T1/E1/J1 Framer  
Intel® IXP43X Product  
Line of Network  
Processors  
HSS 0  
LCD/LED  
Diagnostics  
Display  
Buff  
SSP  
CODEC or  
A/D  
xDSL  
RS232  
Serial Port 0  
UTOPIA Level 2  
DB9  
PLL  
OSC  
Clock Buffer  
RJ45  
Port 0  
10/100  
PHYs  
2-MII  
Ethernet  
Clocks  
PCI  
Clock  
Up to 2 Ports  
RJ45  
Port 1  
5 V  
USB Host  
Connector  
USB v2.0  
USB v2.0  
3.3 V  
2.5/1.8 V  
1.3 V  
Power Supply  
USB Host  
Connector  
Transparent PCI Bridge  
cPCI Bus  
B4835-003  
§ §  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
3.0  
General Hardware Design Considerations  
This chapter contains information for implementing and interfacing with major  
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hardware blocks of the Intel IXP43X Product Line of Network Processors. Such blocks  
include DDRII/I SDRAM, Flash, Ethernet PHYs, UART and other peripherals interfaces.  
Signal definition tables list resistor recommendations for pull-ups and pull-downs.  
Features disabled by a specific part number, do not require pull-ups or pull-downs.  
Therefore, all pins can be left unconnected. Features enabled by a specific part number  
and required to be Soft Fuse-disabled, only require pull-ups or pull-downs in the  
clock-input signals. Other conditions can require pull-up or pull-down resistors for  
configuration purposes at power on or reset. In the same way, open-drain outputs must  
be pulled high.  
Warning:  
With the exception of USB_V5REF all other I/O pins of the IXP43X network processors  
are not 5.0-V tolerant.  
Table 2 gives the legend for interpreting the Type field used in the signal-definition  
tables that are covered in this chapter.  
Table 2.  
Signal Type Definitions  
Symbol  
Description  
Input pin only  
I
O
Output pin only  
Pin can be an input or output  
Open-drain pin  
Tri-State pin  
I/O  
OD  
TRI  
PWR  
GND  
Power pin  
Ground pin  
3.1  
Soft Fusible Features  
Soft Fuse Enable/Disable is a method to enable or disable features in hardware,  
virtually disconnecting the hardware modules from the processor.  
Some of the features offered in the IXP43X product line of network processors can be  
Soft Fuse Enabled/Disabled during boot. It is recommended that if a feature is not used  
in the design, the feature be soft disabled. This helps reduce power and maintain the  
part running at a cooler temperature. When Soft Fuse Disabled, a pull-up resistor must  
be connected to each clock input pins of the disabled feature interface. All other signals  
can be left unconnected.  
Soft Fuse Enable/Disable can be done by writing to EXP_UNIT_FUSE_RESET register.  
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For more information refer to the Intel IXP43X Product Line of Network Processors  
Developer’s Manual and review the register description.  
Table 3.  
Soft Fusible Features (Sheet 1 of 2)  
Name  
Description  
The complete bus must be enabled or disable.  
PCI  
HSS0  
Can only be disable as a pair.  
while enabling UTOPIA, MACs on NPE A is disabled.  
while enabling MACs on NPE A, UTOPIA is disabled.  
UTOPIA  
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Table 3.  
Soft Fusible Features (Sheet 2 of 2)  
Name  
Description  
ETHERNET  
USB Host  
DDR ECC  
Can enable MII MACs. Enable of MACs can be separately done per each NPE.  
Each USB can be Enable separately.  
ECC can be enabled or disabled separately from the rest of the DDR interface.  
3.2  
DDRII/I SDRAM Interface  
The IXP43X network processors support unbuffered, DDRI-266 or DDRII-400 SDRAM  
technology, capable of addressing two memory banks (one bank per CS). Each bank  
can be configured to support 32/64/128/256/512-Mbyte for a total combined memory  
support of 1 Gbyte.  
The IXP43X network processors integrate a high-performance, multi-ported Memory  
Controller Unit (MCU) to provide a direct interface with its local memory subsystem.  
The MCU supports:  
• DDR II/I or DDRII-400 SDRAM  
• 128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support  
• Supports 256/512-Mbit technologies for the DDRII-400  
• Only unbuffered DRAM support (No registered DRAM support)  
• Dedicated port for Intel XScale processor to the DDRII/DDRI SDRAM  
• Between 32 MBs and 1-GB of 32-bit DDRI SDRAM  
• Between 64MBs and 512 MBs of 32-bit DDRII SDRAM  
• 16MB for 16-bit memory systems for DDRI SDRAM (non-ECC) supporting 128-Mbit  
technology only  
• 32MB for 16-bit memory systems for DDRII SDRAM (non-ECC) supporting 256-Mbit  
technology only  
• Single-bit error correction, multi-bit detection support (ECC)  
• 32-bit, 40-bit wide memory interfaces (non-ECC and ECC support), and 16-bit wide  
memory interfaces (non-ECC)  
The DDRII/DDRI SDRAM interface provides a direct connection to a high-bandwidth  
and reliable memory subsystem. The DDRII/DDRI SDRAM interface is a 16 or  
32-bit-wide data path.  
The device supports non-ECC and ECC for error correction, which can be enable or  
disable by software as required. Banks have a bus width of 32 bits for non ECC or  
40 bits for ECC enable (32-bit data + 8-bit ECC).  
An 8-bit Error Correction Code (ECC) across each 32-bit word improves system  
reliability. It is important to note that ECC is also referred to as CB in many DIMM  
specifications. The pins on the IXP43X network processors are called  
DDR_CB[7:0]. ECC is only implemented in the 32-bit mode of operation, while the  
algorithm used to generate the 8-bit ECC is implemented over 64-bit.  
The ECC circuitry is designed to operate always on a 64-bit data and when operating in  
32-bit mode, the upper 32 bits are driven to zeros internally. To summarize the impact  
to the customer, the full 8 bits of ECC is stored and read from a memory array for the  
ECC logic to work. An 8-bit-wide memory is used when implementing ECC.  
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The memory controller only corrects single bit ECC errors on read cycles. The ECC is  
stored into the DDRII/DDRI SDRAM array along with the data and is checked when the  
data is read. If the code is incorrect, the MCU corrects the data before reaching the  
initiator of the read. ECC error scrubbing is done with software. User-defined fault  
correction software is responsible for The value written back into the memory location  
contains the 32-bit word with the modified byte and the new ECC value.  
®
General DDRII/I SDRAM routing guidelines can be found in Section 7.3.3, “Routing  
Guidelines” on page 82. For more detailed information, see the PC266 and PC400 DDR  
SDRAM specification.  
3.2.1  
Signal Interface  
Table 4.  
DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)  
VTT  
Terminatio  
n
Type  
Field  
Name  
Device-Pin Connection  
Description  
Connect a pair of differential clock  
signals to every device; When  
using both banks, daisy chain  
devices with same data bit  
sequence.  
DDRII/I SDRAM Clock Out — Provides the  
positive differential clocks to the external  
SDRAM memory subsystem.  
D_CK[2:0] /  
DDR_CK[2:0]  
O
No  
DDRII/I SDRAM Clock Out — Provides the  
negative differential clocks to the external  
SDRAM memory subsystem.  
D_CK_N[2:0] /  
DDR_CK_N[2:0]  
O
O
O
O
O
Same as above  
No  
Yes  
Yes  
Yes  
Yes  
Chip Select — Must be asserted for all  
transactions to the DDRII/I SDRAM device.  
One per bank.  
D_CS_N[1:0] /  
C_CS_N[1:0]  
Use the same CS to control 32-bit  
data + 8-bit ECC, per bank  
The RAS signal must be connected  
to each device in a daisy chain  
manner  
Row Address Strobe — Indicates that the  
current address on D_MA[13:0] /  
DDR_MA[13:0] is the row.  
D_RAS_N /  
DDR_RAS_N  
The CAS signal must be connected  
to each device in a daisy chain  
manner  
Column Address Strobe — Indicates that the  
current address on D_MA[13:0] /  
DDR_MA[13:0] is the column.  
D_CAS_N /  
DDR_CAS_N  
The WE signal must be connected  
to each device in a daisy chain  
manner  
Write Strobe — Defines whether or not the  
current operation by the DDRII/I SDRAM is to  
be a read or a write.  
D_WE_N / DDR_WE_N  
Data Bus Mask — Controls the DDRII/I SDRAM  
data input buffers. Asserting D_WE_N/  
DDR_WE_N causes the data on D_DQ[31:0]/  
DDR_DQ[31:0] and D_CB[7:0]/DDR_CB[7:0]  
to be written into the DDRII/I SDRAM devices.  
Connect to each DM device pin.  
For the 8-bit devices connect one  
DM signal per device.  
D_DM[4:0] /  
DDR_DM[4:0]  
O
O
Yes  
Yes  
For the 16-bit devices connect two  
DM signal per device (depending  
on how many data bits are being  
used).  
D_DM[4:0]/DDR_DM[4:0] controls this  
operation on a per-byte basis. D_DM[3:0]/  
DDR_DM[3:0] are intended to correspond to  
each byte of a word of data. D/DM[4]/  
DDR_DM[4] is intended to be utilized for the  
ECC byte of data.  
DDRII/I SDRAM Bank Selects — Controls which  
of the internal DDRII/I SDRAM banks to read  
or write. D_BA[1:0]/DDR_BA[1:0] are used for  
all technology types supported.  
The BA signals must be connected  
to each device in a daisy chain  
manner.  
D_BA[1:0] /  
DDR_BA[1:0]  
Address bits 13 through 0 — Indicates the row  
or column to access depending on the state of  
D_RAS_N/DDR_RAS_N and D_CAS_N/  
DDR_CAS_N.  
All address signals must be  
connected to each device in a  
daisy chain manner.  
D_MA[13:0] /  
DDR_MA[13:0]  
O
Yes  
Yes  
D_DQ[31:0] /  
DDR_DQ[31:0]  
Must be connected in parallel to  
achieve a 32-bit bus width.  
I/O  
Data Bus — 32-bit wide data bus.  
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Table 4.  
DDRII/I SDRAM Interface Pin Description (Sheet 2 of 2)  
VTT  
Terminatio  
n
Type  
Field  
Name  
Device-Pin Connection  
Description  
ECC Bus — Eight-bit error correction code  
which accompanies the data on D_DQ[31:0]/  
DDR_DQ[31:0].  
When ECC is disabled and not being used in a  
system design, these signals can be left un-  
connected.  
D_CB[7:0] /  
I/O  
I/O  
Connect to ECC memory devices.  
Yes  
Yes  
DDR_CB[7:0]  
Data Strobes Differential — Strobes that  
accompany the data to be read or written from  
the DDRII/I SDRAM devices. Data is sampled  
on the negative and positive edges of these  
strobes. D_DQS[3:0]/DDR_DQS[3:0] are  
intended to correspond to each byte of a word  
of data. D_DQS[4]/DDR_DQS[4] is intended to  
be utilized for the ECC byte of data.  
Connect DQS[3:0] to devices with  
data signals and DQS[4] to  
devices with ECC signals.  
D_DQS[4:0] /  
DDR_DQS[4:0]  
Clock enables — One clock after D_CKE[1:0]/  
DDR_CKE[1:0] is de-asserted, data is latched  
on D_DQ[31:0]/DDR_DQ[31:0] and  
D_CB[7:0]/DDR_CB[7:0]. Burst counters  
within DDRII/I SDRAM device are not  
incremented. De-asserting this signal places  
the DDRII/I SDRAM in self-refresh mode. For  
normal operation, D_CKE[1:0]/DDR_CKE[1:0]  
must be asserted.  
Use one CKE per bank, never mix  
the CKE on the same bank. Use  
CKE[0] for bank0 and CKE[1] for  
bank1  
D_CKE[1:0] /  
DDR_CKE[1:0]  
O
Yes  
On Die Termination Control — Turns on DDR II  
SDRAM termination during writes.  
D_ODT[1:0]  
D_RES[2:1]  
Compensation for DDR OCD (analog) DDRII  
mode only. This function is not enable and  
special connection is required.  
Refer to Figure 27  
Refer to Figure 27  
Refer to Figure 27  
Compensation Voltage Reference (analog) for  
DDR driver slew rate control connected  
through a resistor to D_CRES0.  
D_SLWCRES  
D_IMPCRES  
Compensation Voltage Reference (analog) for  
DDR driver impedance control connected  
through a resistor to D_CRES0.  
Analog VSS Ref Pin (analog) both D_SLWCRES  
and D_IMPCRES signals connect to this pin  
through a reference resistor. For DDRII/I  
respectively:  
Tied off to a - 285 / 387Ohm Resistor connected to  
D_CRES0  
O
Tied off to a resistor  
resistor  
DDR_IMPCRES used for process and  
temperature adjustments.  
- 825 / 845Ohm Resistor connected to  
DDR_SLWCRES used for process and  
temperature adjustments.  
DDRII/IDDRII/I SDRAM Voltage Reference — is  
used to supply the reference voltage to the  
differential inputs of the memory controller  
pins.  
D_VREF / DDR_VREF  
I
VCCDDR/2  
VCCDDR/2  
3.2.2  
DDRII/I SDRAM Initialization  
For instructions on DDRII/I SDRAM initialization, refer to DDR SDRAM Initialization  
®
subsection in the Memory Controller chapter of the Intel IXP43X Product Line of  
Network Processors Developer’s Manual.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
3.3  
Expansion Bus  
The Expansion Bus of the IXP43X network processors is specifically designed for  
compatibility with Intel-and Motorola* style microprocessor interfaces.  
The expansion bus controller includes a 24-bit address bus and a 16-bit wide data path,  
running at a maximum speed of 80 MHz from an external clock oscillator. The bus can  
be configure to support the following target devices:  
• Intel multiplexed  
• Intel non-multiplexed  
®
®
• Intel StrataFlash  
• Synchronous Intel StrataFlash Memory  
• Motorola multiplexed  
• Motorola non multiplexed  
The expansion bus controller also has an arbiter that supports up to four external  
devices that can master the expansion bus. External masters can be used to access  
external slave devices that reside on the expansion bus, including access to internal  
memory mapped regions within the IXP43X network processors.  
All supported modes are seamless and no additional glue logic is required. Other cycle  
types can be supported by configuring the Timing and Control Register for Chip Select.  
The expansion interface functions support 8-bit or 16-bit data operation and allows an  
address range of 512 bytes to 16 MBs, using 24 address lines for each of the four  
independent chip selects.  
Access to the expansion-bus interface is completed in five phases. Each of the five  
phases can be lengthened or shortened by setting various configuration registers on a  
per-chip-select basis. This feature allows the IXP43X network processors to connect to  
a wide variety of peripheral devices with varying speeds.The expansion interface  
supports Intel or Motorola* microprocessor style bus cycles. The bus cycles can be  
configured to be multiplexed address/data cycles or separate address/data cycles for  
each of the four chip-selects.  
The expansion interface is an asynchronous interface to externally connected chips. A  
clock is supplied to the IXP43X network processors expansion interface for the interface  
to operate. This clock can be driven from GPIO 15 or an external source. Devices on the  
expansion bus can be clocked by an external clock at a rate of up to 80 MHz. If GPIO 15  
is used as the clock source, the Expansion Bus interface can only be clocked at a  
maximum of 33.33 MHz. GPIO 15’s maximum clock rate is 33.33 MHz.  
3.3.1  
Signal Interface  
Table 5.  
Expansion Bus Signal Recommendations (Sheet 1 of 2)  
Pull  
Type  
Field  
Name  
Up  
Recommendations  
Down  
EX_CLK  
EX_ALE  
I
No  
No  
Use series termination resistor, 10Ω to 33Ω at the source.  
TRI O  
Use series termination resistor, 10Ω to 33Ω at the source.  
Use 470Ω resistors for pull-downs; required for boot strapping for initial configuration of  
Configuration Register 0. Pull-ups are not required as for when the system comes out of  
reset, all bits are initially set HIGH. For more details, see Table 6.  
For additional details on address strapping, see the Intel IXP43X Product Line of Network  
Processors Developer’s Manual.  
EX_ADDR[23:0]  
I/O  
Yes  
®
EX_WR_N  
EX_RD_N  
I/O  
I/O  
No  
No  
Use series termination resistor, 10Ω to 33Ω at the source.  
Use series termination resistor, 10Ω to 33Ω at the source.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Table 5.  
Expansion Bus Signal Recommendations (Sheet 2 of 2)  
Pull  
Up  
Down  
Type  
Field  
Name  
Recommendations  
Use series termination resistor, 10Ω to 33Ω at the source.  
Use 10KΩ resistors pull-ups to ensure that the signal remains de-asserted.  
EX_CS_N[3:0]  
I/O  
Yes  
EX_DATA[15:0]  
EX_IOWAIT_N  
I/O  
I
No  
Expansion-bus, bidirectional data.  
Yes  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
3.3.2  
Reset Configuration Straps  
At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs  
are switched to inputs and the state of the inputs are captured and stored in  
Configuration Register 0, bits 23 through 0. This occurs when PLL_LOCKED is de-  
asserted.  
The strapping of Expansion-bus address pins can be done by placing external pull-down  
resistors at the required address pin. It is not required to use external pull-up resistors,  
by default upon reset all bits on Configuration Register 0 are set High, unless an  
external pull down is used to set them Low. For example to register a bit low or high in  
the Configuration Register 0, do the following:  
Place an external 470Ω pull-down resistor to register a bit LOW in the Configuration  
Register 0.  
No external pull-up is required; upon reset, bits are set high by default.  
The state of the boot-strapping resistor is registered on the first cycle after the  
synchronous de-assertion of the reset signal. These bits can be read or written as  
needed for desired configurations. It is recommended that only Bit 31, Memory Map, be  
changed from 1 to 0 after execution of boot code from external flash.  
®
Refer to the Intel IXP43X Product Line of Network Processors Developer’s Manual for  
a complete bit description of Configuration Register 0.  
Table 6.  
Boot/Reset Strapping Configuration (Sheet 1 of 2)  
Name  
Function  
Description  
®
®
Intel XScale  
Processor  
Allow a slower Intel XScale Processor clock speed to override device fuse settings.  
But cannot be used to over clock core speed. Refer to Table 7 for additional  
information.  
EX_ADDR[23:21]  
Clock Set[2:0]  
EX_ADDR[20:17]  
EX_ADDR[16:12]  
Customer  
Customer-defined bits. (Might be used for board revision.)  
(Reserved)  
(Reserved)  
DDRI or DDRII mode selection:  
0 - DDRII mode (400MHz)  
1 - DDRI mode (266MHz)  
EX_ADDR[11]  
DDR_MODE  
DDR_mode or DDR clock speed selection bit is read only and strapped in from exp  
address bit 11 upon activation of reset_early_n and reset_cold_n.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Table 6.  
Boot/Reset Strapping Configuration (Sheet 2 of 2)  
Name  
Function  
Description  
1 = EX_IOWAIT_N is sampled during the read/write expansion bus cycles for Chip  
Select 0.  
0 = EX_IOWAIT_N is ignored for read and write cycles to Chip select 0 if  
®
EXP_TIMING_CS0 is configured to Intel mode that is mentioned in Intel IXP43X  
®
Product Line of Network Processors Datasheet and Intel IXP43X Product Line of  
Network Processors Developer’s Manual.  
Typically, IOWAIT_CS0 must be pulled down to Vss when attaching a Synchronous  
®
Intel StrataFlash on Chip Select 0 since the default mode for EXP_TIMING_CS0 is  
Intel mode and EX_IOWAIT_N is an unknown value for Synchronous Intel  
StrataFlash.  
EX_ADDR[10]  
IOWAIT_CS0  
If the board does not connect the Synchronous Intel StrataFlash WAIT pin to  
EX_WAIT_N (and the board guarantees EX_IOWAIT_N is pulled up), the value of  
IOWAIT_CS0 is a don’t-care, since EX_IOWAIT_N will not be asserted.  
When EXP_TIMING_CS0 is reconfigured to Intel Synchronous mode during  
boot-up (for synchronous Intel chips), the expansion bus controller ignores  
EX_IOWAIT_N during read and write cycles since the WAIT functionality is  
determined from the EXP_SYNCINTEL_COUNT and EXP_TIMING_CS registers.  
EX_ADDR[9]  
EX_ADDR[8]  
EXP_MEM_DRIVE  
USB Clock  
Refer to table found in EX_ADDR[5].  
Controls the USB clock select.  
1 = USB Host/Device clock is generated internally  
0 = USB Device clock is generated from GPIO[0].  
When generating a spread spectrum clock on OSC_IN, GPIO[1] can be driven from  
the system board to generate a 48 MHz clock for the USB Host.  
Selects the data bus width of the FLASH memory device found on Chip Select 0.  
Refer to 8/16_FLASH bit (Bit 0) of this register as well.  
0 = 8 or 16-bit data bus size (must be pulled down during address strapping)  
1 = not supported  
EX_ADDR[7]  
EX_ADDR[6]  
32_FLASH  
(Reserved)  
(Reserved)  
Expansion bus low/medium/high drive strength. The drive strength depends on  
EXP_DRIVE and EXP_MEM_DRIVE configuration bits.  
EXP_MEM_DRIVE EXP_DRIVE  
Expansion drive strength  
------------------------------------------------------------------------------------  
EX_ADDR[5]  
EXP_DRIVE  
0
0
1
1
0
1
0
1
Reserved  
Medium Drive  
Low Drive  
High Drive  
Sets the clock speed of the PCI Interface  
EX_ADDR[4]  
EX_ADDR[3]  
EX_ADDR[2]  
PCI_CLK  
(Reserved)  
PCI_ARB  
0 = 33 MHz (must be pulled down during address strapping)  
1 = not supported  
(Reserved). EX_ADDR[3] must not be pulled down during address strapping. This  
bit must be written to ‘1’ if performing a write to this register.  
Enables the PCI Controller Arbiter  
0 = PCI arbiter disabled  
1 = PCI arbiter enabled  
Configures the PCI Controller as PCI Bus Host  
0 = PCI as non-host  
1 = PCI as host  
EX_ADDR[1]  
EX_ADDR[0]  
PCI_HOST  
Specifies the data bus width of the FLASH memory device found on Chip Select 0.  
8/16_FLASH  
Data bus size  
16-bit  
8/16_FLASH  
0
1
8-bit  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
®
Table 7.  
Setting Intel XScale Processor Operation Speed  
®
Intel XScale Processor  
Cfg0  
Cfg1  
Cfg_en_n  
Actual Core Speed  
(MHz)  
Speed  
EX_ADDR[21] EX_ADDR[22] EX_ADDR[23]  
(Factory Part Speed)  
667 MHz  
667 MHz  
667 MHz  
667 MHz  
667 MHz  
X
0
1
0
1
X
0
0
1
1
1
0
0
0
0
667 MHz  
667 MHz  
533 MHz  
266 MHz  
400 MHz  
533 MHz  
533 MHz  
533 MHz  
533 MHz  
533 MHz  
X
0
1
0
1
X
0
0
1
1
1
0
0
0
0
533 MHz  
533 MHz  
533 MHz  
266 MHz  
400 MHz  
400 MHz  
400 MHz  
400 MHz  
400 MHz  
400 MHz  
X
0
1
0
1
X
0
0
1
1
1
0
0
0
0
400 MHz  
400 MHz  
400 MHz  
266 MHz  
400 MHz  
266 MHz  
X
X
X
266 MHz  
Note:  
The Intel XScale processor can operate at slower speeds than the factory programmed  
speed setting. This is done by placing a value on Expansion bus address bits 23,22,21  
when PLL_LOCK is deasserted and knowing the speed grade of the part from the  
factory. Column 1 above denotes the speed grade of the part from the factory. Column  
2, 3, and 4 denotes the values captured on the Expansion Bus address bits when  
PLL_LOCK is deasserted. Column 5 represents the speed at which the Intel XScale  
processor speed is operating at.  
3.3.3  
8-Bit Device Interface  
The IXP43X network processors support 8-bit-wide data bus devices (byte mode). For  
interface cycles, the data lines and control signals can be connected as shown in  
Figure 3 on page 26. During byte mode accesses, the remaining data signals not being  
used EX_DATA[15:8], are driven by the processor to an unpredictable state on WRITE  
cycles and tri-stated during READ cycles.  
When booting an 8-bit flash device, the expansion bus must be configured during reset  
to the 8-bit mode, bit 0 and 7 of Configuration Register 0 must be set as follows (see  
Table 6):  
Bit 0 = 1. By default this bit is set high when coming off reset or any time reset is  
asserted.  
Bit 7 = 0. This can be done by placing an external 470 ohm pull-down resistor to the  
pin EX_ADDR[7].  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Boot-strapping is required in certain address pins of the Expansion bus. If it is required  
to change access mode, after the system has booted, and during normal operation; the  
Timing and Control Register for Chip Select must be configured to perform the desired  
mode access. For a complete description on accomplishing this refer to the Expansion  
®
Bus chapter in the Intel IXP43X Product Line of Network Processors Developer’s  
Manual.  
3.3.4  
16-Bit Device Interface  
The IXP43X network processors support 16-bit wide data bus devices (16-bit word  
mode). For Intel interface cycles, the data lines and control signals can be connected as  
shown in Figure 3 on page 26.  
When booting a 16-bit flash device, the expansion bus must be configured during reset  
to the 16-bit mode (see Configuration Register 0).  
Bit 0 = 0. This can be done by placing an external 470 ohm pull-down resistor to the  
pin EX_ADDR[0].  
Bit 7 = 0. This can be done by placing an external 470 ohm pull-down resistor to the  
pin EX_ADDR[7].  
Boot-strapping is required in certain address pins of the Expansion bus.To change to  
access mode after booting the system and during normal operation, the Timing and  
Control Register for Chip Select must be configured to perform the desired mode  
access. For a complete description on how to accomplish this refer to the Expansion  
®
Bus chapter in the Intel IXP43X Product Line of Network Processors Developer’s  
Manual.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Figure 3.  
8/16-Bit Device Interface  
EX_DATA[15:0]  
EX_DATA[7:0]  
DATA[7:0]  
Intel® IXP43X Product  
Line of Network  
Processors  
8-Bit Device  
Byte Access  
EX_ADDR[23:0]  
EX_ADDR[23:0]  
ADDR[23:0]  
EX_CS_N  
EX_RD_N  
EX_WR_N  
CS  
OE  
WR  
CS_N  
OE_N  
WR_N  
EX_DATA[15:0]  
EX_DATA[15:0]  
DATA[15:0]  
Intel® IXP43X Product  
Line of Network  
16-Bit Device  
16-Bit-Word Access  
ADDR[23:0]  
Processors  
EX_ADDR[23:0]  
EX_ADDR[23:0]  
EX_CS_N  
EX_RD_N  
EX_WR_N  
CS  
OE  
WR  
CS_N  
OE_N  
WR_N  
B4095-004  
3.3.5  
Figure 4 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM)  
®
used in the block diagram is the Intel StrataFlash memory device TE28F256J3D —  
32-Mbyte, 16-bit, flash in the 56-TSOP package. The Intel StrataFlash memory  
TE28F256J3D is part of the 0.18-µm, 3.3-V Intel StrataFlash memory.  
.
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Figure 4.  
Flash Interface Example  
EX_DATA[15:0]  
DATA[15:0]  
EX_DATA[15:0]  
EX_ADDR[23:0]  
Intel® IXP43X Product  
16-Bit Device  
16-Bit-Word Access  
ADDR[23:0]  
Line of Network  
Processors  
EX_ADDR[23:0]  
EX_CS_N  
EX_RD_N  
EX_WR_N  
CS  
OE  
WR  
CE0  
OE_N  
WR_N  
Intel® Flash  
3.3 V  
RST#  
RP_N  
CE1  
CE2  
0 KΩ  
4.7 KΩ  
BYTE_N  
VPEN_N  
4.7 KΩ  
B4097-005  
3.4  
UART Interface  
The UART interface are a 16550-compliant UART with the exception of transmit and  
receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes  
required by the 16550 UART specification.  
The interface can be configured to support speeds from 1,200 Baud to 921 Kbaud. The  
interface supports the following configurations:  
• Five, six, seven, or eight data-bit transfers  
• One or two stop bits  
• Even, odd, or no parity  
The request-to-send (RTS0_N) and clear-to-send (CTS0_N) modem control signals also  
are available with the interface for hardware flow control. The hardware supports a  
four-wire interface:  
Transmit Data  
• Receive Data  
• Request to Send  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
• Clear to Send  
Note:  
The UART module does not support full modem functionality. However, this can be  
implemented, by using GPIO ports to generate DTR, DSR, RI, and DCD and making  
some changes to the driver.  
3.4.1  
Signal Interface  
Table 8.  
UART Signal Recommendations  
Pull  
Type  
Field  
Name  
Up/  
Recommendations  
Down  
Serial data input Port 0.  
RXDATA0  
TXDATA0  
CTS0_N  
RTS0_N  
I
O
I
Yes  
No  
When signal is not being used in the system, this pin should be pulled high with a 10-KΩ  
resistor.  
Serial data output Port 0.  
Clear-To-Send Port 0.  
\When signal is not being used in the system, this pin should be pulled high with a 10-KΩ  
resistor.  
Yes  
No  
O
Request-To-Send Port 0.  
The following figure contain a typical four signal interface between the UART and an  
RS-232 transceiver driver, required to interface with external devices. Unused inputs to  
the RS-232 driver can be connected to ground. This avoids signals floating to  
undetermined states which can cause over heating of the driver leading to permanent  
damage.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Figure 5.  
UART Interface Example  
DB9  
Connector (Female)  
1 DCD  
1
2
CTS0_N  
OUT4  
IN3  
2 RX  
6
7
RTS0_N  
RXDATA0  
TXDATA0  
IN1  
OUT3  
OUT2  
3 TX  
OUT1  
IN2  
4 DTR  
5 GND  
6 DSR  
7 RTS  
8 CTS  
9 RI  
3
4
5
IN4  
8
9
Intel® IXP43X  
Intel® IXP43X  
Product Line of  
NC  
Product Line of  
Network Processors  
RS-232  
Transceiver  
Network Processors  
B4099-005  
3.5  
MII Interface  
The IXP43X network processors support a maximum of two Ethernet MACs. Depending  
on the part number of the IXP43X network processors, various combinations can be  
®
used. Refer to the Intel IXP43X Product Line of Network Processors Datasheet for a  
detailed list of features that can be enabled depending upon your requirements.  
All MACs contained in the NPEs are compliant to the IEEE 802.3 specification and  
handle flow control for the IEEE 802.3Q VLAN specification.  
The Management Data Interface (MDI) supports a maximum of 32 PHY addresses. MDI  
signals are required to be connected to every PHY chip. Each PHY port is assign a  
unique address in the external PHY chip from 0 to 31, totaling a maximum of 32 PHY  
addresses. The maximum number of MACs supported by the IXP43X network  
processors is two.  
The MII interface supports clock rates of 25 MHz for 100-Mbps operation or 2.5 MHz for  
10-Mbps operation.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
3.5.1  
Signal Interface MII  
Table 9.  
MII NPE A Signal Recommendations  
Pull  
Type  
Name  
Up/  
Recommendations  
Field  
Down  
Transmit Clock.  
ETHA_TXCLK  
I
Yes  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
ETHA_TXDATA[3:0]  
ETHA_TXEN  
O
O
No  
No  
Transmit Data.  
Transmit Enable.  
Receive Clock.  
ETHA_RXCLK  
ETHA_RXDATA[3:0]  
ETHA_RXDV  
I
I
I
I
I
Yes  
Yes  
Yes  
Yes  
Yes  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Receive Data.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Receive Data Valid.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Collision Detect.  
ETHA_COL  
If operating in a full duplex mode and there is no requirement to use the Collision  
Detect signal, then the pin must be pulled low with a 10-KΩ resistor.  
Carrier Sense.  
ETHA_CRS  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Notes:  
1.  
2.  
3.  
Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after  
being disabled without asserting a system reset.  
Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left  
unconnected.  
Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require  
pull-ups or pull-downs in the clock-input signals.  
Table 10.  
MII NPE C Signal Recommendations (Sheet 1 of 2)  
Pull  
Type  
Field  
Name  
Up/  
Recommendations  
Down  
Externally supplied transmit clock.  
25 MHz for 100 Mbps operation  
2.5 MHz for 10 Mbps  
ETHC_txclk  
I
Yes  
This MAC contains hardware hashing capabilities that are local to the interface.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This  
MAC contains hardware hashing capabilities that are local to the interface.  
ETHC_txdATA[3:0]  
ETHC_txen  
O
O
No  
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted  
synchronously, with respect to ETHC_TXCLK, at the first nibble of the preamble, and  
remains asserted until all the nibbles of a frame are presented. This MAC contains  
hardware hashing capabilities that are local to the interface.  
Yes  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Table 10.  
MII NPE C Signal Recommendations (Sheet 2 of 2)  
Pull  
Type  
Field  
Name  
Up/  
Recommendations  
Down  
Externally supplied receive clock:  
25 MHz for 100 Mbps operation  
2.5 MHz for 10 Mbps  
ETHC_rxclk  
I
Yes  
This MAC contains hardware hashing capabilities that are local to the interface.  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
Receive data bus from PHY, data sampled synchronously, with respect to ETHC_RXCLK.  
This MAC contains hardware hashing capabilities that are local to the interface.  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
ETHC_rxdATA[3:0]  
ETHC_rxdv  
I
I
Yes  
Yes  
Receive data valid is used to inform the MII interface about data that is being sent by  
the Ethernet PHY  
This MAC contains hardware hashing capabilities that are local to the interface.  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
Asserted by the PHY when a collision is detected by the PHY. This MAC contains  
hardware hashing capabilities that are local to the interface.  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system  
ETHC_col  
I
I
Yes  
Yes  
When this interface is disabled through the NPE-C Ethernet soft fuse (refer to the  
®
Expansion Bus Controller chapter of the Intel IXP43X Product Line of Network  
Processors Developer’s Manual) and is not being used a system design, this interface/  
signal is not required for any connection.  
Asserted by the PHY when the transmit medium or receive medium are active.  
De-asserted when both the transmit and receive medium are idle. Remains asserted  
throughout the duration of collision condition. PHY asserts CRS asynchronously and  
de-asserts synchronously with respect to ETHC_RXCLK.  
ETHC_crs  
This MAC contains hardware hashing capabilities that are local to the interface.  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
Notes:  
1.  
2.  
3.  
Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after  
being disabled without asserting a system reset.  
Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left  
unconnected.  
Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in note 1 — only require  
pull-ups or pull-downs in the clock-input signals.  
Table 11.  
MAC Management Signal Recommendations - NPE A and NPE C  
Pull  
Type  
Field  
Name  
Up/  
Recommendations  
Down  
NPE A and NPE C  
Management data input output. Provides the write data to both PHY devices connected to  
each MII interface. An external pull-up resistor of 1.5K ohm is required on  
ETHC_MDIO to properly quantify the external PHYs used in the system. For specific  
implementation, see the IEEE 802.3 specification.  
ETH_mdio  
IO  
Yes  
No  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system  
NPE A and NPE C  
Management data clock. Management data interface clock is used to clock the MDIO signal as  
an output and sample the MDIO as an input. The ETHC_MDC is an input on power up and can  
ETH_mdc  
O
®
be configured to be an output through Intel APIs documented in the Intel IXP400 Software  
Programmer’s Guide  
3.5.2  
Device Connection, MII  
Figure 6 is a typical example of an Ethernet PHY device interfacing to one of the MACs  
via the MII hardware protocol.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Figure 6.  
MII Interface Example  
Intel® IXP43X  
Product Line of  
Network Processors  
10/100  
PHY  
TXEN  
ETH_TXEN  
ETH_TXCLK  
TXCLK  
TXDATA[3:0]  
ETH_TXDATA[3:0]  
ETH_RXDV  
ETH_RXCLK  
RXDV  
Magnetics  
RJ45  
RXCLK  
ETH_RXDATA[3:0]  
RXDATA[3:0]  
ETH_COL  
ETH_CRS  
COL  
CRS  
25 MHz  
VCC (3.3 V)  
1.5 K  
MDIO  
MDC  
ETH_MDIO  
ETH_MDC  
MII Interface  
B4101-004  
3.6  
GPIO Interface  
The IXP43X network processors provide 16 general-purpose input/output pins to  
generate and capture application-specific input and output signals. Each individual pin  
can be programmed as an input or output.  
When programmed as an input, GPIO 0 to GPIO 12 can be configured to be an interrupt  
source. Interrupt sources can be configured to detect either active high, active low,  
rising edge, falling edge, or transitional. In addition, GPIO14 and GPIO15 can be  
programmed to provide a user-programmable clock out.  
During reset, all pins are configured as inputs and remain in this state until configured  
otherwise, with the exception of GPIO15, which by default provides a clock output. The  
driver strength of GPIO pins is sufficient to drive external LEDs with a proper limiting  
resistor.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
3.6.1  
Signal Interface  
Table 12.  
GPIO Signal Recommendations  
Pull  
Type  
Name  
Up/  
Recommendations  
Field  
Down  
General Purpose Input/Output.  
If used as an input interrupt (only GPIO [12:0]), should be pull-up or pull-down, depending  
on the level of activation. For example:  
GPIO[13:0]  
IO  
Yes  
Active high, use a 10-KΩ pull-down resistor.  
Active low, use a 10-KΩ pull-up resistor.  
Should be pulled high through a 10-KΩ resistor when not used.  
Note: Alternate function for GPIO[1] - External USB 48 MHz Bypass Clock  
General Purpose Input/Output.  
GPIO[14]  
GPIO[15]  
IO  
IO  
Yes  
Yes  
Same recommendations as GPIO[13:0]. An additional feature includes Clock generation, max  
clock out 33.33 MHz., set as input by default.  
General Purpose Input/Output.  
Same recommendations as GPIO[13:0]. An additional feature includes Clock generation, max  
clock out 33.33 MHz., set as output by default.  
3.6.2  
Design Notes  
The drive strength for GPIO[15:14] is limited to 8 mA, while GPIO [13:0] can output up  
to 16 mA. When used for driving high current devices such as LEDs or relays, make  
sure to place current-limiting resistor; else there could be permanent damage to the  
driver of the IXP43X network processors.  
It is recommended that a 10-KΩ pull-up resistor be used when a GPIO port is  
configured as an input and not being used.  
3.7  
USB Interface  
There are two USBV2.0 Host Controllers in the IXP43X network processors. It supports  
Low-Speed, 1.5 Mbps, Full-Speed, 12 Mbps, High-Speed, 480 Mbps rate and interface  
is EHCI compliant.  
Supported features are:  
• Host function  
• Low-speed interface  
• Full-speed interface  
• High-speed interface  
• EHCI register interface  
• UTMI+ Level 2 Compliant  
The following is a partial list of features that are not supported:  
• Device function  
• OTG function  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
3.7.1  
Signal Interface  
Table 13.  
USB Host Signal Recommendations  
Pull  
Type  
Name  
Up/  
Description  
Field  
Down  
Positive signal of the differential USB receiver/driver for the USB host interface.  
Use an 20Ω series termination resistor at the source.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled low with a 10-KΩ resistor. When this interface is  
disabled through the USB Device soft fuse and is not being used in a system design, it  
is not required for any connection. Refer to Expansion Bus Controller chapter of the  
USB_P0_POS  
I/O  
I/O  
Yes  
Yes  
®
Intel IXP43X Product Line of Network Processors Developer’s Manual.  
Negative signal of the differential USB receiver/driver for the USB host interface.  
Use an 20Ω series termination resistor at the source.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled low with a 10-KΩ resistor. When this interface is  
disabled through the USB Device soft fuse and is not being used in a system design, it  
is not required for any connection. Refer to Expansion Bus Controller chapter of the  
USB_P0_NEG  
®
Intel IXP43X Product Line of Network Processors Developer’s Manual.  
USB_P0_PWREN  
USB_P0_OC  
O
I
No  
No  
Enables the external VBUS power source.  
External VBUS power is in over current condition  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled low with a 10-KΩ resistor. When this interface is  
disabled through the USB Device soft fuse and is not being used in a system design, it  
is not required for any connection. Refer to Expansion Bus Controller chapter of the  
®
Intel IXP43X Product Line of Network Processors Developer’s Manual.  
Positive signal of the differential USB receiver/driver for the USB host interface.  
Use an 20Ω series termination resistor at the source.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled low with a 10-KΩ resistor. When this interface is  
disabled through the USB Device soft fuse. Refer to Expansion Bus Controller chapter  
USB_P1_POS  
USB_P1_NEG  
I/O  
I/O  
Yes  
Yes  
®
of the Intel IXP43X Product Line of Network Processors Developer’s Manual.  
Negative signal of the differential USB receiver/driver for the USB host interface.  
Use an 20Ω series termination resistor at the source.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled low with a 10-KΩ resistor. When this interface is  
disabled through the USB Device soft fuse and is not being used in a system design, it  
is not required for any connection. Refer to Expansion Bus Controller chapter of the  
®
Intel IXP43X Product Line of Network Processors Developer’s Manual.  
USB_P1_PWREN  
USB_P1_OC  
O
I
No  
No  
Enable the external VBUS power source.  
External VBUS power is in over current condition  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled low with a 10-KΩ resistor. When this interface is  
disabled through the USB Device soft fuse and is not being used in a system design, it  
is not required for any connection. Refer to Expansion Bus Controller chapter of the  
®
Intel IXP43X Product Line of Network Processors Developer’s Manual.  
A typical implementation of a USB interface Host down-stream is shown in Figure 9.  
The Host controller cannot be used as a Device controller.  
Note:  
Note:  
Depending on the data rate required, Low-speed, Full-speed or High-speed, the 1.5K  
resistor shown near the device interface must be connected on the D+ or D-.  
Speed configuration at the Device can be set as stated in note 1 and 2 below. For more  
details, refer to the Universal Serial Bus Specification, Revision 2.0.  
1. If a 1.5-KΩ, pull-up resistor is connected to USB_P_POS line, the USB port is  
identified as Full-speed and High-speed mode.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
2. If a 1.5-KΩ, pull-up resistor is connected to USB_P_NEG line, the USB port is  
identified as Low-speed mode.  
To maintain signal integrity and minimize end-users termination mismatch, the IXP43X  
network processors require external series termination resistors. The value of the  
terminating resistors is based on the operational speed and length of the transmission  
line.  
Refer to following termination guidelines for High-speed:  
1. High-speed USB designs require parallel termination at both the transmitter and  
receiver. For host controller designs that use external termination resistors, place  
the termination resistors as close as possible to the host controller signal pins.  
Recommend less than 200 mils if possible. Follow the manufacturer’s  
recommendation for the termination value needed to obtain the required 45 ohm to  
ground parallel HS termination.  
2. For downstream ports, a 15 kΩ pull down resistor on the connector side of the  
termination is required for device connection detection purposes. Note that this pull  
down might be integrated into the host controller silicon. Follow the manufacturer’s  
recommendation for the specific part used.  
3. A common mode (CM) choke should be used to terminate the high speed USB bus  
if they should pass EMI testing. Place the CM choke as close as possible to the  
connector as shown in Figure 8 on page 36. Common mode chokes can provide  
required noise attenuation. Design can include a common mode choke footprint to  
provide a stuffing option in the event the choke is needed to pass EMI testing.  
Note:  
Common mode chokes degrade signal quality, thus they should only be used if EMI is a  
known problem.  
Figure 7.  
Common Mode Choke  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Figure 8.  
USB RCOMP and ICOMP Pin Requirement  
USB_ RBIASP  
USB_ RBIASN  
Intel®  
IXP43X  
Product Line  
of Network  
Processors  
22.6  
Ω
±1%  
resistor  
Figure 9.  
USB Host Down Stream Interface Example  
USB_VDD  
Host  
Device  
Intel® IXP43X  
Product Line of  
Network  
200 mA  
0.1 µF  
FERRITE  
47 µF  
0.1 µF  
Processors  
V_BUS USB_3V3  
USB_HPEN  
USB_HPWR  
4.7 µF  
1.5 KΩ  
Look at  
Note 1&2  
20 Ω  
USB_HPOS  
(D+)  
D
+
FERRITE  
Device  
22 pF 22 pF  
D-  
15 KΩ  
USB  
Port  
20 Ω  
USB_HNEG  
(D-)  
FERRITE  
22 pF 22 pF  
15 KΩ  
B4105-004  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
3.8  
UTOPIA Level 2 Interface  
The IXP43X network processors support the industry-standard UTOPIA Level 2 bus  
interface. A dedicated Network Processor Engine (NPE) handles segmentation and  
reassembly of ATM cells, CRC checking/generation, and transfer of data to/from  
memory. This allows parallel processing of data traffic on the UTOPIA interface,  
®
off-loading processor overhead required by the Intel XScale Processor.  
The UTOPIA module is configured as a master and can support single-PHY (SPHY) or  
multi-PHY (MPHY).  
The IXP43X network processors are in compliance with the ATM Forum, UTOPIA Level 2  
Specification, Revision 1.0. For optimal design results, the guidelines of the  
specification should be followed.  
3.8.1  
Signal Interface  
Table 14.  
UTOPIA Level 2/MII_A  
Pull  
Type  
Field  
Name  
Up/  
Description  
Down  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 Transmit clock input. Also known as UTP_TX_CLK. This signal is  
used to synchronize all UTOPIA Level 2 transmit output to the rising edge of the  
UTP_OP_CLK.  
MII Mode of Operation:  
Externally supplied transmit clock.  
UTP_OP_CLK /  
ETHA_TXCLK  
I
Yes  
25 MHz for 100 Mbps operation  
2.5 MHz for 10 Mbps  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
UTOPIA Level 2 flow control output signal. Also known as the TXENB_N signal.  
Used to inform the selected PHY about data transmission. Placing the PHY’s  
address on the UTP_OP_ADDR and bringing UTP_OP_FCO to logic 1 during the  
current clock, followed by the UTP_OP_FCO going to a logic 0, on the next clock  
cycle, selects the PHY that is active in MPHY mode.  
In SPHY configurations, UTP_OP_FCO is used to inform the PHY that the  
processor is ready to send data.  
UTP_OP_FCO  
UTP_OP_SOC  
TRI  
TRI  
TRI  
Yes  
Yes  
No  
This signal is tied to Vcc with an external 10-KΩ resistor.  
Start of Cell. Also known as TX_SOC.  
Active high signal is asserted when UTP_OP_DATA contains first valid byte of a  
transmitted cell.  
This signal is tied to Vss with an external 10-KΩ resistor.  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data  
from the processor to an ATM UTOPIA Level 2-compliant PHY.  
UTP_OP_DATA[3:0] /  
ETHA_TXDATA[3:0]  
MII Mode of Operation:  
Transmit data bus to PHY, asserted synchronously with respect to ETHA_TXCLK.  
This MAC interface does not contain hardware hashing capabilities that are local  
to the interface. In this mode of operation the pins represented by this interface  
are ETHA_TXDATA[3:0].  
®
††  
Refer to the Intel IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an  
interface.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Pull  
Up/  
Down  
Type  
Field  
Name  
Description  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data  
from the processor to an ATM UTOPIA Level 2-compliant PHY.  
MII Mode of Operation:  
UTP_OP_DATA[4] /  
ETHA_TXEN  
TRI  
No  
Indicates that the PHY is being presented with nibbles on the MII interface.  
Asserted synchronously, with respect to ETHA_TXCLK, at the first nibble of the  
preamble, and remains asserted until all the nibbles of a frame are presented.  
This MAC does not contain hardware hashing capabilities that are local to the  
interface.  
UTOPIA Level 2 Mode of Operation:  
UTP_OP_DATA[7:5]  
UTP_OP_ADDR[4:0]  
TRI  
I/O  
No  
UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data  
from the processor to an ATM UTOPIA Level 2-compliant PHY.  
Transmit PHY address bus. Used by the processor when operating in MPHY  
mode to poll and select a single PHY at any given time.  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
fuse and is not being used in a system design, it is not required for any  
Yes  
®
connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
UTOPIA Level 2 Output data flow control input: Also known as the TXFULL/CLAV  
signal.  
Used to inform the processor, the ability of each polled PHY to receive a complete  
cell. For  
cell-level flow control in an MPHY environment, TxClav is an active high tri-  
stateable signal from the MPHY to ATM layer.  
The UTP_OP_FCI is connected to multiple MPHY devices. It sees the logic high  
generated by the PHY, one clock after the given PHY address is asserted and a  
full cell can be received by the PHY. The UTP_OP_FCI sees a logic low generated  
by the PHY one clock cycle, after the PHY address is asserted, and a full cell  
cannot be received by the PHY.  
UTP_OP_FCI  
I
Yes  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
fuse and is not being used in a system design, it is not required for any  
®
connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 Receive clock input. Also known as UTP_RX_CLK.  
This signal is used to synchronize all UTOPIA Level 2-received inputs to the rising  
edge of the UTP_IP_CLK.  
MII Mode of Operation:  
UTP_IP_CLK /  
ETHA_RXCLK  
Externally supplied receive clock.  
I
Yes  
25 MHz for 100 Mbps operation  
2.5 MHz for 10 Mbps  
This MAC interface does not contain hardware hashing capabilities that are local  
to the interface.  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
®
††  
Refer to the Intel IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an  
interface.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Pull  
Up/  
Down  
Type  
Field  
Name  
Description  
UTOPIA Level 2 Input Data flow control input signal. Also known as RXEMPTY/  
CLAV.  
Used to inform the processor of the ability of each polled PHY to send a complete  
cell. For cell-level flow control in an MPHY environment, RxClav is an active high  
tri-stateable signal from the MPHY to ATM layer. The UTP_IP_FCI, which is  
connected to multiple MPHY devices, sees logic high generated by the PHY, one  
clock after the given PHY address is asserted, when a full cell can be received by  
the PHY. The UTP_IP_FCI sees a logic low generated by the PHY, one clock cycle  
after the PHY address is asserted if a full cell cannot be received by the PHY.  
UTP_IP_FCI  
I
Yes  
In a SPHY mode, this signal is used to indicate to the processor that the PHY has  
an octet or cell available for transferring to the processor.  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
®
fuse (refer to Expansion Bus Controller chapter of the Intel IXP43X Product Line  
of Network Processors Developer’s Manual) and is not being used in a system  
design, the interface/signal is not required for any connection.  
Start of Cell. RX_SOC  
Active-high signal that is asserted when UTP_IP_DATA contains the first valid  
byte of a transmitted cell.  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
fuse and is not being used in a system design, it is not required for any  
connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
UTP_IP_SOC  
I
Yes  
®
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 input data. Also known as RX_DATA.  
Used by the processor to receive data from an ATM UTOPIA Level 2-compliant  
PHY.  
MII Mode of Operation:  
Receives data bus from the PHY; asserted synchronously with respect to  
ETHA_RXCLK.  
When the interface/signal is enabled and is not being used in a system design, it  
UTP_IP_DATA[3:0] /  
ETHA_RXDATA[3:0]  
I
Yes  
should be pulled high with a 10KΩ resistor.  
When the interface is disabled through the UTOPIA Level 2 and/or the NPE-A  
Ethernet soft fuse and is not being used in a system design, it is not required for  
®
any connection. (Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual).  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 input data. Also known as RX_DATA.  
Used by to the processor to receive data from an ATM UTOPIA Level 2-compliant  
PHY.  
MII Mode of Operation:  
Receive data valid used to inform the MII interface about data that is being sent  
by the Ethernet PHY.  
This MAC does not contain hardware hashing capabilities that are local to the  
interface.  
UTP_IP_DATA[4] /  
ETHA_RXDV  
I
Yes  
When the interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
fuse (and is not being used in a system design, it is not required for any  
®
connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
®
††  
Refer to the Intel IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an  
interface.  
®
Intel IXP43X Product Line of Network Processors  
April 2007  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Pull  
Up/  
Down  
Type  
Field  
Name  
Description  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 input data. Also known as RX_DATA.  
Used by the processor to receive data from an ATM UTOPIA Level 2-compliant  
PHY.  
When an NPE A is configured in UTOPIA Level 2 mode of operation and the  
signal is not used, it should be pulled high through a 10-KΩ resistor.  
UTP_IP_DATA[5] /  
ETHA_COL  
MII Mode of Operation:  
Asserted by the PHY when a collision is detected by the PHY.  
I
Yes  
When an NPE A is configured in MII mode of operation and the signal is not  
used, it should be pulled low through a 10-KΩ resistor.  
When this interface is disabled through the UTOPIA Level 2 and/ or the NPE-A  
Ethernet soft fuse and is not being used in a system design, it is not required for  
®
any connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 input data. Also known as RX_DATA.  
Used by the processor to receive data from an ATM UTOPIA Level 2-compliant  
PHY.  
MII Mode of Operation:  
Asserted by the PHY when transmit medium or receive medium is active. De-  
asserted when both the transmit and receive medium are idle. Remains asserted  
throughout the duration of collision condition. PHY asserts CRS asynchronously  
and de-asserts synchronously with respect to ETHA_RXCLK.  
UTP_IP_DATA[6] /  
ETHA_CRS  
I
Yes  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
fuse and is not being used in a system design, it is not required for any  
®
connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
UTOPIA Level 2 Mode of Operation:  
UTOPIA Level 2 input data. Also known as RX_DATA.  
Used by the processor to receive data from an ATM UTOPIA Level 2-compliant  
PHY.  
MII Mode of Operation:  
Not Used.  
UTP_IP_DATA[7]  
I
Yes  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor. When this  
interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft  
fuse and is not being used in a system design, it is not required for any  
®
connection. Refer to Expansion Bus Controller chapter of the Intel IXP43X  
Product Line of Network Processors Developer’s Manual.  
Receive PHY address bus.  
UTP_IP_ADDR[4:0]  
I/O  
TRI  
No  
Used by the processor while operating in an MPHY mode to poll and select a  
single PHY at any given point of time.  
UTOPIA Level 2 Input Data Flow Control Output signal: Also known as the  
RX_ENB_N.  
In a SPHY configuration, UTP_IP_FCO is used to inform the PHY that the  
processor is ready to accept data.  
In MPHY configurations, UTP_IP_FCO is used to select those PHY drives that  
signals UTP_RX_DATA and UTP_RX_SOC. The PHY is selected by placing the  
PHY’s address on the UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during  
the current clock, followed by the UTP_OP_FCO going to a logic 0 on the next  
clock cycle.  
UTP_IP_FCO  
Yes  
When this interface/signal is enabled and is not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
®
††  
Refer to the Intel IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an  
interface.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
3.8.2  
Device Connection  
The following example shown in Figure 10 shows a typical interface to an ADSL Framer  
via the UTOPIA bus. Notice that depending on the framer used some control signals  
might be required which can be derived from the Expansion bus or the GPIO signals.  
Figure 10.  
UTOPIA Interface Example  
Intel® IXP43X  
Product Line of  
Network  
Processors  
Control Signals  
25 MHz  
EX_BUS  
Analog Front  
End  
ATM Layer Device  
ADSL Framer  
Multi-Channel  
AFE  
RJ11  
UTP_OP_CLK  
UTP_OP_FCO  
UTP_OP_ADDR[4:0]  
TXCLK  
TXENB#  
TXADDR[4:0]  
TXCLAV  
TXSOC  
UTP_OP_FCI  
UTP_OP_SOC  
TXDATA[7:0]  
UTP_OP_DATA[7:0]  
RXENB#  
UTP_IP_FCO  
UTP_IP_ADDR[4:0]  
RXADDR[4:0]  
UTP_IP_FCI  
RXCLAV  
RXSOC  
UTP_IP_SOC  
UTP_IP_DATA[7:0]  
RXDATA[7:0]  
AFE  
RJ11  
UTP_IP_CLK  
RXCLK  
UTOPIA Level 2  
Interface  
25 MHz  
SDRAM  
Local Memory  
B4107-005  
3.9  
HSS Interface  
NPE A has an integrated High-Speed Serial (HSS) module, whose primary function is to  
provide connectivity between the internal NPE A and the external HSS interface. There  
is one HSS port that can directly interface to SLIC/CODEC devices for voice  
applications, or serial DSL framers. The HSS ports are software configurable to support  
various serial protocols, such as T1/ E1/J1, and MVIP. For a list of supported protocols,  
®
see the Intel IXP400 Software Programmer’s Guide.  
®
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
3.9.1  
Signal Interface  
Table 15.  
High-Speed, Serial Interface 0  
Pull  
Type  
Name  
HSS_TXFRAME0  
HSS_TXDATA0  
HSS_TXCLK0  
Up  
Recommendations  
Field  
Down  
Transmit frame.  
I/O  
OD  
I/O  
I/O  
I
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Transmit data out. Open Drain Output.  
When this interface/signal is enabled and is used or not used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor to Vcc33.  
Transmit clock.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Receive frame.  
HSS_RXFRAME0  
HSS_RXDATA0  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Receive data input.  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Receive clock.  
HSS_RXCLK0  
I/O  
When this interface/signal is enabled and is not being used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Notes:  
1.  
2.  
3.  
Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after  
being disabled without asserting a system reset.  
Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left  
unconnected.  
Features Enabled by a specific part number and required to be Soft Fuse-disabled, as stated in Note 1 alone require pull-  
ups or pull-downs in the clock-input signals.  
3.9.2  
Figure 11 shows a typical interface between the IXP43X network processors and a SLIC  
CODEC, through the SSP and HSS ports, and a couple of GPIO signals.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Figure 11.  
HSS Interface Example  
Vccp (3.3 V)  
10 KΩ  
Intel® IXP 43X  
Product Line of  
Network Processors  
External Oscillator  
GPIO_0  
GPIO_1  
Clock derived internally  
from 3.6864 MHz  
or external oscilator  
SSP_EXTCLK  
33 MHz  
RESET_N INT_N  
SSP_SCLK  
SSP_SFRM  
SSP_TXD  
SSP_RXD  
CLK  
CS_N  
D I  
DO  
Vccp (3.3 V)  
SSP Interface  
10 KΩ  
HSS_TX_FRAME0  
HSS_TXDATA0  
HSS_TXCLK0  
RJ11  
DTX  
AFE  
HSS_RXFRAME0  
HSS_RXDATA0  
HSS_RXCLK0  
FSYNC  
RXD  
PCLK  
Clock derived from  
SLIC/CODEC  
or external oscilator  
SLIC CODEC  
HSS Interface  
512 KHz to  
8.192 MHz  
B4108-005  
3.10  
SSP Interface  
The IXP43X network processors have a Synchronous Serial Peripheral Interface (SSP)  
®
module. Its primary function is to provide connectivity between the Intel XScale  
Processor and an external SSP interface.  
The SSP module supports Texas Instruments synchronous serial protocol (SSP)*,  
Motorola serial peripheral interface (SPI)* and National Microwire*.  
The clock rate can be selected from an internal, 3.6864-MHz source or external source  
fed at input pin SSP_EXTCLK. The clock can then be divided down anywhere from  
7.2 KHz to 1.84 MHz by setting bits 15:08 in SSP Control Register 0 (SSCR0). For  
instructions on the SSP configuration register, refer to the Serial Clock Register (SCR)  
®
subsection in the Memory Controller chapter of the Intel IXP43X Product Line of  
Network Processors Datasheet.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
3.10.1  
Signal Interface  
Table 16.  
Synchronous Serial Peripheral Port Interface  
Pull  
Up/  
Down  
Type  
Field  
Name  
Recommendations  
SSP_SCLK  
SSP_SFRM  
SSP_TXD  
O
O
O
No  
No  
No  
Serial bit clock.  
Serial frame indicator.  
Transmit data (serial data out).  
Receive data (serial data in).  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
SSP_RXD  
I
I
Yes  
Yes  
External clock input.  
SSP_EXTCLK  
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.  
3.10.2  
Device Connection  
There are a number of devices available that can interface to SSP or SPI ports, these  
can range from RTC (Real-Time Clock), LCD (Liquid Crystal Displays), Digital Thermal  
Sensor to Flash memory devices.  
One of the most common usage for SSP or SPI port, is serial flash code storage. Serial  
flash devices can be used to store board revision, serial numbers, or assembly  
information. Figure 12 provides an example of a Serial Flash device interface to the  
SSP port in the IXP43X network processors. For an additional example of SPI interface,  
refer to Figure 11, where a SLIC is connected to the SSP and HSS ports.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Figure 12.  
Serial Flash and SSP Port (SPI) Interface Example  
Intel® IXP43X Product  
Line of Network  
Processors  
SPI Flash  
SSP_SCLK  
SSP_SFRM  
SSP_TXD  
CLK  
CS_N  
D I  
SSP_RXD  
DO  
SSP_EXTCLK  
7.2 KHz  
to 3.6864 MHz  
SSP Interface  
External Oscillator  
B4109-003  
3.11  
PCI Interface  
The PCI Controller of the IXP43X network processors is an industry-standard, 32-bit  
interface, high-performance bus that operates at 33 MHz(PCI Local Bus Specification,  
Rev. 2.2).  
The PCI interface is capable of operating as a host or an option. This PCI  
As indicated in Figure 13, a PCI transparent bridge is required to support Compact PCI.  
General PCI routing guidelines can be found in Section 6.2, “Topology” on page 67. For  
detailed information, see the PCI Local Bus Specification, Rev. 2.2.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
3.11.1  
Signal Interface  
Table 17.  
PCI Controller (Sheet 1 of 2)  
Pull  
Type  
Name  
PCI_AD[31:0]  
PCI_CBE_N[3:0]  
PCI_PAR  
Up/  
Recommendations  
Field  
Down  
PCI Address/Data bus.  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
PCI Command/Byte Enables.  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
PCI Parity.  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
PCI Cycle Frame.  
PCI_FRAME_N  
PCI_TRDY_N  
PCI_IRDY_N  
PCI_STOP_N  
PCI_PERR_N  
PCI_SERR_N  
PCI_DEVSEL_N  
PCI_IDSEL  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
PCI Target Ready.  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
Initiator Ready.  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
Stop.  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
Parity Error.  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
System Error.  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
Device Select:  
When this interface/signal is enabled and is being used or not being used in a system design,  
the interface/signal should be pulled high with a 10-KΩ resistor.  
Initialization Device Select.  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
Arbitration Request.  
PCI_REQ_N[3:1]  
I
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
Arbitration Request:  
PCI_REQ_N[0]  
PCI_GNT_N[3:1]  
PCI_GNT_N[0]  
Notes:  
I/O  
O
Yes  
No  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
Arbitration Grant.  
Arbitration Grant.  
I/O  
Yes  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
1.  
2.  
3.  
Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after  
being disabled without asserting a system reset.  
Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left  
unconnected.  
Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require  
pull-ups or pull-downs in the clock-input signals.  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
Table 17.  
PCI Controller (Sheet 2 of 2)  
Pull  
Type  
Name  
Up/  
Recommendations  
Field  
Down  
Interrupt A.  
PCI_INTA_N  
O/D  
I
Yes  
Yes  
When this interface/signal is enabled and is used or not used in a system design, the  
interface/signal should be pulled high with a 10-KΩ resistor.  
Clock input.  
PCI_CLKIN  
When this interface/signal is enabled and is not being used in a system design, the interface/  
signal should be pulled high with a 10-KΩ resistor.  
Notes:  
1.  
2.  
3.  
Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after  
being disabled without asserting a system reset.  
Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left  
unconnected.  
Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require  
pull-ups or pull-downs in the clock-input signals.  
3.11.2  
PCI Interface Block Diagram  
While using the IXP43X network processors in Master mode, the PCI module can  
interface to up to four PCI cards (devices) at 33 MHz. The limitation is due to load  
requirements to maintain signal integrity.  
The PCI-to-PCI bridge must be used to address the PCI requirement not to exceed one  
load per PCI connector unless it is through a PCI-to-PCI bridge.  
The IDSEL signals on the PCI slots can be connected to one of the PCI_AD lines,  
preferable to the higher order address signals. Reset support can be accomplished by  
using one of the GPIO pins to generate a reset or through an external decoder of the  
Expansion bus.  
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®
Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Figure 13.  
PCI Interface  
Intel® IXP43X  
Product Line of  
Network Processors  
PCI Bus  
PCI Slots  
B4110-003  
3.11.3  
PCI Option Interface  
The IXP43X network processors can be used in a design as a host or as an option  
device. This section describes how the IXP43X network processors can be connected as  
an option device to obtain proper functionality. There are slight differences in the  
hardware interface when designing for option mode. All routing and board  
recommendations described in this document apply, however the design must use the  
device pin connections listed in Table 18.  
Table 18.  
PCI Host/Option Interface Pin Description (Sheet 1 of 3)  
Option  
Type  
Field  
Type  
Field  
Name  
Device-Pin Connection  
Description  
All address/data signals must be  
PCI_AD[31:0]  
PCI_CBE_N[3:0]  
PCI_PAR  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
PCI Address/Data bus  
connected between the two devices.  
Connect signals to same pins between  
the two devices.  
PCI Command/Byte Enables  
PCI Parity  
Connect signal to same pin between  
the two devices.  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
PCI_FRAME_N  
PCI_TRDY_N  
I/O  
I/O  
I/O  
I/O  
PCI Cycle Frame  
PCI Target Ready  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
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Table 18.  
PCI Host/Option Interface Pin Description (Sheet 2 of 3)  
Option  
Type  
Field  
Type  
Field  
Name  
Device-Pin Connection  
Description  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
PCI_IRDY_N  
PCI_STOP_N  
PCI_PERR_N  
PCI_SERR_N  
PCI_DEVSEL_N  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Initiator Ready  
Stop  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
I/O  
I/O  
I/O  
I/O  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
Parity Error  
System Error  
Device Select  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
Connect signal to same pin between  
the two devices.  
Connect a 10-KΩ pull-up resistor.  
Connect one of the higher order PCI  
address signals to the Device.  
Connect a 10K pull-up resistor to the  
Host.  
PCI_IDSEL  
I
I
I
I
Initialization Device Select  
Arbitration Request  
On the Option device, these signals are not  
used, they should be pulled high with a 10-KΩ  
resistor.  
Note: The PCI_REQ_N[n] must correspond  
to the PCI_GNT_N[n], where n must  
be the same number in the square  
bracket.  
From the Option device, connect output  
signal PCI_REQ_N[0] to one of the  
PCI_REQ_N[3:0] inputs to the Host.  
Note: the PCI_REQ_N[n] must  
correspond to the PCI_GNT_N[n],  
where n must be the same number in  
the square bracket.  
PCI_REQ_N[3:1]  
Arbitration Request  
From the Option device, connect output  
PCI_REQ_N[0] to one of the  
On the Option device, this signal is an output  
and must be connected to one of the  
PCI_REQ_N[3:0] inputs to the Host.  
Note: The PCI_REQ_N[n] must correspond  
to the PCI_GNT_N[n], where n must  
be the same number in the square  
bracket.  
PCI_REQ_N[3:0] inputs to the Host.  
PCI_REQ_N[0]  
PCI_GNT_N[3:1]  
PCI_GNT_N[0]  
I
O
O
I
Note: the PCI_REQ_N[n] must  
correspond to the PCI_GNT_N[n],  
where n must be the same number in  
the square bracket.  
Connect one of the Host outputs  
PCI_GNT_N[3:0] to PCI_GNT_N[0]  
input to the Option.  
Note: the PCI_GNT_N[n] must  
correspond to the PCI_GNT_N[n],  
where n must be the same number in  
the square bracket.  
Arbitration Grant  
On the Option device, these signals are not  
used, they should be pulled high with a 10-KΩ  
resistor.  
O
O
Arbitration Grant  
Connect one of the Host outputs  
PCI_GNT_N[3:0] to PCI_GNT_N[0]  
input to the Option.  
Note: the PCI_GNT_N[n] must  
correspond to the PCI_GNT_N[n],  
where n must be the same number in  
the square bracket.  
On the Option device, this signal is an input  
and must be connected to one of the  
PCI_GNT_N[3:0] outputs of the Host.  
Note: The PCI_REQ_N[n] must correspond  
to the PCI_GNT_N[n], where n must  
be the same number in the square  
bracket.  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Table 18.  
PCI Host/Option Interface Pin Description (Sheet 3 of 3)  
Option  
Type  
Field  
Type  
Field  
Name  
Device-Pin Connection  
Description  
Interrupt A  
Connect PCI_INTA_N output from the  
Option to one of the GPIO input signals  
of the Host. The GPIO signal at the  
Host must be configure as an input  
interrupt level sensitive.  
This interrupt is generated from the Option to  
one of the GPIO inputs to the Host.  
On the Host this signal is not used, it should  
be pulled high with a 10-KΩ resistor.  
PCI_INTA_N  
O/D  
O/D  
Clock must be connected to both  
devices. Trace lengths must be  
matched. Use point to point clock  
distribution.  
PCI_CLKIN  
I
I
Clock input  
3.11.4  
Design Notes  
• The IXP43X network processors do not support the 5 V PCI signal interface by  
itself. Only the 3.3 V signal interface is supported without signal level conversion;  
however, it is possible to interface to 5 V logic while using a voltage level converter.  
• The PCI Local Bus Specification, Rev. 2.2 requires that the bus is always parked,  
as some device is always driving the AD lines. You must use pull-ups on these  
signals. The specification states that the following control lines should be pulled up:  
— FRAME_N  
— STOP_N  
— INTA_N  
— TRDY_N  
— SERR_N  
— INTB_N  
— IRDY_N  
— PERR_N  
— INTC_N  
— DEVSEL_N  
— LOCK_N  
— INTD_N  
• The GPIO pins of the IXP43X network processorscan be used by PCI devices on PCI  
slots to request an interrupt from the processors’ PCI controller.  
• PCI_INTA_N is used to request interrupts to external PCI Masters. This signal is an  
open drain and requires a pull-up resistor.  
3.12  
JTAG Interface  
JTAG is the popular name for IEEE standards 1149.1-1990 and 1149.1a-1993, IEEE  
Standard Test Access Port and Boundary-Scan Architecture, which provides support  
for:  
• Board-level boundary-scan connectivity testing  
• Connection to software debugging tools through the JTAG interface  
• In-system programming of programmable memory and logic devices on the PCB  
The interface is controlled through five dedicated test access port (TAP) pins: TDI, TMS,  
TCK, nTRST, and TDO, as described in the IEEE 1149.1 standard. The boundary-scan  
test-logic elements include the TAP pins, TAP controller, instruction register,  
boundary-scan register, bypass register, device identification register, and data-specific  
®
registers. These are described in the Intel IXP43X Product Line of Network Processors  
Developer’s Manual.  
The IXP43X network processors can be controlled during debug through a JTAG  
interface to the processor, the debug tools such as the Macraigor Systems Raven*, EPI  
Majic*, Wind River Systems* visionPROBE*/ visionICE* or various other JTAG tools  
plug into the JTAG interface through a connector.  
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3.12.1  
Signal Interface  
Table 19.  
Synchronous Serial Peripheral Port Interface  
Pull  
Up/  
Down  
Type  
Field  
Name  
Recommendations  
Test mode select.  
JTG_TMS  
I
Yes  
When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ  
resistor.  
Test Input data.  
JTG_TDI  
JTG_TDO  
I
O
I
Yes  
O
When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ  
resistor.  
Test Output data.  
Test Reset.  
JTG_TRST_N  
Yes  
When the JTAG interface is not being used, the signal must be pulled low using a 10-kΩ  
resistor.  
Test Clock.  
JTG_TCK  
I
Yes  
When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ  
resistor.  
3.13  
Input System Clock  
The IXP43X network processors require a 33.33-MHz reference clock to generate all  
internal clocks required including core clock and the various buses running internally  
within the system.  
3.13.1  
Clock Signals  
Table 20.  
Clock Signals  
Type  
Field  
Name  
Description  
Source must be a clock input of 33.33-MHz.  
Use a series termination resistor, 10 Ω to 33 Ω at the source.  
OSC_IN  
I
OSC_OUT  
O
No connect  
3.13.2  
Clock Oscillator  
While using an external clock oscillator to supply the 33.33-MHz reference system  
clock, connect the clock oscillator output to the OSC_IN pin through a series  
termination of 33 Ω as shown in Figure 14. The series termination helps to smooth the  
rise and fall edges of the clock and eliminate ringing. Leave the OSC_OUT pin  
unconnected.  
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Figure 14.  
Clock Oscillator Interface Example  
3.3 V  
OUT  
33 K  
VDD  
ON  
OSC_IN  
10 KΩ  
0.01 µF  
33.33 MHz  
OSC_OUT  
Intel® IXP43X  
Product Line of  
Network  
Processors  
B4111-005  
3.13.3  
Recommendations for Crystal Selection  
The parameters that should be considered while selecting the crystal to be used are:  
Frequency  
33.33 MHz  
Operation Mode  
Fundamental  
Load  
18 pF (This is the capacitance value of the discrete component) *Note1  
+/- 30 ppm  
Capacitance  
Frequency  
Tolerance  
Frequency  
stability over  
temperature  
+/- 50 ppm  
Effective Series  
20 ohm *Note2  
> 100 uW  
Resistance (ESR)  
Drive level  
Note:  
1) The capacitance value here does not include stray capacitance. The design has been  
simulated to work with load capacitance up to 36pF.  
2) This does not include the stray resistance. The design has been simulated to work up  
to 40 ohm series resistance.  
The Rf and Rs may not needed. Please refer to the crystal vendor datasheet for  
recommendation.  
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Figure 15.  
Recommended circuit design on PCB for crystal oscillator  
osc_out  
osc_in  
RF=1Mohm  
xtal  
RS  
C
C
3.14  
Power  
The IXP43X network processors have separate power supply domains for the processor  
core, DDRII/I SDRAM memory, and input/output peripherals to enable low power  
system design.  
Table 21.  
Power Supply  
Nominal  
Name  
voltage  
Description  
VCC  
1.3V  
3.3V  
1.3-V power supply input pins are used for the internal logic.  
VCC33  
3.3-V power supply input pins are used for the peripheral (I/O) logic.  
1.8V or  
2.5V  
VCCDDR  
VSS  
1.8-V or 2.5-V power supply input pins are used for the DDRII/I memory interface.  
Ground power supply input pins are used for the 3.3-V, 2.5-V, 1.8-V, and the 1.3-V power  
supplies.  
GND  
5.0V  
5-V power supply input pins are used for reference voltage.  
Note: 3.3-V power supply input can be used but causes damage to the USB controller if signal  
pin is shorted to 5V VBUS.  
USB_v5REF  
VCCP_OSC  
3.3-V power supply input pins are used for peripheral (I/O) logic of the analog oscillator circuitry.  
®
3.3V  
Require special power filtering circuitry. See the Intel IXP43X Product Line of Network  
Processors Datasheet  
1.3V  
GND  
1.3-V power supply input pin. Dedicated for Fuse.  
Specialized ground for USB Band Gap.  
1.3-V power supply input pins are used for USB PLL.  
VCCF  
VSSAUBG  
®
VCCAUPLL  
VCCAUBG  
1.3V  
3.3V  
Requires special power filtering circuitry.See the Intel IXP43X Product Line of Network  
Processors Datasheet  
3.3-V power supply input pins are used for USB Band Gap  
®
Requires special power filtering circuitry. See the Intel IXP43X Product Line of Network  
Processors Datasheet  
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Nominal  
Name  
voltage  
Description  
VCCPUSB  
3.3V  
1.3V  
3.3-V power supply input pins are used for USB IO.  
VCCUSBCORE  
1.3-V power supply input pins are used for USB IO core.  
1.3-V power supply input pins are used for internal logic of the analog phase lock-loop circuitry.  
®
VCCA  
1.3V  
Requires special power filtering circuitry. See the Intel IXP43X Product Line of Network  
Processors Datasheet  
3.14.1  
Decoupling Capacitance Recommendations  
It is common practice to place decoupling capacitors between the supply voltages and  
ground. Placement can be near the input supply pins and ground, with one 100-nF  
capacitor per pin. Additional decoupling capacitors can be place all over the board  
every 0.5" to 1.0". This ensures good return path for currents and reduce power surges  
and high-frequency noise.  
It is also recommended that 4.7-µF to 10-µF capacitors be placed every 2" to 3".  
3.14.2  
3.14.3  
3.14.4  
VCC Decoupling  
Connect one 100-nF capacitor per each VCC pin. Placement should be as close as  
possible to the pin. It is also recommended to place a 4.7-µF capacitor near the device.  
Use traces as thick as possible to eliminate voltage drops in the connection.  
VCC33 Decoupling  
Connect one 100-nF capacitor per each Vcc33 pin. Placement should be as close as  
possible to the pin. It is also recommended to place a 4.7-µF capacitor near the device.  
Use traces as thick as possible to eliminate voltage drops in the connection.  
VCCDDR Decoupling  
Connect one 100-nF capacitor per each VCCDDR pin. Placement should be as close as  
possible to the pin. It is also recommended to place a 4.7-µF capacitor near the device.  
Use traces as thick as possible to eliminate voltage drops in the connection.  
3.14.5  
3.14.6  
Power Sequence  
Power sequence is crucial for proper functioning of the IXP43X network processors. For  
®
a complete description of power sequencing, see the Intel IXP43X Product Line of  
Network Processors Datasheet.  
Reset Timing  
Proper reset timing is also a crucial requirement for proper functioning of the IXP43X  
network processors. There are two reset signal PWRON_RESET_N and RESET_IN_N  
which required assertion sequence.  
®
For a complete description of their functionality, see the Intel IXP43X Product Line of  
Network Processors Datasheet and its section titled Reset Timings. PWRON_RESET_N  
is used as a Power Good and RESET_IN_N is used for resetting internal registers.  
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pull-down resistors on the address expansion bus signals EX_ADDR[23:21]. For a  
complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 22.  
§ §  
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4.0  
General PCB Guide  
4.1  
PCB Overview  
Beginning with components selection, this chapter presents general PCB guidelines. In  
cases where it is too difficult to adhere to a guideline, engineering judgment must be  
used. The methods are listed as simple DOs and DO NOT’s.  
This chapter does not discuss the functional aspects of any bus, or layout guides for  
any interfaced devices.  
4.2  
4.3  
General Recommendations  
It is recommended that boards based on the IXP43X network processors employ a PCB  
stackup yielding a target impedance of 50 Ω ± 10% with 5 mil nominal trace width.  
That is, the impedance of the trace when not subjected to the fields created by  
changing current in neighboring traces.  
When calculating flight times, it is important to consider the minimum and maximum  
impedance of a trace based on the switching of neighboring traces. Using wider spaces  
between the traces can minimize this trace-to-trace coupling. In addition, these wider  
spaces reduce crosstalk and settling time.  
Component Selection  
• Do not use components faster than necessary  
Clock rise (fall) time should be as slow as possible, as the spectral content of the  
waveform decreases  
• Use components with output drive strength (slew-rate) controllable if available  
• Use SMT components (not through-hole components) as through-hole (leaded)  
components have more stub inductance due to the protruding leads.  
• Avoid sockets when possible  
• Minimize number of connectors  
4.4  
As shown in Figure 16 on page 57, when placing components, put:  
• High-frequency components in the middle  
• Medium-frequency around the high-frequency components  
• Low-frequency components around the edge of the printed circuit board  
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Figure 16.  
Component Placement on a PCB  
C
O
N
N
E
C
T
Medium Frequency  
High Frequency  
Components  
O
R
Analog Circuit  
Low Frequency  
PCB  
B2264-01  
• Place noisy parts (clock, processor, video, and so on.) at least 1.5 – 3 inches away  
from the edge of the printed circuit board  
• Do not place noisy components close to internal/external cables  
— Any loose cables picks up noise and acts as an antenna to radiate that noise  
— Be aware of the peak in-rush surge current into the device pins. This surge  
current can inject high-frequency switching noise into power planes of the  
printed circuit board  
• Place high-current components near the power sources  
• Do not share the same physical components (such as buffers and inverters)  
between high-speed and low-speed signals. Use separate parts.  
• Place clock drivers and receivers such that clock trace length is minimized  
• Place clock generation circuits near a ground stitch location. Place a localized  
ground plane around the clock circuits and connect the localized plane to system  
ground plane  
• Install clock circuits directly on the printed circuit board, not on sockets  
• Clock crystals should lie flat against the board to provide better coupling of  
electromagnetic fields to the board  
4.5  
Stack-Up Selection  
Stack-up selection directly affects the trace geometry which, in turn, affects the  
characteristic impedance requirement for the printed-circuit board. Additionally, the  
clean, noise-free-planes design and placement is significantly important as  
components run at higher speeds requiring more power.  
Considerations include:  
• Low-speed, printed-circuit-board construction — for example two-layer boards:  
— Advantages:  
• Inexpensive  
• Manufactured by virtually all printed-circuit-board vendors  
— Disadvantages:  
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• Poor routing density  
• Uncontrolled signal trace impedance  
• Lack of power/ground planes, resulting in unacceptable crosstalk  
• Relatively high-impedance power distribution circuitry, resulting in  
noise on the power and ground rails  
• High-speed circuits require multi-layer printed circuit boards:  
— Advantages:  
• Controlled-impedance traces  
• Low-impedance power distribution  
— Disadvantages:  
• Higher cost  
• More weight  
• Manufactured by fewer vendors  
• Symmetry is essential to keep the board stack-up symmetric about the center  
This minimizes warping  
• For best impedance control, have:  
— No more than two signal layers between every power/ground plane pair  
— No more than one embedded micro-strip layer under the top/bottom layers  
• For best noise control, route adjacent layers orthogonally. Avoid layer-to-layer  
parallelism  
• Fabrication house must agree on design rules, including:  
Trace width, trace separation  
— Drill/via sizes  
• The distance between the signal layer and ground (or power) should be minimized  
to reduce the loop area enclosed by the return current  
— Use 0.7:1 ratio as a minimum.  
For example: 5-mil traces, 7-mil prepreg thickness to adjacent power/ground.  
Figure 17 and Figure 18 provides an example for a six-layer and eight-layer board. For  
stripline (signals between planes), the stackup should be such that the signal line is  
closer to one of the planes by a factor of five or more. Then the trace impedance is  
controlled predominantly by the distance to the nearest plane.  
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Figure 17.  
8-Layer Stackup  
4.5 mil  
5 mil  
7 mil  
Legend  
Component (Top) Side  
SIGNAL  
Data  
Data  
Data  
L1  
L2  
L3  
L4  
GND  
17.8 mil  
7 mil  
5 mil  
4.5 mil  
62 mil  
POWER  
Data  
Data  
L5  
L6  
L7  
L8  
Solder (Bottom) Side  
B2244-02  
Figure 18.  
6-Layer Stackup  
Legend  
4.5 mil  
SIGNAL  
GND  
7 mil  
Component (Top) Side  
L1  
~40 mil  
L2  
L3  
7 mil  
62 mil  
POWER  
4.5 mil  
L4  
L5  
L6  
Solder (Bottom) Side  
B2275-02  
• Fast and slow transmission line networks must be considered  
• PCB-board velocities  
• Board FR4 ~ 4.3  
Target impedance of 50 Ω ± 10%  
Trace width: 5 mils  
• Signal Layers (1/2 oz. Copper)  
• Power Layer (1 oz. Copper)  
• Ground (GND) Layer (1 oz. Copper)  
§ §  
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5.0  
General Layout and Routing Guide  
5.1  
Overview  
This chapter provides routing and layout guides for hardware and systems based on the  
IXP43X network processors.  
The high-speed clocking required when designing with the processors requires special  
attention to signal integrity. In fact, it is highly recommended that the board design be  
simulated to determine optimum layout for signal integrity. The information in this  
chapter provides guidelines to aid designers with board layout. In cases where it is too  
difficult to follow a design rule, engineering judgment must be used.  
5.2  
General Layout Guidelines  
The layout guidelines recommended in this section are based on experience and  
knowledge gained from previous designs. Layer stacking varies, depending on design  
complexity, however following standard rules helps minimize potential problems  
dealing with signal integrity.  
The following recommendations help to route a functional board:  
• Provide enough routing layers to comply with minimum and maximum timing  
requirements of the IXP43X network processors and other components.  
• Connectors, and mounting holes must be placed in a ways that will not interfere  
with basic design guidelines in this document.  
• Provide uniform impedance throughout the board, specially for high speed areas  
such us clocking, DDRII/I-SDRAM, PCI, device bus, and so forth.  
• Place analog, high-voltage, power supply, low-speed, and high-speed devices in  
various sections of the board.  
• Decoupling capacitors must be placed next to power pins.  
• Series termination resistors must be placed close to the source.  
• Analog and digital sections of the board must be physically isolated from each  
other. No common ground, power planes, and signal traces are allowed to  
cross-isolation zones. Use appropriately sized PCB traces for larger enough to  
handle peak current. Keep away from high-speed digital signals.  
• Keep stubs as short as possible (preferably, the electrical length of the stub less  
than half of the length of the rise time of signal).  
• All critical signals should be routed before all other non-critical signals.  
• Do not route signals close to the edge of the board, power or ground planes. Route  
signal at least 50 to 100 mils away from the edge of the plane.  
Try to match buses to the same trace length and keep them in groups adjacent to  
each other, away from other signals.  
• Route processor address, data and control signals using a daisy-chain topology.  
• Minimize number of vias and corners on all high speed signals.  
• Do not route under crystals or clock oscillators, clock synthesizers, or magnetic  
devices (ferrites, toroids).  
• Maintain trace spacing consistent between differential pairs and match trace length.  
• Keep differential signals away from long and parallel, high-speed paths, such as  
clock signals and data strobe signals.  
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• Do not place high-frequency oscillators and switching network devices close to  
sensitive analog circuits.  
• Arrange the board so that return currents for high-speed traces must never jump  
between planes. Restrict traces to remain on either side of whichever ground plane  
they start out nearest. This allows the use of naturally grouped horizontal and  
If signals change between layers, the reference voltage changes, as shown in  
Figure 19. This creates discontinuity in the path of the signal.  
Figure 19.  
Signal Changing Reference Planes  
VIAs  
Driver  
Signal  
Receiver  
Signal  
GND  
PWR  
Return Current  
ByPass Caps  
Trace  
Signal  
B2269-01  
The design in Figure 19, routes a signal on the top layer, close to the GND plane, and  
provides a very good return current path. The signal then is routed to the bottom layer,  
close to the PWR plane, such that the return current flows to the ground plane through  
bypass caps. Thus the path for the return currents is less inductive than in the previous  
case where the signal is routed on the top layer.  
5.2.1  
General Component Spacing  
• Do not place components within 125 mils to the edge of the printed circuit board.  
For exact dimensions consult your manufacturing vendor.  
• Keep a minimum spacing between via and the solder pad edges > 25mil.  
• Position devices that interface with each other close to one another to minimize  
trace lengths.  
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Figure 20.  
Good Design Practice for VIA Hole Placement  
25 mils min  
25 mils min  
25 mils min  
B2266-01  
Figure 20 and Figure 21 show good and poor design practices for via placement on  
surface-mount boards.  
Figure 22 shows minimum pad-to-pad clearance for surface-mount passive  
components and PGA or BGA components.  
Figure 21.  
Poor Design Practice for VIA Placement  
Flush Via min  
Potential Bridge min  
B2267-01  
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Figure 22.  
Pad-to-Pad Clearance of Passive Components to a PGA or BGA  
PBGA Package  
60 mils min  
60 mils min  
60 mils min  
B2268 -01  
5.2.2  
Clock Signal Considerations  
• Provide good return current paths for clock traces.  
• Keep clock traces away from the edge of the board and any other high-speed  
devices or traces.  
• Keep clock traces away from analog signals, including voltage reference signals.  
• Clock signals should not cross over a split plane.  
• Route clock signals in a single, internal layers and eliminate routing in multiple  
layers as much as possible.  
• Do not route traces or vias under crystals or clock oscillators devices unless there is  
a plane between the trace and the component.  
• Do not route parallel signal traces directly above or below clock traces unless there  
is a ground or at least a power plane separation between those layers.  
• Route clock traces with a minimum number of vias.  
• Space clock traces away from other signals three times the trace width on each  
side.  
• Use guard traces when routing on top or bottom layers whenever possible. Guard  
traces must be connected to ground.  
• Do not daisy-chain, instead use point-to-point clock distribution. Place a series  
termination resistor as close as possible to the source.  
• Keep traces short to minimize reflections and signal degradation.  
• Maintain control impedance for all clock traces, microstrip or stripline.  
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— Be aware of propagation delays between a microstrip and stripline.  
— Calculate capacitive loading of all components and properly compensate with a  
series or parallel terminations.  
• Measure and match trace lengths for devices that interface with each other and  
have their clock derived from the same source.  
If traces must be long, treat them as transmission lines. Terminate clock traces to  
match trace impedance.  
• If there is a power plane, instead of a ground plane, make sure that the power  
plane has adequate decoupling to ground, especially near clock drivers and  
receivers.  
5.2.3  
5.2.4  
MII Signal Considerations  
MII signals run at 25 MHz and the required routing guide lines are as follows:  
• Minimize the number of vias to two per trace  
• Keep traces as short as possible and straight, away from other signals  
• Control impedance to maintain at 50 Ω  
• the length of Rx or Tx in each group must match  
• Avoid sharp corners, using 45° corners instead  
USB V2.0 Considerations  
The following are recommendations for routing differential pair signal required to by  
the USB interface:  
Traces can be routed in tightly couple structure with 5mil trace width and 10mil air  
gap, or maintain air gap equal 2X trace width. It is recommended to route  
manually.  
• Match trace length for each differential pair.  
• Avoid sharp corners, use 45° corners instead.  
• Always use a perfect symmetry within a differential pair.  
• Minimize the number vias.  
• Avoid routing other signals close by or in parallel to the differential pair,  
maintaining no less than 50 mil to any other signal.  
• Maintain control impedance for each differential pair to 90 Ω +/- 15 Ω.  
• Use high value ferrite beads (100 MHz/60 Ω – 100 MHz/240 Ω).  
5.2.5  
Crosstalk  
Crosstalk is caused by capacitance and inductance coupling between signals. It is  
composed of both backward and forward crosstalk components.  
Backward crosstalk creates an induced signal on the network that propagates in the  
opposite direction of the aggressor signal. Forward crosstalk creates a signal that  
propagates in the same direction as the aggressor signal.  
Circuit board analysis software should be used to analyze your board layout for  
crosstalk problems.  
To effectively route signals on the PCB, signals are grouped (address, data, and so  
on.).  
— The space between groups can be 3 w (where w is the width of the traces).  
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— Space within a group can be just 1 w.  
— Space between clock signals or clock to any other signal should be 3 w. The  
coupled noise between adjacent traces decreases by the square of the distance  
between the adjacent traces.  
5.2.6  
EMI Design Considerations  
It is strongly recommended that good electromagnetic interference (EMI) design  
practices must be followed while designing with the IXP43X network processors.  
®
• Information on spread-spectrum clocking is available in the Intel IXP4XX Product  
Line of Network Processors and IXC1100 Control Plane Processor: Spread-  
Spectrum Clocking to Reduce EMI Application Note.  
• Place high-current devices as closely as possible to the power sources.  
• Proper termination of signals can reduce reflections, which can emit a high-  
frequency component that contribute to more EMI than the original signal itself.  
• Ferrite beads can be used to add high frequency loss to a circuit without  
introducing power loss at DC and low frequencies. They are effective when used to  
absorb high-frequency oscillations from switching transients or parasitic  
resonances within a circuit.  
• Keep rise and fall times as slow as possible. Signals with fast rise and fall times  
contain many high-frequency harmonics which can radiate significantly.  
• A solid ground is essential at the I/O connector to chassis and ground plane.  
• Keep the power plane shorter than the ground plane by at least 5x the spacing  
between the power and ground planes.  
• Stitch together all ground planes around the edge to the board every 100 to  
200 mil. This helps reduce EMI radiating out of the board from inner layers.  
5.2.7  
5.2.8  
Trace Impedance  
All signal layers require controlled impedance of 50 Ω ±10 % microstrip or stripline  
(unless otherwise specified) where appropriate. Selecting the appropriate board stack-  
up to minimize impedance variations is very important.  
When calculating flight times, it is important to consider the minimum and maximum  
trace impedance based on the switching neighboring traces.  
Power and Ground Plane  
sustainable current needed for high-speed switching devices. See Section 3.14.1,  
“Decoupling Capacitance Recommendations” on page 54.  
• It is highly recommended to use sufficient internal power and ground planes.  
®
• The Intel IXP43X Product Line requires a number of power supplies. It is  
appropriate to use power islands in the power plane under the processor, as it will  
be too expensive to have a power plane for each power source.  
• Power islands must be large enough to include the required power supply  
decoupling capacitance, and the necessary connection to the voltage source and  
destination.  
• Islands can be separated by a minimum of 20-mil air gap.  
• Use at least one via per power or ground pin, wherever possible use more vias,  
depending on current drawn.  
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• Use at least one decoupling capacitor per power pin and place it as close as  
possible to the pin.  
• Minimize the number of traces routed across the air gaps between power islands.  
— Each crossing introduces signal degradation due to the impedance  
discontinuity.  
— For traces that must cross air gaps, route them on the side of the board next to  
a ground plane to reduce or eliminate signal degradation caused by crossing  
the gap.  
— When this is not possible, then route the trace to cross the gap at a right angle  
(90°).  
§ §  
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Hardware Design Guidelines—Intel IXP43X Product Line of Network Processors  
6.0  
PCI Interface Design Considerations  
The IXP43X network processors have a single, 32-bit PCI device module that runs at 33  
MHz. This chapter describes some basic guidelines to help design hardware that  
interfaces with PCI devices.  
The PCI module is compatible with the PCI Local Bus Specification, Rev. 2.2. For a  
complete functional description and physical requirements, see the PCI Local Bus  
Specification, Rev. 2.2.  
6.1  
6.2  
Electrical Interface  
The electrical definition is restricted to 3.3 V signaling environment. The device is not  
5 V tolerant. All devices interfacing with the PCI module must operate at 3.3 V.  
Topology  
Interfacing devices must be connected in a daisy-chain topology. When more than one  
device is in the bus, connecting stubs must be kept as short as possible.  
There is a limitation to the number of devices connected to the internal arbiter. If more  
than four devices are required to be connected, an external arbiter is required.  
The system time budget must be satisfied for 33 MHz cycles. The following equation  
and timing parameters must be met while routing a board that interfaces with a single  
PCI device or up to four devices as shown in Figure 23.  
TCYC TVAL +TPROP + TSKEW + TSU  
where:  
TVAL = Valid Output Delay  
TPROP = Bus Propagation Delay (maximum time for complete flight)  
TSKEW = Total Clock Skew  
TSU = Input Setup Time  
@33 MHz  
TCYC = 30 nSec  
TVAL = 11 nSec  
TPROP = 10 nSec  
TSKEW = 2 nSec  
TSU = 7 nSec  
When defining the maximum length of segments A and B as shown in Figure 23, the  
calculation must:  
• Include an additional trace length segment from the PCI connector to the input  
device within the expansion PCI card  
• Assume the segment to be 1.5 inch  
• Use trace propagation delay of 150 to 190 ps/in as specified by the PCI standard  
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Intel IXP43X Product Line of Network Processors—Hardware Design Guidelines  
Figure 23.  
PCI Address/Data Topology  
Intel® IXP43X  
Product Line of  
Network  
PCI Slot  
PCI Slot  
PCI Slot  
PCI Slot  
Processors  
A
B
B
B
B5196-003  
Table 22.  
PCI Address/Data Routing Guidelines  
Parameter  
Routing Guidelines  
Signal Group  
PCI Address/Data  
Daisy Chain  
Ground  
Topology  
Reference Plane  
Characteristic Trace Impedance  
Nominal Trace Width  
55 Ω ±10%  
5 mils  
Nominal Trace Separation  
Spacing to Other Groups  
Limit the number of VIAS to 10 per Signal  
10 mils  
20 mils  
10  
6.3  
Clock Distribution  
To meet timing and avoid clock overloading, it is recommended to use point-to-point  
clock distribution as shown in Figure 24.  
Clock skew between interfacing devices is very critical and must be met. The maximum  
skew must be measured between any two components. If designing a motherboard,  
the skew must be measured to the expansion card device and not to the PCI connector.  
Ensure that clock skew between all devices does not exceed the values in Section 6.2.  
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Figure 24.  
PCI Clock Topology  
PCI Devices  
A
A
B
B
Rs  
Rs  
Clock  
Driver  
33 MHz  
Intel®  
IXP43X  
A
Product Line  
of Network  
Processors  
B
Rs  
B4114-004  
Table 23.  
PCI Clock Routing Guidelines  
Parameter  
Routing Guidelines  
Signal Group  
PCI Clock  
Topology  
Point-to-Point  
Ground  
Reference Plane  
Characteristic Trace Impedance  
Nominal Trace Width  
Nominal Trace Separation  
Spacing to Other Groups  
Trace length A  
55 Ω ±10%  
5 mils  
10 mils  
20 mils  
Maximum 300 mils  
There is no limit as long as the trace length is maintained for  
each clock and that maximum clock skew is not violated.  
Trace length B  
Resistor Rs  
22 Ω ±10%  
Maximum VIAS  
6
6.3.1  
Trace Length Limits  
Maximum trace lengths can be calculated for specific speeds at which the bus is  
intended to run. The limitations of the maximum trace length can be calculated with  
the equations shown in Section 6.2. Solve for TPROP and use it to calculate the maximum  
trace length. This is a straight-forward calculation, but very critical to meet timing. It is  
recommended to keep the trace lengths as short as possible and not to exceed TPROP  
.
Note:  
For acceptable signal integrity at up to 33 MHz, it is very important to design the PCB  
board with controller impedance in the range of 55 Ω ±10%.  
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6.3.2  
Routing Guidelines  
It is recommended to route signals with respect to an adjacent ground plane. If routing  
signals over power planes, ensure that the signals are referenced to a single power  
plane voltage level and not multiple levels. For example, you can route signals over a  
3.3 V plane or a 5 V plane, but do not route the same signal over both planes. If signals  
are routed over split planes, you must connect the splitting planes with 0.01 µF,  
high-speed capacitors near the signal crossing the split. The capacitors should not be  
placed more than 0.25 inches from the point at which the signals cross the split.  
This manual does not repeat all the guidelines that are already stated in the  
PCI Local Bus Specification, Rev. 2.2. Refer to the specification when designing a  
motherboard or an expansion card.  
6.3.3  
Signal Loading  
Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of  
expansion board or add-on device trace length or loading limits compromises  
system-signal integrity.  
§ §  
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7.0  
DDRII / DDRI SDRAM  
7.1  
Introduction  
This document is intended to be used as a guide for routing DDRII/DDRI SDRAM based  
®
on the Intel IXP435 Multi-Service Residential Gateway Reference Platform. It contains  
routing guidelines and simulation results for using x16 Thin Small Outline Package  
(TSOP) memory devices soldered onto the processor module.  
The memory controller only corrects single bit ECC errors on read cycles. The ECC is  
stored into the DDRII/DDRI SDRAM array along with the data and is checked when the  
data is read. If the code is incorrect, the MCU corrects the data before reaching the  
initiator of the read. ECC error scrubbing is done with software. User-defined fault  
correction software is responsible for scrubbing the memory array and handling double-  
bit errors.  
To limit double-bit errors from occurring, periodically read the entire usable memory  
array to allow the hardware unit within the memory controller to correct any single-bit.  
This also prevents the ECC errors that would have occurred prior to these errors  
becoming double-bit ECC errors. Implementing this method is system-dependent.  
Note:  
It is important to note that when sub-word writes (byte writes or half-word writes  
within a word-aligned boundary) are done to a 32-bit memory with ECC enabled, the  
memory controller performs read-modify writes. There is a performance impact with  
read-modify writes that must be considered when writing software.  
With read-modify writes, the memory controller reads the 32-bit word that  
encompasses the byte that is to be written when a byte write is requested. The  
memory controller modifies the specified byte, calculates a new ECC, and writes the  
entire 32-bit word back into the memory location it was read from.  
The value written back into the memory location contains the 32-bit word with the  
modified byte and the new ECC value.  
The MCU supports two physical banks of DDRII/DDRI SDRAM. The MCU has support for  
unbuffered DDRI 266 and DDRII 400 in the form of discrete chips only.  
The MCU supports a memory subsystem ranging from 32 MB to 1 GB for 32-bit  
memory systems for DDRI SDRAM, from 64 MB to 512 MB for 32-bit memory systems  
for DDRII SDRAM, and supports 16 MB for 16-bit memory systems for DDRI SDRAM  
(non-ECC), and 32 MB for 16-bit memory systems for DDRII SDRAM (non-ECC). An  
ECC or non-ECC system can be implemented using x8, or x16 devices. Table 25,  
Table 26, Table 27 and Table 28 illustrate the supported DDRII/DDRI SDRAM  
configurations  
The two DDRII/DDRI SDRAM chip enables (DDR_CS_N[1:0]) support a DDRII/DDRI  
SDRAM memory subsystem consisting of two banks. The base address for the two  
contiguous banks are programmed in the DDRII/DDRI SDRAM Base Register (SDBR)  
and is aligned to a 16 MB boundary. The size of each DDRII/DDRI SDRAM bank is  
programmed with the DDRII/DDRI SDRAM boundary registers (SBR0 and SBR1).  
The DDRII/DDRI SDRAM devices comprise four internal leaves. The MCU controls the  
leaf selects within DDRII/DDRI SDRAM by toggling DDR_BA[0] and DDR_BA[1].  
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Table 24.  
DDRII/I Signal Groups  
Group  
Signal Name  
Description  
D_CK[2:0] / DDR_CK[2:0] DDRII/I SDRAM Differential Clocks  
Clocks  
D_CK_N[2:0] /  
DDRII/I SDRAM Inverted Differential Clocks  
DDR_CK_N[2:0]  
D_CB[7:0] / DDR_CB[7:0] ECC Data  
D_DQ[31:0] /  
Data Bus  
DDR_DQ[31:0]  
D_DQS[4:0] /  
Data Strobes  
DDR_DQS[4:0]  
Data  
D_DQS_N[4:0]  
Complementary Data Strobes  
Data Mask  
D_DM[4:0] /  
DDR_DM[4:0]  
D_CKE[1:0] /  
DDR_CKE[1:0]  
Clock Enable - one per bank  
Chip Select - one per bank  
Address Bus  
Control  
D_CS_N[1:0] /  
DDR_CS_N[1:0]  
D_MA[13:0] /  
DDR_MA[13:0]  
D_BA[1:0] / DDR_BA[1:0] Bank Select  
Command  
D_RAS_N / DDR_RAS_N  
D_CAS_N / DDR_CAS_N  
D_WE_N / DDR_WE_N  
Row Address Select  
Column Address Select  
Write Enable  
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Figure 25.  
Processor-DDRII/I SDRAM Interface  
DDRII/I_DQ[31:0]  
DDRII/I_MA[13:0]  
DATA[31:0]  
DQ[31:0]  
A[13:0]  
ADDRESS[13:0]  
CLOCK[2:0], CLOCK#[2:0]  
CLOCK ENABLE[1:0]  
CHIP SELECT#[1:0]  
DDRII/I_CK[2:0]  
DDRII/I_CK_N[2:0]  
CK[2:0]  
CK#[2:0]  
DDRII/I_CKE[1:0]  
DDRII/I_CS_N[1:0]  
DDRII/I_BA[1:0]  
CKE[1:0]  
CS#[1:0]  
BA[1:0]  
BANK SELECT[1:0]  
DDRII/I_CB[7:0]  
DDRII/I_DM[4:0]  
ECC DATA[7:0]  
DQ[7:0]  
DM[4:0]  
DATA MASK[4:0]  
DDRII/I_DQS[4:0]  
DATA STROBE[4:0]  
WRITE#, RAS#, CAS#  
DQS[4:0]  
WE#  
RAS#  
CAS#  
DDRII/I_WE_N  
DDRII/I_RAS_N  
DDRII/I_CAS_N  
B3986-003  
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Table 25.  
Supported DDRI 32-bit SDRAM Configurations  
Address Size  
Leaf Select  
Total  
DDR SDRAM  
Technology  
DDR SDRAM  
Arrangement  
Page  
# Banks  
Memory  
b
Size  
a
Row  
Column  
DDR_BA[1]  
DDR_BA[0]  
ADDR[25]  
Size  
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
64 M  
128 M  
32 M  
4KB  
4KB  
2KB  
2KB  
4KB  
4KB  
2KB  
2KB  
8KB  
8KB  
4KB  
4KB  
8KB  
8KB  
4KB  
4KB  
16 M x 8  
8 M x 16  
32 M x 8  
16 M x 16  
64 M x 8  
32 M x 16  
128 M x 8  
64 M x 16  
12  
10  
ADDR[26]  
ADDR[25]  
ADDR[27]  
ADDR[26]  
ADDR[28]  
ADDR[27]  
ADDR[29]  
ADDR[28]  
c
128 Mbit  
12  
13  
13  
13  
13  
14  
14  
9
ADDR[24]  
ADDR[26]  
ADDR[25]  
ADDR[27]  
ADDR[26]  
ADDR[28]  
ADDR[27]  
64 M  
128 M  
256 M  
64 M  
10  
9
256 Mbit  
512 Mbit  
128 M  
256 M  
512 M  
128 M  
256 M  
512 M  
1 G  
11  
10  
11  
10  
c
1 Gbit  
256 M  
512 M  
a. Table indicates 32-bit wide memory subsystem sizes.  
b. Table indicates 32-bit wide memory page sizes.  
c. Supported with DDR SDRAM only  
Table 26.  
Supported DDRII 32-bit SDRAM Configurations  
Address Size  
Row Column  
Leaf Select  
Total  
Memory  
Size  
DDR SDRAM  
Technology  
DDR SDRAM  
Arrangement  
# of  
Banks  
Page  
Size  
DDR_BA[1]  
DDR_BA[0]  
1
2
1
2
1
2
1
2
128MB  
256MB  
64MB  
4KB  
4KB  
2KB  
2KB  
4KB  
4KB  
4KB  
4KB  
32M x 8  
16M x16  
64M x 8  
32M x16  
13  
13  
14  
13  
10  
9
ADDR[27]  
ADDR[26]  
256 Mbit  
ADDR[26]  
ADDR[28]  
ADDR[27]  
ADDR[25]  
ADDR[27]  
ADDR[26]  
128MB  
256MB  
512MB  
128MB  
256MB  
10  
10  
512 Mbit  
Table 27.  
Supported DDRI 16-bit SDRAM Configurations  
Address Size  
Leaf Select  
Total  
Memory  
Size  
DDR SDRAM  
Technology  
DDR SDRAM  
Arrangement  
# of  
Banks  
Page  
Size  
Row  
Column  
DDR_BA[1]  
DDR_BA[0]  
128 Mbit  
8M x16  
1
12  
9
ADDR[23]  
ADDR[22]  
16MB  
1KB  
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Table 28.  
Supported DDRII 16-bit SDRAM Configurations  
Address Size  
Leaf Select  
Total  
Memory  
Size  
DDR SDRAM  
Technology  
DDR SDRAM  
Arrangement  
# of  
Banks  
Page  
Size  
DDR_BA[1  
]
Row  
13  
Column  
DDR_BA[0]  
256 Mbit  
16M x16  
1
9
ADDR[24]  
ADDR[23]  
32MB  
The DDR_RCOMP signal must be terminated through resistors specified in Figure 26.  
This allows the DDRII/I controller to make temperature and process adjustments.  
7.2  
DDRII/DDRI RCOMP and Slew Resistances Pin  
Figure 26 shows the requirements for the DDRII/DDRI RCOMP pin.  
Figure 26.  
DDRII/DDRI RCOMP Pin External Resistor Requirements  
DDRI  
R1 =387Ω ±1%  
resistor  
OR  
DDRII  
R 1 =285Ω ±1 % resistor  
DDRIMPCRES  
R1  
R2  
Intel® IXP43X  
Product Line of  
Network Processors  
DDRCRES  
0
DDRSLWCRES  
DDRI  
R2 =845Ω ±1% resistor  
OR  
DDRII  
R 2 =825Ω ±1 % resistor  
For example, when DDRI SDRAM is used, DDRIMPCRES is connected with 387Ω and  
DDRSLWCRES is connected with 845Ω resistor to DDRCRES0.  
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7.3  
Figure 27 shows the requirement for the DDRRES1 and DDRRES2 pins.  
Figure 27.  
DDRII OCD Pin Requirements  
DDRRES2  
Intel® IXP43X  
Product Line  
of Network  
Processors  
DDRRES1  
0. 1 uF  
1 K  
Ω
40.2  
resistor  
Ω
resistor  
Note:  
Since the OCD calibration function is not enabled, DDRRES2 must be pulled to ground  
with a 1-KΩ resistor.  
7.3.1  
Signal-Timing Analysis  
Figure 28.  
DDR Clock Timing Waveform  
V
V
tch  
tcl  
V
ih(min)  
V
ih (min)  
V
test  
V
test  
V
V
V
il(max )  
il(max)  
il(max )  
T
CH  
T
CL  
T
C
Table 29.  
DDR Clock Timings  
DDR-II 400  
DDR-I 266  
Symbol  
Parameter  
Units  
Notes  
Min  
Max  
Min  
Max  
T
DDR SDRAM clock Frequency  
DDR SDRAM clock Cycle Time  
DDR SDRAM clock High Time  
DDR SDRAM clock Low Time  
200  
133  
MHz  
ns  
F
T
5
7.5  
1
1
1
C
T
2.15  
2.15  
3.37  
3.37  
ns  
CH  
T
ns  
CL  
T
DDR SDRAM clock Period Stability  
350  
100  
350  
100  
ps  
CS  
DDR SDRAM clock skew for any  
differential clock pair (D_CK[2:0] -  
T
ps  
skew  
Notes:  
1.  
2.  
See Figure 28, “DDR Clock Timing Waveform” on page 76  
Vtest is nominally (0.5 * Vtch - Vtcl)  
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Figure 29.  
DDR SDRAM Write Timings  
TVA3  
ADDR/CTRL  
TVB3  
TVA5  
CS[1:0]#  
TVB5  
CK  
DQS  
DQS#  
T VA1  
TV7  
TVB1  
DQ  
Figure 30.  
DDR SDRAM Read Timings  
DQS  
TVB4  
TVA4  
DQ  
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Figure 31.  
DDR - Write Preamble/Postamble Duration  
TVB6  
DQS  
TVA6  
DQS  
Table 30.  
DDRII-400 MHz Interface -- Signal Timings  
Symbol  
Parameter  
Minimum  
Nominal  
Maximum  
Units  
Notes  
T
T
DQ, CB and DM write output valid time before DQS.  
DQ, CB and DM write output valid time after DQS.  
521  
521  
ps  
ps  
1
1
VB1  
VA1  
Address and Command write output valid before CK  
rising edge.  
T
T
T
T
1771  
1771  
323  
ps  
ps  
ps  
ps  
1, 4  
1, 4  
2
VB3  
VA3  
VB4  
VA4  
Address and Command write output valid after CK rising  
edge.  
DQ, CB and DM read input valid time before DQS rising  
or falling edges.  
DQ, CB and DM read input valid time after DQS rising or  
falling edges.  
323  
2
T
T
T
T
CS_N[1:0] control valid before CK rising edge.  
CS_N[1:0] control valid after CK rising edge.  
DQS write preamble duration.  
1771  
1771  
ps  
ps  
ps  
ps  
ps  
4
4
3
3
1
VB5  
VA5  
VB6  
VA6  
3750  
2500  
1750  
DQS write postamble duration.  
T
V7  
Notes:  
1.  
2.  
See Figure 29, “DDR SDRAM Write Timings” on page 77  
See Figure 30, “DDR SDRAM Read Timings” on page 77. The specified minimum requirements for the “Data to strobe  
read setup” and “Data from strobe read hold” are determined with the DQS delay programmed for 90 degree phase  
shift.  
3.  
4.  
5.  
See Figure 31, “DDR - Write Preamble/Postamble Duration” on page 78  
Address/Command pin group; RAS_N, CAS_N, WE_N, MA[13:0], BA[1:0]  
Designed to JEDEC specification; it is recommended that IBIS models should be used to verify signal integrity on  
individual designs  
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Table 31.  
DDR II/I SDRAM Interface -- Signal Timings  
Symbol  
Parameter  
Minimum  
Nom.  
Maximum  
Units  
Notes  
DQ, CB and DM write output valid time  
before DQS.  
T
T
T
T
T
T
T
1146  
ps  
1
VB1  
VA1  
VB3  
VA3  
VB4  
VA4  
VB5  
DQ, CB and DM write output valid time after  
DQS.  
1146  
3021  
3021  
948  
ps  
ps  
ps  
ps  
ps  
ps  
1
1, 4  
1, 4  
2
Address and Command write output valid  
before CK rising edge.  
Address and Command write output valid  
after CK rising edge.  
DQ, CB and DM read input valid time before  
DQS rising or falling edges.  
DQ, CB and DM read input valid time after  
DQS rising or falling edges.  
948  
2
CS_N[1:0] control valid before CK rising  
edge.  
3021  
3021  
4
T
T
T
CS_N[1:0] control valid after CK rising edge.  
DQS write preamble duration.  
ps  
ps  
ps  
ps  
4
3
3
1
VA5  
VB6  
VA6  
5625  
3750  
1750  
DQS write postamble duration.  
T
V7  
Notes:  
1.  
2.  
See Figure 29, “DDR SDRAM Write Timings” on page 77  
strobe read setup” and “Data from strobe read hold” are determined with the DQS delay programmed for  
90 degree phase shift.  
3.  
4.  
5.  
See Figure 31, “DDR - Write Preamble/Postamble Duration” on page 78  
Address/Command pin group; RAS_N, CAS_N, WE_N, MA[13:0], BA[1:0]  
Designed to JEDEC specification; it is recommended that IBIS models should be used to verify signal  
integrity on individual designs  
7.3.1.0.1  
Printed Circuit Board Layer Stackup  
®
The layer stackup used for the Intel IXP435 Multi-Service Residential Gateway  
Reference Platform is a 6-layer, printed circuit board with four signal layers and two  
plane layers.  
Details on the voltage reference layout are available in the CAD database or Gerber  
®
files database for the Intel IXP435 Multi-Service Residential Gateway Reference  
Platform.  
7.3.2  
Timing Relationships  
The routing guidelines presented in the following subsections define the recommended  
routing topologies, trace width, spacing geometries, and typical routed lengths for each  
signal group. These parameters are recommended to achieve optimal signal integrity  
and timing.  
All signal groups are length matched to the DDR clocks. The clocks on the processor  
module are length matched to within ±10 mils of each other. Once this overall clock  
length for any given DDR differential clock is determined, the command and control  
signals can be routed to within the timing specified. A simple summary of the timing  
results for each signal group is provided in Table 32 on page 80.  
Control/Command Group to Clock Summary:  
• The maximum allowable difference from any command/control signal to the clock is  
±0.6 ns.  
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Table 31 on page 79  
Data Group to Strobe Summary:  
• The more restrictive data group to strobe timing occurs for read operations  
Table 32 on page 80  
Table 33 on page 80  
• The maximum allowable difference from any data group signal to the strobe is  
±0.25 ns.  
Figure 30 on page 77  
Table 32 on page 80  
Strobe to Clock Summary:  
• The maximum allowable difference from any data strobe signal to the clock is -  
0.475 ns to +0.875 ns  
Figure 32 on page 83  
Table 34 on page 83  
These are absolute maximum ratings for length mismatch based in ideal printed board  
conditions (exact signal propagation delays, ideal signal integrity with no reflections or  
settling, zero rise/fall times, and so on.). To compensate for these non-ideal conditions,  
more restrictive length matching conditions should be used based on signal integrity  
analysis and simulation to provide a buffer zone and avoid possible variations in silicon  
or printed circuit board manufacture.  
Table 32.  
Timing Relationships  
Signal Group  
Absolute Minimum Length  
Absolute Maximum Length  
Control to Clock  
Command to Clock  
Data to Strobe  
Clock – 600 ps  
Clock – 600 ps  
Strobe – 250 ps  
Clock – 475 ps  
Clock + 600 ps  
Clock + 600 ps  
Strobe + 250 ps  
Clock + 875 ps  
Strobe to Clock  
In addition to any trace length differentials which must be considered between signal  
groups, differences in the package length between signals should be considered when  
determining the total propagation delay of the signals. When using the IXP435  
reference platform IBIS model for signal analysis, package characteristics are included  
in the simulation results.  
Table 33.  
Signal Package Lengths (Sheet 1 of 3)  
Group  
Signal Name  
Length (mil)  
Signal Name  
Length (mil)  
D_CK_N0 /  
DDR_CK_N0  
558.19  
D_CK0 / DDR_CK0  
507.46  
D_CK_N1 /  
DDR_CK_N1  
Clock  
385.12  
504.20  
D_CK1 / DDR_CK1  
D_CK2 / DDR_CK2  
385.12  
548.01  
D_CK_N2 /  
DDR_CK_N2  
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Table 33.  
Signal Package Lengths (Sheet 2 of 3)  
Group  
Signal Name  
Length (mil)  
Signal Name  
Length (mil)  
D_CB0 / DDR_CB0  
D_CB1 / DDR_CB1  
D_CB2 / DDR_CB2  
D_CB3 / DDR_CB3  
402.94  
393.93  
377.69  
378.47  
D_CB4 / DDR_CB4  
D_CB5 / DDR_CB5  
D_CB6 / DDR_CB6  
D_CB7 / DDR_CB7  
385.50  
419.24  
398.22  
435.03  
D_DQ16 /  
D_DQ0 / DDR_DQ0  
D_DQ1 / DDR_DQ1  
D_DQ2 / DDR_DQ2  
D_DQ3 / DDR_DQ3  
D_DQ4 / DDR_DQ4  
D_DQ5 / DDR_DQ5  
D_DQ6 / DDR_DQ6  
D_DQ7 / DDR_DQ7  
D_DQ8 / DDR_DQ8  
D_DQ9 / DDR_DQ9  
D_DQ10/ DDR_DQ10  
D_DQ11 / DDR_DQ11  
D_DQ12 / DDR_DQ12  
D_DQ13 / DDR_DQ13  
D_DQ14 / DDR_DQ14  
D_DQ15 / DDR_DQ15  
447.57  
449.41  
394.02  
366.03  
449.58  
470.40  
413.35  
384.02  
368.37  
399.54  
374.55  
398.20  
396.30  
408.81  
371.03  
388.23  
468.21  
371.60  
410.19  
536.32  
569.24  
545.35  
633.70  
604.01  
608.22  
479.46  
555.12  
472.85  
475.30  
421.35  
419.04  
480.43  
489.89  
430.18  
431.50  
517.45  
463.84  
653.53  
DDR_DQ16  
D_DQ17 /  
DDR_DQ17  
D_DQ18 /  
DDR_DQ18  
D_DQ19 /  
DDR_DQ19  
D_DQ20 /  
DDR_DQ20  
D_DQ21 /  
DDR_DQ21  
D_DQ22 /  
DDR_DQ22  
D_DQ23 /  
DDR_DQ23  
D_DQ24 /  
DDR_DQ24  
Data  
D_DQ25 /  
DDR_DQ25  
D_DQ26 /  
DDR_DQ26  
D_DQ27 /  
DDR_DQ27  
D_DQ28 /  
DDR_DQ28  
D_DQ29 /  
DDR_DQ29  
D_DQ30 /  
DDR_DQ30  
D_DQ31 /  
DDR_DQ31  
D_DQS0 /  
DDR_DQS0  
D_DQS2 /  
DDR_DQS2  
D_DQS1 /  
DDR_DQS1  
D_DQS3 /  
DDR_DQS3  
D_DQS4 /  
DDR_DQS4  
D_DM0 / DDR_DM0  
D_DM1 / DDR_DM1  
D_DM2 / DDR_DM2  
D_CKE0 / DDR_CKE0  
482.30  
553.44  
385.61  
D_DM3 / DDR_DM3  
D_DM4 / DDR_DM4  
D_CKE1 / DDR_CKE1  
536.80  
428.52  
384.34  
Control  
D_CS_N0 /  
DDR_CS_N0  
D_CS_N1 /  
DDR_CS_N1  
385.35  
421.27  
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Table 33.  
Signal Package Lengths (Sheet 3 of 3)  
Group  
Signal Name  
Length (mil)  
Signal Name  
Length (mil)  
D_MA0 / DDR_MA0  
D_MA1 / DDR_MA1  
D_MA2 / DDR_MA2  
515.78  
357.69  
509.12  
D_MA7 / DDR_MA7  
D_MA8 / DDR_MA8  
D_MA9 / DDR_MA9  
438.95  
394.65  
429.78  
D_MA10 /  
D_MA3 / DDR_MA3  
D_MA4 / DDR_MA4  
D_MA5 / DDR_MA5  
462.16  
444.71  
576.87  
378.96  
418.37  
392.79  
DDR_MA10  
D_MA11 /  
DDR_MA11  
D_MA12 /  
DDR_MA12  
Command  
D_MA13 /  
D_MA6 / DDR_MA6  
D_BA0 / DDR_BA0  
513.40  
530.35  
506.35  
433.55  
535.27  
477.26  
DDR_MA13  
D_BA1 / DDR_BA1  
D_RAS_N /  
DDR_RAS_N  
D_CAS_N /  
DDR_CAS_N  
D_WE_N /  
DDR_WE_N  
513.09  
7.3.3  
Routing Guidelines  
Clock Group  
7.3.3.1  
The clock signal group includes the differential clock pairs D_CK[2:0] / DDR_CK[2:0]  
and D_CK_N[2:0] / DDR_CK_N[2:0].  
Here are some tips on how to route the differential clock pairs:  
• Ensure that DDR clocks are routed on a single internal layers, except for pin  
escapes  
• A ground plane must be adjacent to the layer where the signals are routed  
• Minimize the number of vias used, but ensure that the same number of vias are  
used in the positive and negative trace  
• It is recommended that pin escape vias be located directly adjacent to the ball pads  
on all clocks  
Traces must be routed for differential mode impedance of 120 Ω  
• Surface layer routing should be minimized (top or bottom layers)  
• It is recommended to perform pre- and post-layout simulation  
A series resistance value in the 25- to 50-Ω range should be used as it adds minimal  
propagation delay to the signal without adversely varying from the CLK plus DQ  
propagation delay average. The appropriate value for termination resistance should be  
verified through simulation for the specific topology.  
Table 34 provides routing guidelines for signals within this group.  
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Figure 32.  
DDRII Clock Simulation Results: CK Signals  
Table 34.  
Clock Signal Group Routing Guidelines  
Parameter  
Definition  
Signal Group Members  
Topology  
D_CK[2:0] and D_CK_N[2:0]  
Differential Pair Point to Point (1 Driver, 4 Receivers)  
Single Ended Trace Impedance (Z )  
o
50 Ω  
Series Resistor  
33 Ω  
1
Nominal Trace Width  
Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils  
2
Nominal Pair Spacing (edge to edge)  
Minimum Pair to Pair Spacing  
Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils  
Any layer 20mils  
Minimum Spacing to Other DDR Signals  
Minimum Spacing to non-DDR Signals  
Maximum Via Count  
20.0 mils  
25.0 mils  
5 per trace  
Total Trace Length  
500 mils to 1000 mils  
DDR_CK to DDR_CK_N Length Matching  
Notes:  
Match total length to +/- 10 mils between clocks  
1.  
Nominal trace width is determined by board physical characteristics and stack-up. This value should  
be verified with the PWB manufacturer to achieve the desired Zo.  
2.  
Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value  
should be verified with the PWB manufacturer to achieve the desired Zdiff.  
7.3.3.2  
Data and Control Groups  
The data and control signal group includes D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] /  
DDR_DQ[31:0], D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0]/DDR_DM[4:0]., D_CS[1:0]/  
DDR_CS[1:0] and D_CKE[1:0]/DDR_CKE[1:0]. The groups should be routed on  
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internal layers, except for pin escapes. It is recommended that pin escape vias be  
located directly adjacent to the ball pads on all signals. Surface layer routing should be  
minimized. The following table provides routing guidelines for signals within these  
groups.  
Figure 33.  
DDRII Data and Control Simulation Results: DQ and DQS signals  
DQ  
22 ohm  
DQS  
Table 35.  
DDRII Data and Control Signal Group Routing Guidelines  
Parameter  
Definition  
D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] / DDR_DQ[31:0],  
D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0]/DDR_DM[4:0].,  
D_CS[1:0]/DDR_CS[1:0] and D_CKE[1:0]/DDR_CKE[1:0]  
Signal Group Members  
Topology  
Differential Pair Point to Point (1 Driver, 2 Receivers)  
Single Ended Trace Impedance (Z )  
o
50 Ω  
Series Resistor  
22 Ω  
1
Nominal Trace Width  
Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils  
Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils  
Any layer 20mils  
2
Nominal Pair Spacing (edge to edge)  
Minimum Pair to Pair Spacing  
Notes:  
1.  
Nominal trace width is determined by board physical characteristics and stack-up. This value should  
be verified with the PWB manufacturer to achieve the desired Zo.  
2.  
Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value  
should be verified with the PWB manufacturer to achieve the desired Zdiff.  
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Table 35.  
DDRII Data and Control Signal Group Routing Guidelines  
Parameter  
Definition  
Minimum Spacing to Other DDR Signals  
Minimum Spacing to non-DDR Signals  
Maximum Via Count  
20.0 mils  
25.0 mils  
5 per trace  
Total Trace Length  
1000 mils to 2000 mils  
Notes:  
1.  
Nominal trace width is determined by board physical characteristics and stack-up. This value should  
be verified with the PWB manufacturer to achieve the desired Zo.  
Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value  
should be verified with the PWB manufacturer to achieve the desired Zdiff.  
2.  
7.3.3.3  
Command Groups  
The command signal groups include all signals D_MA[13:0]/DDR_MA[13:0],  
D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS, D_CAS/DDR_CAS and D_WE/DDR_WE.  
The groups should be routed on internal layers, except for pin escapes. It is  
recommended that pin escape vias be located directly adjacent to the ball pads on all  
signals. Surface layer routing should be minimized. The following table provides routing  
guidelines for signals within these groups.  
Figure 34.  
DDRII Command Simulation Results: ADDRESS signals  
20ohm  
Table 36.  
DDRII Command Signal Group Routing Guidelines  
Parameter  
Signal Group Members  
Definition  
D_MA[13:0]/DDR_MA[13:0], D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS,  
D_CAS/DDR_CAS and D_WE/DDR_WE.  
Topology  
Point to Point (1 Driver, 10Receivers)  
Single Ended Trace Impedance (Z )  
o
50 Ω  
Notes:  
1.  
Nominal trace width is determined by board physical characteristics and stack-up. This value should  
be verified with the PWB manufacturer to achieve the desired Zo.  
Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value  
should be verified with the PWB manufacturer to achieve the desired Zdiff.  
2.  
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Table 36.  
DDRII Command Signal Group Routing Guidelines  
Parameter  
Definition  
Series Resistor  
20 Ω  
1
Nominal Trace Width  
Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils  
2
Nominal Pair Spacing (edge to edge)  
Minimum Pair to Pair Spacing  
Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils  
Any layer 20mils  
20.0 mils  
Minimum Spacing to Other DDR Signals  
Minimum Spacing to non-DDR Signals  
Maximum Via Count  
25.0 mils  
5 per trace  
Total Trace Length  
1500 mils to 2500 mils  
Notes:  
1.  
Nominal trace width is determined by board physical characteristics and stack-up. This value should  
be verified with the PWB manufacturer to achieve the desired Zo.  
2.  
Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value  
should be verified with the PWB manufacturer to achieve the desired Zdiff.  
§ §  
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