Intel Computer Hardware Demo Board with FPGA for SS SMII Fiber to MII Conversion User Manual

LXD9785 PQFP Demo Board with  
FPGA for SS-SMII (Fiber)-to-MII  
Conversion  
Development Kit Manual  
January 2002  
Order Number: 249323-003  
Contents  
Contents  
Figures  
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Development Kit Manual  
iii  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
Contents  
Tables  
iv  
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
Contents  
Revision History  
Date  
Revision  
Page  
Description  
All  
Replaced LXT9785 with LXT9785/9785E globally  
January 2002  
003  
Added new section 4.5 Expended Temperature Operation with the  
LXT9785HE.  
Replaced LXD9785 demo board graphic with A2 version.  
Quick Start Jumper Settings table: Added JP15 and JP16.  
Quick Start Switch Settings table:  
- Removed TxSLEW (S5-1:2)  
- Renumbered remaining switches  
- Replaced MDIX with Section and new configuration.  
- Removed Auto-Negotiation, 10/under Switch S8.  
- Changed Setting for S8-6 / CFG_1 from 1to 0.  
March 2001  
002  
Global Configuration Settings (S5) table:  
- Removed TxSLEW (S5-1:2); renumbered remaining switches.  
Global Configuration Settings (S8) table:  
- Replaced MDIX with Section and new configuration  
- Removed Auto-Negotiation, 10/from table.  
Replaced A1 schematics with A2.  
Bill of Materials (edits throughout for A2 version).  
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion Development Kit Manual  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
1.0  
General Description  
The LXD9785 PQFP MII Demo Board is an eight-port 100 Mbps Fast Ethernet Media Access Unit  
(MAU) that provides a working platform for evaluation of the LXT9785/9785E Fast Ethernet  
Octal Transceiver. All eight network ports provide a fiber interface for a 100BASE-FX connection.  
The Demo Board allows system designers to test 100 Mbps Fiber link performance and register  
functionality using a standard MII interface prior to board prototyping. Two FPGAs convert the  
eight fiber (SS-SMII) interfaces on the LXT9785/9785E to eight standard MII interfaces. This  
conversion simplifies evaluation of the LXT9785/9785E, rendering it compatible with existing MII  
test equipment.  
The Demo Board requires three external power supply inputs supplied by 2.5V and 3.3V power  
supplies.  
1.1  
Features  
Eight independent IEEE 802.3-compliant 100BASE-FX ports.  
Quick setup, ease of use, and clear visibility of application settings for:  
Complete system demonstration.  
Individual circuit isolation.  
JTAG boundary scan.  
Two LED options for major functions:  
Configuration LEDs which can be controlled through register 20 (refer to the LXT9785/  
9785E Datasheet).  
Inter Frame Status LED output controlled by FPGAs.  
Configurable via MDIO port or hardware jumpers.  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 1. LXD9785 PQFP MII Demo Board  
Port 0 MII  
Header  
Port 1 MII  
Header  
Port 2 MII  
Header  
Port 3 MII  
Header  
Port 4 MII  
Header  
Port 5 MII  
Header  
Port 6 MII  
Header  
Port 7 MII  
Header  
FPGA  
FPGA  
SS-SMII to MII Converter and  
SS-SMII to MII Converter and  
Inter Frame Status Output Connector  
Inter Frame Status Output Connector  
RJ-11  
Config Logic  
Switches & Jumpers  
Inter Frame  
Status LEDs  
LXT9785/9785E  
REFCLK Clocks  
and Clock Distribution  
Direct Drive  
LEDs  
+2.5V &  
+3.3V Power  
Supply  
Port 0 Fiber  
Header  
Port 1 Fiber  
Header  
Port 2 Fiber  
Header  
Port 3 Fiber  
Header  
Port 4 Fiber  
Header  
Port 5 Fiber  
Header  
Port 6 Fiber  
Header  
Port 7 Fiber  
Header  
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Development Kit Manual  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
2.0  
Introduction  
2.1  
Overview  
This document describes typical hardware set-up procedures for the LXD9785 PQFP MII Demo  
Board. To begin immediate operation, a Quick-Start Checkliston page 12 supports 100BASE-  
FX operation.  
Hardware switches and jumpers allow the designer access to all hardware configuration options.  
Each option is outlined in the Optional Configurationson page 14.  
The Demo Board provides two sets of LED indicators: Direct Drive LEDs and Inter Frame Status  
per-port LEDs. The Direct Drive LEDs can be used to display speed, transmit and receive  
activities, collision condition, link status, duplex mode, and isolate condition. The Inter Frame  
Status LEDs can be used to display full-duplex or half-duplex, 10 Mbps or 100 Mbps, or link.  
Board schematics and a Bill of Materials are located in the back of the document.  
2.2  
Equipment Requirements  
The LXD9785 Demo Board is populated with all of the IC components needed for twisted-pair  
evaluation. However, the following additional equipment is also required:  
SmartBits Advanced Multi-port Performance Test Box  
PC with Smart Windows (version 6.51 or newer) installed.  
A 3.3V DC Power Supply.  
A 2.5V DC Power Supply.  
Eight MII Cables (male-to-male).  
Eight external NIC cards.  
Eight fiber cables.  
2.3  
Fiber Register Configuration  
For a register setup via MDIO, proceed with the configuration of the device by setting Register Bit  
16.0 to 1 for all ports (see Table 5).  
Development Kit Manual  
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Document #: 249323  
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Rev. Date: January 24, 2002  
       
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
2.4  
Typical Setup  
Figure 2 shows a typical test setup for standard operation of the LXD9785/9785E PQFP MII Demo  
Board. The Demo Board plugs into a SmartBits Advanced Multi-port Performance Test Box via  
eight standard 40-pin MII cables (not included on the board). Eight external NIC cards directly  
connect to the SmartBits test box and plug into the Demo Board through fiber-module connectors.  
Each ports operation speed is set globally via hardware or individually via the MDIO for  
evaluation of 100 Mbps capabilities using all eight ports.  
Figure 2. Typical Test Setup  
Computer Setup  
SmartBits  
Smart  
Windows  
Advanced Multi-port  
Performance  
Tester  
RS-232  
External  
NIC  
Cards  
MII Cable  
Fiber  
Demo Board  
MII  
Connectors  
+2.5V/  
LEDs  
LXT9785  
/9785E  
+3.3V DC  
Power  
Fiber-Module  
Connectors  
Supply  
10  
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Document #: 249323  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 3. LXD9785/9785E SS-SMII Fiber Demo Board  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
3.0  
Quick-Start Checklist  
Use this quick-start procedure for easy setup of the LXD9785 PQFP MII Demo Board. This  
procedure sets all ports to the default condition (100 Mbps and full-duplex capabilities).  
1. Set the jumpers in accordance with Table 1.  
2. Set switches S1, S5, and S8 in accordance with Table 2.  
3. Connect the eight Demo Board MII ports to the SmartBits test box via MII connector/cables.  
Male-to- male connectors are required to interface the SmartBits test box to the LXD9785  
PQFP MII Demo Board and are available from Newark (.5m cable - Newark P/N 91F9746).  
4. Connect the fiber ports to external NIC cards via fiber cables. Each NIC card plugs directly  
into the SmartBits test box.  
5. Connect +2.5V DC power to VCC and a +3.3V DC power supply to VCCIO and VCC-EXT.  
6. With the Demo Board appropriately configured, apply power to the LXD9785 PQFP MII  
Demo Board and press Reset switch S4.  
7. Proceed with evaluation as desired.  
Table 1. Quick-Start Jumper Settings  
Jumper / Label  
Setting  
Configuration  
Jumper Pins  
2 & 3  
JP1 / MDIO  
JP2 / MDC  
Routes MDIO through Port 0 MII Connector.  
Jumper Pins  
2 & 3  
Routes MDC through Port 0 MII Connector.  
JP12 / SD Interface  
JP13  
Open  
Enables 3.3V SD Fiber interface.  
Jumpered  
Provides voltage to Fiber transceivers.  
Jumper Pins  
2 & 3  
JP15  
JP16  
Enables 1x8 mode.  
Enables 2x4 mode.  
Jumper Pins  
1 & 2  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Table 2. Quick-Start Switch Settings  
Switch / Label  
Setting  
Configuration  
Switch S1  
S1-1 / ADD_0  
0
S1-2 / ADD_1  
S1-3 / ADD_2  
S1-4 / ADD_3  
S1-5 / ADD_4  
0
0
0
0
Sets PHY MDIO base address to 00000.  
Switch S5  
S5-1 / PAUSE  
S5-2 / PWRDWN  
S5-3 / MDDIS  
0
0
0
Disables Pause function.  
Disables Power-Down function.  
Enables MDIO channel.  
Switch S8  
S8-1 / ModeSel 0  
S8-2 / ModeSel 1  
S8-3 /Section  
0
1
0
1
1
0
Switch settings for SS-SMII mode.  
Enables Section mode: 1x8 or 2x4.  
S8-4 / CFG_3  
S8-5 / CFG_2  
S8-6 / CFG_1  
Sets port configuration to 100 Mbps and Full-Duplex.  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
4.0  
Optional Configurations  
4.1  
Global Operating Configurations  
Switch S5 and S8 configure operating characteristics on all ports of the LXD9875 Demo Board.  
Each switch can be set manually by toggling the switch either to 1 or 0. Set switches S5 and S8 to  
the desired configuration according to Table 3 and Table 4 respectively.  
Table 3. Global Configuration Settings (Switch S5)  
Switch / Label  
Description  
Pause - Enable Pause capability on all ports.  
1 = Pause enabled.  
0 = Pause disabled.  
S5-1 / PAUSE_0  
S5-2 / PWRDWN  
S5-3 / MDDIS  
Power-Down - Enable global power-down mode.  
1 = Power-Down enabled on all ports.  
0 = Normal operation.  
Management Disable - Disables MDIO Access.  
1 = MDIO is disabled. (no read or write capability).  
0 = MDIO is read/write capable (normal operation).  
Global configuration settings for Switch S8 are displayed in Table 4.  
Table 4. Global Configuration Settings (Switch S8)  
Switch / Label  
Description  
S8-1 / ModeSel 0  
S8-2 / ModeSel 1  
S8-3 /Section  
ModeSel1  
1
ModeSel0  
0
Mode  
Settings for SS-SMII mode.  
SS-SMII  
Enables Section mode: 1x8 or 2x4.  
S8-4 / CFG_3  
S8-5 / CFG_2  
S8-6 / CFG_1  
Sets port configuration to 100 Mbps and Full-Duplex.  
4.2  
MII Address Configurations  
The ADDR <4:0> pins are used to configure the MII address by using the configuration settings for  
Switch S1, as seen in Table 5.  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Table 5. PHY Address Configuration Settings (Switch S1)  
Jumper / Label  
Description  
S1-1 / ADD_0  
S1-2 / ADD_1  
S1-3 / ADD_2  
S1-4 / ADD_3  
Address <4:0> - Sets base address. Each port adds its port number (starting with 0)  
to this address to determine its PHY address.  
Switch 0sets address bit to 0.  
Switch 1sets address bit to 10.  
Note: To make all ports accessible within the 0 - 31 PHY address range, DO NOT  
select a base address higher than 24.  
Port 0 = Base + 0  
Port 1 = Base + 1  
Port 2 = Base + 2  
Port 3 = Base + 3  
Port 4 = Base + 4  
Port 5 = Base + 5  
Port 6 = Base + 6  
Port 7 = Base + 7  
S1-5 / ADD_4  
4.3  
Alternate MDIO Routing Configuration  
The MDIO and MDC signals may be routed either through the 40-pin connector for MII Port 0 (the  
standard configuration) or through an RJ-11 connector (J2), as shown in Table 6. In either  
configuration, the MII registers can be accessed for each port by setting the correct PHY address.  
Refer to the LXT9785/9785E Data Sheet for specific register definitions and functions. The  
standard configuration is to route MDIO through the Port 0 MII connector to the SmartBits Test  
Box by setting the pins for JP1 and JP2 to 2 & 3.  
Note: MDIO sectionalization is not supported on this demo board.  
Table 6. MDIO Routing (Port 0)  
Desired Configuration Jumper  
Setting  
Description  
Jumper  
Pins 2 & 3  
JP2  
Routes MDC0 through Port 0 MII Connector.  
Route MDIO0 and MDC0  
through MII  
Jumper  
JP1  
Routes MDIO0 through Port 0 MII Connector.  
Routes MDC0 through RJ-11 Connector J2.  
Routes MDIO0 through RJ-11 Connector J2.  
Pins 2 & 3  
Jumper  
JP2  
Route MDIO0 and MDC0  
through RJ-11  
Pins 1 & 2  
Jumper  
JP1  
Pins 1 & 2  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
4.4  
JTAG Test Signals  
The boundary scan test port is accessed via JP3 for board- level testing. The JTAG test signal  
descriptions are shown in Table 7. The BSDL file for the LXT9785/9785E is available on the Intel  
Table 7. JTAG Test Signal Descriptions  
Jumper  
Pin#  
Symbol  
Description  
1
TRST#  
TCK  
Test Reset. Input sourced by ATE  
3
5
Test Clock. Input sourced by ATE.  
TMS  
TDO  
TDI  
Test Mode Select. Input sourced by ATE.  
Test Data Output. Output sourced by the PHY.  
Test Data Input. Input sourced by the ATE.  
Connected to system ground.  
JP3  
7
8
2,4,6  
GND  
JP11 is used for FPGA debug and is not designated for evaluation of the LXT9785/9785E  
device.  
JP11 / PLD0  
4.5  
Extended Temperature Operation with the LXT9785HE  
The LXT9785HE provides reliable Ethernet transceiver functionality from -40oC to +85oC. Any  
LXD9785 demo board supporting a QFP package can support an LXT9785HE mounted and  
localized extended temperature applied to the LXT9785HE. The LXD9785 demo board  
components are commercial temperature grade.  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
5.0  
LEDs  
5.1  
Direct Drive LEDs  
The LXD9785 PQFP MII Demo Board provides three programmable LED drivers per port (D4 -  
D28). Each LED can display one of several available status conditions as selected by the LED  
Configuration Register (Address 20) shown in Table 8.  
.
Table 8. Direct Drive LED Configuration Settings (Register 20)  
LED Bits  
Program  
Description  
Bits  
LED1  
LED2  
LED3  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Indicates 100 Mbps operation. (Default for LED1)  
Indicates transmit (Stretched).  
Indicates receive (stretched). (Default for LED3)  
Indicates collision (Stretched).  
Indicates active link (continuous). (Default for LED2)  
Indicates full-duplex.  
Reserved.  
Indicates transmit or receive activity.  
Test Mode. Turn LED on (continuous).  
Test Mode. Turn LED off (continuous).  
Test Mode. Blink LED fast (continuous).  
Test Mode. Blink LED slow (continuous).  
Indicates link and receive status combined1 (Stretched)2.  
Indicates link and activity status combined1 (Stretched)2.  
Indicates duplex and collision status combined3 (Stretched)2.  
Reserved.  
15:12  
11:8  
7:4  
1. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary  
LED driver (receive, activity, or isolate) causes the LED to change state (blink).  
2. Combined event LED settings are not affected by bit 20.1 (Pulse Stretch). These settings are stretched  
regardless of the value of 20.1.  
3. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex.  
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.  
The programmable LEDs (LED_1, LED_2, and LED_3) are set in the default mode and are  
programmable via the MDIO pin. Register address 20 also provides optional LED pulse stretching  
up to 100 ms. Register bits 20.3:2 select one of three possible stretch times as shown in Table 9 on  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Table 9. LED Pulse Stretch Settings (Register 20)  
Bit  
Name  
Description  
Type  
Default  
00 = Stretch LED events to 30 ms.  
01 = Stretch LED events to 60 ms.  
10 = Stretch LED events to 100 ms.  
11 = Reserved.  
20.3:2  
LEDFREQ  
R/W  
00  
PULSE-  
0 = Disable pulse stretching of all LEDs.  
1 = Enable pulse stretching of all LEDs.  
20.1  
R/W  
1
STRETCH  
5.2  
Inter Frame Status LEDs  
By using the conversion FPGAs, the Inter Frame Status information for Speed status, Duplex  
status, and Link status are output to an LED circuit. The LEDs (D101 - D154) provide a  
continuous, real-time status for all eight ports. This feature is provided to assist the customer in  
evaluation of the Inter Frame Status operation.  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
6.0  
Board Schematics  
Figure 4. LXD9785 PQFP MII Demo Board Power (Fiber Board Revision A2)  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 5. Control  
1
3
1
3
1
1
1
20  
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 6. MII Ports 0 and 1  
T P 3 6  
T P 3 5  
T P 3 4  
T P 3 3  
T P 3 2  
T P 3 1  
T P 3 0  
T P 4 4  
T P 4 3  
T P 4 2  
T P 4 1  
T P 4 0  
T P 3 9  
T P 3 8  
T P 3 7  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T P 2 0  
1
T P 2 8  
T P 2 7  
T P 2 6  
T P 2 5  
T P 2 4  
T P 2 3  
T P 2 2  
T P 2 1  
1
1
1
1
1
1
1
1
T P 1 9  
1
T P 1 8  
1
T P 1 7  
1
T P 1 6  
1
T P 1 5  
1
T P 2 9  
1
T P 1 4  
1
T P 1 3  
1
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 7. MII Ports 2 and 3  
T P 1 7 9  
1
T P 1 7 8  
T P 1 4 5  
T P 1 4 4  
T P 1 4 3  
T P 1 4 2  
T P 1 4 1  
T P 1 8 2  
T P 1 8 1  
T P 1 8 0  
1
1
1
1
1
1
1
1
T P 5 2  
T P 5 1  
T P 5 0  
T P 4 9  
T P 4 8  
T P 4 7  
T P 4 6  
T P 6 0  
T P 5 9  
T P 5 8  
T P 5 7  
T P 5 6  
T P 5 5  
T P 5 4  
T P 5 3  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T P 1 7 7  
T P 1 7 6  
1
1
T P 1 7 5  
T P 1 7 4  
T P 1 7 3  
1
1
1
T P 6 1  
1
T P 4 5  
1
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LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 8. MII Ports 4 and 5  
T P 1 6 8  
T P 1 6 7  
T P 1 0 8  
T P 1 0 7  
T P 1 0 6  
T P 1 0 5  
T P 1 0 4  
T P 1 7 1  
T P 1 7 0  
T P 1 6 9  
1
1
1
1
1
1
1
1
1
1
T P 1 6 6  
T P 1 6 5  
1
T P 1 5 3  
1
1
1
1
T P 1 6 1  
T P 1 5 2  
1
T P 1 6 4  
T P 1 6 3  
T P 1 6 2  
1
T P 1 6 0  
T P 1 5 1  
1
1
1
1
T P 1 5 9  
T P 1 5 0  
1
1
T P 1 5 8  
T P 1 4 9  
1
1
T P 1 5 7  
T P 1 4 8  
1
1
1
T P 1 7 2  
T P 1 5 6  
T P 1 4 7  
1
1
T P 1 5 5  
1
T P 1 5 4  
T P 1 4 6  
1
Development Kit Manual  
23  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 9. MII Ports 6 and 7  
T P 1 3 2  
1
T P 1 4 0  
T P 1 3 9  
T P 1 3 8  
T P 1 3 7  
T P 1 3 6  
T P 1 3 5  
T P 1 3 4  
T P 1 3 3  
1
1
1
1
1
1
1
1
T P 1 3 1  
T P 1 3 0  
T P 1 2 4  
T P 1 2 3  
T P 1 2 2  
T P 1 2 1  
T P 1 2 0  
T P 1 1 9  
T P 1 1 8  
T P 1 1 7  
1
1
1
1
1
1
1
1
1
1
T P 1 1 6  
T P 1 1 5  
1
1
T P 1 2 9  
T P 1 2 8  
1
T P 1 1 4  
T P 1 1 3  
1
1
T P 1 2 7  
T P 1 2 6  
1
1
T P 1 1 2  
T P 1 1 1  
T P 1 1 0  
1
1
1
T P 1 2 5  
1
1
T P 1 0 9  
1
24  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 10. Fiber Ports 0 and 1  
1
1
Development Kit Manual  
25  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 11. Fiber Ports 2 and 3  
1
1
26  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 12. Fiber Ports 4 and 5  
1
1
Development Kit Manual  
27  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 13. Fiber Ports 6 and 7  
1
1
28  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 14. Caps  
Development Kit Manual  
29  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 15. SS-SMII to MII ALTERA  
V C C _ C K L K  
G N D _ C K L K  
1 2 8  
1 2 5  
V C C I N T 9  
V C C I N T 8  
V C C I N T 7  
V C C I N T 6  
V C C I N T 5  
V C C I N T 4  
V C C I N T 3  
V C C I N T 2  
V C C I N T 1  
1 8 2  
1 5 6  
1 2 6  
1 0 5  
7 9  
5 2  
2 8  
2 3  
1
G N D I N T 8  
1 8 3  
G N D I N T 7  
1 4 3  
G N D I N T 6  
1 2 7  
G N D I N T 5  
1 1 8  
G N D I N T 4  
7 8  
G N D I N T 3  
3 9  
G N D I N T 2  
2 4  
G N D I N T 1  
1 6  
V C C I O 8  
V C C I O 7  
V C C I O 6  
V C C I O 5  
V C C I O 4  
V C C I O 3  
V C C I O 2  
V C C I O 1  
G N D I O 8  
1 9 9  
2 0 8  
1 8 9  
1 7 2  
1 3 6  
8 6  
8 0  
5 3  
8
G N D I O 7  
1 6 9  
G N D I O 6  
1 4 9  
G N D I O 5  
1 1 4  
G N D I O 4  
9 5  
G N D I O 3  
6 4  
G N D I O 2  
4 3  
G N D I O 1  
1 0  
V C C  
V C C  
8
7
G N D  
5
V C C _ C K L K  
G N D _ C K L K  
1 2 8  
1 2 5  
V C C I N T 9  
V C C I N T 8  
V C C I N T 7  
V C C I N T 6  
V C C I N T 5  
V C C I N T 4  
V C C I N T 3  
V C C I N T 2  
V C C I N T 1  
1 8 2  
1 5 6  
1 2 6  
1 0 5  
7 9  
5 2  
2 8  
2 3  
G N D I N T 8  
1 8 3  
G N D I N T 7  
1 4 3  
G N D I N T 6  
1 2 7  
G N D I N T 5  
1 1 8  
G N D I N T 4  
7 8  
G N D I N T 3  
3 9  
G N D I N T 2  
2 4  
G N D I N T 1  
1 6  
1
V C C I O 8  
V C C I O 7  
V C C I O 6  
V C C I O 5  
V C C I O 4  
V C C I O 3  
V C C I O 2  
V C C I O 1  
G N D I O 8  
1 9 9  
2 0 8  
1 8 9  
1 7 2  
1 3 6  
8 6  
8 0  
5 3  
8
G N D I O 7  
1 6 9  
G N D I O 6  
1 4 9  
G N D I O 5  
1 1 4  
G N D I O 4  
9 5  
G N D I O 3  
6 4  
G N D I O 2  
4 3  
G N D I O 1  
1 0  
V C C  
V C C  
8
7
G N D  
5
30  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 16. Clock Distribution  
1
1
1
1
1
1
1
1
1
1
V C C I N T  
V C C I N T  
V C C I O  
G N D I N T  
3 6  
4 1  
1 7  
2 9  
9
G N D I N T  
1 6  
G N D I O  
2 4  
V C C I O  
G N D I O  
4
Development Kit Manual  
31  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 17. Inter-Frame Status LEDs  
32  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 18. Logic Analyzer  
G N D  
G N D  
G N D  
G N D  
G N D  
4 3  
4 2  
4 1  
4 0  
3 9  
G N D  
G N D  
G N D  
G N D  
G N D  
4 3  
4 2  
4 1  
4 0  
3 9  
Development Kit Manual  
33  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 19. MDIO0 and MDC0 Fix  
V C C I N T  
V C C I N T  
V C C I O  
G N D I N T  
3 6  
4 1  
1 7  
2 9  
9
G N D I N T  
1 6  
G N D I O  
2 4  
V C C I O  
G N D I O  
4
34  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
 
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Figure 20. MDIO1 and MDC1 Fix  
V C C I N T  
V C C I N T  
V C C I O  
G N D I N T  
3 6  
4 1  
1 7  
2 9  
9
G N D I N T  
1 6  
G N D I O  
2 4  
V C C I O  
G N D I O  
4
Development Kit Manual  
35  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
   
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
7.0  
Bill of Materials  
Table 10. LXD9785 Bill of Materials (Fiber - SS-SMII)  
Reference Designator  
Description  
Manufacturer  
Part Number  
108-0740-001  
CONN BANANA  
NUT SILVER  
BN1-5  
EF JOHNSON  
C1-4, 8, 11, 136, 178, 270, 276, 282,  
288, 294, 300, 306, 312, 318  
CAP 10UF 20V  
TANT (CASEC)  
PANASONIC  
PANASONIC  
ECS-T1DC106R  
C5, 15, 19, 44-46, 56, 57, 58, 117, 122-  
124, 128, 140, 154, 156, 182, 225, 227,  
229, 231, 253, 255, 257, 259, 274, 277,  
279-281, 283, 285-287, 289, 291-293,  
295, 297-299, 301, 303-305, 307, 309-  
311, 313, 315-317, 319, 321-323, 347,  
349, 350, 362, (DO NOT INSTALL C262,  
264, 356, 358)  
CAP 0.1UF 16V  
CER X7R (0805)  
ECJ-2VB1C104K  
CAP 100UF 16V  
MIN ELECT (TH)  
C9, 12, 137, 179, 271  
PANASONIC  
PANASONIC  
PANASONIC  
ECE-A1CKA101  
ECS-T1EY105R  
ECU-V1H102JCX  
CAP 1.0UF 25V  
TANT (CASEA)  
C10, 13, 138, 180, 272  
CAP 0.001UF 50V  
5% CER (0805)  
C14, 16-18, 139, 141, 181, 273, 275  
C50-52, 62-64, 120, 121, 126, 127, 129,  
155, 157, 183, 224, 226, 228, 230, 252,  
254, 256, 258, 346, 348, 351 (DO NOT  
INSTALL C260, 261, 263, 266, 267, 352-  
355, 357)  
CAP 0.01UF 50V  
10% CER (0805)  
PANASONIC  
PANASONIC  
ECU-V1H103KBG  
ECS-T1VY224R  
CAP 0.22UF 35V  
TANT TE SERIES  
(CASEA)  
C75-78, 85-88, 184-187, 194-198, 204-  
207, 214-217, 232-235, 242-246  
C80-83, 90-93, 189-192, 199-203, 209-  
212, 219-222, 237-240, 247-251  
CAP .022UF 50V  
CER (0805) SMD  
PANASONIC  
AVX  
ECU-V1H223KBX  
TAJC226M010R  
LNJ208R8ARA  
LL4148  
CAP 22UF TANT  
(CASEC)  
C116, 125, 133  
D1, 93  
LED RED SS TYPE  
LOW CUR SMD  
PANASONIC  
DIODES, INC.  
DIODE, LL4148  
SMD ( )  
D2  
TVS GULLWING  
600W 5V UNI-DIR  
SMD  
GENERAL  
SEMICONDUCTOR  
D3, 4, 94, 157  
SMBG5.0A  
LED, GREEN SS  
TYPE LOW CUR  
SMD  
D5-28, 101-106, 117-122, 133-138, 149-  
156  
PANASONIC  
HP  
LNJ308G8LRA  
IC INTERFACE  
HFBR_5903 3.3V  
FIBER  
HFBR_5903 FIBER  
PORT  
F1-8 (DO NOT INSTALL)  
TRANSCEIVER ( )  
FBEAD REPL/  
CT50ACC-  
322513T  
CENTRAL  
TECHNOLOGY  
FB1, 5, 8 (DO NOT INSTALL FB10)  
CTCB1210-600-HC  
36  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
     
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Table 10. LXD9785 Bill of Materials (Fiber - SS-SMII) (Continued)  
Reference Designator  
FB2-4, 6, 11  
Description  
FERRITE BEAD  
Manufacturer  
FAIR-RITE  
Part Number  
2961666671  
CONN MOD JACK  
6-6 RJ11  
UNSHIELDED  
BLOCK  
J2, 3  
CORCOM  
RJ11-6L-B  
J4, 5 (DO NOT INSTALL)  
CONN SMA  
COAXIAL JACK  
AMPHENOL  
901-144  
JP1, 2, 4, 5, 15, 16  
JP3  
HEADER 3X1  
HEADER 4X2  
BERG  
BERG  
68000-240-3  
C9192-280-4  
HEADER 2X1 (2  
PIN)  
JP12, 19, 20 (DO NOT INSTALL JP10)  
JP14 (DO NOT INSTALL JP11, 21)  
L1-16  
BERG  
BERG  
68000-240-2  
C9192-280-5  
HEADER 5X2  
INDUCTOR 1UH  
SMD (1206)  
TDK#TDKMLF3216 TDKMLF3216A1R0K  
A1R0KT  
T000  
CONN MII 40 PIN  
FEMALE  
P1-8  
AMP  
787171-4  
RES 4.75K 1/10W  
1% (0805)  
POP 0805 4.75K  
OHM - 1%  
R3-10, 14-22, 24-26, 725, 726  
POPPY  
RES 100 OHM 1/  
10W 1% (0805)  
SMD  
R11  
PANASONIC  
ERJ-6ENF1000V  
RES 221 OHM 1/  
10W 1% (0805)  
SMD  
R12, 116-139, 491-496, 507-512, 523-  
528, 539-544  
POP 0805 221 OHM  
-1%  
POPPY  
RES 10K OHM 1/  
10W 1% (0805)  
SMD  
R23  
PANASONIC  
PANASONIC  
ERJ-6ENF1002V  
ERA-67EB102V  
RES 1K OHM 1/  
10W 1% (0805)  
SMD  
R27-29, 549-551, 564, 565, 733-736 (DO  
NOT INSTALL R577-580, 619-622)  
R207-415, 417, 419, 421, 423, 425, 427,  
429, 454-456, 460, 461, 562, 563, 567,  
586-609, 626-649, 654, 655, 663, 664,  
672, 673, 681, 682, 690, 691, 699, 700,  
708, 709, 717, 718, 731, 732 (DO NOT  
INSTALL R575, 576, 581, 582, 616-618,  
623)  
RES 49.9 OHM 1/  
10W 1% (0805)  
SMD  
POP 0805 49.9 OHM  
-1%  
POPPY  
RES 45.3 OHM 1/  
10W 1% (0805)  
SMD  
R416, 418, 420, 422, 424, 426, 428, 430,  
558, 559  
PANASONIC  
PANASONIC  
ERJ-6ENF45R3V  
ERJ-6ENF30R1V  
RES 30.1 OHM 1/  
10W 1% (0805)  
SMD  
R568, 569  
R574, 615, 727-730, 737, 738 (DONT  
INSTALL 573, 614)  
RES 0 OHM 1/10W  
5% (0805) SMD  
PANASONIC  
PANASONIC  
ERJ-6GEY0R00V  
ERJ-6ENF27R4V  
RES 27.4 OHM 1%  
1/10W (0805) SMD  
R650, 659, 668, 677, 686, 695, 704, 713  
Development Kit Manual  
37  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Table 10. LXD9785 Bill of Materials (Fiber - SS-SMII) (Continued)  
Reference Designator  
Description  
Manufacturer  
Part Number  
R651, 656, 657, 660, 665, 666, 669, 674, RES 130 OHM 1/  
675, 678, 683, 684, 687, 692, 693, 696,  
701, 702, 705, 710, 711, 714, 719, 720  
10W 1% (0805)  
SMD  
PANASONIC  
ERJ-6ENF1300V  
RES 82.5 OHM 1/  
10W 1% (0805)  
R658, 667, 676, 685, 694, 703, 712, 721  
PANASONIC  
ERJ-6ENF82R5V  
BD05  
SWITCH DIP 5  
POS TOP SLIDE  
C & K  
COMPONENTS  
S1  
S4  
S5  
SWITCH PB SPDT C & K  
TINY RT-ANGLE  
TP12SH8AQE  
BD04  
COMPONENTS  
SWITCH DIP 4  
POS TOP SLIDE  
C & K  
COMPONENTS  
SWITCH DIP 6  
POS TOP SLIDE  
C & K  
COMPONENTS  
S8  
BD06  
TP1, 2, 5, 13-61, 104-182, 184-223  
HEADER 1X1  
BERG  
68000-240-1  
TESTPOINT  
COLOR CODED  
BLACK  
TP62-71  
KEYSTONE  
5011  
IC PHY LXT9785/  
9785E 208 PIN  
QFP (QFP208)  
U1 (DO NOT INSTALL)  
SOCKET FOR U1  
INTEL PART  
YAMAICHI  
LXT9785/9785E  
SOCKET 208 PIN  
0.5MM PITCH SMT  
IC149-208-061-S5  
IC LOGIC 74HC14  
HEX INVERT  
TRIGGER 14 PIN  
SO  
U2  
FAIRCHILD  
MM74HC14M  
EPC1PC8  
IC MEM PROM  
EPC1 ALTERA 8  
PIN DIP (DIP8)  
U6, 33  
ALTERA  
MILL -- MAX  
MANUFACTURING 110-93-308-41-001  
CORP  
SOCKET 8 PIN DIP  
GOLD  
SOCKET FOR U6, 33  
U9, 10  
CONN 38 PIN  
MICTOR PLUG  
CONNECTOR ( )  
AMP  
2-767004-2  
MISC LATCH  
HOUSING FOR  
MICTOR RECPT  
PRECISION  
INTERCONNECT  
LATCH HOUSING FOR U9, 10  
105-1089-00  
IC LOGIC  
74LVC244 LOW  
VOLTAGE  
BUFFER 20 PIN  
SOIC  
TEXAS  
INSTRUMENTS  
U14-29  
SN74LVC244ADW  
IC FPGA 20K100  
U30, 31  
U32  
2.5V 208 PIN TQFP ALTERA  
( )  
EP20K100QC208-1  
SC1566CM-2.5  
REG SC1566 2.5V  
3A LOW  
DROPOUT 3 PIN  
SEMTECH  
TO-263  
38  
Development Kit Manual  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion  
Table 10. LXD9785 Bill of Materials (Fiber - SS-SMII) (Continued)  
Reference Designator  
Description  
Manufacturer  
Part Number  
IC LOGIC  
(DO NOT INSTALL U34, 35, 37, 40, 41,  
43)  
NC7SZ125  
SINGLE TRISTATE SEMICONDUCTOR  
BUFFER SOT23  
FAIRCHILD  
NC7SZ125M5  
IC FPGA 7032A  
3.3V  
U46 (DO NOT INSTALL U36, 42)  
Y1, 2 (DO NOT INSTALL)  
ALTERA  
EPM7032AETC44-4  
SCS-LO-1067  
PROGRAMMABLE  
PLD 44 PIN TQFP  
OSC 125.000MHZ  
SARONIX  
25PPM 3.3V  
Development Kit Manual  
39  
Document #: 249323  
Revision #: 003  
Rev. Date: January 24, 2002  

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