Fujitsu Computer Hardware F2MC 8FX User Manual
FUJITSU SEMICONDUCTOR  
CONTROLLER MANUAL  
CM26-00301-2E  
2
F MC-8FX  
8-BIT MICROCONTROLLER  
PROGRAMMING MANUAL  
2
F MC-8FX  
8-BIT MICROCONTROLLER  
PROGRAMMING MANUAL  
FUJITSU LIMITED  
PREFACE  
■ Purpose and Audience  
2
The F MC-8FX is original 8-bit one-chip microcontrollers that support application specific IC  
(ASIC). It can be widely applied from household to industrial equipment starting with portable  
equipment.  
2
This manual is intended for engineers who actually develop products using the F MC-8FX  
microcontrollers, especially for programmers who prepare programs using the assembly  
2
2
language for the F MC-8FX series assembler. It describes various instructions for the F MC-  
8FX.  
2
Note: F MC is the abbreviation of FUJITSU Flexible Microcontroller.  
■ Trademark  
The company names and brand names herein are the trademarks or registered trademarks of  
their respective owners.  
■ Organization of This Manual  
This manual consists of the following six chapters:  
2
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F MC-8FX CPU  
2
This chapter outlines the F MC-8FX CPU and explains its configuration by example.  
CHAPTER 2 MEMORY SPACE  
2
This chapter explains the F MC-8FX CPU memory space.  
CHAPTER 3 REGISTERS  
2
This chapter explains the F MC-8FX dedicated registers and general-purpose registers.  
CHAPTER 4 INTERRUPT PROCESSING  
2
This chapter explains the functions and operation of F MC-8FX interrupt processing.  
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
2
This chapter explains the instructions for the F MC-8FX CPU.  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
This chapter explains each execution instruction, used in the assembler, in reference format.  
APPENDIX  
The appendix contains instruction and bus operation lists and an instruction map.  
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•
•
The contents of this document are subject to change without notice.  
Customers are advised to consult with sales representatives before ordering.  
The information, such as descriptions of function and application circuit examples, in this document are presented solely for  
the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not  
warrant proper operation of the device with respect to use based on such information. When you develop equipment  
incorporating the device based on such information, you must assume any responsibility arising out of such use of the  
information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information.  
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license  
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any  
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using  
such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third  
parties which would result from the use of information contained herein.  
The products described in this document are designed, developed and manufactured as contemplated for general use, including  
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed  
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is  
secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or  
other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,  
medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e.,  
submersible repeater and artificial satellite).  
•
•
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection  
with above-mentioned uses of the products.  
•
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such  
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and  
prevention of over-current levels and other abnormal operating conditions.  
•
•
Exportation/release of any products described in this document may require necessary procedures in accordance with the  
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.  
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.  
Copyright© 2004-2008 FUJITSU LIMITED All rights reserved.  
ii  
CONTENTS  
2
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F MC-8FX CPU ........... 1  
2
1.1  
Outline of F MC-8FX CPU .................................................................................................................. 2  
2
1.2  
Configuration Example of Device Using F MC-8FX CPU .................................................................. 3  
CHAPTER 2 MEMORY SPACE ........................................................................................ 5  
2.1  
CPU Memory Space ........................................................................................................................... 6  
Memory Space and Addressing .......................................................................................................... 7  
Data Area ...................................................................................................................................... 9  
Program Area .............................................................................................................................. 11  
Arrangement of 16-bit Data in Memory Space ............................................................................ 13  
2.2  
2.2.1  
2.2.2  
2.2.3  
CHAPTER 3 REGISTERS ............................................................................................... 15  
2
3.1  
3.2  
3.3  
F MC-8FX Registers ........................................................................................................................ 16  
Program Counter (PC) and Stack Pointer (SP) ................................................................................ 17  
Accumulator (A) and Temporary Accumulator (T) ............................................................................ 18  
How To Use The Temporary Accumulator (T) ............................................................................. 20  
Byte Data Transfer and Operation of Accumulator (A) and Temporary Accumulator (T) ............ 21  
Program Status (PS) ......................................................................................................................... 23  
Index Register (IX) and Extra Pointer (EP) ....................................................................................... 26  
Register Banks ................................................................................................................................. 27  
Direct Banks ..................................................................................................................................... 28  
3.3.1  
3.3.2  
3.4  
3.5  
3.6  
3.7  
CHAPTER 4 INTERRUPT PROCESSING ...................................................................... 29  
4.1  
4.2  
4.3  
4.4  
4.5  
Outline of Interrupt Operation ........................................................................................................... 30  
Interrupt Enable/Disable and Interrupt Priority Functions ................................................................. 32  
Creating an Interrupt Processing Program ....................................................................................... 34  
Multiple Interrupt ............................................................................................................................... 36  
Reset Operation ................................................................................................................................ 37  
CHAPTER 5 CPU SOFTWARE ARCHITECTURE ......................................................... 39  
5.1  
Types of Addressing Modes ............................................................................................................. 40  
5.2  
Special Instructions ........................................................................................................................... 43  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS .......................... 47  
6.1  
ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator)  
48  
6.2  
6.3  
ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator) ............................ 50  
ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator)  
52  
6.4  
6.5  
6.6  
AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator) ...................... 54  
AND (AND Byte Data of Accumulator and Memory to Accumulator) ............................................... 56  
ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator) ................. 58  
iii  
6.7  
6.8  
6.9  
BBC (Branch if Bit is Clear) .............................................................................................................. 60  
BBS (Branch if Bit is Set) .................................................................................................................. 62  
BC (Branch relative if C=1)/BLO (Branch if LOwer) ......................................................................... 64  
6.10 BGE (Branch Great or Equal: relative if larger than or equal to Zero) .............................................. 66  
6.11 BLT (Branch Less Than zero: relative if < Zero) ............................................................................... 68  
6.12 BN (Branch relative if N = 1) ............................................................................................................. 70  
6.13 BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal) ................................................................ 72  
6.14 BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same) ...................................................... 74  
6.15 BP (Branch relative if N = 0: PLUS) .................................................................................................. 76  
6.16 BZ (Branch relative if Z = 1)/BEQ (Branch if Equal) ......................................................................... 78  
6.17 CALL (CALL subroutine) ................................................................................................................... 80  
6.18 CALLV (CALL Vectored subroutine) ................................................................................................. 82  
6.19 CLRB (Clear direct Memory Bit) ....................................................................................................... 84  
6.20 CLRC (Clear Carry flag) ................................................................................................................... 86  
6.21 CLRI (CLeaR Interrupt flag) .............................................................................................................. 88  
6.22 CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator) ....................................... 90  
6.23 CMP (CoMPare Byte Data of Accumulator and Memory) ................................................................ 92  
6.24 CMP (CoMPare Byte Data of Immediate Data and Memory) ........................................................... 94  
6.25 CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) .................................. 96  
6.26 DAA (Decimal Adjust for Addition) .................................................................................................... 98  
6.27 DAS (Decimal Adjust for Subtraction) ............................................................................................. 100  
6.28 DEC (DECrement Byte Data of General-purpose Register) ........................................................... 102  
6.29 DECW (DECrement Word Data of Accumulator) ........................................................................... 104  
6.30 DECW (DECrement Word Data of Extra Pointer) ........................................................................... 106  
6.31 DECW (DECrement Word Data of Index Pointer) .......................................................................... 108  
6.32 DECW (DECrement Word Data of Stack Pointer) .......................................................................... 110  
6.33 DIVU (DIVide Unsigned) ................................................................................................................. 112  
6.34 INC (INCrement Byte Data of General-purpose Register) .............................................................. 114  
6.35 INCW (INCrement Word Data of Accumulator) .............................................................................. 116  
6.36 INCW (INCrement Word Data of Extra Pointer) ............................................................................. 118  
6.37 INCW (INCrement Word Data of Index Register) ........................................................................... 120  
6.38 INCW (INCrement Word Data of Stack Pointer) ............................................................................. 122  
6.39 JMP (JuMP to address pointed by Accumulator) ............................................................................ 124  
6.40 JMP (JuMP to effective Address) ................................................................................................... 126  
6.41 MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator) ........ 128  
6.42 MOV (MOVE Byte Data from Memory to Accumulator) .................................................................. 130  
6.43 MOV (MOVE Immediate Byte Data to Memory) ............................................................................. 132  
6.44 MOV (MOVE Byte Data from Accumulator to memory) .................................................................. 134  
6.45 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator)  
136  
6.46 MOVW (MOVE Word Data from Memory to Accumulator) ............................................................. 138  
6.47 MOVW (MOVE Word Data from Extra Pointer to Accumulator) ..................................................... 140  
6.48 MOVW (MOVE Word Data from Index Register to Accumulator) ................................................... 142  
6.49 MOVW (MOVE Word Data from Program Status Register to Accumulator) .................................. 144  
6.50 MOVW (MOVE Word Data from Program Counter to Accumulator) .............................................. 146  
6.51 MOVW (MOVE Word Data from Stack Pointer to Accumulator) .................................................... 148  
6.52 MOVW (MOVE Word Data from Accumulator to Memory) ............................................................. 150  
6.53 MOVW (MOVE Word Data from Accumulator to Extra Pointer) ..................................................... 152  
iv  
6.54 MOVW (MOVE Immediate Word Data to Extra Pointer) ................................................................ 154  
6.55 MOVW (MOVE Word Data from Accumulator to Index Register) ................................................... 156  
6.56 MOVW (MOVE Immediate Word Data to Index Register) .............................................................. 158  
6.57 MOVW (MOVE Word data from Accumulator to Program Status Register) ................................... 160  
6.58 MOVW (MOVE Immediate Word Data to Stack Pointer) ................................................................ 162  
6.59 MOVW (MOVE Word data from Accumulator to Stack Pointer) ..................................................... 164  
6.60 MULU (MULtiply Unsigned) ............................................................................................................ 166  
6.61 NOP (NoOPeration) ........................................................................................................................ 168  
6.62 OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) ........................ 170  
6.63 OR (OR Byte Data of Accumulator and Memory to Accumulator) .................................................. 172  
6.64 ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator) .................... 174  
6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) .............................................. 176  
6.66 POPW (POP Word Data of Intherent Register from Stack Memory) .............................................. 178  
6.67 RET (RETurn from subroutine) ....................................................................................................... 180  
6.68 RETI (RETurn from Interrupt) ......................................................................................................... 182  
6.69 ROLC (Rotate Byte Data of Accumulator with Carry to Left) .......................................................... 184  
6.70 RORC (Rotate Byte Data of Accumulator with Carry to Right) ....................................................... 186  
6.71 SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulator)  
188  
6.72 SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator) .................. 190  
6.73 SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumulator)  
192  
6.74 SETB (Set Direct Memory Bit) ........................................................................................................ 194  
6.75 SETC (SET Carry flag) ................................................................................................................... 196  
6.76 SETI (SET Interrupt flag) ................................................................................................................ 198  
6.77 SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L") .................................................. 200  
6.78 XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L") ............................ 202  
6.79 XCHW (eXCHange Word Data Accumulator and Extrapointer) ..................................................... 204  
6.80 XCHW (eXCHange Word Data Accumulator and Index Register) ................................................. 206  
6.81 XCHW (eXCHange Word Data Accumulator and Program Counter) ............................................. 208  
6.82 XCHW (eXCHange Word Data Accumulator and Stack Pointer) ................................................... 210  
6.83 XCHW (eXCHange Word Data Accumulator and Temporary Accumulator) .................................. 212  
6.84 XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) ...... 214  
6.85 XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator) ............................... 216  
6.86 XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator)  
218  
APPENDIX ......................................................................................................................... 221  
APPENDIX A Instruction List ...................................................................................................................... 222  
2
A.1 F MC-8FX CPU Instruction Overview ............................................................................................ 223  
A.2 Operation List ................................................................................................................................. 226  
A.3 Flag Change Table ......................................................................................................................... 233  
APPENDIX B Bus Operation List ............................................................................................................... 240  
APPENDIX C Instruction Map .................................................................................................................... 251  
INDEX................................................................................................................................... 253  
v
vi  
Main changes in this edition  
Page  
Changes (For details, refer to main body.)  
11  
2.2.2 Program Area  
Table 2.2-2 CALLV Jump Address Table  
( " FFC8 " → " FFC9 " )  
H
H
53  
Execution example : ADDCW A  
( NZVC = "1010" → NZVC = "0000" )  
147  
Execution example : MOVW A, PC  
( A = "F0 63" → A = "F0 62" )  
( PC = "F0 63" → PC = "F0 62" )  
176  
6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory)  
( " Transfer the word value from the memory indicated by SP to dr. Then, subtract 2 fromthe value of SP. " →  
" Subtract 2 from the value of SP. Then, transfer the word value from the memory indicated by SP to dr. " )  
6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory)  
■ PUSHW (PUSH Word Data of Inherent Register to Stack Memory)  
( "((SP)) <-- (dr) (Word transfer) " → " (SP) ← (SP) - 2 (Word subtraction) " )  
( " (SP) <-- (SP) - 2 (Word subtraction) " → " ((SP)) ← (dr) (Word transfer) " )  
226  
232  
A.2 Operation List  
( "((iX)+off) <-- d8 " → " ((IX)+off) ← d8 " )  
Table A.2-4 Operation List (for Other Instructions)  
( "(SP) ← (SP)-2, ((SP)) ← (A)  
(A) ← ((SP)),  
(SP ) ← (SP)+2  
(SP) ← (SP)-2,  
((SP)) ← (IX)  
(IX) ← ((SP)),  
(SP) ← (SP)+2  
No operation  
(C) ← 0  
(C) ← 1  
(I) ← 0  
(I) ← 1 " ) is added.  
The vertical lines marked in the left side of the page show the changes.  
vii  
viii  
CHAPTER 1  
OUTLINE AND  
CONFIGURATION EXAMPLE  
2
OF F MC-8FX CPU  
2
This chapter outlines the F MC-8FX CPU and explains  
its configuration by example.  
2
1.1 Outline of F MC-8FX CPU  
2
1.2 Configuration Example of Device Using F MC-8FX CPU  
1
     
2
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F MC-8FX CPU  
2
1.1  
Outline of F MC-8FX CPU  
2
The F MC-8FX CPU is a high-performance 8-bit CPU designed for the embedded control  
of various industrial and OA equipment.  
2
■ Outline of F MC-8FX CPU  
2
The F MC-8FX CPU is a high-performance 8-bit CPU designed for the control of various industrial and  
OA equipment. It is especially intended for applications requiring low voltages and low power  
consumption. This 8-bit CPU can perform 16-bit data operations and transfer and is suitable for  
2
2
applications requiring 16-bit control data. The F MC-8FX CPU is upper compatibility CPU of the F MC-  
8L CPU, and the instruction cycle number is shortened, the division instruction is strengthened, and a direct  
area is enhanced.  
2
■ F MC-8FX CPU Features  
2
The F MC-8FX CPU features are as follows:  
•
•
•
Minimum instruction execution time: 100 ns  
Memory: 64 Kbytes  
Instruction configuration suitable for controller  
Data type: bit, byte, word  
Addressing modes: 9 types  
High code efficiency  
16-bit data operation: Operations between accumulator (A) and temporary accumulator (T)  
Bit instruction: set, reset, check  
Multiplication/division instruction: 8 × 8 = 16 bits, 16/16 = 16 bits  
Interrupt priorities : 4 levels  
•
2
     
2
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F MC-8FX CPU  
2
1.2  
Configuration Example of Device Using F MC-8FX CPU  
2
The CPU, ROM, RAM and various resources for each F MC-8FX device are designed in  
modules. The change in memory size and replacement of resources facilitate  
manufacturing of products for various applications.  
2
■ Configuration Example of Device Using F MC-8FX CPU  
2
Figure 1.2-1 shows a configuration example of a device using the F MC-8FX CPU.  
2
Figure 1.2-1 Configuration Example of Device Using F MC-8FX CPU  
Timer/counter  
A
T
IX  
PC  
EP  
SP  
Serial port  
A/D converter  
PWM  
Pins inherent  
to the product  
Common pins  
RP  
CCR  
ALU  
RAM  
F2MC-8FX CPU  
ROM  
Clock generator  
Interrupt controller  
F2MC-8FX Device  
3
     
2
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F MC-8FX CPU  
4
CHAPTER 2  
MEMORY SPACE  
2
This chapter explains the F MC-8FX CPU memory space.  
2.1 CPU Memory Space  
2.2 Memory Space and Addressing  
5
     
CHAPTER 2 MEMORY SPACE  
2.1  
CPU Memory Space  
2
All of the data, program, and I/O areas managed by the F MC-8FX CPU are assigned to  
2
the 64 Kbyte memory space of the F MC-8FX CPU. The CPU can access each resource  
by indicating its address on the 16-bit address bus.  
■ CPU Memory Space  
2
Figure 2.1-1 shows the address configuration of the F MC-8FX memory space.  
The I/O area is located close to the least significant address, and the data area is arranged right above it.  
The data area can be divided into the register bank, stack and direct areas for each application. In contrast  
to the I/O area, the program area is located close to the most significant address. The reset, interrupt reset  
vector and vector call instruction tables are arranged in the highest part.  
2
Figure 2.1-1 F MC-8FX Memory Space  
FFFFH  
Program area  
Data area  
I/O  
0000H  
6
     
CHAPTER 2 MEMORY SPACE  
2.2  
Memory Space and Addressing  
2
In addressing by the F MC-8FX CPU, the applicable addressing mode related to memory  
access may change according to the address.  
Therefore, the use of the proper addressing mode increases the code efficiency of  
instructions.  
■ Memory Space and Addressing  
2
The F MC-8FX CPU has the following addressing modes related to memory access. ([ ] indicates one  
byte):  
•
Direct addressing: Specify the lower 8 bits of the address using the operand. The accesses of operand  
address 00 to 7F are always 0000 to 007F . The accesses of operand address  
H
H
H
H
80 to FF are mapped to 0080 to 047F by setting of direct bank pointer (DP).  
H
H
H
H
[Structure] [← OP code →] [← lower 8 bits →] ([← if operand available →]  
Extended addressing:Specify all 16 bits using the operand.  
•
•
[Structure] [← OP code →] [← upper 8 bits →] [← lower 8 bits →]  
Bit direct addressing:Specify the lower 8 bits of the address using the operand. The accesses of operand  
address 00 to 7F are always 0000 to 007F . The accesses of operand address  
H
H
H
H
80 to FF are mapped to 0080 to 047F by setting of direct bank pointer (DP).  
H
H
H
H
The bit positions are included in the OP code.  
[Structure] [← OP code: bit →] [← lower 8 bits →]  
•
Indexed addressing: Add the 8 bits of the operand to the index register (IX) together with the sign and  
use the result as the address.  
[Structure] [← OP code →] [← 8 offset bits →] ([← if operand available →])  
Pointer addressing: Use the contents of the extra pointer (EP) directly as the address.  
[Structure] [← OP code →]  
•
•
General-purpose register addressing: Specify the general-purpose registers. The register numbers are  
included in the OP code.  
[Structure] [← OP code: register →]  
Immediate addressing:Use one byte following the OP code as data.  
[Structure] [← OP code →] [← Immediate data →]  
•
•
Vector addressing: Read the data from a table corresponding to the table number. The table numbers  
are included in the OP code.  
[Structure] [← OP code: table →]  
•
Relative addressing: Calculate the address relatively to the contents of the current PC. This addressing  
mode is used during the execution of the relative jump and bit check instructions.  
[Structure] [← OP code: table →] [← 8 bit relative value →]  
Figure 2.2-1 shows the memory space accessible by each addressing mode.  
7
   
CHAPTER 2 MEMORY SPACE  
Figure 2.2-1 Memory Space and Addressing  
Interrupt vector  
FFFFH  
FFD0H  
FFC0H  
CALLV table  
+127 bytes  
-128 bytes  
Program area  
External area  
047FH  
0200H  
Register bank  
I/O area  
0100H  
0000H  
: Direct addressing  
: Extended addressing  
: Bit direct addressing  
: Index addressing  
: Pointer addressing  
: General-purpose register addressing  
: Immediate addressing  
: Vector addressing  
: Relative addressing  
8
 
CHAPTER 2 MEMORY SPACE  
2.2.1  
Data Area  
2
The F MC-8FX CPU data area can be divided into the following three for each purpose:  
• General-purpose register bank area  
• Stack area  
• Direct area  
■ General-Purpose Register Bank Area  
2
The general-purpose register bank area in the F MC-8FX CPU is assigned to 0100 to 01FF . The general-  
H
H
purpose register numbers are converted to the actual addresses according to the conversion rule shown in  
Figure 2.2-2 by using the register bank pointer (RP) and the lower 3 bits of the OP code.  
Figure 2.2-2 Conversion Rule for Actual Addresses of General-purpose Register Bank Area  
Lower bits of OP code  
R4 R3 R2 R1 R0 b2 b1 b0  
RP  
"0"  
"0"  
"0"  
"0" "0"  
"1"  
"0"  
"0"  
Transaction address  
A15 A14 A13 A12A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
■ Stack Area  
2
The stack area in the F MC-8FX CPU is used as the saving area for return addresses and dedicated  
registers when the subroutine call instruction is executed and when an interrupt occurs. Before pushing data  
into the stack area, decrease the contents of the 16-bit stack pointer (SP) by 2 and then write the data to be  
saved to the address indicated by the SP. To pop data off the stack area, return data from the address  
indicated by the SP and then increase the contents of the SP by 2. This shows that the most recently pushed  
data in the stack is stored at the address indicated by the SP. Figure 2.2-3 and Figure 2.2-4 give examples of  
saving data in the stack area and returning data from it.  
9
       
CHAPTER 2 MEMORY SPACE  
Figure 2.2-3 Example of Saving Data in Stack Area  
Before execution  
MEMORY  
After execution MEMORY  
PUSHWA  
1235H  
1235H  
1234H  
1235H  
1234H  
SP  
67H  
SP  
A
67H  
1233H  
CDH  
ABH  
A
ABCDH  
ABCDH  
1233H  
1232H  
1233H  
1232H  
Figure 2.2-4 Example of Returning Data from Stack Area  
MEMORY  
After execution  
Before execution MEMORY  
POPW IX  
567BH  
567AH  
5679H  
SP  
IX  
SP  
IX  
567AH  
FEDCH  
5678H  
567BH  
567AH  
5679H  
XXXXH  
DCH  
FEH  
DCH  
FEH  
5678H  
5678H  
■ Direct Area  
2
The direct area in the F MC-8FX CPU is located at the lower side of the memory space or the 1152 bytes  
from 0000 to 047F and is mainly accessed by direct addressing and bit direct addressing. The area that  
H
H
can be used at a time by direct addressing and bit direct addressing is 256 bytes. 128 bytes of 0000 to  
H
007F can be used at any time as a direct area. 0080 to 047F is a direct bank of 128 bytes × 8 and can  
H
H
H
use one direct bank as a direct area by setting the direct bank pointer (DP). Conversion from the operand  
address of direct addressing and bit direct addressing to the real address is done by the conversion rule  
shown in Table 2.2-1 by using DP.  
Access to it is obtained by the 2-byte instruction.  
The I/O control registers and part of RAM that are frequently accessed are arranged in this direct area.  
Table 2.2-1 Conversion Rule for Actual Address of Direct Addressing and Bit Direct  
Addressing  
Operand address  
00 to 7F  
Direct bank pointer (DP)  
Actual address  
0000 to 007F  
H
H
H
H
H
H
H
H
H
H
H
H
0080 to 00FF  
000  
001  
010  
011  
100  
101  
110  
111  
H
0100 to 017F  
H
0180 to 01FF  
H
0200 to 027F  
H
80 to FF  
H
H
0280 to 02FF  
H
0300 to 037F  
H
0380 to 03FF  
H
0400 to 047F  
H
10  
       
CHAPTER 2 MEMORY SPACE  
2.2.2  
Program Area  
2
The program area in the F MC-8FX CPU includes the following two:  
• Vector call instruction table  
• Reset and interrupt vector table  
■ Vector Call Instruction Table  
FFC0 to FFCF of the memory space is used as the vector call instruction table. The vector call  
H
H
2
instruction for the F MC-8FX CPU provides access to this area according to the vector numbers included  
in the OP code and makes a subroutine call using the data written there as the jump address. Table 2.2-2  
indicates the correspondence of the vector numbers with the jump address table.  
Table 2.2-2 CALLV Jump Address Table  
CALLV  
#k  
Jump address table  
Upper address Lower address  
#0  
#1  
#2  
#3  
#4  
#5  
#6  
#7  
FFC0  
FFC2  
FFC4  
FFC6  
FFC8  
FFC1  
FFC3  
FFC5  
FFC7  
FFC9  
H
H
H
H
H
H
H
H
H
H
FFCA  
FFCB  
H
H
H
H
FFCC  
FFCE  
FFCD  
H
FFCF  
H
■ Reset and Interrupt Vector Table  
FFCC to FFFF of the memory space is used as the table indicating the starting address of an interrupt or  
H
H
reset Table 2.2-3 indicates the correspondence between the interrupt numbers or resets and the reference  
table.  
11  
       
CHAPTER 2 MEMORY SPACE  
Table 2.2-3 Reset and Interrupt Vector Table  
Interrupt No.  
Table address  
Upper data Lower data  
FFFE FFFF  
Interrupt No.  
Table address  
Upper data Lower data  
Reset  
#11  
#12  
#13  
#14  
#15  
#16  
#17  
#18  
#19  
#20  
#21  
#22  
#23  
FFE4  
FFE2  
FFE0  
FFE5  
FFE3  
FFE1  
H
H
H
H
H
H
H
H
FFFC  
FFFD  
H
H
H
H
#0  
#1  
#2  
#3  
#4  
#5  
#6  
#7  
#8  
#9  
#10  
FFFA  
FFFB  
FFF8  
FFF6  
FFF4  
FFF2  
FFF0  
FFF9  
FFF7  
FFF5  
FFF3  
FFF1  
FFDE  
FFDF  
H
H
H
H
FFDC  
FFDA  
FFDD  
H
H
H
H
H
H
H
H
H
H
H
FFDB  
H
FFD8  
FFD6  
FFD4  
FFD2  
FFD0  
FFD9  
FFD7  
FFD5  
FFD3  
FFD1  
FFCF  
H
H
H
H
H
H
H
H
H
H
H
FFFE  
FFFF  
H
H
FFEC  
FFFD  
H
H
H
FFEA  
FFFB  
FFF9  
H
FFE8  
FFE6  
FFCE  
H
H
H
FFE7  
FFCC  
FFCD  
H
H
H
H
FFFC : Reserved  
H
FFFD : Mode  
H
Note: The actual number varies according to the product.  
Use the interrupt number #22 and #23 exclusively for vector call instruction, CALLV #6 and  
CALLV #7  
12  
 
CHAPTER 2 MEMORY SPACE  
2.2.3  
Arrangement of 16-bit Data in Memory Space  
2
The F MC-8FX CPU can perform 16-bit data transfer and arithmetic operation though it  
is an 8-bit CPU. Arrangement of 16-bit data in the memory space is shown below.  
■ Arrangement of 16-bit Data in Memory Space  
2
As shown in Figure 2.2-5, the F MC-8FX CPU treats 16-bit data in the memory as upper data if it is  
written at the first location having a lower address and as lower data if it is written at the next location after  
that.  
Figure 2.2-5 Arrangement of 16-bit Data in Memory  
Before execution  
MEMORY  
After execution  
MEMORY  
MOVW ABCDH, A  
ABCFH  
ABCFH  
ABCEH  
ABCDH  
ABCCH  
ABCEH  
ABCDH  
ABCCH  
34H  
12H  
A
A
1234H  
1234H  
As when 16 bits are specified by the operand during the execution of an instruction, bytes are assumed to  
be upper and lower in the order of their proximity to the OP code. This applies when the operand indicates  
the memory address and 16-bit immediate data as shown in Figure 2.2-6.  
Figure 2.2-6 Arrangement of 16-bit Data during Instruction Execution  
[Example]  
:
.
MOV A, 5678H  
MOVWA, #1234H  
;
;
Extended address  
16-bit immediate data  
:
.
Assembled  
:
.
XXXXH  
XXXXH  
XXXXH  
XXXXH  
XX  
XX  
;
;
Extended address  
16-bit immediate data  
60 56 78  
E4 12 34  
XX  
:
.
The same may also apply to data saved in the stack by interrupts.  
13  
       
CHAPTER 2 MEMORY SPACE  
14  
CHAPTER 3  
REGISTERS  
2
This chapter explains the F MC-8FX dedicated registers  
and general-purpose registers.  
2
3.1 F MC-8FX Registers  
3.2 Program Counter (PC) and Stack Pointer (SP)  
3.3 Accumulator (A) and Temporary Accumulator (T)  
3.4 Program Status (PS)  
3.5 Index Register (IX) and Extra Pointer (EP)  
3.6 Register Banks  
3.7 Direct Banks  
15  
     
CHAPTER 3 REGISTERS  
2
3.1  
F MC-8FX Registers  
2
In the F MC-8FX series, there are two types of registers: dedicated registers in the CPU,  
and general-purpose registers in memory.  
2
■ F MC-8FX Dedicated Registers  
The dedicated register exists in the CPU as a dedicated hardware resource whose application is restricted to  
the CPU architecture.  
The dedicated register is composed of seven types of 16-bit registers. Some of these registers can be  
operated with only the lower 8 bits.  
Figure 3.1-1 shows the configuration of seven dedicated registers.  
Figure 3.1-1 Configuration of Dedicated Registers  
16 bits  
PC  
Initial value  
FFFDH  
Program counter: indicates the location of the stored instructions  
Accumulator: temporarily stores the result of operations and transfer  
Temporary accumulator: performs operations with the accumulator  
0000H  
A
0000H  
0000H  
T
IX  
EP  
Index register: indicates address indexes  
Extra pointer: indicates memory addresses  
0000H  
0000H  
Stack pointer: indicates the current location of the top of the stack  
SP  
RP DP CCR  
Program status: stores register bank pointers, direct bank pointer  
and condition codes  
CCR: IL1, 0 = 11  
PS  
Other flags = 0  
RP : 00000  
DP : 000  
2
■ F MC-8FX General-Purpose Registers  
The general-purpose register is as follows:  
•
Register bank: 8-bit length: stores data  
16  
       
CHAPTER 3 REGISTERS  
3.2  
Program Counter (PC) and Stack Pointer (SP)  
The program counter (PC) and stack pointer (SP) are application-specific registers  
existing in the CPU.  
The program counter (PC) indicates the address of the location at which the instruction  
currently being executed is stored.  
The stack pointer (SP) holds the addresses of the data location to be referenced by the  
interrupt and stack push/pop instructions. The value of the current stack pointer (SP)  
indicates the address at which the last data pushed onto the stack is stored.  
■ Program Counter (PC)  
Figure 3.2-1 shows the operation of the program counter (PC).  
Figure 3.2-1 Program Counter Operation  
After execution  
MEMORY  
MEMORY  
Before execution  
1235H  
PC  
1234H  
PC  
1235H  
1234H  
XXH  
00H  
00H  
1234H  
Instruction "NOP" executed  
■ Stack Pointer (SP)  
Figure 3.2-2 shows the operation of the stack pointer (SP).  
Figure 3.2-2 Stack Pointer Operation  
MEMORY  
5679H XXH  
MEMORY  
Before execution  
After execution  
1234H  
5679H  
A
XXH  
XXH  
1234H  
A
XXH  
32H  
5678H  
5677H  
5676H  
5678H  
5677H  
5676H  
5676H  
5678H  
SP  
SP  
12H  
PUSHW A  
17  
         
CHAPTER 3 REGISTERS  
3.3  
Accumulator (A) and Temporary Accumulator (T)  
The accumulator (A) and temporary accumulator (T) are application-specific registers  
existing in the CPU.  
The accumulator (A) is used as the area where the results of operations are temporarily  
stored.  
The temporary accumulator (T) is used as the area where the old data is temporarily  
saved for data transfer to the accumulator (A) or the operand for operations.  
■ Accumulator (A)  
For 16-bit operation all 16 bits are used as shown in Figure 3.3-1. For 8-bit operation only the lower 8 bits  
are used as shown in Figure 3.3-2.  
Figure 3.3-1 Accumulator (A) Operation (16-bit Operation)  
Before execution  
After execution  
A
A
T
68ADH  
5678H  
1234H  
T
5678H  
CF  
ADDCW A  
1
CF  
0
Figure 3.3-2 Accumulator (A) Operation (8-bit Operation)  
After execution  
12ADH  
Before execution  
1234H  
A
A
5678H  
T
5678H  
CF  
T
ADDC A  
CF  
1
0
■ Temporary Accumulator (T)  
When 16-bit data is transferred to the accumulator (A), all the old 16-bit data in the accumulator is  
transferred to the temporary accumulator (T) as shown in Figure 3.3-3. When 8-bit data is transferred to the  
accumulator, old 8-bit data stored in the lower 8 bits of the accumulator is transferred to the lower 8 bits of  
the temporary accumulator as shown in Figure 3.3-4. Although all 16-bits are used as the operand for 16-bit  
operations as shown in Figure 3.3-5, only the lower 8 bits are used for 8-bit operations as shown in Figure  
3.3-6.  
18  
         
CHAPTER 3 REGISTERS  
Figure 3.3-3 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (16-bit Transfer)  
Before execution  
After execution  
A
T
5678H  
A
1234H  
5678H  
XXXXH  
T
MOVW A, #1234H  
Figure 3.3-4 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (8-bit Transfer)  
After execution  
Before execution  
A
A
5678H  
5612H  
T
T
XXXXH  
XX78H  
MOV A, #12H  
Figure 3.3-5 Operations between Accumulator (A) and Temporary Accumulator (T) (16-bit Operations)  
1234H+5678H+1  
After execution  
Before execution  
+
A
A
T
1234H  
5678H  
CF  
68ADH  
T
5678H  
CF 0  
ADDCW A  
1
Figure 3.3-6 Operations between Accumulator (A) and Temporary Accumulator (T) (8-bit Operations)  
34H+78H+1  
After execution  
Before execution  
1234H  
A
T
+
A
12ADH  
5678H  
CF 0  
T
5678H  
CF 1  
ADDC A  
19  
       
CHAPTER 3 REGISTERS  
3.3.1  
How To Use The Temporary Accumulator (T)  
2
The F MC-8FX CPU has a special-purpose register called a temporary accumulator. This  
section described the operation of this register.  
■ How to Use the Temporary Accumulator (T)  
2
The F MC-8FX CPU has various binary operation instructions, some data transfer instructions and the  
temporary accumulator (T) for 16-bit data operation. Although there is no instruction for direct data  
transfer to the temporary accumulator, the value of the original accumulator is transferred to the temporary  
accumulator before executing the instruction for data transfer to the accumulator. Therefore, to perform  
operations between the accumulator and temporary accumulator, execute operations after carrying out the  
instruction for data transfer to the accumulator twice. Since data is not automatically transferred by all  
instructions to the temporary accumulator, see the columns of TL and TH in the instruction list for details  
of actual data transfer instructions. An example of addition with carry of 16-bit data stored at addresses  
1280 and 0042 is shown below.  
H
H
MOVW A, 0042H  
MOVW A, 1280H  
ADDCW A  
-
-
-
Figure 3.3-7 shows the operation for the accumulator and temporary accumulator when the above example  
is executed.  
Figure 3.3-7 Operation of Accumulator (A) and Temporary Accumulator (T) in Word Data Processing  
Before execution  
Last result  
68ACH  
1234H  
+
0
A
T
XXXXH  
A
T
A
T
5678H  
1234H  
RAM  
A
T
1234H  
XXXXH  
RAM  
CF  
XXXXH  
RAM  
RAM  
1281H  
1280H  
78H  
56H  
1281H 78H  
78H  
1281H 78H  
1281H  
1280H  
56H  
1280H 56H  
56H  
1280H  
0043H  
0042H  
34H  
12H  
34H  
0043H 34H  
34H  
12H  
0043H  
0042H  
0043H  
0042H 12H  
12H  
0042H  
20  
     
CHAPTER 3 REGISTERS  
3.3.2  
Byte Data Transfer and Operation of Accumulator (A)  
and Temporary Accumulator (T)  
When data transfer to the accumulator (A) is performed byte-by-byte, the transfer data  
is stored in the AL. Automatic data transfer to the temporary accumulator (T) is also  
performed byte-by-byte and only the contents of the original AL are stored in the TL.  
Neither the upper 8 bits of the accumulator nor the temporary accumulator are affected  
by the transfer. Only the lower 8 bits are used for byte operation between the  
accumulator and temporary accumulator. None of the upper 8 bits of the accumulator or  
temporary accumulator are affected by the operation.  
■ Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data  
Processing  
An example of addition with carry of 8-bit data stored at addresses 1280 and 0042 is shown below.  
H
H
MOV A, 0042H  
MOV A, 1280H  
ADDC A  
-
-
-
Figure 3.3-8 shows the operation of the accumulator and temporary accumulator when the above example  
is executed.  
Figure 3.3-8 Operation of Accumulator and Temporary Accumulator in Byte Data Processing  
Before execution  
Last result  
AB*246H  
+
A
A
T
A
T
A
T
ABEFH  
CDXXH  
AB56H  
CDEFH  
ABXXH  
*1  
T
CDXXH  
RAM  
CF 1  
CDEFH  
RAM  
RAM  
RAM  
1280H  
0042H  
56H  
1280H 56H  
0042H EFH  
1280H 56H  
0042H EFH  
1280H 56H  
0042H EFH  
EFH  
*1 The TH does not change when there is automatic data transfer to the temporary accumulator.  
*2 The AH is not changed by the result of the addition of the AL, TL, and CF.  
21  
     
CHAPTER 3 REGISTERS  
■ Direct Data Transfer from Temporary Accumulator (T)  
The temporary accumulator (T) is basically temporary storage for the accumulator (A). Therefore, data  
from the temporary accumulator cannot be transferred directly to memory. However, as an exception, using  
the accumulator as a pointer enabling saving of the contents of the temporary accumulator in memory. An  
example of this case is shown below.  
Figure 3.3-9 Direct Data Transfer from Temporary Accumulator (T)  
[Example]  
MOVW @A,  
T
Before execution  
After execution  
A
T
A
1234H  
CDEFH  
RAM  
1234H  
CDEFH  
RAM  
T
1235H  
1234H  
1235H XXH  
XXH  
EFH  
CDH  
1234H  
22  
 
CHAPTER 3 REGISTERS  
3.4  
Program Status (PS)  
The program status (PS) is a 16-bit application-specific register existing in the CPU.  
In upper byte of program status (PS), the upper 5-bit is the register bank pointer (RP)  
and lower 3-bit is the direct bank pointer (DP). The lower byte of program status (PS) is  
the condition code register (CCR). The upper byte of program status (PS), i.e. RP and  
DP, is mapped to address 0078 . So it is possible to make read and write accesses to  
H
them by an access to address 0078 .  
H
■ Structure of Program Status (PS)  
Figure 3.4-1 shows the structure of the program status.  
The register bank pointer (RP) indicates the address of the register bank currently in use. The relationship  
between the contents of the register bank pointer and actual addresses is as shown in Figure 3.4-2.  
DP shows the memory area (direct bank) used for direct addressing and bit direct addressing. Conversion  
from the operand address of direct addressing and bit direct addressing to the real address follows the  
conversion rule shown in Table 3.4-1 by using DP.  
The condition code register (CCR) has bits for indicating the result of operations and the content of transfer  
data and bits for controlling the operation of the CPU in the event of an interrupt.  
Figure 3.4-1 Structure of Program Status (PS)  
15 14 13 12 11 10  
RP  
9
8
7
6
I
5
4
3
2
1
0
PS  
DP  
H
IL0, 1  
N
Z
V
C
RP  
DP  
CCR  
Figure 3.4-2 Conversion Rule for Actual Address of General-purpose Register Area  
Lower bits of OP code  
R4 R3 R2 R1 R0 b2 b1 b0  
RP  
"0"  
"0"  
"0"  
"0" "0"  
"0"  
"1"  
"0"  
Transaction address  
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
23  
       
CHAPTER 3 REGISTERS  
Table 3.4-1 Conversion Rule for Actual Address of Direct Addressing and Bit  
Direct Addressing  
Operand address  
Direct bank pointer (DP)  
Actual address  
0000 to 007F  
00 to 7F  
H
H
H
H
0080 to 00FF  
000  
001  
010  
011  
100  
101  
110  
111  
H
H
H
H
H
H
H
H
H
0100 to 017F  
H
0180 to 01FF  
H
0200 to 027F  
H
80 to FF  
H
H
0280 to 02FF  
H
0300 to 037F  
H
0380 to 03FF  
H
0400 to 047F  
H
■ Program Status (PS) Flags  
The program status flags are explained below.  
•
H flag  
This flag is 1 if a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 is generated as the result of an  
operation, and it is 0 in other cases. Because it is used for decimal compensation instructions, it cannot  
be guaranteed if it is used for applications other than addition or subtraction.  
•
•
I flag  
An interrupt is enabled when this flag is 1 and is disabled when it is 0. It is set to 0 at reset which results  
in the interrupt disabled state.  
IL1, IL0  
These bits indicate the level of the currently-enabled interrupt. The interrupt is processed only when an  
interrupt request with a value less than that indicated by these bits is issued.  
IL1  
IL0  
Interrupt level  
High and low  
0
0
1
1
0
1
0
1
0
1
2
3
Highest  
Lowest  
•
•
•
N flag  
This flag is 1 when the most significant bit is 1 and is 0 when it is 0 as the result of an operation.  
Z flag  
This flag is 1 when the most significant bit is 0 and is 0 in other cases as the result of an operation.  
V flag  
24  
   
CHAPTER 3 REGISTERS  
This flag is 1 when a two’s complement overflow occurs and is 0 when one does not as the result of an  
operation.  
•
C flag  
This flag is 1 when a carry or a borrow, from bit 7 in byte mode and from bit 15 in word mode, is  
generated as the result of an operation but 0 in other cases. The shifted-out value is provided by the shift  
instruction.  
■ Access to Register Bank Pointer and Direct Bank Pointer  
The upper byte of program status (PS), i.e. register bank pointer (RP) and direct bank pointer (DP), is  
mapped to address 0078 . So it is possible to make read and write accesses to them by an access to address  
H
0078 , besides using instructions that have access to PS (MOVW A, PS or MOVW PS, A).  
H
25  
 
CHAPTER 3 REGISTERS  
3.5  
Index Register (IX) and Extra Pointer (EP)  
The index register (IX) and extra pointer (EP) are 16-bit application-specific registers  
existing in the CPU.  
The index register (IX) adds an 8-bit offset value with its sign to generate the address  
stored by the operand.  
The extra pointer (EP) indicates the address stored by the operand.  
■ Index Register (IX)  
Figure 3.5-1 indicates the operation of the index register.  
Figure 3.5-1 Operation of Index Register (IX)  
Before execution  
MEMORY  
After execution  
MEMORY  
34H  
56CFH  
56CEH  
56CFH  
56CEH  
A
1234H  
5678H  
XXXXH  
5678H  
A
34H  
12H  
IX  
IX  
56CDH 12H  
56CCH  
56CDH  
56CCH  
MOVW A, @IX+55H 5678H+0055H  
= 56CDH  
+
■ Extra Pointer (EP)  
Figure 3.5-2 shows the operation of the extra pointer.  
Figure 3.5-2 Operation of the Extra Pointer (EP)  
After execution  
MEMORY  
Before execution  
MEMORY  
5679H  
34H  
A
1234H  
5678H  
5679H  
5678H  
34H  
12H  
A
XXXXH  
5678H  
5678H  
12H  
EP  
EP  
5677H  
5676H  
5677H  
5676H  
MOVW A, @EP  
26  
         
CHAPTER 3 REGISTERS  
3.6  
Register Banks  
The register bank register is an 8-bit general-purpose register existing in memory.  
There are eight registers per bank of which there can be 32 altogether. The current bank  
is indicated by the register bank pointer (RP).  
■ Register Bank Register  
Figure 3.6-1 shows the configuration of the register bank.  
Figure 3.6-1 Configuration of Register Bank  
Address = 0100H + 8 * (RP)  
R0  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
Maximum of 32 banks  
Memory area  
27  
     
CHAPTER 3 REGISTERS  
3.7  
Direct Banks  
The direct bank is in 0080 to 047F of direct area, and composed of 128 bytes × 8  
H
H
banks. The access that uses direct addressing and bit direct addressing in operand  
address 80 to FF can be extended to 8 direct banks according to the value of the  
H
H
direct bank pointer (DP). The current bank is indicated by the direct bank pointer (DP).  
■ Direct Bank  
Figure 3.7-1 shows the configuration of a direct bank.  
The access that uses direct addressing and bit direct addressing in operand address 80 to FF can be  
H
H
extended to 8 direct banks according to the value of the direct bank pointer (DP). The access that uses  
direct addressing and bit direct addressing in operand address 00 to 7F is not affected by the value of the  
H
H
direct bank pointer (DP). This access is directed to fixed direct area 0000 to 007F .  
H
H
Figure 3.7-1 Configuration of Direct Bank  
Memory  
047FH  
0400H  
Direct bank 7  
(DP=111)  
Direct addressing  
and  
Operand address  
in bit direct addressing  
017FH  
0100H  
Direct bank 1  
(DP=001)  
Direct area  
FFH  
80H  
00FFH  
0080H  
Direct bank 0  
(DP=000)  
7FH  
00H  
007FH  
0000H  
Fixed direct area  
28  
     
CHAPTER 4  
INTERRUPT PROCESSING  
This chapter explains the functions and operation of  
2
F MC-8FX interrupt processing.  
4.1 Outline of Interrupt Operation  
4.2 Interrupt Enable/Disable and Interrupt Priority Functions  
4.3 Creating an Interrupt Processing Program  
4.4 Multiple Interrupt  
4.5 Reset Operation  
29  
     
CHAPTER 4 INTERRUPT PROCESSING  
4.1  
Outline of Interrupt Operation  
2
F MC-8FX series interrupts have the following features:  
• Four interrupt priority levels  
• All maskable features  
• Vector jump feature by which the program jumps to address mentioned in the  
interrupt vector.  
■ Outline of Interrupt Operation  
2
In the F MC-8FX series, interrupts are transferred and processed according to the following procedure:  
1. An interrupt source occurs in resources.  
2. Refer to interrupt enable bits in resources. If an interrupt is enabled, interrupt requests are issued from  
resources to the interrupt controller.  
3. As soon as an interrupt request is received, the interrupt controller decides the priorities of the interrupt  
requested and then transfers the interrupt level corresponding to the interrupts applicable to the CPU.  
4. The CPU compares the interrupt levels requested by the interrupt controller with the IL bit in the  
program status register.  
5. In the comparison, the CPU checks the contents of the I flag in the same program status register only if  
the priority is higher than the current interrupt processing level.  
6. In the check in 5., the CPU sets the contents of the IL bit to the requested level only if the I flag is  
enabled for interrupts, processes interrupts as soon as the instruction currently being executed is  
completed and then transfers control to the interrupt processing routine.  
7. The CPU clears the interrupt source caused in 1. using software in the user’s interrupt processing  
routine to terminate the processing of interrupts.  
30  
   
CHAPTER 4 INTERRUPT PROCESSING  
2
Figure 4.1-1 shows the flow diagram of F MC-8FX interrupt operation.  
2
Figure 4.1-1 Outline of F MC-8FX Interrupt Operation  
F2MC-8FX CPU  
I
IL  
6
4
Check  
Comparator  
5
3
Peripheral  
Interrupt request  
enable bit  
AND  
2
Interrupt request  
flag  
7
1
Peripheral  
Interrupt  
controller  
31  
 
CHAPTER 4 INTERRUPT PROCESSING  
4.2  
Interrupt Enable/Disable and Interrupt Priority Functions  
2
In the F MC-8FX series, interrupt requests are transferred to the CPU using the three  
types of enable/disable functions listed below.  
• Request enable check by interrupt enable flags in resources  
• Checking the level using the interrupt level determination function  
• Interrupt start check by the I flag in the CPU  
Interrupts generated in resources are transferred to the CPU with the priority levels  
determined by the interrupt priority function.  
■ Interrupt Enable/Disable Functions  
•
Request enable check by interrupt enable flags in resources  
This is a function to enable/disable a request at the interrupt source. If interrupt enable flags in resources  
are enabled, interrupt request signals are sent from resources to the interrupt controller. This function is  
used for controlling the presence or absence of an interrupt, resource-by-resource. It is very useful  
because when software is described for each resource operation, interrupts in another resource do not  
need to be checked for whether they are enabled or disabled.  
•
•
Checking the level using the interrupt level determination function  
This function determines the interrupt level. The interrupt levels corresponding to interrupts generated  
in resources are compared with the IL bit in the CPU. If the value is less than the IL bit, a decision is  
made to issue an interrupt request. This function is able to assign priorities if there are two or more  
interrupts.  
Interrupt start check by the I flag in the CPU  
The I flag enables or disables the entire interrupt. If an interrupt request is issued and the I flag in the  
CPU is set to interrupt enable, the CPU temporarily suspends the flow of instruction execution to  
process interrupts. This function is able to temporarily disable the entire interrupt.  
■ Interrupt Requests in Resources  
As shown in Figure 4.2-1, interrupts generated in resources are converted by the corresponding interrupt  
level registers in the interrupt controller into the values set by software and then transferred to the CPU.  
The interrupt level is defined as high if its numerical value is lower, and low if it is higher.  
32  
     
CHAPTER 4 INTERRUPT PROCESSING  
Figure 4.2-1 Relationship between Interrupt Request and Interrupt Level in Resources  
Interrupt level register  
To CPU  
Resource #1  
1H  
2H  
Interrupt  
request F/F  
Resource #2  
0H  
3H  
Resource #n  
Interrupt controller  
33  
 
CHAPTER 4 INTERRUPT PROCESSING  
4.3  
Creating an Interrupt Processing Program  
2
In the F MC-8FX series, basically, interrupt requests from resources are issued by  
hardware and cleared by software.  
■ Creating an Interrupt Processing Program  
The interrupt processing control flow is as follows:  
1. Initialize resources before operation.  
2. Wait until an interrupt occurs.  
3. In the event of an interrupt, if the interrupt can be accepted, perform interrupt processing to branch to  
the interrupt processing routine.  
4. First, set software so as to clear the interrupt source at the beginning of the interrupt processing routine.  
This is done so that the resource causing an interrupt can regenerate the interrupt during the interrupt  
processing program.  
5. Next, perform interrupt processing to transfer the necessary data.  
6. Use the interrupt release instruction to release the interrupt from interrupt processing.  
7. Then, continue to execute the main program until an interrupt recurs. The typical interrupt processing  
flow is shown in Figure 4.3-1.  
The numbers in the figure correspond to the numbers above.  
Figure 4.3-1 Interrupt Processing Flow  
Interrupt processing program  
Set he interrupt level  
to the IL bit.  
Main program  
Clear the interrupt source: To accept a multiple interrupts  
Initialize the  
from the same resource.  
→
resource.  
Prevent multiple  
Set the interrupt request from  
the resource in hardware and  
issue an interrupt request.  
interrupts of the  
same level.  
Interrupt processing program: Transfer the actual  
processing data.  
Release the interrupt from the interrupt processing.  
The time to transfer control to the interrupt processing routine after the occurrence of an interrupt 3 in  
Figure 4.3-1) is 9 instruction cycles. An interrupt can only be processed in the last cycle of each instruction.  
The time shown in Figure 4.3-2 is required to transfer control to the interrupt processing routine after an  
interrupt occurs.  
The longest cycle (17 + 9 = 26 instruction cycles) is required when an interrupt request is issued  
immediately after starting the execution of the DIVU instruction.  
34  
     
CHAPTER 4 INTERRUPT PROCESSING  
Figure 4.3-2 Interrupt Response Time  
Normal  
instruction execution  
Interrupt  
handling  
Interrupt processing program  
CPU operation  
Interrupt wait time  
9 instruction  
cycles (b)  
Sample wait (a)  
Indicates the last instruction cycle  
in which an interrupt is sampled.  
Interrupt request issued  
Note: It will take (a) + (b) instruction cycles to transfer control to  
the interrupt processing routine after an interrupt occurs.  
35  
 
CHAPTER 4 INTERRUPT PROCESSING  
4.4  
Multiple Interrupt  
2
The F MC-8FX CPU can have a maximum of four levels as maskable interrupts. These  
can be used to assign priorities to interrupts from resources.  
■ Multiple Interrupt  
A specific example is given below.  
•
When giving priority over the A/D converter to the timer interrupt  
START  
MOV  
MOV  
ADIL,  
TMIL,  
#2  
#1  
Set the interrupt level of the A/D converter to 2.  
Set the interrupt level of the timer to 1. ADIL and  
TMIL are IL bits in the interrupt controller.  
CALL  
CALL  
STAD  
STTM  
Start the A/D converter.  
Start the timer.  
.
.
.
When the above program is started, interrupts are generated from the A/D converter and timer after an  
elapsed time. In this case, when the timer interrupt occurs while processing the A/D converter interrupt, it  
will be processed through the sequence shown in Figure 4.4-1.  
Figure 4.4-1 Example of Multiple Interrupt  
Main program  
ı
A/D converter interrupt processing Process the timer interrupt.  
IL=2  
IL=1  
Initialize the resource.  
Timer interrupt  
occurs.  
The A/D converter  
interrupt occurs.  
Process the timer interrupt.  
Release the timer interrupt.  
Suspended  
Resumed  
Process the A/D  
ı
converter interrupt.  
The main program  
is resumed.  
Release the timer interrupt.  
When starting processing of an A/D converter interrupt, the IL bit in the PS register of the CPU is  
automatically the same as the value of request (2 here). Therefore, when a level 1 or 0 interrupt request is  
issued during the processing of an A/D converter interrupt, the processing proceeds without disabling the  
A/D converter interrupt request. When temporarily disabling interrupts lower in priority than this interrupt  
during A/D converter interrupt processing, disable the I flag in the PS register of the CPU for the interrupts  
or set the IL bit to 0.  
When control is returned to the interrupted routine by the release instruction after completion of each  
interrupt processing routine, the PS register is set to the value saved in the stack. Consequently, the IL bit  
takes on the value before interruption.  
For actual coding, refer to the Hardware Manual for each device to check the addresses of the interrupt  
controller and each resource and the interrupts to be supported.  
36  
     
CHAPTER 4 INTERRUPT PROCESSING  
4.5  
Reset Operation  
2
In the F MC-8FX series, when a reset occurs, the flag of program status is 0 and the IL  
bit is set to 11. When cleared, the reset operation is executed from the starting address  
written to set vectors (FFFE , FFFF ).  
H
H
■ Reset Operation  
A reset affects:  
•
•
•
Accumulator, temporary accumulator: Initializes to 0000  
H
Stack pointer: Initializes to 0000  
H
Extra pointer, index register: Initializes to 0000  
H
•
•
•
•
•
Program status: Sets flag to 0, sets IL bit to 11, sets RP bit to 00000 and Initializes DP bit to 000  
Program counter: Reset vector values  
RAM (including general-purpose registers): Keeps value before reset  
Resources: Basically stop  
Others: Refer to the manual for each product for the condition of each pin  
Refer to the manual for each product for details of the value and operation of each register for special reset  
conditions.  
37  
   
CHAPTER 4 INTERRUPT PROCESSING  
38  
CHAPTER 5  
CPU SOFTWARE  
ARCHITECTURE  
2
This chapter explains the instructions for the F MC-8FX  
CPU.  
5.1 Types of Addressing Modes  
5.2 Special Instructions  
39  
     
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
5.1  
Types of Addressing Modes  
2
The F MC-8FX CPU has the following ten addressing modes:  
• Direct addressing (dir)  
• Extended addressing (ext)  
• Bit direct addressing (dir:b)  
• Indexed addressing (@IX+off)  
• Pointer addressing (@EP)  
• General-purpose register addressing (Ri)  
• Immediate addressing (#imm)  
• Vector addressing (#k)  
• Relative addressing (rel)  
• Inherent addressing  
■ Direct Addressing (dir)  
This addressing mode, indicated as "dir" in the instruction list, is used to access the direct area from 0000  
H
to 047F . In this addressing, when the operand address is 00 to 7F , it accesses 0000 to 007F .  
H
H
H
H
H
Moreover, when the operand address is 80 to FF , the access is good to 0080 to 047F at the mapping  
H
H
H
H
by direct bank pointer DP setting.  
[Example]  
MOV 92H,A  
DP  
001B  
0112H  
A
45H  
45H  
■ Extended Addressing (ext)  
This addressing mode, indicated as "ext" in the instruction list, is used to access the entire 64-Kbyte area. In  
this addressing mode, the upper byte is specified by the first operand and the lower byte by the second  
operand.  
■ Bit Direct Addressing (dir:b)  
This addressing mode, indicated as "dir:b" in the instruction list, is used for bit-by-bit access of the direct  
area from 0000 to 047F . In this addressing, when the operand address is 00 to 7F , it accesses 0000  
H
H
H
H
H
to 007F . Moreover, when the operand address is 80 to FF , the access is good to 0080 to 047F at the  
H
H
H
H
H
mapping by direct bank pointer DP setting. The position of the bit in the specified address is specified by  
the value for the instruction code of three subordinate position bits.  
[Example]  
7 6 5 4 3 2 1 0  
SETB 34H: 2  
X X X X X 1 X X  
B
0034H  
XXXB  
DP  
40  
       
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
■ Index Addressing (@IX+off)  
This addressing mode, indicated as "@IX+off" in the instruction list, is used to access the entire 64-Kbyte  
area. In this addressing mode, the contents of the first operand are sign-extended and then added to the  
index register (IX). The result is used as the address.  
MOVW A, @IX+5AH  
[Example]  
2800H  
+
27A5H  
IX  
34H  
A
1234H  
12H  
27FFH  
■ Pointer Addressing (@EP)  
This addressing mode, indicated as "@EP" in the instruction list, is used to access the entire 64-Kbyte area.  
In this addressing mode, the contents of the extra pointer (EP) are used as the address.  
[Example]  
MOVW A, @EP  
27A5H  
27A6H 34H  
12H  
A
1234H  
EP  
27A5H  
■ General-Purpose Register Addressing (Ri)  
This addressing mode, indicated as "Ri" in the instruction list, is used to access the register bank area. In  
this addressing mode, one upper byte of the address is set to 01 and one lower byte is created from the  
contents of the register bank pointer (RP) and the 3 lower bits of the instruction to access this address.  
[Example]  
MOV A, R2  
01010B  
0152H  
A
ABH  
RP  
ABH  
■ Immediate Addressing (#imm)  
This addressing mode, indicated as "#imm" in the instruction list, is used for acquiring the immediate data.  
In this addressing mode, the operand is used directly as the immediate data. The byte or word is specified  
by the instruction code.  
[Example]  
MOV A, #56H  
A
56H  
41  
       
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
■ Vector Addressing (#k)  
This addressing mode, indicated as "#k" in the instruction list, is used for branching to the subroutine  
address registered in the table. In this addressing mode, the information about #k is contained in the  
instruction code and the table addresses listed in Table 5.1-1 are created.  
Table 5.1-1 Jump Address Table  
#k  
0
Address table (upper jump address: lower jump address)  
FFC0 :FFC1  
H
H
H
H
H
H
1
FFC2 :FFC3  
H
2
FFC4 :FFC5  
H
3
FFC6 :FFC7  
H
4
FFC8 :FFC9  
H
5
FFCA :FFCB  
H
H
H
H
6
FFCC :FFCD  
H
7
FFCE :FFCF  
H
[Example]  
CALLV #5  
(Conversion)  
FEH  
DCH  
FFCAH  
FFCBH  
PC  
FEDCH  
■ Relative Addressing (rel)  
This addressing mode, indicated as "rel" in the instruction list, is used for branching to the 128-byte area  
across the program counter (PC). In this addressing mode, the contents of the operand are added with their  
sign, to the program counter. The result is stored in the program counter.  
[Example]  
BNE +FEH  
9ABCH + FFFEH  
{
9ABCH  
New PC  
9ABAH  
Old PC  
In this example, the program jumps to the address where the instruction code BNE is stored, resulting in an  
infinite loop.  
■ Inherent Addressing  
This addressing mode, which has no operand in the instruction list, is used for operations to be determined  
by the instruction code. In this addressing mode, the operation varies for every instruction.  
[Example]  
NOP  
9ABCH  
New PC  
9ABDH  
Old PC  
42  
       
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
5.2  
Special Instructions  
2
In the F MC-8FX series, the following six special instructions are available:  
• JMP @A  
• MOVW A, PC  
• MULU A  
• DIVU A  
• XCHW A, PC  
• CALLV #k  
■ JMP @A  
This instruction is used for branching to an address where the contents of the accumulator (A) are used. The  
contents of one of the N jump addresses arranged in table form is selected and transferred to the  
accumulator. Executing this instruction enables the N-branch processing.  
[Example]  
JMP @A  
After execution  
Before execution  
1234H  
A
1234H  
1234H  
Old PC  
New PC  
XXXXH  
■ MOVW A, PC  
This instruction is used for performing the opposite operation to JMP @A. In other words, it stores, the  
contents of the program counter (PC) in the accumulator (A). When this instruction is executed in the main  
routine and a specific subroutine is to be called, make sure that the contents of the accumulator are the  
specified value in the subroutine, that is the branch is from the expected section, enabling a decision on  
crash.  
[Example]  
MOVW A, PC  
After execution  
1234H  
Before execution  
A
A
XXXXH  
1234H  
Old PC  
New PC  
1234H  
When this instruction is executed, the contents of the accumulator are the same as those of the address  
where the code for the next instruction is stored and not the address where the code for this instruction is  
stored. The above example shows that the value 1234 stored in the accumulator agrees with that of the  
H
address where the instruction code next to MOVW A, PC is stored.  
43  
     
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
■ MULU A  
This instruction is used for multiplying 8 bits of the AL by 8 bits of the TL without a sign and stores the 16-  
bit result in the accumulator (A). The contents of the temporary accumulator (T) do not change. In the  
operation, the original contents of the AH and TH are not used. Since the flag does not change, attention  
must be paid to the result of multiplication when branching accordingly.  
[Example]  
MULU A, T  
After execution  
1860H  
Before execution  
A
T
5678H  
1234H  
A
T
1234H  
■ DIVU A  
This instruction is used for dividing 16 bits of the temporary accumulator (T) by 16 bits of the A without a  
sign and stores the results as 16 bits in the A and the remainder as 16 bits in the T. When A is 0000 , Z flag  
H
is 1 as 0 division. At this time, the operation result is not guaranteed.  
[Example]  
DIVU A  
After execution  
Before execution  
A
T
A
1234H  
5678H  
0004H  
0DA8H  
T
■ XCHW A, PC  
This instruction is used for exchanging the contents of the accumulator (A) for those of the program  
counter (PC). As a result, the program branches to the address indicated by the contents of the original  
accumulator and the contents of the current accumulator become the value of the address next to the one  
where the instruction code XCHW A, PC is stored. This instruction is provided especially for specifying  
tables using the main routine and for subroutines to use them.  
[Example]  
XCHW A, PC  
After execution  
1235H  
Before execution  
5678H  
1234H  
A
A
PC  
PC  
5678H  
When this instruction is executed, the contents of the accumulator are the same as those of the address  
where the code for the next instruction is stored and not the address where the code for this instruction is  
stored. The above example shows that the value of the accumulator 1235 agrees with that of the address  
H
where the instruction code next to XCHW A, PC is stored. Consequently, 1235 not 1234 is indicated.  
H
H
44  
     
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
Figure 5.2-1 Example of Using XCHW A, PC  
[Main routine]  
[Subroutine]  
PUTSUB XCHW A, EP  
PUSHW A  
MOVW A, #PUTSUB  
XCHW A, PC  
PTS1  
MOV A, @EP  
INCW EP  
DB 'PUT OUT DATA', EOL  
MOVW A, #1234H  
...  
Output table data here.  
MOV IO, A  
CMP A, #EOL  
BNE PTS1  
POPW A  
XCHW A, EP  
JMP @A  
■ CALLV #k  
This instruction is used for branching to a subroutine address registered in the table. In this addressing  
mode, the information about #k is included in the instruction code and the tale addresses listed in Table 5.2-  
1 are created. After saving the contents of the current program counter (PC) in the stack, the program  
branches to the address in the table. Because it is a 1-byte instruction, using it for frequently-used  
subroutines reduces the size of the entire program.  
Table 5.2-1 Jump Address Table  
#k  
0
Address table (upper jump address : lower jump address)  
FFC0 :FFC1  
H
H
H
H
H
H
1
FFC2 :FFC3  
H
2
FFC4 :FFC5  
H
3
FFC6 :FFC7  
H
4
FFC8 :FFC9  
H
5
FFCA :FFCB  
H
H
H
H
6
FFCC :FFCD  
H
7
FFCE :FFCF  
H
45  
   
CHAPTER 5 CPU SOFTWARE ARCHITECTURE  
[Example]  
CALLV #3  
After execution  
Before execution  
FEDCH  
1232H  
PC  
SP  
PC  
SP  
5678H  
1234H  
(-  
)
2
FFC7H  
FFC6H  
1234H  
1234H  
DCH  
FEH  
DCH  
FEH  
1233H  
1232H  
XXH  
XXH  
1233H  
79H  
1232H 56H  
46  
CHAPTER 6  
DETAILED RULES  
FOR EXECUTION  
INSTRUCTIONS  
This chapter explains each execution instruction, used  
in the assembler, in reference format.  
All execution insurrections are described in alphabetical  
order.  
For information about the outline of each item and the meaning of  
symbols (abbreviations) explained for each execution instruction,  
see "CHAPTER 5 CPU SOFTWARE ARCHITECTURE".  
47  
     
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.1 ADDC (ADD Byte Data of Accumulator and Temporary  
Accumulator with Carry to Accumulator)  
Add the byte data of TL to that of AL, add a carry to the LSB and then return the results  
to AL. The contents of AH are not changed.  
■ ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to  
Accumulator)  
Operation  
(AL) ← (AL) + (TL) + (C) (Byte addition with carry)  
Assembler format  
ADDC A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 22  
48  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : ADDC A  
Memory FFFFH  
Memory FFFFH  
12  
56  
AC  
78  
12  
56  
34  
A
A
T
T
78  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
1
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
49  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.2 ADDC (ADD Byte Data of Accumulator and Memory with  
Carry to Accumulator)  
Add the byte data of EA memory (memory expressed in each type of addressing) to that  
of AL, add a carry to the LSB and then return the results to AL. The contents of AH are  
not changed.  
■ ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator)  
Operation  
(AL) ← (AL) + (EA) + (C) (Byte addition with carry)  
Assembler format  
ADDC A, EA  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Table 6.2-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
@EP  
Ri  
Number of execution  
cycles  
2
3
3
2
2
Byte count  
OP code  
2
2
2
1
1
24  
25  
26  
27  
28 to 2F  
50  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : ADDC A, #25H  
Memory FFFFH  
Memory FFFFH  
12  
5A  
12  
34  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
51  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.3 ADDCW (ADD Word Data of Accumulator and Temporary  
Accumulator with Carry to Accumulator)  
Add the word data of T to that of A, add a carry to the LSB and then return the results to  
A.  
■ ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to  
Accumulator)  
Operation  
(A) ← (A) + (T) + (C) (Word addition with carry)  
Assembler format  
ADDCW A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 23  
52  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : ADDCW A  
Memory FFFFH  
Memory FFFFH  
68  
AD  
12  
56  
34  
A
A
T
T
56  
78  
78  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
53  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.4 AND (AND Byte Data of Accumulator and Temporary  
Accumulator to Accumulator)  
Carry out the logical AND on the byte data of AL and TL for every bit and return the  
result to AL. The byte data of AH is not changed.  
■ AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator)  
Operation  
(AL) ← (AL) ^ (TL) (Byte AND)  
Assembler format  
AND A  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 62  
54  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : AND A  
Memory FFFFH  
Memory FFFFH  
12  
24  
12  
34  
A
A
T
T
XX  
2C  
XX  
2C  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
55  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.5 AND (AND Byte Data of Accumulator and Memory to  
Accumulator)  
Carry out the logical AND on the byte data of AL and EA memory (memory expressed in  
each type of addressing) for every bit and return the result to AL. The byte data of AH is  
not changed.  
■ AND (AND Byte Data of Accumulator and Memory to Accumulator)  
Operation  
(AL) ← (AL) ^ (EA) (Byte AND)  
Assembler format  
AND A, EA  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Table 6.5-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
@EP  
Ri  
Number of execution  
cycles  
2
3
3
2
2
Byte count  
OP code  
2
2
2
1
1
64  
65  
66  
67  
68 to 6F  
56  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : AND , @EP  
Memory FFFFH  
Memory FFFFH  
02  
11  
02  
53  
A
A
T
T
IX  
IX  
31  
0123H  
0000H  
31  
0123H  
0000H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
Byte  
01  
23  
01  
23  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
1
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
57  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.6 ANDW (AND Word Data of Accumulator and Temporary  
Accumulator to Accumulator)  
Carry out the logical AND on the word data of A and T for every bit and return the  
results to A.  
■ ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator)  
Operation  
(A) ← (A) ^ (T) (Word AND)  
Assembler format  
ANDW A  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 63  
58  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : ANDW A  
Memory FFFFH  
Memory FFFFH  
14  
34  
22  
32  
56  
34  
63  
A
A
T
T
32  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
59  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.7 BBC (Branch if Bit is Clear)  
Branch when the value of bit b in dir memory is 0. Branch address corresponds to the  
value of addition between the PC value (word value) of the next instruction and the  
value with rel code-extended (word value).  
■ BBC (Branch if Bit is Clear)  
Operation  
(bit)b = 0: (PC) ← (PC) + 3 + rel (Word addition)  
(bit)b = 1: (PC) ← (PC) + 3 (Word addition)  
Assembler format  
BBC dir:b, rel  
Condition code (CCR)  
N
-
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Set to 1 when the value of dir:b is 0 and set to 0 when it is 1.  
V: Not changed  
C: Not changed  
Number of execution cycles: 5  
Byte count: 3  
OP code: B0 to B7  
60  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BBC 84H : 0, 0FBH  
Memory FFFFH  
Memory FFFFH  
A
A
B0  
E800H  
E7FEH  
B0  
E800H  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
bit0  
XXXX XXX0 0084H  
bit0  
XXXX XXX0 0084H  
E8  
00  
E7  
FE  
Byte  
0000H  
Byte  
0000H  
N
0
Z
1
V
0
C
0
N
0
Z
0
V
0
C
0
00  
Byte  
00  
Byte  
(Before execution)  
(After execution)  
Byte  
Byte  
61  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.8 BBS (Branch if Bit is Set)  
Branch when the value of bit b in dir memory is 1. Branch address corresponds to the  
value of addition between the PC value (word value) of the next instruction and the  
value with rel code-extended (word value).  
■ BBS (Branch if Bit is Set)  
Operation  
(bit)b = 0: (PC) ← (PC) + 3 (Word addition)  
(bit)b = 1: (PC) ← (PC) + 3 + rel (Word addition)  
Assembler format  
BBS dir:b, rel  
Condition code (CCR)  
N
-
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Set to 1 when the value of dir:b is 0 and set to 0 when it is 1.  
V: Not changed  
C: Not changed  
Number of execution cycles: 5  
Byte count: 3  
OP code: B8 to BF  
62  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BBS 84H : 0, 0FBH  
Memory FFFFH  
Memory FFFFH  
A
A
B0  
E800H  
E7FEH  
B0  
E800H  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
bit0  
bit0  
0084H  
0000H  
0084H  
0000H  
XXXX XXX1  
XXXX XXX1  
E8  
00  
E7  
FE  
Byte  
Byte  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
00  
Byte  
00  
Byte  
(Before execution)  
(After execution)  
Byte  
Byte  
63  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.9 BC (Branch relative if C=1)/BLO (Branch if LOwer)  
Execute the next instruction if the C-flag is 0 and the branch if it is 1. Branch address  
corresponds to the value of addition between the PC value (word value) of the next  
instruction and the value with rel code-extended (word value).  
■ BC (Branch relative if C=1)/BLO (Branch if LOwer)  
Operation  
(C) = 0: (PC) ← (PC) + 2 (Word addition)  
(C) = 1: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BC rel/BLO rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: F9  
64  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BC 0FEH  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
E804H  
FE  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
FE  
F9  
F9  
F802H  
0000H  
E802H  
E8  
02  
E8  
04  
Byte  
Byte  
0000H  
N
1
Z
1
V
1
C
0
N
1
Z
1
V
1
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
65  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.10 BGE (Branch Great or Equal: relative if larger than or equal  
to Zero)  
Execute the next instruction if the logical exclusive-OR for the V and N flags is 1 and the  
branch if it is 0. Branch address corresponds to the value of addition between the PC  
value (word value) of the next instruction and the value with rel code-extended (word  
value).  
■ BGE (Branch Great or Equal: relative if larger than or equal to Zero)  
Operation  
(V) ∀ (N) = 1: (PC) ← (PC) + 2 (Word addition)  
(V) ∀ (N) = 0: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BGE rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: FE  
66  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BGE 02H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
F458H  
02  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
FE  
FE  
F456H  
0000H  
F456H  
F4  
56  
F4  
58  
Byte  
Byte  
0000H  
N
0
Z
1
V
1
C
1
N
0
Z
1
V
1
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
67  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.11 BLT (Branch Less Than zero: relative if < Zero)  
Execute the next instruction if the logical exclusive-OR for the V and N flags is 0 and the  
branch if it is 1. Branch address corresponds to the value of addition between the PC  
value (word value) of the next instruction and the value with rel code-extended (word  
value).  
■ BLT (Branch Less Than zero: relative if < Zero)  
Operation  
(V) ∀ (N) = 0: (PC) ← (PC) + 2 (Word addition)  
(V) ∀ (N) = 1: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BLT rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: FF  
68  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BLT 02H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
F45AH  
IX  
IX  
F458H  
F456H  
F458H  
02  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
FF  
FF  
F456H  
F4  
56  
F4  
5A  
Byte  
0000H  
Byte  
0000H  
N
0
Z
1
V
1
C
1
N
0
Z
1
V
1
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
69  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.12 BN (Branch relative if N = 1)  
Execute the next instruction if the N-flag is 0 and the branch if it is 1. Branch address  
corresponds to the value of addition between the PC value (word value) of the next  
instruction and the value with rel code-extended (word value).  
■ BN (Branch relative if N = 1)  
Operation  
N = 0: (PC) ← (PC) + 2 (Word addition)  
N = 1: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BN rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: FB  
70  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BN 02H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
FC63H  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
02  
FB  
FB  
FC5FH  
0000H  
FC5FH  
FC  
5F  
FC  
63  
Byte  
Byte  
0000H  
N
1
Z
1
V
1
C
0
N
1
Z
1
V
1
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
71  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.13 BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal)  
Execute the next instruction if the Z-flag is 1 and the branch if it is 0. Branch address  
corresponds to the value of addition between the PC value (word value) of the next  
instruction and the value with rel code-extended (word value).  
■ BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal)  
Operation  
(Z) = 1: (PC) ← (PC) + 2 (Word addition)  
(Z) = 0: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BNZ rel/BNE rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: FC  
72  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BNZ 0FAH  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
FE20H  
FA  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
FA  
FC  
FC  
FE1EH  
0000H  
FE1EH  
FE  
1E  
FE  
20  
Byte  
Byte  
0000H  
N
0
Z
1
V
0
C
0
N
0
Z
1
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
73  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.14 BNC (Branch relative if C = 0)/BHS (Branch if Higher or  
Same)  
Execute the next instruction if the C-flag is 1 and the branch if it is 0 . Branch address  
corresponds to the value of addition between the PC value (word value) of the next  
instruction and the value with rel code-extended (word value).  
■ BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same)  
Operation  
(C) = 1: (PC) ← (PC) + 2 (Word addition)  
(C) = 0: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BNC rel/BHS rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: F8  
74  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BNC 01H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
E805H  
E804H  
E804H  
01  
01  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
F8  
F8  
E802H  
E802H  
E8  
02  
E8  
05  
Byte  
0000H  
Byte  
0000H  
N
1
Z
1
V
1
C
0
N
1
Z
1
V
1
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
75  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.15 BP (Branch relative if N = 0: PLUS)  
Execute the next instruction if the N-flag is 1 and the branch if it is 0 . Branch address  
corresponds to the value of addition between the PC value (word value) of the next  
instruction and the value with rel code-extended (word value).  
■ BP (Branch relative if N = 0: PLUS)  
Operation  
(N) = 1: (PC) ← (PC) + 2 (Word addition)  
(N) = 1: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BP rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: FA  
76  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BP 04H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
FC61H  
04  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
04  
FA  
FA  
FC5FH  
0000H  
FC5FH  
FC  
5F  
FC  
61  
Byte  
Byte  
0000H  
N
1
Z
0
V
1
C
1
N
1
Z
0
V
1
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
77  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.16 BZ (Branch relative if Z = 1)/BEQ (Branch if Equal)  
Execute the next instruction if the Z-flag is 0 and the branch if it is 1 . Branch address  
corresponds to the value of addition between the PC value (word value) of the next  
instruction and the value with rel code-extended (word value).  
■ BZ (Branch relative if Z = 1)/BEQ (Branch if Equal)  
Operation  
(Z) = 0: (PC) ← (PC) + 2 (Word addition)  
(Z) = 1: (PC) ← (PC) + 2 + rel (Word addition)  
Assembler format  
BZ rel/BEQ rel  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4 (at divergence)/ 2 (at non-divergence)  
Byte count: 2  
OP code: FD  
78  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : BZ 0FAH  
Memory FFFFH  
Memory FFFFH  
A
A
FE20H  
FA  
T
T
FA  
FE1EH  
FD  
FE1EH  
FD  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
FE1AH  
FE  
1E  
FE  
1A  
Byte  
0000H  
Byte  
0000H  
N
0
Z
1
V
0
C
0
N
0
Z
1
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
79  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.17 CALL (CALL subroutine)  
Branch to address of ext. Return to the instruction next to this one by using the RET  
instruction of the branch subroutine.  
■ CALL (CALL subroutine)  
Operation  
(SP) ← (SP) - 2 (Word subtraction), ((SP)) ← (PC) (Word transfer)  
(PC) ← ext  
Assembler format  
CALL ext  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 6  
Byte count: 3  
OP code: 31  
80  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CALL 0FC00H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
020AH  
26  
020AH  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
F6  
OA  
23  
02  
08  
00  
F6  
0208H  
FC  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
81  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.18 CALLV (CALL Vectored subroutine)  
Branch to the vector address (VA) of vct. Return to the instruction next to this one by  
using the RET instruction of the branch subroutine. The vector address (VA) indicated  
by VCT is shown on the next page.  
■ CALLV (CALL Vectored subroutine)  
Operation  
(SP) ← (SP) - 2 (Word subtraction), ((SP)) ← (PC) (Word transfer)  
(PC) ← (VA)  
Assembler format  
CALLV #vct  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 7  
Byte count: 1  
OP code: E8 to EF  
82  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CALL #02H  
Memory FFFFH  
Memory FFFFH  
A
A
vct  
02  
FFC5H  
FFC4H  
00  
T
T
EC00H  
EC  
IX  
IX  
0208H  
01  
0208H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
E8  
08  
00  
02  
06  
E8  
0206H  
EC  
00  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
Table 6.18-1 Call Storage Address of Vector Call Instruction  
Vector address (VA)  
Instruction  
Lower address  
Upper address  
FFCF  
FFCE  
FFCC  
CALL#7  
CALL#6  
CALL#5  
CALL#4  
CALL#3  
CALL#2  
CALL#1  
CALL#0  
H
H
H
FFCD  
H
H
H
H
H
H
H
FFCA  
FFCB  
H
H
H
H
H
H
FFC8  
FFC6  
FFC4  
FFC2  
FFC0  
FFC9  
FFC7  
FFC5  
FFC3  
FFC1  
83  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.19 CLRB (Clear direct Memory Bit)  
Set the contents of 1 bit (indicated by 3 lower bits (b) of mnemonic) of the direct area to  
0.  
■ CLRB (Clear direct Memory Bit)  
Operation  
(dir:b) ← 0  
Assembler format  
CLRB dir:b  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4  
Byte count: 2  
OP code: A0 to A7  
84  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CLRB 84H : 0  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
0000 000X 0084H  
0000 0000 0084H  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
00  
00  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
85  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.20 CLRC (Clear Carry flag)  
Set the C-flag to 0.  
■ CLRC (Clear Carry flag)  
Operation  
(C) ← 0  
Assembler format  
CLRC  
Condition code (CCR)  
N
-
Z
-
V
-
C
R
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Set to 0.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 81  
86  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CLRC  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
87  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.21 CLRI (CLeaR Interrupt flag)  
Set the I-flag to 0.  
■ CLRI (CLeaR Interrupt flag)  
Operation  
(I) ← 0  
Assembler format  
CLRI  
Condition code (CCR)  
I
N
-
Z
-
V
-
C
-
R
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
I: Set to 0  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 80  
88  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CLRI  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
H
0
I
IL1 IL0  
N
0
Z
0
V
0
C
H
0
I
IL1 IL0  
N
0
Z
0
V
0
C
0
1
1
1
1
1
1
1
Byte  
Byte  
(After execution)  
Byte  
Byte  
(Before execution)  
89  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.22 CMP (CoMPare Byte Data of Accumulator and Temporary  
Accumulator)  
Compare the byte data of AL with that of TL and set the results to CCR. AL and TL are  
not changed.  
■ CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator)  
Operation  
(TL) - (AL)  
Assembler format  
CMP A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 12  
90  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CMP A  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
75  
XX  
XX  
75  
48  
T
T
XX  
48  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
1
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
91  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.23 CMP (CoMPare Byte Data of Accumulator and Memory)  
Compare the byte data of AL with that of the EA memory (memory expressed in each  
type of addressing) and set the results to CCR. AL and EA memory are not changed.  
■ CMP (CoMPare Byte Data of Accumulator and Memory)  
Operation  
(AL) - (EA)  
Assembler format  
CMP A, EA  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Table 6.23-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
@EP  
Ri  
Number of  
2
3
3
2
2
execution cycles  
Byte count  
OP code  
2
2
2
1
1
14  
15  
16  
17  
18 to 1F  
92  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CMP A , 80H  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
23  
XX  
23  
T
T
IX  
IX  
56  
0180H  
0000H  
56  
0180H  
0000H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
Byte  
N
1
Z
0
V
0
C
1
N
0
Z
0
V
0
C
1
02  
02  
Byte  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
93  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.24 CMP (CoMPare Byte Data of Immediate Data and Memory)  
Compare the byte data of EA memory (memory expressed in each type of addressing)  
with the immediate data and set the results to CCR. EA memory is not changed.  
■ CMP (CoMPare Byte Data of Immediate Data and Memory)  
Operation  
(EA) - d8  
Assembler format  
CMP EA, #d8  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Table 6.24-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
dir  
@IX+off  
@EP  
Ri  
Number of execution  
cycles  
4
4
3
3
Byte count  
OP code  
3
3
2
2
95  
96  
97  
98 to 9F  
94  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CMP @EP , #33H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
54  
0120H  
0000H  
54  
0120H  
0000H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
Byte  
01  
20  
01  
20  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
95  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.25 CMPW (CoMPare Word Data of Accumulator and Temporary  
Accumulator)  
Compare the word data of A with that of T and set the results to CCR. A and T are not  
changed.  
■ CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator)  
Operation  
(T) - (A)  
Assembler format  
CMPW A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Number of execution cycles: 2  
Byte count: 1  
OP code: 13  
96  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : CMPW A  
Memory FFFFH  
Memory FFFFH  
A
A
86  
24  
75  
48  
86  
24  
75  
48  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
1
C
1
N
1
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
97  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.26 DAA (Decimal Adjust for Addition)  
When adding the correction value to AL by the state in the carry before execution of  
instruction and half-carry, decimal operation is corrected.  
■ DAA (Decimal Adjust for Addition)  
Operation  
(AL) ← (AL) + 6 or 60H or 66H  
(Add a correction value shown in the next page to AL and the value of AL according to the state of the  
C or H-flag.)  
Assembler format  
DAA  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Change as indicated on the next page.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 84  
98  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DAA  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
4A  
XX  
50  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
H
I
IL1 IL0  
N
0
Z
0
V
0
C
0
H
I
IL1 IL0  
N
0
Z
0
V
0
C
0
0
0
1
1
0
0
1
1
Byte  
Byte  
(After execution)  
Byte  
Byte  
(Before execution)  
Table 6.26-1 Decimal Adjustment Table (DAA)  
C-flag  
AL  
H-flag  
AL  
Correction  
value  
C-flag after  
execution  
(bit7 to bit4)  
(bit3 to bit0)  
0
0
0
0
0
0
1
1
1
0 to 9  
0 to 8  
0 to 9  
A to F  
9 to F  
A to F  
0 to 2  
0 to 2  
0 to 3  
0
0
1
0
0
1
0
0
1
0 to 9  
A to F  
0 to 3  
0 to 9  
A to F  
0 to 3  
0 to 9  
A to F  
0 to 3  
00  
06  
06  
60  
66  
66  
60  
66  
66  
0
0
0
1
1
1
1
1
1
Table 6.26-2 Execution Example  
Mnemonic  
AL  
C
H
×
0
0
MOV A, #75H  
ADDC A, #25H  
DAA  
75  
9A  
00  
0
0
1
99  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.27 DAS (Decimal Adjust for Subtraction)  
Subtract the correction value from AL according to the state of the C or H-flag before  
executing instruction.  
■ DAS (Decimal Adjust for Subtraction)  
Operation  
(AL) ← (AL) - 6 or 60H or 66H  
(Subtract a correction value shown in the next page to AL and the value of AL according to the state of  
the C or H-flag.)  
Assembler format  
DAS  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Change as indicated on the next page.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 94  
100  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DAS  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
2F  
XX  
29  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
H
I
IL1 IL0  
N
0
Z
0
V
0
C
H
I
IL1 IL0  
N
0
Z
0
V
0
C
0
1
0
1
1
0
1
0
1
1
Byte  
Byte  
(After execution)  
Byte  
Byte  
(Before execution)  
Table 6.27-1 Decimal Adjustment Table (DAS)  
C-flag  
H-flag  
Correction  
value  
C-flag after  
execution  
0
1
0
1
0
1
1
0
00  
66  
06  
60  
0
1
0
1
Table 6.27-2 Execution Example  
Mnemonic  
AL  
C
H
×
0
0
×
1
1
MOV A, #70H  
SUBC A, #25H  
DAS  
70  
4B  
45  
101  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.28 DEC (DECrement Byte Data of General-purpose Register)  
Decrement byte data of Ri by one.  
■ DEC (DECrement Byte Data of General-purpose Register)  
Operation  
(Ri) ← (Ri) - 1 (byte subtract)  
Assembler format  
DEC Ri  
Condition code (CCR)  
N
+
Z
+
V
+
C
-
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Not changed  
Number of execution cycles: 3  
Byte count: 1  
OP code: D8 to DF  
102  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DEC R2  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
R2  
R1  
R0  
0112H  
FD  
R2  
R1  
R0  
0112H  
0110H  
0000H  
FE  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
0110H  
Byte  
Byte  
0000H  
N
1
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
10  
10  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
103  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.29 DECW (DECrement Word Data of Accumulator)  
Decrement word data of A by one.  
■ DECW (DECrement Word Data of Accumulator)  
Operation  
(A) ← (A) - 1 (Word subtraction)  
Assembler format  
DECW A  
Condition code (CCR)  
N
+
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: D0  
104  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DECW A  
Memory FFFFH  
Memory FFFFH  
78  
21  
78  
22  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
105  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.30 DECW (DECrement Word Data of Extra Pointer)  
Decrement word data of EP by one.  
■ DECW (DECrement Word Data of Extra Pointer)  
Operation  
(EP) ← (EP) - 1 (Word subtraction)  
Assembler format  
DECW EP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: D3  
106  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DECW EP  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
12  
34  
12  
33  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
107  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.31 DECW (DECrement Word Data of Index Pointer)  
Decrement word data of IX by one.  
■ DECW (DECrement Word Data of Index Pointer)  
Operation  
(IX) ← (IX) - 1 (Word subtraction)  
Assembler format  
DECW IX  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: D2  
108  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DECW IX  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
16  
27  
16  
26  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
109  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.32 DECW (DECrement Word Data of Stack Pointer)  
Decrement word data of SP by one.  
■ DECW (DECrement Word Data of Stack Pointer)  
Operation  
(SP) ← (SP) - 1 (Word subtraction)  
Assembler format  
DECW SP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: D1  
110  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DECW SP  
Memory FFFFH  
Memory FFFFH  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
111  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.33 DIVU (DIVide Unsigned)  
Divide the word data of T by that of AL as an unsigned binary value. Return the quotient  
to A and the remainder to T.  
When A is 0, the result is indefinite and Z flag is 1 to show 0 division.  
■ DIVU (DIVide Unsigned)  
Operation  
Quotient (A) ← (T) / (A)  
Remainder (T) ← (T) MOD (A)  
Assembler format  
DIVU A  
Condition code (CCR)  
N
-
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Set to 1 if A before execution of instruction is 0000 and set to 0 in other cases.  
H
V: Not changed  
C: Not changed  
Number of execution cycles: 17  
Byte count: 1  
OP code: 11  
112  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : DIVU A  
Memory FFFFH  
Memory FFFFH  
00  
01  
OA  
41  
00  
00  
20  
01  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
113  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.34 INC (INCrement Byte Data of General-purpose Register)  
Add 1 to byte data of Ri.  
■ INC (INCrement Byte Data of General-purpose Register)  
Operation  
(Ri) ← (Ri) + 1 (Word addition)  
Assembler format  
INC Ri  
Condition code (CCR)  
N
+
Z
+
V
+
C
-
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Not changed  
Number of execution cycles: 3  
Byte count: 1  
OP code: C8 to CF  
114  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : INC R1  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
R1  
R0  
R1  
56  
0109H  
0108H  
57  
0109H  
0108H  
R0  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
08  
08  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
115  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.35 INCW (INCrement Word Data of Accumulator)  
Add 1 to word data of A.  
■ INCW (INCrement Word Data of Accumulator)  
Operation  
(A) ← (A) +1 (Word addition)  
Assembler format  
INCW A  
Condition code (CCR)  
N
+
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: C0  
116  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : INCW A  
Memory FFFFH  
Memory FFFFH  
A
A
12  
33  
12  
34  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
117  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.36 INCW (INCrement Word Data of Extra Pointer)  
Add 1 to word data of EP.  
■ INCW (INCrement Word Data of Extra Pointer)  
Operation  
(EP) ← (EP) + 1 (Word addition)  
Assembler format  
INCW EP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: C3  
118  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : INCW EP  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
25  
42  
25  
43  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
119  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.37 INCW (INCrement Word Data of Index Register)  
Add 1 to word data of IX.  
■ INCW (INCrement Word Data of Index Register)  
Operation  
(IX) ← (IX) + 1 (Word addition)  
Assembler format  
INCW IX  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: C2  
120  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : INCW IX  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
25  
72  
25  
73  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
121  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.38 INCW (INCrement Word Data of Stack Pointer)  
Add 1 to word data of SP.  
■ INCW (INCrement Word Data of Stack Pointer)  
Operation  
(SP) ← (SP) + 1 (Word addition)  
Assembler format  
INCW SP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: C1  
122  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : INCW SP  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
FF  
FF  
00  
00  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
123  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.39 JMP (JuMP to address pointed by Accumulator)  
Transfer word data from A to PC.  
■ JMP (JuMP to address pointed by Accumulator)  
Operation  
(PC) ← (A) (Word transfer)  
Assembler format  
JMP @A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 3  
Byte count: 1  
OP code: E0  
124  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : JMP @A  
Memory FFFFH  
Memory FFFFH  
A
A
F0  
89  
F0  
89  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
XX  
XX  
F0  
89  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
0
N
1
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
125  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.40 JMP (JuMP to effective Address)  
Branch to the PC value indicated by ext.  
■ JMP (JuMP to effective Address)  
Operation  
(PC) ← ext (Word transfer)  
Assembler format  
JMP ext  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4  
Byte count: 3  
OP code: 21  
126  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : JMP 0E654H  
Memory FFFFH  
Memory FFFFH  
E654H  
A
A
T
T
IX  
IX  
54  
E6  
54  
E6  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
21  
D800H  
0000H  
21  
D800H  
0000H  
D8  
00  
E6  
54  
Byte  
Byte  
N
0
Z
1
V
1
C
1
N
0
Z
1
V
1
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
127  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.41 MOV (MOVE Byte Data from Temporary Accumulator to  
Address Pointed by Accumulator)  
Transfer byte data from T to memory indirectly addressed by A.  
■ MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by  
Accumulator)  
Operation  
((A)) ← T (Word transfer)  
Assembler format  
MOV @A, T  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 2  
Byte count: 1  
OP code: 82  
128  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOV @A, T  
Memory FFFFH  
Memory FFFFH  
A
A
01  
20  
01  
20  
3F  
T
T
XX  
3F  
XX  
IX  
IX  
XX  
0120H  
0000H  
3F  
0120H  
0000H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
Byte  
N
0
Z
0
V
C
0
N
0
Z
0
V
0
C
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
129  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.42 MOV (MOVE Byte Data from Memory to Accumulator)  
Transfer byte data from EA memory (memory expressed in each type of addressing) to  
A. Byte data in AL is transferred to TL. AH is not changed.  
■ MOV (MOVE Byte Data from Memory to Accumulator)  
Operation  
(AL) ← (EA) (Byte transfer)  
Assembler format  
MOV A, EA  
Condition code (CCR)  
N
+
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of transferred data is 1 and set to 0 in other cases.  
Z: Set to 1 if transferred data is 00 and set to 0 in other cases.  
H
V: Not changed  
C: Not changed  
Table 6.42-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
ext  
@A  
@EP  
Ri  
Number of  
execution cycles  
2
3
3
4
2
2
2
Byte count  
OP code  
2
2
2
3
1
1
1
04  
05  
06  
60  
92  
07  
08 to 0F  
130  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOV A, 83H  
Memory FFFFH  
Memory FFFFH  
A
A
11  
22  
11  
51  
22  
T
T
XX  
XX  
XX  
IX  
IX  
51  
0383H  
51  
0383H  
0000H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
06  
06  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
131  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.43 MOV (MOVE Immediate Byte Data to Memory)  
Transfer byte immediate data to EA memory (memory expressed in each type of  
addressing).  
■ MOV (MOVE Immediate Byte Data to Memory)  
Operation  
(EA) ← d8 (Byte transfer)  
Assembler format  
MOV EA, #d8  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Table 6.43-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
dir  
@IX+off  
@EP  
Ri  
Number of  
execution cycles  
4
4
3
3
Byte count  
OP code  
3
3
2
2
85  
86  
87  
88 to 8F  
132  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOV @IX+02, #35H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
02  
00  
02  
00  
0202H  
0202H  
35  
XX  
(IX+2)  
(IX+2)  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
0200H  
0200H  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
133  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.44 MOV (MOVE Byte Data from Accumulator to memory)  
Transfer bytes (data from AL) immediate data to EA memory (memory expressed in  
each type of addressing).  
■ MOV (MOVE Byte Data from Accumulator to memory)  
Operation  
(EA) ← (AL) (Byte transfer)  
Assembler format  
MOV EA, A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Table 6.44-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
dir  
@IX+off  
ext  
@EP  
Ri  
Number of  
execution cycles  
3
3
4
2
2
Byte count  
OP code  
2
2
3
1
1
45  
46  
61  
47  
48 to 4F  
134  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOV 82H, A  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
06  
XX  
06  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
0202H  
06  
0202H  
0000H  
XX  
Byte  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
03  
03  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
135  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.45 MOVW (MOVE Word Data from Temporary Accumulator to  
Address Pointed by Accumulator)  
Transfer word data from T to memory indirectly addressed by A.  
■ MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by  
Accumulator)  
Operation  
((A)) ← (T) (Word transfer)  
Assembler format  
MOVW @A, T  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 3  
Byte count: 1  
OP code: 83  
136  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW @A, T  
Memory FFFFH  
Memory FFFFH  
A
A
01  
78  
01  
78  
FB  
AA  
T
T
FB  
AA  
IX  
IX  
AA  
FB  
0179H  
0178H  
XX  
XX  
0179H  
0178H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
137  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.46 MOVW (MOVE Word Data from Memory to Accumulator)  
Transfer word data from EA and EA + 1 memories (EA is an address expressed in each  
type of addressing) to A. Word data in A is transferred to T.  
■ MOVW (MOVE Word Data from Memory to Accumulator)  
Operation  
(A) ← (EA) (Word transfer)  
Assembler format  
MOVW A, EA  
Condition code (CCR)  
N
+
Z
+
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if MSB of transferred data is 1 and set to 0 in other cases.  
Z: Set to 1 if transferred data is 0000 and set to 0 in other cases.  
H
V: Not changed  
C: Not changed  
Table 6.46-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d16  
dir  
@IX+off  
ext  
@A  
@EP  
Number of  
execution cycles  
3
4
4
5
3
3
Byte count  
OP code  
3
2
2
3
1
1
E4  
C5  
C6  
C4  
93  
C7  
138  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW A, @IX+01H  
Memory FFFFH  
Memory FFFFH  
A
A
EF  
01  
23  
02  
01  
02  
T
T
XX  
XX  
IX  
IX  
01  
50  
01  
50  
23  
23  
0151H  
EF  
EF  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
(IX+1)  
0150H  
0150H  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
139  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.47 MOVW (MOVE Word Data from Extra Pointer to  
Accumulator)  
Transfer word data from EP to A.  
■ MOVW (MOVE Word Data from Extra Pointer to Accumulator)  
Operation  
(A) ← (EP) (Word transfer)  
Assembler format  
MOVW A, EP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: F3  
140  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW A, EP  
Memory FFFFH  
Memory FFFFH  
A
A
96  
32  
XX  
XX  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
96  
32  
96  
32  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
141  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.48 MOVW (MOVE Word Data from Index Register to  
Accumulator)  
Transfer word data from IX to A.  
■ MOVW (MOVE Word Data from Index Register to Accumulator)  
Operation  
(A) ← (IX) (Word transfer)  
Assembler format  
MOVW A, IX  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: F2  
142  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW A, IX  
Memory FFFFH  
Memory FFFFH  
A
A
87  
87  
23  
23  
XX  
87  
XX  
T
T
IX  
IX  
23  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
143  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.49 MOVW (MOVE Word Data from Program Status Register to  
Accumulator)  
Transfer word data from PS to A.  
■ MOVW (MOVE Word Data from Program Status Register to Accumulator)  
Operation  
(A) ← (PS) (Word transfer)  
Assembler format  
MOVW A, PS  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 70  
144  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW A, PS  
Memory FFFFH  
Memory FFFFH  
A
A
78  
18  
XX  
XX  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
0
N
1
Z
0
V
0
C
0
78  
18  
Byte  
78  
Byte  
18  
Byte  
(Before execution)  
(After execution)  
Byte  
145  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.50 MOVW (MOVE Word Data from Program Counter to  
Accumulator)  
Transfer word data from PC to A.  
■ MOVW (MOVE Word Data from Program Counter to Accumulator)  
Operation  
(A) ← (PC) (Word transfer)  
Assembler format  
MOVW A, PC  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 2  
Byte count: 1  
OP code: F0  
146  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW A, PC  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
XX  
F0  
62  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
F0  
62  
F0  
62  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
147  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.51 MOVW (MOVE Word Data from Stack Pointer to  
Accumulator)  
Transfer word data from SP to A.  
■ MOVW (MOVE Word Data from Stack Pointer to Accumulator)  
Operation  
(A) ← (SP) (Word transfer)  
Assembler format  
MOVW A, SP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: F1  
148  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW A, SP  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
XX  
69  
05  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
69  
05  
69  
05  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
149  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.52 MOVW (MOVE Word Data from Accumulator to Memory)  
Transfer word data from A to EA and EA + 1 memories (memory expressed in each type  
of addressing).  
■ MOVW (MOVE Word Data from Accumulator to Memory)  
Operation  
(EA) ← (A) (Word transfer)  
Assembler format  
MOVW EA, A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Table 6.52-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
dir  
@IX+off  
ext  
@EP  
Number of  
execution cycles  
4
4
5
3
Byte count  
OP code  
2
2
3
1
D5  
D6  
D4  
D7  
150  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW 93H, A  
Memory FFFFH  
Memory FFFFH  
A
A
10  
56  
10  
56  
T
T
IX  
IX  
56  
10  
0094H  
0093H  
XX  
XX  
0094H  
0093H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
00  
00  
Byte  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
151  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.53 MOVW (MOVE Word Data from Accumulator to Extra  
Pointer)  
Transfer word data from A to EP.  
■ MOVW (MOVE Word Data from Accumulator to Extra Pointer)  
Operation  
(EP) ← (A) (Word transfer)  
Assembler format  
MOVW EP, A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: E3  
152  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW EP, A  
Memory FFFFH  
Memory FFFFH  
A
A
87  
65  
87  
65  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
XX  
XX  
87  
65  
N
1
Z
0
V
0
C
0
N
1
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
153  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.54 MOVW (MOVE Immediate Word Data to Extra Pointer)  
Transfer word immediate data to EP.  
■ MOVW (MOVE Immediate Word Data to Extra Pointer)  
Operation  
(EP) ← d16 (Word transfer)  
Assembler format  
MOVW EP, #d16  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 3  
Byte count: 3  
OP code: E7  
154  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW EP, #2345H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
XX  
XX  
23  
45  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
155  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.55 MOVW (MOVE Word Data from Accumulator to Index  
Register)  
Transfer word data from A to IX.  
■ MOVW (MOVE Word Data from Accumulator to Index Register)  
Operation  
(IX) ← (A) (Word transfer)  
Assembler format  
MOVW IX, A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: E2  
156  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW IX, A  
Memory FFFFH  
Memory FFFFH  
56  
43  
56  
56  
43  
43  
A
A
T
T
IX  
IX  
XX  
XX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
157  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.56 MOVW (MOVE Immediate Word Data to Index Register)  
Transfer word immediate data to IX.  
■ MOVW (MOVE Immediate Word Data to Index Register)  
Operation  
(IX) ← d16 (Word transfer)  
Assembler format  
MOVW IX, #d16  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 3  
Byte count: 3  
OP code: E6  
158  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW IX, #4567H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
XX  
XX  
45  
67  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
159  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.57 MOVW (MOVE Word data from Accumulator to Program  
Status Register)  
Transfer word data from A to PS.  
■ MOVW (MOVE Word data from Accumulator to Program Status Register)  
Operation  
(PS) ← (A) (Word transfer)  
Assembler format  
MOVW PS, A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Become the value for lower bit 3 of A  
Z: Become the value for lower bit 2 of A  
V: Become the value for lower bit 1 of A  
C: Become the value for lower bit 0 of A  
Number of execution cycle: 1  
Byte count: 1  
OP code: 71  
160  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW PS, A  
Memory FFFFH  
Memory  
FFFFH  
A
A
50  
32  
50  
32  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
V
C
0
N
X
Z
V
C
X
0
1
X
X
XX  
Byte  
XX  
Byte  
50  
Byte  
32  
Byte  
(After execution)  
(Before execution)  
161  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.58 MOVW (MOVE Immediate Word Data to Stack Pointer)  
Transfer word immediate data to SP.  
■ MOVW (MOVE Immediate Word Data to Stack Pointer)  
Operation  
(SP) ← d16 (Word transfer)  
Assembler format  
MOVW SP, #d16  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 3  
Byte count: 3  
OP code: E5  
162  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW SP, #6789H  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
XX  
XX  
67  
89  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
163  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.59 MOVW (MOVE Word data from Accumulator to Stack  
Pointer)  
Transfer word data from A to SP.  
■ MOVW (MOVE Word data from Accumulator to Stack Pointer)  
Operation  
(SP) ← (A) (Word transfer)  
Assembler format  
MOVW SP, A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: E1  
164  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MOVW SP, A  
Memory FFFFH  
Memory FFFFH  
43  
21  
A
43  
21  
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
43  
21  
XX  
XX  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
165  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.60 MULU (MULtiply Unsigned)  
Multiply the byte data of AL and TL as unsigned binary values. Return the results to the  
word data of A.  
■ MULU (MULtiply Unsigned)  
Operation  
(A) ← (AL) * (TL)  
Assembler format  
MULU A  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 8  
Byte count: 1  
OP code: 01  
166  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : MULU A  
Memory FFFFH  
Memory FFFFH  
XX  
XX  
20  
40  
A
08  
00  
40  
A
T
XX  
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
167  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.61 NOP (NoOPeration)  
No operation  
■ NOP (NoOPeration)  
Operation  
————  
Assembler format  
NOP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 00  
168  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : NOP  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
PC+1  
PC  
PC+1  
PC  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
C
Byte  
Z
0000H  
C
N
V
N
Z
V
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
169  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.62 OR (OR Byte Data of Accumulator and Temporary  
Accumulator to Accumulator)  
Carry out the logical OR on byte data of AL and TL for every bit and return the results to  
AL. The contents of AH are not changed.  
■ OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator)  
Operation  
(AL) ← (AL) ∨ (TL) (byte logical OR)  
Assembler format  
OR A  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 72  
170  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : OR A  
Memory FFFFH  
Memory FFFFH  
15  
23  
41  
A
15  
63  
41  
A
XX  
T
XX  
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
171  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.63 OR (OR Byte Data of Accumulator and Memory to  
Accumulator)  
Carry out the logical OR on AL and EA memory (memory expressed in each type of  
addressing) for every bit and return the results to AL. The contents of AH are not  
changed.  
■ OR (OR Byte Data of Accumulator and Memory to Accumulator)  
Operation  
(AL) ← (AL)∨ (EA) (byte logical OR)  
Assembler format  
OR A, EA  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Table 6.63-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
@EP  
Ri  
Number of  
execution cycles  
2
3
3
2
2
Byte count  
OP code  
2
2
2
1
1
74  
75  
76  
77  
78 to 7F  
172  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : OR A, @EP  
Memory FFFFH  
Memory FFFFH  
15  
76  
A
A
15  
32  
T
T
IX  
IX  
56  
0122H  
56  
0122H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
01  
22  
01  
22  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
173  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.64 ORW (OR Word Data of Accumulator and Temporary  
Accumulator to Accumulator)  
Carry out the logical OR on the word data of A and T for every bit and return the results  
to A.  
■ ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator)  
Operation  
(A) ← (A) ∨ (T) (word logical OR)  
Assembler format  
ORW A  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 73  
174  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : ORW A  
Memory FFFFH  
Memory FFFFH  
77  
33  
63  
41  
A
A
57  
33  
23  
41  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
175  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.65 PUSHW (PUSH Word Data of Inherent Register to Stack  
Memory)  
Subtract 2 from the value of SP. Then, transfer the word value from the memory  
indicated by SP to dr.  
■ PUSHW (PUSH Word Data of Inherent Register to Stack Memory)  
Operation  
(SP) ← (SP) - 2 (Word subtraction)  
((SP)) ← (dr) (Word transfer)  
Assembler format  
PUSHW dr  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Table 6.65-1 Number of Execution Cycles / Byte Count / OP Code  
DR  
A
IX  
Number of execution  
cycles  
4
4
Byte count  
OP code  
1
1
40  
41  
176  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : PUSHW IX  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
12  
02  
34  
22  
12  
02  
34  
20  
0222H  
0222H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
X
X
34  
12  
0220H  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
177  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.66 POPW (POP Word Data of Intherent Register from Stack  
Memory)  
Transfer the word value from the memory indicated by SP to dr. Then, add 2 to the value  
of SP.  
■ POPW (POP Word Data of Intherent Register from Stack Memory)  
Operation  
(dr) ← ((SP)) (Word transfer)  
(SP) ← (SP) + 2 (Word addition)  
Assembler format  
POPW dr  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Table 6.66-1 Number of Execution Cycles / Byte Count / OP Code  
DR  
A
IX  
Number of execution  
cycles  
3
3
Byte count  
OP code  
1
1
50  
51  
178  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : POPW A  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
XX  
31  
26  
T
T
IX  
IX  
0235H  
02  
35  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
33  
26  
31  
26  
0233H  
0000H  
31  
0233H  
0000H  
Byte  
Byte  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
179  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.67 RET (RETurn from subroutine)  
Return the contents of PC saved in the stack. When this instruction is used in  
combination with the CALLV or CALL instruction, return to the next instruction to each  
of them.  
■ RET (RETurn from subroutine)  
Operation  
(PC) ← ((SP)) (Word transfer)  
(SP) ← (SP) + 2 (Word addition)  
Assembler format  
RET  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 6  
Byte count: 1  
OP code: 20  
180  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : RET  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
IX  
IX  
0208H  
02  
08  
10  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
F8  
06  
09  
10  
10  
FC  
0206H  
0000H  
FC  
0206H  
0000H  
FC  
Byte  
Byte  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
181  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.68 RETI (RETurn from Interrupt)  
Return the contents of PS and PC saved in the stack. Return PS and PC to the state  
before interrupt.  
■ RETI (RETurn from Interrupt)  
Operation  
(PS) ← ((SP)), (PC) ← ((SP + 2)) (Word transfer)  
(SP) ← (SP) + 4 (Word addition)  
Assembler format  
RETI  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Become to the saved value of N.  
Z: Become to the saved value of Z.  
V: Become to the saved value of V.  
C: Become to the saved value of C.  
Number of execution cycles: 8  
Byte count: 1  
OP code: 30  
182  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : RETI  
Memory FFFFH  
Memory FFFFH  
A
A
T
T
020AH  
IX  
IX  
10  
10  
0208H  
FC  
84  
08  
FC  
84  
08  
02  
OA  
10  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
02  
06  
0206H  
0000H  
0206H  
0000H  
XX  
XX  
FC  
Byte  
Byte  
N
0
Z
1
V
0
C
0
N
1
Z
0
V
1
C
1
XX  
Byte  
XB  
08  
84  
Byte  
(Before execution)  
(After execution)  
Byte  
Byte  
183  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.69 ROLC (Rotate Byte Data of Accumulator with Carry to Left)  
Shift byte data of AL with a carry one bit to the left. The contents of AH are not changed.  
■ ROLC (Rotate Byte Data of Accumulator with Carry to Left)  
Operation  
C
AL  
Assembler format  
ROLC A  
Condition code (CCR)  
N
+
Z
+
V
-
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of the shift and set to 0 in other cases.  
Z: Set to 1 if the result of the shift is 00 and set to 0 in other cases.  
H
V: Not changed  
C: Enter Bit 7 of A before shift.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 02  
184  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : ROLC A  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
55  
XX  
AB  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
0
N
0
Z
0
V
0
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
185  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.70 RORC (Rotate Byte Data of Accumulator with Carry to Right)  
Shift byte data of AL with a carry bit to the right. The contents of AH are not changed.  
■ RORC (Rotate Byte Data of Accumulator with Carry to Right)  
Operation  
AL  
C
Assembler format  
RORC A  
Condition code (CCR)  
N
+
Z
+
V
-
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB is 1 as the result of the shift and set to 0 in other cases.  
Z: Set to 1 if the result of the shift is 00 and set to 0 in other cases.  
H
V: Not changed  
C: LSB of A before entering shift  
Number of execution cycle: 1  
Byte count: 1  
OP code: 03  
186  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : RORC A  
Memory FFFFH  
Memory FFFFH  
A
A
XX  
55  
XX  
AA  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
1
N
0
Z
0
V
0
C
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
187  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.71 SUBC (SUBtract Byte Data of Accumulator from Temporary  
Accumulator with Carry to Accumulator)  
Subtract the byte data of AL from that of TL, subtract a carry and then return the result  
to AL. The contents of AH are not changed.  
■ SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to  
Accumulator)  
Operation  
(AL) ← (TL) - (AL) - C (Byte subtraction with carry)  
Assembler format  
SUBC A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 32  
188  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SUBC A  
Memory FFFFH  
Memory FFFFH  
A
A
12  
23  
12  
76  
11  
34  
T
T
76  
34  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
189  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.72 SUBC (SUBtract Byte Data of Memory from Accumulator  
with Carry to Accumulator)  
Subtract the byte data of the EA memory (memory expressed in each type of  
addressing) from that of AL, subtract a carry and then return the results to AL. The  
contents of AH are not changed.  
■ SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator)  
Operation  
(AL) ← (AL) - (EA) - C (Byte subtraction with carry)  
Assembler format  
SUBC A, EA  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Table 6.72-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
@EP  
Ri  
Number of  
execution cycles  
2
3
3
2
2
Byte count  
OP code  
2
2
2
1
1
34  
35  
36  
37  
38 to 3F  
190  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SUBC A, #37H  
Memory FFFFH  
Memory FFFFH  
A
A
12  
34  
12  
FD  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
1
Z
0
V
0
C
1
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
191  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.73 SUBCW (SUBtract Word Data of Accumulator from  
Temporary Accumulator with Carry to Accumulator)  
Subtract the word data of A from that of T, subtract a carry and then return the result to  
A.  
■ SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with  
Carry to Accumulator)  
Operation  
(AL) ← (T) - (A) - C (Word subtraction with carry)  
Assembler format  
SUBCW A  
Condition code (CCR)  
N
+
Z
+
V
+
C
+
+: Changed by executing instruction  
-: Not changed  
N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Set to 1 if an overflow occurs as the result of operation and set to 0 in other cases.  
C: Set to 1 if a carry occurs as the result of operation and set to 0 in other cases.  
Number of execution cycle: 1  
Byte count: 1  
OP code: 33  
192  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SUBCW A  
Memory FFFFH  
Memory FFFFH  
A
A
32  
56  
14  
34  
24  
56  
20  
34  
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
Byte  
0000H  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
193  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.74 SETB (Set Direct Memory Bit)  
Set the contents of 1 bit (indicated by 3 lower bits (b) of mnemonic) for the direct area to  
1.  
■ SETB (Set Direct Memory Bit)  
Operation  
(dir:b) ← 1  
Assembler format  
SETB dir:b  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 4  
Byte count: 2  
OP code: A8 to AF  
194  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SETB 32H : 5  
Memory  
Memory  
FFFFH  
FFFFH  
A
A
T
T
IX  
IX  
00X0 0000 0032H  
0010 0000 0032H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
0
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
05  
05  
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
195  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.75 SETC (SET Carry flag)  
Set the C-flag to 1.  
■ SETC (SET Carry flag)  
Operation  
(C) ← 1  
Assembler format  
SETC  
Condition code (CCR)  
N
-
Z
-
V
-
C
S
+: Changed by executing instruction  
-: Not changed  
S: Set to 1 by executing instruction  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Set to 1  
Number of execution cycle: 1  
Byte count: 1  
OP code: 91  
196  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SETC  
Memory  
Memory  
FFFFH  
FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
1
N
0
Z
0
V
0
C
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
197  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.76 SETI (SET Interrupt flag)  
Set the I-flag to 1 (enable an interrupt).  
■ SETI (SET Interrupt flag)  
Operation  
(I) ← 1  
Assembler format  
SETI  
Condition code (CCR)  
I
N
-
Z
-
V
-
C
-
S
+: Changed by executing instruction  
-: Not changed  
S: Set to 1 by executing instruction  
I: Set to 1  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 90  
198  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SETI  
Memory  
Memory  
FFFFH  
FFFFH  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
H
0
I
IL1 IL0  
N
0
Z
0
V
0
C
H
0
I
IL1 IL0  
N
0
Z
0
V
0
C
0
1
1
1
1
1
1
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
199  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.77 SWAP (SWAP Byte Data Accumulator "H" and Accumulator  
"L")  
Exchange the byte data of AH for that of AL.  
■ SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L")  
Operation  
(AH) ↔ (AL) (Byte data exchange)  
Assembler format  
SWAP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 10  
200  
 
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : SWAP  
Memory  
Memory  
FFFFH  
FFFFH  
32  
AA  
AA  
32  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
201  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.78 XCH (eXCHange Byte Data Accumulator "L" and Temporary  
Accumulator "L")  
Exchange the byte data of AL for that of TL.  
■ XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L")  
Operation  
(AL) ↔ (TL) (conversion of byte data)  
Assembler format  
XCH A, T  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 42  
202  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XCH A, T  
Memory  
Memory  
FFFFH  
FFFFH  
32  
AA  
32  
55  
79  
A
A
T
T
55  
79  
AA  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
203  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.79 XCHW (eXCHange Word Data Accumulator and Extrapointer)  
Exchange the word data of A for that of EP.  
■ XCHW (eXCHange Word Data Accumulator and Extrapointer)  
Operation  
(A) ↔ (EP)  
Assembler format  
XCHW A, EP  
(conversion of word data)  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: F7  
204  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XCHW A, EP  
Memory  
Memory  
FFFFH  
FFFFH  
32  
AA  
55  
79  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
55  
79  
32  
AA  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
205  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.80 XCHW (eXCHange Word Data Accumulator and Index  
Register)  
Exchange the word data of A for that of IX.  
■ XCHW (eXCHange Word Data Accumulator and Index Register)  
Operation  
(A) ↔ (IX) (conversion of word data)  
Assembler format  
XCHW A, IX  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: F6  
206  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XCHW A, IX  
Memory  
Memory  
FFFFH  
FFFFH  
32  
55  
AA  
79  
55  
32  
79  
A
A
T
T
IX  
IX  
AA  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
207  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.81 XCHW (eXCHange Word Data Accumulator and Program  
Counter)  
Exchange the word data of PC for that of A.  
■ XCHW (eXCHange Word Data Accumulator and Program Counter)  
Operation  
(PC) ← (A) (word transfer)  
(A) ← (PC) +1 (word addition, word transfer)  
Assembler format  
XCHW A, PC  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 3  
Byte count: 1  
OP code: F4  
208  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XCHW A, PC  
Memory  
Memory  
FFFFH  
FFFFH  
F0  
C7  
F1  
7A  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
F1  
79  
F0  
C7  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
1
1
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
209  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.82 XCHW (eXCHange Word Data Accumulator and Stack  
Pointer)  
Exchange the word data of A for that of SP.  
■ XCHW (eXCHange Word Data Accumulator and Stack Pointer)  
Operation  
(A) ↔ (SP) (conversion of word data)  
Assembler format  
XCHW A, SP  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycles: 2  
Byte count: 1  
OP code: F5  
210  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XCHW A, SP  
Memory  
Memory  
FFFFH  
FFFFH  
32  
AA  
55  
79  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
55  
79  
32  
AA  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
211  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.83 XCHW (eXCHange Word Data Accumulator and Temporary  
Accumulator)  
Exchange the word data of A for that of T.  
■ XCHW (eXCHange Word Data Accumulator and Temporary Accumulator)  
Operation  
(A) ↔ (T) (conversion of word data)  
Assembler format  
XCHW A, T  
Condition code (CCR)  
N
-
Z
-
V
-
C
-
+: Changed by executing instruction  
-: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 43  
212  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XCHW A, T  
Memory  
Memory  
FFFFH  
FFFFH  
32  
AA  
55  
32  
79  
A
A
T
T
55  
79  
AA  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
213  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.84 XOR (eXclusive OR Byte Data of Accumulator and  
Temporary Accumulator to Accumulator)  
Carry out the logical exclusive-OR on the byte data of AL and TL for every bit and return  
the results to AL. The contents of AH are not changed.  
■ XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to  
Accumulator)  
Operation  
(AL) ← (AL) ∀ (TL) (byte logical exclusive-OR)  
Assembler format  
XOR A  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 52  
214  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XOR A  
Memory  
Memory  
FFFFH  
FFFFH  
76  
23  
76  
62  
41  
A
A
T
T
XX  
41  
XX  
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
0
Z
0
V
0
C
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
215  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.85 XOR (eXclusive OR Byte Data of Accumulator and Memory  
to Accumulator)  
Carry out the logical exclusive-OR for the byte data of AL and EA memory (memory  
expressed in each type of addressing) for every bit and return the results to AL. The  
contents of AH are not changed.  
■ XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator)  
Operation  
(AL) ← (AL) ∀ (EA) (byte logical exclusive-OR)  
Assembler format  
XOR A, EA  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of AL is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 00 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Table 6.85-1 Number of Execution Cycles / Byte Count / OP Code  
EA  
#d8  
dir  
@IX+off  
@EP  
Ri  
Number of  
execution cycles  
2
3
3
2
2
Byte count  
OP code  
2
2
2
1
1
54  
55  
56  
57  
58 to 5F  
216  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XOR A, @EP  
Memory  
Memory  
FFFFH  
FFFFH  
54  
32  
54  
20  
A
A
T
T
IX  
IX  
12  
0122H  
12  
0122H  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
01  
22  
01  
22  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
217  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
6.86 XORW (eXclusive OR Word Data of Accumulator and  
Temporary Accumulator to Accmulator)  
Carry out the logical exclusive-OR on the word data of A and T for every bit and return  
the results to A.  
■ XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to  
Accmulator)  
Operation  
(A) ← (A) ∀ (T) (word logical exclusive-OR)  
Assembler format  
XORW A  
Condition code (CCR)  
N
+
Z
+
V
R
C
-
+: Changed by executing instruction  
-: Not changed  
R: Set to 0 by executing instruction  
N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0000 and set to 0 in other cases.  
H
V: Always set to 0  
C: Not changed  
Number of execution cycle: 1  
Byte count: 1  
OP code: 53  
218  
   
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
Execution example : XORW A  
Memory  
Memory  
FFFFH  
FFFFH  
57  
33  
23  
41  
64  
33  
62  
41  
A
A
T
T
IX  
IX  
SP  
PC  
EP  
PS  
SP  
PC  
EP  
PS  
Byte  
0000H  
0000H  
Byte  
N
Z
0
V
0
C
0
N
Z
0
V
0
C
0
0
0
(Before execution)  
(After execution)  
Byte  
Byte  
Byte  
Byte  
219  
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS  
220  
APPENDIX  
The appendix contains instruction and bus operation  
lists and an instruction map.  
APPENDIX A Instruction List  
APPENDIX B Bus Operation List  
APPENDIX C Instruction Map  
221  
     
APPENDIX  
APPENDIX A Instruction List  
Appendix A contains lists of instructions used in the assembler.  
2
A.1 F MC-8FX CPU Instruction Overview  
A.2 Operation List  
A.3 Flag Change Table  
222  
 
APPENDIX A Instruction List  
2
A.1 F MC-8FX CPU Instruction Overview  
2
This section explains the F MC-8FX CPU instructions.  
2
■ F MC-8FX CPU Instruction Overview  
2
In the F MC-8FX CPU, there is 140 kinds of one byte machine instruction (as the map, 256 bytes), and the  
instruction code is composed of the instruction and the operand following it.  
Figure A.1-1 shows the instruction code and the correspondence of the instruction map.  
Figure A.1-1 Correspondence between the Instruction Code and the Instruction Map  
Give 0 to 2 bytes according to  
the instruction.  
1 byte  
Machine  
instruction  
Instruction code  
Upper 4 bits  
Operand  
Operand  
[Instruction map]  
2
The following are enumerated as a feature of F MC-8FX CPU instruction.  
•
•
The instruction is classified into 4 types: transfer, operation, branch, and others.  
There is various methods of address specification, and ten kinds of addressing can be selected by the  
selection of the instruction and the operand specification.  
•
•
It provides with the bit operation instruction, and the read modification write can operate.  
There is an instruction that directs special operation.  
223  
     
APPENDIX  
■ Sign of the Instruction List  
Table A.1-1 explains the sign used by describing the instruction code in the table.  
Table A.1-1 Sign of the Instruction List  
Notation  
Meaning  
dir  
Direct address (8 bits)  
off  
Offset (8 bits)  
ext  
#vct  
#d8  
#d16  
dir:b  
rel  
Extended address (16 bits)  
Vector table number (3 bits)  
Immediate data (8 bits)  
Immediate data (16 bits)  
Bit direct address (8 bits: 3 bits)  
Relative branch address (8 bits)  
Register indirect (example: @A, @IX, @EP)  
@
A
Accumulator (8-bit or 16-bit length is determined by instruction to be used.)  
Upper 8 bits of accumulator (8 bits)  
AH  
AL  
T
Lower 8 bits of accumulator (8 bits)  
Temporary accumulator (8-bit or 16-bit length is determined by instruction to be used.)  
Upper 8 bits of temporary accumulator (8 bits)  
Lower 8 bits of temporary accumulator (8 bits)  
Index register (16 bits)  
TH  
TL  
IX  
EP  
PC  
SP  
Extra pointer (16 bits)  
Program counter (16 bits)  
Stack pointer (16 bits)  
PS  
Program status (16 bits)  
dr  
Accumulator or index register (16 bits)  
CCR  
RP  
DP  
Ri  
Condition code register (8 bits)  
Register bank pointer (5 bits)  
Direct bank pointer (3 bits)  
General-purpose register (8 bits, i = 0 to 7)  
X indicates immediate data. (8-bit or 16-bit length is determined by instruction to be used.)  
The contents of X are to be accessed. (8-bit or 16-bit length is determined by instruction to be used.)  
X
(X)  
((X))  
The address indicated by the contents of X is to be accessed. (8-bit or 16-bit length is determined by  
instruction to be used.)  
224  
   
APPENDIX A Instruction List  
■ Item in Instruction Table  
Table A.1-2 explains the item of instruction table.  
Table A.1-2 Item in Instruction Table  
Item  
Description  
The assembly description of the instruction is shown.  
NMEMONIC  
RD  
WR  
RMW  
~
The read of an internal bus is shown.  
The write of an internal bus is shown.  
The read modification write signal of an internal bus is shown.  
Cycle of the instruction number is shown. One instruction cycle is one machine cycle.  
Note:  
The instruction cycle number might be postponed one cycle by the immediately preceding instruction.  
Moreover, cycle of the instruction number might be extended in the access to the IO area.  
#
The number of bytes for the instruction is shown.  
The operation of the instruction is shown.  
Operation  
TL, TH, AH  
The change in the content when TL, TH, and AH each instruction is executed is shown. The sign in the  
column shows the following respectively.  
•
•
•
•
- : Do not change.  
dH : Upper 8 bits of the data written in operation  
AL, AH : Become the contents of AL or AH immediately before instruction.  
00 : Become 00.  
N, Z, V, C  
OP CODE  
The flag changed when each instruction is executed is shown. The sign in the column shows the  
following respectively.  
•
•
•
•
- : Do not change.  
+ : Change.  
R : Become 0.  
S : Become 1.  
The code of the instruction is shown. When a pertinent instruction occupies two or more codes, it  
follows the following description rules.  
48 to 4F: 48, 49, ..., 4F are shown.  
225  
   
APPENDIX  
A.2 Operation List  
Table A.2-1 is the operation list for transfer instructions. Table A.2-2 is the operation list  
for operation instructions. Table A.2-3 is the operation list for branch instructions. Table  
A.2-4 is the operation list for other instructions.  
■ Operation List  
Table A.2-1 Operation List (for Transfer Instructions) (1/3)  
No  
MNEMONIC  
~
#
OPERATION  
(dir) ← (A)  
TL TH AH  
N Z V C  
OP CODE  
1
2
MOV dir, A  
3
3
2
2
–
–
–
–
–
–
– – – –  
– – – –  
45  
46  
MOV @IX+off,  
A
(IX)+off) ← (A)  
3
4
5
MOV ext, A  
MOV @EP, A  
MOV Ri, A  
4
2
2
3
1
1
(ext) ← (A)  
((EP)) ← (A)  
(Ri) ← (A)  
–
–
–
–
–
–
–
–
–
– – – –  
– – – –  
– – – –  
61  
47  
48 to 4F  
6
7
8
MOV A, #d8  
MOV A, dir  
2
3
3
2
2
2
(A) ← d8  
AL  
AL  
AL  
–
–
–
–
–
–
+ + – –  
+ + – –  
+ + – –  
04  
05  
06  
(A) ← (dir)  
MOV A,  
@IX+off  
(A) ← ((IX)+off)  
9
MOV A, ext  
MOV A, @A  
4
2
3
1
(A) ← (ext)  
AL  
AL  
–
–
–
–
+ + – –  
+ + – –  
60  
92  
10  
(A) ← ((A))  
11  
12  
13  
14  
MOV A, @EP  
MOV A, Ri  
2
2
4
4
1
1
3
3
(A) ← ((EP))  
(A) ← (Ri)  
AL  
AL  
–
–
–
–
–
–
–
–
–
+ + – –  
+ + – –  
– – – –  
– – – –  
07  
08 to 0F  
85  
MOV dir, #d8  
(dir) ← d8  
MOV @IX+off,  
#d8  
((IX)+off) ← d8  
–
86  
15  
MOV @EP, #d8  
3
2
((EP)) ← d8  
–
–
–
– – – –  
87  
16  
17  
MOV Ri, #d8  
MOVW dir, A  
3
4
2
2
(Ri) ← d8  
–
–
–
–
–
–
– – – –  
– – – –  
88 to 8F  
D5  
(dir) ← (AH),  
(dir+1)←(AL)  
18  
MOVW  
@IX+off, A  
4
2
((IX)+off) ← (AH),  
((IX)+off+1) ← (AL)  
–
–
–
– – – –  
D6  
226  
     
APPENDIX A Instruction List  
Table A.2-1 Operation List (for Transfer Instructions) (2/3)  
No  
MNEMONIC  
~
#
OPERATION  
TL TH AH  
N Z V C  
OP CODE  
19  
MOVW ext, A  
5
3
3
1
(ext) ← (AH),  
–
–
–
– – – –  
D4  
(ext+1) ← (AL)  
20  
MOVW @EP, A  
((EP)) ← (AH),  
((EP)+1) ← (AL)  
–
–
–
– – – –  
D7  
21  
22  
23  
MOVW EP, A  
MOVW A, #d16  
MOVW A, dir  
1
3
4
1
3
2
(EP) ← (A)  
–
–
–
– – – –  
+ + – –  
+ + – –  
E3  
E4  
C5  
(A) ← d16  
AL AH dH  
AL AH dH  
(AH) ← (dir),  
(AL) ← (dir+1)  
24  
25  
MOVW A,  
@IX+off  
4
5
2
3
(AH) ← ((IX)+off),  
AL AH dH  
AL AH dH  
+ + – –  
+ + – –  
C6  
C4  
(AL) ← ((IX)+off+1)  
MOVW A, ext  
(AH) ← (ext),  
(AL) ← (ext+1)  
26  
27  
MOVW A, @A  
MOVW A, @EP  
3
3
1
1
(AH) ← ((A)),  
AL AH dH  
AL AH dH  
+ + – –  
+ + – –  
93  
(AL) ← ((A)+1)  
(AH) ← ((EP)),  
(AL) ← ((EP)+1)  
C7  
28  
29  
30  
MOVW A, EP  
MOVW EP, #d16  
MOVW IX, A  
1
3
1
1
3
1
(A) ← (EP)  
(EP) ← d16  
(IX) ← (A)  
–
–
–
–
–
–
dH  
–
– – – –  
– – – –  
– – – –  
F3  
E7  
E2  
–
31  
32  
33  
34  
35  
MOVW A, IX  
MOVW SP, A  
MOVW A, SP  
MOV @A, T  
MOVW @A, T  
1
1
1
2
3
1
1
1
1
1
(A) ← (IX)  
(SP) ← (A)  
(A) ← (SP)  
((A)) ← (T)  
–
–
–
–
–
–
–
–
–
–
dH  
–
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
F2  
E1  
F1  
82  
83  
dH  
–
((A)) ← (TH),  
((A)+1) ← (TL)  
–
36  
37  
38  
39  
40  
MOVW IX, #d16  
MOVW A, PS  
MOVW PS, A  
MOVW SP, #d16  
SWAP  
3
1
1
3
1
3
1
1
3
1
(IX) ← d16  
(A) ← (PS)  
(PS) ← (A)  
(SP) ← d16  
(AH) ↔ (AL)  
–
–
–
–
–
–
–
–
–
–
–
– – – –  
– – – –  
+ + + +  
– – – –  
– – – –  
E6  
70  
71  
E5  
10  
dH  
–
–
AL  
227  
APPENDIX  
Table A.2-1 Operation List (for Transfer Instructions) (3/3)  
No  
MNEMONIC  
~
#
OPERATION  
(dir):b ← 1  
TL TH AH  
N Z V C  
OP CODE  
41  
42  
43  
44  
45  
SETB dir:b  
CLRB dir:b  
XCH A, T  
4
4
1
1
1
2
2
1
1
1
–
–
–
–
–
–
–
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
A8 to AF  
A0 to A7  
42  
(dir):b ← 0  
(AL) ↔ (TL)  
(A) ↔ (T)  
–
AL  
XCHW A, T  
XCHW A, EP  
AL AH dH  
43  
(A) ↔ (EP)  
–
–
dH  
F7  
46  
47  
48  
XCHW A, IX  
XCHW A, SP  
MOVW A, PC  
1
1
2
1
1
1
(A) ↔ (IX)  
(A) ↔ (SP)  
(A) ← (PC)  
–
–
–
–
–
–
dH  
dH  
dH  
– – – –  
– – – –  
– – – –  
F6  
F5  
F0  
Notes:  
1. In byte transfer to A, T ← A is only low bytes.  
2. The operands of an instruction with two or more operands should be stored in the order designated in  
MNEMONIC.  
Table A.2-2 Operation List (for Operation Instructions) (1/3)  
No  
MNEMONIC  
~
#
OPERATION  
TL TH AH  
NZVC  
OP CODE  
1
ADDC A, Ri  
ADDC A, #d8  
ADDC A, dir  
2
2
3
3
1
2
2
2
(A) ← (A)+(Ri)+C  
(A) ← (A)+d8+C  
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +  
+ + + +  
+ + + +  
+ + + +  
28 to 2F  
24  
2
3
4
(A) ← (A)+(dir)+C  
(A) ← (A)+((IX)+off)+C  
25  
ADDC A,  
@IX+off  
26  
5
ADDC A, @EP  
2
1
(A) ← (A)+((EP))+C  
–
–
–
+ + + +  
27  
6
ADDCW A  
ADDC A  
1
1
2
2
3
1
1
1
2
2
(A) ← (A)+(T)+C  
(AL) ← (AL)+(TL)+C  
(A) ← (A)-(Ri)-C  
(A) ← (A)-d8-C  
–
–
–
–
–
–
–
–
–
–
dH  
–
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
23  
7
22  
8
SUBC A, Ri  
SUBC A, #d8  
SUBC A, dir  
–
38 to 3F  
34  
9
–
10  
(A) ← (A)-(dir)-C  
–
35  
11  
SUBC A,  
@IX+off  
3
2
(A) ← (A)-((IX)+off)-C  
–
–
–
+ + + +  
36  
12  
13  
14  
SUBC A, @EP  
SUBCW A  
2
1
1
1
1
1
(A) ← (A)-((EP))-C  
(A) ← (T)-(A)-C  
–
–
–
–
–
–
–
+ + + +  
+ + + +  
+ + + +  
37  
33  
32  
dH  
–
SUBC  
A
(AL) ← (TL)-(AL)-C  
228  
 
APPENDIX A Instruction List  
Table A.2-2 Operation List (for Operation Instructions) (2/3)  
No  
MNEMONIC  
~
#
OPERATION  
(Ri) ← (Ri)+1  
TL TH AH  
NZVC  
OP CODE  
15  
IINC Ri  
3
1
–
–
–
+ + + –  
C8 to CF  
16  
17  
18  
19  
20  
INCW EP  
INCW IX  
INCW A  
DEC Ri  
1
1
1
3
1
1
1
1
1
1
(EP) ← (EP)+1  
(IX) ← (IX)+1  
(A) ← (A)+1  
(Ri) ← (Ri)-1  
(EP) ← (EP)-1  
–
–
–
–
–
–
–
–
–
–
–
– – – –  
– – – –  
+ + – –  
+ + + –  
– – – –  
C3  
–
C2  
dH  
–
C0  
D8 to DF  
D3  
DECW EP  
–
21  
22  
23  
24  
DECW IX  
DECW A  
MULU A  
DIVU A  
1
1
8
1
1
1
1
(IX) ← (IX)-1  
(A) ← (A)-1  
–
–
–
–
–
– – – –  
+ + – –  
– – – –  
– + – –  
D2  
D0  
01  
–
dH  
dH  
(A) ← (AL)*(TL)  
–
17  
(A) ← (T)/(A),  
MOD → (T)  
dL  
dH dH  
11  
25  
ANDW A  
1
1
(A) ← (A) ^ (T)  
–
–
dH  
+ + R –  
63  
26  
27  
28  
29  
30  
ORW A  
XORW A  
CMP A  
1
1
1
1
1
1
1
1
1
1
(A) ← (A) ∨ (T)  
(A) ← (A) ∀ (T)  
(TL)-(AL)  
–
–
–
–
–
–
–
–
–
–
dH  
dH  
–
+ + R –  
+ + R –  
+ + + +  
+ + + +  
+ + – +  
73  
53  
12  
13  
03  
CMPW A  
RORC A  
(T)- (A)  
–
–
C → A  
31  
ROLC A  
1
1
–
–
–
+ + – +  
02  
C ← A  
32  
33  
34  
35  
CMP A, #d8  
CMP A, dir  
CMP A, @EP  
2
3
2
3
2
2
1
2
(A)- d8  
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +  
+ + + +  
+ + + +  
+ + + +  
14  
15  
17  
16  
(A)- (dir)  
(A)- ((EP))  
(A)- ((IX)+off)  
CMP A,  
@IX+off  
36  
37  
CMP A, Ri  
DAA  
2
1
1
1
(A)- (Ri)  
–
–
–
–
–
–
+ + + +  
+ + + +  
18 to 1F  
84  
decimal adjust for addition  
229  
APPENDIX  
Table A.2-2 Operation List (for Operation Instructions) (3/3)  
No  
MNEMONIC  
DAS  
~
#
OPERATION  
TL TH AH  
NZVC  
OP CODE  
38  
1
1
decimal adjust for  
subtraction  
–
–
–
+ + + +  
94  
39  
40  
XOR A  
1
2
1
2
(A) ← (AL) ∀ (TL)  
–
–
–
–
–
–
+ + R –  
+ + R –  
52  
54  
XOR A, #d8  
(A) ← (AL) ∀ d8  
41  
42  
43  
44  
45  
XOR A, dir  
XOR A, @EP  
XOR A, @IX+off  
XOR A, Ri  
3
3
4
2
1
2
1
2
1
1
(A) ← (AL) ∀ (dir)  
(A) ← (AL) ∀ ((EP))  
(A) ← (AL) ∀ ((IX)+off)  
(A) ← (AL) ∀ (Ri)  
(A) ← (AL) ^ (TL)  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
55  
57  
56  
58 to 5F  
62  
AND A  
46  
47  
48  
49  
AND A, #d8  
2
3
2
3
2
2
1
2
(A) ← (AL) ^ d8  
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –  
+ + R –  
+ + R –  
+ + R –  
64  
65  
67  
66  
AND A, dir  
(A) ← (AL) ^ (dir)  
(A) ← (AL) ^ ((EP))  
(A) ← (AL) ^ ((IX)+off)  
AND A, @EP  
AND A, @IX+off  
50  
AND A, Ri  
2
1
(A) ← (AL) ^ (Ri)  
–
–
–
+ + R –  
68 to 6F  
51  
52  
53  
54  
55  
OR A  
1
2
3
2
3
1
2
2
1
2
(A) ← (AL) ∨ (TL)  
(A) ← (AL) ∨ d8  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
72  
74  
75  
77  
76  
OR A, #d8  
OR A, dir  
OR A,@EP  
OR A, @IX,off  
(A) ← (AL) ∨ (dir)  
(A) ← (AL) ∨ ((EP))  
(A) ← (AL) ∨ ((IX)+off)  
56  
57  
58  
59  
OR A, Ri  
2
4
3
4
1
3
2
3
(A) ← (AL) ∨ (Ri)  
(dir) - d8  
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –  
+ + + +  
+ + + +  
+ + + +  
78 to 7F  
95  
CMP dir, #d8  
CMP @EP, #d8  
((EP))- d8  
97  
CMP @IX+off,  
#d8  
((IX)+off) - d8  
96  
60  
61  
62  
CMP Ri, #d8  
INCW SP  
3
1
1
2
1
1
(Ri) - d8  
–
–
–
–
–
–
–
–
–
– – – –  
– – – –  
– – – –  
98 to 9F  
C1  
(SP) ← (SP) + 1  
(SP) ← (SP) - 1  
DECW SP  
D1  
230  
APPENDIX A Instruction List  
Table A.2-3 Operation List (for Branch Instructions)  
No  
MNEMONIC  
~
#
OPERATION  
TL TH AH  
NZVC  
OP CODE  
BZ/BEQ rel  
BNZ/BNE rel  
BC/BLO rel  
BNC/BHS rel  
BN rel  
(divergence)  
(no divergence)  
1
4
2
2
if Z=1 then PC ← PC+rel  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –  
FD  
(divergence)  
(no divergence)  
2
3
4
5
4
2
2
2
2
2
if Z=0 then PC ← PC+rel  
if C=1 then PC ← PC+rel  
if C=0 then PC ← PC+rel  
if N=1 then PC ← PC+rel  
– – – –  
– – – –  
– – – –  
– – – –  
FC  
F9  
F8  
FB  
(divergence)  
(no divergence)  
4
2
(divergence)  
(no divergence)  
4
2
(divergence)  
(no divergence)  
4
2
BP rel  
(divergence)  
(no divergence)  
6
4
2
2
2
2
3
3
if N=0 then PC ← PC+rel  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –  
– – – –  
– – – –  
– + – –  
– + – –  
FA  
BLT rel  
(divergence)  
(no divergence)  
7
4
2
if V ∀ N=1 then  
PC ← PC+rel  
FF  
BGE rel  
(divergence)  
(no divergence)  
8
4
2
if V ∀ N=0 then  
PC ← PC+rel  
FE  
BBC dir:b, rel  
BBS dir:b, rel  
9
5
if (dir:b)=0 then  
PC ← PC+rel  
B0 to B7  
B8 to BF  
10  
5
if (dir:b)=1 then  
PC ← PC+rel  
JMP @A  
11  
12  
13  
14  
15  
3
4
7
6
3
1
3
1
3
1
(PC) ← (A)  
(PC) ← ext  
vector call  
–
–
–
–
–
–
–
–
–
–
–
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
E0  
JMP ext  
–
21  
CALLV #vct  
CALL ext  
XCHW A, PC  
–
E8 to EF  
31  
subroutine call  
–
(PC) ← (A),  
(A) ← (PC)+1  
dH  
F4  
RET  
16  
17  
6
8
1
1
return from subroutine  
return from interrupt  
–
–
–
–
–
–
– – – –  
20  
30  
RETI  
restore  
231  
 
APPENDIX  
Table A.2-4 Operation List (for Other Instructions)  
No  
MNEMONIC  
~
#
OPERATION  
TL  
TH AH  
N Z V C  
OP CODE  
1
PUSHW A  
POPW A  
4
3
1
1
(SP) ← (SP)-2, ((SP)) ← (A)  
–
–
–
–
– – – –  
– – – –  
40  
50  
2
3
4
5
(A) ← ((SP)),  
(SP ) ← (SP)+2  
–
–
–
–
dH  
PUSHW IX  
POPW IX  
NOP  
4
3
1
1
1
1
(SP) ← (SP)-2,  
((SP)) ← (IX)  
–
–
–
–
–
–
– – – –  
– – – –  
– – – –  
41  
51  
00  
(IX) ← ((SP)),  
(SP) ← (SP)+2  
No operation  
6
7
8
9
CLRC  
SETC  
CLRI  
SETI  
1
1
1
1
1
1
1
1
(C) ← 0  
(C) ← 1  
(I) ← 0  
(I) ← 1  
–
–
–
–
–
–
–
–
–
–
–
–
– – – R  
– – – S  
– – – –  
– – – –  
81  
91  
80  
90  
232  
 
APPENDIX A Instruction List  
A.3 Flag Change Table  
Table A.3-1 is the flag change table for transfer instructions. Table A.3-2 is the flag  
change table for operation instructions. Table A.3-3 is the flag change table for branch  
instructions. Table A.3-4 is the flag change table for other instructions.  
■ Flag Change Table  
Table A.3-1 Flag Change Table (for Transfer Instructions) (1/2)  
Instruction  
MOV dir, A  
Flag change  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
MOV @IX+off, A  
MOV ext, A  
MOV @EP, A  
MOV Ri, A  
MOV , #d8  
N: Set to 1 if the transferred data is negative and set to 0 in other cases.  
Z: Set to 1 if the transferred data is 0 and set to 0 in other cases  
V: Not changed  
MOV A, dir  
MOV A, @IX+off  
MOV A, ext  
C: Not changed  
MOV A, @A  
MOV A, @EP  
MOV A, Ri  
MOV dir, #d8  
MOV @IX+off, #d8  
MOV @EP, #d8  
MOV Ri, #d8  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
MOVW dir, A  
MOVW @IX+off, A  
MOVW ext, A  
MOVW @EP, A  
MOVW A, #d16  
MOVW A, dir  
MOVW A, @IX+off  
MOVW A, ext  
MOVW A, @A  
MOVW A, @EP  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
N: Set to 1 if the transferred data is negative and set to 0 in other cases.  
Z: Set to 1 if the transferred data is 0 and set to 0 in other cases  
V: Not changed  
C: Not changed  
233  
     
APPENDIX  
Table A.3-1 Flag Change Table (for Transfer Instructions) (2/2)  
Instruction  
MOVW A, EP  
Flag change  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
MOVW EP, #d16  
MOVW IX, A  
MOVW A, IX  
MOVW SP, A  
MOVW A, SP  
MOVW SP, #d16  
MOV @A, T  
N: Not changed  
MOVW @A, T  
Z: Not changed  
V: Not changed  
C: Not changed  
MOVW IX, #d16  
MOVW A, PS  
MOVW A, PC  
JMP @A  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
MOVW PS, A  
N: Set to 1 if bit 3 of A is 1 and set to 0 if 0.  
Z: Set to 1 if bit 2 of A is 1 and set to 0 if 0.  
V: Set to 1 if bit 1 of A is 1 and set to 0 if 0.  
C: Set to 1 if bit 0 of A is 1 and set to 0 if 0.  
N: Not changed  
SETB dir:b  
CLRB dir:b  
Z: Not changed  
V: Not changed  
C: Not changed  
SWAP  
N: Not changed  
XCH A, T  
Z: Not changed  
V: Not changed  
C: Not changed  
XCHW A, T  
XCHW A, EP  
XCHW A, IX  
XCHW A, SP  
XCHW A, PC  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
234  
APPENDIX A Instruction List  
Table A.3-2 Flag Change Table (for Operation Instructions) (1/3)  
Instruction  
ADDC A, Ri  
Flag change  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
ADDC A, #d8  
ADDC A, dir  
ADDC A, @IX+off  
ADDC A, @EP  
ADDC A  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a carry occurs and set to 0 in other cases.  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a carry occurs and set to 0 in other cases.  
ADDCW A  
SUBC A, Ri  
SUBC A, #d8  
SUBC A, dir  
SUBC A, @IX+off  
SUBC A, @EP  
SUBC A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a borrow occurs and set to 0 in other cases.  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a borrow occurs and set to 0 in other cases.  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Not changed  
SUBCW A  
INC Ri  
INCW EP  
INCW IX  
INCW SP  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
INCW A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Not changed  
C: Not changed  
DEC Ri  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Not changed  
235  
 
APPENDIX  
Table A.3-2 Flag Change Table (for Operation Instructions) (2/3)  
Instruction  
DECW EP  
Flag change  
N: Not changed  
DECW IX  
DECW SP  
Z: Not changed  
V: Not changed  
C: Not changed  
DECW A  
MULU A  
DIVU A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Not changed  
C: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
N: Not changed  
Z: Set to 1 if A before operation is 0000 and set to 0 in other cases.  
H
V: Not changed  
C: Not changed  
ANDW A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Always Set to 0  
C: Not changed  
AND A, #d8  
AND A, dir  
AND A, @EP  
AND A, @IX+off  
AND A, Ri  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Always set to 0  
C: Not changed  
ORW A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Always set to 0  
C: Not changed  
OR A, #d8  
OR A, dir  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Always set to 0  
OR A, @EP  
OR A, @IX+off  
OR A, Ri  
C: Not changed  
236  
APPENDIX A Instruction List  
Table A.3-2 Flag Change Table (for Operation Instructions) (3/3)  
Instruction  
XORW A  
Flag change  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Always set to 0  
C: Not changed  
XOR A, #d8  
XOR A, dir  
XOR A, @EP  
XOR A, @IX+off  
XOR A, Ri  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Always set to 0  
C: Not changed  
CMP A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a borrow occurs and set to 0 in other cases.  
CMPW A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a borrow occurs and set to 0 in other cases.  
CMP A, #d8  
CMP A, dir  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a borrow occurs and set to 0 in other cases.  
CMP A, @EP  
CMP A, @IX+off  
CMP A, Ri  
CMP dir, #d8  
CMP @EP #d8  
CMP @IX+off, #d8  
CMP Ri, #d8  
RORC A  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a borrow occurs and set to 0 in other cases.  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Not changed  
ROLC A  
C: Enter bit 0 (when RORA) or bit 7 (when ROLA) of A before the operation.  
N: Set to 1 if the result of operation is negative and set to 0 in other cases.  
Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.  
V: Set to 1 if an overflow occurs and set to 0 in other cases.  
C: Set to 1 if a carry (borrow) occurs and set to 0 in other cases.  
DAA  
DAS  
237  
APPENDIX  
Table A.3-3 Flag Change Table (for Branch Instructions)  
Instruction  
Flag change  
BZ rel/BEQ rel  
BNZ rel/BNE rel  
BC rel/BLO rel  
BNC rel/BHS rel  
BN rel  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
BP rel  
BLT rel  
BGE rel  
JMP addr16  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
N: Not changed  
BBC dir:b, rel  
BBS dir:b, rel  
Z: Set to 1 if bit b is 0 and set to 0 if 1.  
V: Not changed  
C: Not changed  
CALL addr16  
CALLV #vct  
RET  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
RETI  
N: N value of saved CCR is entered.  
Z: Z value of saved CCR is entered.  
V: V value of saved CCR is entered.  
C: C value of saved CCR is entered.  
238  
 
APPENDIX A Instruction List  
Table A.3-4 Flag Change Table (for Other Instructions)  
Instruction  
Flag change  
PUSHW A  
PUSHW IX  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Become to 0  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Become to 1  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
I: Become to 0  
N: Not changed  
Z: Not changed  
V: Not changed  
C: Not changed  
I: Become to 1  
POPW A  
POPW IX  
NOP  
CLRC  
SETC  
CLRI  
SETI  
239  
 
APPENDIX  
APPENDIX B Bus Operation List  
Table B-1 is a bus operation list.  
■ Bus Operation List  
Table B-1 Bus Operation List (1/11)  
CODE  
MNEMONIC  
NOP  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
00  
80  
90  
81  
91  
10  
12  
22  
32  
42  
52  
62  
72  
13  
23  
33  
43  
53  
63  
73  
04  
1
1
The following  
1
0
0
following instruction  
CLRI  
SETI  
CLRC  
SETC  
SWAP  
1
1
N +2  
The following  
following instruction  
1
0
0
CMP A  
ADDC A  
SUBC A  
XCH A, T  
XOR A  
AND A  
OR  
A
CMPW A  
ADDCW A  
SUBCW A  
XCHW A, T  
XORW A  
ANDW A  
1
1
N +2  
The following  
following instruction  
1
0
0
ORW  
A
MOV A, #d8  
2
1
2
N +2  
N +3  
The following  
instruction  
1
1
0
0
0
0
14  
24  
34  
54  
64  
74  
CMP A, #d8  
ADDC A, #d8  
SUBC A, #d8  
XOR A, #d8  
AND A, #d8  
OR A, #d8  
The following  
following instruction  
240  
     
APPENDIX B Bus Operation List  
Table B-1 Bus Operation List (2/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
05  
MOV A, dir  
3
1
The following  
instruction  
1
0
0
15  
25  
35  
55  
65  
75  
45  
CMP A, dir  
ADDC A, dir  
SUBC A, dir  
XOR A, dir  
AND A, dir  
OR A, dir  
MOV dir, A  
2
3
dir address  
N +3  
Data  
1
1
0
0
0
0
The following  
following instruction  
3
3
1
N +2  
The following  
instruction  
1
0
0
2
3
dir address  
N +3  
Data  
0
1
1
0
0
0
The following  
following instruction  
06  
16  
26  
MOV A, @IX+off  
CMP A, @IX+off  
ADDC A, @IX+off  
1
2
3
N +2  
N +3  
The following  
instruction  
1
1
1
0
0
0
0
0
0
The following  
following instruction  
(IX)+off  
address  
Data  
36  
56  
66  
76  
46  
SUBC A, @IX+off  
XOR A, @IX+off  
AND A, @IX+off  
OR A, @IX+off  
MOV @IX+off, A  
3
2
1
2
N +2  
N +3  
The following  
instruction  
1
1
0
0
0
0
The following  
following instruction  
3
1
(IX)+off address  
N +2  
Data  
0
1
1
0
0
0
07  
MOV A, @EP  
The following  
following instruction  
17  
27  
37  
57  
67  
77  
47  
CMP A, @EP  
ADDC A, @EP  
SUBC A, @EP  
XOR A, @EP  
AND A, @EP  
OR A, @EP  
MOV @EP, A  
2
(EP) address  
Data  
1
0
0
2
1
2
N +2  
The following  
following instruction  
1
0
0
1
0
0
(EP) address  
Data  
241  
APPENDIX  
Table B-1 Bus Operation List (3/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
08 - 0F  
MOV A, Ri  
2
1
The following  
1
0
0
following instruction  
18 - 1F  
28 - 2F  
38 - 3F  
58 - 5F  
68 - 6F  
78 - 7F  
48 - 4F  
CMP A, Ri  
ADDC A, Ri  
SUBC A, Ri  
XOR A, Ri  
AND A, Ri  
OR A, Ri  
MOV Ri, A  
2
Rn address  
Data  
1
0
0
2
1
1
N +2  
The following  
following instruction  
1
0
0
2
1
Rn address  
N +2  
Data  
0
1
1
0
0
0
C0  
D0  
C1  
D1  
C2  
D2  
C3  
D3  
F0  
INCW A  
The following  
following instruction  
DECW A  
INCW SP  
DECW SP  
INCW IX  
DECW IX  
INCW EP  
DECW EP  
MOVW A, PC  
2
1
1
N +2  
The following  
following instruction  
1
0
0
2
1
−
−
0
1
0
0
0
0
E1  
F1  
E2  
F2  
E3  
F3  
E0  
MOVW SP, A  
MOVW A, SP  
MOVW IX, A  
MOVW A, IX  
MOVW EP, A  
MOVW A, EP  
JMP @A  
N +2  
The following  
following instruction  
3
1
1
2
N +2  
Data of N +2  
1
1
0
0
0
0
Address divergence  
The following  
instruction  
3
1
Address divergence  
+1  
The following  
following instruction  
1
1
0
0
0
0
F5  
F6  
F7  
XCHW A, SP  
XCHW A, IX  
XCHW A, EP  
N +2  
The following  
following instruction  
242  
APPENDIX B Bus Operation List  
Table B-1 Bus Operation List (4/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
F4  
XCHW A, PC  
3
1
2
Data of N +2  
1
1
0
0
0
0
Address divergence  
The following  
instruction  
3
1
Address divergence  
+1  
The following  
following instruction  
1
1
0
0
0
1
A0 - A7 CLRB dir:n  
A8 - AF SETB dir:n  
4
N +2  
The following  
instruction  
2
3
4
dir address  
dir address  
N +3  
Data  
Data  
1
0
1
0
1
0
1
0
0
The following  
following instruction  
B0 - B7 BBC dir:n, rel  
B8 - BF BBS dir:n, rel  
Divergence  
5
1
N +2  
rel  
1
1
1
1
0
0
0
0
0
0
0
0
2
3
4
dir address  
N +3  
Data  
Data of N+3  
Address divergence  
The following  
instruction  
5
Address divergence  
+1  
The following  
following instruction  
1
0
0
No divergence  
5
1
2
3
N +2  
rel  
1
1
1
0
0
0
0
0
0
dir address  
N +3  
Data  
The following  
instruction  
4
5
−
−
0
1
0
0
0
0
N +4  
The following  
following instruction  
60  
61  
MOV A, ext  
4
4
1
2
N +2  
N +3  
ext (L byte)  
1
1
0
0
0
0
The following  
instruction  
3
4
ext address  
N +4  
Data  
1
1
0
0
0
0
The following  
following instruction  
MOV ext, A  
1
2
N +2  
N +3  
ext (L byte)  
1
1
0
0
0
0
The following  
instruction  
3
4
ext address  
N +4  
Data  
0
1
1
0
0
0
The following  
following instruction  
243  
APPENDIX  
Table B-1 Bus Operation List (5/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
ext (L byte)  
RD WR RMW  
C4  
MOVW A, ext  
5
1
2
1
1
0
0
0
0
N +3  
The following  
instruction  
3
4
5
ext address  
ext+1 address  
N +4  
Data (H byte)  
Data (L byte)  
1
1
1
0
0
0
0
0
0
The following  
following instruction  
D4  
MOVW ext, A  
5
1
2
N +2  
N +3  
ext (L byte)  
1
1
0
0
0
0
The following  
instruction  
3
4
5
ext address  
ext+1 address  
N +4  
Data (H byte)  
Data (L byte)  
0
0
1
1
1
0
0
0
0
The following  
following instruction  
C5  
D5  
C6  
D6  
MOVW A, dir  
4
4
4
4
1
N +2  
The following  
instruction  
1
0
0
2
3
4
dir address  
dir+1 address  
N +3  
Data (H byte)  
Data (L byte)  
1
1
1
0
0
0
0
0
0
The following  
following instruction  
MOVW dir, A  
1
N +2  
The following  
instruction  
1
0
0
2
3
4
dir address  
dir+1 address  
N +3  
Data (H byte)  
Data (L byte)  
0
0
1
1
1
0
0
0
0
The following  
following instruction  
MOVW A,  
@IX+off  
1
2
N +2  
N +3  
The following  
instruction  
1
1
0
0
0
0
The following  
following instruction  
3
4
1
(IX)+off address  
(IX)+off+1 address  
N +2  
Data (H byte)  
Data (L byte)  
1
1
1
0
0
0
0
0
0
MOVW @IX+off,  
A
The following  
instruction  
2
N +3  
The following  
1
0
0
following instruction  
3
4
(IX)+off address  
Data (H byte)  
Data (L byte)  
0
0
1
1
0
0
(IX)+off+1 address  
244  
APPENDIX B Bus Operation List  
Table B-1 Bus Operation List (6/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
C7  
MOVW A, @EP  
3
1
The following  
1
0
0
following instruction  
2
3
1
(EP) address  
(EP)+1 address  
N +2  
Data(H byte)  
Data(L byte)  
1
1
1
0
0
0
0
0
0
D7  
85  
MOVW @EP, A  
MOV dir, #d8  
3
4
The following  
following instruction  
2
3
1
2
3
(EP) address  
(EP)+1 address  
N +2  
Data(H byte)  
Data(L byte)  
#d8  
0
0
1
0
1
1
1
0
1
0
0
0
0
0
0
dir address  
N +3  
Data  
The following  
instruction  
4
N +4  
The following  
1
0
0
following instruction  
95  
86  
CMP dir, #d8  
4
4
1
2
3
N +2  
#d8  
1
1
1
0
0
0
0
0
0
dir address  
N +3  
Data  
The following  
instruction  
MOV @IX+off,  
#d8  
1
2
N +2  
N +3  
#d8  
1
1
0
0
0
0
The following  
instruction  
3
4
(IX)+off address  
N +4  
Data  
0
1
1
0
0
0
The following  
following instruction  
96  
CMP @IX+off, #d8  
4
1
2
N +2  
N +3  
#d8  
1
1
0
0
0
0
The following  
instruction  
3
4
(IX)+off address  
N +4  
Data  
1
1
0
0
0
0
The following  
following instruction  
245  
APPENDIX  
Table B-1 Bus Operation List (7/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
87  
MOV @EP, #d8  
3
1
The following  
instruction  
1
0
0
2
3
(EP) address  
N +3  
Data  
0
1
1
0
0
0
The following  
following instruction  
97  
CMP @EP, #d8  
MOV Ri, #d8  
CMP Ri, #d8  
3
3
3
1
N +2  
The following  
instruction  
1
0
0
2
3
(EP) address  
N +3  
Data  
1
1
0
0
0
0
The following  
following instruction  
88 - 8F  
98 - 9F  
1
N +2  
The following  
instruction  
1
0
0
2
3
Rn address  
N +3  
Data  
0
1
1
0
0
0
The following  
following instruction  
1
N +2  
The following  
instruction  
1
0
0
2
3
Rn address  
N +3  
Data  
1
1
0
0
0
0
The following  
following instruction  
82  
92  
83  
MOV @A, T  
MOV A, @A  
MOVW @A, T  
2
2
3
1
N +2  
The following  
following instruction  
1
0
0
2
1
(A) address  
N +2  
Data  
0
1
1
0
0
0
The following  
following instruction  
2
1
(A) address  
N +2  
Data  
1
1
0
0
0
0
The following  
following instruction  
2
3
(A) address  
Data (H byte)  
Data (L byte)  
0
0
1
1
0
0
(A) +1 address  
246  
APPENDIX B Bus Operation List  
Table B-1 Bus Operation List (8/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
93  
MOVW A, @A  
3
1
The following  
1
0
0
following instruction  
2
3
1
2
(A) address  
(A) +1 address  
N +2  
Data (H byte)  
Data (L byte)  
Data (L byte)  
1
1
1
1
0
0
0
0
0
0
0
0
E4  
E5  
MOVW A, #d16  
MOVW SP, #d16  
3
1
N +3  
The following  
instruction  
E6  
MOVW IX, #d16  
3
1
N +4  
N +2  
The following  
following instruction  
1
1
0
0
0
0
E7  
84  
MOVW EP, #d16  
DAA  
The following  
following instruction  
94  
02  
03  
70  
71  
DAS  
ROLC A  
RORC A  
MOVW A, PS  
MOVW PS, A  
C8 - CF INC Ri  
3
7
1
N +2  
The following  
following instruction  
1
0
1
D8 - DF DEC Ri  
2
3
1
2
3
4
5
6
Rn address  
Rn address  
N +2  
Data  
1
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
Data  
E8 - EF CALLV #n  
Data of N +2  
Vector (H)  
Vector (L)  
Vector address  
Vector address +1  
SP -1  
Return address (L)  
Return address (H)  
SP -2  
Address divergence  
ahead  
The following  
instruction  
7
Address divergence  
ahead +1  
The following  
following instruction  
1
0
0
247  
APPENDIX  
Table B-1 Bus Operation List (9/11)  
CODE  
MNEMONIC  
BNC rel  
~
Cycle  
Address bus  
Data bus  
RD WR RMW  
F8  
F9  
FA  
FB  
Divergence  
BC rel  
BP rel  
BN rel  
4
1
2
3
N +2  
Data of N +2  
Data of N +3  
1
1
1
0
0
0
0
0
0
N +3  
Address divergence  
ahead  
The following  
instruction  
FC  
BNZ rel  
4
Address divergence  
ahead +1  
The following  
following instruction  
1
0
0
FD  
FE  
BZ rel  
No divergence  
BGE rel  
2
1
2
1
N +2  
N +3  
N +2  
The following  
instruction  
1
1
1
0
0
0
0
0
0
FF  
40  
41  
BLT rel  
The following  
following instruction  
PUSHW A  
PUSHW IX  
4
The following  
following instruction  
2
3
4
1
−
−
0
0
0
1
0
1
1
0
0
0
0
0
SP -1  
SP -2  
N +2  
Save data (L)  
Save data (H)  
50  
51  
POPW A  
POPW IX  
3
6
The following  
following instruction  
2
3
1
2
3
4
5
SP  
Return data (H)  
Return data (L)  
Data of N +2  
Return address (H)  
Return address (L)  
−
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SP +1  
20  
RET  
N +2  
SP  
SP +1  
−
Return address  
The following  
instruction  
6
Return address +1  
The following  
1
0
0
following instruction  
30  
RETI  
8
1
2
3
4
5
6
7
N +2  
Data of N +2  
PSH (RP, DP)  
PSL (CCR)  
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SP  
SP +1  
SP +2  
SP +3  
−
Return address (H)  
Return address (L)  
−
Return address  
The following  
instruction  
8
Return address +1  
The following  
1
0
0
following instruction  
248  
APPENDIX B Bus Operation List  
Table B-1 Bus Operation List (10/11)  
CODE  
MNEMONIC  
CALL ext  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
31  
6
1
Address divergence  
ahead (L)  
1
0
0
2
3
4
5
−
−
0
0
0
1
0
1
1
0
0
0
0
0
SP -1  
SP -2  
Return address (L)  
Return address (H)  
Address divergence  
ahead  
The following  
instruction  
6
1
Address divergence  
ahead +1  
The following  
following instruction  
1
1
0
0
0
0
21  
JMP ext  
4
N +2  
Address divergence  
ahead (L)  
2
3
−
−
0
1
0
0
0
0
Address divergence  
ahead  
The following  
instruction  
4
1
Address divergence  
ahead +1  
The following  
following instruction  
1
1
0
0
0
0
0
0
0
01  
11  
−
MULU A  
DIVU A  
RESET  
8
17  
7
N +2  
The following  
following instruction  
2
to  
8
−
−
−
−
0
1
0
0
0
0
1
N +2  
The following  
following instruction  
2
to  
17  
1
−
−
0
0
0
−
−
−
0
0
1
0
0
0
0
0
0
−
2
0FFFD  
Mode data  
H
H
H
3
4
0FFFE  
Reset vector (H)  
Reset vector (L)  
−
1
1
0
0
0
0
0FFFF  
5
6
−
0
1
0
0
0
0
Start address  
The following  
instruction  
7
Start address +1  
The following  
1
0
0
following instruction  
249  
APPENDIX  
Table B-1 Bus Operation List (11/11)  
CODE  
MNEMONIC  
~
Cycle  
Address bus  
N +2  
Data bus  
RD WR RMW  
−
INTERRUPT  
9
1
2
3
4
5
6
7
8
Data of N +2  
Vector (H)  
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
Vector address  
Vector address +1  
SP -1  
Vector (L)  
Return address (L)  
Return address (H)  
PSL (CCR)  
SP -2  
SP -3  
SP -4  
PSH (RP, DP)  
Address divergence  
ahead  
The following  
instruction  
9
Address divergence  
ahead +1  
The following  
following instruction  
1
0
0
-: Invalid bus cycle  
N: Address where instruction under execution is stored  
Note:  
The cycle of the instruction might be extended by the immediately preceding instruction by one cycle.  
Moreover, cycle of the instruction number might be extended in the access to the IO area.  
250  
APPENDIX C Instruction Map  
APPENDIX C Instruction Map  
Table C-1 is an instruction map.  
■ Instruction Map  
Table C-1 Instruction Map  
251  
   
APPENDIX  
252  
INDEX  
INDEX  
The index follows on the next page.  
This is listed in alphabetic order.  
253  
 
INDEX  
Index  
Symbols  
A
#imm  
A
Immediate Addressing (#imm) ............................41  
Accumulator (A)................................................ 18  
Example of Operation of Accumulator (A) and  
Temporary Accumulator (T) in Byte Data  
#k  
Vector Addressing (#k).......................................42  
@EP  
Pointer Addressing (@EP) ..................................41  
@IX+off  
Index Addressing (@IX+off)...............................41  
Processing............................................ 21  
Accumulator  
Accumulator (A)................................................ 18  
Example of Operation of Accumulator (A) and  
Temporary Accumulator (T) in Byte Data  
Processing............................................ 21  
Numerics  
ADDC  
16-bit Data  
ADDC (ADD Byte Data of Accumulator and Memory  
with Carry to Accumulator) ................... 50  
ADDC (ADD Byte Data of Accumulator and  
Temporary Accumulator with Carry to  
Arrangement of 16-bit Data in Memory Space ......13  
Accumulator) ....................................... 48  
ADDCW  
ADDCW (ADD Word Data of Accumulator and  
Temporary Accumulator with Carry to  
Accumulator) ....................................... 52  
Addressing  
Memory Space and Addressing ............................. 7  
AND  
AND (AND Byte Data of Accumulator and Memory  
to Accumulator).................................... 56  
AND (AND Byte Data of Accumulator and  
Temporary Accumulator to Accumulator)  
........................................................... 54  
ANDW  
ANDW (AND Word Data of Accumulator and  
Temporary Accumulator to Accumulator)  
........................................................... 58  
B
BBC  
BBC (Branch if Bit is Clear) ............................... 60  
BBS  
BBS (Branch if Bit is Set)................................... 62  
BC  
BC (Branch relative if C=1)/BLO (Branch if LOwer)  
........................................................... 64  
BEQ  
BZ (Branch relative if Z=1)/BEQ (Branch if Equal)  
........................................................... 78  
BGE  
BGE (Branch Great or Equal: relative if larger than or  
equal to Zero) ....................................... 66  
254  
INDEX  
BHS  
BNC (Branch relative if C=0)/BHS (Branch if Higher  
or Same) .............................................. 74  
Bit Direct Addressing  
Bit Direct Addressing (dir:b)............................... 40  
BLO  
CMPW  
CMPW (CoMPare Word Data of Accumulator and  
Temporary Accumulator) .......................96  
CPU  
2
Configuration Example of Device Using F MC-8FX  
CPU .......................................................3  
2
F MC-8FX CPU Features......................................2  
BC (Branch relative if C=1)/BLO (Branch if LOwer)  
2
F MC-8FX CPU Instruction Overview ...............223  
............................................................ 64  
2
Outline of F MC-8FX CPU ...................................2  
BLT  
BLT (Branch Less Than zero: relative if < Zero)  
D
............................................................ 68  
BN  
DAA  
DAA (Decimal Adjust for Addition).....................98  
DAS  
DAS (Decimal Adjust for Subtraction) ...............100  
DEC  
DEC (DECrement Byte Data of General-purpose  
Register).............................................102  
BN (Branch relative if N=1)................................ 70  
BNC  
BNC (Branch relative if C=0)/BHS (Branch if Higher  
or Same) .............................................. 74  
BNE  
BNZ (Branch relative if Z=0)/BNE (Branch if Not  
Equal).................................................. 72  
DECW  
BNZ  
DECW (DECrement Word Data of Accumulator)  
..........................................................104  
DECW (DECrement Word Data of Extra Pointer)  
..........................................................106  
DECW (DECrement Word Data of Index Pointer)  
..........................................................108  
DECW (DECrement Word Data of Stack Pointer)  
..........................................................110  
BNZ (Branch relative if Z=0)/BNE (Branch if Not  
Equal).................................................. 72  
BP  
BP (Branch relative if N=0: PLUS)...................... 76  
Bus Operation  
Bus Operation List ........................................... 240  
Byte Data Processing  
Dedicated Register  
Example of Operation of Accumulator (A) and  
Temporary Accumulator (T) in Byte Data  
Processing............................................ 21  
2
F MC-8FX Dedicated Registers...........................16  
dir  
Direct Addressing (dir)........................................40  
BZ  
BZ (Branch relative if Z=1)/BEQ (Branch if Equal)  
............................................................ 78  
dir:b  
Bit Direct Addressing (dir:b) ...............................40  
Direct Addressing  
C
Direct Addressing (dir)........................................40  
Direct Area  
CALL  
Direct Area ........................................................10  
CALL (CALL subroutine) .................................. 80  
Direct Bank  
CALLV  
Direct Bank........................................................28  
CALLV #k ........................................................ 45  
CALLV (CALL Vectored subroutine).................. 82  
Direct Bank Pointer  
Access to Register Bank Pointer and Direct Bank  
Pointer..................................................25  
CLRB  
CLRB (Clear direct Memory Bit) ........................ 84  
Direct Data Transfer  
CLRC  
Direct Data Transfer from Temporary Accumulator  
(T)........................................................22  
CLRC (Clear Carry flag) .................................... 86  
CLRI  
DIVU  
CLRI (CLeaR Interrupt flag)............................... 88  
DIVU (DIVide Unsigned) .................................112  
DIVU A.............................................................44  
CMP  
CMP (CoMPare Byte Data of Accumulator and  
Memory).............................................. 92  
CMP (CoMPare Byte Data of Accumulator and  
Temporary Accumulator)....................... 90  
CMP (CoMPare Byte Data of Immediate Data and  
Memory).............................................. 94  
E
EP  
Extra Pointer (EP)...............................................26  
255  
INDEX  
ext  
Interrupt Enable/Disable Functions...................... 32  
Interrupt Requests in Resources........................... 32  
Multiple Interrupt............................................... 36  
Outline of Interrupt Operation............................. 30  
Reset and Interrupt Vector Table ......................... 11  
Extended Addressing (ext) ..................................40  
Extended Addressing  
Extended Addressing (ext) ..................................40  
Extra Pointer  
Item  
Extra Pointer (EP) ..............................................26  
Item in Instruction Table................................... 225  
IX  
F
Index Register (IX) ............................................ 26  
Flag  
Program Status (PS) Flags...................................24  
J
Flag Change  
JMP  
JMP (JuMP to address pointed by Accumulator)  
Flag Change Table ...........................................233  
......................................................... 124  
JMP (JuMP to effective Address) ...................... 126  
JMP @A........................................................... 43  
G
General-Purpose Register  
2
F MC-8FX General-Purpose Registers.................16  
General-Purpose Register Addressing  
M
General-Purpose Register Addressing (Ri)............41  
Memory Space  
Arrangement of 16-bit Data in Memory Space...... 13  
General-Purpose Register Bank Area  
General-Purpose Register Bank Area .....................9  
CPU Memory Space............................................. 6  
Memory Space and Addressing ............................. 7  
I
MOV  
Immediate Addressing  
MOV (MOVE Byte Data from Accumulator to  
memory) ............................................ 134  
MOV (MOVE Byte Data from Memory to  
Accumulator) ..................................... 130  
MOV (MOVE Byte Data from Temporary  
Accumulator to Address Pointed by  
Accumulator) ..................................... 128  
MOV (MOVE Immediate Byte Data to Memory)  
......................................................... 132  
Immediate Addressing (#imm) ............................41  
INC  
INC (INCrement Byte Data of General-purpose  
Register).............................................114  
INCW  
INCW (INCrement Word Data of Accumulator)  
..........................................................116  
INCW (INCrement Word Data of Extra Pointer)  
..........................................................118  
INCW (INCrement Word Data of Index Register)  
..........................................................120  
INCW (INCrement Word Data of Stack Pointer)  
..........................................................122  
MOVW  
MOVW (MOVE Immediate Word Data to Extra  
Pointer).............................................. 154  
MOVW (MOVE Immediate Word Data to Index  
Register) ............................................ 158  
MOVW (MOVE Immediate Word Data to Stack  
Pointer).............................................. 162  
MOVW (MOVE Word Data from Accumulator to  
Extra Pointer) ..................................... 152  
MOVW (MOVE Word Data from Accumulator to  
Index Register) ................................... 156  
MOVW (MOVE Word Data from Accumulator to  
Memory)............................................ 150  
MOVW (MOVE Word data from Accumulator to  
Program Status Register) ..................... 160  
MOVW (MOVE Word data from Accumulator to  
Stack Pointer)..................................... 164  
MOVW (MOVE Word Data from Extra Pointer to  
Accumulator) ..................................... 140  
MOVW (MOVE Word Data from Index Register to  
Accumulator) ..................................... 142  
MOVW (MOVE Word Data from Memory to  
Accumulator) ..................................... 138  
Index Addressing  
Index Addressing (@IX+off)...............................41  
Index Register  
Index Register (IX).............................................26  
Inherent Addressing  
Inherent Addressing............................................42  
Instruction  
2
F MC-8FX CPU Instruction Overview...............223  
Instruction List  
Sign of the Instruction List ................................224  
Instruction Map  
Instruction Map................................................251  
Instruction Table  
Item in Instruction Table...................................225  
Interrupt  
Creating an Interrupt Processing Program.............34  
256  
INDEX  
MOVW (MOVE Word Data from Program Counter to  
Accumulator)...................................... 146  
MOVW (MOVE Word Data from Program Status  
Register to Accumulator)..................... 144  
MOVW (MOVE Word Data from Stack Pointer to  
Accumulator)...................................... 148  
MOVW (MOVE Word Data from Temporary  
Accumulator to Address Pointed by  
R
Register Bank  
Register Bank Register........................................27  
Register Bank Pointer  
Access to Register Bank Pointer and Direct Bank  
Pointer..................................................25  
rel  
Relative Addressing (rel).....................................42  
Accumulator)...................................... 136  
MOVW A,PC.................................................... 43  
Relative Addressing  
Relative Addressing (rel).....................................42  
Multiple Interrupt  
Multiple Interrupt............................................... 36  
Reset  
Reset and Interrupt Vector Table..........................11  
Reset Operation..................................................37  
MULU  
MULU (MULtiply Unsigned) ........................... 166  
MULU A .......................................................... 44  
RET  
RET (RETurn from subroutine) .........................180  
N
RETI  
RETI (RETurn from Interrupt)...........................182  
NOP  
Ri  
NOP (NoOPeration) ......................................... 168  
General-Purpose Register Addressing (Ri) ............41  
ROLC  
O
ROLC (Rotate Byte Data of Accumulator with Carry  
to Left) ...............................................184  
Operation  
Operation List.................................................. 226  
RORC  
OR  
RORC (Rotate Byte Data of Accumulator with Carry  
to Right) .............................................186  
OR (OR Byte Data of Accumulator and Memory to  
Accumulator)...................................... 172  
OR (OR Byte Data of Accumulator and Temporary  
Accumulator to Accumulator) .............. 170  
S
SETB  
ORW  
SETB (Set Direct Memory Bit)..........................194  
ORW (OR Word Data of Accumulator and Temporary  
Accumulator to Accumulator) .............. 174  
SETC  
SETC (SET Carry flag) .....................................196  
SETI  
P
SETI (SET Interrupt flag)..................................198  
PC  
Sign  
Program Counter (PC)........................................ 17  
Sign of the Instruction List ................................224  
Pointer Addressing  
SP  
Pointer Addressing (@EP) .................................. 41  
Stack Pointer (SP)...............................................17  
POPW  
Stack Area  
POPW (POP Word Data of Intherent Register from  
Stack Memory) ................................... 178  
Stack Area ...........................................................9  
Stack Pointer  
Program Counter  
Stack Pointer (SP)...............................................17  
Program Counter (PC)........................................ 17  
SUBC  
Program Status  
SUBC (SUBtract Byte Data of Accumulator from  
Temporary Accumulator with Carry to  
Accumulator) ......................................188  
SUBC (SUBtract Byte Data of Memory from  
Accumulator with Carry to Accumulator)  
..........................................................190  
Program Status (PS) Flags .................................. 24  
Structure of Program Status (PS) ......................... 23  
PS  
Program Status (PS) Flags .................................. 24  
Structure of Program Status (PS) ......................... 23  
PUSHW  
SUBCW  
PUSHW (PUSH Word Data of Inherent Register to  
Stack Memory) ................................... 176  
SUBCW (SUBtract Word Data of Accumulator from  
Temporary Accumulator with Carry to  
Accumulator) ......................................192  
257  
INDEX  
SWAP  
Vector Table  
Reset and Interrupt Vector Table ......................... 11  
SWAP (SWAP Byte Data Accumulator ’H’and  
Accumulator ’L’) ................................200  
X
T
XCH  
T
XCH (eXCHange Byte Data Accumulator ’L’and  
Temporary Accumulator ’L’) ............... 202  
Direct Data Transfer from Temporary Accumulator  
(T) .......................................................22  
Example of Operation of Accumulator (A) and  
Temporary Accumulator (T) in Byte Data  
XCHW  
XCHW (eXCHange Word Data Accumulator and  
Extrapointer) ...................................... 204  
Processing ............................................21  
How to Use the Temporary Accumulator (T) ........20  
Temporary Accumulator (T)................................18  
XCHW (eXCHange Word Data Accumulator and  
Index Register) ................................... 206  
XCHW (eXCHange Word Data Accumulator and  
Program Counter) ............................... 208  
Temporary Accumulator  
Direct Data Transfer from Temporary Accumulator  
(T) .......................................................22  
Example of Operation of Accumulator (A) and  
Temporary Accumulator (T) in Byte Data  
Processing ............................................21  
How to Use the Temporary Accumulator (T) ........20  
Temporary Accumulator (T)................................18  
XCHW (eXCHange Word Data Accumulator and  
Stack Pointer)..................................... 210  
XCHW (eXCHange Word Data Accumulator and  
Temporary Accumulator)..................... 212  
XCHW A,PC..................................................... 44  
XOR  
XOR (eXclusive OR Byte Data of Accumulator and  
Memory to Accumulator)..................... 216  
XOR (eXclusive OR Byte Data of Accumulator and  
Temporary Accumulator to Accumulator)  
V
Vector Addressing  
......................................................... 214  
Vector Addressing (#k).......................................42  
XORW  
Vector Call  
XORW (eXclusive OR Word Data of Accumulator  
and Temporary Accumulator to Accmulator)  
......................................................... 218  
Vector Call Instruction Table...............................11  
258  
CM26-00301-2E  
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL  
2
F MC-8FX  
8-BIT MICROCONTROLLER  
PROGRAMMING MANUAL  
February 2008 the second edition  
Published FUJITSU LIMITED Electronic Devices  
Edited  
Strategic Business Development Dept.  

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