-
CMOS 8 BIT SINGLE CHIP MICROCOMPUTER
S1C88650
Technical Manual
S1C88650 Technical Hardware
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2004, All rights reserved.
Configuration of product number
Devices
S1
C
88104
F
0A01
00
Packing specifications
00 : Besides tape & reel
0A : TCP BL
2 directions
0B : Tape & reel BACK
0C: TCP BR
0D: TCP BT
0E : TCP BD
2 directions
2 directions
2 directions
0F : Tape & reel FRONT
0G: TCP BT
0H: TCP BD
0J : TCP SL
0K : TCP SR
4 directions
4 directions
2 directions
2 directions
0L : Tape & reel LEFT
0M: TCP ST
0N: TCP SD
0P : TCP ST
0Q: TCP SD
2 directions
2 directions
4 directions
4 directions
0R: Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 88348 D1
C
1
00
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Ex : EVA board
Px : Peripheral board
Wx: Flash ROM writer for the microcomputer
Xx : ROM writer peripheral board
Cx : C compiler package
Ax : Assembler package
Dx : Utility tool by the model
Qx : Soft simulator
Corresponding model number
88348: for S1C88348
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
CONTENTS
Co nte nts
1
INTRODUCTION .............................................................................................. 1
1.1
1.2
1.3
Features .............................................................................................................................1
Block Diagram ...................................................................................................................2
Pins ....................................................................................................................................3
1.3.1 Pin layout diagram ................................................................................................................... 3
1.3.2 Pin description ......................................................................................................................... 4
1.4
Mask Option.......................................................................................................................5
2
3
POWER SUPPLY............................................................................................... 7
2.1
2.2
Operating Voltage..............................................................................................................7
Internal Power Supply Circuit ...........................................................................................7
CPU AND BUS CONFIGURATION ................................................................ 8
3.1
3.2
CPU ...................................................................................................................................8
Internal Memory ................................................................................................................8
3.2.1 Program ROM .......................................................................................................................... 8
3.2.2 RAM.......................................................................................................................................... 8
3.2.3 I/O memory............................................................................................................................... 8
3.2.4 Display memory........................................................................................................................ 8
3.2.5 Kanji font ROM ........................................................................................................................ 8
3.3
3.4
3.5
Exception Processing Vectors ...........................................................................................9
CC (Customized Condition Flag) ......................................................................................9
Chip Mode..........................................................................................................................9
3.5.1 MCU mode and MPU mode ..................................................................................................... 9
3.5.2 Bus mode ................................................................................................................................. 10
3.5.3 CPU mode ............................................................................................................................... 11
3.6
External Bus......................................................................................................................11
3.6.1 Data bus .................................................................................................................................. 11
3.6.2 Address bus ............................................................................................................................. 12
3.6.3 Read (RD)/write (WR) signals................................................................................................. 12
3.6.4 Chip enable (CE) signal .......................................................................................................... 12
3.6.5 WAIT control ........................................................................................................................... 13
3.6.6 Bus authority release state ...................................................................................................... 14
4
5
INITIAL RESET ............................................................................................... 15
4.1
Initial Reset Factors..........................................................................................................15
4.1.1 RESET terminal ....................................................................................................................... 15
4.1.2 Simultaneous LOW level input at input port terminals K00–K03........................................... 16
4.1.3 Initial reset sequence ............................................................................................................... 16
4.2
Initial Settings After Initial Reset......................................................................................17
PERIPHERAL CIRCUITS AND THEIR OPERATION................................ 18
5.1
5.2
I/O Memory Map ..............................................................................................................18
System Controller and Bus Control ..................................................................................34
5.2.1 Bus mode and CPU mode settings .......................................................................................... 34
5.2.2 Address decoder (CE output) settings ..................................................................................... 34
5.2.3 WAIT state settings .................................................................................................................. 35
5.2.4 Setting the bus authority release request signal...................................................................... 35
5.2.5 Stack page setting .................................................................................................................... 35
5.2.6 Control of system controller.................................................................................................... 36
5.2.7 Programming notes ................................................................................................................. 38
S1C88650 TECHNICAL MANUAL
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CONTENTS
5.3
Watchdog Timer................................................................................................................39
5.3.1 Configuration of watchdog timer ............................................................................................ 39
5.3.2 Interrupt function .................................................................................................................... 39
5.3.3 Control of watchdog timer ...................................................................................................... 40
5.3.4 Programming notes ................................................................................................................. 40
5.4
5.5
Oscillation Circuits ...........................................................................................................41
5.4.1 Configuration of oscillation circuits ....................................................................................... 41
5.4.2 Mask option ............................................................................................................................. 41
5.4.3 OSC1 oscillation circuit .......................................................................................................... 41
5.4.4 OSC3 oscillation circuit .......................................................................................................... 42
5.4.5 Switching the CPU clocks ....................................................................................................... 42
5.4.6 Control of oscillation circuit ................................................................................................... 43
5.4.7 Programming notes ................................................................................................................. 43
Input Ports (K ports) .........................................................................................................44
5.5.1 Configuration of input ports.................................................................................................... 44
5.5.2 Mask option ............................................................................................................................. 44
5.5.3 Pull-up control ........................................................................................................................ 45
5.5.4 Interrupt function and input comparison register ................................................................... 45
5.5.5 Control of input ports .............................................................................................................. 47
5.5.6 Programming notes ................................................................................................................. 50
5.6
5.7
Output Ports (R ports) ......................................................................................................51
5.6.1 Configuration of output ports.................................................................................................. 51
5.6.2 High impedance control .......................................................................................................... 51
5.6.3 DC output ................................................................................................................................ 51
5.6.4 Control of output ports ............................................................................................................ 52
I/O Ports (P ports) ............................................................................................................54
5.7.1 Configuration of I/O ports....................................................................................................... 54
5.7.2 Mask option ............................................................................................................................. 54
5.7.3 I/O control registers and I/O mode ......................................................................................... 54
5.7.4 Pull-up control ........................................................................................................................ 55
5.7.5 Special output .......................................................................................................................... 55
5.7.6 Control of I/O ports ................................................................................................................. 57
5.7.7 Programming notes ................................................................................................................. 60
5.8
Serial Interface .................................................................................................................61
5.8.1 Configuration of serial interface ............................................................................................. 61
5.8.2 Switching of terminal functions ............................................................................................... 61
5.8.3 Transfer modes ........................................................................................................................ 62
5.8.4 Clock source ............................................................................................................................ 63
5.8.5 Transmit-receive control ......................................................................................................... 64
5.8.6 Operation of clock synchronous transfer ................................................................................ 65
5.8.7 Operation of asynchronous transfer ....................................................................................... 69
5.8.8 Interrupt function .................................................................................................................... 73
5.8.9 Control of serial interface ....................................................................................................... 75
5.8.10 Programming notes ............................................................................................................... 80
5.9
Clock Timer.......................................................................................................................81
5.9.1 Configuration of clock timer ................................................................................................... 81
5.9.2 Interrupt function .................................................................................................................... 81
5.9.3 Control of clock timer ............................................................................................................. 83
5.9.4 Programming notes ................................................................................................................. 85
5.10 Programmable Timer........................................................................................................86
5.10.1 Configuration of programmable timer .................................................................................. 86
5.10.2 Operation mode ..................................................................................................................... 87
5.10.3 Setting of input clock ............................................................................................................. 89
5.10.4 Operation and control of timer ............................................................................................. 89
5.10.5 Interrupt function .................................................................................................................. 91
5.10.6 Setting of TOUT output ......................................................................................................... 93
5.10.7 Transfer rate setting of serial interface................................................................................. 94
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S1C88650 TECHNICAL MANUAL
CONTENTS
5.10.8 Setting frame frequency for LCD driver ............................................................................... 94
5.10.9 Control of programmable timer ............................................................................................ 95
5.10.10 Programming notes ............................................................................................................ 107
5.11 LCD Driver ......................................................................................................................108
5.11.1 Configuration of LCD driver................................................................................................ 108
5.11.2 LCD power supply................................................................................................................ 108
5.11.3 Frame frequency .................................................................................................................. 109
5.11.4 Switching drive duty ............................................................................................................. 109
5.11.5 Display memory.................................................................................................................... 113
5.11.6 Display control ..................................................................................................................... 120
5.11.7 Control of LCD driver .......................................................................................................... 121
5.11.8 Programming notes .............................................................................................................. 123
5.12 Supply Voltage Detection (SVD) Circuit .........................................................................124
5.12.1 Configuration of SVD circuit ............................................................................................... 124
5.12.2 SVD operation ...................................................................................................................... 124
5.12.3 Control of SVD circuit.......................................................................................................... 125
5.12.4 Programming notes .............................................................................................................. 125
5.13 Heavy Load Protection Function.....................................................................................126
5.13.1 Outline of heavy load protection function ............................................................................ 126
5.13.2 Control of heavy load protection function ........................................................................... 126
5.13.3 Programming note................................................................................................................ 126
5.14 Interrupt and Standby Status ...........................................................................................127
5.14.1 Interrupt generation conditions ........................................................................................... 127
5.14.2 Interrupt factor flag .............................................................................................................. 129
5.14.3 Interrupt enable register ...................................................................................................... 130
5.14.4 Interrupt priority register and interrupt priority level ......................................................... 131
5.14.5 Exception processing vectors ............................................................................................... 132
5.14.6 Control of interrupt .............................................................................................................. 133
5.14.7 Programming notes .............................................................................................................. 135
6
SUMMARY OF NOTES .................................................................................. 136
6.1
6.2
Notes for Low Current Consumption ...............................................................................136
Precautions on Mounting.................................................................................................137
7
8
BASIC EXTERNAL WIRING DIAGRAM ..................................................... 139
ELECTRICAL CHARACTERISTICS ............................................................ 140
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Absolute Maximum Rating ...............................................................................................140
Recommended Operating Conditions ..............................................................................140
DC Characteristics ..........................................................................................................141
Analog Circuit Characteristics ........................................................................................142
Power Current Consumption ...........................................................................................143
AC Characteristics...........................................................................................................144
Oscillation Characteristics ..............................................................................................149
Characteristics Curves (reference value) ........................................................................150
9
PACKAGE ........................................................................................................ 159
9.1
9.2
Plastic Package................................................................................................................159
Ceramic Package for Test Samples .................................................................................160
10 PAD LAYOUT .................................................................................................. 161
10.1 Diagram of Pad Layout ...................................................................................................161
10.2 Pad Coordinates ..............................................................................................................162
S1C88650 TECHNICAL MANUAL
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CONTENTS
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL
(Peripheral Circuit Board for S1C88650) ...................................... 163
A.1 Names and Functions of Each Part .................................................................................163
A.2 Precautions ......................................................................................................................165
A.2.1 Precaution for operation ....................................................................................................... 165
A.2.2 Differences from actual IC .................................................................................................... 165
A.3 Connecting to the Target System .....................................................................................168
A.4 Product Specifications .....................................................................................................171
APPENDIX B USING KANJI FONT ..................................................................... 172
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S1C88650 TECHNICAL MANUAL
1 INTRODUCTION
1 INTRODUCTION
The S1C88650 is an 8-bit microcomputer for
portable equipment with an LCD display that has a
built-in LCD controller/ driver and a character
generator (kanji) ROM. This microcomputer
features low-voltage (1.8 V) and high-speed (8.2
MHz) operations as well as low-current
other characters and user-defined characters, this
makes it possible to display kanji characters
without any external kanji font ROM (refer to
Appendix B, "USING KANJI FONT"). This 8-bit
CPU has up to 16MB accessible address space
allowing easy implementation of a large data
processing application.
consumption (2.5 µA during standby).
The LCD controller/ driver contains an LCD drive
power supply circuit and can drive an maximum of
126 × 32-dot LCD panel in low-power consumption.
The S1C88650 has a built-in 11 × 12-dot kanji font
ROM that contains JIS level-1 and level-2 kanji sets,
The S1C88650 is suitable for display modules,
portable CD/ MD, solid audio players, PDA, data
bank and other applications that required an
exclusive LCD driver in conventional systems.
1.1 Features
Table 1.1.1 lists the features of the S1C88650.
Table 1.1.1 Main features
Core CPU
S1C88 (MODEL3) CMOS 8-bit core CPU
Main (OSC3) oscillation circuit Crystal oscillation circuit/ceramic oscillation circuit 8.2 MHz (Max.), or CR oscillation circuit 2.2 MHz (Max.)
Sub (OSC1) oscillation circuit Crystal oscillation circuit 32.768 kHz (Typ.), or CR oscillation circuit 200 kHz (Max.)
Instruction set
608 types (usable for multiplication and division instructions)
Min. instruction execution time 0.244 µsec/8.2 MHz (2 clock)
Internal ROM capacity
48K bytes/program ROM
896K bytes/kanji font ROM (can be used for a program and data ROM when no font data is stored.)
8K bytes/RAM 768 bytes/display memory
Internal RAM capacity
Bus line
Address bus: 20 bits (also usable as general output ports when not used for the bus)
Data bus:
8 bits (also usable as general I/O ports when not used for the bus)
3 bits
CE signal:
WR signal: 1 bit
RD signal: 1 bit
(also usable as general output ports when not used for the bus)
Input port
8 bits (4 bits can be used as the source clock inputs for PWM timers and 1 bit as a bus request signal input)
Output port
0–3 bits (when the external bus is used)
26 bits (when the external bus is not used)
8 bits (when the external bus is used)
16 bits (when the external bus is not used)
(1 bit can be configured for the bus acknowledge signal output)
I/O port
(shard with serial interface, FOUT and TOUT terminals)
Serial interface
Timer
1 ch (optional clock synchronous system or asynchronous system)
Programmable timer: 16 bits (8 bits × 2) 4 ch (with PWM function)
Clock timer:
1 ch
LCD driver
Dot matrix type (supports 16 × 16/5 × 8 or 12 × 12 dot font)
126 segments × 32, 16 or 8 commons (1/5 bias)
Built-in LCD power supply circuit (booster type, 5 potentials)
Built-in (1–8 second cycles)
Watchdog timer
Supply voltage detection
(SVD) circuit
13 value programmable (1.8–2.7 V)
Interrupt
External interrupt: Input interrupt
Internal interrupt: Timer interrupt
1 system (8 types)
2 systems (16 types)
1 system (3 types)
Serial interface interrupt
Supply voltage
1.8–3.6 V
Current consumption
SLEEP mode: 1 µA
(Typ.)
HALT mode: 2.5 µA (Typ.) 32 kHz crystal, LCD OFF
10 µA (Typ.) 32 kHz CR, LCD OFF
7.6 µA (Typ.) 32 kHz crystal, LCD ON*, VDD = 2.5–3.6 V
Run state:
9 µA
(Typ.) 32 kHz crystal, LCD OFF
15 µA (Typ.) 32 kHz CR, LCD OFF
1700 µA (Typ.) 8 MHz ceramic, LCD OFF
600 µA (Typ.) 2 MHz CR, LCD OFF
14 µA (Typ.) 32 kHz crystal, LCD ON*, VDD = 2.5–3.6 V
19 µA (Typ.) 32 kHz crystal, LCD ON*, VDD = 1.8–2.5 V, Power voltage booster ON
14 µA (Typ.) 32 kHz crystal, SVD ON
Supply form
QFP22-256pin or chip
∗ The current consumption with LCD ON listed above is the value under the conditions of LCDCx = "11 (all on)", LCx = "0FH" and
"No panel load". Current consumption increases according to the display contents and panel load.
S1C88650 TECHNICAL MANUAL
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1
1 INTRODUCTION
1.2 Block Diagram
Core CPU S1C88
OSC1, 2
OSC3, 4
Oscillator
System Controller
Reset/Test
Interrupt Controller
Input Port
MCU/MPU
K00–K02
BREQ (K03)
BACK (R33)
K03 (BREQ)
K04–K07
P10 (SIN)
RESET
TEST
P11 (SOUT)
I/O Port
P12 (SCLK)
P13 (SRDY)
P14 (TOUT0/TOUT1)
P15 (TOUT2/TOUT3)
P16 (FOUT)
Watchdog Timer
Serial Interface
EXCL0–EXCL3 (K04–K07)
TOUT0–TOUT3 (P14, P15)
TOUT2/TOUT3 (P17)
P17 (TOUT2/TOUT3)
P00–P07 (D0–D7)
External
Memory Interface
Programmable Timer
/Event Counter
R00–R07, R10–R17, R20–R23
(A0–A7, A8–A15, A16–A19)
R24, R25 (RD, WR)
R30–R32 (CE0–CE2)
R33 (BACK)
Clock Timer
Output Port
LCD Driver
VDD
VSS
SEG0–SEG125
COM0–COM31
VD1
Power Generator
VD2
VC1–VC5
CA–CG
Supply Voltage Detector
RAM
ROM
8K bytes
48K bytes+896K bytes
Fig. 1.2.1 S1C88650 block diagram
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S1C88650 TECHNICAL MANUAL
1 INTRODUCTION
1.3 Pins
1.3.1 Pin layout diagram
QFP22-256pin
192
129
193
128
INDEX
256
65
1
64
Pin No.
1
2
3
4
5
6
7
8
Pin name
N.C.
N.C.
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Pin name
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
N.C.
Pin No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
Pin name
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
VD2
CG
CF
CE
CD
CC
CB
CA
VC5
VC4
VC3
VC2
VC1
N.C.
N.C.
N.C.
N.C.
N.C.
VDD
OSC3
OSC4
VSS
Pin No.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Pin name
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
R00/A0
R01/A1
R02/A2
R03/A3
R04/A4
R05/A5
R06/A6
R07/A7
R10/A8
R11/A9
R12/A10
R13/A11
R14/A12
R15/A13
R16/A14
R17/A15
R20/A16
R21/A17
R22/A18
R23/A19
R24/RD
R25/WR
R30/CE0
R31/CE1
VDD
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
R32/CE2
R33/BACK
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
Pin No.
Pin name
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
VSS
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
–
TEST
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
N.C.
N.C.
N.C.
N.C.
VSS
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
VD1
OSC1
OSC2
TEST
RESET
MCU/MPU
K07/EXCL3
K06/EXCL2
K05/EXCL1
K04/EXCL0
K03/BREQ
K02
K01
K00
149 P17/TOUT2/TOUT3 201
150 P16/FOUT 202
151 P15/TOUT2/TOUT3 203
152 P14/TOUT0/TOUT1 204
153
154
155
156
N.C.
N.C.
N.C.
–
–
–
–
P13/SRDY
P12/SCLK
P11/SOUT
P10/SIN
205
206
207
208
–
–
–
COM9
COM10
Fig. 1.3.1.1 S1C88650 pin layout
S1C88650 TECHNICAL MANUAL
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3
1 INTRODUCTION
1.3.2 Pin description
Table 1.3.2.1 S1C88650 pin description
Pin name
Pin No.
In/Out
Function
VDD
VSS
VD1
VD2
131, 189
67, 134, 195, 253
135
–
–
–
Power supply (+) terminal
Power supply (GND) terminal
Internal logic system and oscillation system voltage regulator output terminals
LCD circuit power voltage booster output terminal
113
–
VC1–VC5
CA–CG
OSC1
OSC2
OSC3
OSC4
MCU/MPU
K00–K02
K03/BREQ
K04/EXCL0
K05/EXCL1
K06/EXCL2
K07/EXCL3
R00–R07/A0–A7
R10–R17/A8–A15
R20–R23/A16–A19
R24/RD
125–121
120–114
136
137
132
133
140
148–146
145
144
–
–
I
O
I
O
I
I
I
I
LCD drive voltage output terminals
LCD and power voltage booster capacitor connection terminals
OSC1 oscillation input terminal (select crystal/CR oscillation by mask option)
OSC1 oscillation output terminal
OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation by mask option)
OSC3 oscillation output terminal
MCU/MPU mode setup terminal
Input terminals (K00–K02)
Input terminal (K03) or bus request signal input terminal (BREQ)
Input terminal (K04) or programmable timer external clock input terminal (EXCL0)
Input terminal (K05) or programmable timer external clock input terminal (EXCL1)
Input terminal (K06) or programmable timer external clock input terminal (EXCL2)
Input terminal (K07) or programmable timer external clock input terminal (EXCL3)
Output terminals (R00–R07) or address bus (A0–A7)
Output terminals (R10–R17) or address bus (A8–A15)
Output terminals (R20–R23) or address bus (A16–A19)
Output terminal (R24) or read signal output terminal (RD)
Output terminal (R25) or write signal output terminal (WR)
Output terminals (R30–R32) or chip enable signal output terminals (CE0–CE2)
Output terminal (R33) or bus acknowledge signal output terminal (BACK)
I/O terminals (P00–P07) or data bus (D0–D7)
143
142
141
I
I
I
165–172
173–180
181–184
185
186
187, 188, 196
197
164–157
156
155
154
153
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
R25/WR
R30–R32/CE0–CE2
R33 (BACK)
P00–P07/D0–D7
P10/SIN
P11/SOUT
P12/SCLK
P13/SRDY
P14/TOUT0/TOUT1
I/O terminal (P10) or serial I/F data input terminal (SIN)
I/O terminal (P11) or serial I/F data output terminal (SOUT)
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
I/O terminal (P14)
152
or programmable timer underflow signal output terminal (TOUT0/TOUT1)
I/O terminal (P15)
P15/TOUT2/TOUT3
151
I/O
or programmable timer underflow signal output terminal (TOUT2/TOUT3)
I/O terminal (P16) or clock output terminal (FOUT)
I/O terminal (P17)
P16/FOUT
P17/TOUT2/TOUT3
150
149
I/O
I/O
or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3)
LCD common output terminals
LCD segment output terminals
COM0–COM31
SEG0–SEG125
198–213, 112–97
214–252, 4–61,
O
O
68–96
139
138
3
RESET
TEST
TEST
I
I
–
Initial reset input terminal
Test input terminal
Test terminal (open during normal operation)
4
EPSON
S1C88650 TECHNICAL MANUAL
1 INTRODUCTION
Select the specifications that meet the target system
and check the appropriate box.
1.4 Mask Option
Mask options shown below are provided for the
S1C88650.
Several hardware specifications are prepared in
each mask option, and one of them can be selected
according to the application. Multiple specifications
are available in each option item as indicated in the
Option List.
The option selection is done interactively on the
screen during function option generator winfog
execution, using this option list as reference. Mask
pattern of the IC is finally generated based on the
data created by the winfog. Refer to the
"S5U1C88000C Manual II" for details on the winfog.
PERIPHERAL CIRCUIT BOARD option list
The following shows the options for configuring the Peripheral Circuit Board (S5U1C88000P1 with
S5U1C88649P2) installed in the ICE (S5U1C88000H5). The selections do not affect the IC's mask option.
A OSC1 SYSTEM CLOCK
When User Clock is selected, input a clock to the OSC1
terminal. When Internal Clock is selected, the clock
frequency is changed according to the oscillation circuit
selected by the IC's mask option.
■ 1. Internal Clock
■ 2. User Clock
B OSC3 SYSTEM CLOCK
When User Clock is selected, input a clock to the OSC3
terminal. When Internal Clock is selected, the clock
frequency is changed according to the oscillation circuit
■ 1. Internal Clock
■ 2. User Clock
selected by the IC's mask option.
S1C88650 mask option list
The following shows the option list for generating the IC's mask pattern. Note that the Peripheral Circuit
Board installed in the ICE does not support some options.
1 OSC1 SYSTEM CLOCK
The specification of the OSC1 oscillation circuit can be
selected from among two types: "Crystal oscillation" and
"CR oscillation". Refer to Section 5.4.3, "OSC1 oscillation
circuit", for details.
■ 1. Crystal
■ 2. CR
2 OSC3 SYSTEM CLOCK
The specification of the OSC3 oscillation circuit can be
selected from among three types: "Crystal oscillation",
"Ceramic oscillation" and "CR oscillation". Refer to
Section 5.4.4, "OSC3 oscillation circuit", for details.
■ 1. Crystal
■ 2. Ceramic
■ 3. CR
3 MULTIPLE KEY ENTRY RESET
This mask option can select whether the multiple key
entry reset function is used or not. When the function is
used, a combination of the input ports (K00–K03), which
are connected to the keys, can be selected. Refer to
Section 4.1.2, "Simultaneous LOW level input at input
port terminals K00–K03", for details.
• Combination .. ■ 1. Not Use
■ 2. Use K00, K01
■ 3. Use K00, K01, K02
■ 4. Use K00, K01, K02, K03
4 INPUT PORT PULL UP RESISTOR
• K00................... ■ 1. With Resistor ■ 2. Gate Direct
• K01................... ■ 1. With Resistor ■ 2. Gate Direct
• K02................... ■ 1. With Resistor ■ 2. Gate Direct
• K03................... ■ 1. With Resistor ■ 2. Gate Direct
• K04................... ■ 1. With Resistor ■ 2. Gate Direct
• K05................... ■ 1. With Resistor ■ 2. Gate Direct
• K06................... ■ 1. With Resistor ■ 2. Gate Direct
• K07....._.._._.._._.._...... ■ 1. With Resistor ■ 2. Gate Direct
This mask option can select whether the pull-up resistor
for the input (K) port terminal is used or not. It is
possible to select for each bit of the input ports. Refer to
Section 5.5, "Input Ports (K ports)", for details.
Furthermore, a pull-up option is also provided for the
______
________
MCU/ MPU and RESET terminals.
• MCU/ MPU .... ■ 1. With Resistor ■ 2. Gate Direct
________
• RESET ............. ■ 1. With Resistor ■ 2. Gate Direct
S1C88650 TECHNICAL MANUAL
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5
1 INTRODUCTION
5 I/O PORT PULL UP RESISTOR
This mask option can select whether the pull-up resistor
for the I/ O port terminal (it works during input mode) is
used or not. It is possible to select for each bit of the I/ O
ports. Refer to Section 5.7, "I/ O Ports (P ports)", for
details.
• P00 ......... ■ 1. With Resistor
• P01 ......... ■ 1. With Resistor
• P02 ......... ■ 1. With Resistor
• P03 ......... ■ 1. With Resistor
• P04 ......... ■ 1. With Resistor
• P05 ......... ■ 1. With Resistor
• P06 ......... ■ 1. With Resistor
• P07 ......... ■ 1. With Resistor
• P10 ......... ■ 1. With Resistor
• P11 ......... ■ 1. With Resistor
• P12 ......... ■ 1. With Resistor
• P13 ......... ■ 1. With Resistor
• P14 ......... ■ 1. With Resistor
• P15 ......... ■ 1. With Resistor
• P16 ......... ■ 1. With Resistor
• P17 ......... ■ 1. With Resistor
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
■ 2. Gate Direct
6 INPUT PORT INPUT I/F LEVEL
This mask option can select the interface level of the
input (K) port from either the CMOS level or CMOS
Schmitt level. It is possible to select for each bit of the
input ports. Refer to Section 5.5, "Input Ports (K ports)",
for details.
The input port on the ICE (with the Peripheral Circuit
Board installed) is fixed to the CMOS level interface
regardless of this option selection.
• K00......... ■ 1. CMOS Level
• K01......... ■ 1. CMOS Level
• K02......... ■ 1. CMOS Level
• K03......... ■ 1. CMOS Level
• K04......... ■ 1. CMOS Level
• K05......... ■ 1. CMOS Level
• K06......... ■ 1. CMOS Level
• K07......... ■ 1. CMOS Level
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
7 I/O PORT INPUT I/F LEVEL
• P10 ......... ■ 1. CMOS Level
• P11 ......... ■ 1. CMOS Level
• P12 ......... ■ 1. CMOS Level
• P13 ......... ■ 1. CMOS Level
• P14 ......... ■ 1. CMOS Level
• P15 ......... ■ 1. CMOS Level
• P16 ......... ■ 1. CMOS Level
• P17 ......... ■ 1. CMOS Level
This mask option can select the interface level of the I/ O
(P) port from either the CMOS level or CMOS Schmitt
level. It is possible to select for each bit of the I/ O ports.
Refer to Section 5.7, "I/ O Ports (P ports)", for details.
The input port on the ICE (with the Peripheral Circuit
Board installed) is fixed to the CMOS level interface
regardless of this option selection.
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
■ 2. CMOS Schmitt
______
8 WATCHDOG TIMER NMI GENERATION CYCLE
______
■ 1. 32768/ fOSC1
(0.75–1-sec cycle when fOSC1 = 32 kHz)
■ 2. 65536/ fOSC1
This mask option can select the NMI generation cycle of
the watchdog timer. Refer to Section 5.3.1, "Configuration
of watchdog timer", for details.
(1.5–2-sec cycle when fOSC1 = 32 kHz)
■ 3. 131072/ fOSC1
(3–4-sec cycle when fOSC1 = 32 kHz)
■ 4. 262144/ fOSC1
(6–8-sec cycle when fOSC1 = 32 kHz)
6
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S1C88650 TECHNICAL MANUAL
2 POWER SUPPLY
2 POWER SUPPLY
In this section, we will explain the operating voltage and the configuration of the internal power
supply circuit of the S1C88650.
Either <VDD> or <VD2> can be selected as the
power source for the LCD system voltage regulator
2.1 Operating Voltage
The S1C88650 operating power voltage is as
follows:
according to the <VDD> power supply voltage
level.
1.8 V to 3.6 V
Table 2.2.2 Power source for LCD system
voltage regulator
2.2 Internal Power Supply Circuit
Supply voltage
VDD
Power source for
LCD system voltage regulator
The S1C88650 incorporates the power supply
circuit shown in Figure 2.2.1. When voltage within
the range described above is supplied to VDD (+)
and VSS (GND), all the voltages needed for the
internal circuit are generated internally in the IC.
1.8–2.5 V
2.5–3.6 V
VD2
VDD
The VD2 voltage is about double the VDD voltage
level. Refer to Chapter 8, "ELECTRICAL
CHARACTERISTICS", for details.
Roughly speaking, the power supply circuit is
divided into three sections.
The LCD system voltage regulator generates the 1/
5-bias LCD drive voltages <VC1>, <VC2>, <VC3>,
<VC4> and <VC5>. See Chapter 8, "ELECTRICAL
CHARACTERISTICS" for the voltage values.
Table 2.2.1 Power supply circuit
Circuit
Power supply circuit Output voltage
Oscillation circuits,
Internal circuits
Internal logic
voltage regulator
VD1
In the S1C88650, the LCD drive voltage is supplied
to the built-in LCD driver which drives the LCD
panel connected to the SEG and COM terminals.
LCD system voltage Power voltage
VDD or VD2
regulator
booster
LCD driver
LCD system voltage VC1–VC5
regulator
Notes: • Under no circumstances should VD1,VD2,
VC1, VC2, VC3, VC4 and VC5, terminal
The internal logic voltage regulator generates the
operating voltage <VD1> for driving the internal
logic circuits and the oscillation circuit.
output be used to drive external circuit.
• If VDD is used as the power source for the
LCD system voltage regulator when VDD is
2.5 V or less, the VC1 to VC5 voltages
The VD1 voltage value is fixed at 1.8 V (Typ.).
The power voltage booster generates the operating
voltage <VD2> for the LCD system voltage
regulator.
cannot be generated within specifications.
VDD
OSC1, OSC2
OSC3, OSC4
Oscillation circuit
External
power
supply
Internal logic
VD1
VD1
Internal circuit
voltage regulator
VD2
CF
CG
Power voltage
booster
VD2
VC1
VC2
VC3
VC4
VC5
CA
CB
CC
CD
CE
COM0–COM31
SEG0–SEG125
VC1–VC5
LCD system
voltage regulator
LCD driver
VSS
Fig. 2.2.1 Configuration of power supply circuit
S1C88650 TECHNICAL MANUAL
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7
3 CPU AND BUS CONFIGURATION
3 CPU AND BUS CONFIGURATION
In this section, we will explain the CPU, operating mode and bus configuration.
3.2.2 RAM
The internal RAM capacity is 8K bytes and is
allocated to 00D800H–00F7FFH.
Even when external memory which overlaps the
3.1 CPU
The S1C88650 utilize the S1C88 8-bit core CPU
whose resistor configuration, command set, etc. are
virtually identical to other units in the family of
internal RAM area is expanded, the RAM area is
processors incorporating the S1C88.
not released to external memory. Access to this area
See the "S1C88 Core CPU Manual" for the S1C88.
is via internal RAM.
Specifically, the S1C88650 employ the Model 3
S1C88 CPU which has a maximum address space of
1M bytes × 3.
3.2.3 I/O memory
A memory mapped I/ O method is employed in the
S1C88650 for interfacing with internal peripheral
circuit. Peripheral circuit control bits and data
register are arranged in data memory space.
Control and data exchange are conducted via
normal memory access. I/ O memory is arranged in
page 0: 00FF00H–00FFFFH area.
3.2 Internal Memory
The S1C88650 is equipped with internal ROM and
RAM as shown in Figure 3.2.1. Small scale applica-
tions can be handled by one chip. It is also possible
to utilize internal memory in combination with
external memory.
See Section 5.1, "I/ O Memory Map", for details of
the I/ O memory.
Furthermore, internal ROM can be disconnected
from the bus and the resulting space released for
external applications.
Even when external memory which overlaps the I/
O memory area is expanded, the I/ O memory area
is not released to external memory. Access to this
area is via I/ O memory.
0EFFFFH
Kanji font ROM
(896K bytes)
3.2.4 Display memory
The S1C88650 is equipped with an internal display
memory which stores a display data for LCD
driver.
Display memory is arranged in page 0: 00Fx00H–
00Fx7FH (x = 8–DH) in the data memory area. See
Section 5.11, "LCD Driver", for details of the display
memory. Like the I/ O memory, display memory
cannot be released to external memory.
010000H
00FFFFH
00FF00H
00FD7FH
00F800H
00F7FFH
00D800H
00D7FFH
I/O memory
Display memory
RAM (8K bytes)
Unused
area
:
00C000H
00BFFFH
3.2.5 Kanji font ROM
The S1C88650 has a built-in kanji font ROM that
can be used to store JIS level-1 and level-2 kanji
sets, alphanumeric characters and music shift-JIS
characters.
ROM
(48K bytes)
The kanji font ROM capacity is 896K bytes and is
allocated to 010000H–0EFFFFH.
000000H
When the kanji font is not used the remaining area
or the entire area can be used for a program and
data storage area (see the "S5U1C88xxxRx Manual"
for use of font data).
Fig. 3.2.1 Internal memory map
3.2.1 Program ROM
The S1C88650 has a built-in 48K-byte program
ROM. The ROM is allocated to 000000H–00BFFFH.
This ROM areas shown above can be released to
This ROM areas shown above can be released to
external memory depending on the setting of the
_______
MCU/ MPU terminal. (See "3.5 Chip Mode".)
external memory depending on the setting of the
_______
MCU/ MPU terminal. (See "3.5 Chip Mode".)
8
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S1C88650 TECHNICAL MANUAL
3 CPU AND BUS CONFIGURATION
When multiple exception processing factors are
generated at the same time, execution starts with
the highest priority item.
The priority sequence shown in Table 3.3.1 assumes
that the interrupt priority levels are all the same.
The interrupt priority levels can be set by software
in each system. (See Section 5.14, "Interrupt and
Standby Status".)
3.3 Exception Processing Vectors
000000H–00004BH in the program area of the
S1C88650 is assigned as exception processing
vectors. Furthermore, from 00004EH to 0000FFH,
software interrupt vectors are assignable to any two
bytes which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they corre-
spond.
Note: For exception processing other than reset,
SC (system condition flag) and PC (program
counter) are evacuated to the stack and
branches to the exception processing
Table 3.3.1 Exception processing vector table
Vector
address
Priority
Exception processing factor
routines. Consequently, when returning to
the main routine from exception processing
routines, please use the RETE instruction.
000000H Reset
High
000002H Zero division
000004H Watchdog timer (NMI)
000006H K07 input interrupt
↑
See the "S1C88 Core CPU Manual" for information
on CPU operations when an exception processing
factor is generated.
000008H K06 input interrupt
00000AH K05 input interrupt
00000CH K04 input interrupt
00000EH K03 input interrupt
000010H K02 input interrupt
000012H K01 input interrupt
3.4 CC (Customized Condition Flag)
The S1C88650 does not use the customized condi-
tion flag (CC) in the core CPU. Accordingly, it
cannot be used as a branching condition for the
conditional branching instruction (JRS, CARS).
000014H K00 input interrupt
000016H PTM 0 underflow interrupt
000018H PTM 0 compare match interrupt
00001AH PTM 1 underflow interrupt
00001CH PTM 1 compare match interrupt
00001EH PTM 2 underflow interrupt
000020H PTM 2 compare match interrupt
000022H PTM 3 underflow interrupt
000024H PTM 3 compare match interrupt
000026H System reserved (cannot be used)
000028H Serial I/F error interrupt
00002AH Serial I/F receiving complete interrupt
00002CH Serial I/F transmitting complete interrupt
00002EH System reserved (cannot be used)
000030H System reserved (cannot be used)
000032H System reserved (cannot be used)
000034H Clock timer 32 Hz interrupt
000036H Clock timer 8 Hz interrupt
000038H Clock timer 2 Hz interrupt
00003AH Clock timer 1 Hz interrupt
00003CH PTM 4 underflow interrupt
00003EH PTM 4 compare match interrupt
000040H PTM 5 underflow interrupt
000042H PTM 5 compare match interrupt
000044H PTM 6 underflow interrupt
000046H PTM 6 compare match interrupt
000048H PTM 7 underflow interrupt
00004AH PTM 7 compare match interrupt
00004CH System reserved (cannot be used)
00004EH
3.5 Chip Mode
3.5.1 MCU mode and MPU mode
The chip operating mode__c_a_n___be set to one of two
settings using the MCU/ MPU terminal.
_______
■ MCU mode...Set the MCU/MPU terminal to HIGH
Switch to this setting when using internal ROM.
With respect to areas other than internal
memory, external memory can even be
expanded. See Section 3.5.2, "Bus mode", for the
memory map.
In the MCU mode, during initial reset, only
systems in internal memory are activated.
Internal program ROM is normally fixed as the
top portion of the program memory from the
common area (logical space 0000H–7FFFH).
Exception processing vectors are assigned in
internal program ROM. Furthermore, the
application initialization routines that start with
reset exception processing must likewise be
written to internal program ROM. Since bus and
other settings which correlate with external
expanded memory can be executed in software,
this processing is executed in the initialization
routine written to internal program ROM. Once
these bus mode settings are made, external
memory can be accessed.
↓
Low
No
priority
rating
:
Software interrupt
0000FEH
For each vector address and the address after it, the
start address of the exception processing routine is
written into the subordinate and super ordinate
sequence. When an exception processing factor is
generated, the exception processing routine is
executed starting from the recorded address.
S1C88650 TECHNICAL MANUAL
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9
3 CPU AND BUS CONFIGURATION
When accessing _in__t_ernal memo_r_y__in this mode,
3.5.2 Bus mode
_____
the chip enable (CE) and read (RD)/ write (WR)
signals are not output to external memory, and
the data bus (D0–D7) goes into high impedance
status (or pull-up status).
Consequently, in cases where addresses overlap
in external and internal memory, the areas in
external memory will be unavailable.
In order to set bus specifications to match the
configuration of external expanded memory, two
different bus modes described below are selectable
in software.
■ Single chip mode
- MCU mode -
_______
■ MPU mode...Set the MCU/MPU terminal to LOW
0EFFFFH
Kanji font ROM
(896K bytes)
Internal ROM area is released to an external
device source. Internal ROM then becomes
unusabl_e__a_nd when this area is accessed, chip
enable (CE) and read (RD)/ write (WR) signals
are output to external memory and the data bus
(D0–D7) become active. These signals are not
output to an external source when other areas of
internal memory are accessed.
010000H
00FFFFH
00FF00H
00FD7FH
00F800H
00F7FFH
00D800H
____
_____
I/O memory
Display memory
Internal RAM
00D7FFH
In the MPU mode, the system is activated by
external memory.
When employing this mode, the exception
processing vectors and initialization routine
must be assigned within the common area
(000000H–007FFFH).
:
Unused area
00C000H
00BFFFH
Internal ROM
You can select wheth_e_r__t_o__use the built-in pull-up
resistor of the MCU/ MPU terminal by the mask
option.
000000H
Iput port pull-up resistor
Fig. 3.5.2.1 Memory map for the single chip mode
_______
MCU/ MPU ..... ■ With resistor ■ Gate direct
The single chip mode setting applies when the
S1C88650 is used as a single chip microcom-
puter without external expanded memory.
Since this mode employs internal ROM, the
system can only be operated in the MCU mode
discussed in Section 3.5.1.
In the MPU mode, the system cannot be set to
the single chip mode.
Since there is no need for an external bus line in
this mode, terminals normally set for bus use
can be used as general purpose output ports or
I/ O ports.
Notes: • Setting of MCU/MPU terminal is latched at
the rising edge of a reset signal input from
the RESET terminal. Therefore, if the setting
is to be changed, the RESET terminal must
be set to LOW level once again.
•
The data bus while the CPU accesses to the
internal memory can be select into high-
impedance status or pulled up to high using
the pull-up control register and mask option.
See Section 5.7, "I/O Ports (P ports)", for
details.
■ Expansion mode
The expansion mode setting applies when the
S1C88650 is used with less than 1M bytes × 3 of
external expanded memory. This mode is
usable regardless of the MCU/ MPU mode
setting.
Because internal ROM is being used in the MCU
mode, external memory in this model can be
assigned to the area from 100000H to 3FFFFFH.
Since the internal ROM area is released in the
MPU mode, external memory in this model can
be assigned to the area from 000000H to
2FFFFFH.
However, the area from 00C000H to 00FFFFH is
assigned to internal memory and cannot be
used to access an external device.
10
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S1C88650 TECHNICAL MANUAL
3 CPU AND BUS CONFIGURATION
- MCU mode -
- MPU mode -
3.6 External Bus
3FFFFFH
The S1C88650 has bus terminals that can address a
maximum of 1M × 3 bytes and memory (and other)
devices can be externally expanded according to
the range of each bus mode described in the
previous section.
2FFFFFH
External
memory area
:
External
memory area
Address bus (A0–A19)
100000H
Data bus (D0–D7)
Unused area
S1C88650
0F0000H
0EFFFFH
BREQ
External
device
External
device
External
device
BACK
Internal memory
010000H
00FFFFH
00D800H
00D7FFH
:
Internal memory
RD
WR
CE0
CE1
CE2
Unused area
00C000H
00BFFFH
Fig. 3.6.1 External bus lines
Below is an explanation of external bus terminals.
For information on control methods, see Section 5.2,
"System Controller and Bus Control".
External
memory area
Internal memory
3.6.1 Data bus
The S1C88650 possesses an 8-bit external data bus
(D0–D7). The terminals and I/ O circuits of data bus
D0–D7 are shared with I/ O ports P00–P07, switch-
ing between these functions being determined by
the bus mode setting.
In the single chip mode, the 8-bit terminals are all
set as I/ O ports P00–P07 and in the expansion
mode, they are set as data bus (D0–D7).
000000H
See Figure 3.2.1 for the internal memory
Fig. 3.5.2.2 Memory map for the expansion mode
There is an explanation on how all these settings
are actually made in "5.2 System Controller and Bus
Control" of this Manual.
When set as data bus, the data register and I/ O
control register of each I/ O port are detached from
the I/ O circuits and usable as a general purpose
data register with read/ write capabilities.
3.5.3 CPU mode
The CPU allows software to select its operating
mode from two types shown below according to
the programming area size.
The data bus can be pulled up to high during input
mode using the built-in pull-up resistor. This pull-
up resistor is enabled or disabled using the pull-up
control register and mask option. See "5.7 I/ O
Ports" for details.
■ Minimum mode
The program area is configured within 64K
bytes in any one-bank. However, the bank to be
used must be specified in the CB register and
cannot be changed after an initialization. This
mode does not push the CB register contents
onto the stack when a subroutine is called. It
makes it possible to economize on stack area
usage. This mode is suitable for small- to mid-
scale program memory and large-scale data
memory systems.
I/O
port
Data
bus
P00
P01
P02
P03
P04
P05
P06
P07
D0
D1
D2
D3
D4
D5
D6
D7
Bus mode
Bus mode
Single
chip
Expansion
■ Maximum mode
The program area can be configured exceeding
64K bytes. However the CB register must be
setup when the program exceeds a bank
boundary every 64K bytes. This mode pushes
the CB register contents when a subroutine is
called. This mode is suitable for large-scale
program and data memory systems.
Fig. 3.6.1.1 Correspondence between data bus
and I/O ports
S1C88650 TECHNICAL MANUAL
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11
3 CPU AND BUS CONFIGURATION
____
_____
When set as read (RD)/ write (WR) signal output
terminal, the data register and high impedance
control register for each output port (R24, R25) are
detached from the output circuit and is usable as a
general purpose data register with read/ write
capabilities.
3.6.2 Address bus
The S1C88650 possesses a 20-bit external address
bus A0–A19. The terminals and output circuits of
address bus A0–A19 are shared with output ports
R00–R07 (=A0–A7), R10–R17 (=A8–A15) and R20–
R23 (=A16–A19), switching between these functions
being determined by the bus mode setting.
In the single chip mode, the 20-bit terminals are all
set as output ports R00–R07, R10–R17 and R20–R23.
In the expansion mode, all of the 20-bit terminals
are set as the address bus (A0–A19).
See Section 3.6.5, "WAIT control", for the output
timing of the signal.
Output
port
RD/WR
signal
When set as an address bus, the data register and
high impedance control register of each output port
are detached from the output circuit and used as a
general purpose data register with read/ write
capabilities.
Bus mode
Bus mode
R24
R25
RD
Single
chip
Expansion
WR
____
Output
port
Address
bus
Fig. 3.6.3.1 Correspondence between read (RD)/
_____
write (WR) signal and output ports
R00
R01
R02
R03
R04
R05
R06
R07
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
R23
A0
A1
_____
3.6.4 Chip enable (CE) signal
A2
The S1C88650 is equipped with address decoders
____
A3
which can output three different chip enable (CE)
signals.
Consequently, three devices equipped with a chip
enable (CE) or chip select (CS) terminal can be
directly connected without setting the address
A4
A5
_____
_____
A6
A7
Bus mode
Bus mode
A8
decoder to an external device.
_____ _____
A9
Single
chip
The three chip enable (CE0–CE2) signal output
terminals and output circuits are shared with
output ports R30–R32 and in the expansion mode,
either the chip enable (CE) output or general output
Expansion
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
____
can be selected in software for each of the three bits.
____
When set for chip enable (CE) output, the data
register and high impedance control register for
each output port are detached from the output
circuit and is usable as general purpose data
register with read/ write capabilities.
In the single chip mode, these terminals are set as
output ports R30–R32.
Fig. 3.6.2.1 Correspondence between address bus
and output ports
Output
port
CE
signal
Bus mode
Bus mode
Expansion
____
_____
______
R30
R31
R32
CE0
CE1
CE2
3.6.3 Read (RD)/write (WR) signals
Single
chip
The output terminals and output circuits for the
____
_____
read (RD)/ write (WR) signals directed to external
devices are shared respectively with output ports
R24 and R25, switching between these functions
being determined by the bus mode setting.
Fig. 3.6.4.1 Correspondence between CE signals
and output ports
Table 3.6.4.1 shows the address ranges which are
assigned to the chip enable (CE) signal in the
expansion mode.
____
In the single chip mode, both of these terminals are
set as output port terminals__a_n_d in the expansion
_____
mode, they are set as read (RD)/ write (WR) signal
output terminals.
12
EPSON
S1C88650 TECHNICAL MANUAL
3 CPU AND BUS CONFIGURATION
_____ _____
Table 3.6.4.1 CE0–CE2 address settings
Address range (expansion mode)
CE signal
MCU mode
MPU mode
CE0
CE1
CE2
300000H–3FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
000000H–00D7FFH, 010000H–0FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
_____
When accessing the internal memory area, the CE
signal is not output. Care should be taken here
because the address range for these portions of
memory involves irregular settings.
The arrangement of memory space for external
devices does not necessarily have to be continuous
from a subordinate address and any of the chip
enable signals can be used to assign areas in
memory.
Table 3.6.5.1 Selectable WAIT state numbers
Selection No.
Insert states
1
0
2
2
3
4
4
6
5
8
6
7
8
10 12 14
* One state is a 1/ 2 cycle of the clock in length.
The WAIT states set in software are inserted
between bus cycle states T3–T4.
Note, however, that WAIT states cannot be inserted
when an internal register and internal memory are
being accessed and when operating with the OSC1
oscillation circuit (see "5.4 Oscillation Circuits").
Consequently, WAIT state settings are meaningless
in the single chip mode.
____
Note: The CE signals will be inactive status when
the chip enters the standby mode (HALT
mode or SLEEP mode).
See Section 3.6.5, "WAIT control", for the output
timing of signal.
Figure 3.6.5.1 shows the memory read/ write
timing charts.
T1 T2 T3 T4 T1 T2 T3 T4
CLK
3.6.5 WAIT control
In order to insure accessing of external low speed
devices during high speed operations, the S1C88650
is equipped with a WAIT function which prolongs
access time. (See the "S1C88 Core CPU Manual" for
details of the WAIT function.)
Address
Address
A0–A19
CE0
CE1
The WAIT state numbers to be inserted can be
selected in software from a series of 8 as shown in
Table 3.6.5.1.
WR
RD
Read data
Read cycle
Write data
D0–D7
Write cycle
(1) No WAIT
WAIT (4 states inserted)
WAIT (4 states inserted)
T1 T2 T3 Tw1 Tw2 Tw1 Tw2 T4 T1 T2 T3 Tw1 Tw2 Tw1 Tw2 T4
CLK
A0–A19
CE0
Address
Address
CE1
WR
RD
Read data
Read cycle
Write data
D0–D7
Write cycle
(2) WAIT state insertion
Fig. 3.6.5.1 Memory read/write cycle
S1C88650 TECHNICAL MANUAL
EPSON
13
3 CPU AND BUS CONFIGURATION
________
When the bus authority release request (BREQ =
3.6.6 Bus authority release state
LOW) is received from an external device, the____
S1C88650 switches the address bus, data bus, RD/
The S1C88650 is equipped with a bus authority
release function on request from an external device
so that DMA (Direct Memory Access) transfer can
be conducted between external devices. The
internal memory cannot be accessed by this
function.
_____
____
WR signal, and CE signal lines to a h_i_g_h___i_m_ pedance
state, outputs a LOW level from the BACK terminal
and releases bus authority.
________
As soon as a LOW level is output from the BACK
terminal, the external device can use the external
bus. When DMA is completed, the external device
returns the BREQ terminal to HIGH and releases
bus authority.
There are two terminals used for this_f_u__n__c_t_ion: the
bus authority release request signal (BREQ) input
termina_l__a_n__d__the bus authority release acknowledge
________
Figure 3.6.6.2 shows the bus authority release
sequence.
signal (BACK) output terminal.
________
The BREQ input terminal is shared with input port
________
terminal K03 and the BACK output terminal with
During bus authority release state, internal memory
cannot be accessed from the external device. In
cases where external memory has areas which
overlap areas in internal memory, the external
output port terminal R33, use with setting to
________ ________
BREQ/ BACK terminals done in software. In the
single chip mode, or when using a system which
does not require bus authority release, set respec-
tive terminals as input and output ports.
memory areas can be accessed accordance with the
____
CE signal output by the external device.
Input
BREQ
port
Note: Be careful with the system, such that an
external device does not become the bus
master, other than during the bus release
input
K03
status.
Output
BACK
port
_______
After setting the BREQ terminal to LOW
level, hold the BREQ terminal at LOW level
_______
output
R33
_______
until the BACK terminal becomes LOW level.
_______ _______
_______
Fig. 3.6.6.1 BREQ/BACK terminals
If the BREQ term_in__a_l_i_s_ returned to HIGH
level, before the BACK terminal becomes
LOW level, the shift to the bus authorization
release status will become indefinite.
Tw2
T4
T1
T2
T3
Tw1
Tw2
T4
Tz1
Tz2
Tz1
Tz2
Tz1
Tz2
Tz1
Tz2
T1
T2
T3
CLK
A0–A19
D0–D7
WR
IX
HL
PC
(IX)
(IX)
ANY
RD
BREQ
BACK
L
L
L
L
H
Program
exection
status
Program exection status
Bus authority release status
LD [HL],[IX]
Fig. 3.6.6.2 Bus authority release sequence
14
EPSON
S1C88650 TECHNICAL MANUAL
4 INITIAL RESET
4 INITIAL RESET
Initial reset in the S1C88650 is required in order to initialize circuits. This section of the Manual
contains a description of initial reset factors and the initial settings for internal registers, etc.
____________
4.1.1 RESET terminal
4.1 Initial Reset Factors
There are two initial reset factors for the S1C88650
Initial reset can be done by externally inputting a
_________
LOW level to the RESET terminal.
_________
as shown below.
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset. (See Section 8.6, "AC
_________
(1) External initial reset by the RESET terminal
(2) External initial reset by the simultaneous LOW
level input at input port terminals K00–K03
(mask option)
Characteristics".)
_________
In addition, be sure to use the RESET terminal for
the f_ir__s_t__i_n_i_tial reset after the power is turned on.
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
Figure 4.1.1 shows the configuration of the initial
reset circuit.
The CPU and peripheral circuits are initialized by
means of initial reset factors. When the factor is
canceled, the CPU commences reset exception
processing. (See the "S1C88 Core CPU Manual".)
When this occurs, the reset exception processing
vector, Bank 0, 000000H–000001H from program
memory is read out and the program (initialization
routine) which begins at the readout address is
executed.
Input port pull-up resistor
_________
RESET ............■ With resistor
■ Gate direct
Operating clock status
OSC3
oscillation
circuit
OSC3
OSC4
fOSC3/1,024 Hz
Divider
Divider
Selector
fOSC1/256 Hz
OSC1
oscillation
circuit
OSC1
OSC2
Reset release
clock
Time
authorize
circuit
Input port K00
Input port K01
Input port K01
Input port K03
K00
K01
K02
K03
Internal initial
reset
R
S
Q
Reset signal
SLEEP status
Oscillation stability
waiting signal
VDD
Mask
option
RESET
Fig. 4.1.1 Configuration of initial reset circuit
S1C88650 TECHNICAL MANUAL
EPSON
15
4 INITIAL RESET
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is
to input a LOW level simultaneously to the input
ports (K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for 65536/ fOSC1 seconds (two seconds
when the oscillation frequency is fOSC1 = 32.768
kHz) or more to perform the initial reset by means
of this function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
4.1.3 Initial reset sequence
After cancellation of the LOW level input to the
_________
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (512/ fOSC3 sec.) have
elapsed.
Figure 4.1.3.1 shows the operating sequence
following initial reset release.
The CPU starts operating in synchronization with
the OSC3 clock after reset status is released.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time, following cancellation of the LOW level
simultaneous input.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
Multiple key entry reset
■ Not use
■ K00 & K01
■ K00 & K01 & K02
■ K00 & K01 & K02 & K03
(2) Other than during SLEEP status, an initial reset
will be triggered 65536/ fOSC3 seconds after a
LOW level simultaneous input. In this case,
since a reset differential pulse (64/ fOSC1
seconds) is generated within the S1C88650, the
CPU will start even if the LOW level
For instance, let's say that mask option "K00 & K01
& K02 & K03" is selected, when the input level at
input ports K00–K03 is simultaneously LOW, initial
reset will take place.
simultaneous input status is not canceled.
Note: The oscillation stabilization time described in
this section does not include oscillation start
time. Therefore the time interval until the
CPU starts executing instructions after
power is turned on or SLEEP status is
cancelled may be longer than that indicated
in the figure below.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
fOSC3
Reset release
Reset signal
Reset release clock
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
Internal initial reset release
PC
PC
PC
00-0000
VECL
Dummy
Dummy
512/fOSC3 [sec]
Oscillation stable waiting time
Dummy cycle
Reset exception processing
∗ Reset status is maintained
during this period.
Fig. 4.1.3.1 Initial reset sequence
16
EPSON
S1C88650 TECHNICAL MANUAL
4 INITIAL RESET
4.2 Initial Settings After Initial Reset
The CPU internal registers are initialized as follows
during initial reset.
Table 4.2.1 Initial settings
Register name
Data register A
Code Bit length Setting value
A
B
8
8
Undefined
Data register B
Index (data) register L
Index (data) register H
Index register IX
Index register IY
Program counter
Stack pointer
Undefined
L
8
Undefined
H
8
Undefined
IX
IY
PC
SP
BR
Z
16
16
16
16
8
Undefined
Undefined
Undefined*
Undefined
Base register
Undefined
Zero flag
1
0
Carry flag
C
1
0
Overflow flag
V
1
0
Negative flag
N
1
0
Decimal flag
D
1
0
Unpack flag
U
1
0
Interrupt flag 0
Interrupt flag 1
New code bank register
Code bank register
Expand page register
I0
1
1
1
I1
1
NB
CB
EP
8
01H
8
Undefined*
00H
8
Expand page register for IX XP
Expand page register for IY YP
8
00H
8
00H
* Reset exception processing loads the preset
values stored in 0 bank, 0000H–0001H into the
PC. At the same time, 01H of the NB initial
value is loaded into CB.
Initialize the registers which are not initialized at
initial reset using software.
Since the internal RAM and display memory are
not initialized at initial reset, be sure to initialize
using software.
The respectively stipulated initializations are done
for internal peripheral circuits. If necessary, the
initialization should be done using software.
For initial value at initial reset, see the sections on
the I/ O memory map and peripheral circuit
descriptions in the following chapter of this
manual.
S1C88650 TECHNICAL MANUAL
EPSON
17
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
5 PERIPHERAL CIRCUITS AND
THEIR OPERATION
The peripheral circuits of the S1C88650 is interfaced with the CPU by means of the memory mapped
I/ O method. For this reason, just as with other memory access operations, peripheral circuits can be
controlled by manipulating I/ O memory. Below is a description of the operation and control method for
each individual peripheral circuit.
5.1 I/O Memory Map
Table 5.1.1(a) I/O Memory map (00FF00H–00FF03H)
Address Bit Name
00FF00 D7 BUSMOD Bus mode
(MCU) D6 CPUMOD CPU mode
Function
1
Expansion Single chip
0
SR R/W
Comment
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W
R/W
Maximum
Minimum
D5 –
R/W register
R/W register
R/W register
CE2 (R32)
CE1 (R31)
CE0 (R30)
1
1
1
0
0
0
R/W Reserved register
R/W
D4 –
D3 –
R/W
D2 CE2
D1 CE1
D0 CE0
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
R/W In Single chip mode,
R/W these setting are fixed
R/W at DC output.
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
00FF00 D7 BUSMOD Bus mode
Expansion
–
R
Expansion mode only
(MPU) D6 CPUMOD CPU mode
Maximum
Minimum
R/W
D5 –
D4 –
R/W register
R/W register
R/W register
CE2 (R32)
CE1 (R31)
CE0 (R30)
1
1
1
0
0
0
R/W Reserved register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D3 –
D2 CE2
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
D1 CE1
D0 CE0
00FF01 D7 SPP7
D6 SPP6
D5 SPP5
D4 SPP4
D3 SPP3
D2 SPP2
D1 SPP1
D0 SPP0
00FF02 D7 EBR
Stack pointer page address
(MSB)
1
0
1
0
< SP page allocatable address >
• Single chip mode: only 0 page
• Expansion mode: 0–27H page
1
0
1
0
1
0
1
1
0
0
(LSB)
K03
1
0
Bus release enable register
BREQ
BACK
Input port
Output port
(K03 and R33 terminal specification) R33
D6 WT2
D5 WT1
D4 WT0
Wait control register
0
0
0
R/W
R/W
R/W
Number
of state
WT2
WT1
WT0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14
12
10
8
6
4
2
No wait
D3 CLKCHG CPU operating clock switch
OSC3
OSC1
1
1
0
0
–
–
–
–
–
–
0
0
R/W
D2 SOSC3 OSC3 oscillation On/Off control
On
1
Off
0
R/W
D1 –
D0 –
R/W register
R/W Reserved register
R/W
R/W register
1
0
00FF03 D7 –
D6 –
–
–
–
–
–
–
–
–
Constantly "0" when
being read
–
–
D5 –
–
–
D4 –
–
–
D3 –
–
–
D2 –
–
–
D1 VDSEL Power source select for LCD voltage regulator
VD2
VDD
R/W
R/W
D0 DBON Power voltage_b_o_o_ster On/Off control
On
Off
Note: All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.
18
EPSON
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(b) I/O Memory map (00FF10H–00FF14H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF10 D7 HLMOD Heavy load protection mode
On
Off
0
0
0
0
0
0
1
R/W
R/W
D6 SEGREV Reverse SEG assignment
Reverse
Normal
D5 –
D4 –
D3 –
R/W register
R/W register
R/W register
1
0
R/W Reserved register
1
1
0
0
R/W
R/W
R/W
R/W
D2 DTFNT LCD dot font selection
D1 LDUTY1 LCD drive duty selection
LDUTY1 LDUTY0
12×12
16×16/5×8
Duty
Not allowed
1/16
1
1
0
0
1
0
1
0
D0 LDUTY0
0
R/W
1/32
1/8
00FF11 D7 FRMCS LCD frame signal source clock selection
D6 DSPAR LCD display memory area selection
D5 LCDC1 LCD display control
PTM
fOSC1
0
0
0
R/W
R/W
Display area 1 Display area 0
These bits are reset
R/W
to (0, 0) when
LCD display
LCDC1 LCDC0
SLP instruction
1
1
0
0
1
0
1
0
All LCDs lit
All LCDs out
Normal display
Drive off
is executed.
R/W
D4 LCDC0
0
D3 LC3
D2 LC2
D1 LC1
D0 LC0
LCD contrast adjustment
0
0
0
R/W
R/W
R/W
LC3 LC2 LC1 LC0
Contrast
Dark
1
1
:
1
1
:
1
1
:
1
0
:
:
:
Light
0
0
0
0
0
–
–
0
0
0
R/W
00FF12 D7 –
D6 –
–
–
–
–
–
–
Constantly "0" when
being read
D5 SVDDT SVD detection data
Low
On
Normal
Off
R
D4 SVDON SVD circuit On/Off
R/W
R/W
SVD criteria voltage setting
SVDS3 SVDS2 SVDS1 SVDS0 Voltage (V)
D3 SVDS3
D2 SVDS2
D1 SVDS1
D0 SVDS0
0
0
0
R/W
R/W
R/W
1
1
1
:
1
1
1
:
1
1
0
:
1
0
1
:
2.7
2.6
2.5
:
0
0
1
1
1.8
00FF14 D7 PRPRT1 Programmable timer 1 clock control
On
Off
0
0
R/W
R/W
D6 PST12 Programmable timer 1 division ratio
PST12 PST11 PST10 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST11
D4 PST10
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
Programmable timer 0 clock control
Programmable timer 0 division ratio
D3 PRPRT0
D2 PST02
On
Off
0
0
R/W
R/W
PST02 PST01 PST00 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST01
D0 PST00
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
S1C88650 TECHNICAL MANUAL
EPSON
19
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(c) I/O Memory map (00FF15H–00FF18H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF15 D7 PRPRT3 Programmable timer 3 clock control
On
Off
0
0
R/W
R/W
D6 PST32 Programmable timer 3 division ratio
PST32 PST31 PST30 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST31
D4 PST30
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D3 PRPRT2 Programmable timer 2 clock control
On
Off
0
0
R/W
R/W
D2 PST22 Programmable timer 2 division ratio
PST22 PST21 PST20 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST21
D0 PST20
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
00FF17 D7 –
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
R/W register
1
0
R/W Reserved register
D3 PRTF3 Programmable timer 3 source clock selection
D2 PRTF2 Programmable timer 2 source clock selection
D1 PRTF1 Programmable timer 1 source clock selection
D0 PRTF0 Programmable timer 0 source clock selection
00FF18 D7 PRPRT5 Programmable timer 5 clock control
D6 PST52 Programmable timer 5 division ratio
fOSC1
fOSC1
fOSC1
fOSC1
On
fOSC3
fOSC3
fOSC3
fOSC3
Off
R/W
R/W
R/W
R/W
R/W
R/W
PST52 PST51 PST50 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST51
D4 PST50
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D3 PRPRT4 Programmable timer 4 clock control
On
Off
0
0
R/W
R/W
D2 PST42 Programmable timer 4 division ratio
PST42 PST41 PST40 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST41
D0 PST40
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
20
EPSON
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(d) I/O Memory map (00FF19H–00FF22H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF19 D7 PRPRT7 Programmable timer 7 clock control
On
Off
0
0
R/W
R/W
D6 PST72 Programmable timer 7 division ratio
PST72 PST71 PST70 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST71
D4 PST70
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D3 PRPRT6 Programmable timer 6 clock control
On
Off
0
0
R/W
R/W
D2 PST62 Programmable timer 6 division ratio
PST62 PST61 PST60 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST61
D0 PST60
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
00FF1B D7 –
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
D3 PRTF7 Programmable timer 7 source clock selection
D2 PRTF6 Programmable timer 6 source clock selection
D1 PRTF5 Programmable timer 5 source clock selection
D0 PRTF4 Programmable timer 4 source clock selection
fOSC1
fOSC1
fOSC1
fOSC1
fOSC3
fOSC3
fOSC3
fOSC3
R/W
R/W
R/W
R/W
R/W
PK01 PK00 Priority
PSIF1 PSIF0 level
00FF20 D7 PK01
K00–K07 interrupt priority register
D6 PK00
D5 PSIF1
D4 PSIF0
D3 –
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
Serial interface interrupt priority register
0
R/W
–
–
–
–
–
–
0
Constantly "0" when
being read
D2 –
–
–
PTM1 PTM0 Priority level
D1 PTM1
Clock timer interrupt priority register
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D0 PTM0
00FF21 D7 –
–
–
–
–
–
–
0
Constantly "0" when
being read
D6 –
–
–
PPT3 PPT2 Priority
PPT1 PPT0
D5 PPT3
D4 PPT2
D3 PPT1
D2 PPT0
D1 –
Programmable timer 3–2 interrupt
R/W
R/W
level
priority register
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Programmable timer 1–0 interrupt
0
priority register
–
Level 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D0 –
00FF22 D7 –
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 ETM32 Clock timer 32 Hz interrupt enable register
D2 ETM8
D1 ETM2
D0 ETM1
Clock timer 8 Hz interrupt enable register
Clock timer 2 Hz interrupt enable register
Clock timer 1 Hz interrupt enable register
Interrupt
enable
Interrupt
disable
0
R/W
S1C88650 TECHNICAL MANUAL
EPSON
21
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(e) I/O Memory map (00FF23H–00FF28H)
Address Bit Name
00FF23 D7 –
D6 –
Function
1
–
–
–
–
–
0
–
–
–
–
–
SR R/W
Comment
Constantly "0" when
being read
–
–
–
–
–
–
–
–
–
–
D5 –
D4 –
D3 –
D2 ESERR Serial I/F (error) interrupt enable register
D1 ESREC Serial I/F (receiving) interrupt enable register
D0 ESTRA Serial I/F (transmitting) interrupt enable register
Interrupt
enable
Interrupt
disable
0
R/W
R/W
00FF24 D7 EK07
K07 interrupt enable
D6 EK06
D5 EK05
D4 EK04
D3 EK03
D2 EK02
D1 EK01
D0 EK00
00FF25 D7 ETC3
D6 ETU3
D5 ETC2
D4 ETU2
D3 ETC1
D2 ETU1
D1 ETC0
D0 ETU0
00FF26 D7 –
D6 –
K06 interrupt enable
K05 interrupt enable
K04 interrupt enable
Interrupt
enable
Interrupt
disable
0
K03 interrupt enable
K02 interrupt enable
K01 interrupt enable
K00 interrupt enable
PTM3 compare match interrupt enable
PTM3 underflow interrupt enable
PTM2 compare match interrupt enable
PTM2 underflow interrupt enable
PTM1 compare match interrupt enable
PTM1 underflow interrupt enable
PTM0 compare match interrupt enable
PTM0 underflow interrupt enable
–
Interrupt
enable
Interrupt
disable
0
R/W
–
–
–
–
–
–
–
–
Constantly "0" when
being read
–
D5 –
–
–
–
D4 –
–
–
–
D3 FTM32 Clock timer 32 Hz interrupt factor flag
(R)
(R)
D2 FTM8
D1 FTM2
D0 FTM1
Clock timer 8 Hz interrupt factor flag
Generated Not generated
0
R/W
Clock timer 2 Hz interrupt factor flag
(W)
(W)
Clock timer 1 Hz interrupt factor flag
Reset
No operation
00FF27 D7 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
(R)
(R)
D2 FSERR Serial I/F (error) interrupt factor flag
D1 FSREC Serial I/F (receiving) interrupt factor flag
D0 FSTRA Serial I/F (transmitting) interrupt factor flag
Generated Not generated
(W)
Reset
0
R/W
R/W
(W)
No operation
00FF28 D7 FK07
K07 interrupt factor flag
K06 interrupt factor flag
K05 interrupt factor flag
K04 interrupt factor flag
K03 interrupt factor flag
K02 interrupt factor flag
K01 interrupt factor flag
K00 interrupt factor flag
(R)
(R)
D6 FK06
D5 FK05
D4 FK04
D3 FK03
D2 FK02
D1 FK01
D0 FK00
Interrupt
factor is
generated
No interrupt
factor is
generated
0
(W)
(W)
Reset
No operation
22
EPSON
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(f) I/O Memory map (00FF29H–00FF31H)
Address Bit Name
00FF29 D7 FTC3
D6 FTU3
Function
1
0
SR R/W
Comment
PTM3 compare match interrupt factor flag
PTM3 underflow interrupt factor flag
PTM2 compare match interrupt factor flag
PTM2 underflow interrupt factor flag
PTM1 compare match interrupt factor flag
PTM1 underflow interrupt factor flag
PTM0 compare match interrupt factor flag
PTM0 underflow interrupt factor flag
–
(R)
(R)
Interrupt
factor is
generated
No interrupt
factor is
generated
D5 FTC2
D4 FTU2
0
R/W
D3 FTC1
D2 FTU1
(W)
(W)
D1 FTC0
Reset
No operation
D0 FTU0
00FF2A D7 –
D6 –
–
–
–
–
–
–
–
–
–
–
–
–
0
Constantly "0" when
being read
–
D5 –
–
D4 –
–
PPT7 PPT6 Priority
PPT5 PPT4
D3 PPT7
Programmable timer 7–6 interrupt
priority register
R/W
R/W
level
D2 PPT6
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D1 PPT5
Programmable timer 5–4 interrupt
priority register
0
D0 PPT4
00FF2C D7 ETC7
D6 ETU7
D5 ETC6
D4 ETU6
D3 ETC5
D2 ETU5
D1 ETC4
D0 ETU4
00FF2E D7 FTC7
D6 FTU7
PTM7 compare match interrupt enable
PTM7 underflow interrupt enable
PTM6 compare match interrupt enable
PTM6 underflow interrupt enable
PTM5 compare match interrupt enable
PTM5 underflow interrupt enable
PTM4 compare match interrupt enable
PTM4 underflow interrupt enable
PTM7 compare match interrupt factor flag
PTM7 underflow interrupt factor flag
PTM6 compare match interrupt factor flag
PTM6 underflow interrupt factor flag
PTM5 compare match interrupt factor flag
PTM5 underflow interrupt factor flag
PTM4 compare match interrupt factor flag
PTM4 underflow interrupt factor flag
Interrupt
enable
Interrupt
disable
0
R/W
(R)
(R)
Interrupt
factor is
No interrupt
factor is
D5 FTC6
D4 FTU6
generated
generated
0
R/W
D3 FTC5
D2 FTU5
(W)
(W)
D1 FTC4
Reset
No operation
D0 FTU4
00FF30 D7 MODE16_A PTM0–1 8/16-bit mode selection
16-bit x 1
Enable
–
8-bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_A External clock 0 noise rejecter selection
Disable
D5 –
D4 –
–
–
"0" when being read
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT0 PTM0 clock output control
D2 PTRUN0 PTM0 Run/Stop control
D1 PSET0 PTM0 preset
On
R/W
R/W
Run
Stop
Preset
No operation
W
"0" when being read
D0 CKSEL0 PTM0 input clock selection
External clock Internal clock
R/W
00FF31 D7 –
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
–
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT1 PTM1 clock output control
D2 PTRUN1 PTM1 Run/Stop control
D1 PSET1 PTM1 preset
On
Run
Preset
R/W
R/W
Stop
No operation
W
"0" when being read
D0 CKSEL1 PTM1 input clock selection
External clock Internal clock
R/W
S1C88650 TECHNICAL MANUAL
EPSON
23
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(g) I/O Memory map (00FF32H–00FF37H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF32 D7 RDR07 PTM0 reload data D7 (MSB)
D6 RDR06 PTM0 reload data D6
D5 RDR05 PTM0 reload data D5
D4 RDR04 PTM0 reload data D4
D3 RDR03 PTM0 reload data D3
D2 RDR02 PTM0 reload data D2
D1 RDR01 PTM0 reload data D1
D0 RDR00 PTM0 reload data D0 (LSB)
00FF33 D7 RDR17 PTM1 reload data D7 (MSB)
D6 RDR16 PTM1 reload data D6
D5 RDR15 PTM1 reload data D5
D4 RDR14 PTM1 reload data D4
D3 RDR13 PTM1 reload data D3
D2 RDR12 PTM1 reload data D2
D1 RDR11 PTM1 reload data D1
D0 RDR10 PTM1 reload data D0 (LSB)
00FF34 D7 CDR07 PTM0 compare data D7 (MSB)
D6 CDR06 PTM0 compare data D6
D5 CDR05 PTM0 compare data D5
D4 CDR04 PTM0 compare data D4
D3 CDR03 PTM0 compare data D3
D2 CDR02 PTM0 compare data D2
D1 CDR01 PTM0 compare data D1
D0 CDR00 PTM0 compare data D0 (LSB)
00FF35 D7 CDR17 PTM1 compare data D7 (MSB)
D6 CDR16 PTM1 compare data D6
D5 CDR15 PTM1 compare data D5
D4 CDR14 PTM1 compare data D4
D3 CDR13 PTM1 compare data D3
D2 CDR12 PTM1 compare data D2
D1 CDR11 PTM1 compare data D1
D0 CDR10 PTM1 compare data D0 (LSB)
00FF36 D7 PTM07 PTM0 data D7 (MSB)
D6 PTM06 PTM0 data D6
High
Low
1
1
0
0
1
1
R/W
R/W
R/W
R/W
R
High
High
High
High
High
Low
Low
Low
Low
Low
D5 PTM05 PTM0 data D5
D4 PTM04 PTM0 data D4
D3 PTM03 PTM0 data D3
D2 PTM02 PTM0 data D2
D1 PTM01 PTM0 data D1
D0 PTM00 PTM0 data D0 (LSB)
00FF37 D7 PTM17 PTM1 data D7 (MSB)
D6 PTM16 PTM1 data D6
D5 PTM15 PTM1 data D5
D4 PTM14 PTM1 data D4
R
D3 PTM13 PTM1 data D3
D2 PTM12 PTM1 data D2
D1 PTM11 PTM1 data D1
D0 PTM10 PTM1 data D0 (LSB)
24
EPSON
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(h) I/O Memory map (00FF38H–00FF3DH)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF38 D7 MODE16_B PTM2–3 8/16-bit mode selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_B External clock 1 noise rejecter selection
Enable
–
Disable
D5 –
–
–
Off
"0" when being read
D4 RPTOUT2 PTM2 inverted clock output control
D3 PTOUT2 PTM2 clock output control
D2 PTRUN2 PTM2 Run/Stop control
D1 PSET2 PTM2 preset
On
R/W
R/W
R/W
W
On
Off
Run
Preset
Stop
No operation
"0" when being read
D0 CKSEL2 PTM2 input clock selection
External clock Internal clock
R/W
00FF39 D7 –
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
–
–
–
Off
D4 RPTOUT3 PTM3 inverted clock output control
D3 PTOUT3 PTM3 clock output control
D2 PTRUN3 PTM3 Run/Stop control
D1 PSET3 PTM3 preset
On
On
Run
Preset
R/W
R/W
R/W
W
Off
Stop
No operation
"0" when being read
D0 CKSEL3 PTM3 input clock selection
00FF3A D7 RDR27 PTM2 reload data D7 (MSB)
D6 RDR26 PTM2 reload data D6
External clock Internal clock
R/W
D5 RDR25 PTM2 reload data D5
D4 RDR24 PTM2 reload data D4
High
High
High
High
Low
Low
Low
Low
1
1
0
0
R/W
R/W
R/W
R/W
D3 RDR23 PTM2 reload data D3
D2 RDR22 PTM2 reload data D2
D1 RDR21 PTM2 reload data D1
D0 RDR20 PTM2 reload data D0 (LSB)
00FF3B D7 RDR37 PTM3 reload data D7 (MSB)
D6 RDR36 PTM3 reload data D6
D5 RDR35 PTM3 reload data D5
D4 RDR34 PTM3 reload data D4
D3 RDR33 PTM3 reload data D3
D2 RDR32 PTM3 reload data D2
D1 RDR31 PTM3 reload data D1
D0 RDR30 PTM3 reload data D0 (LSB)
00FF3C D7 CDR27 PTM2 compare data D7 (MSB)
D6 CDR26 PTM2 compare data D6
D5 CDR25 PTM2 compare data D5
D4 CDR24 PTM2 compare data D4
D3 CDR23 PTM2 compare data D3
D2 CDR22 PTM2 compare data D2
D1 CDR21 PTM2 compare data D1
D0 CDR20 PTM2 compare data D0 (LSB)
00FF3D D7 CDR37 PTM3 compare data D7 (MSB)
D6 CDR36 PTM3 compare data D6
D5 CDR35 PTM3 compare data D5
D4 CDR34 PTM3 compare data D4
D3 CDR33 PTM3 compare data D3
D2 CDR32 PTM3 compare data D2
D1 CDR31 PTM3 compare data D1
D0 CDR30 PTM3 compare data D0 (LSB)
S1C88650 TECHNICAL MANUAL
EPSON
25
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(i) I/O Memory map (00FF3EH–00FF41H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF3E D7 PTM27 PTM2 data D7 (MSB)
D6 PTM26 PTM2 data D6
D5 PTM25 PTM2 data D5
D4 PTM24 PTM2 data D4
High
Low
1
R
D3 PTM23 PTM2 data D3
D2 PTM22 PTM2 data D2
D1 PTM21 PTM2 data D1
D0 PTM20 PTM2 data D0 (LSB)
00FF3F D7 PTM37 PTM3 data D7 (MSB)
D6 PTM36 PTM3 data D6
D5 PTM35 PTM3 data D5
D4 PTM34 PTM3 data D4
High
Low
1
R
D3 PTM33 PTM3 data D3
D2 PTM32 PTM3 data D2
D1 PTM31 PTM3 data D1
D0 PTM30 PTM3 data D0 (LSB)
00FF40 D7 WDEN Watchdog timer enable
D6 FOUT2 FOUT frequency selection
FOUT2 FOUT1 FOUT0
Enable
Disable
1
0
R/W
R/W
Frequency
fOSC3 / 8
fOSC3 / 4
fOSC3 / 2
fOSC3 / 1
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D5 FOUT1
D4 FOUT0
0
0
R/W
R/W
D3 FOUTON FOUT output control
D2 WDRST Watchdog timer reset
D1 TMRST Clock timer reset
On
Off
0
–
–
0
R/W
W
Reset
Reset
Run
No operation
No operation
Stop
Constantly "0" when
being read
W
D0 TMRUN Clock timer Run/Stop control
R/W
00FF41 D7 TMD7
D6 TMD6
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
Clock timer data
1 Hz
2 Hz
D5 TMD5
4 Hz
D4 TMD4
8 Hz
High
Low
0
R
D3 TMD3
16 Hz
32 Hz
64 Hz
D2 TMD2
D1 TMD1
D0 TMD0
Clock timer data 128 Hz
26
EPSON
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(j) I/O Memory map (00FF48H–00FF4BH)
Address Bit Name
00FF48 D7 –
D6 EPR
Function
1
0
SR R/W
Comment
–
–
–
–
"0" when being read
Parity enable register
Parity mode selection
Clock source selection
SCS1 SCS0
With parity Non parity
0
0
0
R/W Only for
D5 PMD
Odd
Even
R/W asynchronous mode
R/W In the clock synchro-
nous slave mode,
D4 SCS1
Clock source
1
1
0
0
1
0
1
0
Programmable timer
fOSC3 / 4
external clock is
D3 SCS0
D2 SMD1
D1 SMD0
0
0
0
R/W selected.
fOSC3 / 8
fOSC3 / 16
Serial I/F mode selection
SMD1 SMD0
R/W
R/W
Mode
1
1
0
0
1
0
1
0
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
D0 ESIF
00FF49 D7 –
D6 FER
Serial I/F enable register
Serial I/F
–
I/O port
–
0
–
0
R/W
–
"0" when being read
R/W Only for
asynchronous mode
R/W
Serial I/F framing error flag
R
W
R
Error
No error
Reset (0) No operation
Error No error
Reset (0) No operation
Error No error
Reset (0) No operation
D5 PER
D4 OER
Serial I/F parity error flag
Serial I/F overrun error flag
0
0
0
W
R
R/W
R/W
W
R
D3 RXTRG Serial I/F receive trigger/status
Run
Stop
No operation
Disable
W
Trigger
Enable
Run
D2 RXEN
Serial I/F receive enable
0
0
R/W
R/W
D1 TXTRG Serial I/F transmit trigger/status
R
Stop
W
Trigger
Enable
No operation
Disable
D0 TXEN
Serial I/F transmit enable
0
R/W
00FF4A D7 TRXD7 Serial I/F transmit/Receive data D7 (MSB)
D6 TRXD6 Serial I/F transmit/Receive data D6
D5 TRXD5 Serial I/F transmit/Receive data D5
D4 TRXD4 Serial I/F transmit/Receive data D4
D3 TRXD3 Serial I/F transmit/Receive data D3
D2 TRXD2 Serial I/F transmit/Receive data D2
D1 TRXD1 Serial I/F transmit/Receive data D1
D0 TRXD0 Serial I/F transmit/Receive data D0 (LSB)
High
Low
X
R/W
00FF4B D7 –
D6 –
–
–
–
–
–
–
–
–
–
0
0
Constantly "0" when
being read
–
–
–
D5 –
–
–
–
D4 –
–
–
–
–
D3 –
–
–
–
D2 –
–
–
D1 STPB
D0 SDP
Serial I/F stop bit selection
2 bits
1 bit
R/W
R/W
Serial I/F data input/output permutation selection MSB first
LSB first
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(k) I/O Memory map (00FF52H–00FF60H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF52 D7 KCP07 K07 input comparison register
D6 KCP06 K06 input comparison register
D5 KCP05 K05 input comparison register
D4 KCP04 K04 input comparison register
D3 KCP03 K03 input comparison register
D2 KCP02 K02 input comparison register
D1 KCP01 K01 input comparison register
D0 KCP00 K00 input comparison register
Interrupt
generated
at falling
edge
Interrupt
generated
at rising
edge
1
–
1
R/W
00FF54 D7 K07D
D6 K06D
K07 input port data
K06 input port data
K05 input port data
K04 input port data
K03 input port data
K02 input port data
K01 input port data
K00 input port data
D5 K05D
D4 K04D
High level
input
Low level
input
R
D3 K03D
D2 K02D
D1 K01D
D0 K00D
00FF56 D7 PULK07 K07 pull-up control register
D6 PULK06 K06 pull-up control register
D5 PULK05 K05 pull-up control register
D4 PULK04 K04 pull-up control register
D3 PULK03 K03 pull-up control register
D2 PULK02 K02 pull-up control register
D1 PULK01 K01 pull-up control register
D0 PULK00 K00 pull-up control register
On
Off
R/W
00FF58 D7 –
–
–
–
–
0
"0" when being read
D6 CTK02H K04–K07 port chattering-eliminate setup
R/W
R/W
R/W
(Input level check time)
CTK02H CTK01H CTK00H
Check time
[sec]
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D5 CTK01H
D4 CTK00H
D3 –
0
0
–
–
–
–
0
"0" when being read
D2 CTK02L K00–K03 port chattering-eliminate setup
R/W
R/W
R/W
(Input level check time)
CTK02L CTK01L CTK00L
Check time
[sec]
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D1 CTK01L
D0 CTK00L
0
0
00FF60 D7 IOC07 P07 I/O control register
D6 IOC06 P06 I/O control register
D5 IOC05 P05 I/O control register
D4 IOC04 P04 I/O control register
D3 IOC03 P03 I/O control register
D2 IOC02 P02 I/O control register
D1 IOC01 P01 I/O control register
D0 IOC00 P00 I/O control register
Output
Input
0
R/W
28
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(l) I/O Memory map (00FF61H–00FF70H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF61 D7 IOC17 P17 I/O control register
D6 IOC16 P16 I/O control register
D5 IOC15 P15 I/O control register
D4 IOC14 P14 I/O control register
D3 IOC13 P13 I/O control register
D2 IOC12 P12 I/O control register
D1 IOC11 P11 I/O control register
D0 IOC10 P10 I/O control register
Output
Input
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
00FF62 D7 P07D
D6 P06D
P07 I/O port data
P06 I/O port data
P05 I/O port data
P04 I/O port data
P03 I/O port data
P02 I/O port data
P01 I/O port data
P00 I/O port data
P17 I/O port data
P16 I/O port data
P15 I/O port data
P14 I/O port data
P13 I/O port data
P12 I/O port data
P11 I/O port data
P10 I/O port data
D5 P05D
D4 P04D
High
High
On
Low
Low
Off
D3 P03D
D2 P02D
D1 P01D
D0 P00D
00FF63 D7 P17D
D6 P16D
D5 P15D
D4 P14D
D3 P13D
D2 P12D
D1 P11D
D0 P10D
00FF64 D7 PULP07 P07 pull-up control register
D6 PULP06 P06 pull-up control register
D5 PULP05 P05 pull-up control register
D4 PULP04 P04 pull-up control register
D3 PULP03 P03 pull-up control register
D2 PULP02 P02 pull-up control register
D1 PULP01 P01 pull-up control register
D0 PULP00 P00 pull-up control register
00FF65 D7 PULP17 P17 pull-up control register
D6 PULP16 P16 pull-up control register
D5 PULP15 P15 pull-up control register
D4 PULP14 P14 pull-up control register
D3 PULP13 P13 pull-up control register
D2 PULP12 P12 pull-up control register
D1 PULP11 P11 pull-up control register
D0 PULP10 P10 pull-up control register
On
Off
00FF70 D7 –
D6 –
R/W register
R/W register
R/W register
R/W register
1
1
1
1
0
0
0
0
0
0
0
0
R/W Reserved register
R/W
R/W
R/W
D5 –
D4 –
D3 HZR1H R14–R17 high impedance control
D2 HZR1L R10–R13 high impedance control
D1 HZR0H R04–R07 high impedance control
D0 HZR0L R00–R03 high impedance control
High
Comple-
mentary
0
R/W
impedance
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(m) I/O Memory map (00FF71H–00FF76H)
Address Bit Name
00FF71 D7 –
D6 –
Function
1
1
1
0
0
0
SR R/W
Comment
R/W register
R/W register
0
0
R/W Reserved register
R/W
D5 HZR25 R25 high impedance control
D4 HZR24 R24 high impedance control
D3 HZR23 R23 high impedance control
D2 HZR22 R22 high impedance control
D1 HZR21 R21 high impedance control
D0 HZR20 R20 high impedance control
High
Comple-
mentary
0
R/W
impedance
00FF72 D7 –
R/W register
R/W register
R/W register
R/W register
1
1
1
1
0
0
0
0
0
0
0
0
R/W Reserved register
D6 –
D5 –
D4 –
R/W
R/W
R/W
D3 HZR33 R33 high impedance control
D2 HZR32 R32 high impedance control
D1 HZR31 R31 high impedance control
D0 HZR30 R30 high impedance control
High
Comple-
mentary
0
R/W
R/W
impedance
00FF73 D7 R07D
R07 output port data
R06 output port data
R05 output port data
R04 output port data
R03 output port data
R02 output port data
R01 output port data
R00 output port data
R17 output port data
R16 output port data
R15 output port data
R14 output port data
R13 output port data
R12 output port data
R11 output port data
R10 output port data
R/W register
D6 R06D
D5 R05D
D4 R04D
D3 R03D
D2 R02D
D1 R01D
D0 R00D
00FF74 D7 R17D
D6 R16D
D5 R15D
D4 R14D
D3 R13D
D2 R12D
D1 R11D
D0 R10D
00FF75 D7 –
D6 –
High
Low
1
High
Low
1
R/W
1
1
0
0
0
0
R/W Reserved register
R/W
R/W register
D5 R25D
D4 R24D
D3 R23D
D2 R22D
D1 R21D
D0 R20D
00FF76 D7 –
D6 –
R25 output port data
R24 output port data
R23 output port data
R22 output port data
R21 output port data
R20 output port data
R/W register
High
Low
1
R/W
1
1
1
1
0
0
0
0
0
0
0
0
R/W Reserved register
R/W register
R/W
R/W
R/W
D5 –
R/W register
D4 –
R/W register
D3 R33D
D2 R32D
D1 R31D
D0 R30D
R33 output port data
R32 output port data
R31 output port data
R30 output port data
High
Low
1
R/W
30
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(n) I/O Memory map (00FFB0H–00FFB5H)
Address Bit Name
Function
1
0
SR R/W
Comment
00FFB0 D7 MODE16_C PTM4–5 8/16-bit mode selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_C External clock 2 noise rejecter selection
Enable
Disable
D5 –
D4 –
D3 –
–
–
1
–
"0" when being read
R/W register
R/W register
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN4 PTM4 Run/Stop control
D1 PSET4 PTM4 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL4 PTM4 input clock selection
External clock Internal clock
R/W
00FFB1 D7 –
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
–
–
–
–
R/W register
R/W register
1
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN5 PTM5 Run/Stop control
D1 PSET5 PTM5 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL5 PTM5 input clock selection
00FFB2 D7 RDR47 PTM4 reload data D7 (MSB)
D6 RDR46 PTM4 reload data D6
External clock Internal clock
R/W
D5 RDR45 PTM4 reload data D5
D4 RDR44 PTM4 reload data D4
High
High
High
High
Low
Low
Low
Low
1
1
0
0
R/W
R/W
R/W
R/W
D3 RDR43 PTM4 reload data D3
D2 RDR42 PTM4 reload data D2
D1 RDR41 PTM4 reload data D1
D0 RDR40 PTM4 reload data D0 (LSB)
00FFB3 D7 RDR57 PTM5 reload data D7 (MSB)
D6 RDR56 PTM5 reload data D6
D5 RDR55 PTM5 reload data D5
D4 RDR54 PTM5 reload data D4
D3 RDR53 PTM5 reload data D3
D2 RDR52 PTM5 reload data D2
D1 RDR51 PTM5 reload data D1
D0 RDR50 PTM5 reload data D0 (LSB)
00FFB4 D7 CDR47 PTM4 compare data D7 (MSB)
D6 CDR46 PTM4 compare data D6
D5 CDR45 PTM4 compare data D5
D4 CDR44 PTM4 compare data D4
D3 CDR43 PTM4 compare data D3
D2 CDR42 PTM4 compare data D2
D1 CDR41 PTM4 compare data D1
D0 CDR40 PTM4 compare data D0 (LSB)
00FFB5 D7 CDR57 PTM5 compare data D7 (MSB)
D6 CDR56 PTM5 compare data D6
D5 CDR55 PTM5 compare data D5
D4 CDR54 PTM5 compare data D4
D3 CDR53 PTM5 compare data D3
D2 CDR52 PTM5 compare data D2
D1 CDR51 PTM5 compare data D1
D0 CDR50 PTM5 compare data D0 (LSB)
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(o) I/O Memory map (00FFB6H–00FFBBH)
Address Bit Name
Function
1
0
SR R/W
Comment
00FFB6 D7 PTM47 PTM4 data D7 (MSB)
D6 PTM46 PTM4 data D6
D5 PTM45 PTM4 data D5
D4 PTM44 PTM4 data D4
High
Low
1
R
D3 PTM43 PTM4 data D3
D2 PTM42 PTM4 data D2
D1 PTM41 PTM4 data D1
D0 PTM40 PTM4 data D0 (LSB)
00FFB7 D7 PTM57 PTM5 data D7 (MSB)
D6 PTM56 PTM5 data D6
D5 PTM55 PTM5 data D5
D4 PTM54 PTM5 data D4
High
Low
1
R
D3 PTM53 PTM5 data D3
D2 PTM52 PTM5 data D2
D1 PTM51 PTM5 data D1
D0 PTM50 PTM5 data D0 (LSB)
00FFB8 D7 MODE16_D PTM6–7 8/16-bit mode selection
D6 PTNREN_D External clock 3 noise rejecter selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
Enable
Disable
D5 –
D4 –
D3 –
–
–
1
–
"0" when being read
R/W register
R/W register
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN6 PTM6 Run/Stop control
D1 PSET6 PTM6 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL6 PTM6 input clock selection
External clock Internal clock
R/W
00FFB9 D7 –
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
–
–
–
–
R/W register
R/W register
1
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN7 PTM7 Run/Stop control
D1 PSET7 PTM7 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL7 PTM7 input clock selection
00FFBA D7 RDR67 PTM6 reload data D7 (MSB)
D6 RDR66 PTM6 reload data D6
D5 RDR65 PTM6 reload data D5
D4 RDR64 PTM6 reload data D4
D3 RDR63 PTM6 reload data D3
D2 RDR62 PTM6 reload data D2
D1 RDR61 PTM6 reload data D1
D0 RDR60 PTM6 reload data D0 (LSB)
00FFBB D7 RDR77 PTM7 reload data D7 (MSB)
D6 RDR76 PTM7 reload data D6
D5 RDR75 PTM7 reload data D5
D4 RDR74 PTM7 reload data D4
D3 RDR73 PTM7 reload data D3
D2 RDR72 PTM7 reload data D2
D1 RDR71 PTM7 reload data D1
D0 RDR70 PTM7 reload data D0 (LSB)
External clock Internal clock
R/W
High
Low
1
R/W
High
Low
1
R/W
32
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(p) I/O Memory map (00FFBCH–00FFBFH)
Address Bit Name
Function
1
0
SR R/W
Comment
00FFBC D7 CDR67 PTM6 compare data D7 (MSB)
D6 CDR66 PTM6 compare data D6
D5 CDR65 PTM6 compare data D5
D4 CDR64 PTM6 compare data D4
D3 CDR63 PTM6 compare data D3
D2 CDR62 PTM6 compare data D2
D1 CDR61 PTM6 compare data D1
D0 CDR60 PTM6 compare data D0 (LSB)
00FFBD D7 CDR77 PTM7 compare data D7 (MSB)
D6 CDR76 PTM7 compare data D6
D5 CDR75 PTM7 compare data D5
D4 CDR74 PTM7 compare data D4
D3 CDR73 PTM7 compare data D3
D2 CDR72 PTM7 compare data D2
D1 CDR71 PTM7 compare data D1
D0 CDR70 PTM7 compare data D0 (LSB)
00FFBE D7 PTM67 PTM6 data D7 (MSB)
D6 PTM66 PTM6 data D6
High
Low
0
0
1
1
R/W
R/W
R
High
High
High
Low
Low
Low
D5 PTM65 PTM6 data D5
D4 PTM64 PTM6 data D4
D3 PTM63 PTM6 data D3
D2 PTM62 PTM6 data D2
D1 PTM61 PTM6 data D1
D0 PTM60 PTM6 data D0 (LSB)
00FFBF D7 PTM77 PTM7 data D7 (MSB)
D6 PTM76 PTM7 data D6
D5 PTM75 PTM7 data D5
D4 PTM74 PTM7 data D4
R
D3 PTM73 PTM7 data D3
D2 PTM72 PTM7 data D2
D1 PTM71 PTM7 data D1
D0 PTM70 PTM7 data D0 (LSB)
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
Below is a description of the how these settings are
to be made.
5.2 System Controller and Bus Control
The system controller is a management unit which
sets such items as the bus mode in accordance with
memory system configuration factors.
For the purposes of controlling the system, the
following settings can be performed in software:
5.2.1 Bus mode and CPU mode settings
The S1C88650 has two bus modes and two CPU
modes and the software must select appropriate
modes according to the external memory size
connected to the S1C88650.
(1) Bus and CPU mode settings
____
(2) Chip enable (CE) signal output settings
(3) WAIT state settings for external memory
(4) Page address setting of the stack pointer
As shown in Table 5.2.1.1, these modes are speci-
fied usng the registers BUSMOD and CPUMOD.
Table 5.2.1.1 Bus and CPU mode settings
MCU/MPU
terminal
Setting value
BUSMOD CPUMOD
Bus mode CPU mode
Configuration of external memory
1 (MCU mode)
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Expansion Maximum ROM+RAM>64K bytes (Program≥64K bytes)
Minimum ROM+RAM>64K bytes (Program<64K bytes)
Single chip
Maximum None (Program≥64K bytes)
Minimum None (Program<64K bytes)
0 (MPU mode)
Expansion Maximum ROM+RAM>64K bytes (Program≥64K bytes)
Minimum ROM+RAM>64K bytes (Program<64K bytes)
Maximum ROM+RAM>64K bytes (Program≥64K bytes)
Minimum ROM+RAM>64K bytes (Program<64K bytes)
Table 5.2.1.2 I/O terminal settings
The function of I/ O terminals is set as shown in
Table 5.2.1.2 in accordance with mode selection.
At initial reset, the bus mode (CPU mode) is set as
explained below.
Bus mode
Terminal
Single chip
Output port R00
Output port R01
Output port R02
Output port R03
Output port R04
Output port R05
Output port R06
Output port R07
Output port R10
Output port R11
Output port R12
Output port R13
Output port R14
Output port R15
Output port R16
Output port R17
Output port R20
Output port R21
Output port R22
Output port R23
Output port R24
Output port R25
I/O port P00
Expansion
R00
R01
R02
R03
R04
R05
R06
R07
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
R23
R24
R25
P00
P01
P02
P03
P04
P05
P06
P07
Address bus A0
Address bus A1
Address bus A2
Address bus A3
Address bus A4
Address bus A5
Address bus A6
Address bus A7
Address bus A8
Address bus A9
Address bus A10
Address bus A11
Address bus A12
Address bus A13
Address bus A14
Address bus A15
Address bus A16
Address bus A17
Address bus A18
Address bus A19
RD signal
•
In MCU mode:
At initial reset, the S1C88650 is set in single chip
mode (minimum).
Accordingly, in MCU mode, even if a memory
has been externally expanded, the system is
activated by the program written to internal
ROM.
In the system with externally expanded
memory, perform the applicable bus mode
settings during the initialization routine
originating in internal ROM.
•
In MPU mode:
At initial reset, the S1C88650 is set in expansion
mode (minimum).
Therefore, the internal ROM will be disabled.
_____
5.2.2 Address decoder (CE output) settings
WR signal
Data bus D0
As explained in Section 3.6.4, the S1C88650 is
equipped with address decoders that ca_n__o__ut_p__u__t a
maximum of three chip enable signals (CE0–CE2) to
external devices.
I/O port P01
Data bus D1
I/O port P02
Data bus D2
I/O port P03
Data bus D3
I/O port P04
I/O port P05
I/O port P06
I/O port P07
Data bus D4
Data bus D5
Data bus D6
Data bus D7
34
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
_____ _____
Table 5.2.2.1 Address settings of CE0–CE2
Address range (expansion mode)
CE signal
MCU mode
MPU mode
000000H–00D7FFH, 010000H–0FFFFFH
100000H–1FFFFFH
CE0
CE1
CE2
300000H–3FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
200000H–2FFFFFH
_____
The output terminals and output circuits for CE0–
CE2 are shared with output ports R30–R32. At
initial reset, they are set as output port terminals.
Consequently, WAIT state settings in single chip
mode are meaningless.
With regard to WAIT insertion timing, see Section
3.6.5, "WAIT control".
_____
For this reason, when operating in expansion mode,
_____
the ports to be used as CE signal output terminals
must be set as such.
This setting is performed through software which
5.2.4 Setting the bus authority release
request signal
writes "1" to registers CE0–CE2 corresponding the
____
With systems performing DMA transfer, the bus
CE signals to be used.
________
authority release request signal (BREQ) input
Table 5.2.2.1 shows the address range assigned to
________
____
terminal and acknowledge signal (BACK) output
term_i_n__a_l__h_ave to be set.
the three chip enable (CE) signals.
The arrangement of memory space for external
devices does not necessarily have to be continuous
from a subordinate address and any of the chip
enable signals can be used to assign areas in
memory. However, in the MP_U___m_ ode, program
The BREQ input terminal is shared with input port
________
terminal K03 and the BACK output terminal with
output port terminal R33. At initial reset, these
terminal facilities are set as input port terminal and
output port terminal, respect_i_v_e__l_y_._ T_h_e___t_e_r_minals
can be altered to function as BREQ/ BACK termi-
nals by writing a "1" to register EBR.
memory must be assigned to CE0.
____
The CE signals are only output when the appointed
external memory area is accessed and are not
output when internal memory is accessed.
For details on bus authority release, see "3.6.6 Bus
authority release state" and "S1C88 Core CPU
Manual".
5.2.3 WAIT state settings
In order to insure accessing of external low speed
devices during high speed operations, the S1C88650
is equipped with a WAIT function which prolongs
access time.
The number of wait states inserted can be selected
from a choice of eight as shown in Table 5.2.3.1 by
means of registers WT0–WT2.
5.2.5 Stack page setting
Although the stack area used to evacuate registers
during subroutine calls can be arbitrarily moved to
any area in data RAM using the stack pointer SP, its
page address is set in registers SPP0–SPP7 in I/ O
memory.
At initial reset, SPP0–SPP7 are set to "00H" (page 0).
Table 5.2.3.1 Setting the number of WAIT states
Since the internal RAM is arranged on page 0
(00D800H–00F7FFH), the stack area in single chip
mode is inevitably located in page 0.
In order to place the stack area at the final address
in internal RAM, the stack pointer SP is placed at an
initial setting of "F800H". (SP is pre-decremented.)
WT2
WT1
WT0 Number of inserted states
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14
12
10
8
6
In the expansion mode, to place the stack in
external expanded RAM, set a corresponding page
to SPP0–SPP7. The page addresses to which SPP0–
SPP7 can be set are 00H–27H and must be within a
RAM area.
4
2
No wait
*
The length of one state is a 1/2 clock cycle.
WAIT states set in software are inserted between
bus cycle states T3–T4.
*
A page is each recurrent 64K division of data
memory beginning at address zero.
Note, however, that WAIT states cannot be inserted
when an internal register and internal memory are
being accessed and when operating with the OSC1
oscillation circuit (see "5.4 Oscillation Circuits").
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
5.2.6 Control of system controller
Table 5.2.6.1 shows the control bits for the system controller.
Table 5.2.6.1 System controller control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF00 D7 BUSMOD Bus mode
(MCU) D6 CPUMOD CPU mode
Expansion Single chip
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W
R/W
Maximum
Minimum
D5 –
R/W register
R/W register
R/W register
CE2 (R32)
CE1 (R31)
CE0 (R30)
1
1
1
0
0
0
R/W Reserved register
R/W
D4 –
D3 –
R/W
D2 CE2
D1 CE1
D0 CE0
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
R/W In Single chip mode,
R/W these setting are fixed
R/W at DC output.
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
00FF00 D7 BUSMOD Bus mode
Expansion
–
R
Expansion mode only
(MPU) D6 CPUMOD CPU mode
Maximum
Minimum
R/W
D5 –
D4 –
R/W register
R/W register
R/W register
CE2 (R32)
CE1 (R31)
CE0 (R30)
1
1
1
0
0
0
R/W Reserved register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D3 –
D2 CE2
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
D1 CE1
D0 CE0
00FF01 D7 SPP7
D6 SPP6
D5 SPP5
D4 SPP4
D3 SPP3
D2 SPP2
D1 SPP1
D0 SPP0
00FF02 D7 EBR
Stack pointer page address
(MSB)
1
0
1
0
< SP page allocatable address >
• Single chip mode: only 0 page
• Expansion mode: 0–27H page
1
0
1
0
1
0
1
1
0
0
(LSB)
K03
1
0
Bus release enable register
BREQ
BACK
Input port
Output port
(K03 and R33 terminal specification) R33
D6 WT2
D5 WT1
D4 WT0
Wait control register
0
0
0
R/W
R/W
R/W
Number
of state
WT2
WT1
WT0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14
12
10
8
6
4
2
No wait
D3 CLKCHG CPU operating clock switch
OSC3
OSC1
1
1
0
0
R/W
D2 SOSC3 OSC3 oscillation On/Off control
On
1
Off
0
R/W
D1 –
D0 –
R/W register
R/W register
R/W Reserved register
R/W
1
0
____
Note: All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.
36
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
Since a carry and borrow from/ to the stack pointer
SP is not reflected in register SPP, the upper limit
on continuous use of the stack area is 64K bytes.
At initial reset, this register is set to "00H" (page 0).
BUSMOD, CPUMOD: 00FF00H•D7, D6
Bus mode and CPU mode are set as shown in Table
5.2.6.2.
Table 5.2.6.2 Bus mode and CPU mode settings
Note: To avoid a malfunction from an interrupt
MCU/MPU
Setting value
generated before the bus configuration is
Bus mode CPU mode
_____
terminal BUSMOD CPUMOD
initialized, all interrupts including NMI are
disabled, until you write an optional value
into "00FF01H" address. Furthermore, to
avoid generating an interrupt while the st_a_c__k_
area is being set, all interrupts including NMI
are disabled in one instruction execution
period after writing to address "00FF01H".
1 (MCU mode)
0 (MPU mode)
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Expansion Maximum
Minimum
Single
chip
Maximum
Minimum
Expansion Maximum
Minimum
Maximum
Minimum
WT0–WT2: 00FF02H•D4–D6
How WAIT state settings are performed.
The number of WAIT states to be inserted based on
register settings is as shown in Table 5.2.6.3.
The single chip mode configuration is only possible
when this IC is used in the MCU mode. The single
chip mode setting is incompatible with the MPU
mode, since this mode does not utilize internal
ROM.
At initial reset, in the MCU mode the unit is set to
single chip (minimum) mode and in the MPU mode
the expansion (minimum) mode is used to select
the applicable mode.
Table 5.2.6.3 Setting WAIT states
WT2
WT1
WT0 Number of inserted states
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14
12
10
8
6
CE0–CE2: 00FF00H•D0–D2
4
2
_____
Sets the CE output terminals being used.
_____
No wait
When "1" is written: CE output enable
_____
When "0" is written: CE output disable
*
The length of one state is a 1/2 clock cycle.
Reading:
Valid
At initial reset, this register is set to "0" (no wait).
____
CE output is enabled when a "1" is written to
registers CE0–CE2 which correspond to the CE
____
EBR: 00FF02H•D7
________ ________
output being used. A "0" written to any of the
Sets the BREQ/ BACK terminals function.
____
________ ________
registers disables CE signal output from that
terminal and it reverts to its alternate function as an
output port terminal (R30–R32).
At initial reset, register CE0 is set to "0" in the MCU
mode and in the MPU mode, "1" is set in the
register. Registers CE1–CE2 are always set to "0"
regardless of the MCU/ MPU mode setting.
When "1" is written: BREQ/ BACK enabled
________ ________
When "0" is written: BREQ/ BACK disabled
Reading:
Valid
________
________
How BREQ and BACK terminal functions are set.
________ ________
Writing "1" to EBR enables BREQ/ BACK input/
________
output. Writing "0" sets the BREQ terminal as input
________
port terminal K03 and the BACK terminal as output
Note: To avoid a malfunction from an interrupt
port terminal R33.
________ ________
generated before the bus configuration is
_____
At initial reset, EBR is set to "0" (BREQ/ BACK
disabled).
initialized, all interrupts including NMI are
masked until you write an optional value into
address "00FF00H".
SPP0–SPP7: 00FF01H
Sets the page address of stack area.
In single chip mode, set page address to "00H". In
expansion mode, it can be set to any value within
the range "00H"–"27H".
S1C88650 TECHNICAL MANUAL
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37
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
5.2.7 Programming notes
______
(1) All the interrupts including NMI are masked,
until you write the optional value into both the
"00FF00H" and "00FF01H" addresses. Conse-
quently, even if you do not change the content
of this address (You use the initial value, as is.),
you should still be sure to perform the writing
operation using the initialization routine.
(2) When setting stack fields, including page
addresses as well, you should write them in the
order of the register SPP ("00FF01H") and the
stack pointer SP.
Example: When setting the "178000H" address
LD
LD
LD
LD
EP, #00H
HL, #0FF01H
[HL], #17H
SP, #8000H
During this period the
interrupts (including
_______
NMI) are masked.
38
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)
Normally, this routine is integrated at points that
are regularly being processed.
5.3 Watchdog Timer
The watchdog timer continues to operate during
5.3.1 Configuration of watchdog timer
HALT and when HALT state is continuous for
longer than the selected period, the CPU starts
exception processing.
The S1C88650 is equipped with a watchdog timer
driven by OSC1 as source oscillation. The watchdog
timer must be reset periodically by software, and if
reset does not take place within the selected period,
a non-maskable interrupt signal is generated and
output to the CPU. The watchdog timer starts
operating after initial reset, however, it can be
During SLEEP, the watchdog timer is stopped.
Note: The NMI generation cycles in the watchdog
timer mask option list represent maximum
values. A maximum minus (<selected
optional cycle> / 4) seconds of error occurs
depending on the watchdog timer reset
timing. For example, when 131072/fOSC1 is
selected by mask option, the actual NMI
generation cycle is within the range of
98304/fOSC1 to 131072/fOSC1 seconds.
stopped by the software.
_______
The NMI generation cycle by the watchdog timer
can be selected by mask option.
_____
Watchdog timer NMI generation cycle
■ 32768/ fOSC1
(0.75–1-sec cycle when fOSC1 = 32 kHz)
■ 65536/ fOSC1
(1.5–2-sec cycle when fOSC1 = 32 kHz)
■ 131072/ fOSC1
5.3.2 Interrupt function
In cases where the watchdog timer is not periodi-
cally reset in software, the watchdog timer outputs
______
an interrupt signal to the CPU's NMI (level 4) input.
Unmaskable and taking priority over other inter-
rupts, this interrupt triggers the generation of
(3–4-sec cycle when fOSC1 = 32 kHz)
■ 262144/ fOSC1
(6–8-sec cycle when fOSC1 = 32 kHz)
exception processing. See the "S1C88 Core CPU
______
Manual" for more details on NMI exception
processing.
This exception processing vector is set at 000004H.
Figure 5.3.1.1 is a block diagram of the watchdog
timer.
By running watchdog timer reset during the main
routine of the program, it is possible to detect
program runaway as if watchdog timer processing
had not been applied.
Mask option
1/16384
1/32768
1/65536
1/131072
OSC1
oscillation
circuit
fOSC1
Divider
Watchdog timer
1/4
Non-maskable
interrupt (NMI)
WDEN
Watchdog timer
enable signal
WDRST
Watchdog timer
reset signal
Fig. 5.3.1.1 Block diagram of watchdog timer
S1C88650 TECHNICAL MANUAL
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39
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)
5.3.3 Control of watchdog timer
Table 5.3.3.1 shows the control bits for the watchdog timer.
Table 5.3.3.1 Watchdog timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF40 D7 WDEN Watchdog timer enable
D6 FOUT2 FOUT frequency selection
FOUT2 FOUT1 FOUT0
Enable
Disable
1
0
R/W
R/W
Frequency
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D5 FOUT1
D4 FOUT0
0
0
R/W
R/W
D3 FOUTON FOUT output control
D2 WDRST Watchdog timer reset
D1 TMRST Clock timer reset
On
Off
0
–
–
0
R/W
W
Reset
Reset
Run
No operation
No operation
Stop
Constantly "0" when
being read
W
D0 TMRUN Clock timer Run/Stop control
R/W
WDEN: 00FF40H•D7
5.3.4 Programming notes
Selects whether the watchdog timer is used
(enabled) or not (disabled).
(1) When the watchdog timer is being used, the
software must reset it within the cycles selected
by mask option.
When "1" is written: Enabled
When "0" is written: Disabled
(2) Do not_e_x__e_c_ute the SLP instruction for 2 msec
after a NMI interrupt has occurred (when fOSC1
is 32.768 kHz).
Reading:
When "1" is written to the WDEN register, the
watchdog timer starts count operation. When "0" is
Valid
(3) Because the watchdog timer is set in operation
state by initial reset, set the watchdog timer to
disabled st_a_t_e___(not used) before generating an
written, the watchdog timer does not count and
______
does not generate the interrupt (NMI).
At initial reset, this register is set to "1".
interrupt (NMI) if it is not used.
______
(4) The NMI generation cycles in the watchdog
WDRST: 00FF40H•D2
timer mask option list represent maximum
values. A maximum minus (<selected optional
cycle> / 4) seconds of error occurs depending
on the watchdog timer reset timing. For
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading:
Constantly "0"
example, when 131072/ fOSC1 is selected by
______
mask option, the actual NMI generation cycle is
within the range of 98304/ fOSC1 to 131072/ fOSC1
seconds.
By writing "1" to WDRST, the watchdog timer is
reset, after which it is immediately restarted.
Writing "0" will mean no operation.
Since WDRST is for writing only, it is constantly set
to "0" during readout.
40
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits)
5.4.3 OSC1 oscillation circuit
The OSC1 oscillation circuit generates the 32.768
kHz (Typ.) system clock which is utilized during
low speed operation (low power mode) of the CPU
and peripheral circuits. Furthermore, even when
OSC3 is utilized as the system clock, OSC1
continues to generate the source clock for the clock
timer and stopwatch timer.
This oscillation circuit stops when the SLP instruc-
tion is executed.
In terms of the oscillation circuit types, either
crystal oscillation or CR oscillation can be selected
with the mask option.
5.4 Oscillation Circuits
5.4.1 Configuration of oscillation circuits
The S1C88650 is twin clock system with two
internal oscillation circuits (OSC1 and OSC3).
The OSC3 oscillation circuit generates the main-
clock (Max. 8.2 MHz) to run the CPU and some
peripheral circuits in high speed, and the OSC1
oscillation circuit generates the sub-clock (Typ.
32.768 kHz) for low-power operation.
Figure 5.4.1.1 shows the configuration of the
oscillation circuit.
Figure 5.4.3.1 shows the configuration of the OSC1
oscillation circuit.
OSC1
oscillation circuit
(fOSC1)
To peripheral
circuit
Prescaler
Clock
switch
To CPU (CLK)
SLEEP status
OSC1
To some peripheral
circuit
OSC3
oscillation circuit
fOSC1
(fOSC3)
CG1
Oscillation circuit
control signal
CPU clock
selection signal
CLKCHG
SLEEP
status
X'tal1
SOSC3
OSC2
VSS
VSS
Fig. 5.4.1.1 Configuration of oscillation circuits
At initial reset, OSC3 oscillation circuit is selected
for the CPU operating clock. ON/ OFF switching of
the OSC3 oscillation circuit and switching of the
system clock between OSC3 and OSC1 are control-
led in software. OSC3 circuit is utilized when high
speed operation of the CPU and some peripheral
circuits become necessary. Otherwise, OSC1 should
be used to generate the operating clock and OSC3
circuit placed in a stopped state in order to reduce
current consumption.
(1) Crystal oscillation circuit
OSC1
fOSC1
RCR1
OSC2
SLEEP status
(2) CR oscillation circuit
Fig. 5.4.3.1 OSC1 oscillation circuit
5.4.2 Mask option
OSC1 oscillation circuit
■ Crystal oscillation circuit
■ CR oscillation circuit
When crystal oscillation is selected, a crystal
oscillation circuit can be easily formed by connect-
ing a crystal oscillator X'tal1 (Typ. 32.768 kHz)
between the OSC1 and OSC2 terminals along with
a trimmer capacitor CG1 (5–25 pF) between the
OSC1 terminal and VSS.
When CR oscillation is selected, the CR oscillation
circuit (Max. 200 kHz) is formed merely by
connecting a resistor (RCR1) between OSC1 and
OSC2 terminals.
OSC3 oscillation circuit
■ Crystal oscillation circuit
■ Ceramic oscillation circuit
■ CR oscillation circuit
In terms of the oscillation circuit types for OSC1,
either crystal oscillation or CR oscillation can be
selected with the mask option.
In terms of the oscillation circuit types for OSC3,
either crystal oscillation, ceramic oscillation or CR
oscillation can be selected with the mask option, in
the same way as OSC1.
Note: Do not select CR oscillation for the OSC1
oscillation circuit when crystal oscillation is
selected for the OSC3 oscillation circuit.
When such a selection is made, the OSC3
clock may be supplied to the internal circuits
even though the OSC3 oscillation has not
stabilized.
S1C88650 TECHNICAL MANUAL
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41
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits)
When CR oscillation is selected, the CR oscillation
5.4.4 OSC3 oscillation circuit
The OSC3 oscillation circuit generates the system
clock when the CPU and some peripheral circuits
are in high speed operation.
circuit (Max. 2.2 MHz) is formed merely by
connecting a resistor (RCR3) between OSC3 and
OSC4 terminals.
This oscillation circuit stops when the SLP instruc-
tion is executed, or the SOSC3 register is set to "0".
In terms of oscillation circuit types, any one of
crystal oscillation, ceramic oscillation or CR
oscillation can be selected with the mask option.
Figure 5.4.4.1 shows the configuration of the OSC3
oscillation circuit.
5.4.5 Switching the CPU clocks
You can use either OSC1 or OSC3 as the system
clock for the CPU and you can switch over by
means of software.
You can save power by turning the OSC3 oscilla-
tion circuit off while the CPU is operating in OSC1.
When you must operate on OSC3, you can change
to high speed operation by turning the OSC3
oscillation circuit ON and switching over the
system clock.
In this case, since several msec to several tens of
msec are necessary for the oscillation to stabilize
after turning the OSC3 oscillation circuit ON, you
should switch over the clock after stabilization time
has elapsed.
CG2
OSC3
fOSC3
X'tal 2
or
Rf
Ceramic
Oscillation circuit
control signal
SLEEP status
OSC4
CD2
VSS
(1) Crystal/Ceramic oscillation circuit
When switching over from the OSC3 to the OSC1,
turn the OSC3 oscillation circuit OFF immediately
following the clock changeover.
OSC3
fOSC3
When switching the system clock from OSC3 to
OSC1 immediately after the power is turned on, it
is necessary to wait for the OSC1 oscillation to
stabilize before the clock can be switched. The
OSC3 oscillation may take several tens of msec to
several seconds until it has completely stabilized.
(The oscillation start time will vary somewhat
depending on the oscillator and on the externally
attached parts. Refer to the oscillation start time
example indicated in Chapter 8, "ELECTRICAL
CHARACTERISTICS".)
RCR3
Oscillation circuit
control signal
SLEEP status
OSC4
(2) CR oscillation circuit
Fig. 5.4.4.1 OSC3 oscillation circuit
When crystal or ceramic oscillation circuit is
selected, the crystal or ceramic oscillation circuit
(Max. 8.2 MHz) are formed by connecting either a
crystal oscillator (X'tal2) or a combination of
ceramic oscillator (Ceramic) and feedback resistor
(Rf) between OSC3 and OSC4 terminals and
connecting two capacitors (CG2, CD2) between the
OSC3 terminal and VSS, and between the OSC4
terminal and VSS, respectively.
Figure 5.4.5.1 indicates the status transition dia-
gram for the clock changeover.
Program Execution Status
RESET
High speed operation
Low speed operation
CLKCHG=0
SOSC3=0
SOSC3=1
Low speed and
low power operation
OSC1
OSC3
ON
ON
OSC1
OSC3
ON
ON
OSC1
OSC3
ON
OFF
CPU clock OSC3
CPU clock OSC1
CLKCHG=1
CPU clock OSC1
*
*
Interrupt
HALT instruction
Interrupt
SLP instruction
(Input interrupt)
HALT status
SLEEP status
OSC1
OSC3
ON
ON or OFF
OSC1
OSC3
OFF
OFF
CPU clock STOP
CPU clock STOP
Standby Status
*
The return destination from the standby status becomes the program execution status prior to shifting to the standby status.
Fig. 5.4.5.1 Status transition diagram for the clock changeover
42
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Oscillation Circuits)
5.4.6 Control of oscillation circuit
Table 5.4.6.1 shows the control bits for the oscillation circuits.
Table 5.4.6.1 Oscillation circuit control bits
Address Bit Name
00FF02 D7 EBR
Function
Bus release enable register
1
0
SR R/W
Comment
K03
BREQ
BACK
Input port
Output port
0
R/W
(K03 and R33 terminal specification) R33
D6 WT2
D5 WT1
D4 WT0
Wait control register
0
R/W
Number
of state
WT2
WT1
WT0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14
12
10
8
6
4
2
0
0
R/W
R/W
No wait
D3 CLKCHG CPU operating clock switch
OSC3
OSC1
1
1
0
0
R/W
R/W
D2 SOSC3 OSC3 oscillation On/Off control
On
1
Off
0
D1 –
D0 –
R/W register
R/W register
R/W Reserved register
R/W
1
0
SOSC3: 00FF02H•D2
5.4.7 Programming notes
Controls the ON and OFF settings of the OSC3
oscillation circuit.
(1) When the high speed CPU operation is not
necessary, you should operate the peripheral
circuits according to the setting outline indicate
below.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
• CPU operating clock
• OSC3 oscillation circuit
OSC1
OFF
Reading:
Valid
When the CPU and some peripheral circuits are to
be operated at high speed, SOSC3 is to be set to "1".
At all other times, it should be set to "0" in order to
reduce current consumption.
At initial reset, SOSC3 is set to "1" (OSC3 oscillation
ON).
(When the OSC3 clock is not necessary for
some peripheral circuits.)
(2) Since several msec to several tens of msec are
necessary for the oscillation to stabilize after
turning the OSC3 oscillation circuit ON.
Consequently, you should switch the CPU
operating clock (OSC1 → OSC3) after allowing
for a sufficient waiting time once the OSC3
oscillation goes ON. (The oscillation start time
will vary somewhat depending on the oscillator
and on the externally attached parts. Refer to the
oscillation start time example indicated in
Chapter 8, "ELECTRICAL CHARACTERIS-
TICS".)
CLKCHG: 00FF02H•D3
Selects the operating clock for the CPU.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading:
Valid
When the operating clock for the CPU is switched
to OSC3, CLKCHG should be set to "1" and when
the clock is switched to OSC1, CLKCHG should be
set to "0".
(3) When switching the clock from OSC3 to OSC1, be
sure to switch OSC3 oscillation OFF with
separate instructions. Using a single instruction
to process simultaneously can cause a malfunc-
tion of the CPU.
At initial reset, CLKCHG is set to "1" (OSC3 clock).
(4) When switching the system clock from OSC3 to
OSC1 immediately after the power is turned on,
it is necessary to wait the OSC1 oscillation to
stabilize before the clock can be switched. The
OSC3 oscillation takes several tens of msec to
several seconds until it has completely stabilized.
(The oscillation start time will vary somewhat
depending on the oscillator and on the externally
attached parts. Refer to the oscillation start time
example indicated in Chapter 8, "ELECTRICAL
CHARACTERISTICS".)
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
5.5.2 Mask option
5.5 Input Ports (K ports)
Input port pull-up resistors
K00 .... ■ With resistor ■ Gate direct
K01 .... ■ With resistor ■ Gate direct
K02 .... ■ With resistor ■ Gate direct
K03 .... ■ With resistor ■ Gate direct
K04 .... ■ With resistor ■ Gate direct
K05 .... ■ With resistor ■ Gate direct
K06 .... ■ With resistor ■ Gate direct
K07 .... ■ With resistor ■ Gate direct
5.5.1 Configuration of input ports
The S1C88650 is equipped with 8 input port bits
(K00–K07) all of which are usable as general purpose
input port terminals with interrupt function.
K04–K07 terminals doubles as the external clock
(EXCL0–EXCL3) input terminal of the
programmable timer (event counter) with input
port functions sharing the input signal as is. (See
"5.10 Programmable Timer")
Input port Input I/F level
K00 .... ■ CMOS level ■ CMOS schmitt
K01 .... ■ CMOS level ■ CMOS schmitt
K02 .... ■ CMOS level ■ CMOS schmitt
K03 .... ■ CMOS level ■ CMOS schmitt
K04 .... ■ CMOS level ■ CMOS schmitt
K05 .... ■ CMOS level ■ CMOS schmitt
K06 .... ■ CMOS level ■ CMOS schmitt
K07 .... ■ CMOS level ■ CMOS schmitt
Furthermore, it should be noted, however, that K03
terminal is shar_e__d___w__i_th the bus authority release
request signal (BREQ) input terminal. Function
assignment of this terminal can be selected i_n________
software. When this terminal is selected for BREQ
signal, K03 cannot be used as an input port. (See
"5.2 System Controller and Bus Control")
In the explanation below, it is assumed that K03 is
set as an input port.
Input ports K00–K07 are all equipped with pull-up
resistors. The mask option can be used to select
'With resistor' or 'Gate direct' for each port (bit).
Also the interface level, either CMOS level or
CMOS Schmitt level, can be selected for each port
(in a bit units).
Figure 5.5.1.1 shows the structure of the input port.
VDD
Pull-up
control
register
Address
Mask option
KxxD
Kxx
Mask option
Address
Input
interrupt
circuit
VSS
Fig. 5.5.1.1 Structure of input port
Each input port terminal is directly connected via a
three-state buffer to the data bus. Furthermore, the
input signal state at the instant of input port
readout is read in that form as data.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
5.5.3 Pull-up control
When "With resistor" is selected by mask option,
the software can enable and disable the pull-up
resistor for each port (1-bit units).
5.5.4 Interrupt function and input
comparison register
All the input ports (K00–K07) provide the interrupt
functions. The conditions for issuing an interrupt
can be set by the software.
When the interrupt generation condition set for a
terminal is met, the interrupt factor flag FK00–FK07
corresponding to the terminal is set at "1" and an
interrupt is generated.
The pull-up resistor becomes effective by writing
"1" to the pull-up control register PULK0x that
corresponds to each port, and the input line is
pulled up. When "0" has been written, no pull-up is
done.
Interrupt can be prohibited by setting the interrupt
enable registers EK00–EK07 for the corresponding
interrupt factor flags.
Furthermore, the priority level for input interrupt
can be set at the desired level (0–3) using the
interrupt priority registers PK00–PK01.
When "Gate direct" is selected by mask option, the
corresponding pull-up control register is
disconnected from the input line, so it can be used
as a general-purpose register.
At initial reset, the pull-up control register is set to
"1" (pulled up).
For details on the interrupt control registers for the
above and on operations subsequent to interrupt
generation, see "5.14 Interrupt and Standby Status".
The input port with a pull-up resistor suits input
from the push switch and key matrix.
When changing the input terminal from LOW level
to HIGH with the built-in pull-up resistor, a delay
in the waveform rise time will occur depending on
the time constant of the pull-up resistor and the
load capacitance of the terminal. It is necessary to
set an appropriate wait time for introduction of an
input port. In particular, special attention should be
paid to key scan for key matrix formation. Make
this wait time the amount of time or more calcu-
lated by the following expression.
The exception processing vectors for each interrupt
factor are set as follows:
K07 input interrupt: 000006H
K06 input interrupt: 000008H
K05 input interrupt: 00000AH
K04 input interrupt: 00000CH
K03 input interrupt: 00000EH
K02 input interrupt: 000010H
K01 input interrupt: 000012H
K00 input interrupt: 000014H
Wait time = RIN x (CIN + load capacitance on the
board) x 1.6 [sec]
Figure 5.5.4.1 shows the configuration of the input
interrupt circuit.
RIN: Pull up resistance Max. value
CIN: Terminal capacitance Max. value
The input comparison register KCP selects whether
the interrupt for each input port will be generated
on the rising edge or the falling edge of input.
When the K0x input signal changes to the status set
by the input comparison register KCP0x, the
interrupt factor flag FK0x is set to "1" and an
interrupt occurs.
The input port has a chattering-eliminate circuit
that checks input level to avoid unnecessary
interrupt generation due to chattering. There are
two separate chattering-eliminate circuits for K00–
K03 and K04–K07 and they can be set up
individually. The CTK00x–CTK02x registers allow
selection of signal level check time as shown in
Table 5.5.4.1.
The input port without a pull-up resistor is suits for
slide switch input and interfacing with other LSIs.
In this case, take care that a floating state does not
occur in input.
For unused ports, select "With resistor" and enable
pull-up using the pull-up control registers.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
Notes: • Be sure to disable interrupts before
Table 5.5.4.1 Setting the input level check time
changing the contents of the CTK0x
register. Unnecessary interrupts may
occur if the register is changed when the
corresponding input port interrupts have
been enabled by the interrupt enable
register EK0x.
CTK02x CTK01x CTK00x Check time (∗)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
4/fOSC3
2/fOSC3
1/fOSC3
(2 µs)
(1 µs)
(0.5 µs)
4096/fOSC1 (128 ms)
2048/fOSC1 (64 ms)
512/fOSC1
128/fOSC1
None
(16 ms)
(4 ms)
–
• The chattering-eliminate check time
means the maximum pulse width that can
be eliminated. The valid interrupt input
needs a pulse width of the set check time
(minimum) to twice that of the check time
(maximum).
∗: When OSC1 = 32 kHz, OSC3 = 2 MHz
• The internal signal may oscillate if the rise /
fall time of the input signal is too long
because the input signal level transition to
the threshold level duration of time is too
long. This causes the input interrupt to
malfunction, therefore setup the input signal
so that the rise/fall time is 25 nsec or less.
Check time setup register
CTK00L–CTK02L
Address
K00
fOSC1
fOSC3
OSC1
oscillation circuit
Divider
Divider
Input port
K00D
Chattering-eliminate
circuit
OSC3
oscillation circuit
Input comparison
register KCP00
Interrupt factor
flag FK00
Address
Address
Interrupt enable
register EK00
Address
K01
K02
K03
Interrupt
priority level
judgement
circuit
Check time setup register
CTK00H–CTK02H
Interrupt
request
Address
K04
Input port
K04D
Chattering-eliminate
circuit
Input comparison
register KCP04
Interrupt factor
flag FK04
Address
Address
Interrupt enable
register EK04
Interrupt
priority
register
Address
PK00, PK01
K05
K06
K07
Address
Fig. 5.5.4.1 Configuration of input interrupt circuit
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
5.5.5 Control of input ports
Table 5.5.5.1 shows the input port control bits.
Table 5.5.5.1(a) Input port control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF52 D7 KCP07 K07 input comparison register
D6 KCP06 K06 input comparison register
D5 KCP05 K05 input comparison register
D4 KCP04 K04 input comparison register
D3 KCP03 K03 input comparison register
D2 KCP02 K02 input comparison register
D1 KCP01 K01 input comparison register
D0 KCP00 K00 input comparison register
Interrupt
generated
at falling
edge
Interrupt
generated
at rising
edge
1
–
1
R/W
00FF54 D7 K07D
D6 K06D
K07 input port data
K06 input port data
K05 input port data
K04 input port data
K03 input port data
K02 input port data
K01 input port data
K00 input port data
D5 K05D
D4 K04D
High level
input
Low level
input
R
D3 K03D
D2 K02D
D1 K01D
D0 K00D
00FF56 D7 PULK07 K07 pull-up control register
D6 PULK06 K06 pull-up control register
D5 PULK05 K05 pull-up control register
D4 PULK04 K04 pull-up control register
D3 PULK03 K03 pull-up control register
D2 PULK02 K02 pull-up control register
D1 PULK01 K01 pull-up control register
D0 PULK00 K00 pull-up control register
On
Off
R/W
00FF58 D7 –
–
–
–
–
0
"0" when being read
D6 CTK02H K04–K07 port chattering-eliminate setup
R/W
R/W
R/W
(Input level check time)
CTK02H CTK01H CTK00H
Check time
[sec]
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D5 CTK01H
D4 CTK00H
D3 –
0
0
–
–
–
–
0
"0" when being read
D2 CTK02L K00–K03 port chattering-eliminate setup
R/W
R/W
R/W
(Input level check time)
CTK02L CTK01L CTK00L
Check time
[sec]
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
D1 CTK01L
D0 CTK00L
0
0
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
Table 5.5.5.1(b) Input port control bits
Address Bit Name
00FF20 D7 PK01
D6 PK00
Function
1
0
SR R/W
Comment
PK01 PK00 Priority
PSIF1 PSIF0 level
K00–K07 interrupt priority register
0
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D5 PSIF1
D4 PSIF0
D3 –
Serial interface interrupt priority register
0
R/W
–
–
–
–
–
–
0
Constantly "0" when
being read
D2 –
–
–
PTM1 PTM0 Priority level
D1 PTM1
Clock timer interrupt priority register
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D0 PTM0
00FF24 D7 EK07
D6 EK06
K07 interrupt enable
K06 interrupt enable
K05 interrupt enable
K04 interrupt enable
K03 interrupt enable
K02 interrupt enable
K01 interrupt enable
K00 interrupt enable
K07 interrupt factor flag
K06 interrupt factor flag
K05 interrupt factor flag
K04 interrupt factor flag
K03 interrupt factor flag
K02 interrupt factor flag
K01 interrupt factor flag
K00 interrupt factor flag
D5 EK05
D4 EK04
Interrupt
enable
Interrupt
disable
0
R/W
D3 EK03
D2 EK02
D1 EK01
D0 EK00
00FF28 D7 FK07
D6 FK06
(R)
(R)
Interrupt
factor is
No interrupt
factor is
D5 FK05
D4 FK04
generated
generated
0
R/W
D3 FK03
(W)
(W)
D2 FK02
Reset
No operation
D1 FK01
D0 FK00
K00D–K07D: 00FF54H
PULK00–PULK07: 00FF56H
Input data of input port terminal K0x can be read
out.
Controls the input pull-up resistor.
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
When "1" is read:
When "0" is read:
Writing:
HIGH level
LOW level
Invalid
Reading:
Valid
PULK0x is the pull-up control register
corresponding to the input port K0x that turns the
pull-up resistor built into the input port ON and
OFF.
When "Gate direct" is selected by mask option, the
corresponding pull-up control register is
disconnected from the input line, so it can be used
as a general-purpose register.
The terminal voltage of each of the input port K00–
K07 can be directly read out as either a "1" for
HIGH (VDD) level or a "0" for LOW (VSS) level.
This bit is exclusively for readout and are not
usable for write operations.
When "1" is written to PULK0x, the corresponding
input port K0x is pulled up to high. When "0" is
written, the input port is not pulled up.
At initial reset, this register is set to "1" (Pull-up
ON).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
KCP00–KCP07: 00FF52H
PK00, PK01: 00FF20H•D6, D7
Sets the interrupt generation condition (interrupt
generation timing) for input port terminals K00–
K07.
Sets the input interrupt priority level. PK00 and
PK01 are the interrupt priority registers
corresponding to the input interrupts.
Table 5.5.5.4 shows the interrupt priority level
which can be set by this register.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading:
Valid
Table 5.5.5.4 Interrupt priority level settings
PK01
PK00
Interrupt priority level
Level 3 (IRQ3)
KCP0x is the input comparison register which
corresponds to the input port K0x. Interrupt in
those ports which have been set to "1" is generated
on the falling edge of the input and in those set to
"0" on the rising edge.
1
1
0
0
1
0
1
0
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "1" (falling
edge).
At initial reset, this register is set to "0" (level 0).
EK00–EK07: 00FF24H
CTK00L–CTK02L: 00FF58H•D0–D2
How interrupt generation to the CPU is permitted
or prohibited.
Sets the input level check time of the chattering-
eliminate circuit for the K00–K03 input port
interrupts as shown in Table 5.5.5.2.
When "1" is written: Interrupt permitted
When "0" is written: Interrupt prohibited
Table 5.5.5.2 Setting the input level check time
Reading:
Valid
CTK02L CTK01L CTK00L Input level check time [sec]
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
EK0x is the interrupt enable register which
correspond to the input port K0x.
Interrupt is permitted in those terminals set to "1"
and prohibited in those set to "0".
At initial reset, this register is set to "0" (interrupt
prohibited).
FK00–FK07: 00FF28H
Be sure to disable interrupts before changing the
contents of this register. Unnecessary interrupts
may occur if the register is changed when the
corresponding input port interrupts have been
enabled by the interrupt enable register EK0x.
At initial reset, this register is set to "0" (None).
Indicates the generation state for an input interrupt.
When "1" is read:
When "0" is read:
Interrupt factor present
Interrupt factor not present
When "1" is written: Reset factor flag
When "0" is written: Invalid
The interrupt factor flag FK0x corresponds to K0x is
set to "1" by the occurrence of an interrupt
generation condition.
CTK00H–CTK02H: 00FF58H•D4–D6
Sets the input level check time of the chattering-
eliminate circuit for the K04–K07 input port
interrupts as shown in Table 5.5.5.3.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
Table 5.5.5.3 Setting the input level check time
CTK02H CTK01H CTK00H Input level check time [sec]
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
4/fOSC3
2/fOSC3
1/fOSC3
4096/fOSC1
2048/fOSC1
512/fOSC1
128/fOSC1
None
Be sure to disable interrupts before changing the
contents of this register. Unnecessary interrupt may
occur if the register is changed when the
corresponding input port interrupts have been
enabled by the interrupt enable register EK0x.
At initial reset, this register is set to "0" (None).
At initial reset, this flag is all reset to "0".
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
5.5.6 Programming notes
(1) When changing the input terminal from LOW
level to HIGH with the built-in pull-up resistor,
a delay in the waveform rise time will occur
depending on the time constant of the pull-up
resistor and the load capacitance of the
terminal. It is necessary to set an appropriate
wait time for introduction of an input port. In
particular, special attention should be paid to
key scan for key matrix formation. Make this
wait time the amount of time or more calculated
by the following expression.
Wait time = RIN x (CIN + load capacitance on the
board) x 1.6 [sec]
RIN: Pull up resistance Max. value
CIN: Terminal capacitance Max. value
(2) Be sure to disable interrupts before changing
the contents of the CTK0x register. Unnecessary
interrupts may occur if the register is changed
when the corresponding input port interrupts
have been enabled by the interrupt enable
register EK0x.
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In expansion mode, the data registers and high
impedance control registers of the output ports
used for bus function can be used as general
purpose registers with read/ write capabilities. This
will not in any way affect bus signal output.
The output specification of each output port is as
complementary output with high impedance
control in software possible.
5.6 Output Ports (R ports)
5.6.1 Configuration of output ports
The S1C88650 is equipped with 26 bits of output
ports (R00–R07, R10–R17, R20–R25, R30–R33).
Depending on the bus mode setting, the configura-
tion of the output ports may vary as shown in the
table below.
5.6.2 High impedance control
The output port can be high impedance controlled
in software.
This makes it possible to share output signal lines
with an other external device.
Table 5.6.1.1 Configuration of output ports
Bus mode
Terminal
Single chip
Expansion
Address A0
R00
R01
R02
R03
R04
R05
R06
R07
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
R23
R24
R25
R30
R31
R32
R33
Output port R00
Output port R01
Output port R02
Output port R03
Output port R04
Output port R05
Output port R06
Output port R07
Output port R10
Output port R11
Output port R12
Output port R13
Output port R14
Output port R15
Output port R16
Output port R17
Output port R20
Output port R21
Output port R22
Output port R23
Output port R24
Output port R25
Output port R30
Output port R31
Output port R32
Address A1
A high impedance control register is set for each
series of output port terminals as shown below.
Either complementary output and high impedance
state can be selected with this register.
Address A2
Address A3
Address A4
Address A5
Address A6
Table 5.6.2.1 High impedance control registers
Address A7
Register
HZR0L
HZR0H
HZR1L
HZR1H
HZR20
HZR21
HZR22
HZR23
HZR24
HZR25
HZR30
HZR31
HZR32
HZR33
Output port terminal
Address A8
R00–R03
R04–R07
R10–R13
R14–R17
R20
Address A9
Address A10
Address A11
Address A12
Address A13
Address A14
Address A15
Address A16
Address A17
Address A18
Address A19
RD signal
R21
R22
R23
R24
R25
R30
R31
R32
WR signal
R33
Output port R30/CE0 signal
Output port R31/CE1 signal
Output port R32/CE2 signal
When a high impedance control register HZRxx is
set to "1", the corresponding output port terminal
becomes high impedance state and when set to "0",
it becomes complementary output.
Output port R33 Output port R33/BACK signal
Only the configuration of the output ports in single
chip mode will be discussed here. With respect to
bus control, see "5.2 System Controller and Bus
Control".
Figure 5.6.1.1 shows the basic structure of the
output ports.
5.6.3 DC output
As Figure 5.6.1.1 shows, when "1" is written to the
output port data register, the output terminal
switches to HIGH (VDD) level and when "0" is
written it switches to LOW (VSS) level. When
output is in a high impedance state, the data
written to the data register is output from the
terminal at the instant when output is switched to
complementary.
Address
VDD
High impedance
control register
Data register
Rxx
Address
VSS
Fig. 5.6.1.1 Structure of output ports
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
5.6.4 Control of output ports
Table 5.6.4.1 shows the output port control bits.
Table 5.6.4.1(a) Output port control bits
Address Bit Name
00FF70 D7 –
D6 –
Function
1
1
1
1
1
0
0
0
0
0
SR R/W
Comment
R/W register
R/W register
R/W register
R/W register
0
0
0
0
R/W Reserved register
R/W
R/W
R/W
D5 –
D4 –
D3 HZR1H R14–R17 high impedance control
D2 HZR1L R10–R13 high impedance control
D1 HZR0H R04–R07 high impedance control
D0 HZR0L R00–R03 high impedance control
High
Comple-
mentary
0
R/W
impedance
00FF71 D7 –
D6 –
R/W register
R/W register
1
1
0
0
0
0
R/W Reserved register
R/W
D5 HZR25 R25 high impedance control
D4 HZR24 R24 high impedance control
D3 HZR23 R23 high impedance control
D2 HZR22 R22 high impedance control
D1 HZR21 R21 high impedance control
D0 HZR20 R20 high impedance control
High
Comple-
mentary
0
R/W
impedance
00FF72 D7 –
R/W register
R/W register
R/W register
R/W register
1
1
1
1
0
0
0
0
0
0
0
0
R/W Reserved register
D6 –
D5 –
D4 –
R/W
R/W
R/W
D3 HZR33 R33 high impedance control
D2 HZR32 R32 high impedance control
D1 HZR31 R31 high impedance control
D0 HZR30 R30 high impedance control
High
Comple-
mentary
0
R/W
R/W
impedance
00FF73 D7 R07D
R07 output port data
R06 output port data
R05 output port data
R04 output port data
R03 output port data
R02 output port data
R01 output port data
R00 output port data
R17 output port data
R16 output port data
R15 output port data
R14 output port data
R13 output port data
R12 output port data
R11 output port data
R10 output port data
R/W register
D6 R06D
D5 R05D
D4 R04D
D3 R03D
D2 R02D
D1 R01D
D0 R00D
00FF74 D7 R17D
D6 R16D
D5 R15D
D4 R14D
D3 R13D
D2 R12D
D1 R11D
D0 R10D
00FF75 D7 –
D6 –
High
Low
1
High
Low
1
R/W
1
1
0
0
0
0
R/W Reserved register
R/W
R/W register
D5 R25D
D4 R24D
D3 R23D
D2 R22D
D1 R21D
D0 R20D
R25 output port data
R24 output port data
R23 output port data
R22 output port data
R21 output port data
R20 output port data
High
Low
1
R/W
52
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
Table 5.6.4.1(b) Output port control bits
Address Bit Name
00FF76 D7 –
D6 –
Function
1
1
1
1
1
0
0
0
0
0
SR R/W
Comment
R/W register
R/W register
R/W register
R/W register
0
0
0
0
R/W Reserved register
R/W
R/W
R/W
D5 –
D4 –
D3 R33D
D2 R32D
D1 R31D
D0 R30D
R33 output port data
R32 output port data
R31 output port data
R30 output port data
High
Low
1
R/W
HZR0L, HZR0H: 00FF70H•D0, D1
HZR1L, HZR1H: 00FF70H•D2, D3
HZR20–HZR25: 00FF71H•D0–D5
HZR30–HZR33: 00FF72H•D0–D3
R00D–R07D: 00FF73H
R10D–R17D: 00FF74H
R20D–R25D: 00FF75H•D0–D5
R30D–R33D: 00FF76H•D0–D3
Sets the output terminals to a high impedance state.
Sets the data output from the output port terminal Rxx.
When "1" is written: High impedance
When "0" is written: Complementary
When "1" is written: HIGH level output
When "0" is written: LOW level output
Reading:
Valid
Reading:
Valid
HZRxx is the high impedance control register
which correspond as shown in Table 5.6.2.1 to the
various output port terminals.
When "1" is set to the HZRxx register, the corre-
sponding output port terminal becomes high
impedance state and when "0" is set, it becomes
complementary output.
RxxD is the data register for each output port.
When "1" is set, the corresponding output port
terminal switches to HIGH (VDD) level, and when
"0" is set, it switches to LOW (VSS) level.
At initial reset, this register is set to "1" (HIGH level
output).
The output data registers set for bus signal output
can be used as general purpose registers with read/
write capabilities which do not affect the output
terminals.
At initial reset, this register is set to "0"
(complementary).
S1C88650 TECHNICAL MANUAL
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53
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
The data registers and I/ O control registers of I/ O
5.7 I/O Ports (P ports)
ports set for data bus and serial interface output
terminals use are usable as general purpose
registers with read/ write capabilities which do not
affect I/ O activities of the terminal.
The same as above, the I/ O control register of I/ O
port set for serial interface input terminal use is
usable as general purpose register.
5.7.1 Configuration of I/O ports
The S1C88650 is equipped with 16 bits of I/ O ports
(P00–P07, P10–P17). The configuration of these I/ O
ports will vary according to the bus mode as shown
below.
In addition to the general-purpose DC output,
special output can be selected for the I/ O ports
P14–P17 with the software.
Table 5.7.1.1 Configuration of I/O ports
Bus mode
Terminal
Single chip
I/O port P00
I/O port P01
I/O port P02
I/O port P03
I/O port P04
I/O port P05
I/O port P06
I/O port P07
Expansion
Data bus D0
Data bus D1
Data bus D2
Data bus D3
Data bus D4
Data bus D5
Data bus D6
Data bus D7
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
5.7.2 Mask option
I/O port pull-up resistors
P00 ............ ■ With resistor
P01 ............ ■ With resistor
P02 ............ ■ With resistor
P03 ............ ■ With resistor
P04 ............ ■ With resistor
P05 ............ ■ With resistor
P06 ............ ■ With resistor
P07 ............ ■ With resistor
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
I/O port P10 (SIN)
I/O port P11 (SOUT)
P10 ............ ■ With resistor
P11 ............ ■ With resistor
P12 ............ ■ With resistor
P13 ............ ■ With resistor
P14 ............ ■ With resistor
P15 ............ ■ With resistor
P16 ............ ■ With resistor
P17 ............ ■ With resistor
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
■ Gate direct
I/O port P12 (SCLK)
I/O port P13 (SRDY)
I/O port P14 (TOUT0/TOUT1)
I/O port P15 (TOUT2/TOUT3)
I/O port P16 (FOUT)
I/O port P17 (TOUT2/TOUT3)
With respect to the data bus, see "5.2 System
Controller and Bus Control".
Figure 5.7.1.1 shows the structure of an I/ O port.
I/O port input interface level
P10 ............ ■ CMOS level
P11 ............ ■ CMOS level
P12 ............ ■ CMOS level
P13 ............ ■ CMOS level
P14 ............ ■ CMOS level
P15 ............ ■ CMOS level
P16 ............ ■ CMOS level
P17 ............ ■ CMOS level
■ CMOS Schmitt
■ CMOS Schmitt
■ CMOS Schmitt
■ CMOS Schmitt
■ CMOS Schmitt
■ CMOS Schmitt
■ CMOS Schmitt
■ CMOS Schmitt
VDD
Pull-up control
register
I/O control
register
Mask
option
Data
register
Pxx
I/ O ports P00–P07 and P10–P17 are equipped with
a pull-up resistor which goes ON in the input
mode. Whether this resistor is used or not can be
selected for each port (one bit unit). Furthermore,
the interface level for each port in P10–P17 can be
selected from CMOS level and CMOS Schmitt level.
*1
*2
Input
control
VSS
*1: During output mode
*2: During input mode
*3
*3: Schmitt input can be selected for P10–P17
by mask option.
5.7.3 I/O control registers and I/O mode
I/ O ports P00–P07 and P10–P17 are set either to
input or output modes by writing data to the I/ O
control registers IOC00–IOC07 and IOC10–IOC17
which correspond to each bit.
To set an I/ O port to input mode, write "0" to the I/
O control register.
An I/ O port which is set to input mode will shift to
a high impedance state and functions as an input
port.
Fig. 5.7.1.1 Structure of I/O port
I/ O port can be set for input or output mode in one
bit unit. These settings are performed by writing
data to the I/ O control registers.
I/ O port terminals P10–P13 are shared with serial
interface input/ output terminals and the function
of each terminal is switchable in software.
With respect to serial interface see "5.8 Serial
Interface".
54
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
Readout in input mode consists simply of a direct
readout of the input terminal state: the data being
"1" when the input terminal is at HIGH (VDD) level
and "0" when it is at LOW (VSS) level.
When the built-in pull-up resistor is enabled with
the software, the port terminal will be pulled-up to
high during input mode.
Even in input mode, data can be written to the data
registers without affecting the terminal state.
To set an I/ O port to output mode, write "1" to the
I/ O control register. An I/ O port which is set to
output mode functions as an output port.
When port output data is "1", a HIGH (VDD) level is
output and when it is "0", a LOW (VSS) level is
output. Readout in output mode consists of the
contents of the data register.
5.7.5 Special output
Besides general purpose DC input/ output, I/ O
ports P14–P17 can also be assigned special output
functions in software as shown in Table 5.7.5.1.
Table 5.7.5.1 Special output ports
Output port
P14
Special output
TOUT0/TOUT1 output
TOUT2/TOUT3 output
FOUT output
P15
P16
P17
TOUT2/TOUT3 output
When using P14–P17 as a special output port, write
"1" to the corresponding I/ O control register
(IOC14–IOC17) to set the port to the output mode.
At initial reset, I/ O control registers are set to "0"
(I/ O ports are set to input mode).
■ TOUT output (P14, P15)
In order for the S1C88650 to provide clock signal to
an external device, the terminals P14 and P15 can
be used to output a TOUTx signal (clock output by
the programmable timer).
5.7.4 Pull-up control
When "With resistor" is selected by mask option,
the software can enable and disable the pull-up
resistor for each port (1-bit units).
The output control for the TOUTx signals (x = 0–3)
is done by the registers PTOUTx. When PTOUTx is
set to "1", the TOUTx signal is output from the
corresponding port terminal, when "0" is set, the
port is set for DC output. When PTOUTx is "1",
settings of the I/ O control register IOC14/ IOC15
and data register P14D/ P15D become invalid.
The TOUT0–TOUT3 signals are generated from the
underflow and compare-match signals of the
programmable timers 0–3.
The pull-up resistor becomes effective by writing
"1" to the pull-up control register PULPxx that
corresponds to each port, and the Pxx terminal is
pulled up during the input mode. When "0" has
been written, no pull-up is done. When "Gate
direct" is selected by mask option, the
corresponding pull-up control register is
disconnected from the input line, so it can be used
as a general-purpose register. When the port is set
in the output mode, the setting of the pull-up
control register becomes invalid (no pull-up is done
during output).
With respect to frequency control, see "5.10 Pro-
grammable Timer".
Since the TOUTx signals are generated asynchro-
nously from the registers PTOUTx, when the
signals are turned ON or OFF by the register
settings, a hazard of a 1/ 2 cycle or less is generated.
Figure 5.7.5.1 shows the output waveform of the
TOUT signal.
At initial reset, the pull-up control registers are set
to "1" (pulled up).
When changing the port terminal from LOW level
to HIGH with the built-in pull-up resistor, a delay
in the waveform rise time will occur depending on
the time constant of the pull-up resistor and the
load capacitance of the terminal. It is necessary to
set an appropriate wait time for introduction of an
I/ O port. Make this wait time the amount of time
or more calculated by the following expression.
PTOUTx
0
1
TOUTx output
(P14/15)
Fig. 5.7.5.1 Output waveform of TOUT signal
Note: If PTOUT0 and PTOUT1 are set to "1" at the
same time, PTOUT1 is effective. Similarly, if
PTOUT2 and PTOUT3 are set to "1",
PTOUT3 is effective.
Wait time = RIN x (CIN + load capacitance on the
board) x 1.6 [sec]
RIN: Pull up resistance Max. value
CIN: Terminal capacitance Max. value
For unused ports, select "With resistor" and enable
pull-up using the pull-up control registers.
S1C88650 TECHNICAL MANUAL
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55
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
■ FOUT output (P16)
■ Inverted TOUT output (P17)
In order for the S1C88650 to provide clock signal to
an external device, a FOUT signal (oscillation clock
fOSC1 or fOSC3 dividing clock) can be output from
the P16 port terminal.
The S1C88650 provides an output of the TOUT2 or
TOUT3 inverted signal (programmable timer
output clock) to supply a clock to external devices
or to drive a buzzer.
The output control for the FOUT signal is done by
the register FOUTON. When FOUTON is set to "1",
the FOUT signal is output from the P16 port
terminal, when "0" is set, the port is set for DC
output. When FOUTON is "1", settings of the I/ O
control register IOC16 and data register P16D
become invalid.
The frequency of the FOUT signal can be selected in
software by setting the registers FOUT0–FOUT2.
The frequency is selected any one from among
eight settings as shown in Table 5.7.5.2.
By using this output with the TOUT2 or TOUT3
output from the P15 terminal, the bias level to be
applied to the buzzer can be increased.
___________
The output control for the TOUTx signals (x = 2 or
3) is done by the registers RPTOUTx. When
___________
RPTOUTx is set to "1", the TOUTx signal is output
from the P17 port terminal, when "0" is set, the port
is set for DC output. When RPTOUTx is "1",
settings of the I/ O control register IOC17 and data
register P17D become invalid.
___________
___________
The TOUT2 and TOUT3 signals are generated from
the underflow and compare-match signals of the
programmable timers 2 and 3.
With respect to frequency control, see "5.10 Pro-
grammab_l_e__T__i_m___e_r".
Since the TOUTx signals are generated asynchro-
nously from the registers RPTOUTx, when the
signals are turned ON or OFF by the register
settings, a hazard of a 1/ 2 cycle or less is generated.
_F_i_g__u__r_e_ 5.7.5.3 shows the output waveform of the
TOUT signal.
Table 5.7.5.2 FOUT frequency setting
FOUT2
FOUT1
FOUT0
FOUT frequency
fOSC3 / 8
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4
fOSC3 / 2
fOSC3 / 1
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
RPTOUTx
0
1
fOSC1: OSC1 oscillation frequency
fOSC3: OSC3 oscillation frequency
TOUTx output
(P17)
________
Fig. 5.7.5.3 Output waveform of TOUT signal
When the FOUT frequency is made "fOSC3/ n", you
must turn on the OSC3 oscillation circuit before
outputting FOUT. A time interval of several msec
to several 10 msec, from the turning ON of the
OSC3 oscillation circuit to until the oscillation
stabilizes, is necessary, due to the oscillation
element that is used. Consequently, if an abnormal-
ity occurs as the result of an unstable FOUT signal
being output externally, you should allow an
adequate waiting time after turning ON of the
OSC3 oscillation, before turning outputting FOUT.
(The oscillation start time will vary somewhat
depending on the oscillator and on the externally
attached parts. Refer to the oscillation start time
example indicated in Chapter 8, "ELECTRICAL
CHARACTERISTICS".)
Note: If RPTOUT2 and RPTOUT3 are set to "1" at
the same time, RPTOUT3 is effective.
Since the FOUT signal is generated asynchronously
from the register FOUTON, when the signal is
turned ON or OFF by the register settings, a hazard
of a 1/ 2 cycle or less is generated.
Figure 5.7.5.2 shows the output waveform of the
FOUT signal.
FOUTON
0
1
FOUT output
(P16)
Fig. 5.7.5.2 Output waveform of FOUT signal
56
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
5.7.6 Control of I/O ports
Table 5.7.6.1 shows the I/ O port control bits.
Table 5.7.6.1(a) I/O port control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF60 D7 IOC07 P07 I/O control register
D6 IOC06 P06 I/O control register
D5 IOC05 P05 I/O control register
D4 IOC04 P04 I/O control register
D3 IOC03 P03 I/O control register
D2 IOC02 P02 I/O control register
D1 IOC01 P01 I/O control register
D0 IOC00 P00 I/O control register
00FF61 D7 IOC17 P17 I/O control register
D6 IOC16 P16 I/O control register
D5 IOC15 P15 I/O control register
D4 IOC14 P14 I/O control register
D3 IOC13 P13 I/O control register
D2 IOC12 P12 I/O control register
D1 IOC11 P11 I/O control register
D0 IOC10 P10 I/O control register
Output
Input
0
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Output
High
High
On
Input
Low
Low
Off
00FF62 D7 P07D
D6 P06D
P07 I/O port data
P06 I/O port data
P05 I/O port data
P04 I/O port data
P03 I/O port data
P02 I/O port data
P01 I/O port data
P00 I/O port data
P17 I/O port data
P16 I/O port data
P15 I/O port data
P14 I/O port data
P13 I/O port data
P12 I/O port data
P11 I/O port data
P10 I/O port data
D5 P05D
D4 P04D
D3 P03D
D2 P02D
D1 P01D
D0 P00D
00FF63 D7 P17D
D6 P16D
D5 P15D
D4 P14D
D3 P13D
D2 P12D
D1 P11D
D0 P10D
00FF64 D7 PULP07 P07 pull-up control register
D6 PULP06 P06 pull-up control register
D5 PULP05 P05 pull-up control register
D4 PULP04 P04 pull-up control register
D3 PULP03 P03 pull-up control register
D2 PULP02 P02 pull-up control register
D1 PULP01 P01 pull-up control register
D0 PULP00 P00 pull-up control register
00FF65 D7 PULP17 P17 pull-up control register
D6 PULP16 P16 pull-up control register
D5 PULP15 P15 pull-up control register
D4 PULP14 P14 pull-up control register
D3 PULP13 P13 pull-up control register
D2 PULP12 P12 pull-up control register
D1 PULP11 P11 pull-up control register
D0 PULP10 P10 pull-up control register
On
Off
S1C88650 TECHNICAL MANUAL
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57
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
Table 5.7.6.1(b) I/O port control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF30 D7 MODE16_A PTM0–1 8/16-bit mode selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
1
0
R/W
R/W
D6 PTNREN_A External clock 0 noise rejecter selection
Enable
–
Disable
D5 –
D4 –
–
–
"0" when being read
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT0 PTM0 clock output control
D2 PTRUN0 PTM0 Run/Stop control
D1 PSET0 PTM0 preset
On
R/W
R/W
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL0 PTM0 input clock selection
External clock Internal clock
R/W
00FF31 D7 –
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
–
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT1 PTM1 clock output control
D2 PTRUN1 PTM1 Run/Stop control
On
Run
Preset
R/W
R/W
Stop
D1 PSET1 PTM1 preset
No operation
W
"0" when being read
"0" when being read
"0" when being read
D0 CKSEL1 PTM1 input clock selection
00FF38 D7 MODE16_B PTM2–3 8/16-bit mode selection
D6 PTNREN_B External clock 1 noise rejecter selection
External clock Internal clock
16 bit x 1 bit x 2
R/W
R/W
R/W
-
8-
Enable
–
Disable
D5 –
–
–
Off
D4 RPTOUT2 PTM2 inverted clock output control
D3 PTOUT2 PTM2 clock output control
D2 PTRUN2 PTM2 Run/Stop control
D1 PSET2 PTM2 preset
On
R/W
R/W
R/W
W
On
Off
Run
Preset
Stop
No operation
D0 CKSEL2 PTM2 input clock selection
External clock Internal clock
R/W
00FF39 D7 –
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
–
–
–
Off
D4 RPTOUT3 PTM3 inverted clock output control
D3 PTOUT3 PTM3 clock output control
D2 PTRUN3 PTM3 Run/Stop control
On
On
Run
Preset
R/W
R/W
R/W
W
Off
Stop
D1 PSET3 PTM3 preset
No operation
"0" when being read
D0 CKSEL3 PTM3 input clock selection
00FF40 D7 WDEN Watchdog timer enable
D6 FOUT2 FOUT frequency selection
External clock Internal clock
R/W
R/W
R/W
Enable
Disable
FOUT2 FOUT1 FOUT0
Frequency
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 8
fOSC3 / 4
fOSC3 / 2
fOSC3 / 1
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D5 FOUT1
D4 FOUT0
0
0
R/W
R/W
D3 FOUTON FOUT output control
D2 WDRST Watchdog timer reset
D1 TMRST Clock timer reset
On
Off
0
–
–
0
R/W
W
Reset
Reset
Run
No operation
No operation
Stop
Constantly "0" when
being read
W
D0 TMRUN Clock timer Run/Stop control
R/W
58
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
■ DC output control
PULP00–PULP07: 00FF64H
PULP10–PULP17: 00FF65H
P00D–P07D: 00FF62H
P10D–P17D: 00FF63H
The pull-up during the input mode are set with
these registers.
How I/ O port terminal Pxx data readout and
output data settings are performed.
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
When writing data:
Reading:
Valid
When "1" is written: HIGH level
When "0" is written: LOW level
PULPxx is the pull-up control register
corresponding to each I/ O port (in bit units).
When "Gate direct" is selected by mask option, the
corresponding pull-up control register is
disconnected from the input line, so it can be used
as a general-purpose register.
By writing "1" to the PULPxx register, the
corresponding I/ O ports are pulled up (during
input mode), while writing "0" turns the pull-up
function OFF.
When the I/ O port is set to output mode, the data
written is output as is to the I/ O port terminal. In
terms of port data, when "1" is written, the port
terminal goes to HIGH (VDD) level and when "0" is
written to a LOW (VSS) level.
Even when the port is in input mode, data can still
be written in.
When reading out data:
At initial reset, these registers are all set to "1", so
the pull-up function is set to ON.
When "1" is read:
When "0" is read:
HIGH level ("1")
LOW level ("0")
Note: The pull-up control registers of the ports that
are configured to the serial interface outputs
or special outputs can be used as general
purpose registers that do not affect the pull-
up control. The pull-up control registers of
the port that are configured to the serial
interface inputs function the same as the I/O
port.
When an I/ O port is in input mode, the voltage
level being input to the port terminal is read out.
When terminal voltage is HIGH (VDD), it is read as
a "1", and when it is LOW (VSS), it is read as a "0".
Furthermore, in output mode, the contents of the
data register are read out.
At initial reset, this register is set to "1" (HIGH
level).
■ Special output control
Note: The data registers of the ports that are
configured to the data bus, serial interface
outputs and special outputs can be used as
general purpose registers that do not affect
the terminal inputs/outputs.
PTOUT0: 00FF30H•D3
PTOUT1: 00FF31H•D3
PTOUT2: 00FF38H•D3
PTOUT3: 00FF39H•D3
IOC00–IOC07: 00FF60H
IOC10–IOC17: 00FF61H
Controls the TOUT (programmable timer output
clock) signal output.
Sets the I/ O ports to input or output mode.
When "1" is written: TOUT signal output
When "0" is written: DC output
When "1" is written: Output mode
When "0" is written: Input mode
Reading:
Valid
Reading:
Valid
PTOUT0–PTOUT3 are the output control registers
for the TOUT0–TOUT3 signals. When PTOUT0 (or
PTOUT1) is set to "1", the TOUT0 (or TOUT1) signal
is output from the P14 port terminal. When
PTOUT2 (or PTOUT3) is set to "1", the TOUT2 (or
TOUT3) signal is output from the P15 port terminal.
When "0" is set, P14/ P15 is set for DC output.
At this time, settings of the I/ O control register
IOC14/ IOC15 and data register P14D/ P15D
become invalid.
IOCxx is the I/ O control register which correspond
to each I/ O port in a bit unit.
Writing "1" to the IOCxx register will switch the
corresponding I/ O port Pxx to output mode, and
writing "0" will switch it to input mode.
When the special output is used, "1" must always be
set for the I/ O control registers (IOC14–IOC17) of
I/ O ports which will become output terminals.
At initial reset, this register is set to "0" (input
mode).
At initial reset, PTOUT is set to "0" (DC output).
Note: If PTOUT0 and PTOUT1 are set to "1" at the
same time, PTOUT1 is effective. Similarly, if
PTOUT2 and PTOUT3 are set to "1",
Note: The I/O control registers of the ports that are
configured to the data bus, serial interface
inputs/outputs and special outputs can be
used as general purpose registers that do
not affect the terminal inputs/outputs.
PTOUT3 is effective. Furthermore, if the
programmable timer is set in 16-bit mode, the
TOUT0 and TOUT2 signals cannot be output.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Ports)
RPTOUT2: 00FF38H•D4
5.7.7 Programming notes
RPTOUT3: 00FF39H•D4
(1) When changing the port terminal in which the
pull-up resistor is enabled from LOW level to
HIGH, a delay in the waveform rise time will
occur depending on the time constant of the
pull-up resistor and the load capacitance of the
terminal. It is necessary to set an appropriate
wait time for introduction of an I/ O port. Make
this wait time the amount of time or more
calculated by the following expression.
___________ ___________
Controls the TOUT2/ TOUT3 (inverted TOUT2/
TOUT3) signal output.
_________
When "1" is written: TOUT signal output
When "0" is written: DC output
Reading:
Valid
RPTOUT2 and RPTOUT3 are the output control
___________
___________
registers for the TOUT2 and TOUT3 signals,
respectively. When RPTOUT2 (or RPTOUT3) is set
___________
___________
Wait time = RIN x (CIN + load capacitance on the
board) x 1.6 [sec]
to "1", the TOUT2 (or TOUT3) signal is output from
the P17 port terminal. When "0" is set, P17 is set for
DC output.
At this time, settings of the I/ O control register
IOC17 and data register P17D become invalid.
At initial reset, RPTOUT is set to "0" (DC output).
RIN: Pull up resistance Max. value
CIN: Terminal capacitance Max. value
(2) Since the special output signals (TOUT0–3,
_______________ _ _
TOUT2–3, and FOUT) are generated
asynchronously from the output control
registers (PTOUT0–3, RPTOUT2–3, and
FOUTON), when the signals is turned ON or
OFF by the output control register settings, a
hazard of a 1/ 2 cycle or less is generated.
Note: If RPTOUT2 and RPTOUT3 are set to "1" at
the same time, RPTOUT3 is effective.
Furthermore, if the programmable timer is set
________
in 16-bit mode, the TOUT2 signal cannot be
output.
(3) When the FOUT frequency is made "fOSC3/ n",
you must turn on the OSC3 oscillation circuit
before outputting FOUT. A time interval of
several msec to several 10 msec, from the
turning ON of the OSC3 oscillation circuit to
until the oscillation stabilizes, is necessary, due
to the oscillation element that is used.
FOUTON: 00FF40H•D3
Controls the FOUT (fOSC1/ fOSC3 dividing clock)
signal output.
When "1" is written: FOUT signal output
When "0" is written: DC output
Reading:
Valid
Consequently, if an abnormality occurs as the
result of an unstable FOUT signal being output
externally, you should allow an adequate
waiting time after turning ON of the OSC3
oscillation, before turning outputting FOUT.
(The oscillation start time will vary somewhat
depending on the oscillator and on the
externally attached parts. Refer to the oscillation
start time example indicated in Chapter 8,
"ELECTRICAL CHARACTERISTICS".)
FOUTON is the output control register for FOUT
signal. When "1" is set, the FOUT signal is output
from the P16 port terminal and when "0" is set, P16
is set for DC output. At this time, settings of the I/
O control register IOC16 and data register P16D
become invalid.
At initial reset, FOUTON is set to "0" (DC output).
FOUT0–FOUT2: 00FF40H•D4–D6
FOUT signal frequency is set as shown in Table
5.7.6.2.
(4) The SLP instruction has executed when the
_______________ _ _
special output signals (TOUT0–3, TOUT2–3,
and FOUT) are in the enable status, an unstable
clock is output for the special output at the time
of return from the SLEEP state. Consequently,
when shifting to the SLEEP state, you should set
the special output signal to the disable status
prior to executing the SLP instruction.
Table 5.7.6.2 FOUT frequency settings
FOUT2
FOUT1
FOUT0
FOUT frequency
fOSC3 / 8
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4
fOSC3 / 2
fOSC3 / 1
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
fOSC1: OSC1 oscillation frequency
fOSC3: OSC3 oscillation frequency
At initial reset, this register is set to "0" (fOSC1/ 1).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.8.2 Switching of terminal functions
_S_e__r__i_a_l_ inter_f_a_c__e___i_nput/ output terminals, SIN, SOUT,
SCLK and SRDY are shared with I/ O ports P10–
P13. In order to utilize these terminals for the serial
interface input/ output terminals, "1" must be
written to the ESIF register.
At initial reset, these terminals are set as I/ O port
terminals.
The direction of I/ O port terminals set for serial
interface input/ output terminals are determined by
the signal and transfer mode for each terminal.
Furthermore, the settings for the corresponding I/
O control registers for the I/ O ports become
invalid.
5.8 Serial Interface
5.8.1 Configuration of serial interface
The S1C88650 incorporates a full duplex serial
interface (when asynchronous system is selected)
that allows the user to select either clock synchro-
nous system or asynchronous system.
The data transfer method can be selected in soft-
ware.
When the clock synchronous system is selected, 8-
bit data transfer is possible.
When the asynchronous system is selected, either 7-
bit or 8-bit data transfer is possible, and a parity
check of received data and the addition of a parity
bit for transmitting data can automatically be done
by selecting in software.
Table 5.8.2.1 Configuration of input/output terminals
Terminal
P10
When serial interface is selected
Figure 5.8.1.1 shows the configuration of the serial
interface.
SIN
P11
SOUT
SCLK
SRDY
P12
P13
* The terminals used may vary depending on the transfer mode.
Data bus
Serial I/O control
& status register
Received
data buffer circuit
Error detection
Interrupt
control circuit
Interrupt
request
Serial input
control circuit
Received data
shift register
Transmitting data
shift register
Serial output
control circuit
SIN(P10)
SOUT(P11)
SRDY(P13)
Start bit
detection circuit
READY output
control circuit
Clock
control circuit
Programmable timer 1 underflow signal
SCLK(P12)
Fig. 5.8.1.1 Configuration of serial interface
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
The serial interface terminals are configured
according to the transfer mode set using the
registers SMD0 and SMD1. SIN and SOUT are
serial data input and output terminals which
■ Clock synchronous slave mode
In this mode, a synchronous clock from the external
(master side) serial input/ output device is utilized
and clock synchronous 8-bit serial transfers can be
performed with this serial interface as_t__h__e__s__lave.
The synchronous clock is input to the SCLK
function identically in clock synchronous system
_________
and asynchronous system. SCLK is exclusively for
use with clock synchronous system and functions
terminal and is utilized by this interface as the
as a synchronous clock input/ output terminal.
synchronous clock.
_________
_________
SRDY is exclusively for use in clock synchronous
slave mode and functions as a send-receive ready
Furthermore, the SRDY signal indicating the
transmit-receive ready status is output from the
_________
signal output terminal.
SRDY terminal in accordance with the serial
interface operating status.
_________
Whe_n___a__s_y__nchronous system is selected, since SCLK
and SRDY are superfluous, the I/ O port terminals
P12 and P13 can be used as I/ O ports.
In the same way, when_c__l_o__c_k__ synchronous master
mode is selected, since SRDY is superfluous, the
I/ O port terminal P13 can be used as I/ O port.
In the slave mode, the settings for registers SCS0
and SCS1 used to select the clock source are invalid.
Figure 5.8.3.1(b) shows the connection example of
input/ output terminals in the clock synchronous
slave mode.
■ Asynchronous 7-bit mode
5.8.3 Transfer modes
In this mode, asynchronous 7-bit transfer can be
performed. Parity check during data reception and
addition of parity bit (odd/ even/ none) during
transmitting can be specified and data processed in
7 bits with or without parity. Si_n__c_e___t_h_ is mode
There are four transfer modes for the serial inter-
face and mode selection is made by setting the two
bits of the mode selection registers SMD0 and
SMD1 as shown in the table below.
employs the internal clock, the SCLK terminal is
Table 5.8.3.1 Transfer modes
_________
not used. Furthermore, since the SRDY terminal is
not utilized either, both of these terminals can be
used as I/ O ports.
Figure 5.8.3.1(c) shows the connection example of
input/ output terminals in the asynchronous mode.
SMD1
SMD0
Mode
1
1
0
0
1
0
1
0
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
■ Asynchronous 8-bit mode
Table 5.8.3.2 Terminal settings corresponding
to each transfer mode
In this mode, asynchronous 8-bit transfer can be
performed. Parity check during data reception and
addition of parity bit (odd/ even/ none) during
transmitting can be specified and data processed in
8 bits with or without parity. Si_n__c_e___t_h_ is mode
Mode
SIN SOUT SCLK SRDY
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Input Output P12
Input Output P12
P13
P13
employs the internal clock, the SCLK terminal is
_________
Input Output Input Output
not used. Furthermore, since the SRDY terminal is
not utilized either, both of these terminals can be
used as I/ O ports.
Figure 5.8.3.1(c) shows the connection example of
input/ output terminals in the asynchronous mode.
Clock synchronous master Input Output Output P13
At initial reset, transfer mode is set to clock syn-
chronous master mode.
■ Clock synchronous master mode
In this mode, the internal clock is utilized as a
synchronous clock for the built-in shift registers,
and clock synchronous 8-bit serial transfers can be
performed with this serial interface as the master.
The synchronous clock is also output from the
_________
SCLK terminal which enables control of the
external (slave side) serial I/ O device. Since the
_________
SRDY terminal is not utilized in this mode, it can be
used as an I/ O port.
Figure 5.8.3.1(a) shows the connection example of
input/ output terminals in the clock synchronous
master mode.
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This register setting is invalid in clock synchronous
S1C88650
External
serial device
slave mode and the external clock input from the
_________
SIN(P10)
SOUT(P11)
Data input
SCLK terminal is used.
When the "programmable timer" is selected, the
programmable timer 1 underflow signal is divided
Data output
SCLK(P12)
CLOCK input
by 2 and this signal is used as the clock source.
With respect to the transfer rate setting, see "5.10
Programmable Timer".
Input port(Kxx)
READY output
(a) Clock synchronous master mode
At initial reset, the synchronous clock is set to
"fOSC3/ 16".
S1C88650
External
serial device
Whichever clock is selected, the signal is further
divided by 16 and then used as the synchronous
clock.
SIN(P10)
SOUT(P11)
SCLK(P12)
SRDY(P13)
Data input
Data output
CLOCK output
READY input
Furthermore, external clock input is used as is for
_________
SCLK in clock synchronous slave mode.
Table 5.8.4.2 shows an examples of transfer rates and
OSC3 oscillation frequencies when the clock source
is set to programmable timer.
(b) Clock synchronous slave mode
S1C88650
External
serial device
When the demultiplied signal of the OSC3 oscilla-
tion circuit is made the clock source, it is necessary
to turn the OSC3 oscillation ON, prior to using the
serial interface.
SIN(P10)
Data input
SOUT(P11)
Data output
A time interval of several msec to several 10 msec,
from the turning ON of the OSC3 oscillation circuit
to until the oscillation stabilizes, is necessary, due to
the oscillation element that is used. Consequently,
you should allow an adequate waiting time after
turning ON of the OSC3 oscillation, before starting
transmitting/ receiving of serial interface. (The
oscillation start time will vary somewhat depending
on the oscillator and on the externally attached parts.
Refer to the oscillation start time example indicated
in Chapter 8, "ELECTRICAL CHARACTERISTICS".)
At initial reset, the OSC3 oscillation circuit is set to
ON status.
(c) Asynchronous 7-bit/8-bit mode
Fig. 5.8.3.1 Connection examples of serial interface I/O terminals
5.8.4 Clock source
There are four clock sources and selection is made
by setting the two bits of the clock source selection
register SCS0 and SCS1 as shown in table below.
Table 5.8.4.1 Clock source
SCS1
SCS0
Clock source
Programmable timer
fOSC3 / 4
1
1
0
0
1
0
1
0
fOSC3 / 8
fOSC3 / 16
1/4
1/8
1/16
OSC3
oscillation
circuit
fOSC3
Synchro-
nous clock
Divider
Selector
1/16
Selector
Programmable timer 1
underflow signal
1/2
(Clock synchronous slave mode)
Fig. 5.8.4.1
Division of the synchronous clock
SCLK
Table 5.8.4.2 OSC3 oscillation frequencies and transfer rates
OSC3 oscillation frequency / Programmable timer settings
Transfer rate
fOSC3 = 2.4756 MHz fOSC3 = 3.0720 MHz fOSC3 = 3.6864 MHz
(bps)
PST1X
00H
00H
00H
00H
00H
00H
02H
02H
RDR1X
03H
PST1X
00H
00H
00H
00H
00H
00H
03H
03H
RDR1X
04H
PST1X
00H
00H
00H
00H
00H
00H
01H
02H
RDR1X
05H
19,200
9,600
4,800
2,400
1,200
600
07H
09H
0BH
17H
0FH
1FH
3FH
7FH
1FH
3FH
13H
27H
2FH
4FH
9FH
09H
5FH
BFH
BFH
5FH
300
150
13H
∗ Since the underflow signal only is used as the clock source, the
CDR1X register value does not affect the transfer rates.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
In addition, TXTRG can be read as the status. When
set to "1", it indicates transmitting operation, and
"0" indicates transmitting stop.
For details on timing, see the timing chart which
gives the timing for each mode.
5.8.5 Transmit-receive control
Below is a description of the registers which handle
transmit-receive control. With respect to transmit-
receive control procedures and operations, please
refer to the following sections in which these are
discussed on a mode by mode basis.
When not transmitting, set TXEN to "0" to disable
transmitting status.
■ Shift register and received data buffer
Exclusive shift registers for transmitting and
receiving are installed in this serial interface.
Consequently, duplex communication simultane-
ous transmit and receive is possible when the
asynchronous system is selected.
■ Receive enable register, receive control bit
For receiving control, use the receive enable register
RXEN and receive control bit RXTRG.
Receive enable register RXEN is used to set receiv-
ing enable/ disable status. When "1" is written into
this register to set the receiving enable status, clock
input to the shift register is enabled and the system
is ready to receive data. In the clock synchronous
Data being transmitted are written to TRXD0–
TRXD7 and converted to serial through the shift
register and is output from the SOUT terminal.
mode, synchronous clock input/ output from the
_________
SCLK terminal is also enabled.
In the reception section, a received data buffer is
installed separate from the shift register.
Data being received are input to the SIN terminal
and is converted to parallel through the shift
register and written to the received data buffer.
Since the received data buffer can be read even
during serial input operation, the continuous data
is received efficiently.
With the above setting, receiving begins and serial
data input from the SIN terminal goes to the shift
register.
The operation of the receive control bit RXTRG is
slightly different depending on whether a clock
synchronous system or an asynchronous system is
being used.
In the clock synchronous system, the receive
control bit RXTRG is used as the trigger to start
receiving data.
However, since buffer functions are not used in
clock synchronous mode, be sure to read out data
before the next data reception begins.
When received data has been read and the prepara-
tion for next data receiving is completed, write "1"
■ Transmit enable register and transmit
control bit
For transmitting control, use the transmit enable
register TXEN and transmit control bit TXTRG.
into RXTRG to start receiving. (When "1" is written
_________
to RXTRG in slave mode, SRDY switches to "0".)
In an asynchronous system, RXTRG is used to
prepare for next data receiving. After reading the
received data from the received data buffer, write
"1" into RXTRG to signify that the received data
buffer is empty. If "1" is not written into RXTRG,
the overrun error flag OER will be set to "1" when
the next receiving operation is completed. (An
overrun error will be generated when receiving is
completed between reading the received data and
the writing of "1" to RXTRG.)
In addition, RXTRG can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRG is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
The transmit enable register TXEN is used to set the
transmitting enable/ disable status. When "1" is
written to this register to set the transmitting enable
status, clock input to the shift register is enabled
and the system is ready to transmit data. In the
clock synchronous mode, synchronous clock input/
_________
output from the SCLK terminal is also enabled.
The transmit control bit TXTRG is used as the
trigger to start transmitting data.
Data to be transmitted is written to the transmit
data shift register, and when transmitting prepara-
tions a recomplete, "1" is written to TXTRG where-
upon data transmitting begins.
When interrupt has been enabled, an interrupt is
generated when the transmission is completed. If
there is subsequent data to be transmitted it can be
sent using this interrupt.
For details on timing, see the timing chart which
gives the timing for each mode.
When you do not receive, set RXEN to "0" to disable
receiving status.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
(2) Port selection
5.8.6 Operation of
clock synchronous transfer
Because serial inte_r_f_a__c__e__input/ output ports SIN,
_________
SOUT, SCLK and SRDY are set as I/ O port
Clock synchronous transfer involves the transfer of
8-bit data by synchronizing it to eight clocks. The
same synchronous clock is used by both the
transmitting and receiving sides.
terminals P10–P13 at initial reset, "1" must be
written to the serial interface enable register
ESIF in order to set these terminals for serial
interface use.
When the serial interface is used in the master
mode, the clock signal selected using SCS0 and
SCS1 is further divided by 1/ 16 and employed as
(3) Setting of transfer mode
Select the clock synchronous mode by writing
the data as indicated below to the two bits of the
mode selection registers SMD0 and SMD1.
the synchronous clock. This signal is then sent via
_________
the SCLK terminal to the slave side (external serial
I/ O device).
Master mode:
Slave mode:
SMD0 = "0", SMD1 = "0"
SMD0 = "1", SMD1 = "0"
When used in the slave mode, the clock input to the
_________
SCLK terminal from the master side (external serial
input/ output device) is used as the synchronous
clock.
(4) Clock source selection
In the master mode, select the synchronous
clock source by writing data to the two bits of
the clock source selection registers SCS0 and
SCS1. (See Table 5.8.4.1.)
This selection is not necessary in the slave
mode.
I_n__t__h__e__clock synchronous mode, since one clock line
(SCLK) is shared for both transmitting and receiv-
ing, transmitting and receiving cannot be per-
formed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Since all the registers mentioned in (2)–(4) are
assigned to the same address, it's possible to set
them all with one instruction. The parity enable
register EPR is also assigned to this address,
however, since parity is not necessary in the
clock synchronous mode, parity check will not
take place regardless of how they are set.
The transfer data length is fixed at 8 bits. Data can
be switched using a register whether it is
transmitted/ received from LSB (bit 0) or MSB (bit
7).
LSB first
SCLK
(5) Clock source control
LSB
MSB
When the master mode is selected and pro-
grammable timer for the clock source is se-
lected, set transfer rate on the programmable
timer side. (See "5.10 Programmable Timer".)
When the divided signal of OSC3 oscillation
circuit is selected for the clock source, be sure
that the OSC3 oscillation circuit is turned ON
prior to commencing data transfer. (See "5.4
Oscillation Circuits".)
Data
D0 D1 D2 D3 D4 D5 D6 D7
MSB first
SCLK
MSB
LSB
Data
D7 D6 D5 D4 D3 D2 D1 D0
Fig. 5.8.6.1 Transfer data configuration using
clock synchronous mode
(6) Serial data input/output permutation
The S1C88650 provides the data input/ output
permutation select register SDP to select
whether the serial data bits are transfered from
the LSB or MSB. The SDP register should be set
before writing data to TRXD0–TRXD7.
Below is a description of initialization when
performing clock synchronous transfer, transmit-
receive control procedures and operations.
With respect to serial interface interrupt, see "5.8.8
Interrupt function".
■ Initialization of serial interface
When performing clock synchronous transfer, the
following initial settings must be made.
(1) Setting of transmitting/receiving disable
To set the serial interface into a status in which
both transmitting and receiving are disabled, "0"
must be written to both the transmit enable
register TXEN and the receive enable register
RXEN. Fix these two registers to a disable status
until data transfer actually begins.
S1C88650 TECHNICAL MANUAL
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65
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
■ Data transmit procedure
The control procedure and operation during
transmitting is as follows.
(1) Write "0" in the transmit enable register TXEN
and the receive enable register RXEN to reset
the serial interface.
(2) Write "1" in the transmit enable register TXEN
to set into the transmitting enable status.
(3) Write the transmitting data into TRXD0–
TRXD7.
Data transmitting
TXEN ← 0, RXEN ← 0
TXEN ← 1
(4) In case of the master mode, confirm the receive
ready status on the slave side (external serial
input/ output device), if necessary. Wait until it
reaches the receive ready status.
(5) Write "1" in the transmit control bit TXTRG and
start transmitting.
Set transmitting data
to TRXD0–TRXD7
In the master mode, this control causes the
synchronous clock to change to enable and to be
provided to the shift _r_e__g__i_s_t_er for transmitting
and output from the SCLK terminal.
No
Receiver ready ?
In case of master mode
Yes
In the slave mode, it waits_f_o__r___t_h_ e synchronous
clock to be input from the SCLK terminal.
The transmitting data of the shift register shifts
one bit at a time at each falling edge of the
synchronous clock and is output from the SOUT
terminal. When the final bit (MSB when "LSB
first" is selected, or LSB when "MSB first" is
selected) is output, the SOUTx terminal is
maintained at that level, until the next
TXTRG ← 1
No
FSTRA = 1 ?
Yes
No
Transmit complete ?
Yes
TXEN ← 0
transmitting begins.
The transmitting complete interrupt factor flag
FSTRA is set to "1" at the point where the data
transmitting of the shift register is completed.
When interrupt has been enabled, a transmit-
ting complete interrupt is generated at this
point.
End
Fig. 5.8.6.2 Transmit procedure in clock synchronous mode
Set the following transmitting data using this
interrupt.
(6) Repeat steps (3) to (5) for the number of bytes of
transmitting data, and then set the transmit
disable status by writing "0" to the transmit
enable register TXEN, when the transmitting is
completed.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
■ Data receive procedure
The control procedure and operation during
receiving is as follows.
(1) Write "0" in the receive enable register RXEN
and transmit enable register TXEN to reset the
serial interface.
(2) Write "1" in the receive enable register RXEN to
set into the receiving enable status.
(3) In case of the master mode, confirm the transmit
ready status on the slave side (external serial
input/ output device), if necessary. Wait until it
reaches the transmit ready status.
Data receiving
RXEN ← 0, TXEN ← 0
RXEN ← 1
(4) Write "1" in the receive control bit RXTRG and
start receiving.
In the master mode, this control causes the
synchronous clock to change to enable and is
No
Transmitter ready ?
In case of master mode
provided to the shift register for receiving and
_________
Yes
output from the SCLK terminal.
RXTRG ← 1
In the slave mode, it waits_f_o__r___t_h_ e synchronous
clock to be input from the SCLK terminal. The
received data input from the SIN terminal is
successively incorporated into the shift register
in synchronization with the rising edge of the
synchronous clock.
At the point where the data of the 8th bit has
been incorporated at the final (8th) rising edge
of the synchronous clock, the content of the shift
register is sent to the received data buffer and
the receiving complete interrupt factor flag
FSREC is set to "1". When interrupt has been
enabled, a receiving complete interrupt is
generated at this point.
No
FSREC = 1 ?
Yes
Received data reading
from TRXD0–TRXD7
No
Receiving complete ?
Yes
RXEN ← 0
End
(5) Read the received data from TRXD0–TRXD7
using receiving complete interrupt.
Fig. 5.8.6.3 Receiving procedure in clock synchronous mode
(6) Repeat steps (3) to (5) for the number of bytes of
receiving data, and then set the receive disable
status by writing "0" to the receive enable
register RXEN, when the receiving is com-
pleted.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
_________
_________
■ Transmit/receive ready (SRDY) signal
The SRDY signal changes the "1" to "0," immedi-
When this serial interface is used in the clock
ately after writing "1" into the transmit control bit
TXTRG or the receive control bit RXTRG and
returns from "0" to "1", at the point where the first
synchronous clock has been input (falling edge).
When you have set in the master mode, control the
transfer by inputting the same signal from the slave
synchronous slave mode (external clock input), an
_________
SRDY signal is output to indicate whether or not
this serial interface can transmit/ receive to the
master side (external serial input/ output device).
_________
This signal is output from the SRDY terminal and
when this interface enters the transmit or receive
enable (READY) status, it becomes "0" (LOW level)
and becomes "1" (HIGH level) when there is a
BUSY status, such as during transmit/ receive
operation.
side using the input port or I/ O port. At this time,
_________
since the SRDY terminal is not set and instead P13
functions as the I/ O port, you can apply this port
for said control.
■ Timing chart
The timing chart for the clock synchronous system
transmission is shown in Figure 5.8.6.4.
RXEN
TXEN
RXTRG (RD)
RXTRG (WR)
SCLK
TXTRG (RD)
TXTRG (WR)
SCLK
SIN
D0 D1 D2 D3 D4 D5 D6 D7
SOUT
D0 D1 D2 D3 D4 D5 D6 D7
TRXD
Interrupt
7F
1st data
Interrupt
(a) Transmit timing for master mode
(c) Receive timing for master mode
RXEN
TXEN
RXTRG (RD)
RXTRG (WR)
SCLK
TXTRG (RD)
TXTRG (WR)
SCLK
SIN
D0 D1 D2 D3 D4 D5 D6 D7
7F
SOUT
D0 D1 D2 D3 D4 D5 D6 D7
TRXD
1st data 7F
SRDY
SRDY
Interrupt
Interrupt
(b) Transmit timing for slave mode
(d) Receive timing for slave mode
Fig. 5.8.6.4 Timing chart (clock synchronous system transmission, LSB first)
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
■ Initialization of serial interface
The below initialization must be done in cases of
5.8.7 Operation of asynchronous transfer
Asynchronous transfer is a mode that transfers by
adding a start bit and a stop bit to the front and the
back of each piece of serial converted data. In this
mode, there is no need to use a clock that is fully
synchronized clock on the transmit side and the
receive side, but rather transmission is done while
adopting the synchronization at the start/ stop bits
that have attached before and after each piece of
data. The RS-232C interface functions can be easily
realized by selecting this transfer mode.
asynchronous system transfer.
(1) Setting of transmitting/receiving disable
To set the serial interface into a status in which
both transmitting and receiving are disabled, "0"
must be written to both the transmit enable
register TXEN and the receive enable register
RXEN. Fix these two registers to a disable status
until data transfer actually begins.
(2) Port selection
This interface has separate transmit and receive
shift registers and is designed to permit full duplex
transmission to be done simultaneously for trans-
mitting and receiving.
Because serial interface input/ output terminals
SIN and SOUT are set as I/ O port terminals P10
and P11 at initial reset, "1" must be written to
the serial interface enable register ESIF in order
to set these terminals for serial interface use.
For transfer data in the asynchronous 7-bit mode,
either 7 bits data (no parity) or 7 bits data + parity
bit can be selected. In the asynchronous 8-bit mode,
either 8 bits data (no parity) or 8 bits data + parity
bit can be selected.
_________
_________
SCLK and SRDY terminals set in the clock
synchronous mode are not used in the asynchro-
nous mode. These terminals function as I/ O
port terminals P12 and P13.
Parity can be even or odd, and parity checking of
received data and adding a party bit to transmitting
data will be done automatically. Thereafter, it is not
necessary to be conscious of parity itself in the
program.
The start bit length is fixed at 1 bit. For the stop bit
length, either 1 bit or 2 bits can be selected using
the stop bit select register STPB. Whether data is
transmitted/ received from LSB (bit 0) or MSB (bit
7) it can be switched using the data input/ output
permutation select register SDP.
(3) Setting of transfer mode
Select the asynchronous mode by writing the
data as indicated below to the two bits of the
mode selection registers SMD0 and SMD1.
7-bit mode:
8-bit mode:
SMD0 = "0", SMD1 = "1"
SMD0 = "1", SMD1 = "1"
(4) Parity bit selection
When checking and adding parity bits, write "1"
into the parity enable register EPR to set to "with
parity check". As a result of this setting, in the
asynchronous 7-bit mode, it has a 7 bits data +
parity bit configuration and in the asynchronous
8-bit mode it has an 8 bits data + parity bit
configuration.In this case, parity checking for
receiving and adding a party bit for transmitting
is done automatically in hardware. Moreover,
when "with parity check" has been selected,
"odd" or "even" parity must be further selected in
the parity mode selection register PMD.
LSB first
Sampling
clock
7bit data
s1 D0 D1 D2 D3 D4 D5 D6 s2
s1 D0 D1 D2 D3 D4 D5 D6
s1 D0 D1 D2 D3 D4 D5 D6 D7 s2
7bit data
+parity
p
s2
8bit data
8bit data
+parity
s1 D0 D1 D2 D3 D4 D5 D6 D7
p
s2
When "0" is written to the PMD register to select
"without parity check" in the asynchronous 7-bit
mode, data configuration is set to 7 bits data (no
parity) and in the asynchronous 8-bit mode (no
parity) it is set to 8 bits data (no parity) and parity
checking and parity bit adding will not be done.
MSB first
Sampling
clock
7bit data
s1 D6 D5 D4 D3 D2 D1 D0 s2
s1 D6 D5 D4 D3 D2 D1 D0
7bit data
+parity
p
s2
8bit data
s1 D7 D6 D5 D4 D3 D2 D1 D0 s2
(5) Clock source selection
8bit data
+parity
s1 D7 D6 D5 D4 D3 D2 D1 D0
p
s2
Select the clock source by writing data to the
two bits of the clock source selection registers
SCS0 and SCS1. (See Table 5.8.4.1.)
s1 : Start bit (Low level, 1 bit)
s2 : Stop bit (High level, 1 bit or 2 bits)
p : Parity bit
Since all the registers mentioned in (2)–(5) are
assigned to the same address, it's possible to set
them all with one instruction.
Fig. 5.8.7.1 Transfer data configuration
for asynchronous system
Here following, we will explain the control se-
quence and operation for initialization and trans-
mitting / receiving in case of asynchronous data
transfer. See "5.8.8 Interrupt function" for the serial
interface interrupts.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
(6) Clock source control
(4) Write "1" in the transmit control bit TXTRG and
When the programmable timer is selected for
the clock source, set transfer rate on the pro-
grammable timer side. (See "5.10 Programmable
Timer".)
When the divided signal of OSC3 oscillation
circuit is selected for the clock source, be sure
that the OSC3 oscillation circuit is turned ON
prior to commencing data transfer. (See "5.4
Oscillation Circuits".)
start transmitting.
This control causes the shift clock to change to
enable and a start bit (LOW) is output to the
SOUT terminal in synchronize to its rising edge.
The transmitting data set to the shift register is
shifted one bit at a time at each rising edge of
the clock thereafter and is output from the
SOUT terminal. After the data output, it outputs
a stop bit (HIGH) and HIGH level is maintained
until the next start bit is output.
(7) Stop bit length selection
The stop bit length can be configured to 1 bit or
2 bits using the stop bit select register STPB.
The transmitting complete interrupt factor flag
FSTRA is set to "1" at the point where the data
transmitting is completed. When interrupt has
been enabled, a transmitting complete interrupt
is generated at this point.
Table 5.8.7.1 Stop bit and parity bit settings
Settings
STPB EPR PMD
Stop bit
2 bits
2 bits
2 bits
1 bit
Parity bit
Odd
Set the following transmitting data using this
interrupt.
1
1
1
0
–
1
0
–
Even
(5) Repeat steps (3) to (4) for the number of bytes of
transmitting data, and then set the transmit
disable status by writing "0" to the transmit
enable register TXEN, when the transmitting is
completed.
0
1
Non parity
Odd
0
1 bit
Even
0
1 bit
Non parity
(8) Serial data input/output permutation
The S1C88650 provides the data input/ output
permutation select register SDP to select
whether the serial data bits are transfered from
the LSB or MSB. The SDP register should be set
before writing data to TRXD0–TRXD7.
Data transmitting
TXEN ← 0
TXEN ← 1
■ Data transmit procedure
The control procedure and operation during
transmitting is as follows.
Set transmitting data
to TRXD0–TRXD7
(1) Write "0" in the transmit enable register TXEN
to reset the serial interface.
TXTRG ← 1
No
(2) Write "1" in the transmit enable register TXEN
to set into the transmitting enable status.
FSTRA = 1 ?
Yes
(3) Write the transmitting data into TRXD0–TRXD7.
Also, when 7-bit data is selected, the TRXD7
data becomes invalid.
No
Transmit complete ?
Yes
TXEN ← 0
End
Fig. 5.8.7.2 Transmit procedure in asynchronous mode
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
■ Data receive procedure
(5) Write "1" to the receive control bit RXTRG to
inform that the receive data has been read out.
When the following data is received prior to
writing "1" to RXTRG, it is recognized as an
overrun error and the error interrupt factor flag is
set to "1". When the interrupt has been enabled,
an error interrupt is generated at this point just as
in the framing error and parity error mentioned
above.
The control procedure and operation during
receiving is as follows.
(1) Write "0" in the receive enable register RXEN to
set the receiving disable status and to reset the
respective PER, OER, FER flags that indicate
parity, overrun and framing errors.
(2) Write "1" in the receive enable register RXEN to
set into the receiving enable status.
(6) Repeat steps (3) to (5) for the number of bytes of
receiving data, and then set the receive disable
status by writing "0" to the receive enable register
RXEN, when the receiving is completed.
(3) The shift clock will change to enable from the
point where the start bit (LOW) has been input
from the SIN terminal and the receive data will
be synchronized to the rising edge following the
second clock, and will thus be successively
incorporated into the shift register.
Data receiving
After data bits have been incorporated, the stop bit
is checked and, if it is not HIGH, it becomes a
framing error and the error interrupt factor flag
FSERR is set to "1". When interrupt has been
enabled, an error interrupt is generated at this point.
When receiving is completed, data in the shift
register is transferred to the received data buffer
and the receiving complete interrupt flag FSREC
is set to "1". When interrupt has been enabled, a
receiving complete interrupt is generated at this
point. (When an overrun error is generated, the
interrupt factor flag FSREC is not set to "1" and a
receiving complete interrupt is not generated.)
If "with parity check" has been selected, a parity
check is executed when data is transferred into
the received data buffer from the shift register
and if a parity error is detected, the error inter-
rupt factor flag is set to "1". When the interrupt
has been enabled, an error interrupt is generated
at this point just as in the framing error men-
tioned above.
RXEN ← 0
Resets error flags
PER, OER and FER
RXEN ← 1
Yes
Error generated ?
No
No
Receiving interrupt ?
Yes
Received data reading
Error processing
from TRXD0–TRXD7
RXTRG ← 1
No
Receiving complete ?
Yes
RXEN ← 0
(4) Read the received data from TRXD0–TRXD7
using receiving complete interrupt.
End
Fig. 5.8.7.3 Receiving procedure in asynchronous mode
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
■ Receive error
(3) Overrun error
During receiving the following three types of errors
can be detected by an interrupt.
When the next data is received before "1" is
written to RXTRG, an overrun error will be
generated, because the previous receive data
will be overwritten. When this error is gener-
ated, the overrun error flag OER and the error
interrupt factor flag FSERR are set to "1". When
interrupt has been enabled, an error interrupt is
generated at this point. The OER flag is reset to
"0" by writing "1" into it.
Even when this error has been generated, the
received data corresponding to the error is
transferred in the received data buffer and the
receive operation also continues.
(1) Parity error
When writing "1" to the EPR register to select
"with parity check", a parity check (vertical
parity check) is executed during receiving. After
each data bit is sent a parity check bit is sent.
The parity check bit is a "0" or a "1". Even parity
checking will cause the sum of the parity bit
and the other bits to be even. Odd parity causes
the sum to be odd. This is checked on the
receiving side.
The parity check is performed when data
received in the shift register is transferred to the
received data buffer. It checks whether the
parity check bit is a "1" or a "0" (the sum of the
bits including the parity bit) and the parity set
in the PMD register match. When it does not
match, it is recognized as an parity error and the
parity error flag PER and the error interrupt
factor flag FSERR are set to "1".
Furthermore, when the timing for writing "1" to
RXTRG and the timing for the received data
transfer to the received data buffer overlap, it
will be recognized as an overrun error.
■ Timing chart
Figure 5.8.7.4 show the asynchronous transfer
timing chart.
When interrupt has been enabled, an error
interrupt is generated at this point.
The PER flag is reset to "0" by writing "1".
Even when this error has been generated, the
received data corresponding to the error is
transferred in the received data buffer and the
receive operation also continues.
The received data at this point cannot assured
because of the parity error.
(2) Framing error
In asynchronous transfer, synchronization is
adopted for each character at the start bit ("0")
and the stop bit ("1"). When receiving has been
done with the stop bit set at "0", the serial
interface judges the synchronization to be off
and a framing error is generated. When this
error is generated, the framing error flag FER
and the error interrupt factor flag FSERR are set
to "1". When interrupt has been enabled, an
error interrupt is generated at this point.
The FER flag is reset to "0" by writing "1".
Even when this error has been generated, the
received data for it is loaded into the receive
data buffer and the receive operation also
continues. However, even when it does not
become a framing error with the following data
receipt, such data cannot be assured.
Even when this error has been generated, the
received data corresponding to the error is
transferred in the received data buffer and the
receive operation also continues. However, even
when it does not become a framing error with
the following data receiving, such data cannot
be assured.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
TXEN
TXTRG(RD)
TXTRG(WR)
Sumpling
clock
D0 D1 D2 D3 D4 D5 D6 D7
SOUT
(In 8-bit mode/Non parity)
Interrupt
(a) Transmit timing
RXEN
RXTRG(RD)
RXTRG(WR)
Sumpling
clock
SIN
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
(In 8-bit mode/Non parity)
TRXD
1st data
2st data
OER control signal
OER
Interrupt
(b) Receive timing
Fig. 5.8.7.4 Timing chart (asynchronous transfer, LSB first, stop bit = 1 bit)
■ Transmitting complete interrupt
5.8.8 Interrupt function
This interrupt factor is generated at the point where
the sending of the data written into the shift
register has been completed and sets the interrupt
factor flag FSTRA to "1". When set in this manner, if
the corresponding interrupt enable register ESTRA
is set to "1" and the corresponding interrupt priority
registers PSIF0 and PSIF1 are set to a higher level
than the setting of interrupt flags (I0 and I1), an
interrupt will be generated to the CPU.
When "0" has been written into the interrupt enable
register ESTRA and interrupt has been disabled, an
interrupt is not generated to the CPU. Even in this
case, the interrupt factor flag FSTRA is set to "1".
The interrupt factor flag FSTRA is reset to "0" by
writing "1".
This serial interface includes a function that
generates the below indicated three types of
interrupts.
• Transmitting complete interrupt
• Receiving complete interrupt
• Error interrupt
The interrupt factor flag FSxxx and the interrupt
enable register ESxxx for the respective interrupt
factors are provided and then the interrupt enable/
disable can be selected by the software. In addition,
a priority level of the serial interface interrupt for
the CPU can be optionally set at levels 0 to 3 by the
interrupt priority registers PSIF0 and PSIF1.
For details on the above mentioned interrupt
control register and the operation following
generation of an interrupt, see "5.14 Interrupt and
Standby Status".
The following transmitting data can be set and the
transmitting start (writing "1" to TXTRG) can be
controlled by generation of this interrupt factor.
The exception processing vector address is set as
follows:
Figure 5.8.8.1 shows the configuration of the serial
interface interrupt circuit.
Transmitting complete interrupt: 00002CH
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
Interrupt priority
register PSIF0, PSIF1
Address
Error generation
Interrupt factor
flag
FSERR
Address
Interrupt enable
register ESERR
Address
Receive completion
Address
Interrupt factor
flag
FSREC
Interrupt priority
level judgement
circuit
Interrupt
request
Interrupt enable
register ESREC
Address
Transmit completion
Address
Interrupt factor
flag
FSTRA
Interrupt enable
register ESTRA
Address
Fig. 5.8.8.1 Configuration of serial interface interrupt circuit
■ Error interrupt
■ Receiving complete interrupt
This interrupt factor is generated at the point where
a parity error, framing error or overrun error is
detected during receiving and it sets the interrupt
factor flag FSERR to "1". When set in this manner, if
the corresponding interrupt enable register ESERR
is set to "1" and the corresponding interrupt priority
registers PSIF0 and PSIF1 are set to a higher level
than the setting of interrupt flags (I0 and I1), an
interrupt will be generated to the CPU.
When "0" has been written in the interrupt enable
register ESERR and interrupt has been disabled, an
interrupt is not generated to the CPU. Even in this
case, the interrupt factor flag FSERR is set to "1".
The interrupt factor flag FSERR is reset to "0" by
writing "1".
This interrupt factor is generated at the point where
receiving has been completed and the receive data
incorporated into the shift register has been trans-
ferred into the received data buffer and it sets the
interrupt factor flag FSREC to "1". When set in this
manner, if the corresponding interrupt enable
register ESREC is set to "1" and the corresponding
interrupt priority registers PSIF0 and PSIF1 are set to
a higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
When "0" has been written into the interrupt enable
register ESREC and interrupt has been disabled, an
interrupt is not generated to the CPU. Even in this
case, the interrupt factor flag FSREC is set to "1".
The interrupt factor flag FSREC is reset to "0" by
writing "1".
Since all three types of errors result in the same
interrupt factor, you should identify the error that
has been generated by the error flags PER (parity
error), OER (overrun error) and FER (framing
error).
The generation of this interrupt factor permits the
received data to be read.
Also, the interrupt factor flag is set to "1" when a
parity error or framing error is generated.
The exception processing vector address is set as
follows:
The exception processing vector address is set as
follows:
Receive error interrupt: 000028H.
Receiving complete interrupt: 00002AH.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.8.9 Control of serial interface
Table 5.8.9.1 show the serial interface control bits.
Table 5.8.9.1(a) Serial interface control bits
Address Bit Name
00FF48 D7 –
D6 EPR
Function
1
0
SR R/W
Comment
–
–
–
–
"0" when being read
Parity enable register
Parity mode selection
Clock source selection
SCS1 SCS0
With parity Non parity
0
0
0
R/W Only for
D5 PMD
Odd
Even
R/W asynchronous mode
R/W In the clock synchro-
nous slave mode,
D4 SCS1
Clock source
1
1
0
0
1
0
1
0
Programmable timer
fOSC3 / 4
external clock is
D3 SCS0
D2 SMD1
D1 SMD0
0
0
0
R/W selected.
fOSC3 / 8
fOSC3 / 16
Serial I/F mode selection
SMD1 SMD0
R/W
R/W
Mode
1
1
0
0
1
0
1
0
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
D0 ESIF
00FF49 D7 –
D6 FER
Serial I/F enable register
Serial I/F
–
I/O port
–
0
–
0
R/W
–
"0" when being read
R/W Only for
asynchronous mode
R/W
Serial I/F framing error flag
R
W
R
Error
No error
Reset (0) No operation
Error No error
Reset (0) No operation
Error No error
Reset (0) No operation
D5 PER
D4 OER
Serial I/F parity error flag
Serial I/F overrun error flag
0
0
0
W
R
R/W
R/W
W
R
D3 RXTRG Serial I/F receive trigger/status
Run
Stop
No operation
Disable
W
Trigger
Enable
Run
D2 RXEN
Serial I/F receive enable
0
0
R/W
R/W
D1 TXTRG Serial I/F transmit trigger/status
R
Stop
W
Trigger
Enable
No operation
Disable
D0 TXEN
Serial I/F transmit enable
0
R/W
00FF4A D7 TRXD7 Serial I/F transmit/Receive data D7 (MSB)
D6 TRXD6 Serial I/F transmit/Receive data D6
D5 TRXD5 Serial I/F transmit/Receive data D5
D4 TRXD4 Serial I/F transmit/Receive data D4
D3 TRXD3 Serial I/F transmit/Receive data D3
D2 TRXD2 Serial I/F transmit/Receive data D2
D1 TRXD1 Serial I/F transmit/Receive data D1
D0 TRXD0 Serial I/F transmit/Receive data D0 (LSB)
High
Low
X
R/W
00FF4B D7 –
D6 –
–
–
–
–
–
–
–
–
–
0
0
Constantly "0" when
being read
–
–
–
D5 –
–
–
–
D4 –
–
–
–
–
D3 –
–
–
–
D2 –
–
–
D1 STPB
D0 SDP
Serial I/F stop bit selection
2 bits
1 bit
R/W
R/W
Serial I/F data input/output permutation selection MSB first
LSB first
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
Table 5.8.9.1(b) Serial interface control bits
Address Bit Name
00FF20 D7 PK01
D6 PK00
Function
1
0
SR R/W
Comment
PK01 PK00 Priority
PSIF1 PSIF0 level
K00–K07 interrupt priority register
0
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D5 PSIF1
D4 PSIF0
D3 –
Serial interface interrupt priority register
0
R/W
–
–
–
–
–
–
0
Constantly "0" when
being read
D2 –
–
–
PTM1 PTM0 Priority level
D1 PTM1
Clock timer interrupt priority register
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D0 PTM0
00FF23 D7 –
D6 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D5 –
D4 –
D3 –
D2 ESERR Serial I/F (error) interrupt enable register
D1 ESREC Serial I/F (receiving) interrupt enable register
D0 ESTRA Serial I/F (transmitting) interrupt enable register
Interrupt
enable
Interrupt
disable
0
R/W
00FF27 D7 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
(R)
(R)
D2 FSERR Serial I/F (error) interrupt factor flag
D1 FSREC Serial I/F (receiving) interrupt factor flag
D0 FSTRA Serial I/F (transmitting) interrupt factor flag
Generated No generated
(W)
Reset
0
R/W
(W)
No operation
ESIF: 00FF48H•D0
SMD0, SMD1: 00FF48H•D1, D2
Sets the serial interface terminals (P10–P13).
Set the transfer modes according to Table 5.8.9.2.
When "1" is written: Serial input/ output terminal
When "0" is written: I/ O port terminal
Table 5.8.9.2 Transfer mode settings
SMD1
SMD0
Mode
Reading:
Valid
1
1
0
0
1
0
1
0
Asynchronous 8-bit
Asynchronous 7-bit
The ESIF is the serial interface enable register and
P10–P13 terminals become ser_i_a__l_i__n__put/ output
Clock synchronous slave
Clock synchronous master
_________
terminals (SIN, SOUT, SCLK, SRDY) when "1" is
written, and they become I/ O port terminals when
"0" is written.
Also, see Table 5.8.3.2 for the terminal settings
according to the transfer modes.
SMD0 and SMD1 can also read out.
At initial reset, this register is set to "0" (clock
synchronous master mode).
At initial reset, ESIF is set to "0" (I/ O port).
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SCS0, SCS1: 00FF48H•D3, D4
PMD: 00FF48H•D5
Select the clock source according to Table 5.8.9.3.
Selects odd parity/ even parity.
Table 5.8.9.3 Clock source selection
When "1" is written: Odd parity
When "0" is written: Even parity
SCS1
SCS0
Clock source
Programmable timer
fOSC3 / 4
Reading:
Valid
1
1
0
0
1
0
1
0
When "1" is written to PMD, odd parity is selected
and even parity is selected when "0" is written. The
parity check and addition of a parity bit is only
valid when "1" has been written to EPR. When "0"
has been written to EPR, the parity setting by PMD
becomes invalid.
fOSC3 / 8
fOSC3 / 16
SCS0 and SCS1 can also be read out.
In the clock synchronous slave mode, setting of this
register is invalid.
At initial reset, PMD is set to "0" (even parity).
At initial reset, this register is set to "0" (fOSC3/ 16).
TXEN: 00FF49H•D0
SDP: 00FF4BH•D0
Sets the serial interface to the transmitting enable
status.
Selects the serial data input/ output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
When "1" is written: Transmitting enable
When "0" is written: Transmitting disable
Reading:
Valid
Reading:
Valid
Select whether the data input/ output permutation
will be MSB first or LSB first.
At initial reset, SDP is set to "0" (LSB first).
When "1" is written to TXEN, the serial interface
shifts to the transmitting enable status and shifts to
the transmitting disable status when "0" is written.
Set TXEN to "0" when making the initial settings of
the serial interface and similar operations.
At initial reset, TXEN is set to "0" (transmitting
disable).
STPB: 00FF4BH•D1
Selects the stop bit length for asynchronous data
transfer.
When "1" is written: 2 bits
When "0" is written: 1 bit
TXTRG: 00FF49H•D1
Functions as the transmitting start trigger and the
operation status indicator (transmitting/ stop
status).
Reading:
Valid
STPB is the stop bit select register that is effective in
asynchronous mode. When "1" is written to STPB,
the stop bit length is set to 2 bits, and when "0" is
written, it is set to 1 bit.
When "1" is read:
When "0" is read:
During transmitting
During stop
In clock synchronous mode, no start/ stop bits can
be added to transfer data. Therefore, setting STPB
becomes invalid.
When "1" is written: Transmitting start
When "0" is written: Invalid
Starts the transmitting when "1" is written to
TXTRG after writing the transmitting data.
TXTRG can be read as the status. When set to "1", it
indicates transmitting operation, and "0" indicates
transmitting stop.
At initial reset, STPB is set to "0" (1 bit).
EPR: 00FF48H•D6
Selects the parity function.
When "1" is written: With parity
When "0" is written: Non parity
At initial reset, TXTRG is set to "0" (during stop).
RXEN: 00FF49H•D2
Reading:
Valid
Sets the serial interface to the receiving enable status.
Selects whether or not to check parity of the
received data and to add a parity bit to the trans-
mitting data. When "1" is written to EPR, the most
significant bit of the received data is considered to
be the parity bit and a parity check is executed. A
parity bit is added to the transmitting data. When
"0" is written, neither checking is done nor is a
parity bit added.
When "1" is written: Receiving enable
When "0" is written: Receiving disable
Reading:
Valid
When "1" is written to RXEN, the serial interface
shifts to the receiving enable status and shifts to the
receiving disable status when "0" is written.
Set RXEN to "0" when making the initial settings of
the serial interface and similar operations.
Parity is valid only in asynchronous mode and the
EPR setting becomes invalid in the clock synchro-
nous mode.
At initial reset, RXEN is set to "0" (receiving disable).
At initial reset, EPR is set to "0" (non parity).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
During receiving
Read the received data.
RXTRG: 00FF49H•D3
Functions as the receiving start trigger or prepara-
tion for the following data receiving and the opera-
tion status indicator (during receiving/ during stop).
When "1" is read:
When "0" is read:
HIGH level
LOW level
The data from the received data buffer can be read out.
Since the sift register is provided separately from
this buffer, reading can be done during the receive
operation in the asynchronous mode. (The buffer
function is not used in the clock synchronous mode.)
Read the data after waiting for the receiving
complete interrupt.
When performing parity check in the asynchronous
7-bit mode, "0" is loaded into the 8th bit (TRXD7)
that corresponds to the parity bit.
When "1" is read:
When "0" is read:
During receiving
During stop
When "1" is written: Receiving start/ following
data receiving preparation
When "0" is written: Invalid
RXTRG has a slightly different operation in the clock
synchronous system and the asynchronous system.
The RXTRG in the clock synchronous system, is
used as the trigger for the receiving start.
The serial data input from the SIN terminal is level
converted, making the HIGH (VDD) level bit "1" and
the LOW (VSS) level bit "0" and is then loaded into
this buffer.
Writes "1" into RXTRG to start receiving at the
point where the receive data has been read and the
following receiv_e__p__r__e_p_ aration has been done. (In
the slave mode, SRDY becomes "0" at the point
where "1" has been written into into the RXTRG.)
At initial reset, the buffer content is undefined.
OER: 00FF49H•D4
RXTRG is used in the asynchronous system for
preparation of the following data receiving. Reads
the received data located in the received data buffer
and writes "1" into RXTRG to inform that the
received data buffer has shifted to empty. When "1"
has not been written to RXTRG, the overrun error
flag OER is set to "1" at the point where the follow-
ing receiving has been completed. (When the
receiving has been completed between the opera-
tion to read the received data and the operation to
write "1" into RXTRG, an overrun error occurs.)
Indicates the generation of an overrun error.
When "1" is read:
When "0" is read:
Error
No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
OER is an error flag that indicates the generation of
an overrun error and becomes "1" when an error
has been generated.
An overrun error is generated when the receiving
of data has been completed prior to the writing of
"1" to RXTRG in the asynchronous mode.
OER is reset to "0" by writing "1".
In addition, RXTRG can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRG is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
At initial reset and when RXEN is "0", OER is set to
"0" (no error).
At initial reset, RXTRG is set to "0" (during stop).
PER: 00FF49H•D5
TRXD0–TRXD7: 00FF4AH
Indicates the generation of a parity error.
During transmitting
Write the transmitting data into the transmit shift
register.
When "1" is read:
When "0" is read:
Error
No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
When "1" is written: HIGH level
When "0" is written: LOW level
PER is an error flag that indicates the generation of
a parity error and becomes "1" when an error has
been generated.
Write the transmitting data prior to starting
transmitting.
In the case of continuous transmitting, wait for the
transmitting complete interrupt, then write the data.
The TRXD7 becomes invalid for the asynchronous
7-bit mode.
When a parity check is performed in the asynchro-
nous mode, if data that does not match the parity is
received, a parity error is generated.
PER is reset to "0" by writing "1".
Converted serial data for which the bits set at "1" as
HIGH (VDD) level and for which the bits set at "0"
as LOW (VSS) level are output from the SOUT
terminal.
At initial reset and when RXEN is "0", PER is set to
"0" (no error).
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FER: 00FF49H•D6
FSTRA, FSREC, FSERR: 00FF27H•D0, D1, D2
Indicates the generation of a framing error.
Indicates the serial interface interrupt generation status.
When "1" is read:
When "0" is read:
Error
No error
When "1" is read:
When "0" is read:
Interrupt factor present
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
When "1" is written: Reset to "0"
When "0" is written: Invalid
FSTRA, FSREC and FSERR are interrupt factor flags
that respectively correspond to the interrupts for
transmitting complete, receiving complete and
receiving error and are set to "1" by generation of
each factor.
Transmitting complete interrupt factor is generated
at the point where the data transmitting of the shift
register has been completed.
Receiving complete interrupt factor is generated at
the point where the received data has been trans-
ferred into the received data buffer.
Receive error interrupt factor is generated when a
parity error, framing error or overrun error has been
detected during data receiving.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the corre-
sponding interrupt priority register is set to a higher
level than the setting of interrupt flags (I0 and I1), an
interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
FER is an error flag that indicates the generation of
a framing error and becomes "1" when an error has
been generated.
When the stop bit for the receiving of the asynchro-
nous mode has become "0", a framing error is
generated.
FER is reset to "0" by writing "1".
At initial reset and when RXEN is "0", FER is set to
"0" (no error).
PSIF0, PSIF1: 00FF20H•D4, D5
Sets the priority level of the serial interface interrupt.
The two bits PSIF0 and PSIF1 are the interrupt
priority register corresponding to the serial inter-
face interrupt. Table 5.8.9.4 shows the interrupt
priority level which can be set by this register.
Table 5.8.9.4 Interrupt priority level settings
PSIF1
PSIF0
Interrupt priority level
Level 3 (IRQ3)
1
1
0
0
1
0
1
0
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
ESTRA, ESREC, ESERR: 00FF23H•D0, D1, D2
Enables or disables the generation of an interrupt
for the CPU.
At initial reset, this flag is reset to "0".
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
ESTRA, ESREC and ESERR are interrupt enable
registers that respectively correspond to the inter-
rupt factors for transmitting complete, receiving
complete and receiving error. Interrupts set to "1"
are enabled and interrupts set to "0" are disabled.
At initial reset, this register is set to "0" (interrupt
disabled).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.8.10 Programming notes
(1) Be sure to initialize the serial interface mode in
the transmitting/ receiving disable status (TXEN
= RXEN = "0").
(2) Do not perform double trigger (writing "1") to
TXTRG (RXTRG) when the serial interface is in the
transmitting (receiving) operation. Furthermore, do
not execute the SLP instruction. (When executing
the SLP instruction, set TXEN = RXEN = "0".)
(3) In the clock synchronous mode, since one clock
_________
line (SCLK) is shared for both transmitting and
receiving, transmitting and receiving cannot be
performed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Consequently, be sure not to write "1" to
RXTRG (TXTRG) when TXTRG (RXTRG) is "1".
(4) When a parity error or flaming error is generated
during receiving in the asynchronous mode, the
receiving error interrupt factor flag FSERR is set
to "1" prior to the receiving complete interrupt
factor flag FSREC for the time indicated in Table
5.8.10.1. Consequently, when an error is generated,
you should reset the receiving complete interrupt
factor flag FSREC to "0" by providing a wait time in
error processing routines and similar routines.
When an overrun error is generated, the receiving
complete interrupt factor flag FSREC is not set to "1"
and a receiving complete interrupt is not generated.
Table 5.8.10.1 Time difference between FSERR
and FSREC on error generation
Clock source
Time difference
1/2 cycles of fOSC3 / n
fOSC3 / n
Programmable timer
1 cycle of timer 1 underflow
(5) When the demultiplied signal of the OSC3
oscillation circuit is made the clock source, it is
necessary to turn the OSC3 oscillation ON, prior to
using the serial interface.
A time interval of several msec to several 10 msec,
from the turning ON of the OSC3 oscillation
circuit to until the oscillation stabilizes, is neces-
sary, due to the oscillation element that is used.
Consequently, you should allow an adequate
waiting time after turning ON of the OSC3
oscillation, before starting transmitting/ receiving
of serial interface. (The oscillation start time will
vary somewhat depending on the oscillator and on
the externally attached parts. Refer to the
oscillation start time example indicated in Chapter
8, "ELECTRICAL CHARACTERISTICS".)
At initial reset, the OSC3 oscillation circuit is set to
ON status.
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5.9.2 Interrupt function
The clock timer can generate an interrupt by each of
the 32 Hz, 8 Hz, 2 Hz and 1 Hz signals.
5.9 Clock Timer
5.9.1 Configuration of clock timer
The configuration of the clock timer interrupt
The S1C88650 has built in a clock timer that uses
the OSC1 oscillation circuit as clock source. The
clock timer is composed of an 8-bit binary counter
that uses the 256 Hz signal dividing fOSC1 as its
input clock and can read the data of each bit (128–1
Hz) by software.
Normally, this clock timer is used for various
timing functions such as clocks.
The configuration of the clock timer is shown in
Figure 5.9.1.1.
circuit is shown in Figure 5.9.2.1.
Interrupts are generated by respectively setting the
corresponding interrupt factor flags FTM32, FTM8,
FTM2 and FTM1 at the falling edge of the 32 Hz, 8
Hz, 2 Hz and 1 Hz signals to "1". Interrupt can be
prohibited by the setting the interrupt enable
registers ETM32, ETM8, ETM2 and ETM1 corre-
sponding to each interrupt factor flag.
In addition, a priority level of the clock timer
interrupt for the CPU can be optionally set at levels
0 to 3 by the interrupt priority registers PTM0 and
PTM1.
For details on the above mentioned interrupt
control register and the operation following
generation of an interrupt, see "5.14 Interrupt and
Standby Status".
The exception processing vector addresses for each
interrupt factor are respectively set as shown
below.
32 Hz interrupt:
8 Hz interrupt:
2 Hz interrupt:
1 Hz interrupt:
000034H
000036H
000038H
00003AH
Figure 5.9.2.2 shows the timing chart for the clock
timer.
Data bus
Clock timer
TMD0–TMD7
OSC1
oscillation
circuit
fOSC1
256 Hz
128 64 32 16
Hz Hz Hz Hz Hz Hz Hz Hz
8
4
2
1
Divider
Clock timer reset
Clock timer Run/Stop
TMRST
Interrupt
request
Interrupt control circuit
TMRUN
Fig. 5.9.1.1 Configuration of clock timer
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer)
Interrupt priority
register PTM0, PTM1
Address
32 Hz falling edge
Interrupt factor
flag
FTM32
Address
Interrupt enable
register ETM32
Address
8 Hz falling edge
Address
Interrupt factor
flag
FTM8
Interrupt enable
register ETM8
Interrupt priority
level judgement
circuit
Address
Interrupt
request
2 Hz falling edge
Address
Interrupt factor
flag
FTM2
Interrupt enable
register ETM2
Address
1 Hz falling edge
Address
Interrupt factor
flag
FTM1
Interrupt enable
register ETM1
Address
Fig. 5.9.2.1 Configuration of clock timer interrupt circuit
OSC1/128 256 Hz
TMD0 128 Hz
TMD1
TMD2
TMD3
TMD4
TMD5
TMD6
TMD7
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
32 Hz interrupt
8 Hz interrupt
2 Hz interrupt
1 Hz interrupt
Fig. 5.9.2.2 Timing chart of clock timer
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5.9.3 Control of clock timer
Table 5.9.3.1 shows the clock timer control bits.
Table 5.9.3.1 Clock timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF40 D7 WDEN Watchdog timer enable
D6 FOUT2 FOUT frequency selection
FOUT2 FOUT1 FOUT0
Enable
Disable
1
0
R/W
R/W
Frequency
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D5 FOUT1
D4 FOUT0
0
0
R/W
R/W
D3 FOUTON FOUT output control
D2 WDRST Watchdog timer reset
D1 TMRST Clock timer reset
On
Off
0
–
–
0
R/W
W
Reset
Reset
Run
No operation
No operation
Stop
Constantly "0" when
being read
W
D0 TMRUN Clock timer Run/Stop control
R/W
00FF41 D7 TMD7
Clock timer data 1 Hz
Clock timer data 2 Hz
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
Clock timer data 32 Hz
Clock timer data 64 Hz
Clock timer data 128 Hz
D6 TMD6
D5 TMD5
D4 TMD4
D3 TMD3
D2 TMD2
D1 TMD1
D0 TMD0
00FF20 D7 PK01
D6 PK00
High
Low
0
R
PK01 PK00 Priority
PSIF1 PSIF0 level
K00–K07 interrupt priority register
0
0
R/W
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D5 PSIF1
D4 PSIF0
D3 –
Serial interface interrupt priority register
–
–
–
–
–
–
0
Constantly "0" when
being read
D2 –
–
–
PTM1 PTM0 Priority level
D1 PTM1
Clock timer interrupt priority register
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D0 PTM0
00FF22 D7 –
D6 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D5 –
D4 –
D3 ETM32 Clock timer 32 Hz interrupt enable register
D2 ETM8
D1 ETM2
D0 ETM1
Clock timer 8 Hz interrupt enable register
Interrupt
enable
Interrupt
disable
0
R/W
Clock timer 2 Hz interrupt enable register
Clock timer 1 Hz interrupt enable register
00FF26 D7 –
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
D3 FTM32 Clock timer 32 Hz interrupt factor flag
(R)
(R)
D2 FTM8
D1 FTM2
D0 FTM1
Clock timer 8 Hz interrupt factor flag
Clock timer 2 Hz interrupt factor flag
Clock timer 1 Hz interrupt factor flag
Generated Not generated
0
R/W
(W)
(W)
Reset
No operation
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer)
TMD0–TMD7: 00FF41H
ETM1, ETM2, ETM8, ETM32: 00FF22H•D0–D3
The clock timer data can be read out.
Each bit of TMD0–TMD7 and frequency corre-
spondence are as follows:
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
TMD0: 128 Hz
TMD1: 64 Hz
TMD2: 32 Hz
TMD3: 16 Hz
TMD4: 8 Hz
TMD5: 4 Hz
TMD6: 2 Hz
TMD7: 1 Hz
Reading:
Valid
The ETM1, ETM2, ETM8 and ETM32 are interrupt
enable registers that respectively correspond to the
interrupt factors for 1 Hz, 2 Hz, 8 Hz and 32 Hz.
Interrupts set to "1" are enabled and interrupts set
to "0" are disabled.
Since the TMD0–TMD7 is exclusively for reading,
the write operation is invalid.
At initial reset, the timer data is set to "00H".
At initial reset, this register is set to "0" (interrupt
disabled).
TMRST: 00FF40H•D1
Resets the clock timer.
FTM1, FTM2, FTM8, FTM32: 00FF26H•D0–D3
When "1" is written: Clock timer reset
When "0" is written: No operation
Indicates the clock timer interrupt generation status.
Reading:
Always "0"
When "1" is read:
When "0" is read:
Interrupt factor present
Interrupt factor not present
The clock timer is reset by writing "1" to the
TMRST.
When "1" is written: Resets factor flag
When "0" is written: Invalid
When the clock timer is reset in the RUN status, it
restarts immediately after resetting. In the case of
the STOP status, the reset data "00H" is maintained.
No operation results when "0" is written to the
TMRST.
The FTM1, FTM2, FTM8 and FTM32 are interrupt
factor flags that respectively correspond to the
interrupts for 1 Hz, 2 Hz, 8 Hz and 32 Hz and are
set to "1" at the falling edge of each signal.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
Since the TMRST is exclusively for writing, it
always becomes "0" during reading.
TMRUN: 00FF40H•D0
Controls RUN/ STOP of the clock timer.
When "1" is written: RUN
When "0" is written: STOP
Reading:
Valid
The clock timer starts up-counting by writing "1" to
the TMRUN and stops by writing "0".
In the STOP status, the count data is maintained
until it is reset or set in the next RUN status. Also,
when the STOP status changes to the RUN status,
the data that was maintained can be used for
resuming the count.
At initial reset, the TMRUN is set to "0" (STOP).
At initial reset, this flag is reset to "0".
PTM0, PTM1: 00FF20H•D0, D1
Sets the priority level of the clock timer interrupt.
The two bits PTM0 and PTM1 are the interrupt
priority register corresponding to the clock timer
interrupt. Table 5.9.3.2 shows the interrupt priority
level which can be set by this register.
Table 5.9.3.2 Interrupt priority level settings
PTM1
PTM0
Interrupt priority level
Level 3 (IRQ3)
1
1
0
0
1
0
1
0
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
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5.9.4 Programming notes
(1) The clock timer is actually made to RUN/ STOP
in synchronization with the falling edge of the
256 Hz signal after writing to the TMRUN
register. Consequently, when "0" is written to
the TMRUN, the timer shifts to STOP status
when the counter is incremented "1". The
TMRUN maintains "1" for reading until the
timer actually shifts to STOP status.
Figure 5.9.4.1 shows the timing chart of the
RUN/ STOP control.
256 Hz
TMRUN(RD)
TMRUN(WR)
TMDX
57H
58H 59H 5AH 5BH
5CH
Fig. 5.9.4.1 Timing chart of RUN/STOP control
(2) The SLP instruction is executed when the clock
timer is in the RUN status (TMRUN = "1"). The
clock timer operation will become unstable
when returning from SLEEP status. Therefore,
when shifting to SLEEP status, set the clock
timer to STOP status (TMRUN = "0") prior to
executing the SLP instruction.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Two 8-bit down counters, the reload data register
5.10 Programmable Timer
and compare data register corresponding to each
down counter are arranged in the 16-bit program-
mable timer.
The reload data register is used to set an initial
value to the down counter.
The compare data register stores data for
comparison with the content of the down counter.
By setting these registers, a PWM waveform is
generated and it can be output to external devices
as the TOUT0, 1, 2 or 3 signal. Furthermore, the
serial interface clock is generated from the Timer 1
underflow signal. The Timer 5 underflow signal can
be used to set the frame frequency for the LCD
driver.
5.10.1 Configuration of
programmable timer
The S1C88650 has four built-in 16-bit program-
mable timer systems. Each system timer consists of
a 16-bit presettable down counter, and can be used
as 16-bit × 1 channel or 8-bit × 2 channels of
programmable timer. Furthermore, they function
as event counters using the input port terminal.
Figures 5.10.1.1 and 5.10.1.2 shows the configura-
tion of the 16-bit programmable timers.
INCL0
Timer 0
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR0)
Input port (K04)
EXCL0
TOUT0
8-bit down counter (PTM0)
Underflow
Clock output
Clock output circuit
Interrupt circuit
Comparator
Compare match
Control circuit
8-bit compare data register (CDR0)
Timer 0 control registers
Underflow
interrupt
Compare match
interrupt
Underflow signal
INCL1
Timer 1
8-bit reload data register (RDR1)
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
Input port (K04)
EXCL0
8-bit down counter (PTM1)
Comparator
Clock output
To serial I/F
Underflow
Clock output circuit
Interrupt circuit
TOUT1
Compare match
Control circuit
8-bit compare data register (CDR1)
Timer 1 control registers
Underflow
interrupt
Compare match
interrupt
INCL2
Timer 2
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR2)
Input port (K05)
EXCL1
TOUT2
8-bit down counter (PTM2)
Comparator
Underflow
Clock output
Clock output circuit
Interrupt circuit
TOUT2
Compare match
Control circuit
8-bit compare data register (CDR2)
Timer 2 control registers
Underflow
interrupt
Compare match
interrupt
Underflow signal
INCL3
Timer 3
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR3)
Input port (K05)
EXCL1
TOUT3
8-bit down counter (PTM3)
Comparator
Underflow
Clock output
Clock output circuit
Interrupt circuit
TOUT3
Compare match
Control circuit
8-bit compare data register (CDR3)
Timer 3 control registers
Underflow
interrupt
Compare match
interrupt
Fig. 5.10.1.1 Configuration of 16-bit programmable timer (Timers 1–3)
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INCL4
Timer 4
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR4)
8-bit down counter (PTM4)
Comparator
Input port (K06)
EXCL2
Underflow
Underflow
interrupt
Compare match
interrupt
Compare match
Interrupt circuit
Control circuit
8-bit compare data register (CDR4)
Timer 4 control registers
Underflow signal
INCL5
Timer 5
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR5)
Input port (K06)
EXCL2
8-bit down counter (PTM5)
Comparator
To LCD driver
Underflow
Underflow
interrupt
Compare match
interrupt
Compare match
Interrupt circuit
Control circuit
8-bit compare data register (CDR5)
Timer 5 control registers
INCL6
Timer 6
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR6)
Input port (K07)
EXCL3
8-bit down counter (PTM6)
Comparator
Underflow
Underflow
interrupt
Compare match
interrupt
Compare match
Interrupt circuit
Control circuit
8-bit compare data register (CDR6)
Timer 6 control registers
Underflow signal
INCL7
Timer 7
fOSC3/fOSC1
Prescaler/clock
control circuit
Clock selection
circuit
8-bit reload data register (RDR7)
Input port (K07)
EXCL3
8-bit down counter (PTM7)
Comparator
Underflow
Underflow
interrupt
Compare match
interrupt
Compare match
Interrupt circuit
Control circuit
8-bit compare data register (CDR7)
Timer 7 control registers
Fig. 5.10.1.2 Configuration of 16-bit programmable timer (Timers 4–7)
In the 8-bit mode, Timers 0 and 1 can be controlled
individually.
5.10.2 Operation mode
Timers 0 and 1, Timers 2 and 3, Timers 4 and 5, or
Timers 6 and 7 can be used as two channels of 8-bit
timers or one channel of 16-bit timer. Two kinds of
operation modes are provided corresponding to
this configuration, and it can be selected by the 8/
16-bit mode selection registers MODE16_A (for
Timer 0–1) through MODE16_D (for Timer 6–7).
When "0" is set to the MODE16_A register, Timers 0
and 1 enter the 8-bit mode (8-bit × 2 channels) and
when "1" is set, they enter the 16-bit mode (16-bit ×
1 channel).
In the 16-bit mode, the underflow signal of Timer 0
is used as the input clock of Timer 1 so that the
down counters operate as a 16-bit counter.
The timer in the 16-bit mode is controlled with the
control registers for Timer 0 except for the clock
output.
MODE16_B through MODE16_D have the same
function.
Figure 5.10.2.1 shows the timer configuration
depending on the operation mode and Table
5.10.2.1 shows the configuration of the control
registers.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
[8-bit mode]
8-bit data
[16-bit mode]
Low-order 8-bit data
Timer 0
input clock
Timer 0
input clock
Interrupt request
TOUT output
Timer 0
Timer 0
Timer 0
underflow
signal
Timer 1
input clock
Interrupt request
TOUT output
Interrupt request
TOUT output
Timer 1
Timer 1
8-bit data
High-order 8-bit data
Fig. 5.10.2.1 Counter configuration in 8- and 16-bit mode (example of Timers 0 and 1)
Table 5.10.2.1(a) Control registers in 8-bit mode (example of Timers 0 and 1)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF30 D7 MODE16_A PTM0–1 8/16-bit mode selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_A External clock 0 noise rejecter selection
Enable
–
Disable
D5 –
D4 –
–
–
"0" when being read
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT0 PTM0 clock output control
D2 PTRUN0 PTM0 Run/Stop control
D1 PSET0 PTM0 preset
On
R/W
R/W
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL0 PTM0 input clock selection
External clock Internal clock
R/W
00FF31 D7 –
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
–
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT1 PTM1 clock output control
D2 PTRUN1 PTM1 Run/Stop control
D1 PSET1 PTM1 preset
On
Run
Preset
R/W
R/W
Stop
No operation
W
"0" when being read
D0 CKSEL1 PTM1 input clock selection
External clock Internal clock
R/W
Table 5.10.2.1(b) Control registers in 16-bit mode (example of Timers 0 and 1)
Address Bit Name
Function
1
0
SR R/W
Comment
00FF30 D7 MODE16_A PTM0–1 8/16-bit mode selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_A External clock 0 noise rejecter selection
Enable
–
Disable
D5 –
D4 –
–
–
0
"0" when being read
R/W register
1
R/W Reserved register
D3 PTOUT0 Invalid (fixed at "0")
D2 PTRUN0 PTM0 Run/Stop control
D1 PSET0 PTM0 preset
Invalid
Run
Preset
Fixed at "0"
Stop
R/W
R/W
No operation
W
"0" when being read
D0 CKSEL0 PTM0 input clock selection
External clock Internal clock
R/W
00FF31 D7 –
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
–
R/W register
1
0
R/W Reserved register
D3 PTOUT1 PTM1 clock output control
D2 PTRUN1 Invalid (fixed at "0")
D1 PSET1 Invalid (fixed at "0")
D0 CKSEL1 Invalid (fixed at "0")
On
Off
R/W
R/W
Invalid
Invalid
Invalid
Fixed at "0"
Fixed at "0"
Fixed at "0"
W
"0" when being read
R/W
Note: The register names contain a timer number (0–7) to identify the timer to which the register belongs.
The following explanation uses "x" instead of the timer number except when it is required. For
example, PTRUNx represents PTRUN0 through PTRUN7. Furthermore, a pair of timers are
described as Timer(L) and Timer(H) in explanations for 16-bit mode.
Timer(L) = Timer 0, Timer 2, Timer 4 or Timer 6
Timer(H) = Timer 1, Timer 3, Timer 5 or Timer 7
This is used for register names.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.3.2 Division ratio and control registers
5.10.3 Setting of input clock
Register
Dividing ratio
(OSC1)
The clock to be input to the counter can be selected
from either the internal clock or external clock by
the input clock selection register (CKSEL) pro-
vided for each timer. The internal clock is an
output of the prescaler. The external clock is used
for the event counter function. A signal from the
input port is used as the count clock.
PSTx2 PSTx1 PSTx0 (OSC3)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3/4096 fOSC1/128
fOSC3/1024 fOSC1/64
fOSC3/256 fOSC1/32
fOSC3/64
fOSC3/32
fOSC3/8
fOSC3/2
fOSC3/1
fOSC1/16
fOSC1/8
fOSC1/4
fOSC1/2
fOSC1/1
Table 5.10.3.1 shows the input clock selection
register and input clock of each timer.
Table 5.10.3.1 Input clock selection
The set clock is output to Timer x by writing "1" to
the clock control register PRPRTx.
Timer
Register setting
Input clock
Timer 0
CKSEL0 = "0" INCL0 (Prescaler)
CKSEL0 = "1" EXCL0 (K04 input)
CKSEL1 = "0" INCL1 (Prescaler)
CKSEL1 = "1" EXCL0 (K04 input)
CKSEL2 = "0" INCL2 (Prescaler)
CKSEL2 = "1" EXCL1 (K05 input)
CKSEL3 = "0" INCL3 (Prescaler)
CKSEL3 = "1" EXCL1 (K05 input)
CKSEL4 = "0" INCL4 (Prescaler)
CKSEL4 = "1" EXCL2 (K06 input)
CKSEL5 = "0" INCL5 (Prescaler)
CKSEL5 = "1" EXCL2 (K06 input)
CKSEL6 = "0" INCL6 (Prescaler)
CKSEL6 = "1" EXCL3 (K07 input)
CKSEL7 = "0" INCL7 (Prescaler)
CKSEL7 = "1" EXCL3 (K07 input)
When the 16-bit mode is selected, the program-
mable timer operates with the clock input to
Timer(L), and Timer(H) inputs the Timer(L)
underflow signal as the clock. Therefore, the
setting of Timer(H) input clock is invalid.
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
5.10.4 Operation and control of timer
Reload data register and setting
of initial value
The reload data register (RDRx) is used to set an
initial value of the down counter.
In the 8-bit mode, RDRx is used as an 8-bit register
separated for each timer.
In the 16-bit mode, the RDR(L) register is handled
as low-order 8 bits of reload data, and the RDR(H)
register is as high-order 8 bits.
When the external clock is selected, a signal from
the input port is input to the programmable timer.
An noise rejecter is incorporated in the external
clock input circuit and it can be enabled/ disabled
using the external clock noise rejecter select
The reload data register can be read and written,
and all the registers are set to FFH at initial reset.
registers PTNREN_A through PTNREN_D corre-
sponding to the EXCL0 through EXCL3 inputs.
Writing "1" to PTNREN_A (–D) enables the noise
rejecter for the external clock EXCL0 (–3). The
noise rejecter regards pulses less than a 16/ fOSC1
seconds in width as noise and rejects them (an
external clock must have a pulse width at least
double the rejected width). When PTNREN_A (–D)
is "0", the external clock bypasses the noise rejecter.
Data written in this register is loaded into the
down counter, and a down counting starts from
the value.
The down counter is preset, in the following two
cases:
1) When software presets
The software preset can be done using the
preset control bits PSETx corresponding to
Timer x. When the preset control bit is set to
"1", the content of the reload data register is
loaded into the down counter at that point.
In the 16-bit mode, a 16-bit reload data is
loaded all at one time by setting PSET(L). In
this case, writing to PSET(H) is invalid.
When the internal clock is used, select a source
clock and a division ratio of the prescaler to set the
clock frequency for each timer.
The source clock is specified using the source clock
selection register PRTFx provided for each timer.
When "1" is written to PRTFx, the OSC1 clock is
selected as the source clock for Timer x. When "0"
is written, the OSC3 clock is selected. The OSC3
oscillation circuit must be on before the OSC3 can
be used. See "5.4 Oscillation Circuits" for the
controlling of the OSC3 oscillation circuit.
2) When down counter has underflowed during a count
Since the down counter presets the reload data
by the underflow, the underflow period is
decided according to the value set in the reload
data register. This underflow generates an
interrupt, and controls the clock (TOUTx
signal) output.
The prescaler provides the division ratio selection
register PSTx0–PSTx2 for each timer. Note that the
division ratio varies depending on the selected
source clock.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
When "0" is written to PTRUNx register, clock
Compare data register
input is prohibited, and the count stops.
This RUN/ STOP control does not affect data in the
counter. The data in the counter is maintained
during count deactivation, so it is possible to
resume counting from the data.
The programmable timer has a built-in data
comparator so that count data can be compared
with an optional value. The compare data register
(CDRx) is used to set the value to be compared.
In the 8-bit mode, CDRx is used as an 8-bit register
separated for each timer.
In the 16-bit mode, the CDR(L) register is handled
as low-order 8 bits of compare data, and the
CDR(H) register is as high-order 8 bits.
In the 8-bit mode, the timers can be controlled
individually by the PTRUNx register.
In the 16-bit mode, the PTRUN(L) register controls
a pair of timers as a 16-bit timer. In this case,
control of the PTRUN(H) register is invalid.
The compare data register can be read and written,
and all the registers are set to 00H at initial reset.
The buffers PTMx is attached to the counter, and
reading is possible in optional timing.
The programmable timer compares count data
with the compare data register (CDRx), and
generates a compare match signal when they
become the same value. This compare match signal
generates an interrupt, and controls the clock
(TOUTx signal) output.
When the counter agrees with the data set in the
compare data register during down counting, the
timer generates a compare match interrupt.
And, when the counter underflows, an underflow
interrupt is generated, and the initial value set in
the reload data register is loaded to the counter.
The interrupt generated does not stop the down
counting.
Timer operation
Timer is equipped with PTRUNx register which
controls the RUN/ STOP of the timer. Timer x
starts down counting by writing "1" to the
PTRUNx register. However, it is necessary to
control the input clock and to preset the reload
data before starting a count.
After an underflow interrupt is generated, the
counter continues counting from the initial value
reloaded.
PTRUNx
PSETx
RDRx
A6H
58H
A6H
58H
F3H
58H
CDRx
Input clock
PTMx7
PTMx6
PTMx5
PTMx4
PTMx3
PTMx2
PTMx1
PTMx0
∗1
Reload
Preset
Compare match
interrupt generation
Underflow interrupt
generation
Fig. 5.10.4.1 Basic operation timing of counter (an example of 8-bit mode)
Note: The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as ∗1
in the figure).
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period ∗1. Be especially careful when using the OSC1
(low-speed clock) as the clock source of the programmable timer and the CPU is operating with the
OSC3 (high-speed clock).
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In the 16-bit mode, the interrupt factor flags of
Timer(H) are set to "1" by the compare match and
underflow in 16 bits.
5.10.5 Interrupt function
The 16-bit programmable timer can generate an
interrupt with the compare match signal and
underflow signal of each timer.
Figure 5.10.5.1 shows the configuration of the 16-
bit programmable timer interrupt circuit.
Refer to Section 5.14, "Interrupt and Standby
Status", for details of the interrupt control registers
and operations subsequent to interrupt generation.
The exception processing vector addresses for the 16-
bit programmable timer interrupt are set as follows:
The compare match signal and underflow signal of
each timer set the corresponding interrupt factor
flag to "1". At that point, the interrupt is generated.
The interrupt can also be prohibited by setting the
interrupt enable register to correspond with the
interrupt factor flag.
Furthermore, the priority level of the interrupt for
the CPU can be set to an optional level (0–3) using
the interrupt priority register.
Timer 0 underflow interrupt:
Timer 0 compare match interrupt: 000018H
Timer 1 underflow interrupt: 00001AH
Timer 1 compare match interrupt: 00001CH
Timer 2 underflow interrupt: 00001EH
Timer 2 compare match interrupt: 000020H
Timer 3 underflow interrupt: 000022H
Timer 3 compare match interrupt: 000024H
Timer 4 underflow interrupt: 00003CH
Timer 4 compare match interrupt: 00003EH
Timer 5 underflow interrupt: 000040H
Timer 5 compare match interrupt: 000042H
Timer 6 underflow interrupt: 000044H
Timer 6 compare match interrupt: 000046H
Timer 7 underflow interrupt: 000048H
Timer 7 compare match interrupt: 00004AH
000016H
Table 5.10.5.1 shows the interrupt factor flags,
interrupt enable registers and interrupt priority
registers corresponding to the interrupt factors.
In the 8-bit mode, the compare match interrupt
factor flag and underflow interrupt factor flag are
individually set to "1" by the timers.
Table 5.10.5.1 Interrupt control registers
Interrupt factor flag
Interrupt enable register Interrupt priority register
Interrupt factor
Name Address·Dx Name Address·Dx Name Address·Dx
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
Counter underflow
Compare match
FTU0
FTC0
FTU1
FTC1
FTU2
FTC2
FTU3
FTC3
FTU4
FTC4
FTU5
FTC5
FTU6
FTC6
FTU7
FTC7
00FF29H·D0 ETU0
00FF29H·D1 ETC0
00FF29H·D2 ETU1
00FF29H·D3 ETC1
00FF29H·D4 ETU2
00FF29H·D5 ETC2
00FF29H·D6 ETU3
00FF29H·D7 ETC3
00FF2EH·D0 ETU4
00FF2EH·D1 ETC4
00FF2EH·D2 ETU5
00FF2EH·D3 ETC5
00FF2EH·D4 ETU6
00FF2EH·D5 ETC6
00FF2EH·D6 ETU7
00FF2EH·D7 ETC7
00FF25H·D0 PPT0
00FF25H·D1 PPT1
00FF25H·D2
00FF21H·D2
00FF21H·D3
00FF25H·D3
00FF25H·D4 PPT2
00FF25H·D5 PPT3
00FF25H·D6
00FF21H·D4
00FF21H·D5
00FF25H·D7
00FF2CH·D0 PPT4
00FF2CH·D1 PPT5
00FF2CH·D2
00FF2AH·D0
00FF2AH·D1
00FF2CH·D3
00FF2CH·D4 PPT6
00FF2CH·D5 PPT7
00FF2CH·D6
00FF2AH·D2
00FF2AH·D3
00FF2CH·D7
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Interrupt priority register
PPT0, PPT1
Address
Underflow
Interrupt factor flag
FTU0
Address
Interrupt enable
register ETU0
Address
Interrupt priority
level judgment
circuit
Timer 0
interrupt request
Compare match
Interrupt factor flag
FTC0
Timer 1
interrupt request
Address
Interrupt enable
register ETC0
Address
Timer 0
Timer 1
Interrupt priority register
PPT2, PPT3
Address
Underflow
Interrupt factor flag
FTU2
Address
Interrupt enable
register ETU2
Address
Interrupt priority
level judgment
circuit
Timer 2
interrupt request
Compare match
Interrupt factor flag
FTC2
Timer 3
interrupt request
Address
Interrupt enable
register ETC2
Address
Timer 2
Timer 3
Interrupt priority register
PPT4, PPT5
Address
Underflow
Interrupt factor flag
FTU4
Address
Interrupt enable
register ETU4
Address
Interrupt priority
level judgment
circuit
Timer 4
interrupt request
Compare match
Interrupt factor flag
FTC4
Timer 5
interrupt request
Address
Interrupt enable
register ETC4
Address
Timer 4
Timer 5
Interrupt priority register
PPT6, PPT7
Address
Underflow
Interrupt factor flag
FTU6
Address
Interrupt enable
register ETU6
Address
Interrupt priority
level judgment
circuit
Timer 6
interrupt request
Compare match
Interrupt factor flag
FTC6
Timer 7
interrupt request
Address
Interrupt enable
register ETC6
Address
Timer 6
Timer 7
Fig. 5.10.5.1 Configuration of 16-bit programmable timer interrupt circuit
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
However, it needs a condition setting: RDR > CDR,
CDR ≠ 0. In the case of RDR ≤ CDR, TOUT signal
is fixed at "1".
5.10.6 Setting of TOUT output
The 16-bit programmable timer can generate TOUT
signals with the underflow and compare match
signals of each timer. The TOUT signal generated in
the 16-bit programmable timer can be output from
the I/ O port terminal shown in Table 5.10.6.1 so
that a clock is supplied for external devices or it can
be used as a PWM waveform output.
The TOUT output can be controlled ON and OFF
using the clock output control register PTOUTx of
_________
each timer and the TOUT output can be controlled
using the inverted clock output control register
RPTOUTx of Timer 2 or Timer 3.
When PTOUTx (RPTOUTx) is set to "1", the TOUTx
___________
Table 5.10.6.1 TOUT output terminal
(TOUTx) signal is output from the corresponding
port terminal, when "0" is set, the port is set for DC
output. When PTOUTx (RPTOUTx) is "1", settings
of the I/ O control register IOC14/ IOC15/ IOC17
and data register P14D/ P15D/ P17D become
invalid.
Timer
Timer 0
Timer 1
Timer 2
Output clock name Output terminal
TOUT0
TOUT1
TOUT2
TOUT2
TOUT3
TOUT3
P14
P14
P15
P17
P15
P17
Timer 3
Note: If PTOUT0 and PTOUT1 are set to "1" at the
same time, PTOUT1 is effective. Similarly, if
PTOUT2 (RPTOUT2) and PTOUT3
(RPTOUT3) are set to "1", PTOUT3
(RPTOUT3) is effective.
The TOUT signal rises at the falling edge of the
underflow signal and falls at the falling edge of the
_________
compare match signal. TOUT is the inverted TOUT
signal. Therefore, it is possible to change the
frequency and duty ratio of the TOUT signal by
setting the reload data register (RDR) and compare
data register (CDR).
In the 16-bit mode, the output is controlled by the
control register PTOUT(H) for Timer(H). The clock
is output from Timer(H).
___________
Since the TOUTx (TOUTx) signal is generated
asynchronously from the register PTOUTx
(RPTOUTx), when the signal is turned ON or OFF
by the register settings, a hazard of a 1/ 2 cycle or
less is generated.
Figure 5.10.6.1 shows the output waveform of
TOUT signal.
Input clock
RDRx register
CDRx register
7
6
Down counter
Compare match signal
Underflow signal
0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
TOUTx signal
CDR register value
RDR register value + 1
PTOUTx/RPTOUTx
Output from TOUTx (P14/P15) terminal
Output from TOUTx (P17) terminal
Fig. 5.10.6.1 Output waveform of TOUT signal
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
5.10.7 Transfer rate setting of serial interface
The underflow signal of Timer 1 can be used to
clock the serial interface.
Since the underflow signal of Timer 1 is divided by
32 in the serial interface, the value set in the
register RDR1X which corresponds to the transfer
rate is shown in the following expression:
The transfer rate setting in this case is made in the
registers PST1X and RDR1X (since only the
underflow signal is used as the serial interface clock
source, the CDR1X register value does not affect the
transfer rates. It can be set to any value).
fdiv
RDR1X = ————— - 1
32 × bps
fdiv: Input clock frequency (setteing of PST1X)
bps: Transfer rate
Table 5.10.7.1 Example of transfer rate setting
OSC3 oscillation frequency / Programmable timer settings
Transfer rate
(bps)
fOSC3 = 2.4756 MHz fOSC3 = 3.0720 MHz fOSC3 = 3.6864 MHz
PST1X
00H
00H
00H
00H
00H
00H
02H
02H
RDR1X
03H
PST1X
00H
00H
00H
00H
00H
00H
03H
03H
RDR1X
04H
PST1X
00H
00H
00H
00H
00H
00H
01H
02H
RDR1X
05H
19,200
9,600
4,800
2,400
1,200
600
07H
09H
0BH
17H
0FH
1FH
3FH
7FH
1FH
3FH
13H
27H
2FH
4FH
9FH
09H
5FH
BFH
BFH
5FH
300
150
13H
∗ Since the underflow signal only is used as the clock source, the CDR1X
register value does not affect the transfer rates.
5.10.8 Setting frame frequency for LCD driver
The underflow signal of Timer 5 can be used as the
source clock to generate the frame signal for the
LCD driver.
The frame frequency is set up using the registers
PST5X and RDR5X (since only the underflow signal
is used as the source clock, the CDR5X register
value does not affect the frame signal. It can be set
to any value).
The Timer 5 underflow signal is divided by 128 (for
1/ 16 or 1/ 3 duty) or 256 (for 1/ 8 duty) in the LCD
driver, so set a value represented by the following
expressions to the register RDR5X.
(for 1/ 16 or 1/ 32 duty)
fdiv
RDR5X = ————— - 1
128 × fFRM
(for 1/ 8 duty)
fdiv
RDR5X = ————— - 1
256 × fFRM
fdiv: Input clock frequency (setteing of PST5X)
fFRM: Frame frequency (Hz)
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5.10.9 Control of programmable timer
Table 5.10.9.1 shows the programmable timer control bits.
Table 5.10.9.1(a) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF14 D7 PRPRT1 Programmable timer 1 clock control
On
Off
0
0
R/W
R/W
D6 PST12 Programmable timer 1 division ratio
PST12 PST11 PST10 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST11
D4 PST10
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
Programmable timer 0 clock control
Programmable timer 0 division ratio
D3 PRPRT0
D2 PST02
On
On
On
On
On
Off
Off
Off
Off
Off
0
0
R/W
R/W
PST02 PST01 PST00 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST01
D0 PST00
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
00FF15 D7 PRPRT3 Programmable timer 3 clock control
0
0
R/W
R/W
D6 PST32 Programmable timer 3 division ratio
PST32 PST31 PST30 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST31
D4 PST30
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D3 PRPRT2 Programmable timer 2 clock control
0
0
R/W
R/W
D2 PST22 Programmable timer 2 division ratio
PST22 PST21 PST20 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST21
D0 PST20
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
00FF18 D7 PRPRT5 Programmable timer 5 clock control
0
0
R/W
R/W
D6 PST52 Programmable timer 5 division ratio
PST52 PST51 PST50 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST51
D4 PST50
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D3 PRPRT4 Programmable timer 4 clock control
0
0
R/W
R/W
D2 PST42 Programmable timer 4 division ratio
PST42 PST41 PST40 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST41
D0 PST40
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(b) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF19 D7 PRPRT7 Programmable timer 7 clock control
On
Off
0
0
R/W
R/W
D6 PST72 Programmable timer 7 division ratio
PST72 PST71 PST70 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D5 PST71
D4 PST70
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
D3 PRPRT6 Programmable timer 6 clock control
On
Off
0
0
R/W
R/W
D2 PST62 Programmable timer 6 division ratio
PST62 PST61 PST60 (OSC3)
(OSC1)
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fOSC3 / 4096 fOSC1 / 128
fOSC3 / 1024 fOSC1 / 64
fOSC3 / 256 fOSC1 / 32
D1 PST61
D0 PST60
0
0
R/W
R/W
fOSC3 / 64
fOSC3 / 32
fOSC3 / 8
fOSC3 / 2
fOSC3 / 1
fOSC1 / 16
fOSC1 / 8
fOSC1 / 4
fOSC1 / 2
fOSC1 / 1
00FF17 D7 –
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
–
–
–
–
0
0
0
0
–
–
0
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
R/W register
1
0
R/W Reserved register
D3 PRTF3 Programmable timer 3 source clock selection
D2 PRTF2 Programmable timer 2 source clock selection
D1 PRTF1 Programmable timer 1 source clock selection
D0 PRTF0 Programmable timer 0 source clock selection
fOSC1
fOSC1
fOSC1
fOSC1
–
fOSC3
fOSC3
fOSC3
fOSC3
–
R/W
R/W
R/W
R/W
00FF1B D7 –
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
–
–
D3 PRTF7 Programmable timer 7 source clock selection
D2 PRTF6 Programmable timer 6 source clock selection
D1 PRTF5 Programmable timer 5 source clock selection
D0 PRTF4 Programmable timer 4 source clock selection
fOSC1
fOSC1
fOSC1
fOSC1
–
fOSC3
fOSC3
fOSC3
fOSC3
–
R/W
R/W
R/W
R/W
00FF21 D7 –
–
Constantly "0" when
being read
R/W
D6 –
–
–
–
PPT3 PPT2 Priority
PPT1 PPT0
D5 PPT3
D4 PPT2
D3 PPT1
D2 PPT0
D1 –
Programmable timer 3–2 interrupt
level
priority register
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Programmable timer 1–0 interrupt
0
R/W
priority register
–
Level 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
Constantly "0" when
being read
D0 –
–
00FF2A D7 –
–
Constantly "0" when
being read
D6 –
–
D5 –
–
D4 –
–
PPT7 PPT6 Priority
PPT5 PPT4
D3 PPT7
D2 PPT6
D1 PPT5
D0 PPT4
Programmable timer 7–6 interrupt
priority register
R/W
R/W
level
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
Programmable timer 5–4 interrupt
priority register
0
96
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(c) Programmable timer control bits
Address Bit Name
00FF25 D7 ETC3
D6 ETU3
Function
1
0
SR R/W
Comment
PTM3 compare match interrupt enable
PTM3 underflow interrupt enable
D5 ETC2
PTM2 compare match interrupt enable
PTM2 underflow interrupt enable
D4 ETU2
Interrupt
enable
Interrupt
disable
0
0
0
0
R/W
R/W
R/W
R/W
D3 ETC1
PTM1 compare match interrupt enable
PTM1 underflow interrupt enable
D2 ETU1
D1 ETC0
PTM0 compare match interrupt enable
PTM0 underflow interrupt enable
D0 ETU0
00FF29 D7 FTC3
D6 FTU3
PTM3 compare match interrupt factor flag
PTM3 underflow interrupt factor flag
PTM2 compare match interrupt factor flag
PTM2 underflow interrupt factor flag
PTM1 compare match interrupt factor flag
PTM1 underflow interrupt factor flag
PTM0 compare match interrupt factor flag
PTM0 underflow interrupt factor flag
PTM7 compare match interrupt enable
PTM7 underflow interrupt enable
(R)
(R)
Interrupt
factor is
generated
No interrupt
factor is
D5 FTC2
D4 FTU2
generated
D3 FTC1
D2 FTU1
(W)
(W)
D1 FTC0
Reset
No operation
D0 FTU0
00FF2C D7 ETC7
D6 ETU7
D5 ETC6
PTM6 compare match interrupt enable
PTM6 underflow interrupt enable
D4 ETU6
Interrupt
enable
Interrupt
disable
D3 ETC5
PTM5 compare match interrupt enable
PTM5 underflow interrupt enable
D2 ETU5
D1 ETC4
PTM4 compare match interrupt enable
PTM4 underflow interrupt enable
D0 ETU4
00FF2E D7 FTC7
D6 FTU7
PTM7 compare match interrupt factor flag
PTM7 underflow interrupt factor flag
PTM6 compare match interrupt factor flag
PTM6 underflow interrupt factor flag
PTM5 compare match interrupt factor flag
PTM5 underflow interrupt factor flag
PTM4 compare match interrupt factor flag
PTM4 underflow interrupt factor flag
(R)
(R)
Interrupt
factor is
generated
No interrupt
factor is
D5 FTC6
D4 FTU6
generated
D3 FTC5
D2 FTU5
(W)
(W)
D1 FTC4
Reset
No operation
D0 FTU4
00FF30 D7 MODE16_A PTM0–1 8/16-bit mode selection
16-bit x 1
Enable
–
8-bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_A External clock 0 noise rejecter selection
Disable
D5 –
D4 –
–
–
"0" when being read
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT0 PTM0 clock output control
D2 PTRUN0 PTM0 Run/Stop control
D1 PSET0 PTM0 preset
On
R/W
R/W
Run
Stop
Preset
No operation
W
"0" when being read
D0 CKSEL0 PTM0 input clock selection
External clock Internal clock
R/W
00FF31 D7 –
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
–
–
–
–
–
R/W register
1
0
Off
R/W Reserved register
D3 PTOUT1 PTM1 clock output control
D2 PTRUN1 PTM1 Run/Stop control
D1 PSET1 PTM1 preset
On
Run
Preset
R/W
R/W
Stop
No operation
W
"0" when being read
D0 CKSEL1 PTM1 input clock selection
External clock Internal clock
R/W
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(d) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF32 D7 RDR07 PTM0 reload data D7 (MSB)
D6 RDR06 PTM0 reload data D6
D5 RDR05 PTM0 reload data D5
D4 RDR04 PTM0 reload data D4
D3 RDR03 PTM0 reload data D3
D2 RDR02 PTM0 reload data D2
D1 RDR01 PTM0 reload data D1
D0 RDR00 PTM0 reload data D0 (LSB)
00FF33 D7 RDR17 PTM1 reload data D7 (MSB)
D6 RDR16 PTM1 reload data D6
D5 RDR15 PTM1 reload data D5
D4 RDR14 PTM1 reload data D4
D3 RDR13 PTM1 reload data D3
D2 RDR12 PTM1 reload data D2
D1 RDR11 PTM1 reload data D1
D0 RDR10 PTM1 reload data D0 (LSB)
00FF34 D7 CDR07 PTM0 compare data D7 (MSB)
D6 CDR06 PTM0 compare data D6
D5 CDR05 PTM0 compare data D5
D4 CDR04 PTM0 compare data D4
D3 CDR03 PTM0 compare data D3
D2 CDR02 PTM0 compare data D2
D1 CDR01 PTM0 compare data D1
D0 CDR00 PTM0 compare data D0 (LSB)
00FF35 D7 CDR17 PTM1 compare data D7 (MSB)
D6 CDR16 PTM1 compare data D6
D5 CDR15 PTM1 compare data D5
D4 CDR14 PTM1 compare data D4
D3 CDR13 PTM1 compare data D3
D2 CDR12 PTM1 compare data D2
D1 CDR11 PTM1 compare data D1
D0 CDR10 PTM1 compare data D0 (LSB)
00FF36 D7 PTM07 PTM0 data D7 (MSB)
D6 PTM06 PTM0 data D6
High
Low
1
1
0
0
1
1
R/W
R/W
R/W
R/W
R
High
High
High
High
High
Low
Low
Low
Low
Low
D5 PTM05 PTM0 data D5
D4 PTM04 PTM0 data D4
D3 PTM03 PTM0 data D3
D2 PTM02 PTM0 data D2
D1 PTM01 PTM0 data D1
D0 PTM00 PTM0 data D0 (LSB)
00FF37 D7 PTM17 PTM1 data D7 (MSB)
D6 PTM16 PTM1 data D6
D5 PTM15 PTM1 data D5
D4 PTM14 PTM1 data D4
R
D3 PTM13 PTM1 data D3
D2 PTM12 PTM1 data D2
D1 PTM11 PTM1 data D1
D0 PTM10 PTM1 data D0 (LSB)
98
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(e) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF38 D7 MODE16_B PTM2–3 8/16-bit mode selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
D6 PTNREN_B External clock 1 noise rejecter selection
Enable
–
Disable
D5 –
–
–
Off
"0" when being read
D4 RPTOUT2 PTM2 inverted clock output control
D3 PTOUT2 PTM2 clock output control
D2 PTRUN2 PTM2 Run/Stop control
D1 PSET2 PTM2 preset
On
R/W
R/W
R/W
W
On
Off
Run
Preset
Stop
No operation
"0" when being read
D0 CKSEL2 PTM2 input clock selection
External clock Internal clock
R/W
00FF39 D7 –
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
–
–
–
Off
D4 RPTOUT3 PTM3 inverted clock output control
D3 PTOUT3 PTM3 clock output control
D2 PTRUN3 PTM3 Run/Stop control
D1 PSET3 PTM3 preset
On
On
Run
Preset
R/W
R/W
R/W
W
Off
Stop
No operation
"0" when being read
D0 CKSEL3 PTM3 input clock selection
00FF3A D7 RDR27 PTM2 reload data D7 (MSB)
D6 RDR26 PTM2 reload data D6
External clock Internal clock
R/W
D5 RDR25 PTM2 reload data D5
D4 RDR24 PTM2 reload data D4
High
High
High
High
Low
Low
Low
Low
1
1
0
0
R/W
R/W
R/W
R/W
D3 RDR23 PTM2 reload data D3
D2 RDR22 PTM2 reload data D2
D1 RDR21 PTM2 reload data D1
D0 RDR20 PTM2 reload data D0 (LSB)
00FF3B D7 RDR37 PTM3 reload data D7 (MSB)
D6 RDR36 PTM3 reload data D6
D5 RDR35 PTM3 reload data D5
D4 RDR34 PTM3 reload data D4
D3 RDR33 PTM3 reload data D3
D2 RDR32 PTM3 reload data D2
D1 RDR31 PTM3 reload data D1
D0 RDR30 PTM3 reload data D0 (LSB)
00FF3C D7 CDR27 PTM2 compare data D7 (MSB)
D6 CDR26 PTM2 compare data D6
D5 CDR25 PTM2 compare data D5
D4 CDR24 PTM2 compare data D4
D3 CDR23 PTM2 compare data D3
D2 CDR22 PTM2 compare data D2
D1 CDR21 PTM2 compare data D1
D0 CDR20 PTM2 compare data D0 (LSB)
00FF3D D7 CDR37 PTM3 compare data D7 (MSB)
D6 CDR36 PTM3 compare data D6
D5 CDR35 PTM3 compare data D5
D4 CDR34 PTM3 compare data D4
D3 CDR33 PTM3 compare data D3
D2 CDR32 PTM3 compare data D2
D1 CDR31 PTM3 compare data D1
D0 CDR30 PTM3 compare data D0 (LSB)
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(f) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FF3E D7 PTM27 PTM2 data D7 (MSB)
D6 PTM26 PTM2 data D6
D5 PTM25 PTM2 data D5
D4 PTM24 PTM2 data D4
High
Low
1
R
D3 PTM23 PTM2 data D3
D2 PTM22 PTM2 data D2
D1 PTM21 PTM2 data D1
D0 PTM20 PTM2 data D0 (LSB)
00FF3F D7 PTM37 PTM3 data D7 (MSB)
D6 PTM36 PTM3 data D6
D5 PTM35 PTM3 data D5
D4 PTM34 PTM3 data D4
High
Low
1
R
D3 PTM33 PTM3 data D3
D2 PTM32 PTM3 data D2
D1 PTM31 PTM3 data D1
D0 PTM30 PTM3 data D0 (LSB)
00FFB0 D7 MODE16_C PTM4–5 8/16-bit mode selection
D6 PTNREN_C External clock 2 noise rejecter selection
16
-
bit x 1
8
-
bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
Enable
Disable
D5 –
D4 –
D3 –
–
–
1
–
"0" when being read
R/W register
R/W register
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN4 PTM4 Run/Stop control
D1 PSET4 PTM4 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL4 PTM4 input clock selection
External clock Internal clock
R/W
00FFB1 D7 –
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
–
–
–
–
R/W register
R/W register
1
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN5 PTM5 Run/Stop control
D1 PSET5 PTM5 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL5 PTM5 input clock selection
00FFB2 D7 RDR47 PTM4 reload data D7 (MSB)
D6 RDR46 PTM4 reload data D6
D5 RDR45 PTM4 reload data D5
D4 RDR44 PTM4 reload data D4
D3 RDR43 PTM4 reload data D3
D2 RDR42 PTM4 reload data D2
D1 RDR41 PTM4 reload data D1
D0 RDR40 PTM4 reload data D0 (LSB)
00FFB3 D7 RDR57 PTM5 reload data D7 (MSB)
D6 RDR56 PTM5 reload data D6
D5 RDR55 PTM5 reload data D5
D4 RDR54 PTM5 reload data D4
D3 RDR53 PTM5 reload data D3
D2 RDR52 PTM5 reload data D2
D1 RDR51 PTM5 reload data D1
D0 RDR50 PTM5 reload data D0 (LSB)
External clock Internal clock
R/W
High
Low
1
R/W
High
Low
1
R/W
100
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(g) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FFB4 D7 CDR47 PTM4 compare data D7 (MSB)
D6 CDR46 PTM4 compare data D6
D5 CDR45 PTM4 compare data D5
D4 CDR44 PTM4 compare data D4
D3 CDR43 PTM4 compare data D3
D2 CDR42 PTM4 compare data D2
D1 CDR41 PTM4 compare data D1
D0 CDR40 PTM4 compare data D0 (LSB)
00FFB5 D7 CDR57 PTM5 compare data D7 (MSB)
D6 CDR56 PTM5 compare data D6
D5 CDR55 PTM5 compare data D5
D4 CDR54 PTM5 compare data D4
D3 CDR53 PTM5 compare data D3
D2 CDR52 PTM5 compare data D2
D1 CDR51 PTM5 compare data D1
D0 CDR50 PTM5 compare data D0 (LSB)
00FFB6 D7 PTM47 PTM4 data D7 (MSB)
D6 PTM46 PTM4 data D6
High
Low
0
0
1
1
R/W
R/W
R
High
High
High
Low
Low
Low
D5 PTM45 PTM4 data D5
D4 PTM44 PTM4 data D4
D3 PTM43 PTM4 data D3
D2 PTM42 PTM4 data D2
D1 PTM41 PTM4 data D1
D0 PTM40 PTM4 data D0 (LSB)
00FFB7 D7 PTM57 PTM5 data D7 (MSB)
D6 PTM56 PTM5 data D6
D5 PTM55 PTM5 data D5
D4 PTM54 PTM5 data D4
R
D3 PTM53 PTM5 data D3
D2 PTM52 PTM5 data D2
D1 PTM51 PTM5 data D1
D0 PTM50 PTM5 data D0 (LSB)
00FFB8 D7 MODE16_D PTM6–7 8/16-bit mode selection
D6 PTNREN_D External clock 3 noise rejecter selection
16-bit x 1
8-bit x 2
0
0
–
0
0
0
0
0
–
–
–
0
0
0
0
0
R/W
R/W
Enable
Disable
D5 –
D4 –
D3 –
–
–
1
–
"0" when being read
R/W register
R/W register
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN6 PTM6 Run/Stop control
D1 PSET6 PTM6 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL6 PTM6 input clock selection
External clock Internal clock
R/W
00FFB9 D7 –
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
–
–
–
–
R/W register
R/W register
1
0
R/W Reserved register
1
0
R/W
R/W
D2 PTRUN7 PTM7 Run/Stop control
D1 PSET7 PTM7 preset
Run
Preset
Stop
No operation
W
"0" when being read
D0 CKSEL7 PTM7 input clock selection
External clock Internal clock
R/W
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Table 5.10.9.1(h) Programmable timer control bits
Address Bit Name
Function
1
0
SR R/W
Comment
00FFBA D7 RDR67 PTM6 reload data D7 (MSB)
D6 RDR66 PTM6 reload data D6
D5 RDR65 PTM6 reload data D5
D4 RDR64 PTM6 reload data D4
D3 RDR63 PTM6 reload data D3
D2 RDR62 PTM6 reload data D2
D1 RDR61 PTM6 reload data D1
D0 RDR60 PTM6 reload data D0 (LSB)
00FFBB D7 RDR77 PTM7 reload data D7 (MSB)
D6 RDR76 PTM7 reload data D6
D5 RDR75 PTM7 reload data D5
D4 RDR74 PTM7 reload data D4
D3 RDR73 PTM7 reload data D3
D2 RDR72 PTM7 reload data D2
D1 RDR71 PTM7 reload data D1
D0 RDR70 PTM7 reload data D0 (LSB)
00FFBC D7 CDR67 PTM6 compare data D7 (MSB)
D6 CDR66 PTM6 compare data D6
D5 CDR65 PTM6 compare data D5
D4 CDR64 PTM6 compare data D4
D3 CDR63 PTM6 compare data D3
D2 CDR62 PTM6 compare data D2
D1 CDR61 PTM6 compare data D1
D0 CDR60 PTM6 compare data D0 (LSB)
00FFBD D7 CDR77 PTM7 compare data D7 (MSB)
D6 CDR76 PTM7 compare data D6
D5 CDR75 PTM7 compare data D5
D4 CDR74 PTM7 compare data D4
D3 CDR73 PTM7 compare data D3
D2 CDR72 PTM7 compare data D2
D1 CDR71 PTM7 compare data D1
D0 CDR70 PTM7 compare data D0 (LSB)
00FFBE D7 PTM67 PTM6 data D7 (MSB)
D6 PTM66 PTM6 data D6
High
Low
1
1
0
0
1
1
R/W
R/W
R/W
R/W
R
High
High
High
High
High
Low
Low
Low
Low
Low
D5 PTM65 PTM6 data D5
D4 PTM64 PTM6 data D4
D3 PTM63 PTM6 data D3
D2 PTM62 PTM6 data D2
D1 PTM61 PTM6 data D1
D0 PTM60 PTM6 data D0 (LSB)
00FFBF D7 PTM77 PTM7 data D7 (MSB)
D6 PTM76 PTM7 data D6
D5 PTM75 PTM7 data D5
D4 PTM74 PTM7 data D4
R
D3 PTM73 PTM7 data D3
D2 PTM72 PTM7 data D2
D1 PTM71 PTM7 data D1
D0 PTM70 PTM7 data D0 (LSB)
102
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
When "0" is written to the CKSELx register, the
internal clock (prescaler output INCLx) is selected
as the input clock for Timer x.
When "1" is written, the external clock (EXCL0
(K04 input) for Timers 0 and 1, EXCL1 (K05 input)
for Timers 2 and 3, EXCL2 (K06 input) for Timers 4
and 5, EXCL3 (K07 input) for Timers 6 and 7) is
selected and the timer functions as an event
counter.
In the 16-bit mode, the setting of the CKSEL(H)
register is invalid.
MODE16_A: 00FF30H•D7
MODE16_B: 00FF38H•D7
MODE16_C: 00FFB0H•D7
MODE16_D: 00FFB8H•D7
Selects either the 8/ 16 bit mode.
When "1" is written: 16 bits × 1 channel
When "0" is written: 8 bits × 2 channels
Reading:
Valid
MODE16_A, MODE16_B, MODE16_C and
MODE16_D are the 8/ 16-bit mode selection
registers corresponding to Timers 0 and 1, Timers 2
and 3, Timers 4 and 5, and Timers 6 and 7,
respectively. Select whether Timer(L) and Timer(H)
are used as 2 channels independent 8-bit timers or
as 1 channel combined 16-bit timer.
When "0" is written to the MODE16_A (–D)
register, 8-bit × 2 channels is selected and when "1"
is written, 16-bit × 1 channel is selected.
At initial reset, this register is set to "0" (8-bit × 2
channels).
At initial reset, this register is set to "0" (internal
clock).
PRTF0: 00FF17H•D0
PRTF1: 00FF17H•D1
PRTF2: 00FF17H•D2
PRTF3: 00FF17H•D3
PRTF4: 00FF1BH•D0
PRTF5: 00FF1BH•D1
PRTF6: 00FF1BH•D2
PRTF7: 00FF1BH•D3
PTNREN_A: 00FF30H•D6
PTNREN_B: 00FF38H•D6
PTNREN_C: 00FFB0H•D6
PTNREN_D: 00FFB8H•D6
Selects the source clock for each timer (when
internal clock is used).
When "1" is written: fOSC1
When "0" is written: fOSC3
Enables/ disables the noise rejecter in the external
clock input circuit.
Reading:
Valid
When "1" is written to the PRTFx register, the
OSC1 clock is selected as the source clock for
Timer x.
When "0" is written, the OSC3 clock is selected.
At initial reset, this register is set to "0" (fOSC3).
When "1" is written: Enabled
When "0" is written: Disabled
Reading:
Valid
Writing "1" to PTNREN_A (–D) enables the noise
rejecter for the external clock EXCL0 (–3). The noise
rejecter regards pulses less than a 16/ fOSC1 seconds
in width as noise and rejects them.
When PTNREN_A (–D) is "0", the external clock
bypasses the noise rejecter.
PST00–PST02: 00FF14H•D0–D2
PST10–PST12: 00FF14H•D4–D6
PST20–PST22: 00FF15H•D0–D2
PST30–PST32: 00FF15H•D4–D6
PST40–PST42: 00FF18H•D0–D2
PST50–PST52: 00FF18H•D4–D6
PST60–PST62: 00FF19H•D0–D2
PST70–PST72: 00FF19H•D4–D6
At initial reset, this register is set to "0" (disabled).
CKSEL0: 00FF30H•D0
CKSEL1: 00FF31H•D0
CKSEL2: 00FF38H•D0
CKSEL3: 00FF39H•D0
CKSEL4: 00FFB0H•D0
CKSEL5: 00FFB1H•D0
CKSEL6: 00FFB8H•D0
CKSEL7: 00FFB9H•D0
Selects the input clock for each timer (when internal
clock is used).
It can be selected from 8 types of division ratio
shown in Tables 5.10.9.1(a) and (b).
This register can also be read.
At initial reset, this register is set to "0".
Selects the input clock for each timer.
When "1" is written: External clock
When "0" is written: Internal clock
Reading:
Valid
The clock to be input to each timer is selected from
either the external clock (input signal of input
port) or the internal clock (prescaler output clock).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
PRPRT0: 00FF14H•D3
PRPRT1: 00FF14H•D7
PRPRT2: 00FF15H•D3
PRPRT3: 00FF15H•D7
PRPRT4: 00FF18H•D3
PRPRT5: 00FF18H•D7
PRPRT6: 00FF19H•D3
PRPRT7: 00FF19H•D7
PTM00–PTM07: 00FF36H
PTM10–PTM17: 00FF37H
PTM20–PTM27: 00FF3EH
PTM30–PTM37: 00FF3FH
PTM40–PTM47: 00FFB6H
PTM50–PTM57: 00FFB7H
PTM60–PTM67: 00FFBEH
PTM70–PTM77: 00FFBFH
Controls the clock supply of each timer (when
internal clock is used).
The counter data of each timer can be read.
Data can be read at any given time. However, in
the 16-bit mode, reading PTM(L) does not latch the
Timer(H) counter data in PTM(H). To avoid
generating a borrow from Timer(L) to Timer(H),
read the counter data after stopping the timer by
writing "0" to PTRUN(L).
When "1" is written: ON
When "0" is written: OFF
Reading:
Valid
By writing "1" to the PRPRTx register, the clock
that is selected with the PSTx register is output to
Timer x.
PTMx can only be read, so writing operation is
invalid.
When "0" is written, the clock is not output.
At initial reset, the this register is set to "0" (OFF).
At initial reset, PTMx is set to "FFH".
PSET0: 00FF30H•D1
PSET1: 00FF31H•D1
PSET2: 00FF38H•D1
PSET3: 00FF39H•D1
PSET4: 00FFB0H•D1
PSET5: 00FFB1H•D1
PSET6: 00FFB8H•D1
PSET7: 00FFB9H•D1
RDR00–RDR07: 00FF32H
RDR10–RDR17: 00FF33H
RDR20–RDR27: 00FF3AH
RDR30–RDR37: 00FF3BH
RDR40–RDR47: 00FFB2H
RDR50–RDR57: 00FFB3H
RDR60–RDR67: 00FFBAH
RDR70–RDR77: 00FFBBH
Presets the reload data to the counter.
Sets the initial value for the counter of each timer.
Each counter loads the reload data set in this
register and counts using it as the initial value.
The reload data set in this register is loaded into
the counter when "1" is written to PSETx, or when
a counter underflow occurs.
When "1" is written: Preset
When "0" is written: Invalid
Reading:
Always "0"
Writing "1" to PSETx presets the reload data in the
RDRx register to the counter of Timer x. When the
counter of Timer x is in RUN status, the counter
restarts immediately after presetting.
In the case of STOP status, the counter maintains
the preset data.
No operation results when "0" is written.
In the 16-bit mode, writing "1" to PSET(H) is
invalid because 16-bit data is preset by PSET(L)
only.
This register can also be read.
At initial reset, this register is set to "FFH".
CDR00–CDR07: 00FF34H
CDR10–CDR17: 00FF35H
CDR20–CDR27: 00FF3CH
CDR30–CDR37: 00FF3DH
CDR40–CDR47: 00FFB4H
CDR50–CDR57: 00FFB5H
CDR60–CDR67: 00FFBCH
CDR70–CDR77: 00FFBDH
PSETx is only for writing, and it is always "0"
during reading.
Sets the compare data for each timer.
The timer compares the data set in this register
with the corresponding counter data, and outputs
the compare match signals when they are the
same. The compare match signal controls the
interrupt and the TOUT output waveform.
This register can also be read.
At initial reset, this register is set to "00H".
104
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S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
PTRUN0: 00FF30H•D2
PTRUN1: 00FF31H•D2
PTRUN2: 00FF38H•D2
PTRUN3: 00FF39H•D2
PTRUN4: 00FFB0H•D2
PTRUN5: 00FFB1H•D2
PTRUN6: 00FFB8H•D2
PTRUN7: 00FFB9H•D2
RPTOUT2: 00FF38H•D4
RPTOUT3: 00FF39H•D4
_________
Controls the output of the TOUT signal.
_________
When "1" is written: TOUT signal output
When "0" is written: DC output
Reading:
Valid
The RPTOUTx is the output control register for the
___________
TOUTx signal (Timer x inverted output clock).
Controls the RUN/ STOP of the counter.
When RPT_O__U___T__2___or RPTOUT3 is set to "1", the
___________
TOUT2 or TOUT3 signal is output from the P17
port terminal. When "0" is set, P17 is set for DC
output.
When "1" is written: RUN
When "0" is written: STOP
Reading:
Valid
At this time, settings of the I/ O control register
IOC17 and data register P17D become invalid.
In the 16-bit mode, the timers are controlled with
the RPTOUT3 register, and the RPTOUT2 register is
fixed at "0".
The counter of Timer x starts down-counting by
writing "1" to the PTRUNx register and stops by
writing "0".
In STOP status, the counter data is maintained
until it is preset or the counter restarts. When
STOP status changes to RUN status, the counter
resumes counting from the data maintained.
In the 16-bit mode, the timers are controlled with
the PTRUN(L) register, and the PTRUN(H) register
is fixed at "0".
At initial reset, this register is set to "0" (DC
output).
Note: If RPTOUT2 and RPTOUT3 are set to "1" at
the same time, RPTOUT3 is effective.
PPT0, PPT1: 00FF21H•D2, D3
PPT2, PPT3: 00FF21H•D4, D5
PPT4, PPT5: 00FF2AH•D0, D1
PPT6, PPT7: 00FF2AH•D2, D3
At initial reset, this register is set to "0" (STOP).
PTOUT0: 00FF30H•D3
PTOUT1: 00FF31H•D3
PTOUT2: 00FF38H•D3
PTOUT3: 00FF39H•D3
Sets the priority level of the programmable timer
interrupt.
PPT0–PPT1, PPT2–PPT3, PPT4–PPT5, and PPT6–
PPT7 are the interrupt priority register
corresponding to Timers 0–1, Timers 2–3, Timers 4–
5, and Timers 6–7, respectively.
Table 5.10.9.2 shows the interrupt priority level
which can be set by this register.
Controls the output of the TOUT signal.
When "1" is written: TOUT signal output
When "0" is written: DC output
Reading:
Valid
The PTOUTx is the output control register for the
TOUTx signal (Timer x output clock). When
PTOUT0 or PTOUT1 is set to "1", the TOUT0 or
TOUT1 signal is output from the P14 port terminal.
When PTOUT2 or PTOUT3 is set to "1", the TOUT2
or TOUT3 signal is output from the P15 port
terminal. When "0" is set, P14/ P15 is set for DC
output.
Table 5.10.9.2 Interrupt priority level settings
PPT7
PPT5
PPT3
PPT1
1
PPT6
PPT4
PPT2
PPT0
1
Interrupt priority level
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
1
0
0
0
1
0
At this time, settings of the I/ O control register
IOC14/ IOC15 and data register P14D/ P15D
become invalid.
In the 16-bit mode, the timers are controlled with
the PTOUT(H) register, and the PTOUT(L) register
is fixed at "0".
At initial reset, this register is set to "0" (level 0).
At initial reset, this register is set to "0" (DC
output).
Note: If PTOUT0 and PTOUT1 are set to "1" at the
same time, PTOUT1 is effective. Similarly, if
PTOUT2 and PTOUT3 are set to "1",
PTOUT3 is effective. Furthermore, if the
programmable timer is set in 16-bit mode,
the TOUT0 and TOUT2 signals cannot be
output.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
ETU0: 00FF25H•D0
ETU1: 00FF25H•D2
ETU2: 00FF25H•D4
ETU3: 00FF25H•D6
ETU4: 00FF2CH•D0
ETU5: 00FF2CH•D2
ETU6: 00FF2CH•D4
ETU7: 00FF2CH•D6
FTU0: 00FF29H•D0
FTU1: 00FF29H•D2
FTU2: 00FF29H•D4
FTU3: 00FF29H•D6
FTU4: 00FF2EH•D0
FTU5: 00FF2EH•D2
FTU6: 00FF2EH•D4
FTU7: 00FF2EH•D6
Enables or disables the underflow interrupt
generation to the CPU.
Indicates the generation of underflow interrupt
factor.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
When "1" is read:
When "0" is read:
Int. factor has generated
Int. factor has not generated
Reading:
Valid
When "1" is written: Factor flag is reset
When "0" is written: Invalid
The ETUx register is the interrupt enable register
corresponding to the underflow interrupt factor of
Timer x.
Interrupt in which the ETUx register is set to "1" is
enabled, and the others in which the ETUx register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETU(L) is
invalid.
At initial reset, this register is set to "0" (interrupt
is disabled).
FTUx is the interrupt factor flag corresponding to
interrupt of Timer x, and is set to "1" due to the
counter underflow.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
ETC0: 00FF25H•D1
ETC1: 00FF25H•D3
ETC2: 00FF25H•D5
ETC3: 00FF25H•D7
ETC4: 00FF2CH•D1
ETC5: 00FF2CH•D3
ETC6: 00FF2CH•D5
ETC7: 00FF2CH•D7
Enables or disables the compare match interrupt
generation to the CPU.
In the 16-bit mode, the interrupt factor flag FTU(L)
is not set to "1" and Timer(L) interrupt is not
generated. In this mode, the interrupt factor flag
FTU(H) is set to "1" by the underflow of the 16-bit
counter.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
Valid
At initial reset, this flag is reset to "0".
The ETCx register is the interrupt enable register
corresponding to the compare match interrupt
factor of Timer x.
Interrupt in which the ETCx register is set to "1" is
enabled, and the others in which the ETCx register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETC(L) is
invalid.
At initial reset, this register is set to "0" (interrupt
is disabled).
FTC0: 00FF29H•D1
FTC1: 00FF29H•D3
FTC2: 00FF29H•D5
FTC3: 00FF29H•D7
FTC4: 00FF2EH•D1
FTC5: 00FF2EH•D3
FTC6: 00FF2EH•D5
FTC7: 00FF2EH•D7
Indicates the generation of compare match inter-
rupt factor.
When "1" is read:
When "0" is read:
Int. factor has generated
Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
106
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
FTCx is the interrupt factor flag corresponding to
interrupt of Timer x, and is set to "1" with the
compare match signal.
(3) In the 16-bit mode, reading PTM(L) does not
latch the Timer(H) counter data in PTM(H). To
avoid generating a borrow from Timer(L) to
Timer(H), read the counter data after stopping
the timer by writing "0" to PTRUN(L).
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
(4) For the reason below, pay attention to the
reload data write timing when changing the
interval of the programmable timer interrupts
while the programmable timer is running.
The programmable timer counts down at the
falling edge of the input clock and at the same
time it generates an interrupt if the counter
underflows. Then it starts loading the reload
data to the counter and the counter data is
determined at the next rising edge of the input
clock (period shown in as ➀ in the figure).
(Reload data = 25H)
➀
Input clock
In the 16-bit mode, the interrupt factor flag FTC(L)
is not set to "1" and Timer(L) interrupt is not
generated. In this mode, the interrupt factor flag
FTC(H) is set to "1" by the compare match of the
16-bit counter.
03H
02H
01H
00H
25H
24H
Counter data
(continuous mode)
Underflow (interrupt is generated)
Counter data is determined by reloading
Fig. 5.10.10.2 Reload timing for programmable timer
At initial reset, this flag is reset to "0".
To avoid improper reloading, do not rewrite
the reload data after an interrupt occurs until
the counter data is determined including the
reloading period ➀. Be especially careful when
using the OSC1 (low-speed clock) as the clock
source of the programmable timer and the CPU
is operating with the OSC3 (high-speed clock).
5.10.10 Programming notes
(1) The programmable timer actually enters into
RUN or STOP status at the falling edge of the
input clock after writing to the PTRUNx
register. Consequently, when "0" is written to
PTRUNx, the timer stops after counting once
more (+1). PTRUNx is read as "1" until the
timer actually stops.
Figure 5.10.10.1 shows the timing chart at the
RUN/ STOP control.
Input clock
PTRUNx(RD)
PTRUNx(WR)
PTMx
42H
41H 40H 3FH 3EH
3DH
Fig. 5.10.10.1 Timing chart at RUN/STOP control
(2) When the SLP instruction is executed while the
programmable timer is running (PTRUNx =
"1"), the timer stops counting during SLEEP
status. When SLEEP status is canceled, the
timer starts counting. However, the operation
becomes unstable immediately after SLEEP
status is canceled. Therefore, when shifting to
SLEEP status, stop the 16-bit programmable
timer (PTRUNx = "0") prior to executing the
SLP instruction.
Same as above, the TOUT signal output should
be disabled (PTOUTx = "0") so that an unstable
clock is not output to the clock output port
terminal.
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
5.11.2 LCD power supply
5.11 LCD Driver
The S1C88650 generates the LCD drive voltages
VC1 to VC5 using the internal power supply circuit.
It is not necessary to apply an external voltage.
Note that the internally generated voltage cannot
be used for driving external loads.
5.11.1 Configuration of LCD driver
The S1C88650 has a built-in dot matrix LCD driver
that can drive an LCD panel with a maximum of
4,032 dots (126 segments × 32 commons).
Figure 5.11.1.1 shows the configuration of the LCD
driver and the drive power supply.
The LCD system voltage regulator can be driven
with VDD or VD2 depending on the power supply
voltage level. Use the LCD system voltage regulator
power select register VDSEL for this switching.
When VDSEL is set to "0", VDD is selected and
when VDSEL is set to "1", VD2 is selected. The VD2
voltage is generated by approximately doubling the
VDD voltage in the power voltage booster circuit.
When using VD2, write "1" to the power voltage
booster circuit ON/ OFF control register DBON to
turn the power voltage booster circuit on. This must
be done before the power source of the LCD system
voltage regulator can be switched to VD2.
Programmable timer 5
underflow signal
Clock
control
circuit
FRMCS
OSC1 oscillation
circuit
fOSC1
Divider
VD2
CF
CG
DBON
Power voltage
booster
VD2
VDD
LC3
LC2
LC1
LC0
LCD contrast
adjustment circuit
VDSEL
VC1
VC2
VC3
VC4
VC5
LCDC1
LCDC0
DTFNT
LCD system
voltage regulator
VC1–VC5
LDUTY1
LDUTY0
LCD driver
CA
CB
CC
CD
CE
SEGREV
COM0–COM31
SEG0–SEG125
VSS
Display memory
DSPAR
Fig. 5.11.1.1 Configuration of LCD driver and drive power supply
108
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
5.11.3 Frame frequency
5.11.4 Switching drive duty
This LCD driver allows selection of the source clock
for generating the frame signal from the OSC1
oscillation clock (fOSC1) and the programmable
timer 5 underflow signal. By using programmable
timer 5, flexible frame frequencies can be
programmed. Refer to Section 5.10.8, "Setting frame
frequency for LCD driver".
Use the LCD frame frequency source clock select
register FRMCS to select the source clock. When
FRMCS is set to "0", fOSC1 is selected, and when it is
set to "1", programmable timer 5 is selected. The
following shows the frame frequencies when fOSC1
is selected (fOSC1 = 32.768 kHz).
The S1C88650 supports three types of LCD drive
duty settings, 1/ 8, 1/ 16 and 1/ 32, and it can be
switched using the LDUTY0 and LDUTY1 registers.
Table 5.11.4.1 shows the relationship of the LDUTY
setting, drive duty and the maximum number of
displaying dots.
When 1/ 32 duty is selected, an LCD panel with 126
segments × 32 commons (maximum 4,032 dots) can
be driven.
When 1/ 16 duty is selected, an LCD panel with 126
segments × 16 commons (maximum 2,016 dots) can
be driven. The COM16–COM31 terminals become
invalid, in that they always output an OFF signal.
When 1/ 8 duty is selected, an LCD panel with 126
segments × 8 commons (maximum 1,008 dots) can
be driven. The COM8–COM31 terminals become
invalid, in that they always output an OFF signal.
1/ 8 duty: 64 Hz
1/ 16 duty: 32 Hz
1/ 32 duty: 32 Hz
The drive bias is 1/ 5 (five potentials, VC1, VC2, VC3,
VC4 and VC5) regardless of the drive duty selected.
The respective drive waveforms are shown in
Figures 5.11.4.1 to 5.11.4.3.
Table 5.11.4.1 Correspondence between drive duty and maximum number of displaying dots
Common
terminal
Segment
terminal
Maximum number
of display dots
LDUTY1 LDUTY0
Duty
1
1
0
0
1
0
1
0
Not allowed
1/16
–
–
–
COM0–COM15 SEG0–SEG125
COM0–COM31 SEG0–SEG125
COM0–COM7 SEG0–SEG125
2,016 dots
4,032 dots
1,008 dots
1/32
1/8
OSC1
oscillation
circuit
1/64 (1/32, 1/16 duty)
1/128 (1/8 duty)
Frame
frequency
fOSC1
1/16
Divider
1/2
Selector
Programmable timer 5
underflow signal
Fig. 5.11.3.1 Dividing the source clock to generate frame frequency
S1C88650 TECHNICAL MANUAL
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109
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
32 Hz*
0 1 2 3 – – 31 0 1 2 3 – – 31
V
V
DD
SS
FR
COM0
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS
1
2
3
4
5
6
7
COM0
VC5
VC4
VC3
VC2
VC1
VSS
8
9
COM1
COM2
SEG0
SEG1
10
11
12
13
14
15
VC5
VC4
VC3
VC2
VC1
VSS
16
17
18
19
20
21
22
23
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
24
25
26
27
28
29
30
31
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS (GND)
COM0–SEG0
-VC1
-VC2
-VC3
-VC4
-VC5
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS (GND)
COM0–SEG1
-VC1
-VC2
-VC3
-VC4
-VC5
∗ when fOSC1 (32.768 kHz) is selected as the source clock (FRMCS = "0")
Fig. 5.11.4.1 Drive waveform for 1/32 duty
110
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
32 Hz*
0 1 2 3 – – 15 0 1 2 3 – – 15
V
V
DD
SS
FR
COM0
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS
1
2
3
4
5
6
7
COM0
VC5
VC4
VC3
VC2
VC1
VSS
8
9
COM1
COM2
SEG0
SEG1
10
11
12
13
14
15
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS (GND)
COM0–SEG0
-VC1
-VC2
-VC3
-VC4
-VC5
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS (GND)
COM0–SEG1
-VC1
-VC2
-VC3
-VC4
-VC5
∗ when fOSC1 (32.768 kHz) is selected as the source clock (FRMCS = "0")
Fig. 5.11.4.2 Drive waveform for 1/16 duty
S1C88650 TECHNICAL MANUAL
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111
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
64 Hz*
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
V
V
DD
SS
FR
COM0
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS
1
2
3
4
5
6
7
COM0
VC5
VC4
VC3
VC2
VC1
VSS
COM1
COM2
SEG0
SEG1
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
VC5
VC4
VC3
VC2
VC1
VSS
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS (GND)
COM0–SEG0
-VC1
-VC2
-VC3
-VC4
-VC5
V
V
V
V
V
V
C5
C4
C3
C2
C1
SS (GND)
COM0–SEG1
-VC1
-VC2
-VC3
-VC4
-VC5
∗ when fOSC1 (32.768 kHz) is selected as the source clock (FRMCS = "0")
Fig. 5.11.4.3 Drive waveform for 1/8 duty
112
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
The memory allocation for the SEG terminals can
be reversed using the SEG assignment reverse
register SEGREV.
5.11.5 Display memory
The S1C88650 has a built-in 768-byte display
memory. The display memory is allocated to
address Fx00H–Fx7FH (x = 8–DH) and the corre-
spondence between the memory bits and com-
mon/ segment terminal is changed according to
the selection status of the following items.
(1) Drive duty (1/32, 1/16 or 1/8 duty)
Table 5.11.5.1 Selecting SEG assignment
SEGREV
Assignment
Reverse
Fx00H
SEG125
SEG0
Fx70H
SEG0
1
0
Normal
SEG125
(2) Dot font (16 × 16/5 × 8 or 12 × 12 dots)
The correspondence between the display memory
bits set according to the drive duty and font size,
and the common/ segment terminals are shown in
Figures 5.11.5.1–5.11.5.6.
When "1" is written to the display memory bit
corresponding to the dot on the LCD panel, the
dot goes ON and when "0" is written, it goes OFF.
Since display memory is designed to permit
reading/ writing, it can be controlled in bit units
by logical operation instructions and other means
(read, modify and write instructions).
The display area bits which have not been as-
signed within the 768-byte display memory can be
used as general purpose RAM with read/ write
capabilities. Even when external memory has
expanded into the display memory area, this area
is not released to external memory. Access to this
area is always via display memory.
(3) SEG terminal assignment (normal or reverse)
When 1/ 16 or 1/ 8 duty is selected for the drive
duty, two screen areas are reserved in the display
memory and the area to be displayed can be
selected by the display memory area select register
DSPAR. When "0" is written to DSPAR, display
area 0 is selected and when "1" is written, display
area 1 is selected.
Furthermore, memory allocation for 16 × 16/ 5 × 8
dots and 12 × 12 dots can be selected in order to
easily display 12 × 12-dot font characters on the
LCD panel.
This selection can be done by the dot font selection
register DTFNT: when "0" is written to DTFNT, 16
× 16/ 5 × 8 dots is selected and when "1" is written,
12 × 12 dots is selected.
S1C88650 TECHNICAL MANUAL
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113
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
0
0–F
1
0–F
2
0–F
3
0–F
4
0–F
5
0–F
6
0–F
7
0–D
Address /
Data bit
COM
D0
0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
00F800H
|
Display area
Display area
Display area
Display area
00F87DH D5
D6
D7
D0
D1
D2
D3
D4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
00F900H
|
00F97DH D5
D6
D7
D0
D1
D2
D3
D4
00FA00H
|
00FA7DH D5
D6
D7
D0
D1
D2
D3
D4
00FB00H
|
00FB7DH D5
D6
D7
D0
D1
D2
D3
D4
00FC00H
|
00FC7DH D5
D6
D7
D0
D1
D2
D3
D4
00FD00H
|
00FD7DH D5
D6
D7
SEG (normal)*1
0–15
16–31
32–47
48–63
79–64
64–79
63–48
80–95 96–111 112–125
47–32 31–16 15–0
SEG (reverse)*2 125–112 111–96 95–80
∗1: SEGREV = "0" ∗2: SEGREV = "1"
Fig. 5.11.5.1 Display memory map for 1/32 duty and 16 × 16/5 × 8-dot font
114
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
0
0–F
1
0–F
2
0–F
3
0–F
4
0–F
5
0–F
6
0–F
7
0–D
Address /
Data bit
COM
D0
0
1
2
3
4
D1
D2
D3
D4
00F800H
|
00F87DH D5
5
6
7
8
Display area
D6
D7
D0
D1
9
D2
D3
D4
10
11
00F900H
|
00F97DH D5
D6
D7
D0
D1
D2
D3
D4
12
13
14
15
Display area
00FA00H
|
00FA7DH D5
D6
D7
D0
D1
D2
D3
D4
16
17
18
19
20
21
22
23
24
25
26
27
00FB00H
|
00FB7DH D5
Display area
D6
D7
D0
D1
D2
D3
D4
00FC00H
|
00FC7DH D5
D6
D7
D0
D1
D2
D3
D4
28
29
30
31
Display area
00FD00H
|
00FD7DH D5
D6
D7
SEG (normal)*1
0–15
16–31
32–47
48–63
79–64
64–79
63–48
80–95 96–111 112–125
47–32 31–16 15–0
SEG (reverse)*2 125–112 111–96 95–80
∗1: SEGREV = "0" ∗2: SEGREV = "1"
Fig. 5.11.5.2 Display memory map for 1/32 duty and 12× 12-dot font
S1C88650 TECHNICAL MANUAL
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115
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
0
0–F
1
0–F
2
0–F
3
0–F
4
0–F
5
0–F
6
0–F
7
0–D
Address /
Data bit
COM
D0
0
1
2
3
4
D1
D2
D3
D4
00F800H
|
Display area 0 (when DSPAR is set to "0")
Display area 0 (when DSPAR is set to "0")
Display area 1 (when DSPAR is set to "1")
Display area 1 (when DSPAR is set to "1")
00F87DH D5
5
6
7
8
D6
D7
D0
D1
D2
D3
D4
9
10
11
12
13
14
15
0
1
2
3
4
00F900H
|
00F97DH D5
D6
D7
D0
D1
D2
D3
D4
00FA00H
|
00FA7DH D5
5
6
7
8
D6
D7
D0
D1
D2
D3
D4
9
10
11
12
13
14
15
00FB00H
|
00FB7DH D5
D6
D7
D0
D1
D2
D3
D4
00FC00H
|
00FC7DH D5
D6
D7
D0
D1
D2
D3
D4
00FD00H
|
00FD7DH D5
D6
D7
SEG (normal)*1
0–15
16–31
32–47
48–63
79–64
64–79
63–48
80–95 96–111 112–125
47–32 31–16 15–0
SEG (reverse)*2 125–112 111–96 95–80
∗1: SEGREV = "0" ∗2: SEGREV = "1"
Fig. 5.11.5.3 Display memory map for 1/16 duty and 16 × 16/5 × 8-dot font
116
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
0
0–F
1
0–F
2
0–F
3
0–F
4
0–F
5
0–F
6
0–F
7
0–D
Address /
Data bit
COM
D0
0
1
2
3
4
D1
D2
D3
D4
00F800H
|
00F87DH D5
5
6
7
8
Display area 0 (when DSPAR is set to "0")
D6
D7
D0
D1
9
D2
D3
D4
10
11
00F900H
|
00F97DH D5
D6
D7
D0
D1
D2
D3
D4
12
13
14
15
Display area 0 (when DSPAR is set to "0")
00FA00H
|
00FA7DH D5
D6
D7
D0
D1
0
1
D2
D3
D4
2
3
4
00FB00H
|
00FB7DH D5
5
6
7
8
Display area 1 (when DSPAR is set to "1")
D6
D7
D0
D1
9
D2
D3
D4
10
11
00FC00H
|
00FC7DH D5
D6
D7
D0
D1
D2
D3
D4
12
13
14
15
Display area 1 (when DSPAR is set to "1")
00FD00H
|
00FD7DH D5
D6
D7
SEG (normal)*1
0–15
16–31
32–47
48–63
79–64
64–79
63–48
80–95 96–111 112–125
47–32 31–16 15–0
SEG (reverse)*2 125–112 111–96 95–80
∗1: SEGREV = "0" ∗2: SEGREV = "1"
Fig. 5.11.5.4 Display memory map for 1/16 duty and 12× 12-dot font
S1C88650 TECHNICAL MANUAL
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117
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
0
0–F
1
0–F
2
0–F
3
0–F
4
0–F
5
0–F
6
0–F
7
0–D
Address /
Data bit
COM
D0
0
1
2
3
4
5
6
7
D1
D2
D3
D4
00F800H
|
Display area 0 (when DSPAR is set to "0")
00F87DH D5
D6
D7
D0
D1
D2
D3
D4
00F900H
|
00F97DH D5
D6
D7
D0
D1
D2
D3
D4
0
1
2
3
4
5
6
7
00FA00H
|
Display area 1 (when DSPAR is set to "1")
00FA7DH D5
D6
D7
D0
D1
D2
D3
D4
00FB00H
|
00FB7DH D5
D6
D7
D0
D1
D2
D3
D4
00FC00H
|
00FC7DH D5
D6
D7
D0
D1
D2
D3
D4
00FD00H
|
00FD7DH D5
D6
D7
SEG (normal)*1
0–15
16–31
32–47
48–63
79–64
64–79
63–48
80–95 96–111 112–125
47–32 31–16 15–0
SEG (reverse)*2 125–112 111–96 95–80
∗1: SEGREV = "0" ∗2: SEGREV = "1"
Fig. 5.11.5.5 Display memory map for 1/8 duty and 5 × 8-dot font
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
0
0–F
1
0–F
2
0–F
3
0–F
4
0–F
5
0–F
6
0–F
7
0–D
Address /
Data bit
COM
D0
0
1
2
3
4
5
6
7
D1
D2
D3
D4
00F800H
|
Display area 0 (when DSPAR is set to "0")
00F87DH D5
D6
D7
D0
D1
D2
D3
D4
00F900H
|
00F97DH D5
D6
D7
D0
D1
D2
D3
D4
00FA00H
|
00FA7DH D5
D6
D7
D0
D1
D2
D3
D4
0
1
2
3
4
5
6
7
00FB00H
|
Display area 1 (when DSPAR is set to "1")
00FB7DH D5
D6
D7
D0
D1
D2
D3
D4
00FC00H
|
00FC7DH D5
D6
D7
D0
D1
D2
D3
D4
00FD00H
|
00FD7DH D5
D6
D7
SEG (normal)*1
0–15
16–31
32–47
48–63
79–64
64–79
63–48
80–95 96–111 112–125
47–32 31–16 15–0
SEG (reverse)*2 125–112 111–96 95–80
∗1: SEGREV = "0" ∗2: SEGREV = "1"
Fig. 5.11.5.6 Display memory map for 1/8 duty and 12× 12-dot font
S1C88650 TECHNICAL MANUAL
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119
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
Selecting LCD drive OFF turns the LCD drive
power circuit OFF and all the VC1 to VC5 terminals
go to VSS level.
Furthermore, when the SLP instruction is executed,
registers LCDC0 and LCDC1 are automatically
reset to "0" (set to drive off) by hardware.
5.11.6 Display control
The display status of the built-in LCD driver and
the contrast adjustment can be controlled with the
built-in LCD driver. The LCD display status can be
selected by display control registers LCDC0 and
LCDC1. Setting the value and display status are
shown in Table 5.11.6.1.
The LCD contrast can be adjusted in 16 stages. This
adjustment is done by the contrast adjustment
register LC0–LC3, and the setting values corre-
spond to the contrast as shown in Table 5.11.6.2.
Table 5.11.6.1 LCD display control
LCDC1 LCDC0
LCD display
All LCDs lit (Static)
All LCDs out (Dynamic)
Normal display
1
1
0
0
1
0
1
0
Table 5.11.6.2 LCD contrast adjustment
LC3 LC2 LC1 LC0
Contrast
Dark
↑
1
1
1
:
1
1
1
:
1
1
0
:
1
0
1
:
Drive OFF
All the dots in the LCD display can be turned on or
off directly by the drive waveform output from the
LCD driver, and data in the display memory is not
changed. Also, since the common terminal at this
time is set to static drive when all the dots are on
and is set to dynamic drive when they are off, this
function can be used as follows:
0
0
0
0
0
0
1
0
0
0
1
0
↓
Light
(1) Since all dots on is binary output (VC5 and VSS)
with static drive, the common/ segment termi-
nal can be used as a monitor terminal for the
OSC1 oscillation frequency adjustment.
(2) Since all dots off is dynamic drive, you can
brink the entire LCD display without changing
display memory data.
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
5.11.7 Control of LCD driver
Table 5.11.7.1 shows the LCD driver control bits.
Table 5.11.7.1 LCD driver control bits
Address Bit Name
Function
1
–
–
–
–
–
–
0
–
SR R/W
Comment
Constantly "0" when
being read
00FF03 D7 –
D6 –
–
–
–
–
–
–
–
–
–
–
–
–
–
D5 –
–
D4 –
–
D3 –
–
D2 –
–
D1 VDSEL Power source select for LCD voltage regulator
D0 DBON Power voltage booster On/Off control
00FF10 D7 HLMOD Heavy load protection mode
D6 SEGREV Reverse SEG assignment
V
D2
V
DD
0
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
On
Off
On
Off
Reverse
Normal
D5 –
D4 –
D3 –
R/W register
R/W register
R/W register
1
0
R/W Reserved register
1
1
0
0
R/W
R/W
R/W
R/W
D2 DTFNT LCD dot font selection
D1 LDUTY1 LCD drive duty selection
LDUTY1 LDUTY0
12×12
16×16/5×8
Duty
Not allowed
1/16
1
1
0
0
1
0
1
0
D0 LDUTY0
0
R/W
1/32
1/8
00FF11 D7 FRMCS LCD frame signal source clock selection
D6 DSPAR LCD display memory area selection
D5 LCDC1 LCD display control
PTM
fOSC1
0
0
0
R/W
R/W
Display area 1 Display area 0
These bits are reset
R/W
to (0, 0) when
LCD display
LCDC1 LCDC0
SLP instruction
1
1
0
0
1
0
1
0
All LCDs lit
All LCDs out
Normal display
Drive off
is executed.
R/W
D4 LCDC0
0
D3 LC3
D2 LC2
D1 LC1
D0 LC0
LCD contrast adjustment
0
0
0
0
R/W
R/W
R/W
R/W
LC3 LC2 LC1 LC0
Contrast
Dark
1
1
:
1
1
:
1
1
:
1
0
:
:
:
Light
0
0
0
0
LDUTY0, LDUTY1: 00FF10H•D0, D1
Selects the drive duty.
Table 5.11.7.2 Setting drive duty
Common
terminal
Segment
terminal
Maximum number
of display dots
LDUTY1 LDUTY0
Duty
1
1
0
0
1
0
1
0
Not allowed
1/16
–
–
–
COM0–COM15 SEG0–SEG125
COM0–COM31 SEG0–SEG125
COM0–COM7 SEG0–SEG125
2,016 dots
4,032 dots
1,008 dots
1/32
1/8
At initial reset, LDUTY is set to "10" (1/ 16 duty).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
DTFNT: 00FF10H•D2
LCDC0, LCDC1: 00FF11H•D4, D5
Selects the dot font.
Controls the LCD display.
When "1" is written: 12 × 12 dots
Table 5.11.7.4 LCD display control
When "0" is written: 16 × 16/ 5 × 8 dots
LCDC1 LCDC0
LCD display
All LCDs lit (Static)
All LCDs out (Dynamic)
Normal display
Reading:
Valid
1
1
0
0
1
0
1
0
Select 16 × 16/ 5 × 8 dots or 12 × 12 dots type for the
display memory area.
When "0" is written to DTFNT, 16 × 16/ 5 × 8 dots is
selected and when "1" is written, 12 × 12 dots is
selected.
The correspondence between the display memory
bits set according to the dot font, and the common/
segment terminals are shown in Figures 5.11.5.1–
5.11.5.5.
At initial reset, DTFNT is set to "0" (16 × 16/ 5 × 8
dots).
Drive OFF
The four settings mentioned above can be made
without changing the display memory data.
At initial reset and in the SLEEP status, this register
is set to "0" (drive off).
LC0–LC3: 00FF11H•D0–D3
Adjusts the LCD contrast.
Table 5.11.7.5 LCD contract adjustment
SEGREV: 00FF10H•D6
LC3
1
LC2
1
LC1
1
LC0
1
Contrast
Dark
↑
Reverses the memory allocation for the SEG
terminals.
1
1
1
0
Table 5.11.7.3 Selecting SEG assignment
1
1
0
1
SEGREV
Assignment
Reverse
Fx00H
SEG125
SEG0
Fx70H
SEG0
1
1
0
0
1
0
1
0
1
1
Normal
SEG125
1
0
1
0
1
0
0
1
At initial reset, SEGREV is set to "0" (normal).
1
0
0
0
DSPAR: 00FF11H•D6
0
1
1
1
0
1
1
0
Selects the display area.
0
1
0
1
When "1" is written: Display area 1
When "0" is written: Display area 0
0
1
0
0
0
0
1
1
Reading:
Valid
0
0
1
0
An area to be displayed is selected from two areas
in the display memory.
When "0" is written to DSPAR, display area 0 is
selected and when "1" is written, display area 1 is
selected.
The correspondence between the display memory
bits set according to the display area, and the
common/ segment terminals are shown in Figures
5.11.5.1–5.11.5.5.
0
0
0
1
↓
0
0
0
0
Light
The contrast can be adjusted in 16 stages as
mentioned above. This adjustment changes the
drive voltage on terminals VC1 to VC5.
At initial reset, this register is set to "0".
FRMCS: 00FF11H•D7
At initial reset, DSPAR is set to "0" (display area 0).
Selects the source clock for generating the frame
signal.
When "1" is written: Programmable timer 5
When "0" is written: fOSC1
Reading:
Valid
When "0" is written to FRMCS, fOSC1 is selected,
and when "1" is written, programmable timer 5 is
selected.
At initial reset, FRMCS is set to "0" (fOSC1).
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (LCD Driver)
DBON: 00FF03H•D0
5.11.8 Programming notes
(1) When the SLP instruction is executed, display
control registers LCDC0 and LCDC1 are
automatically reset to "0" by hardware.
Control the power voltage booster circuit.
When "1" is written: ON
When "0" is written: OFF
Reading:
Valid
(2) When driving the LCD system voltage regulator
with VD2, wait at least 1 msec for stabilization of
When "1" is written to DBON, the power voltage
booster activates and almost doubles the VDD
voltage to generate the VD2 voltage. Turn the power
voltage booster on when driving the LCD system
voltage regulator with VD2.
the voltage before switching the power voltage
for the LCD system voltage regulator to VD2
using VDSEL after the power voltage booster is
turned on.
When "0" is written to DBON, the power voltage
booster goes off. When driving the LCD system
voltage regulator with VDD, turn the power voltage
booster off to reduce current consumption.
At initial reset, DBON is set to "0" (OFF).
VDSEL: 00FF03H•D1
Selects the power voltage for the LCD system
voltage regulator.
When "1" is written: VD2
When "0" is written: VDD
Reading:
Valid
When "1" is written to VDSEL, the LCD system
voltage regulator is driven with VD2 generated by
the power voltage booster. Before this setting is
made, it is necessary to write "1" to DBON to turn
on the power voltage booster. Furthermore, do not
switch the power voltage to VD2 for at least 1 msec
after the power voltage booster is turned on to
allow VD2 stabilize.
When "0" is written to VDSEL, the LCD system
voltage regulator is driven with VDD.
At initial reset, VDSEL is set to "0" (VDD).
S1C88650 TECHNICAL MANUAL
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123
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
Table 5.12.2.1 Criteria voltage setting
Criteria
5.12 Supply Voltage Detection
SVDS3 SVDS2 SVDS1 SVDS0
(SVD) Circuit
voltage (V)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.05
2.0
1.95
1.9
1.85
1.8
–
5.12.1 Configuration of SVD circuit
The S1C88650 has a built-in SVD (supply voltage
detection) circuit, so that the software can find
when the source voltage lowers. Turning the SVD
circuit ON/ OFF and the SVD criteria voltage
setting can be done with software.
Figure 5.12.1.1 shows the configuration of the SVD
circuit.
5.12.2 SVD operation
The SVD circuit compares the criteria voltage set by
software and the supply voltage (VDD–VSS) and sets
its results into the SVDDT latch. By reading the
data of this SVDDT latch, it can be determined by
means of software whether the supply voltage is
normal or has dropped.
–
–
The criteria voltage can be set for the 13 types
shown in Table 5.12.2.1 by the SVDS3–SVDS0
registers.
When the SVDON register is set to "1", source
voltage detection by the SVD circuit is executed. As
soon as the SVDON register is reset to "0", the result
is loaded to the SVDDT latch and the SVD circuit
goes OFF.
To obtain a stable detection result, the SVD circuit
must be ON for at least 500 µsec. So, to obtain the
SVD detection result, follow the programming
sequence below.
1. Set SVDON to "1"
2. Maintain for 500 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
When the SVD circuit is ON, the IC draws a large
current, so keep the SVD circuit off unless it is.
VDD
Detection output
SVDDT
SVDON
SVD circuit
VSS
SVDS3
|
SVDS0
Criteria voltage
setting circuit
Fig. 5.12.1.1 Configuration of SVD circuit
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
5.12.3 Control of SVD circuit
Table 5.12.3.1 shows the SVD circuit control bits.
Table 5.12.3.1 SVD circuit control bits
Address Bit Name
00FF12 D7 –
D6 –
Function
1
–
0
SR R/W
Comment
Constantly "0" when
being read
–
–
–
–
–
–
–
D5 SVDDT SVD detection data
Low
On
Normal
Off
0
0
0
R
D4 SVDON SVD circuit On/Off
R/W
R/W
SVD criteria voltage setting
SVDS3 SVDS2 SVDS1 SVDS0 Voltage (V)
D3 SVDS3
D2 SVDS2
D1 SVDS1
D0 SVDS0
0
0
0
R/W
R/W
R/W
1
1
1
:
1
1
1
:
1
1
0
:
1
0
1
:
2.7
2.6
2.5
:
0
0
1
1
1.8
SVDS3–SVDS0: 00FF12H•D3–D0
5.12.4 Programming notes
Criteria voltage for SVD is set as shown in Table
5.12.2.1.
At initial reset, this register is set to "0".
(1) To obtain a stable detection result, the SVD
circuit must be ON for at least 500 µsec. So, to
obtain the SVD detection result, follow the
programming sequence below.
SVDON: 00FF12H•D4
1. Set SVDON to "1"
2. Maintain for 500 µsec minimum
3. Set SVDON to "0"
Controls the SVD circuit ON and OFF.
When "1" is written: SVD circuit ON
When "0" is written: SVD circuit OFF
4. Read SVDDT
Reading:
Valid
(2) The SVD circuit should normally be turned OFF
because SVD operation increase current con-
sumption.
When the SVDON register is set to "1", a supply
voltage detection is executed by the SVD circuit. As
soon as SVDON is reset to "0", the result is loaded
to the SVDDT latch. To obtain a stable detection
result, the SVD circuit must be ON for at least 500
µsec.
At initial reset, this register is set to "0".
SVDDT: 00FF12H•D5
This is the result of supply voltage detection.
When "0" is read:
When "1" is read:
Writing:
Supply voltage (VDD–VSS)
≥ Criteria voltage
Supply voltage (VDD–VSS)
< Criteria voltage
Invalid
The result of supply voltage detection at time of
SVDON is set to "0" can be read from this latch.
At initial reset, SVDDT is set to "0".
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Heavy Load Protection Function)
5.13 Heavy Load Protection Function
5.13.1 Outline of heavy load protection function
The S1C88650 has a heavy load protection function to
prevent malfunction due to a power voltage
fluctuation caused by a heavy battery load such as
when an external lamp is driven and while the IC is
running in high-speed with the OSC3 clock. This
function works when the IC enters the heavy load
protection mode. Set the IC into the heavy load
protection mode when there are inconsistencies in
density on the LCD panel as well as when the IC is
under one of the condition above.
The normal mode (heavy load protection function
is off) changes to the heavy load protection mode
(heavy load protection function is on) when the
software changes the mode to the heavy load
protection mode (HLMOD = "1").
Note: In the heavy load protection mode, more
current is consumed than in the normal
mode. Unless necessary, do not select the
heavy load protection mode with the
software.
5.13.2 Control of heavy load protection function
Table 5.13.2.1 shows the control bit for the heavy load protection function.
Table 5.13.2.1 Control bit for heavy load protection function
Address Bit Name
Function
1
0
SR R/W
Comment
00FF10 D7 HLMOD Heavy load protection mode
On
Off
0
0
0
0
0
0
1
R/W
R/W
D6 SEGREV Reverse SEG assignment
Reverse
Normal
D5 –
D4 –
D3 –
R/W register
R/W register
R/W register
1
0
R/W Reserved register
1
1
0
0
R/W
R/W
R/W
R/W
D2 DTFNT LCD dot font selection
D1 LDUTY1 LCD drive duty selection
LDUTY1 LDUTY0
12×12
16×16/5×8
Duty
Not allowed
1/16
1
1
0
0
1
0
1
0
D0 LDUTY0
0
R/W
1/32
1/8
HLMOD: 00FF10H•D7
5.13.3 Programming note
Controls the heavy load protection mode.
In the heavy load protection mode, more current is
consumed than in the normal mode. Unless
necessary, do not select the heavy load protection
mode with the software.
When "1" is written: Heavy load protection ON
When "0" is written: Heavy load protection OFF
Reading:
Valid
The device enters the heavy load protection mode
by writing "1" to HLMOD, and returns to the
normal mode by writing "0". In the heavy load
protection mode, the consumed current becomes
larger. Unless necessary, do not select the heavy
load protection mode with the software.
At initial reset, this register is set to "0".
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
5.14.1 Interrupt generation conditions
5.14 Interrupt and Standby Status
The interrupt factor flags that indicate the genera-
tion of their respective interrupt factors are pro-
vided for the previously indicated 4 systems and 31
types of interrupts and they will be set to "1" by the
generation of a factor.
■ Types of interrupts
4 systems and 31 types of interrupts have been
provided for the S1C88650.
External interrupt
In addition, interrupt enable registers with a 1 to 1
correspondence to each of the interrupt factor flags
are provided. An interrupt is enabled when "1" is
written and interrupt is disabled when "0" is
written.
• K00–K07 input interrupt (8 types)
Internal interrupt
• Clock timer interrupt (4 types)
• Programmable timer interrupt (16 types)
• Serial interface interrupt (3 types)
The CPU manages the enable/ disable of interrupt
requests at the interrupt priority level. An interrupt
priority register that sets the priority level is
provided for each of the interrupts of the 4 systems
and the CPU accepts only interrupts above the level
that has been indicated with the interrupt flags (I0
and I1).
An interrupt factor flag that indicates the genera-
tion of an interrupt factor and an interrupt enable
register that sets enable/ disable for interrupt
requests have been provided for each interrupt
and interrupt generation can be optionally set for
each factor.
Consequently, the following three conditions are
necessary for the CPU to accept the interrupt.
In addition, an interrupt priority register has been
provided for each system of interrupts and the
priority of interrupt processing can be set to 3
levels in each system.
Figure 5.14.1 shows the configuration of the
interrupt circuit.
(1) The interrupt factor flag has been set to "1" by
generation of an interrupt factor.
(2) The interrupt enable register corresponding to
the above has been set to "1".
Refer to the explanations of the respective periph-
eral circuits for details on each interrupt.
(3) The interrupt priority register corresponding to
the above has been set to a priority level higher
than the interrupt flag (I0 and I1) setting.
■ HALT status
By executing the program's HALT instruction, the
The CPU initially samples the interrupt for the first
op-code fetch cycle of each instruction. Thereupon,
the CPU shifts to the exception processing when the
above mentioned conditions have been established.
See the "S1C88 Core CPU Manual" for the exception
processing sequence.
S1C88650 enters the HALT status.
Since CPU operation stops in the HALT status,
power consumption can be reduced with only
peripheral circuit operation.
Cancellation of the HALT status is done by initial
reset or an optional interrupt request, and the CPU
restarts program execution from an exception
processing routine.
See the "S1C88 Core CPU Manual" for the HALT
status and reactivation sequence.
■ SLEEP status
By executing the program's SLP instruction, the
S1C88650 enters the SLEEP status.
Since the operation of the CPU and peripheral
circuits stop completely in the SLEEP status, power
consumption can be reduced even more than in the
HALT status.
Cancellation of the SLEEP status is done by initial
reset or an input interrupt from the input port. The
CPU reactivates after waiting 128/ fOSC1 or 512/
fOSC3 seconds of oscillation stabilization time (the
oscillation stabilization time varies depending on
the operating clock being used when the SLP
instruction is executed). At this time, the CPU
restarts program execution from an exception
processing routine (input interrupt routine).
Note: The oscillation becomes unstable for a while
after SLEEP status is cancelled, the wait
time for restarting the CPU may be longer
than 128/fOSC1 or 512/fOSC3 seconds.
S1C88650 TECHNICAL MANUAL
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
Interrupt factor flag
Interrupt enable register
Interrupt priority register
Vector
address
Interrupt vector
address generation
circuit
FK07
K07
EK07
FK06
K06
EK06
FK05
K05
EK05
FK04
K04
EK04
Input port
FK03
K03
PK00
EK03
FK02
EK02
FK01
EK01
FK00
EK00
PK01
K02
K01
K00
FTU0
ETU0
FTC0
ETC0
Underflow
Program-
mable
timer 0
Compare
match
FTU1
ETU1
FTC1
ETC1
Underflow
PPT0
PPT1
Program-
mable
timer 1
Compare
match
FTU2
ETU2
FTC2
ETC2
Underflow
Program-
mable
timer 2
Compare
match
FTU3
ETU3
FTC3
ETC3
Underflow
PPT2
PPT3
NMI
Program-
mable
timer 3
Interrupt priority
level judgement
circuit
IRQ3
IRQ2
IRQ1
Compare
match
FTU4
ETU4
FTC4
ETC4
Underflow
Program-
mable
timer 4
Compare
match
FTU5
ETU5
FTC5
ETC5
Underflow
PPT4
PPT5
Program-
mable
timer 5
Compare
match
FTU6
ETU6
FTC6
ETC6
Underflow
Program-
mable
timer 6
Compare
match
FTU7
ETU7
FTC7
ETC7
Underflow
PPT6
PPT7
Program-
mable
timer 7
Compare
match
FSERR
ESERR
FSREC
ESREC
FSTRA
ESTRA
Error
Serial
interface
Receive
Transmit
PSIF0
PSIF1
FTM32
ETM32
FTM8
ETM8
FTM2
ETM2
FTM1
ETM1
32 Hz
8 Hz
2 Hz
1 Hz
Clock timer
PTM0
PTM1
Fig. 5.14.1 Configuration of interrupt circuit
128
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
Note: When executing the RETE instruction
5.14.2 Interrupt factor flag
Table 5.14.2.1 shows the correspondence between
the factors generating an interrupt and the inter-
rupt factor flags.
The corresponding interrupt factor flags are set to
"1" by generation of the respective interrupt factors.
The corresponding interrupt factor can be con-
firmed by reading the flags through software.
Interrupt factor flag that has been set to "1" is reset
to "0" by writing "1".
without resetting the interrupt factor flag after
an interrupt has been generated, the same
interrupt will be generated. Consequently,
the interrupt factor flag corresponding to that
routine must be reset (writing "1") in the
interrupt processing routine.
At initial reset, the interrupt factor flags are reset to "0".
Table 5.14.2.1 Interrupt factors
Interrupt factor
K07 input of falling edge or rising edge (instruction at KCP07)
K06 input of falling edge or rising edge (instruction at KCP06)
K05 input of falling edge or rising edge (instruction at KCP05)
K04 input of falling edge or rising edge (instruction at KCP04)
K03 input of falling edge or rising edge (instruction at KCP03)
K02 input of falling edge or rising edge (instruction at KCP02)
K01 input of falling edge or rising edge (instruction at KCP01)
K00 input of falling edge or rising edge (instruction at KCP00)
Programmable timer 0 underflow
Programmable timer 0 compare match
Programmable timer 1 underflow
Programmable timer 1 compare match
Programmable timer 2 underflow
Programmable timer 2 compare match
Programmable timer 3 underflow
Programmable timer 3 compare match
Programmable timer 4 underflow
Programmable timer 4 compare match
Programmable timer 5 underflow
Programmable timer 5 compare match
Programmable timer 6 underflow
Programmable timer 6 compare match
Programmable timer 7 underflow
Programmable timer 7 compare match
Serial interface receiving error (in asynchronous mode)
Serial interface receiving completion
Interrupt factor flag
FK07
00FF28H·D7
00FF28H·D6
00FF28H·D5
00FF28H·D4
00FF28H·D3
00FF28H·D2
00FF28H·D1
00FF28H·D0
00FF29H·D0
00FF29H·D1
00FF29H·D2
00FF29H·D3
00FF29H·D4
00FF29H·D5
00FF29H·D6
00FF29H·D7
00FF2EH·D0
00FF2EH·D1
00FF2EH·D2
00FF2EH·D3
00FF2EH·D4
00FF2EH·D5
00FF2EH·D6
00FF2EH·D7
00FF27H·D2
00FF27H·D1
00FF27H·D0
00FF26H·D3
00FF26H·D2
00FF26H·D1
00FF26H·D0
FK06
FK05
FK04
FK03
FK02
FK01
FK00
FTU0
FTC0
FTU1
FTC1
FTU2
FTC2
FTU3
FTC3
FTU4
FTC4
FTU5
FTC5
FTU6
FTC6
FTU7
FTC7
FSERR
FSREC
FSTRA
FTM32
FTM8
FTM2
FTM1
Serial interface transmitting completion
Falling edge of the clock timer 32 Hz signal
Falling edge of the clock timer 8 Hz signal
Falling edge of the clock timer 2 Hz signal
Falling edge of the clock timer 1 Hz signal
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
This register also permits reading, thus making it
5.14.3 Interrupt enable register
The interrupt enable register has a 1 to 1 corre-
spondence with each interrupt factor flag and
enable/ disable of interrupt requests can be set.
possible to confirm that a status has been set.
At initial reset, the interrupt enable registers are set
to "0" and shifts to the interrupt disable status.
Table 5.14.3.1 shows the correspondence between
the interrupt enable registers and the interrupt
factor flags.
When "1" is written to the interrupt enable register,
an interrupt request is enabled, and is disabled
when "0" is written.
Table 5.14.3.1 Interrupt enable registers and interrupt factor flags
Interrupt
Interrupt factor flag
Interrupt enable register
K07 input
K06 input
K05 input
K04 input
K03 input
K02 input
K01 input
K00 input
Timer 0 underflow
Timer 0 compare match
Timer 1 underflow
Timer 1 compare match
Timer 2 underflow
Timer 2 compare match
Timer 3 underflow
Timer 3 compare match
Timer 4 underflow
Timer 4 compare match
Timer 5 underflow
Timer 5 compare match
Timer 6 underflow
Timer 6 compare match
Timer 7 underflow
Timer 7 compare match
Serial interface receiving error
Serial interface receiving completion
Serial interface transmitting completion
Clock timer 32 Hz
FK07
FK06
FK05
FK04
FK03
FK02
FK01
FK00
FTU0
FTC0
FTU1
FTC1
FTU2
FTC2
FTU3
FTC3
FTU4
FTC4
FTU5
FTC5
FTU6
FTC6
FTU7
FTC7
FSERR
FSREC
FSTRA
FTM32
FTM8
FTM2
FTM1
00FF28H·D7
00FF28H·D6
00FF28H·D5
00FF28H·D4
00FF28H·D3
00FF28H·D2
00FF28H·D1
00FF28H·D0
00FF29H·D0
00FF29H·D1
00FF29H·D2
00FF29H·D3
00FF29H·D4
00FF29H·D5
00FF29H·D6
00FF29H·D7
00FF2EH·D0
00FF2EH·D1
00FF2EH·D2
00FF2EH·D3
00FF2EH·D4
00FF2EH·D5
00FF2EH·D6
00FF2EH·D7
00FF27H·D2
00FF27H·D1
00FF27H·D0
00FF26H·D3
00FF26H·D2
00FF26H·D1
00FF26H·D0
EK07
EK06
EK05
EK04
EK03
EK02
EK01
EK00
ETU0
ETC0
ETU1
ETC1
ETU2
ETC2
ETU3
ETC3
ETU4
ETC4
ETU5
ETC5
ETU6
ETC6
ETU7
ETC7
ESERR
ESREC
ESTRA
ETM32
ETM8
ETM2
ETM1
00FF24H·D7
00FF24H·D6
00FF24H·D5
00FF24H·D4
00FF24H·D3
00FF24H·D2
00FF24H·D1
00FF24H·D0
00FF25H·D0
00FF25H·D1
00FF25H·D2
00FF25H·D3
00FF25H·D4
00FF25H·D5
00FF25H·D6
00FF25H·D7
00FF2CH·D0
00FF2CH·D1
00FF2CH·D2
00FF2CH·D3
00FF2CH·D4
00FF2CH·D5
00FF2CH·D6
00FF2CH·D7
00FF23H·D2
00FF23H·D1
00FF23H·D0
00FF22H·D3
00FF22H·D2
00FF22H·D1
00FF22H·D0
Clock timer 8 Hz
Clock timer 2 Hz
Clock timer 1 Hz
130
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
5.14.4 Interrupt priority register and interrupt priority level
Table 5.14.4.1 Interrupt priority register
Interrupt
Interrupt priority register
K00–K07 input interrupt
PK00, PK01
PPT0, PPT1
PPT2, PPT3
PPT4, PPT5
PPT6, PPT7
PSIF0, PSIF1
PTM0, PTM1
00FF20·D6, D7
00FF21·D2, D3
00FF21·D4, D5
00FF2A·D0, D1
00FF2A·D2, D3
00FF20·D4, D5
00FF20·D0, D1
Programmable timer interrupt 1–0
Programmable timer interrupt 3–2
Programmable timer interrupt 5–4
Programmable timer interrupt 7–6
Serial interface interrupt
Clock timer interrupt
The interrupt priority registers shown in Table
5.14.4.1 are set to each system of interrupts and the
interrupt priority levels for the CPU can be set to
the optional priority level (0–3). As a result, it is
possible to have multiple interrupts that match the
system's interrupt processing priority levels.
After an interrupt has been accepted, the interrupt
flags are written to the level of that interrupt.
However, interrupt flags after an NMI has been
accepted are written to level 3 (I0 = I1 = "1").
Table 5.14.4.4 Interrupt flags after acceptance of interrupt
Accepted interrupt priority level
I1
1
I0
1
The interrupt priority level between each system
can optionally be set to three levels by the interrupt
priority register. However, when more than one
system is set to the same priority level, they are
processed according to the default priority level.
Level 4
Level 3
Level 2
Level 1
(NMI)
(IRQ3)
(IRQ2)
(IRQ1)
1
1
1
0
0
1
Table 5.14.4.2 Setting of interrupt priority level
The set interrupt flags are reset to their original
value on return from the interrupt processing
routine. Consequently, multiple interrupts up to 3
levels can be controlled by the initial settings of the
interrupt priority registers alone. Additional
multiplexing can be realized by rewriting the
interrupt flags and interrupt enable register in the
interrupt processing routine.
Interrupt priority level
P*1
P*0
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, the interrupt priority registers are
all set to "0" and each interrupt is set to level 0.
Furthermore, the priority levels in each system
have been previously decided and they cannot be
changed.
The CPU can mask each interrupt by setting the
interrupt flags (I0 and I1). The relation between the
interrupt priority level of each system and interrupt
flags is shown in Table 5.14.4.3, and the CPU
accepts only interrupts above the level indicated by
the interrupt flags.
Note: Beware. If the interrupt flags have been
rewritten (set to lower priority) prior to
resetting an interrupt factor flag after an
interrupt has been generated, the same
interrupt will be generated again.
The NMI (watchdog timer) that has level 4 priority,
is always accepted regardless of the setting of the
interrupt flags.
Table 5.14.4.3 Interrupt mask setting of CPU
Acceptable interrupt
Level 4 (NMI)
I1
1
I0
1
1
0
Level 4, Level 3 (IRQ3)
0
1
Level 4, Level 3, Level 2 (IRQ2)
Level 4, Level 3, Level 2, Level 1 (IRQ1)
0
0
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
Table 5.14.5.1 Vector address and exception
5.14.5 Exception processing vectors
processing correspondence
When the CPU accepts an interrupt request, it starts
exception processing following completion of the
instruction being executed. In exception processing,
the following operations branch the program.
Vector
address
Priority
Exception processing factor
000000H Reset
000002H Zero division
High
↑
(1) In the minimum mode, the program counter
(PC) and system condition flag (SC) are moved
to stack and in the maximum mode, the code
bank register (CB), PC and SC are moved.
000004H Watchdog timer (NMI)
000006H K07 input interrupt
000008H K06 input interrupt
00000AH K05 input interrupt
00000CH K04 input interrupt
(2) The branch destination address is read from the
exception processing vector corresponding to
each exception processing (interrupt) factor and
is placed in the PC.
00000EH K03 input interrupt
000010H K02 input interrupt
000012H K01 input interrupt
000014H K00 input interrupt
000016H PTM 0 underflow interrupt
000018H PTM 0 compare match interrupt
00001AH PTM 1 underflow interrupt
00001CH PTM 1 compare match interrupt
00001EH PTM 2 underflow interrupt
000020H PTM 2 compare match interrupt
000022H PTM 3 underflow interrupt
000024H PTM 3 compare match interrupt
000026H System reserved (cannot be used)
000028H Serial I/F error interrupt
00002AH Serial I/F receiving complete interrupt
00002CH Serial I/F transmitting complete interrupt
00002EH System reserved (cannot be used)
000030H System reserved (cannot be used)
000032H System reserved (cannot be used)
000034H Clock timer 32 Hz interrupt
000036H Clock timer 8 Hz interrupt
000038H Clock timer 2 Hz interrupt
00003AH Clock timer 1 Hz interrupt
00003CH PTM 4 underflow interrupt
00003EH PTM 4 compare match interrupt
000040H PTM 5 underflow interrupt
000042H PTM 5 compare match interrupt
000044H PTM 6 underflow interrupt
000046H PTM 6 compare match interrupt
000048H PTM 7 underflow interrupt
00004AH PTM 7 compare match interrupt
00004CH System reserved (cannot be used)
00004EH
An exception vector is 2 bytes of data in which the
top address of each exception (interrupt) processing
routine has been stored and the vector addresses
correspond to the exception processing factors as
shown in Table 5.14.5.1.
Note: An exception processing vector is fixed at 2
bytes, so it cannot specify a branch destination
bank address. Consequently, to branch from
multiple banks to a common exception process-
ing routine, the top portion of an exception
processing routine must be described within the
common area (000000H–007FFFH).
↓
Low
No
priority
rating
:
Software interrupt
0000FEH
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
5.14.6 Control of interrupt
Table 5.14.6.1 shows the interrupt control bits.
Table 5.14.6.1(a) Interrupt control bits
Address Bit Name
00FF20 D7 PK01
D6 PK00
Function
1
0
SR R/W
Comment
PK01 PK00 Priority
PSIF1 PSIF0 level
K00–K07 interrupt priority register
0
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D5 PSIF1
D4 PSIF0
D3 –
Serial interface interrupt priority register
0
R/W
–
–
–
–
–
–
0
Constantly "0" when
being read
D2 –
–
–
PTM1 PTM0 Priority level
D1 PTM1
Clock timer interrupt priority register
R/W
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
D0 PTM0
00FF21 D7 –
D6 –
–
–
–
–
–
–
0
Constantly "0" when
being read
–
–
PPT3 PPT2 Priority
PPT1 PPT0
D5 PPT3
D4 PPT2
D3 PPT1
D2 PPT0
D1 –
Programmable timer 3–2 interrupt
R/W
R/W
level
priority register
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Programmable timer 1–0 interrupt
0
priority register
–
Level 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
Constantly "0" when
being read
D0 –
–
00FF2A D7 –
D6 –
–
Constantly "0" when
being read
–
D5 –
–
D4 –
–
PPT7 PPT6 Priority
PPT5 PPT4
D3 PPT7
D2 PPT6
D1 PPT5
D0 PPT4
00FF22 D7 –
D6 –
Programmable timer 7–6 interrupt
R/W
R/W
level
priority register
1
1
0
0
1
0
1
0
Level 3
Level 2
Level 1
Level 0
Programmable timer 5–4 interrupt
0
priority register
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D5 –
D4 –
D3 ETM32 Clock timer 32 Hz interrupt enable register
D2 ETM8
D1 ETM2
D0 ETM1
Clock timer 8 Hz interrupt enable register
Interrupt
enable
Interrupt
disable
0
R/W
Clock timer 2 Hz interrupt enable register
Clock timer 1 Hz interrupt enable register
00FF23 D7 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
D2 ESERR Serial I/F (error) interrupt enable register
D1 ESREC Serial I/F (receiving) interrupt enable register
D0 ESTRA Serial I/F (transmitting) interrupt enable register
Interrupt
enable
Interrupt
disable
0
R/W
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
Table 5.14.6.1(b) Interrupt control bits
Address Bit Name
00FF24 D7 EK07
D6 EK06
Function
K07 interrupt enable
1
0
SR R/W
Comment
K06 interrupt enable
D5 EK05
K05 interrupt enable
D4 EK04
K04 interrupt enable
Interrupt
enable
Interrupt
disable
0
0
0
R/W
R/W
R/W
D3 EK03
K03 interrupt enable
D2 EK02
K02 interrupt enable
D1 EK01
K01 interrupt enable
D0 EK00
K00 interrupt enable
00FF25 D7 ETC3
D6 ETU3
PTM3 compare match interrupt enable
PTM3 underflow interrupt enable
PTM2 compare match interrupt enable
PTM2 underflow interrupt enable
PTM1 compare match interrupt enable
PTM1 underflow interrupt enable
PTM0 compare match interrupt enable
PTM0 underflow interrupt enable
PTM7 compare match interrupt enable
PTM7 underflow interrupt enable
PTM6 compare match interrupt enable
PTM6 underflow interrupt enable
PTM5 compare match interrupt enable
PTM5 underflow interrupt enable
PTM4 compare match interrupt enable
PTM4 underflow interrupt enable
–
D5 ETC2
D4 ETU2
Interrupt
enable
Interrupt
disable
D3 ETC1
D2 ETU1
D1 ETC0
D0 ETU0
00FF2C D7 ETC7
D6 ETU7
D5 ETC6
D4 ETU6
Interrupt
enable
Interrupt
disable
D3 ETC5
D2 ETU5
D1 ETC4
D0 ETU4
00FF26 D7 –
D6 –
–
–
–
–
–
–
–
–
Constantly "0" when
being read
–
D5 –
–
–
–
D4 –
–
–
–
D3 FTM32 Clock timer 32 Hz interrupt factor flag
(R)
(R)
D2 FTM8
D1 FTM2
D0 FTM1
Clock timer 8 Hz interrupt factor flag
Generated Not generated
0
R/W
Clock timer 2 Hz interrupt factor flag
(W)
(W)
Clock timer 1 Hz interrupt factor flag
Reset
No operation
00FF27 D7 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Constantly "0" when
being read
D6 –
D5 –
D4 –
D3 –
–
–
(R)
(R)
D2 FSERR Serial I/F (error) interrupt factor flag
D1 FSREC Serial I/F (receiving) interrupt factor flag
D0 FSTRA Serial I/F (transmitting) interrupt factor flag
Generated Not generated
(W)
Reset
0
R/W
R/W
(W)
No operation
00FF28 D7 FK07
K07 interrupt factor flag
K06 interrupt factor flag
K05 interrupt factor flag
K04 interrupt factor flag
K03 interrupt factor flag
K02 interrupt factor flag
K01 interrupt factor flag
K00 interrupt factor flag
(R)
(R)
D6 FK06
D5 FK05
D4 FK04
D3 FK03
D2 FK02
D1 FK01
D0 FK00
Interrupt
factor is
generated
No interrupt
factor is
generated
0
(W)
(W)
Reset
No operation
134
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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
Table 5.14.6.1(c) Interrupt control bits
Address Bit Name
00FF29 D7 FTC3
D6 FTU3
Function
1
0
SR R/W
Comment
PTM3 compare match interrupt factor flag
PTM3 underflow interrupt factor flag
PTM2 compare match interrupt factor flag
PTM2 underflow interrupt factor flag
PTM1 compare match interrupt factor flag
PTM1 underflow interrupt factor flag
PTM0 compare match interrupt factor flag
PTM0 underflow interrupt factor flag
PTM7 compare match interrupt factor flag
PTM7 underflow interrupt factor flag
PTM6 compare match interrupt factor flag
PTM6 underflow interrupt factor flag
PTM5 compare match interrupt factor flag
PTM5 underflow interrupt factor flag
PTM4 compare match interrupt factor flag
PTM4 underflow interrupt factor flag
(R)
(R)
Interrupt
factor is
generated
No interrupt
factor is
generated
D5 FTC2
D4 FTU2
0
R/W
D3 FTC1
D2 FTU1
(W)
(W)
D1 FTC0
Reset
No operation
D0 FTU0
00FF2E D7 FTC7
D6 FTU7
(R)
(R)
Interrupt
factor is
generated
No interrupt
factor is
D5 FTC6
D4 FTU6
generated
0
R/W
D3 FTC5
D2 FTU5
(W)
(W)
D1 FTC4
Reset
No operation
D0 FTU4
Refer to the explanations on the respective peripheral circuits for the setting content and control method for each bit.
5.14.7 Programming notes
(3) An exception processing vector is fixed at 2
bytes, so it cannot specify a branch destination
bank address. Consequently, to branch from
multiple banks to a common exception process-
ing routine, the front portion of an exception
processing routine must be described within the
common area (000000H–007FFFH).
(1) When executing the RETE instruction without
resetting the interrupt factor flag after an
interrupt has been generated, the same interrupt
will be generated. Consequently, the interrupt
factor flag corresponding to that routine must
be reset (writing "1") in the interrupt processing
routine.
(2) Beware. If the interrupt flags (I0 and I1) have
been rewritten (set to lower priority) prior to
resetting an interrupt factor flag after an
interrupt has been generated, the same interrupt
will be generated again.
(4) Do not execute the SLP instruction for 2 msec
after a NMI interrupt has occurred (when fOSC1
is 32.768 kHz).
S1C88650 TECHNICAL MANUAL
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6 SUMMARY OF NOTES
6 SUMMARY OF NOTES
Next, which circuit systems' operation can be
6.1 Notes for Low Current
Consumption
The S1C88650 can turn circuits, which consume a
large amount of power, ON or OFF by control
registers.
controlled and their control registers (instructions)
are explained. You should refer to these when
programming.
See Chapter 8, "ELECTRICAL CHARACTERIS-
TICS" for the current consumption.
You can reduce power consumption by creating a
program that operates the minimum necessary
circuits using these control registers.
Refer to "Programming notes" in each peripheral
section for precautions of each peripheral circuit.
Table 6.1.1 Circuit systems and control registers
Control register (Instruction) Status at time of initial resetting
HALT and SLP instructions Operation status
Circuit type
CPU
Oscillation circuit
CLKCHG, SOSC3
OSC3 clock (CLKCHG = "1")
OSC3 oscillation ON (SOSC3 = "1")
OFF status (DBON = "0")
Drive OFF (LCDC0 = LCDC1 = "0")
OFF status (SVDON = "0")
Power voltage booster
LCD controller
SVD circuit
DBON
LCDC0, LCDC1
SVDON
Heavy lord protection
HLMOD
OFF status (HLMOD = "0")
136
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6 SUMMARY OF NOTES
<Power Supply Circuit>
6.2 Precautions on Mounting
<Oscillation Circuit>
● Oscillation characteristics change depending on
conditions (board pattern, components used,
etc.).
● Sudden power supply variation due to noise
may cause malfunction. Consider the following
points to prevent this:
(1) The power supply should be connected to
the VDD and VSS terminal with patterns as
short and large as possible.
In particular, when a ceramic or crystal
oscillator is used, use the oscillator
manufacturer's recommended values for
constants such as capacitance and resistance.
(2) When connecting between the VDD and VSS
terminals with a bypass capacitor, the
terminals should be connected as short as
possible.
● Disturbances of the oscillation clock due to
noise may cause a malfunction. Consider the
following points to prevent this:
Bypass capacitor connection example
(1) Components which are connected to the
OSC1, OSC2, OSC3 and OSC4 terminals,
such as oscillators, resistors and capacitors,
should be connected in the shortest line.
VDD
VSS
VDD
VSS
(2) As shown in the right hand figure, make a
VSS pattern as large as possible at circum-
scription of the OSC1, OSC2, OSC3 and
OSC4 terminals and the components
connected to these terminals.
(3) Components which are connected to the
VD1, VC1, VC2, VC3, VC4 and VC5 terminals,
such as capacitors and resistors, should be
connected in the shortest line.
In particular, the VC1, VC2, VC3, VC4 and VC5
voltages affect the display quality.
Furthermore, do not use this VSS pattern for
any purpose other than the oscillation
system.
<Arrangement of Signal Lines>
● In order to prevent generation of
Sample VSS pattern (OSC3)
electromagnetic induction noise caused by
mutual inductance, do not arrange a large
current signal line near the circuits that are
sensitive to noise such as the oscillation unit.
OSC4
OSC3
VSS
● When a signal line is parallel with a high-speed
line in long distance or intersects a high-speed
line, noise may generated by mutual
interference between the signals and it may
cause a malfunction.
● In order to prevent unstable operation of the
oscillation circuit due to current leak between
OSC1/ OSC3 and VDD, please keep enough
distance between OSC1/ OSC3 and VDD or other
signals on the board pattern.
Do not arrange a high-speed signal line
especially near circuits that are sensitive to
noise such as the oscillation unit.
Prohibited pattern
<Reset Circuit>
OSC4
OSC3
VSS
● The power-on reset signal which is input to the
RESET terminal changes depending on
conditions (power rise time, components used,
board pattern, etc.).
Decide the time constant of the capacitor and
resistor after enough tests have been completed
with the application product.
Large current signal line
High-speed signal line
When the built-in pull-up resistor of the RESET
terminal is used, take into consideration
dispersion of the resistance for setting the
constant.
● In order to prevent any occurrences of unneces-
sary resetting caused by noise during operating,
components such as capacitors and resistors
should be connected to the RESET terminal in
the shortest line.
S1C88650 TECHNICAL MANUAL
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6 SUMMARY OF NOTES
<Precautions for Visible Radiation
(when bare chip is mounted)>
● Visible radiation causes semiconductor devices
to change the electrical characteristics. It may
cause this IC to malfunction. When developing
products which use this IC, consider the
following precautions to prevent malfunctions
caused by visible radiations.
(1) Design the product and implement the IC on
the board so that it is shielded from visible
radiation in actual use.
(2) The inspection process of the product needs
an environment that shields the IC from
visible radiation.
(3) As well as the face of the IC, shield the back
and side too.
138
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S1C88650 TECHNICAL MANUAL
7 BASIC EXTERNAL WIRING DIAGRAM
7 BASIC EXTERNAL WIRING DIAGRAM
LCD panel 126 x 32
VSS
∗2
∗1
CG1
X'tal1
CG2
OSC1
K00–K02
K03 (BREQ)
K04–K07
OSC2
OSC3
∗3
∗4
X'tal2 or
Ceramic
Rf
C1
OSC4
VD1
VC1
VC2
VC3
VC4
VC5
CA
R00–R07 (A0–A7)
R10–R17 (A8–A15)
R20–R23 (A16–A19)
R24 (RD)
CD2
C2
C3
C4
C5
C6
R25 (WR)
R30–R32 (CE0–CE2)
R33 (BACK)
S1C88650
[The potential of the substrate
C7
C8
CB
(back of the chip) is VSS.]
CC
P00–P07 (D0–D7)
P10 (SIN)
CD
C9
CE
P11 (SOUT)
C10
VD2
CF
P12 (SCLK)
P13 (SRDY)
C11
CG
P14 (TOUT0/TOUT1)
P15 (TOUT2/TOUT3)
P16 (FOUT)
RESET
Cres
P17 (TOUT2/TOUT3)
-
+
CP
3 V
VDD
TEST
∗1: OSC1 = Crystal oscillation
∗2: OSC1 = CR oscillation
∗3: OSC3 = Crystal or Ceramic oscillation
∗4: OSC3 = CR oscillation
Recommended values for external parts
Symbol
X'tal1
CG1
Name
Crystal oscillator
Trimmer capacitor
Recommended value
32.768 kHz, CI(Max.) = 35 kΩ
0–25 pF
Symbol
C1
Name
Recommended value
Capacitor between VSS and VD1 0.1 µF
Capacitor between VSS and VC1 0.1 µF
Capacitor between VSS and VC2 0.1 µF
Capacitor between VSS and VC3 0.1 µF
Capacitor between VSS and VC4 0.1 µF
Capacitor between VSS and VC5 0.1 µF
C2
RCR1
Resistor for CR oscillation 1.5 MΩ
Crystal oscillator
C3
X'tal2
4 MHz
C4
Ceramic Ceramic oscillator
4 MHz
C5
Rf
Feedback resistor
Gate capacitor
1 MΩ
C6
CG2
15 pF (Crystal oscillation)
30 pF (Ceramic oscillation)
15 pF (Crystal oscillation)
30 pF (Ceramic oscillation)
C7–C9 Booster capacitors
0.1 µF
C10
C11
CP
Capacitor between VSS and VD2 0.1 µF
Booster capacitor
CD2
Drain capacitor
0.1 µF
3.3 µF
0.47 µF
Capacitor for power supply
Capacitor for RESET terminal
RCR3
Resistor for CR oscillation 40 kΩ
Cres
Note: The above table is simply an example, and is not guaranteed to work.
S1C88650 TECHNICAL MANUAL
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8 ELECTRICAL CHARACTERISTICS
8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Rating
(VSS = 0 V)
Item
Symbol
VDD
Condition
Rated value
Unit Note
Power voltage
-0.3 to +4.7
V
V
Liquid crystal power voltage
Input voltage
VC5
-0.3 to +6.0
VI
-0.3 to VDD + 0.3
V
Output voltage
VO
-0.3 to VDD + 0.3
V
High level output current
IOH
1 terminal
-5
mA
mA
mA
mA
Total of all terminals
1 terminal
-20
5
Low level output current
IOL
Total of all terminals
20
Permitted loss
P
D
200
mW
°C
°C
–
1
Operating temperature
Storage temperature
Topr
Tstg
Tsol
-20 to +70
-65 to +150
(
)
Soldering temperature / time
Note) 1 In case of plastic package.
260°C, 10 sec lead section
8.2 Recommended Operating Conditions
Item
Operating power voltage
Operating frequency
Symbol
Condition
Min.
1.8
Typ.
Max.
3.6
Unit Note
VDD
V
fOSC1
30
32.768
200
2.2
kHz
MHz
MHz
µF
fOSC3 CR oscillation
0.03
0.03
Crystal/ceramic oscillation
8.2
Capacitor between VD1 and VSS
Capacitor between VC1 and VSS
Capacitor between VC2 and VSS
Capacitor between VC3 and VSS
Capacitor between VC4 and VSS
Capacitor between VC5 and VSS
Capacitor between CA and CB
Capacitor between CA and CC
Capacitor between CD and CE
Capacitor between VD2 and VSS
Capacitor between CF and CG
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
7
8
9
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
µF
µF
µF
µF
µF
µF
µF
µF
µF
µF
1
1
1
1
1
1
1
1
1
1
C10
C11
Note) 1 When LCD drive power is not used, the capacitor is not necessary.
In this case, leave the VC1 to VC5 and CA to CG terminals open.
140
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S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
8.3 DC Characteristics
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = -20 to 70°C
Item
Symbol
Condition
Min.
0.8VDD
0
Typ.
Max.
VDD
Unit Note
High level input voltage
VIH
Kxx, Pxx
Kxx, Pxx
V
V
V
V
Low level input voltage
VIL
0.2VDD
0.9VDD
0.5VDD
0.9VDD
0.5VDD
-0.5
High level schmitt input voltage (1)
Low level schmitt input voltage (1)
High level schmitt input voltage (2)
Low level schmitt input voltage (2)
High level output current
Low level output current
Input leak current
VT1+
VT1-
VT2+
VT2-
IOH
RESET, MCU/MPU
RESET, MCU/MPU
Kxx
0.5VDD
0.1VDD
0.5VDD
0.1VDD
V
V
1
1
Kxx
Pxx, Rxx, VOH = 0.9 VDD
Pxx, Rxx, VOL = 0.1 VDD
Kxx, Pxx, RESET, MCU/MPU
Pxx, Rxx
mA
mA
µA
µA
kΩ
pF
IOL
0.5
-1
ILI
1
1
Output leak current
ILO
-1
Input pull-up resistance
RIN
Kxx, Pxx, RESET, MCU/MPU
Kxx, Pxx
100
500
15
2
Input terminal capacitance
CIN
VIN = 0 V, f = 1 MHz, Ta = 25°C
Segment/Common output current
ISEGH SEGxx, COMxx, VSEGH = VC5-0.1 V
-5
µA
ISEGL SEGxx, COMxx, VSEGL = 0.1 V
5
µA
Note) 1 When CMOS Schmitt level is selected by mask option.
2 When addition of pull-up resistor is selected by mask option.
VDD
0
0
V
T-
V
T+
VDD
VIN (V)
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8 ELECTRICAL CHARACTERISTICS
8.4 Analog Circuit Characteristics
■ LCD drive circuit
The typical values in the following LCD driver characteristics varies depending on the panel load (panel
size, number of display pixels and display contents), so evaluate them by connecting to the actually used
LCD panel. Refer to Section 8.8, "Characteristics Curves" for the load characteristic.
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, C1–C11 = 0.1 µF, When a checker pattern is displayed, No panel load
Item
Symbol
Condition
Min.
Typ.
Max.
Unit Note
LCD drive voltage
VC1
*1
*2
*3
*4
*5
0.18•VC5
0.39•VC5
0.59•VC5
0.79•VC5
0.22•VC5
0.43•VC5
0.63•VC5
0.83•VC5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VC2
VC3
VC4
VC5
LCX = 0H
LCX = 1H
LCX = 2H
LCX = 3H
LCX = 4H
LCX = 5H
LCX = 6H
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
5.30
5.40
5.50
5.60
5.70
LCX = 7H Typ×0.94
LCX = 8H
Typ×1.06
LCX = 9H
LCX = AH
LCX = BH
LCX = CH
LCX = DH
LCX = EH
LCX = FH
*1 Connects 1 MΩ load resistor between VSS and VC1.
*2 Connects 1 MΩ load resistor between VSS and VC2.
*3 Connects 1 MΩ load resistor between VSS and VC3.
*4 Connects 1 MΩ load resistor between VSS and VC4.
*5 Connects 1 MΩ load resistor between VSS and VC5.
■ SVD circuit
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C
Item Symbol Condition
Min.
Typ.
–
Max.
Unit Note
SVD voltage
VSVD SVDS0–3 = "0"
SVDS0–3 = "1"
SVDS0–3 = "2"
SVDS0–3 = "3"
SVDS0–3 = "4"
SVDS0–3 = "5"
SVDS0–3 = "6"
SVDS0–3 = "7"
SVDS0–3 = "8"
SVDS0–3 = "9"
SVDS0–3 = "10"
SVDS0–3 = "11"
SVDS0–3 = "12"
SVDS0–3 = "13"
SVDS0–3 = "14"
SVDS0–3 = "15"
tSVD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µs
–
–
1.8
1.85
1.9
1.95
2.0
2.05
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Typ×0.91
Typ×1.09
SVD circuit response time
500
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S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
8.5 Power Current Consumption
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, C1–C11 = 0.1 µF, No panel load
Item
Symbol
Condition
Min. Typ. Max. Unit Note
Current consumption
in SLEEP mode
ISLP
OSC1 = OFF, OSC3 = OFF
1
2.5 µA
Current consumption
in HALT mode
IHALT1 OSC1 = 32kHz Crystal, OSC3 = OFF
IHALT2 OSC1 = 32kHz CR, OSC3 = OFF
2.5
5
µA
10 20 µA
250 450 µA
220 450 µA
IHALT3 OSC1 = 32kHz Crystal, OSC3 = 8MHz Ceramic
IHALT4 OSC1 = 32kHz CR, OSC3 = 2MHz CR
Current consumption
during execution
IEXE1
IEXE2
IEXE3
IEXE4
IHVL1
IHVL2
OSC1 = 32kHz Crystal, OSC3 = OFF
9
16 µA
OSC1 = 32kHz CR, OSC3 = OFF
15 30 µA
1700 3000 µA
600 1200 µA
15 27 µA
20 40 µA
OSC1 = 32kHz Crystal, OSC3 = 8MHz Ceramic
OSC1 = 32kHz CR, OSC3 = 2MHz CR
OSC1 = 32kHz Crystal, OSC3 = OFF, HLMOD = H
OSC1 = 32kHz CR, OSC3 = OFF, HLMOD = H
Current consumption
during execution in heavy
load protection mode
LCD circuit current
ILCD1
LCDCx = All on, LCx = FH, fOSC1 = 32.768kHz,
VDD = 2.5 to 3.6V
5
10 µA
1
2
3
4
LCD circuit current
ILCD1H LCDCx = All on, LCx = FH, fOSC1 = 32.768kHz,
HLMOD = H
15 30 µA
10 20 µA
30 60 µA
in heavy load protection mode
LCD circuit current when the
power voltage booster is active
ILCD2
LCDCx = All on, LCx = FH, fOSC1 = 32.768kHz,
DBON = H, VDD = 1.8 to 2.5V
LCD circuit current in heavy load ILCD2H LCDCx = All on, LCx = FH, fOSC1 = 32.768kHz,
protection mode when the
power voltage booster is active
SVD circuit current
DBON = H, VDD = 1.8 to 2.5V, HLMOD = H
ISVD
SVDON = ON
5
10 µA
5
Note) 1 This value is added to the current consumption during execution when the LCD circuit is active. Current consumption
increases according to the display contents and panel load.
2 This value is added to the current consumption during execution in heavy load protection mode when the LCD circuit is
active. Current consumption increases according to the display contents and panel load.
3 This value is added to the current consumption during execution when the power voltage booster and the LCD circuit are
active. Current consumption increases according to the display contents and panel load.
4 This value is added to the current consumption during execution in heavy load protection mode when the power voltage
booster and the LCD circuit are active. Current consumption increases according to the display contents and panel load.
5 This value is added to the current consumption during execution or current consumption during execution in heavy load
protection mode when the SVD circuit is active.
S1C88650 TECHNICAL MANUAL
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143
8 ELECTRICAL CHARACTERISTICS
8.6 AC Characteristics
■ Operating range
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = -20 to 70°C
Item
Symbol
fOSC1
fOSC3
tcy
Condition
Min.
30
Typ.
Max.
200
Unit Note
Operating frequency
VDD = 1.8 to 3.6 V
32.768
kHz
MHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
0.03
10
8.2
Instruction execution time
1-cycle instruction
2-cycle instruction
3-cycle instruction
4-cycle instruction
5-cycle instruction
6-cycle instruction
1-cycle instruction
2-cycle instruction
3-cycle instruction
4-cycle instruction
5-cycle instruction
6-cycle instruction
61
67
(during operation with OSC1 clock)
20
122
183
244
305
366
133
30
200
40
267
50
333
60
400
Instruction execution time
tcy
0.24
0.49
0.73
0.98
1.22
1.46
66.7
133.3
200.0
266.7
333.3
400.0
(
during operation with OSC3 clock
)
µs
144
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S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
■ External memory access
• Read cycle
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD, VIH2 = 1.6 V, VIL2 = 0.6 V,
VOH = 0.8VDD, VOL = 0.2VDD, CL = 100 pF (load capacitance)
Item
Symbol
Min.
tc+tl-50+n•tc/2
th-40
tc-10+n•tc/2
150
Typ.
Max.
Unit Note
Address set-up time in read cycle
Address hold time in read cycle
Read signal pulse width
tras
trah
trp
trds
ns
ns
ns
ns
ns
1
1
Data input set-up time in read cycle
Data input hold time in read cycle
trdh
0
Note)
1
Substitute the number of states for wait insertion in n.
• Write cycle
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD, VIH2 = 1.6 V, VIL2 = 0.6 V,
VOH = 0.8VDD, VOL = 0.2VDD, CL = 100 pF (load capacitance)
Item
Symbol
Min.
tc-90
th-40
Typ.
Max.
Unit Note
Address set-up time in write cycle
Address hold time in write cycle
Write signal pulse width
twas
twah
twp
twds
twdh
ns
ns
tl-20+n•tc/2
tc-90+n•tc/2
th-40
ns
ns
ns
1
1
Data output set-up time in write cycle
Data output hold time in write cycle
th+40
Note)
1
Substitute the number of states for wait insertion in n.
*
t
c
VIH2
ICLK
VIL2
*
*
t
h
tl
A00–A19
CE
VOH
VOL
tras
trah
trdh
VOH
VOL
RD
trp
VIH1
trds
DIN
VIL1
A00–A19
CE
VOH
VOL
twas
twah
twdh
VOH
VOL
WR
twp
twds
VIH1
VIL1
DOUT
* In the case of crystal oscillation and ceramic oscillation: th = 0.5tc 0.05tc, tl = tc - th (1/tc: oscillation frequency)
* In the case of CR oscillation: th = 0.5tc 0.10tc, tl = tc - th (1/tc: oscillation frequency)
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8 ELECTRICAL CHARACTERISTICS
■ Serial interface
• Clock synchronous master mode
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD, VOH = 0.8VDD, VOL = 0.2VDD
Item
Symbol
Min.
Typ.
Max.
Unit Note
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
tsmd
tsms
tsmh
100
ns
ns
ns
250
100
• Clock synchronous slave mode
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD, VOH = 0.8VDD, VOL = 0.2VDD
Item
Symbol
Min.
Typ.
Max.
Unit Note
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
tssd
tsss
tssh
250
ns
ns
ns
100
100
• Asynchronous system
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C
Item
Symbol
Min.
0
Typ.
Max.
t/16
10t/16
Unit Note
Start bit detection error time
tsa1
tsa2
s
s
1
2
Erroneous start bit detection range time
9t/16
Note)
1
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
2
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started.
When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit.
(Time as far as AC is excluded.)
VOH
SCLK OUT
VOL
tsmd
VOH
VOL
SOUT
tsms
tsmh
VIH1
VIL1
SIN
VIH1
SCLK IN
VIL1
tssd
VOH
VOL
SOUT
SIN
tsss
tssh
VIH1
VIL1
Start bit
Stop bit
SIN
tsa1
Sampling
clock
t
Erroneous
start bit
detection signal
tsa2
146
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S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
■ Input clock
_________
• SCLK, EXCL input clock
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD
Item
Symbol
Min.
Typ.
Max.
Unit Note
SCLK input clock time
Cycle time
tsccy
2
µs
µs
µs
s
"H" pulse width tsch
"L" pulse width tscl
Cycle time
tevcy
"H" pulse width tevh
"L" pulse width tevl
Cycle time
tevcy
1
1
EXCL input clock time
(with noise rejecter)
64/fOSC1
32/fOSC1
s
32/fOSC1
s
EXCL input clock time
(without noise rejecter)
2
1
1
µs
µs
µs
ns
ns
"H" pulse width tevh
"L" pulse width tevl
Input clock rising time
Input clock falling time
tckr
tckf
25
25
tsccy
tckf
tckr
VIH1
VIL1
SCLK
tscl
tsch
tevcy
tckf
tckr
VIH1
VIL1
EXCL
tevl
tevh
___________
• RESET input clock
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C, VIH = 0.5VDD, VIL = 0.1VDD
Item
Symbol
Min.
Typ.
Max.
Unit Note
RESET input time
tsr
100
µs
tsr
VIH
RESET
VIL
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8 ELECTRICAL CHARACTERISTICS
■ Power ON reset using an external capacitor
Condition: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C
Item
Operating power voltage
RESET input time
Symbol
Min.
1.8
Typ.
Max.
Unit Note
Vsr
V
tpsr
10
ms
Vsr
VDD
tpsr
0.5VDD
0.1VDD
RESET
Power ON
VDD
*1
RESET
VSS
*1 Because the potential of the RESET terminal not reached VDD level or higher.
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8 ELECTRICAL CHARACTERISTICS
8.7 Oscillation Characteristics
Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the
following characteristics as reference values. In particular, when a ceramic oscillator or crystal oscillator is
used for OSC3, use the oscillator manufacturer’s recommended values for constants such as capacitance
and resistance. The oscillation start time is important because it becomes the wait time when OSC3 clock is
used. (If OSC3 is used as CPU clock before oscillation stabilizes, the CPU may malfunction.)
■ OSC1 (Crystal)
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C,
Crystal oscillator = Q12C2000 (Ri = 30 kΩ Typ.)*, CG1 = 25 pF, CD1 = Built-in
Item
Symbol
tsta
Condition
Min.
5
Typ.
Max.
3
Unit Note
Oscillation start time
s
pF
External gate capacitance
Built-in drain capacitance
Frequency/IC deviation
Frequency/power voltage deviation
Frequency adjustment range
CG1
Including board capacitance
In case of the chip
25
CD1
10
pF
∂
∂
∂
f/
f/
f/
∂
∂
∂
IC VDD = constant
-10
25
10
1
ppm
ppm/V
ppm
V
C
G
VDD = constant, CG = 5 to 25 pF
*
Q12C2000 Made by Seiko Epson corporation
■ OSC1 (CR)
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C
Item
Oscillation start time
Frequency/IC deviation
Symbol
Condition
Min.
Typ.
Max.
100
25
Unit Note
tsta
µs
%
∂
f/
∂
IC RCR = constant
-25
■ OSC3 (Crystal)
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C,
Crystal oscillator = Q21CA301*, RF = 1 MΩ, CG2 = CD2 = 15 pF
Item
Symbol
Condition
Min.
Typ.
Max.
Unit Note
Oscillation start time
tsta
10
ms
1
*
1
Q21CA301 Made by Seiko Epson corporation
Note)
The crystal oscillation start time changes by the crystal oscillator to be used, CG2 and CD2.
■ OSC3 (Ceramic)
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C,
Ceramic oscillator = KBR-4.0MSB/KBR-8.0MSB*, RF = 1 MΩ, CG2 = CD2 = 30 pF
Item
Oscillation start time
Symbol
Condition
Min.
Typ.
Max.
Unit Note
ms
tsta
1
1
*
1
KBR-4.0MSB/KBR-8.0MSB Made by Kyocera
Note)
The ceramic oscillation start time changes by the ceramic oscillator to be used, CG2 and CD2.
■ OSC3 (CR)
Unless otherwise specified: VDD = 1.8 to 3.6 V, VSS = 0 V, Ta = 25°C
Item
Oscillation start time
Frequency/IC deviation
Symbol
Condition
Min.
Typ.
Max.
100
25
Unit Note
tsta
µs
%
∂
f/
∂
IC RCR = constant
-25
S1C88650 TECHNICAL MANUAL
EPSON
149
8 ELECTRICAL CHARACTERISTICS
8.8 Characteristics Curves (reference value)
■ High level output current-voltage characteristic
VDD–VOH [V]
Ta = 70°C, Max. value
0.8 1.0
0.0
0.2
0.4
0.6
0
-3
-6
VDD = 1.8 V
-9
-12
-15
VDD = 3.6 V
VDD = 2.4 V
■ Low level output current-voltage characteristic
Ta = 70°C, Min. value
VDD = 1.8 V
15
VDD = 3.6 V
VDD = 2.4 V
12
9
6
3
0
0.0
0.1
0.2
0.3
VOL [V]
0.4
0.5
0.6
150
EPSON
S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
■ LCD drive voltage-supply voltage characteristic
(when the power voltage booster is not used)
Connects 1 MΩ load resistor between VSS and VC5. (no panel load)
Ta = 25°C, Typ. value
7.0
6.0
5.0
4.0
3.0
2.0
LCx = FH
LCx = 0H
1.5
2.0
2.5
3.0
3.5
4.0
VDD [V]
■ LCD drive voltage-supply voltage characteristic
(when the power voltage booster is used)
Connects 1 MΩ load resistor between VSS and VC5. (no panel load)
Ta = 25°C, Typ. value
7.0
6.0
5.0
4.0
3.0
2.0
LCx = FH
LCx = 0H
1.5
1.8
2.1
2.4
2.7
3.0
VDD [V]
S1C88650 TECHNICAL MANUAL
EPSON
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8 ELECTRICAL CHARACTERISTICS
■ LCD drive voltage-ambient temperature characteristic
Typ. value
1.05VC5
1.04VC5
1.03VC5
1.02VC5
1.01VC5
1.00VC5
0.99VC5
0.98VC5
0.97VC5
0.96VC5
0.95VC5
-50
-25
0
25
50
75
100
Ta [°C]
■ LCD drive voltage-load characteristic
Ta = 25°C, Typ. value, LCx = 8H
5.30
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
0
4
8
12
16
20
-IVC5 [µA]
152
EPSON
S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
■ SVD voltage-ambient temperature characteristic
Typ. value, SVDSx = FH
1.05VSVD
1.04VSVD
1.03VSVD
1.02VSVD
1.01VSVD
1.00VSVD
0.99VSVD
0.98VSVD
0.97VSVD
0.96VSVD
0.95VSVD
-50
-25
0
25
50
75
100
Ta [°C]
S1C88650 TECHNICAL MANUAL
EPSON
153
8 ELECTRICAL CHARACTERISTICS
■ In HALT status current consumption temperature characteristic
(During operation with OSC1) <Crystal oscillation, fOSC1 = 32.768 kHz>
Typ. value
8
6
4
2
0
-50
-25
0
25
50
75
100
Ta [°C]
■ In HALT status current consumption resistor characteristic
(During operation with OSC1) <CR oscillation>
Ta = 25°C
60
50
40
30
20
Max.
10
Typ.
0
100
1000
10000
RCR1 [kΩ]
154
EPSON
S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
■ In executed status current consumption temperature characteristic
(During operation with OSC1) <Crystal oscillation, fOSC1 = 32.768 kHz>
Typ. value
16
12
8
4
0
-50
-25
0
25
50
75
100
Ta [°C]
■ In executed status current consumption resistor characteristic
(During operation with OSC1) <CR oscillation>
Ta = 25°C
160
140
120
100
80
60
40
Max.
Typ.
20
0
100
1000
10000
RCR1 [kΩ]
S1C88650 TECHNICAL MANUAL
EPSON
155
8 ELECTRICAL CHARACTERISTICS
■ In executed status current consumption frequency characteristic
(During operation with OSC3) <Crystal oscillation/Ceramic oscillation>
Ta = 25°C
4000
3500
3000
2500
2000
1500
1000
500
Max.
Typ.
0
0.0
2.0
4.0
6.0
8.0
10.0
fOSC3 [MHz]
■ In executed status current consumption resistor characteristic
(During operation with OSC3) <CR oscillation>
Ta = 25°C
1800
1600
1400
1200
1000
800
600
400
200
0
Max.
Typ.
10
100
1000
RCR3 [kΩ]
156
EPSON
S1C88650 TECHNICAL MANUAL
8 ELECTRICAL CHARACTERISTICS
■ Oscillation frequency resistor characteristic (OSC1) <CR oscillation>
Ta = 25°C, Typ. value
1000
100
10
100
1000
10000
RCR1 [kΩ]
■ Oscillation frequency temperature characteristic (OSC1) <CR oscillation>
Typ. value, RCR1 = 1500 kΩ
1000
100
10
-50
-25
0
25
50
75
100
Ta [°C]
S1C88650 TECHNICAL MANUAL
EPSON
157
8 ELECTRICAL CHARACTERISTICS
■ Oscillation frequency resistor characteristic (OSC3) <CR oscillation>
Ta = 25°C, Typ. value
10000
1000
100
10
10
100
1000
RCR3 [kΩ]
■ Oscillation frequency temperature characteristic (OSC3) <CR oscillation>
Typ. value, RCR3 = 40 kΩ
10000
1000
100
-50
-25
0
25
50
75
100
Ta [°C]
158
EPSON
S1C88650 TECHNICAL MANUAL
9 PACKAGE
9 PACKAGE
9.1 Plastic Package
QFP22-256pin
(Unit: mm)
0.4
0.1
30
28
192
129
193
128
INDEX
256
65
1
64
+0.05
–0.03
0.4
0.16
+0.05
–0.025
0.125
0°
10°
0.2
0.5
1
S1C88650 TECHNICAL MANUAL
EPSON
159
9 PACKAGE
9.2 Ceramic Package for Test Samples
50.8
PGA-256pin
(Unit: mm)
A
B
C
D
E
F
G
H
J
INDEX
Extra pin
K
L
Bottom View
M
N
P
R
T
U
V
W
Y
2019181716151413121110 9
8
7
6
5
4
3
2
1
φ0.46±0.05
2.54
Pin No.
Pin name
N.C.
N.C.
VDD
OSC3
OSC4
VSS
VD1
OSC1
Pin No.
Pin name
R20/A16
R21/A17
R22/A18
R23/A19
R24/RD
R25/WR
R30/CE0
R31/CE1
VDD
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
R32/CE2
R33/BACK
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
Pin No.
Pin name
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
VSS
Pin No.
Pin name
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
N.C.
Pin No.
Pin name
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
VD2
CG
CF
CE
CD
CC
CB
CA
VC5
VC4
VC3
VC2
VC1
N.C.
N.C.
N.C.
–
1
A1
53
U1
P4
105 Y14
106 U12
107 W14
108 V12
109 Y15
110 V13
111 W15
112 U13
113 Y16
114 V14
115 W16
116 V15
117 Y17
118 U14
119 W17
120 V16
121 Y18
122 U15
123 W18
124 V17
125 Y19
126 U16
127 W19
128 V18
129 Y20
130 U17
131 V19
132 U18
133 W20
134 T17
135 U19
136 T18
137 V20
138 R17
139 T19
140 R18
141 U20
142 P17
143 R19
144 P18
145 T20
146 N17
147 P19
148 N18
149 R20
150 M18
151 N19
152 M17
153 P20
154 M19
155 N20
156 L18
157 M20
158 L17
159 L20
160 L19
161 K20
162 K19
163 J20
164 K17
165 H20
166 K18
167 H19
168 J19
169 G20
170 J17
171 G19
172 J18
173 F20
174 H18
175 F19
176 H17
177 E20
178 G18
179 E19
180 F18
181 D20
182 G17
183 D19
184 E18
185 C20
186 F17
187 C19
188 D18
189 B20
190 E17
191 B19
192 C18
193 A20
194 D17
195 B18
196 C17
197 A19
198 D16
199 B17
200 C16
201 A18
202 D15
203 B16
204 C15
205 A17
206 D14
207 B15
208 C14
209 A16
210 D13
211 B14
212 C13
213 A15
214 C12
215 B13
216 D12
217 A14
218 B12
219 A13
220 C11
221 A12
222 D11
223 A11
224 B11
225 A10
226 B10
227 A9
228 D10
229 A8
230 C10
231 B8
232 B9
233 A7
234 D9
235 B7
236 C9
237 A6
238 C8
239 B6
240 D8
241 A5
242 C7
243 B5
244 C6
245 A4
246 D7
247 B4
248 C5
249 A3
250 D6
251 B3
252 C4
253 A2
254 D5
255 B2
256 C3
2
3
4
5
6
7
8
9
D4
C2
D3
B1
E4
D2
E3
C1
F4
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
U2
T3
V1
R4
V2
U3
W1
T4
OSC2
TEST
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
E2
F3
D1
G4
F2
G3
E1
H4
G2
H3
RESET
MPU/MPU
K07/EXCL3
K06/EXCL2
K05/EXCL1
K04/EXCL0
K03/BREQ
K02
W2
V3
Y1
U4
W3
V4
Y2
U5
W4
V5
Y3
U6
W5
V6
Y4
U7
W6
V7
Y5
U8
W7
V8
Y6
V9
W8
U9
Y7
W9
Y8
K01
K00
F1 P17/TOUT2/TOUT3 73
J3 P16/FOUT 74
H2 P15/TOUT2/TOUT3 75
J4 P14/TOUT0/TOUT1 76
G1
J2
H1
K3
J1
K4
K1
K2
L1
L2
M1
L4
N1
L3
N2
M2
P1
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
P13/SRDY
P12/SCLK
P11/SOUT
P10/SIN
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
P02/D2
P01/D1
P00/D0
N.C.
N.C.
N.C.
N.C.
R00/A0
R01/A1
R02/A2
R03/A3
R04/A4
R05/A5
R06/A6
R07/A7
R10/A8
R11/A9
R12/A10
R13/A11
R14/A12
R15/A13
R16/A14
R17/A15
VSS
92 V10
93 Y9
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
M4
P2
94 U10
95 Y10
96 W10
97 Y11
98 W11
99 Y12
100 U11
101 Y13
102 V11
103 W13
104 W12
SEG9
M3
R1
N3
R2
N4
T1
P3
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
–
–
–
–
–
–
–
–
–
–
–
T2
R3
160
EPSON
S1C88650 TECHNICAL MANUAL
10 PAD LAYOUT
10 PAD LAYOUT
10.1 Diagram of Pad Layout
55
50
45
40
35
30
25
20
15
10
5
1
60
235
230
225
220
215
210
205
200
195
190
185
180
65
70
75
80
Y
85
X
90
(0, 0)
95
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
Die. No.
6.7 mm
Chip thickness: 400 µm
Pad opening: 90 µm
■ Pad 119 is used for the IC shipment test, so you should not bond it.
S1C88650 TECHNICAL MANUAL
EPSON
161
10 PAD LAYOUT
10.2 Pad Coordinates
(Unit: mm)
Coordinates
Pad
Name
Coordinates
Pad
Name
Coordinates
Pad
Name
Coordinates
Pad
Name
No.
1
X
Y
No.
X
Y
No.
X
Y
No.
X
Y
VDD
2.900
2.800
2.700
2.600
2.500
2.400
2.300
2.200
2.100
2.000
1.900
1.800
1.700
1.600
1.500
1.400
1.300
1.200
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
60 VSS
-3.232
-3.232
2.907 119 TEST
2.807 120 SEG39
2.707 121 SEG40
2.607 122 SEG41
2.507 123 SEG42
2.407 124 SEG43
2.307 125 SEG44
2.207 126 SEG45
2.107 127 SEG46
2.007 128 SEG47
1.907 129 SEG48
1.807 130 SEG49
1.707 131 SEG50
1.607 132 SEG51
1.507 133 SEG52
1.407 134 SEG53
1.307 135 SEG54
1.207 136 SEG55
1.107 137 SEG56
0.994 138 SEG57
0.894 139 SEG58
0.794 140 SEG59
0.694 141 SEG60
0.594 142 SEG61
0.494 143 SEG62
0.394 144 SEG63
0.294 145 SEG64
0.194 146 SEG65
0.094 147 SEG66
-2.900 -3.232 178 VSS
-2.800 -3.232 179 SEG97
-2.700 -3.232 180 SEG98
-2.600 -3.232 181 SEG99
-2.500 -3.232 182 SEG100
-2.400 -3.232 183 SEG101
-2.300 -3.232 184 SEG102
-2.200 -3.232 185 SEG103
-2.100 -3.232 186 SEG104
-2.000 -3.232 187 SEG105
-1.900 -3.232 188 SEG106
-1.800 -3.232 189 SEG107
-1.700 -3.232 190 SEG108
-1.600 -3.232 191 SEG109
-1.500 -3.232 192 SEG110
-1.400 -3.232 193 SEG111
-1.300 -3.232 194 SEG112
-1.200 -3.232 195 SEG113
-1.100 -3.232 196 SEG114
-1.000 -3.232 197 SEG115
-0.900 -3.232 198 SEG116
-0.800 -3.232 199 SEG117
-0.700 -3.232 200 SEG118
-0.600 -3.232 201 SEG119
-0.500 -3.232 202 SEG120
-0.400 -3.232 203 SEG121
-0.300 -3.232 204 SEG122
-0.200 -3.232 205 SEG123
-0.100 -3.232 206 SEG124
0.000 -3.232 207 SEG125
0.100 -3.232 208 COM31
0.200 -3.232 209 COM30
0.300 -3.232 210 COM29
0.400 -3.232 211 COM28
0.500 -3.232 212 COM27
0.600 -3.232 213 COM26
0.700 -3.232 214 COM25
0.800 -3.232 215 COM24
0.900 -3.232 216 COM23
1.000 -3.232 217 COM22
1.100 -3.232 218 COM21
1.200 -3.232 219 COM20
1.300 -3.232 220 COM19
1.400 -3.232 221 COM18
1.500 -3.232 222 COM17
1.600 -3.232 223 COM16
1.700 -3.232 224 VD2
3.232 -2.907
3.232 -2.807
3.232 -2.707
3.232 -2.607
3.232 -2.507
3.232 -2.407
3.232 -2.307
3.232 -2.207
3.232 -2.107
3.232 -2.007
3.232 -1.907
3.232 -1.807
3.232 -1.707
3.232 -1.607
3.232 -1.507
3.232 -1.407
3.232 -1.307
3.232 -1.207
3.232 -1.107
3.232 -1.007
3.232 -0.907
3.232 -0.807
3.232 -0.707
3.232 -0.607
3.232 -0.507
3.232 -0.407
3.232 -0.307
3.232 -0.207
3.232 -0.107
3.232 -0.007
2
OSC3
OSC4
VSS
61 R32/CE2
3
62 R33/BACK -3.232
4
63 COM0
64 COM1
65 COM2
66 COM3
67 COM4
68 COM5
69 COM6
70 COM7
71 COM8
72 COM9
73 COM10
74 COM11
75 COM12
76 COM13
77 COM14
78 COM15
79 SEG0
80 SEG1
81 SEG2
82 SEG3
83 SEG4
84 SEG5
85 SEG6
86 SEG7
87 SEG8
88 SEG9
89 SEG10
90 SEG11
91 SEG12
92 SEG13
93 SEG14
94 SEG15
95 SEG16
96 SEG17
97 SEG18
98 SEG19
99 SEG20
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
-3.232
5
VD1
6
OSC1
OSC2
TEST
7
8
9
RESET
10 MCU/MPU
11 K07/EXCL3
12 K06/EXCL2
13 K05/EXCL1
14 K04/EXCL0
15 K03/BREQ
16 K02
17 K01
18 K00
19 P17/TOUT2/TOUT3 1.100
20 P16/FOUT 1.000
21 P15/TOUT2/TOUT3 0.900
22 P14/TOUT0/TOUT1 0.800
23 P13/SRDY
24 P12/SCLK
25 P11/SOUT
26 P10/SIN
27 P07/D7
28 P06/D6
29 P05/D5
30 P04/D4
31 P03/D3
32 P02/D2
33 P01/D1
34 P00/D0
35 R00/A0
36 R01/A1
37 R02/A2
38 R03/A3
39 R04/A4
40 R05/A5
41 R06/A6
42 R07/A7
43 R10/A8
44 R11/A9
45 R12/A10
46 R13/A11
47 R14/A12
48 R15/A13
49 R16/A14
50 R17/A15
51 R20/A16
52 R21/A17
53 R22/A18
54 R23/A19
55 R24/RD
56 R25/WR
57 R30/CE0
58 R31/CE1
59 VDD
0.700
0.600
0.500
0.400
0.300
0.200
0.100
0.000
-3.232 -0.007 148 SEG67
-3.232 -0.107 149 SEG68
-3.232 -0.207 150 SEG69
-3.232 -0.307 151 SEG70
-3.232 -0.407 152 SEG71
-3.232 -0.507 153 SEG72
-3.232 -0.607 154 SEG73
-3.232 -0.707 155 SEG74
-3.232 -0.807 156 SEG75
-3.232 -0.907 157 SEG76
-3.232 -1.007 158 SEG77
-3.232 -1.107 159 SEG78
-3.232 -1.207 160 SEG79
-3.232 -1.307 161 SEG80
-3.232 -1.407 162 SEG81
-3.232 -1.507 163 SEG82
-3.232 -1.607 164 SEG83
-3.232 -1.707 165 SEG84
-3.232 -1.807 166 SEG85
-3.232 -1.907 167 SEG86
-3.232 -2.007 168 SEG87
-3.232 -2.107 169 SEG88
-3.232 -2.207 170 SEG89
-3.232 -2.307 171 SEG90
-3.232 -2.407 172 SEG91
-3.232 -2.507 173 SEG92
-3.232 -2.607 174 SEG93
-3.232 -2.707 175 SEG94
-3.232 -2.807 176 SEG95
-3.232 -2.907 177 SEG96
-0.100
-0.200
-0.300
-0.400
-0.500
-0.600
-0.700
-0.800
-0.900
-1.000
-1.100
-1.200
-1.300
-1.400
-1.500
-1.600
-1.700
-1.800
-1.900
-2.000
-2.100
-2.200
-2.300
-2.400
-2.500
-2.600
-2.700
-2.800
-2.900
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
3.232
0.107
0.207
0.307
0.407
0.507
0.607
0.707
0.807
0.907
1.007
1.107
1.207
1.307
1.407
1.507
1.607
1.707
1.807
1.907
2.007
2.107
2.207
2.307
2.407
2.507
2.607
2.707
2.807
2.907
3.232 100 SEG21
3.232 101 SEG22
3.232 102 SEG23
3.232 103 SEG24
3.232 104 SEG25
3.232 105 SEG26
3.232 106 SEG27
3.232 107 SEG28
3.232 108 SEG29
3.232 109 SEG30
3.232 110 SEG31
3.232 111 SEG32
3.232 112 SEG33
3.232 113 SEG34
3.232 114 SEG35
3.232 115 SEG36
3.232 116 SEG37
3.232 117 SEG38
3.232 118 VSS
1.800 -3.232 225 CG
1.900 -3.232 226 CF
2.000 -3.232 227 CE
2.100 -3.232 228 CD
2.200 -3.232 229 CC
2.300 -3.232 230 CB
2.400 -3.232 231 CA
2.500 -3.232 232 VC5
2.600 -3.232 233 VC4
2.700 -3.232 234 VC3
2.800 -3.232 235 VC2
2.900 -3.232 236 VC1
162
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S1C88650 TECHNICAL MANUAL
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL
(Peripheral Circuit Board for S1C88650)
This manual describes how to use the Peripheral Circuit Board for S1C88650 (S5U1C88000P1&S5U1C88649P2).
This circuit board is used to provide emulation functions when it is installed in the ICE (S5U1C88000H5),
a debugging tool for the 8-bit Single Chip Microcomputer S1C88 Family.
The explanation assumes that the S1C88650 circuit data has been downloaded into the S1C88 Family
Peripheral Circuit Board (S5U1C88000P1).
Refer to the "S5U1C88000P Manual" for how to download circuit data into the S1C88 Family Peripheral
Circuit Board (S5U1C88000P1) and common specifications of the board. For details on ICE functions and
how to operate the debugger, refer to the separately prepared manuals.
A.1 Names and Functions of Each Part
The following explains the names and functions of each part of the S5U1C88000P1&S5U1C88649P2.
SW1
(1)
LCDVCC
(on the back)
I/O #3 connector
I/O #4 connector
I/O #1 connector
I/O #2 connector
(26)
(26)
(2)
(26)
(26)
Main board (S5U1C88000P1)
Add-on board (S5U1C88649P2)
Fig. A.1.1 Board layout
(3) (4) (5) (6) (7) (8) (9)
(26)
OSC1
OSC3
L
VLCD VSVD
H
L
H
RESET
S5U1C88000P1
S1C88 Family Peripheral circuit board
EPSON
LED
1
9
2
3
4
5
6
7
8
10 11 12 13 14 15 16
MONITOR
I/O #1
I/O #2
(10–24)
(25)
(26)
Fig. A.1.2 Panel layout (S5U1C88000P1)
S1C88650 TECHNICAL MANUAL
EPSON
163
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
(1) SW1
When downloading circuit data, set this switch
(11) LED 2 (BUSMOD), LED 3 (CPUMOD)
Indicates the bus and CPU modes (BUSMOD/
CPUMOD register settings).
to the "3" position. Otherwise, set to position "1".
Table A.1.2 Bus and CPU modes
(2) LCDVCC (on the back of the S5U1C88000P1 board)
The internal power voltage (VC5) for the LCD
driver can be varied using the DIP switch as
shown in Table A.1.1. Be aware that the VC5
voltage level on this board is different from
that of the actual IC.
BUSMOD CPUMOD
Bus mode
CPU mode
Maximum
Minimum
Maximum
Minimum
Lit
Lit
Not lit
Not lit
Lit
Not lit
Lit
Expansion
Single chip
Not lit
(12) LED 4 (CLKCHG)
Indicates the CPU operating clock.
Lit: OSC3 (CLKCHG register = "1")
Table A.1.1 Setting LCDVCC
LCDVCC
Setting
1
2
3
4
ON OFF OFF ON
OFF ON OFF OFF
OFF OFF ON OFF
OFF OFF OFF ON
Other combinations
VC5 = 6 V
VC5 = 5.75 V
VC5 = 5.5 V
VC5 = 5 V
Not lit: OSC1 (CLKCHG register = "0")
(13) LED 5 (SOSC3)
Indicates the OSC3 oscillation status.
Not allowed
Lit:
OSC3 oscillation is on
(SOSC3 register = "1")
∗ The voltage value assumes that the LCD
contrast adjustment register LC0–LC3 is
0FH. There is a need to allow for a maximum
±6% of error due to the characteristics of the
parts used on this board.
Not lit: OSC3 oscillation is off
(SOSC3 register = "0")
(14) LED 6 (SVDON)
Indicates the SVD circuit status.
(3) VLCD control
Lit:
SVD circuit is on
Unused.
(SVDON register = "1")
Not lit: SVD circuit is off
(SVDON register = "0")
(4) VSVD control
This control is used for varying the power
supply voltage to confirm the supply voltage
detection (SVD) function. (Refer to Section
A.2.2, "Differences from Actual IC".)
(15) LED 7 (LCDC)
Indicates the LCD circuit status.
Lit:
LCD circuit is on
(LCDC register = Not "00")
Not lit: LCD circuit is off
(LCDC register = "00")
(5) OSC1 H control
This control is used for coarse adjustment of
the OSC1 CR oscillation frequency.
(16) LED 8 (HLMOD)
(6) OSC1 L control
Indicates the heavy load protection status.
This control is used for fine adjustment of the
OSC1 CR oscillation frequency.
Lit:
Heavy load protection mode
(HLMOD register = "1")
Not lit: Normal mode
(HLMOD register = "0")
(7) OSC3 H control
This control is used for coarse adjustment of
the OSC3 CR oscillation frequency.
(17) LED 9 (HALT/SLEEP)
Indicates the CPU status.
(8) OSC3 L control
Lit:
HALT or SLEEP
This control is used for fine adjustment of the
OSC3 CR oscillation frequency.
Not lit: RUN
(18) LED 10 (VDSEL)
(9) RESET switch
Indicates the power voltage (VDD or VD2)
selected for the LCD system voltage regulator.
This switch initializes the internal circuits of
this board and feeds a reset signal to the ICE.
Lit:
VD2 (VDSEL register = "1")
Not lit: VDD (VDSEL register = "0")
(10) LED 1 (MPU/MCU)
Indicates the MPU or MCU mode.
(19) LED 11 (DBON)
Lit:
MPU mode
Indicates the status of the power voltage booster.
Not lit: MCU mode
Lit:
ON (DBON register = "1")
Not lit: OFF (DBON register = "0")
(20) LED 12 (SEGREV)
Indicates the SEG output assignment status.
Lit:
Reverse (SEGREV register = "1")
Not lit: Normal (SEGREV register = "0")
164
EPSON
S1C88650 TECHNICAL MANUAL
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
(21) LED 13 (Reserved)
A.2 Precautions
Unused.
Take the following precautions when using the
S5U1C88000P1&S5U1C88649P2.
(22) LED 14 (OSC1 operating clock)
The OSC1 operating clock is connected to this
LED. The corresponding monitor pin (pin 14)
can be used to check the OSC1 clock frequency.
A.2.1 Precaution for operation
(1) Turn the power of all equipment off before
connecting or disconnecting cables.
(23) LED 15 (OSC3 operating clock)
The OSC3 operating clock is connected to this
LED. The corresponding monitor pin (pin 15)
can be used to check the OSC3 clock frequency.
(2) Make sure that the input ports (K00–K03) are
not all set to low when turning the power on
until the mask option data is loaded, as the
key-entry reset function may activated.
(24) LED 16 (FPGA configuration)
If the FPGA on the S5U1C88000P1 includes
circuit data, this LED lights when the power is
turned on. If this LED does not light at power-
up, a circuit data must be written to the FPGA
before debugging can be started (turn the
power on again after writing data).
(3) The mask option data must be loaded before
debugging can be started.
A.2.2 Differences from actual IC
Caution is called for due to the following function
and property related differences with the actual
IC. If these precautions are overlooked, it may not
operate on the actual IC, even if it operates on the
ICE in which the S5U1C88000P1&S5U1C88649P2
has been installed.
(25) LED signal monitor connector
This connector provides the signals that drive the
LEDs shown above for monitoring. The signals
listed below are output from the connector pins.
The signal level is high when the LED is lit and is
low when the LED is not lit.
(1) I/O differences
19 17 15 13 11 9
7
5
3
1
Interface power voltage
This board and target system interface voltage
is set to +3.3 V. To obtain the same interface
voltage as in the actual IC, attach a level shifter
or similar circuit on the target system side to
accommodate the required interface voltage.
20 18 16 14 12 10 8
6
4
2
Fig. A.1.3 LED signal monitor connector
Pin 1: LED 1 (MPU/ MCU mode)
Pin 2: LED 2 (Bus mode 1)
Pin 3: LED 3 (CPU mode 0)
Drive capability of each output port
Pin 4: LED 4 (CPU operating clock)
Pin 5: LED 5 (OSC3 oscillation status)
Pin 6: LED 6 (SVD circuit status)
Pin 7: LED 7 (LCD circuit status)
Pin 8: LED 8 (Heavy load protection status)
Pin 9: LED 9 (HALT/ SLEEP, RUN status)
Pin 10: LED 10 (LCD voltage regulator power status
Pin 11: LED 11 (Power voltage booster status)
Pin 12: LED 12 (SEG output assignment status)
Pin 14: OSC1 operating clock
The drive capability of each output port on this
board is higher than that of the actual IC.
When designing the application system and
software, refer to Chapter 8, "ELECTRICAL
CHARACTERISTICS" to confirm the drive
capability of each output port.
)
Input port characteristics
The AC characteristic of the input terminal is
different from that of the actual IC and it
affects the input interrupt function. Therefore,
evaluate the operation in the actual IC if the
rise/ fall time of the input signal is long.
Pin 15: OSC3 operating clock
Pin 18: OSC1 CR oscillation frequency monitor pin
Pin 19: OSC3 CR oscillation frequency monitor pin
Pins 13 , 17 and 20 are not used.
Protective diode of each port
The OSC3 CR oscillation clock is connected to
pins 18 and 19. (The CR oscillation circuit on
this board always operates even if crystal
oscillation is selected by mask option and
regardless of the SOSC3 register status.) These
pins can be used to monitor CR oscillation
when adjusting the oscillation frequency.
All I/ O ports incorporate a protective diode
for VDD and VSS, and the interface signals
between this board and the target system are
set to +3.3 V. Therefore, this board and the
target system cannot be interfaced with a
voltage exceeding VDD even if the output ports
are configured with open-drain output.
(26) I/O #1, I/O #2, I/O #3, I/O #4 connectors
These are the connectors for connecting the I/
O and LCD. The I/ O cables (80-pin/ 40-pin × 2
flat type, 100-pin/ 50-pin × 2 flat type, 40-pin/
20-pin × 2 flat type) are used to connect to the
target system.
S1C88650 TECHNICAL MANUAL
EPSON
165
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
Pull-up resistance value
(3) Functional precautions
The pull-up resistance values on this board are
set to 300 kΩ which differ from those for the
actual IC. For the resistance values on the
actual IC, refer to Chapter 8, "ELECTRICAL
CHARACTERISTICS".
Note that when using pull-up resistors to pull
the input terminals high, the input terminals
may require a certain period to reach a valid
high level. Exercise caution if a key matrix
circuit is configured using a combination of
output and input ports, since rise delay times
on these input ports differ from those of the
actual IC.
LCD circuit
• Pay attention to the output drive capability
and output voltage of the LCD terminals (SEG,
COM), since they are different from those of
the actual IC. The system and the software
should be designed in order to adjust the LCD
contrast. The S5U1C88000P1 board allows
switching of the LCD drive voltage with its
switch on the back side. (Refer to Section A.1,
"Names and Functions of Each Part")
• When the LCDC0 and LCDC1 registers are
both set to "0" (LCD power control circuit is
off), the SEG and COM terminal outputs of the
actual IC are fixed at VSS level. Note, however,
that the COM outputs are fixed at VC4 level
and the SEG outputs are fixed at VC3 level in
this board.
(2) Differences in current consumption
The amount of current consumed by this board
differs significantly from that of the actual IC.
Inspecting the LEDs on the S5U1C88000P1
front panel may help keep track of approxi-
mate current consumption. The following
factors/ components greatly affect device
current consumption:
• This board supports 16 × 16/ 5 × 8 dot font only
and 12 × 12 dot font can not be used. (Writing
and reading to/ from DTFNT bit are enabled.)
• This board does not support reversing of the
SEG assignment using the SEGREV bit. Check
whether LED12 is lit or not to confirm the
SEGREV status. (Writing and reading to/ from
SEGREV bit are enabled.)
Those which can be verified by LEDs
and monitor pins
a) Run and Halt execution ratio
(verified by LEDs and monitor pins on the
ICE)
• The actual IC outputs only COM0 to COM15
signals even if the display area is switched
(DSPAR = "1") when the LCD driver is set to
1/ 16 (0r 1/ 8) duty drive. This board outputs
COM16 to COM31 signals with the same
waveform as the COM0 to COM15. Therefore,
if COM16 to COM31 along with COM0 to
COM15 are connected to the LCD panel, the
LCD panel displays the same contents twice to
the upper half and lower half.
b) CPU operating clock change control
(LED 4: monitor pin 4)
c) OSC3 oscillation on/ off control
(LED 5: monitor pin 5)
d) SVD circuit on/ off control
(LED 6: monitor pin 6)
e) LCD power supply control
(LED 7: monitor pin 7)
f) Heavy load protection mode
(LED 8: monitor pin 8)
g) SLEEP and Halt execution ratio
(LED 9: monitor pin 9)
h) LCD voltage regulator power selection
(LED 10: monitor pin 10)
i) Power voltage booster
(LED 11: monitor pin 11)
SVD circuit
• The SVD function is realized by artificially
varying the power supply voltage using the
VSVD control on the front panel of the
S5U1C88000P1.
• There is a finite delay time from when the
power to the SVD circuit turns on until actual
detection of the voltage. The delay time on this
board differs from that of the actual IC. Refer
to Chapter 8, "ELECTRICAL CHARACTERIS-
TICS" when setting the appropriate wait time
for the actual IC.
j) OSC1 operating clock
(LED 14: monitor pin 14)
k) OSC3 operating clock
(LED 15: monitor pin 15)
Those that can only be counteracted
by system or software
l) Current consumed by the internal pull-up
resistors
m) Input ports in a floating state
•
The evaluation voltages supported in this
board are different from those of the actual IC.
When debugging the SVD operation using this
board, evaluate the SVD results as levels not
voltages.
166
EPSON
S1C88650 TECHNICAL MANUAL
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
Oscillation circuit
• The OSC1 crystal oscillation frequency is fixed
at 32.768 kHz.
Access to undefined address space
If any undefined space in the S1C88650's
internal ROM/ RAM or I/ O is accessed for
data read or write operations, the read/ written
value is indeterminate. Additionally, it is
important to remain aware that the indetermi-
nate state differs between this board and the
actual IC.
• The OSC1 CR oscillation frequency can be
adjusted in the range of approx. 20 kHz to 500
kHz using the control on the S5U1C88000P1
front panel. Note that the actual IC does not
operate with all of these frequencies; refer to
Chapter 8, "ELECTRICAL CHARACTERIS-
TICS" to select the appropriate operating
frequency.
Reset circuit
Keep in mind that the operation sequence from
when the ICE with this board installed is
powered on until the time at which the
program starts running differs from the
sequence of the actual IC. This is because this
board becomes capable of operating as a
debugging system after the user program and
optional data are downloaded.
• The OSC3 crystal oscillation frequency is fixed
at 4.9152 MHz.
• The OSC3 CR oscillation frequency can be
adjusted in the range of approx. 100 kHz to 8
MHz using the control on the S5U1C88000P1
front panel. Note that the actual IC does not
operate with all of these frequencies; refer to
Chapter 8, "ELECTRICAL CHARACTERIS-
TICS" to select the appropriate operating
frequency.
Internal power supply circuit
The LCD drive voltage on this board is
different from that on the actual IC.
Size of the Kanji-font ROM
The actual IC contains 896K bytes of Kanji-font
memory (address 010000H to 0EFFFFH). The
memory size implemented in the ICE is 448K
bytes.
• The S5U1C88000P1&S5U1C88649P2 does not
include the OSC3 ceramic oscillation circuit.
When ceramic oscillation circuit is selected by
mask option, the S5U1C88649P2 uses the on-
board crystal oscillation circuit.
Function option
• Input interface level
• When using an external clock, adjust the
external clock (amplitude: 3.3 V ±5%, duty:
50% ±10%) and input to the OSC1 or OSC3
terminal with VSS as GND.
The actual IC allows selection of the input
interface level either COMS level or CMOS
Schmitt level by a function option. This board
supports CMOS level only and selection of the
function option using Winfog does not affect
the interface level of this board.
• This board can operate normally even when the
CPU clock is switched to OSC3 (CLKCHG = "1")
immediately after the OSC3 oscillation control
circuit is turned on (SOSC3 = "1") without a wait
time inserted. In the actual IC, an oscillation
stability wait time is required before switching
the CPU clock after the OSC3 oscillation is
turned on. Refer to Chapter 8, "ELECTRICAL
CHARACTERISTICS" when setting the appro-
priate wait time for the actual IC.
(4) Notes on model support
Parameter file
The ROM, RAM and I/ O spaces in the ICE with
this board installed are configured when the
debugger on the personal computer starts up
using the parameter file (88650.par) provided for
each model.
The parameter file allows the user to modify its
contents according to the ROM and RAM spaces
actually used. Do not configure areas other than
below when using the IC in single chip maxi-
mum mode.
• Use separate instructions to switch the clock
from OSC3 to OSC1 and to turn off the OSC3
oscillation circuit. If executed simultaneously
with a single instruction, these operations,
although good with this board, may not
function properly with the actual IC.
ROM area: 0000H to BFFFH
10000H to EFFFFH
RAM area: D800H to F7FFH
Stack area: D800H to F7FFH
• This board contains oscillation circuits for
OSC1 and OSC3. Keep in mind that even
though the actual IC may not have a resonator
connected to its OSC3, this board can operate
with the OSC3 circuit.
Access disable area
When using this board for development of an
S1C88650 application, be sure not to read and
write from/ to I/ O memory addresses FF16H
and FF90H to FFADH.
Furthermore, do not change the initial values
when writing to bit D4 of address FF17H, bits D6
and D7 of address FF21H, bit D7 of address
FF22H, and bit D7 of address FF26H.
• Because the logic level of the oscillation circuit
is high, the timing at which the oscillation
starts on this board differs from that of
theactual IC.
S1C88650 TECHNICAL MANUAL
EPSON
167
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
A.3 Connecting to the Target System
This section explains how to connect the S5U1C88000P1&S5U1C88649P2 to the target system.
Note: Turn the power of all equipment off before connecting or disconnecting cables.
Use the I/ O cables (80-pin/ 40-pin × 2 flat type,
100-pin/ 50-pin × 2 flat type, 40-pin/ 20-pin × 2 flat
type) to connect between the I/ O #1 to I/ O #4
connectors of the front panel and the target
system.
The following shows the clock frequencies
generated from the on-board crystal oscillation
circuits:
OSC1 crystal oscillation circuit: 32.768 kHz
OSC3 crystal oscillation circuit: 4.9152 MHz
Connect the 80-pin, 100-pin and 40-pin cable
connectors to the I/ O #1 to I/ O #4 connectors, and
the 40-pin × 2, 50-pin × 2 and 20-pin × 2 connectors
to the target system. Be careful as power (VDD) is
supplied to I/ O #1, I/ O #2 and I/ O #3 connectors.
When CR oscillation is selected, the oscillation
frequency can be adjusted using the controls on
the front panel (OSC1H and OSC1L for adjusting
OSC1, OSC3H and OSC3L for adjusting OSC3).
Use a frequency counter or other equipment to be
connected to the OSC1 CR oscillation frequency
monitor pin (pin 18) on the monitor connector or
OSC3 CR oscillation frequency monitor pin (pin
19) for monitoring the frequency during adjust-
ment. Be sure of the frequency when using this
monitor pin because the CR oscillation frequency
is initially undefined.
OSC1
OSC3
L
VLCD VSVD
H
L
H
RESET
S5U1C88000P1
S1C88 Family Peripheral circuit board
EPSON
LCD
MONITOR
I/O #1
I/O #2
DIAG
ON/OFF
EMU
POWER
SLP/HALT
ICE88UR
amily In-Circuit Emulator
I/O #3
I/O #1
I/O #2
I/O #4
(40-pin)
(80-pin)
(80-pin)
(100-pin)
CN3-2
CN3-1
CN1-2
CN1-1
CN2-1
CN2-2
CN4-1
CN4-2
(20-pin)
(20-pin)
(40-pin)
(40-pin)
(40-pin)
(40-pin)
(50-pin)
(50-pin)
CN3-2
CN3-1
CN1-2
CN1-1
CN2-1
CN2-2
CN4-1
CN4-2
Target board
Fig. A.3.1 Connecting to the target system
168
EPSON
S1C88650 TECHNICAL MANUAL
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
I/O connector pin assignment
Table A.3.1 I/O #1 connector
Table A.3.2 I/O #2 connector
40-pin CN1-1
Pin name
VDD (3.3 V)
VDD (3.3 V)
VSS
40-pin CN1-2
Pin name
R12/A10
R13/A11
R14/A12
R15/A13
R16/A14
R17/A15
R20/A16
R21/A17
R22/A18
R23/A19
R24/RD
R25/WR
N.C.
40-pin CN2-1
Pin name
40-pin CN2-2
No.
1
2
3
4
5
6
7
8
No.
1
2
3
4
5
6
7
8
No.
1
2
3
4
5
6
7
8
No.
1
2
3
4
5
6
7
8
Pin name
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
VDD (3.3 V)
VDD (3.3 V)
VSS
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
RESET
MCU/MPU
OSC1EX
OSC3EX
N.C.
N.C.
N.C.
N.C.
N.C.
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
9
9
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
N.C.
R30/CE0
R31/CE1
R32/CE2
R33/(BACK)
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
N.C.
N.C.
N.C.
R00/A0
R01/A1
R02/A2
R03/A3
R04/A4
R05/A5
R06/A6
R07/A7
R10/A8
R11/A9
COM10
COM11
COM12
COM13
COM14
COM15
39
40
3
4
1
2
Fig. A.3.2 CN1-1/CN1-2 and CN2-1/CN2-2 pin layout
S1C88650 TECHNICAL MANUAL
EPSON
169
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
Table A.3.3 I/O #3 connector
Table A.3.4 I/O #4 connector
20-pin CN3-1
Pin name
20-pin CN3-2
50-pin CN4-1
Pin name
50-pin CN4-2
No.
1
2
3
4
5
6
7
8
No.
1
2
3
4
5
6
7
8
Pin name
VSS
VSS
P00/D0
P01/D1
P02/D2
P03/D3
P04/D4
P05/D5
P06/D6
P07/D7
VDD (3.3 V)
VDD (3.3 V)
P10/SIN
No.
1
2
3
4
5
6
7
8
No.
1
2
3
4
5
6
7
8
Pin name
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
K00
K01
K02
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
K03(BREQ)
K04/EXCL0
K05/EXCL1
K06/EXCL2
K07/EXCL3
N.C.
9
9
9
9
10
11
12
13
14
15
16
17
18
19
20
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P11/SOUT
P12/SCLK
P13/SRDY
P14/TOUT0/TOUT1
P15/TOUT2/TOUT3
P16/FOUT
P17/TOUT2/TOUT3
N.C.
N.C.
N.C.
170
EPSON
S1C88650 TECHNICAL MANUAL
APPENDIX A S5U1C88000P1&S5U1C88649P2 MANUAL (Peripheral Circuit Board for S1C88650)
A.4 Product Specifications
The components specifications of the S5U1C88649P2
are listed below.
S5U1C88649P2
Dimensions (mm):
184 (W) × 152 (D) × 17 (H)
I/O cable (100-pin/50-pin x 2)
S5U1C88649P2 connector (100-pin):
KEL 8830E-100-170L
Cable connector (100-pin):
KEL 8822E-100-170L
Cable connector (50-pin):
× 1
Connector
Strain relief 3M 3448-7950
3M 7950-B500SC
× 2
× 2
Cable:
50-pin flat cable
× 1
Interface:
CMOS interface (3.3 V)
Length:
Approx. 40 cm
I/O cable (40-pin/20-pin x 2)
S5U1C88649P2 connector (40-pin):
KEL 8830E-040-170L
Cable connector (40-pin):
KEL 8822E-040-170L
Cable connector (20-pin):
× 1
Connector
Strain relief 3M 3448-7920
3M 7920-B500SC
× 2
× 2
Cable:
20-pin flat cable
× 1
Interface:
CMOS interface (3.3 V)
Length:
Approx. 40 cm
Accessories
50-pin connector for the target system:
3M 3433-6002LCSC
20-pin connector for the target system:
3M 3428-6002LCSC
× 2
× 2
S1C88650 TECHNICAL MANUAL
EPSON
171
APPENDIX B USING KANJI FONT
APPENDIX B USING KANJI FONT
Use the S5U1C88000R1 (12 × 12-dot RIS 506 kanji
font package) to display kanji font on an LCD in
the S1C88650 microcomputer.
The kanji font data is supplied in an object file
format (assembler output file identified by the
extension .obj) to enable it to be embedded in the
S1C88-Family microcomputer programs. Simply
by linking this object file to the created application
program, the kanji font data can be used
easily.Note 2
This package contains 12 × 12-dot-sized fonts
(Seiko Epson original designNote 1) for the charac-
ter codes conforming to the music shift-JIS kanji
stipulated in the Recording Industry Association
of Japan standard RIS 506-1996, which are sup-
plied in the form of embeddable data for S1C88-
Family microcomputer programs. The package
also contains a sample program that runs on the
S1C88-Family microcomputer to display this font
data on an LCD, an application note for the
sample program, and a bitmap utility that can be
used to create custom font data.
See the "S5U1C88000R1 Manual" for details.
Notes 1 Before the kanji font data included with
the package and the typefaces shown in
the manual can be used, a contract for a
license to use the typefaces must be
concluded between Seiko Epson and the
purchaser.
2 The programs necessary to obtain font
data from the character codes and display
the font data on an LCD must be created
by the user.
User-developed program
Compile
Assemble
Font data
object
Linker
ROM size used:
133,388 bytes
Locator
Shown here is the typeface of an excerpted kanji font.
Executable file
172
EPSON
S1C88650 TECHNICAL MANUAL
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
23F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
- HEADQUARTERS -
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: 64106655
Fax: 64107319
Phone: +1-408-922-0200
Fax: +1-408-922-0238
SHANGHAI BRANCH
7F, High-Tech Bldg., 900, Yishan Road
Shanghai 200233, CHINA
- SALES OFFICES -
West
Phone: 86-21-5423-5577 Fax: 86-21-5423-4677
1960 E. Grand Avenue
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
EI Segundo, CA 90245, U.S.A.
Phone: +1-310-955-5300
Fax: +1-310-955-5400
Central
Phone: +852-2585-4600 Fax: +852-2827-4346
Telex: 65542 EPSCO HX
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630
Fax: +1-815-455-7633
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road, Taipei 110
Northeast
Phone: 02-8786-6688
Fax: 02-8786-6660
301 Edgewater Place, Suite 120
Wakefield, MA 01880, U.S.A.
Phone: +1-781-246-3600
HSINCHU OFFICE
No. 99, Jiangong Rd., Hsinchu City 300
Fax: +1-781-246-5443
Phone: +886-3-573-9900 Fax: +886-3-573-9169
Southeast
3010 Royal Blvd. South, Suite 170
Alpharetta, GA 30005, U.S.A.
Phone: +1-877-EEA-0020 Fax: +1-770-777-2637
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00
Millenia Tower, SINGAPORE 039192
Phone: +65-6337-7911
Fax: +65-6334-2716
EUROPE
SEIKO EPSON CORPORATION KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
EPSON EUROPE ELECTRONICS GmbH
Phone: 02-784-6027
Fax: 02-767-3677
- HEADQUARTERS -
Riesstrasse 15
80992 Munich, GERMANY
GUMI OFFICE
6F, Good Morning Securities Bldg.
56 Songjeong-Dong, Gumi-City, 730-090, KOREA
Phone: +49-(0)89-14005-0
Fax: +49-(0)89-14005-110
Phone: 054-454-6027
Fax: 054-454-6093
DÜSSELDORF BRANCH OFFICE
Altstadtstrasse 176
51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0
SEIKO EPSON CORPORATION
Fax: +49-(0)2171-5045-10
ELECTRONIC DEVICES MARKETING DIVISION
UK & IRELAND BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
ED International Marketing Department
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
Fax: +81-(0)42-587-5117
Phone: +44-(0)1344-381700
Fax: +44-(0)1344-381701
FRENCH BRANCH OFFICE
1 Avenue de l' Atlantique, LP 915 Les Conquerants
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
Phone: +33-(0)1-64862350
Fax: +33-(0)1-64862355
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vallès, SPAIN
Phone: +34-93-544-2490
Fax: +34-93-544-2491
Scotland Design Center
Integration House, The Alba Campus
Livingston West Lothian, EH54 7EG, SCOTLAND
Phone: +44-1506-605040
Fax: +44-1506-605041
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