MF297-07
-
CMOS 4 BIT SINGLE CHIP MICROCOMPUTER
S1C6200/6200A
Core CPU Manual
NOTICE
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© SEIKO EPSON CORPORATION 2001 All rights reserved.
CONTENTS
S1C6200/6200A Core CPU Manual
CONTENTS
1 DESCRIPTION ____________________________________________________ 1
1.1 System Features........................................................................................................ 1
1.2 Instruction Set Features ........................................................................................... 1
1.3 Differences between S1C6200 and S1C6200A......................................................... 1
2 MEMORY AND OPERATIONS __________________________________________ 3
2.1 Program Memory (ROM) ......................................................................................... 3
2.1.1 Program counter block ............................................................................................ 4
2.1.2 Flags ........................................................................................................................ 4
2.1.3 Jump instructions..................................................................................................... 5
2.1.4 PSET with jump instructions ................................................................................... 5
2.1.5 Call instructions ...................................................................................................... 5
2.1.6 PSET instruction...................................................................................................... 6
2.1.7 CALZ instruction ..................................................................................................... 6
2.1.8 RET and RETS instructions ..................................................................................... 7
2.1.9 Stack considerations for call instructions ............................................................... 7
2.2 Data Memory ............................................................................................................ 8
2.2.1 Data memory addressing......................................................................................... 8
2.3 ALU (Arithmetic Logic Unit) and Registers ............................................................ 10
2.3.1 D (decimal) flag and decimal operations ............................................................... 10
2.3.2 A and B registers .................................................................................................... 11
2.4 Timing Generator .................................................................................................... 11
2.4.1 HALT and SLP (sleep) modes................................................................................. 11
2.5 Interrupts ................................................................................................................. 12
2.5.1 Interrupt vectors ..................................................................................................... 12
2.5.2 I (interrupt) flag...................................................................................................... 12
2.5.3 Operation during interrupt generation .................................................................. 12
2.5.4 Initial reset.............................................................................................................. 15
3 INSTRUCTION SET _________________________________________________ 16
3.1 Instruction Indices ................................................................................................... 16
3.1.1 By function .............................................................................................................. 17
3.1.2 In alphabetical order .............................................................................................. 20
3.1.3 By operation code ................................................................................................... 23
3.2 Operands ................................................................................................................. 26
3.3 Flags ........................................................................................................................ 26
3.4 Instruction Types ..................................................................................................... 27
3.5 Instruction Descriptions .......................................................................................... 27
APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU _________________ 84
B. INSTRUCTION INDEX ______________________________________ 87
S1C6200/6200A CORE CPU MANUAL
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1 DESCRIPTION
1 DESCRIPTION
The S1C6200/ 6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput-
ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include
RAM, ROM, I/ O ports, interrupt controllers, timers and LCD drivers, depending upon the application.
The memory address space is divided into program and data memory, each with data and address lines.
Program memory consists of on-chip ROM, containing instructions to be executed by the CPU. Data
memory consists of RAM and memory-mapped I/ O, as determined by the design of the peripheral cir-
cuitry.
A large memory as well as instructions capable of 8-bit data manipulation enhance the functionality of the
S1C62 Family. Implementation of a common Core CPU ensures that a wide range of application-specific
devices can be designed and fabricated with the minimum turnaround time.
1.1 System Features
• Common Core CPU for all S1C62 Family microcomputers
• UP to 8,192 12-bit words of program memory (ROM)
• UP to 4,096 4-bit words of data memory (RAM/peripheral circuits)
• Memory-mapped I/O
• 5, 7 or 12 clock cycle instructions
• 109 instructions
• Up to 85 levels of subroutine nesting
• 8-bit stack pointer
• Up to 15 interrupt vectors
• Two standby modes
• Low-power CMOS process
1.2 Instruction Set Features
• Four addressing modes: one direct, two indirect, and one stack pointer
• Direct addressing transfers data to and from data memory with a single instruction, resulting in more
efficient code
• 8-bit load instructions and table look-up instructions
• Arithmetic operations in either hexadecimal or decimal
• Arithmetic and logical instructions: addition, subtraction, logical AND, OR, exclusive-OR, comparison
and rotation
1.3 Differences between S1C6200 and S1C6200A
There are some differences in the following operation/ circuit between the S1C6200 and the S1C6200A.
For the detailes of each difference, refer to the section enclosed with parentheses.
• Initial setting of D (decimal) flag (refer to Section 2.5.5, "Initial reset".)
• Interrupt circuit
–
–
Interrupt timing (refer to Section 2.5.3, "Operation during interrupt generation".)
Writing to interrupt mask registers and reading of interrupt flags (refer to Appendix A, "S1C6200A
(Advanced S1C6200) Core CPU".)
S1C6200/6200A CORE CPU MANUAL
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1 DESCRIPTION
4-bit address bus
XP (4)
YP (4)
Data Memory
RAM, Peripheral I/O
(4,096 4-bit words max.)
Oscillator
RP (4)
Interrupt
Timing
Controller
Generator
YHL (8)
XHL (8)
A (4)
B (4)
Stack Pointer (8)
Program Counter Block
TEMPB(5) TEMPA(5)
ALU
Micro-Instructions
I D Z C
Instruction Decorder
Instruction Register (12)
S1C6200 CORE CPU
12-bit data bus
Program Memory
ROM
(8,192 12-bit words max.)
Fig. 1.1 Block diagram
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S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
2 MEMORY AND OPERATIONS
A single-chip microcomputer using the S1C6200/ 6200A Core CPU has four major blocks: the
program memory (ROM), the data memory (RAM and I/ O), the arithmetic logic unit (ALU) and the timing
generator circuit. This section describes each of these blocks in detail.
2.1 Program Memory (ROM)
Program memory contains the instructions that the CPU executes. Figure 2.1.1 shows the configuration of
the program memory.
Each instruction is a 12-bit word. Program memory can also be used for data tables for the table look-up
instructions.
There are two banks of program memory. Each bank is subdivided into 16 pages of 256 words (or steps).
That is:
Program memory = 2 banks
= 8,192 steps
1 bank
= 4,096 steps
= 16 pages
= 256 steps
= 1 word
1 page
1 step
= 12 bits
Certain addresses in ROM have specific functions, as shown in Table 2.1.1.
Table 2.1.1 Allocated program memory
Address
Function
Bank 0, Page 1, Step 0
Reset vector
Bank 0, Page 1, Step 1 to 15
Bank 0, Page 0, Step 0 to 255
Interrupt vectors used while a program is running in bank 0
Bank 0, page 0 area
Direct call subroutines for use by CALZ while a program is running in bank 0
Interrupt vectors used while a program is running in bank 1
Bank 1, page 0 area
Bank 1, Page 1, Step 1 to 15
Bank 1, Page 0, Step 0 to 255
Direct call subroutines for use by CALZ while a program is running in bank 1
Bank 0 Page 1
Step 0 Reset vector
Bank 0 Page 15
Bank 0 Page 14
Step 0
Step 1
Bank 1 Page 15
Bank 0
Bank 1
Bank 1 Page 14
Step 0
Step 1
Step 1
Interrupt
vectors
PCS
(within bank)
Step 15 for Bank 0
Bank 0 Page 3
Bank 0 Page 2
Step 0
Bank 1 Page 3
Bank 1 Page 2
Step 0
Step 254
Step 255
Step 254
Step 255
Step 254
Step 255
Bank 0 Page 0
Step 0
Bank 1 Page 0
Step 0
Step 1
Step 1
Bank 1 Page 1
Step 0
PCP
(within bank)
12-bit
instructions
Step 1
Interrupt
vectors
Step 15 for Bank 1
Step 254
Step 255
Step 254
Step 255
PCB (between banks)
Step 254
Step 255
Program or data
code area
Program or data
Program or data
code or CALZ
subloutines in
Bank 1
code or CALZ
subloutines in
Bank 0
Fig. 2.1.1 Program memory configuration
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2 MEMORY AND OPERATIONS
2.1.1 Program counter block
The program counter is used to point to the next instruction step to be executed by the CPU. See Figure
2.1.1.1.
The program counter has the following registers.
Table 2.1.1.1 Program counter registers
Register
Size
PCB (Program Counter-Bank)
PCP (Program Counter-Page)
PCS (Program Counter-Step)
NBP (New Bank Pointer)
NPP (New Page Pointer)
1-bit register
4-bit counter
8-bit counter
1-bit register
4-bit register
Program memory
(8,192 12-bit words max.)
Address decoder
PCB
(1)
PCP
(4)
PCS
(8)
NBP
(1)
NPP
(4)
Program counter block
Fig. 2.1.1.1 Program counter configuration
PCB, PCP and PCS together from a 13-bit counter which can address any location in program memory.
PCP and PCS together from a 12-bit counter which can address any location within a given bank of pro-
gram memory. Each time an instruction other than a jump is executed, this counter increments by one.
Thus, a jump instruction does not need to be executed between the last step of one page and the first step of
the next.
The contents of NBP and NPP are loaded into PCB and PCP each time an instruction is executed. On reset,
NBP and NPP are loaded with the same values as PCB and PCP.
2.1.2 Flags
The following flags are provided.
Table 2.1.2.1 Flags
Flag
Interrupt
Menus
Size
1: Enabled
0: Disabled
1: Decimal
0: Hexadecimal
1: Set
I
Decimal mode
Zero
D
Z
C
0: Ignored
1: Set
Carry
0: Ignored
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S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
2.1.3 Jump instructions
A jump can be made using the instructions in Table 2.1.3.1.
Table 2.1.3.1 Jump instructions
Type of jump
Unconditional
Conditional
Subroutine call
Return
Instruction
JP
JP C, JP NC, JP Z, JP NZ
CALL, CALZ
RET, RETS, RETD
PSET
Page set
Indirect
JPBA
The differences between jumps within the same page and jumps from one page to another is as follows.
• Jumps within the same page
A jump can be made within the same page using any of the following instructions:
JP, JP C, JP Z, JP NZ, JPBA or CALL
The destination address is specified by the 8-bit operand. A label can be used to specify a destination
address with the S1C62 Family cross assembler.
• Jumps from one page to another
The destination bank and page should be set using PSET before executing a JP instruction.
2.1.4 PSET with jump instructions
PSET loads the four low-order bits (page part) of its 5-bit operand to NPP (new page pointer) and loads the
high-order bit (bank part) to NBP (new bank pointer). Executing a JP instruction immediately after PSET
causes a jump to the bank specified by NBP, the page specified by NPP and the step specified by the JP
instruction operand. See Figure 2.1.4.1.
Bank 0 Page 15
Bank 0 Page 14
Step 0
Step 1
Bank 0
Jump with PSET can go anywhere
within the program memory
Jump can go between banks
PSET
JUMP
Bank 0 Page 3
Bank 0 Page 2
Bank 0 Page 1
Bank 0 Page 0
Step 0
Step 1
Step 254
Step 255
Bank 1 Page 15
Bank 1 Page 14
Step 0
Step 1
Bank 1
JUMP
Bank 1 Page 3
Bank 1 Page 2
Bank 1 Page 1
Step 254
Step 255
Step 254
Step 255
Bank 1 Page 0
Step 0
Jump without PSET
can go anywhere
within one page
Step 1
Step 254
Step 255
Fig. 2.1.4.1 The PSET and jump instructions
2.1.5 Call instructions
As only the page data specified by NPP is loaded to PCP when a call instruction is executed, subroutine
calls between banks are not possible. Jumps between banks can only be made using JP instructions.
S1C6200/6200A CORE CPU MANUAL
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2 MEMORY AND OPERATIONS
2.1.6 PSET instruction
Jump or call instructions must follow PSET immediately in order for PSET to affect the destination address.
When a jump or call is not immediately preceded by PSET, the destination address is within the current
page.
Some examples using PSET are shown in Table 2.1.6.1.
Table 2.1.6.1 PSET examples
Bank Page Stap
Instruction
01H 10H PSET 13H
01H 11H JP 08H
Operation
0
0
•
The program jumps to bank 1, page 3, step 8.
•
•
•
•
•
•
•
0
0
0
•
01H 21H PSET 15H
01H 22H NOP5
The data set by PSET is canceled.
The program jumps to bank 0, page 1, step 9.
01H 23H JP
09H
•
•
•
•
•
•
•
0
0
0
•
01H 55H SCF
01H 56H PSET 14H
01H 57H JP C, 07H The program jumps to bank 1, page 4, step 7 because C flag = 1.
C flag is set.
•
•
•
•
•
•
•
0
0
0
0
•
01H 60H RFC
01H 61H PSET 05H
C flag is reset.
01H 62H JP
01H 63H JP
C, 08H No jump occurs because C flag = 0.
09H The data set by PSET is canceled, and the program jumps to bank 0, page 1, step 9.
•
•
•
•
•
•
•
2.1.7 CALZ instruction
CALZ is a direct subroutine call instruction. It calls a subroutine, in page 0 of the current bank, from any
page without requiring the use of PSET.
If CALZ is executed immediately after PSET, the bank and page set by PSET is canceled. This allows direct
subroutine calls to page 0, minimizing repeated code and unnecessary use of PSET. See Figure 2.1.7.1.
Bank 0 Page 0
EEE....................
RET
Bank 0 Page 2
Not effect
on destination
of CALZ
PSET 0AH
CALZ EEE
LD
A,0
Fig. 2.1.7.1 The use of the CALZ instruction
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2 MEMORY AND OPERATIONS
The difference between CALL and CALZ is shown in Figure 2.1.7.2.
CALL with PSET
can go anywhere
within a bank
Bank 0 Page 15
Bank 0 Page 14
Step 0
Step 1
Bank 1 Page 15
Bank 1 Page 14
Step 0
Step 1
Bank 0
Bank 1
CALL
PSET
CALL
Bank 0 Page 3
Bank 1 Page 3
CALZ
Bank 0 Page 1
Bank 0 Page 0
Step 0
Step 1
Bank 1 Page 1
Bank 1 Page 0
Step 0
Step 1
Ste4
Sp 255
Step 254
Step 255
CALZ
CALL without PSET
can go anywhere
in a page
CALL and CALZ
cannot go
between banks
Step 254
Step 255
Step 254
Step 255
CALZ can only go to page 0
of the current bank
Fig. 2.1.7.2 The difference between CALL and CALZ instructions
2.1.8 RET and RETS instructions
The RET instruction causes a return from a subroutine to the address immediately following the address
from where that subroutine was called. The RETS instruction causes a return to the address following this
address. Proper use of RET and RETS allows simple conditional exits subroutines back to the main routine.
See Figure 2.1.8.1.
Bank 0 Page 0
Program memory
PSET 0AH
CALL DDD
LD
LD
A,0
B,0
Bank 0 Page 10
Program memory
DDD....................
RET
RETS
Fig. 2.1.8.1 Difference between RET and RETS instructions
2.1.9 Stack considerations for call instructions
When a subroutine is called, the return address is loaded into the stack and retrieved when control is
returned to the calling program. Nesting allows efficient usage of the stack area.
As the stack area resides in the data memory, care should be taken to ensure that the stack area is not
corrupted by other data.
S1C6200/6200A CORE CPU MANUAL
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2 MEMORY AND OPERATIONS
2.2 Data Memory
The data memory area comprises 4,096 4-bit words. The RAM, timer, I/ O and other peripheral circuits are
mapped into this memory according to the designer's specifications. Figure 2.2.1 shows the data memory
configuration.
Page 15
Page 14
Step 0
Step 1
RP
XHL or YHL
Page 0
only
(within page)
Page 3
Page 2
Page 1
Page 0
Step 254
Step 255
Step 0
Step 1
XP or YP
(page specification)
SP
Page 0
only
Step 15
Memory or I/O
Register area
Step 254
Step 255
4-bit data
Fig. 2.2.1 Data memory configuration
2.2.1 Data memory addressing
The following registers and pointers, which are described in detail below, are used to address the data
memory.
Table 2.2.1.1 Registers and pointer for data memory addressing
Register/Pointer
Index Register X
Index Register Y
Stack Pointer
Mnemonic
Size (bits)
IX
IY
SP
RP
12
12
8
Register
4
• Index register IX
MSB
LSB
Index register IX has a 4-bit page part (XP) and an 8-
bit register (XHL), and can address any location in
the data memory. See Figure 2.2.1.1.
4
4
4
XP
XH
XL
XHL
XHL is divided into two 4-bit groups: the four high-
order bits (XH) and the four low-order bits (XL), and
can address any location within a page.
IX
Fig. 2.2.1.1 The configuration of the index register IX
–
–
–
MX is the data memory location whose address is specified by IX.
M(X) refers to the contents of the data memory location whose address is specified by IX.
XHL can be incremented by 1 or 2 using a post-increment instruction (LDPX, ACPX, SCPX, LBPX or
RETD). An overflow occurring in XHL does not affect the flags.
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S1C6200/6200A CORE CPU MANUAL
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• Index register IY
MSB
LSB
Index register IY is like the index register IX: it has a
4-bit page part (YP), an 8-bit register (YHL), and can
address any location in the data memory. See Figure
2.2.1.2.
4
4
4
YP
YH
YL
YHL
YHL is divided into two 4-bit groups: the four high-
order bits (YH) and the four low-order bits (YL), and
can address any location within a page.
IY
Fig. 2.2.1.2 The configuration of the index register IY
–
–
–
MY is the data memory location whose address is specified by IY.
M(Y) refers to the contents of the data memory location whose address is specified by IY.
YHL can be incremented by 1 using a post-increment instruction (LDPY, ACPY or SCPY). An
overflow occurring in YHL does not affect the flags.
• Stack pointer SP
The stack area resides in the data memory. The 8-bit, push-down/ pop-up stack pointer (SP) is used to
address an element within the stack.
Table 2.2.1.2 Stack usage
Since it is an 8-bit pointer, SP can only address 256
Operation
Push-down
Instruction
Interrupt
Stack usage
words out of the total 4,096 words of data memory.
When SP is used, the high-order 4 bits (page part) of
the data memory address are 0, giving a stack area of
256 words in the address range 000H to 0FFH.
-3
-3
(SP is decremented) CALL or CALZ
PUSH
-1
DEC SP
-1
In systems with a RAM area of less than 256 words,
the entire RAM area can be used as the stack area.
Pop-up
RET, RETS or RETD
+3
+1
+1
(SP is incremented) POP
INC SP
Stack area usage is shown in Table 2.2.1.2.
The PUSH instruction can be used to store registers and flags in the stack in single-word (4-bit) units.
The POP instruction is used to retrieve this data.
When an interrupt occurs or a call instruction is executed, the return address from the program counter
is pushed onto the stack. When a return instruction is executed, the return address is retrieved from the
stack and loaded into the program counter.
On an interrupt, only the program counter is saved on the stack; flag and register data are not saved.
Programs should be designed so that flag and register data are pushed onto the stack by the interrupt
service routines.
Following a system reset, SP should be initialized using the LD SPH,r or LD SPL,r instructions, where
r represents A, B, MX or MY (4 bits).
Stack pointer data can be read using LD r,SPH or LD r,SPL.
• Register pointer RP
The register pointer (RP) is a 4-bit register used to address the first 16 words of data memory, or the
register area. Direct addressing can be used to read from, write to, increment or decrement any location
within this area efficiently, using a single instruction.
Programs cannot directly access RP. It uses the
operand of direct addressing instructions. The
instructions that can access the register area of data
memory are:
LD
LD
LD
LD
INC
A,Mn
B,Mn
Mn,A
Mn,B
Mn
A ← M(n)
B ← M(n)
M(n) ← A
M(n) ← B
where M(n) is the contents of a data memory
location within the register area.
M(n) ← M(n) + 1
As the register area can also be indirectly accessed
using IX, IY or SP, the stack area should not grow
to address 000H to 00FH when RP is used.
DEC Mn
M(n) ← M(n)
n: 0 to F
–
1
S1C6200/6200A CORE CPU MANUAL
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2 MEMORY AND OPERATIONS
2.3 ALU (Arithmetic Logic Unit) and Registers
Table 2.3.1 shows ALU operations between the 4-bit registers, TEMPA and TEMPB.
Table 2.3.1 ALU register operation
Operation
Add, without carry
Instruction
ADD
ADC
SUB
SBC
Add, with carry
Subtract, without borrow
Subtract, with borrow
Logical-AND
AND
OR
Logical-OR
Exclusive-OR
XOR
CP
Comparison
Flag bit test
FAN
RRC
RLC
NOT
Rotate right, with carry
Rotate left, with carry
Invert
The Z (zero) flag is set when the result of ALU operation is
C
X
3
0
2
0
1
0
0
0
X: Don't care.
The C (carry) flag is set when an add operation causes a carry or when a subtract operation causes a
borrow.
2.3.1 D (decimal) flag and decimal operations
Setting the D (decimal) flag activates the decimal mode, allowing decimal addition and subtraction. Table
2.3.1.1 shows the relations of actual (decimal) results, ALU outputs, and the values of the C and Z flags.
Table 2.3.1.1 Results of hexadecimal and decimal operations
Addition
D = 0 : Result of
result hexadecimal operation
Subtraction
D = 0 : Result of
result hexadecimal operation
Actual
D = 1 : Result of
decimal operation
Actual
D = 1 : Result of
decimal operation
Z
C
ALU output
Z
C
ALU output
Z
C
ALU output
Z
C
ALU output
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
-16
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
9
10
11
12
13
14
15
10
EPSON
S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
Hexadecimal operations will not always produce the correct result if performed in decimal mode.
Note that:
• An add instruction with carry (for example, ADC XH,i) which uses index registers XH, XL, YH and YL,
does not involve decimal correction even if it is performed in the decimal mode. This is because it uses
an 8-bit field for 4-bit data.
• The results of the compare instruction (CP) is not decimal-corrected, because the carry flag is ignored.
• The result of the register memory increment instruction (INC Mn) and decrement instruction (DEC Mn)
are not decimal-corrected.
2.3.2 A and B registers
The A and B registers are 4-bit general-purpose registers used as accumulators. They transfer data and
perform ALU operations with other registers, data memory and immediate data.
The data in A can be paired with that in B for use as an indirect jump address by the JPBA instruction.
2.4 Timing Generator
S1C6200/ 6200A instructions can be divided into three different types depending on the number of clock
cycles per instruction: 5, 7 or 12 clock cycles. The more complex the instruction, the more cycles it requires.
Note that the number of clock cycles determines the duration of instructions which, in turn, will affect any
timing performed in software.
As shown in Figure 2.4.1, the first state of all instructions is a fetch cycle. This is followed by a number of
execute cycles.
5-clock/7-clock instructions
Clock
Fetch
Execute
State
1
Fetch
Execute
Status
State
0
State
2
State
0
State
1
State
2
State
3
Instruction
register
Date
memory
12-clock instructions
Clock
Fetch
Execute
Status
State
0
State
1
State
2
State
3
State
4
State
5
State
6
Instruction
register
Fig. 2.4.1 Instruction execution timing
2.4.1 HALT and SLP (sleep) modes
HALT and SLP cause the CPU to store the return address on the stack and then stop. HALT will only stop
the CPU; the system clock will continue to run. SLP also stops the system clock, resulting in reduced power
consumption. The CPU can be restarted by an interrupt.
As interrupts are not automatically enabled by the execution of HALT or SLP, programs should always
enable interrupts before executing HALT or SLP, otherwise they will hang waiting for an interrupt.
S1C6200/6200A CORE CPU MANUAL
EPSON
11
2 MEMORY AND OPERATIONS
2.5 Interrupts
The S1C6200/ 6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow
internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4.
2.5.1 Interrupt vectors
The interrupt vectors are assigned to steps 1 to 15 in page 1 of each bank of the program memory. When an
interrupt occurs, the program jumps to the appropriate interrupt vector in the current bank.
The priority and linking of these vectors to actual outside events depends on the configuration of the
peripheral circuits and therefore is device-specific. This information can be found in the technical manuals
for the specific device.
2.5.2 I (interrupt) flag
The I (interrupt) flag enables or disables all interrupts.
When DI or RST F is used to reset the I flag, interrupts are disabled with that instruction step. When EI or
SET F is used to set the I flag, interrupts are enabled after the following instruction step. For example, to
return control from the interrupt subroutine to the main routine, the sequence EI, RET, does not enable
interrupts until after RET has been executed.
The I flag is reset to 0 (DI) on reset.
2.5.3 Operation during interrupt generation
When an interrupt is generated, the program is halted, the program counter (PCP and PCS) is stored on the
stack, the I flag is reset to DI mode and NPP is set to 1. The program then branches to the interrupt vector
corresponding to the interrupt request. Registers and flags are unaffected by an interrupt.
Register and flag data must be saved by the program since they are not automatically stored on the stack.
The I flag can be set to 1 (EI) within the interrupt subroutine, because nesting of multiple interrupts is
available.
If an interrupt is generated while the CPU is in HALT or SLP mode, the CPU is restarted and the interrupt
serviced. When the interrupt service routine is completed, the program resumes from the instruction
following the HALT or SLP.
<Differences between S1C6200 and S1C6200A>
In the S1C6200 and the S1C6200A, the time it takes to complete interrupt processing by hardware after the
Core CPU receives the interrupt request is different as follows:
Table 2.5.3.1 Required interrupt processing time
S1C6200A
(clock cycles)
12.5 to 24.5
12.5 to 19.5
12.5 to 17.5
14 to 15
S1C6200
(clock cycles)
13 to 25
Item
a) During instruction execution
b) At HALT mode
12-cycle instruction execution
7-cycle instruction execution
5-cycle instruction execution
13 to 20
13 to 18
14 to 15
c) During PSET instruction execution
PSET + CALL
PSET + JP
12.5 to 24.5
12.5 to 22.5
13 to 25
13 to 23
12
EPSON
S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
S1C6200
Clock
Status
5-clock Instrruction
12-clock Instrruction
Interrupt
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt processing: 12-clock instruction ... 13 to 25 clock cycles
7-clock instruction ... 13 to 20 clock cycles
5-clock instruction ... 13 to 18 clock cycles
S1C6200A
Clock
Status
5-clock Instrruction
12-clock Instrruction
Interrupt
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt processing: 12-clock instruction ... 12.5 to 24.5 clock cycles
7-clock instruction ... 12.5 to 19.5 clock cycles
5-clock instruction ... 12.5 to 17.5 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
Fig. 2.5.3.1 Interrupt timing during execution
S1C6200/6200A
System clock
CPU clock
Status
5-clock Instrruction
HALT
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt
Interrupt processing: 14 to 15 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
Fig. 2.5.3.2 Interrupt timing in the HALT mode
S1C6200/6200A CORE CPU MANUAL
EPSON
13
2 MEMORY AND OPERATIONS
S1C6200/6200A
System clock
CPU clock
Status
5-clock Instrruction
SLEEP
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt
Interrupt processing: 14 to 15 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
Fig. 2.5.3.3 Interrupt timing in SLEEP mode
S1C6200
Clock
Status
PSET
CALL
Interrupt
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt processing: PSET + CALL ... 13 to 25 clock cycles
PSET + JP ... 13 to 23 clock cycles
S1C6200A
Clock
Status
PSET
CALL
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt
Interrupt processing: PSET + CALL ... 12.5 to 24.5 clock cycles
PSET + JP ... 12.5 to 22.5 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
Fig. 2.5.3.4 Interrupt timing with PSET
14
EPSON
S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
2.5.4 Initial reset
On reset, the registers and flags are set as shown in Table 2.5.4.1.
Table 2.5.4.1 Reset value
Bit length
Value
00H
01H
00H
01H
Program Counter Step
Program Counter Page
PCS
PCP
8
4
Program Counter Bank PCB
1
New Page Pointer
New Bank Pointer
Stack Pointer
NPP
NBP
SP
IX
IY
RP
A
4
1
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0H
8
Index Register
Index Register
Register Pointer
General Register
General Register
Interrupt Flag
Decimal Flag
Zero Flag
12
12
4
4
B
4
I
1
D
1
*
Z
1
Undefined
Undefined
* S1C6200
...Undefined
Carry Flag
C
1
S1C6200A ...0
<Difference between S1C6200 and S1C6200A>
There is a difference in the setting value of the D (decimal) flag at initial reset between the S1C6200 and the
S1C6200A.
Table 2.5.4.2 D (decimal) flag initial setting
CPU Core
D (decimal) flag setting
S1C6200A
S1C6200
0
Undefined
When using the model loaded with the S1C6200 Core CPU, set or reset the D flag in the user's initial
routine before using an arithmetic instruction. (refer to the SDF and RDF instructions.)
S1C6200/6200A CORE CPU MANUAL
EPSON
15
3 INSTRUCTION SET
3 INSTRUCTION SET
This chapter describes the entire instruction set of the S1C6200/ 6200A Core CPU.
A subset is allocated to each device within the S1C62 Family according to the configuration of the device.
Therefore not all instructions are available in every device. The relevant information is in the technical
manual for each device.
The source format and a description of the assembler is in the series-specific cross assembler manuals.
The instruction set contains 109 instructions. Each instruction comprises of one 12-bit word.
3.1 Instruction Indices
Three index tables are used for easy reference instructions.
a. Index by function
The instructions are arranged by function.
1. Branch
2. System control
3. Flag operation
4. Stack operation
5. Index operation
6. Data transfer
7. Arithmetic and logical operation
b. Index in alphabetical order
The instructions are arranged in alphabetical order. Page number references are provided.
c. Index by operation code
The instructions are arranged in numerical order by operation code.
16
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
3.1.1 By function
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
0
0
0
0
0
1
0
A
1
0
0
0
1
1
1
1
9
1
0
1
1
1
1
1
0
8
0
0
0
1
0
1
1
0
7
6
5
4
3
2
1
0
I
D
Z
C
Branch
PSET
p
0
1
0 p4 p3 p2 p1 p0
5
5
5
5
5
5
5
7
NBP← p4, NPP← p3~p0
instructions JP
s
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
PCB← NBP, PCP← NPP, PCS← s7~s0
PCB← NBP, PCP← NPP, PCS← s7~s0 if C=1
PCB← NBP, PCP← NPP, PCS← s7~s0 if C=0
PCB← NBP, PCP← NPP, PCS← s7~s0 if Z=1
PCB← NBP, PCP← NPP, PCS← s7~s0 if Z=0
PCB← NBP, PCP← NPP, PCSH← B, PCSL← A
M(SP-1)← PCP, M(SP-2)← PCSH, M(SP-3)← PCSL+1
SP← SP-3, PCP← NPP, PCS← s7~s0
C, s
NC, s
Z, s
NZ, s
JPBA
1
1
1
0
1
0
0
0
CALL
CALZ
RET
s
s
s7 s6 s5 s4 s3 s2 s1 s0
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
s7 s6 s5 s4 s3 s2 s1 s0
7
7
M(SP-1)← PCP, M(SP-2)← PCSH, M(SP-3)← PCSL+1
SP← SP-3, PCP← 0, PCS← s7~s0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3
RETS
RETD
12 PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3, PC← PC+1
e
1 e7 e6 e5 e4 e3 e2 e1 e0
12 PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3, M(X)← e3~e0, M(X+1)← e7~e4, X← X+2
System
control
NOP5
NOP7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
5
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
No operation (5 clock cycles)
No operation (7 clock cycles)
Halt (stop clock)
SLEEP (stop oscillation)
X← X+1
instructions HALT
SLP
Index
INC
X
operation
Y
Y← Y+1
instructions LD
X, e
1 e7 e6 e5 e4 e3 e2 e1 e0
0 e7 e6 e5 e4 e3 e2 e1 e0
XH← e7~e4, XL← e3~e0
YH← e7~e4, YL← e3~e0
XP← r
Y, e
XP, r
XH, r
XL, r
YP, r
YH, r
YL, r
r, XP
r, XH
r, XL
r, YP
r, YH
r, YL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
XH← r
XL← r
YP← r
YH← r
YL← r
r← XP
r← XH
r← XL
r← YP
r← YH
r← YL
ADC XH, i
XL, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑
↑
XH← XH+i3~i0+C
XL← XL+i3~i0+C
YH← YH+i3~i0+C
YL← YL+i3~i0+C
↓
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
YH, i
YL, i
S1C6200/6200A CORE CPU MANUAL
EPSON
17
3 INSTRUCTION SET
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
0
0
0
1
1
1
1
0
0
0
0
7
0
0
0
0
0
1
1
1
1
1
0
1
0
1
6
1
1
1
1
0
1
0
0
0
0
1
1
1
1
5
0
0
1
1
4
0
1
0
1
3
2
1
0
I
D
Z
C
XH-i3~i0
Index
CP
XH, i
XL, i
YH, i
YL, i
r, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
XL-i3~i0
operation
instructions
YH-i3~i0
YL-i3~i0
↑
↓
r← i3~i0
Data
LD
r1 r0 i3 i2 i1 i0
r← q
transfer
instructions
r, q
0
1
1
0
0
1
1
1
1
0
r1 r0 q1 q0
A← M(n3~n0)
B← M(n3~n0)
M(n3~n0)← A
M(n3~n0)← B
A, Mn
B, Mn
Mn, A
Mn, B
0 n3 n2 n1 n0
1 n3 n2 n1 n0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
M(X)← i3~i0, X← X+1
r← q, X← X+1
LDPX MX, i
r, q
0
0
1
1
i3 i2 i1 i0
r1 r0 q1 q0
i3 i2 i1 i0
r1 r0 q1 q0
M(Y)← i3~i0, Y← Y+1
r← q, Y← Y+1
LDPY MY, i
r, q
M(X)← e3~e0, M(X+1)← e7~e4, X← X+2
F← FVi3~i0
LBPX MX, e
1 e7 e6 e5 e4 e3 e2 e1 e0
Flag
SET
RST
F, i
F, i
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
i3 i2 i1 i0 ↑
↑
↓
↑
↓
↑
↓
↑
↓
F← FΛi3~i0
operation
i3 i2 i1 i0 ↓
C← 1
instructions SCF
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
C← 0
RCF
SZF
RZF
SDF
RDF
EI
Z← 1
↑
↓
Z← 0
D← 1 (Decimal Adjuster ON)
D← 0 (Decimal Adjuster OFF)
I← 1 (Enables Interrupt)
I← 0 (Disables Interrupt)
SP← SP+1
↑
↓
↑
↓
DI
Stack
INC
SP
SP← SP-1
operation
DEC SP
SP← SP-1, M(SP)← r
SP← SP-1, M(SP)← XP
SP← SP-1, M(SP)← XH
SP← SP-1, M(SP)← XL
SP← SP-1, M(SP)← YP
SP← SP-1, M(SP)← YH
SP← SP-1, M(SP)← YL
SP← SP-1, M(SP)← F
r← M(SP), SP← SP+1
XP← M(SP), SP← SP+1
XH← M(SP), SP← SP+1
XL← M(SP), SP← SP+1
YP← M(SP), SP← SP+1
instructions PUSH
r
r1 r0
XP
XH
XL
YP
YH
YL
F
0
0
1
1
0
0
1
0
1
0
1
0
1
0
POP
r
r1 r0
XP
XH
XL
YP
0
0
1
1
0
1
0
1
18
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
1
1
A
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
8
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
5
0
0
0
1
1
1
1
4
1
1
1
0
1
0
1
3
1
1
1
0
0
0
0
2
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
I
D
Z
C
Stack
POP
YH
YL
F
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
YH← M(SP), SP← SP+1
operation
instructions
YL← M(SP), SP← SP+1
F← M(SP), SP← SP+1
SPH← r
↑
↓
↑
↓
↑
↓
↑
↓
LD
SPH, r 1
SPL, r
r, SPH 1
r, SPL
Arithmetic ADD r, i
r1 r0
r1 r0
r1 r0
r1 r0
1
SPL← r
r← SPH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
r← SPL
r1 r0 i3 i2 i1 i0
★ ↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
r← r+i3~i0
r← r+q
instructions
r, q
ADC r, i
r, q
0
0
r1 r0 q1 q0 ★ ↑
↓
r1 r0 i3 i2 i1 i0
★ ↑
↓
r← r+i3~i0+C
r← r+q+C
r← r-q
0
1
1
0
r1 r0 q1 q0 ★ ↑
↓
SUB r, q
r1 r0 q1 q0 ★ ↑
↓
SBC
r, i
r1 r0 i3 i2 i1 i0
★ ↑
↓
↑
↓
↑
↓
r← r-i3~i0-C
r← r-q-C
r← rΛi3~i0
r← rΛq
r, q
1
1
r1 r0 q1 q0 ★ ↑
↓
AND r, i
r, q
r1 r0 i3 i2 i1 i0
r1 r0 q1 q0
r1 r0 i3 i2 i1 i0
r1 r0 q1 q0
r1 r0 i3 i2 i1 i0
r1 r0 q1 q0
r1 r0 i3 i2 i1 i0
r1 r0 q1 q0
r1 r0 i3 i2 i1 i0
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
★ ↑
↓
★ ↑
↓
★ ↑
↓
0
0
OR
r, i
r← rVi3~i0
r← rVq
r, q
0
1
XOR r, i
r, q
r← r∀i3~i0
r← r∀q
1
0
CP
r, i
↑
↓
↑
↓
r-i3~i0
r, q
0
0
r-q
FAN r, i
r, q
rΛi3~i0
0
1
0
1
1
1
1
1
1
1
1
0
r1 r0 q1 q0
r1 r0 r1 r0
rΛq
RLC
RRC
INC
r
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
d3← d2, d2← d1, d1← d0, d0← C, C← d3
d3← C, d2← d3, d1← d2, d0← d1, C← d0
M(n3~n0)← M(n3~n0)+1
r
1
1
r1 r0
Mn
0 n3 n2 n1 n0
1 n3 n2 n1 n0
DEC Mn
M(n3~n0)← M(n3~n0)-1
ACPX MX, r
ACPY MY, r
SCPX MX, r
SCPY MY, r
0
0
1
1
1
1
1
1
1
0
1
0
1
1
r1 r0
r1 r0
r1 r0
r1 r0
M(X)← M(X)+r+C, X← X+1
M(Y)← M(Y)+r+C, Y← Y+1
M(X)← M(X)-r-C, X← X+1
M(Y)← M(Y)-r-C, Y← Y+1
r← r
★ ↑
↓
↑
↓
NOT
r
r1 r0
1
1
S1C6200/6200A CORE CPU MANUAL
EPSON
19
3 INSTRUCTION SET
3.1.2 In alphabetical order
Operation Code
Flag
Mne-
monic
Page
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
0
A
1
1
1
0
0
0
0
0
1
0
1
0
1
9
1
1
0
1
1
1
1
1
0
1
0
1
0
8
1
1
0
0
0
0
0
0
0
0
0
0
7
0
0
0
1
0
0
0
0
0
1
1
1
6
0
0
1
0
0
0
0
0
0
0
0
1
5
1
1
4
0
0
3
1
1
2
0
1
1
0
I
D
Z
C
28 ACPX MX, r
28 ACPY MY, r
29 ADC r, i
r1 r0
r1 r0
★ ↑ ↑
↓ ↓
★ ↑ ↑
↓ ↓
★ ↑ ↑
↓ ↓
7
7
7
7
7
7
7
7
7
7
7
7
7
M(X)← M(X)+r+C, X← X+1
M(Y)← M(Y)+r+C, Y← Y+1
r1 r0 i3 i2 i1 i0
r← r+i3~i0+C
29
30
30
31
31
r, q
0
0
0
1
1
1
0
1
0
1
r1 r0 q1 q0 ★ ↑ ↑
↓ ↓
r← r+q+C
XH, i
XL, i
YH, i
YL, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
XH← XH+i3~i0+C
XL← XL+i3~i0+C
YH← YH+i3~i0+C
YL← YL+i3~i0+C
32 ADD r, i
32 r, q
33 AND r, i
r1 r0 i3 i2 i1 i0
★ ↑ ↑
↓ ↓
r1 r0 q1 q0 ★ ↑ ↑
↓ ↓
r← r+i3~i0
0
0
r← r+q
r1 r0 i3 i2 i1 i0
↑
↓
↑
↓
r← rΛi3~i0
33
r, q
s
0
0
r1 r0 q1 q0
r← rΛq
34 CALL
0 s7 s6 s5 s4 s3 s2 s1 s0
M(SP-1)← PCP, M(SP-2)← PCSH, M(SP-3)← PCSL+1
SP← SP-3, PCP← NPP, PCS← s7~s0
34 CALZ
s
0
1
0
1 s7 s6 s5 s4 s3 s2 s1 s0
7
M(SP-1)← PCP, M(SP-2)← PCSH, M(SP-3)← PCSL+1
SP← SP-3, PCP← 0, PCS← s7~s0
35 CP
35
r, i
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
r1 r0 i3 i2 i1 i0
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
↑ ↑
↓ ↓
7
7
7
7
7
7
7
5
7
7
7
7
5
7
5
5
5
5
5
5
5
5
5
5
r-i3~i0
r, q
0
0
0
1
1
1
0
0
0
0
0
1
0
1
r1 r0 q1 q0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
r-q
36
XH, i
XL, i
YH, i
YL, i
XH-i3~i0
36
XL-i3~i0
37
YH-i3~i0
37
YL-i3~i0
38 DEC Mn
1 n3 n2 n1 n0
M(n3~n0)← M(n3~n0)-1
SP← SP-1
38
SP
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
39 DI
39 EI
↓
↑
I← 0 (Disables Interrupt)
I← 1 (Enables Interrupt)
rΛi3~i0
40 FAN r, i
r1 r0 i3 i2 i1 i0
↑
↓
↑
↓
40
r, q
0
1
1
0
1
1
1
1
1
r1 r0 q1 q0
rΛq
41 HALT
1
0
0
0
Halt (stop clock)
41 INC
Mn
SP
X
0 n3 n2 n1 n0
↑ ↑
↓ ↓
M(n3~n0)← M(n3~n0)+1
SP← SP+1
42
1
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
42
X← X+1
43
Y
Y← Y+1
43 JPBA
PCB← NBP, PCP← NPP, PCSH← B, PCSL← A
PCB← NBP, PCP← NPP, PCS← s7~s0 if C=1
PCB← NBP, PCP← NPP, PCS← s7~s0 if C=0
PCB← NBP, PCP← NPP, PCS← s7~s0 if Z=0
PCB← NBP, PCP← NPP, PCS← s7~s0
PCB← NBP, PCP← NPP, PCS← s7~s0 if Z=1
M(X)← e3~e0, M(X+1)← e7~e4, X← X+2
44 JP
44
C, s
NC, s
NZ, s
s
0 s7 s6 s5 s4 s3 s2 s1 s0
1 s7 s6 s5 s4 s3 s2 s1 s0
1 s7 s6 s5 s4 s3 s2 s1 s0
0 s7 s6 s5 s4 s3 s2 s1 s0
0 s7 s6 s5 s4 s3 s2 s1 s0
1 e7 e6 e5 e4 e3 e2 e1 e0
45
45
46
Z, s
46 LBPX MX, e
20
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
Operation Code
Flag
Mne-
monic
Page
Operand
Clock
Operation
B
1
1
1
1
1
1
A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
8
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
7
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
5
1
1
0
0
4
3
2
1
0
I
D
Z
C
47 LD
47
A, Mn
B, Mn
Mn, A
Mn, B
r, i
0 n3 n2 n1 n0
1 n3 n2 n1 n0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
5
5
5
5
5
5
5
5
A← M(n3~n0)
B← M(n3~n0)
M(n3~n0)← A
M(n3~n0)← B
r← i3~i0
r← q
48
48
51
r1 r0 i3 i2 i1 i0
r1 r0 q1 q0
51
r, q
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
52
r, SPH 1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
1
1
0
0
1
0
0
0
0
1
0
0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r← SPH
r← SPL
52
r, SPL
r, XH
r, XL
r, XP
r, YH
r, YL
r, YP
1
1
1
1
1
1
1
53
r← XH
53
r← XL
54
r← XP
54
r← YH
55
r← YL
55
r← YP
56
SPH, r 1
SPH← r
SPL← r
56
SPL, r
XH, r
XL, r
XP, r
X, e
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
57
XH← r
58
XL← r
58
XP← r
57
1 e7 e6 e5 e4 e3 e2 e1 e0
XH← e7~e4, XL← e3~e0
YH← r
59
YH, r
YL, r
YP, r
Y, e
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
r1 r0
r1 r0
r1 r0
60
YL← r
60
YP← r
59
0 e7 e6 e5 e4 e3 e2 e1 e0
YH← e7~e4, YL← e3~e0
M(X)← i3~i0, X← X+1
r← q, X ← X+1
49 LDPX MX, i
49 r, q
50 LDPY MY, i
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
i3 i2 i1 i0
r1 r0 q1 q0
i3 i2 i1 i0
r1 r0 q1 q0
M(Y)← i3~i0, Y← Y+1
r← q, Y← Y+1
50
r, q
61 NOP5
1
1
1
0
1
1
1
1
1
1
1
1
No operation (5 clock cycles)
No operation (7 clock cycles)
r← r
61 NOP7
62 NOT
r
r1 r0
↑
↓
↑
↓
↑
↓
62 OR
r, i
r, q
F
r1 r0 i3 i2 i1 i0
r← rVi3~i0
63
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
r1 r0 q1 q0
r← rVq
63 POP
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
↑ ↑ ↑ ↑
↓ ↓ ↓ ↓
F← M(SP), SP← SP+1
r← M(SP), SP← SP+1
XH← M(SP), SP← SP+1
XL← M(SP), SP← SP+1
XP← M(SP), SP← SP+1
YH← M(SP), SP← SP+1
YL← M(SP), SP← SP+1
YP← M(SP), SP← SP+1
64
64
65
65
66
66
67
r
r1 r0
XH
XL
XP
YH
YL
YP
0
1
0
0
0
1
1
0
0
0
1
1
S1C6200/6200A CORE CPU MANUAL
EPSON
21
3 INSTRUCTION SET
Operation Code
Flag
Mne-
monic
Page
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
A
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
8
0
1
1
1
1
1
1
1
1
1
1
1
7
0
1
1
1
1
1
1
1
1
0
0
1
6
1
1
1
1
1
1
1
1
1
1
1
1
5
4
3
2
1
0
I
D
Z
C
67 PSET
p
0 p4 p3 p2 p1 p0
5
5
5
5
5
5
5
5
5
7
7
7
NBP← p4, NPP← p3~p0
68 PUSH
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
0
1
1
0
SP← SP-1, M(SP)← F
SP← SP-1, M(SP)← r
68
r
r1 r0
69
XH
XL
XP
YH
YL
YP
0
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
SP← SP-1, M(SP)← XH
SP← SP-1, M(SP)← XL
SP← SP-1, M(SP)← XP
SP← SP-1, M(SP)← YH
SP← SP-1, M(SP)← YL
SP← SP-1, M(SP)← YP
C← 0
69
70
70
71
71
72 RCF
72 RDF
73 RET
↓
↓
D← 0 (Decimal Adjuster OFF)
PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3
73 RETD
74 RETS
e
0
1
0
1
0
1
1 e7 e6 e5 e4 e3 e2 e1 e0
12 PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3, M(X)← e3~e0, M(X+1)← e7~e4, X← X+2
12 PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3, PC← PC+1
1
1
1
0
1
1
1
1
0
74 RLC
75 RRC
75 RST
76 RZF
76 SBC
77
r
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
1
1
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
r1 r0 r1 r0
r1 r0
i3 i2 i1 i0 ↓ ↓ ↓ ↓
↑ ↑
7
5
7
7
7
7
7
7
7
7
7
5
7
7
7
7
d3← d2, d2← d1, d1← d0, d0← C, C← d3
↓ ↓
r
1
1
↑ ↑
↓ ↓
d3← C, d2← d3, d1← d2, d0← d1, C← d0
F, i
F← FΛi3~i0
1
1
0
1
↓
Z← 0
r, i
r1 r0 i3 i2 i1 i0
★ ↑ ↑
↓ ↓
r1 r0 q1 q0 ★ ↑ ↑
↓ ↓
r← r-i3~i0-C
r, q
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
0
0
r← r-q-C
77 SCF
0
1
1
0
0
0
1
1
0
1
↑
C← 1
78 SCPX MX, r
78 SCPY MY, r
79 SDF
r1 r0
r1 r0
★ ↑ ↑
↓ ↓
★ ↑ ↑
↓ ↓
M(X)← M(X)-r-C, X← X+1
M(Y)← M(Y)-r-C, Y← Y+1
D← 1 (Decimal Adjuster ON)
F← FVi3~i0
0
0
↑
79 SET
80 SLP
F, i
i3 i2 i1 i0 ↑ ↑ ↑ ↑
1
0
0
1
SLEEP (stop oscillation)
r← r-q
80 SUB r, q
81 SZF
r1 r0 q1 q0 ★ ↑ ↑
↓ ↓
0
0
1
0
↑
Z← 1
81 XOR r, i
r1 r0 i3 i2 i1 i0
r1 r0 q1 q0
↑
↓
↑
↓
r← r∀i3~i0
82
r, q
1
0
r← r∀q
22
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
3.1.3 By operation code
Operation Code
Flag
Operation
Code (HEX)
Mne-
monic
Operand
Clock
Operation
B
0
0
A
0
0
9
0
0
8
7
6
5
4
3
2
1
0
I
D
Z
C
000 to 0FF JP
s
0
s7 s6 s5 s4 s3 s2 s1 s0
5
PCB← NBP, PCP← NPP, PCS← s7~s0
100 to 1FF RETD
e
1 e7 e6 e5 e4 e3 e2 e1 e0
12 PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3, M(X)← e3~e0, M(X+1)← e7~e4, X← X+2
200 to 2FF JP
300 to 3FF JP
400 to 4FF CALL
C, s
NC, s
s
0
0
0
0
0
1
1
1
0
0
1
0
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
5
5
7
PCB← NBP, PCP← NPP, PCS← s7~s0 if C=1
PCB← NBP, PCP← NPP, PCS← s7~s0 if C=0
M(SP-1)← PCP, M(SP-2)← PCSH, M(SP-3)← PCSL+1
SP← SP-3, PCP← NPP, PCS← s7~s0
500 to 5FF CALZ
s
0
1
0
1
s7 s6 s5 s4 s3 s2 s1 s0
7
M(SP-1)← PCP, M(SP-2)← PCSH, M(SP-3)← PCSL+1
SP← SP-3, PCP← 0, PCS← s7~s0
600 to 6FF JP
700 to 7FF JP
800 to 8FF LD
Z, s
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
s7 s6 s5 s4 s3 s2 s1 s0
s7 s6 s5 s4 s3 s2 s1 s0
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
7
7
5
PCB← NBP, PCP← NPP, PCS← s7~s0 if Z=1
NZ, s
Y, e
PCB← NBP, PCP← NPP, PCS← s7~s0 if Z=0
0 e7 e6 e5 e4 e3 e2 e1 e0
1 e7 e6 e5 e4 e3 e2 e1 e0
YH← e7~e4, YL← e3~e0
900 to 9FF LBPX MX, e
A00 to A0F ADC XH, i
A10 to A1F ADC XL, i
A20 to A2F ADC YH, i
A30 to A3F ADC YL, i
M(X)← e3~e0, M(X+1)← e7~e4, X← X+2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
XH← XH+i3~i0+C
XL← XL+i3~i0+C
YH← YH+i3~i0+C
YL← YL+i3~i0+C
XH-i3~i0
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
A40 to A4F CP
A50 to A5F CP
A60 to A6F CP
A70 to A7F CP
XH, i
XL, i
YH, i
YL, i
XL-i3~i0
YH-i3~i0
YL-i3~i0
A80 to A8F ADD r, q
A90 to A9F ADC r, q
AA0 to AAF SUB r, q
r1 r0 q1 q0 ★ ↑
r← r+q
↓
r1 r0 q1 q0 ★ ↑
r← r+q+C
↓
r1 r0 q1 q0 ★ ↑
r← r-q
↓
AB0 to ABF SBC
AC0 to ACF AND r, q
AD0 to ADF OR r, q
AE0 to AEF XOR r, q
r, q
r1 r0 q1 q0 ★ ↑
r← r-q-C
↓
↑
↓
↑
↓
↑
↓
r1 r0 q1 q0
r1 r0 q1 q0
r1 r0 q1 q0
r1 r0 r1 r0
r← rΛq
r← rVq
r← r∀q
AF0 to AFF RLC
r
↑
↓
↑
↓
d3← d2, d2← d1, d1← d0, d0← C, C← d3
XH← e7~e4, XL← e3~e0
r← r+i3~i0
B00 to BFF LD
X, e
1 e7 e6 e5 e4 e3 e2 e1 e0
C00 to C3F ADD r, i
C40 to C7F ADC r, i
C80 to CBF AND r, i
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
★ ↑
↓
★ ↑
↓
↑
↓
↑
↓
↑
↓
↑
↓
★ ↑
↓
↑
↓
↑
↓
↑
↓
r← r+i3~i0+C
r← rΛi3~i0
r← rVi3~i0
CC0 to CFF OR
r, i
D00 to D3F XOR r, i
r← r∀i3~i0
r← r
D0F to D3F NOT
r
r1 r0
1
1
1
1
D40 to D7F SBC
r, i
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
r1 r0 i3 i2 i1 i0
↑
↓
r← r-i3~i0-C
rΛi3~i0
D80 to DBF FAN r, i
DC0 to DFF CP
r, i
r, i
↑
↓
↑
↓
r-i3~i0
E00 to E3F LD
r← i3~i0
S1C6200/6200A CORE CPU MANUAL
EPSON
23
3 INSTRUCTION SET
Operation Code
Flag
Operation
Code (HEX)
Mne-
monic
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
6
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
5
4
3
2
1
0
I
D
Z
C
E40 to E5F PSET
p
0 p4 p3 p2 p1 p0
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
NBP← p4, NPP← p3~p0
E60 to E6F LDPX MX, i
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
1
1
1
1
1
i3 i2 i1 i0
i3 i2 i1 i0
M(X)← i3~i0, X← X+1
E70 to E7F LDPY MY, i
M(Y)← i3~i0, Y← Y+1
E80 to E83 LD
E84 to E87 LD
E88 to E8B LD
E8C to E8F RRC
E90 to E93 LD
E94 to E97 LD
E98 to E9B LD
EA0 to EA3 LD
EA4 to EA7 LD
EA8 to EAB LD
EB0 to EB3 LD
EB4 to EB7 LD
EB8 to EBB LD
EC0 to ECF LD
XP, r
XH, r
XL, r
r
0
0
1
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
r1 r0
XP← r
XH← r
XL← r
↑
↑
d3← C, d2← d3, d1← d2, d0← d1, C← d0
↓
↓
YP, r
YH, r
YL, r
r, XP
r, XH
r, XL
r, YP
r, YH
r, YL
r, q
YP← r
YH← r
YL← r
r← XP
r← XH
r← XL
r← YP
r← YH
r← YL
r1 r0 q1 q0
r← q
EE0
INC
X
0
0
0
0
X← X+1
EE0 to EEF LDPX r, q
EF0 INC
EF0 to EFF LDPY r, q
F00 to F0F CP r, q
r1 r0 q1 q0
r← q, X← X+1
Y← Y+1
Y
0
0
0
0
r1 r0 q1 q0
r1 r0 q1 q0
r1 r0 q1 q0
r← q, Y← Y+1
r-q
↑
↓
↑
↓
★ ↑
↓
★ ↑
↓
★ ↑
↓
★ ↑
↓
↑
↑
↓
F10 to F1F FAN r, q
F28 to F2B ACPX MX, r
F2C to F2F ACPY MY, r
F38 to F3B SCPX MX, r
F3C to F3F SCPY MY, r
rΛq
1
1
1
1
0
1
0
1
r1 r0
r1 r0
r1 r0
r1 r0
↑
↓
↑
↓
↑
↓
↑
↓
↑
↑
M(X)← M(X)+r+C, X← X+1
M(Y)← M(Y)+r+C, Y← Y+1
M(X)← M(X)-r-C, X← X+1
M(Y)← M(Y)-r-C, Y← Y+1
F← FVi3~i0
F40 to F4F SET
F, i
F, i
Mn
i3 i2 i1 i0 ↑
↑
F41
F42
F44
F48
SCF
SZF
SDF
EI
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
C← 1
↑
Z← 1
↑
↓
↓
D← 1 (Decimal Adjuster ON)
I← 1 (Enables Interrupt)
F← FΛi3~i0
↑
F50 to F5F RST
i3 i2 i1 i0 ↓
↓
↓
↓
F57
F5B
F5D
F5E
DI
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
↓
I← 0 (Disables Interrupt)
D← 0 (Decimal Adjuster OFF)
Z← 0
RDF
RZF
RCF
↓
C← 0
F60 to F6F INC
0 n3 n2 n1 n0
1 n3 n2 n1 n0
0 n3 n2 n1 n0
↑
↓
↑
↓
↑
↓
↑
↓
M(n3~n0)← M(n3~n0)+1
M(n3~n0)← M(n3~n0)-1
M(n3~n0)← A
F70 to F7F DEC Mn
F80 to F8F LD Mn, A
24
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
Operation Code
Flag
Operation
Code (HEX)
Mne-
monic
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
I
D
Z
C
F90 to F9F LD
FA0 to FAF LD
FB0 to FBF LD
FC0 to FC3 PUSH
Mn, B
A, Mn
B, Mn
r
1 n3 n2 n1 n0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
M(n3~n0)← B
A← M(n3~n0)
B← M(n3~n0)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
r1 r0
SP← SP-1, M(SP)← r
FC4
FC5
FC6
FC7
FC8
FC9
FCA
FCB
PUSH XP
PUSH XH
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SP← SP-1, M(SP)← XP
SP← SP-1, M(SP)← XH
SP← SP-1, M(SP)← XL
SP← SP-1, M(SP)← YP
SP← SP-1, M(SP)← YH
SP← SP-1, M(SP)← YL
SP← SP-1, M(SP)← F
SP ← SP-1
PUSH XL
PUSH YP
PUSH YH
PUSH YL
PUSH
F
DEC SP
FD0 to FD3 POP
r
r1 r0
r← M(SP), SP← SP+1
XP← M(SP), SP← SP+1
XH← M(SP), SP←SP+1
XL← M(SP), SP← SP+1
YP← M(SP), SP← SP+1
YH← M(SP), SP← SP+1
YL← M(SP), SP← SP+1
F← M(SP), SP← SP+1
SP← SP+1
FD4
FD5
FD6
FD7
FD8
FD9
FDA
FDB
FDE
POP
POP
POP
POP
POP
POP
POP
INC
RETS
XP
XH
XL
YP
YH
YL
F
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
↑
↓
↑
↓
↑
↓
↑
↓
SP
12 PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3, PC← PC+1
FDF
RET
1
1
1
1
1
1
0
1
1
1
1
1
7
PCSL← M(SP), PCSH← M(SP+1), PCP← M(SP+2)
SP← SP+3
FE0 to FE3 LD
SPH, r 1
r, SPH 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
0
0
0
1
r1 r0
r1 r0
5
5
5
5
5
5
5
5
7
SPH← r
FE4 to FE7 LD
r← SPH
FE8
JPBA
0
0
PCB← NBP, PCP← NPP, PCSH← B, PCSL← A
SPL← r
FF0 to FF3 LD
FF4 to FF7 LD
SPL, r
r, SPL
1
1
1
1
1
1
r1 r0
r1 r0
r← SPL
FF8
FF9
FFB
FFF
HALT
0
0
1
1
0
1
1
1
Halt (stop clock)
SLP
SLEEP (stop oscillation)
No operation (5 clock cycles)
No operation (7 clock cycles)
NOP5
NOP7
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3 INSTRUCTION SET
3.2 Operands
This section describes the operands used in the instructions.
p
s
e
i
5-bit immediate data or labels 00H to 1FH. Used to specify a destination address.
8-bit immediate data or labels 00H to FFH. Used to specify a destination address.
8-bit immediate data 00H to FFH.
4-bit immediate data 00H to 0FH.
r
q
2-bit immediate data. See Table 3.2.1.
2-bit immediate data. See Table 3.2.1.
The contents of A, B, MX, MY are referenced using r and q as shown in the following table.
Table 3.2.1 Values of r and q
r1 or q1
r0 or q0
A
B
0
0
1
1
0
1
0
1
MX
MY
A
B
A register
B register
XP
YP
X
XP register---four high-order bits of IX
YP register---four high-order bits of IY
XHL register---eight low-order bits of IX
YHL register---eight low-order bits of IY
XH register---four high-order bits of XHL
XL register---four low-order bits of XHL
YH register---four high-order bits of YHL
YL register---four low-order bits of YHL
Stack pointer SP
Y
XH
XL
YH
YL
SP
SPH Four high-order bits of SP
SPL Four low-order bits of SP
F
Flag register (IF, DF, ZF, CF)
MX
MY
Mn
C
Data memory location whose address is specified by IX
Data memory location whose address is specified by IY
Data memory location within the register area (000H to 00FH), specified by immediate data n (0H to FH)
Carry
NC
Z
No carry
Zero
NZ
Not zero
3.3 Flags
1. Carry flag
The carry flag is set if a carry was generated by the previous operation. It is affected by 17 arithmetic
and logical instructions, four flag operations, eight index operation instructions and the POP F instruc-
tion.
2. Zero flag
The zero flag is set if a zero occurred in the previous operation. It is affected by 26 arithmetic and logical
instructions, four flag operations, eight index operation instructions and the POP F instruction.
3. Decimal flag
The decimal flag enables decimal addition and subtraction when set. It is set by SDF or SET F,i and reset
by RDF or RST F,i. It is affected by the POP F instruction.
4. Interrupt flag
The interrupt flag enables interrupts when set. It is set by EI or SET F,i and reset by DI or RST F,i. It is
affected by the POP F instruction. When an interrupt is generated, the I flag is automatically reset. It is
not automatically set at the end of the interrupt service routine.
26
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3 INSTRUCTION SET
3.4 Instruction Types
Instructions are divided into six types according to the size of the operand.
(I)
MSB
LSB
LSB
LSB
LSB
ex: JP
CALL
s
s
Op-code
8-bit operand
LBPX MX,e
etc.
etc.
(II) MSB
(III) MSB
(IV) MSB
(V) MSB
(VI) MSB
ex: ADD
r, i
r, i
r, i
Op-code
6-bit operand
LD
FAN
ex: PSET
p
Op-code
5-bit operand
ex: SET
LD
F, i
r, q
Mn
Op-code
4-bit operand
INC
etc.
etc.
etc.
LSB
ex: ACPX MX, r
2-bit
operand
Op-code
LD
PUSH
XH, r
r
LSB
ex: JPBA
POP
Op-code
YL
X
INC
3.5 Instruction Descriptions
This section describes S1C6200/ 6200A instructions in alphabetical order.
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
ACPX MX,r
Add with carry r-register to M(X), increment X by 1
Source Format:
ACPX MX,r
Operation:
M(X) ← M(X) + r + C, X ← X + 1
OP-Code:
1
MSB
1
1
1
0
0
1
0
1
0
r1 r0
LSB
F28H to F2BH
Type:
Clock Cycles:
Flag:
V
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and the contents of the r-register to the data memory location
addressed by IX. X is incremented by one. Incrementing X does not affect the
flags.
ACPX MX,A
ACPX MX,MY
X register
Y register
Memory (A0H)
Memory (A1H)
Memory (46H)
A register
C flag
1010 0000
0100 0110
0110
0011
0100
1000
1
1010 0001
0100 0110
1010 0010
0100 0110
1111
0111
0100
1000
0
1111
0011
0100
1000
0
Z flag
0
0
0
ACPY MY,r
Add with carry r-register to M(Y), increment Y by 1
Source Format:
Operation:
ACPY MY,r
M(Y) ← M(Y) + r + C, Y ← Y + 1
OP-Code:
1
MSB
1
1
1
0
0
1
0
1
1
r1 r0
LSB
F2CH to F2FH
Type:
Clock Cycles:
Flag:
V
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and the contents of the r-register to the data memory location
addressed by IY. Y is incremented by one. Incrementing Y does not affect the
flags.
ACPY MY,A
ACPY MY,MX
X register
Y register
Memory (0EH)
Memory (0FH)
Memory (21H)
A register
C flag
0010 0001
0000 1110
1000
0100
0110
0010
1
0010 0001
0000 1111
0010 0001
0001 0000
1011
1010
0110
0010
0
1011
0100
0110
0010
0
Z flag
0
0
0
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3 INSTRUCTION SET
ADC r,i
Add with carry immediate data i to r-register
Source Format:
ADC r,i
Operation:
OP-Code:
r ← r + i3 to i0 + C
1
1
0
0
0
1
r1 r0 i3 i2 i1 i0
LSB
C40H to C7FH
MSB
Type:
Clock Cycles:
Flag:
II
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and immediate data i to the r-register.
ADC MX,3
ADC B,7
Memory (MX)
B register
C flag
0100
1001
1
1000
1001
0
1000
0000
1
Z flag
1
0
1
ADC r,q
Add with carry q-register to r-register
Source Format:
Operation:
ADC r,q
r ← r + q + C
OP-Code:
1
MSB
0
1
0
1
0
0
1
r1 r0 q1 q0
LSB
A90H to A9FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and the contents of the q-register to the r-register.
ADC MY,A
ADC MX,B
A register
B register
Memory (MX)
Memory (MY)
C flag
0101
0001
0111
1011
1
0101
0001
0111
0001
1
0101
0001
1001
0001
0
Z flag
0
0
0
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
ADC XH,i
Add with carry immediate data i to XH
Source Format:
ADC XH,i
Operation:
XH ← XH + i3 to i0 + C
OP-Code:
1
MSB
0
1
0
0
0
0
0
i3 i2 i1 i0
LSB
A00H to A0FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and immediate data i to XH, the four high-order bits of XHL.
ADC XH,2
ADC XH,4
XH register
C flag
Z flag
1001
1
0
1100
0
0
0000
1
1
ADC XL,i
Add with carry immediate data i to XL
Source Format:
Operation:
ADC XL,i
XL ← XL + i3 to i0 + C
OP-Code:
1
MSB
0
1
0
0
0
0
1
i3 i2 i1 i0
LSB
A10H to A1FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and immediate data i to XL, the four low-order bits of XHL.
ADC XL,3
ADC XL,0EH
XL register
C flag
Z flag
0000
1
1
0100
0
0
0010
1
0
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
ADC YH,i
Add with carry immediate data i to YH
Source Format:
ADC YH,i
Operation:
OP-Code:
YH ← YH + i3 to i0 + C
1
0
1
0
0
0
1
0
i3 i2 i1 i0
LSB
A20H to A2FH
MSB
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and immediate data i to YH, the four high-order bits of YHL.
ADC YH,3
ADC YH,6
YH register
C flag
Z flag
1010
1
0
1110
0
0
0100
1
0
ADC YL,i
Add with carry immediate data i to YL
Source Format:
Operation:
ADC YL,i
YL ← YL + i3 to i0 + C
OP-Code:
1
MSB
0
1
0
0
0
1
1
i3 i2 i1 i0
LSB
A30H to A3FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the carry bit and immediate data i to YL, the four low-order bits of YHL.
ADC YL,3
ADC YL,2
YL register
C flag
Z flag
1010
1
0
1110
0
0
0000
1
1
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
ADD r,i
Add immediate data i to r-register
Source Format:
ADD r,i
Operation:
r ← r + i3 to i0
OP-Code:
1
MSB
1
0
0
0
0
r1 r0 i3 i2 i1 i0
LSB
C00H to C3FH
Type:
Clock Cycles:
Flag:
II
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds immediate data i to the contents of the r-register.
ADD A,5
ADD MY,2
A register
Memory (MY)
C flag
1010
0110
1
1111
0110
0
1111
1000
0
Z flag
0
0
0
ADD r,q
Add q-register to r-register
Source Format:
Operation:
ADD r,q
r ← r + q
OP-Code:
1
MSB
0
1
0
1
0
0
0
r1 r0 q1 q0
LSB
A80H to A8FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Adds the contents of the q-register to the contents of the r-register.
ADD A,MY
ADD MX,B
A register
B register
Memory (MX)
Memory (MY)
C flag
0010
0100
0111
1101
1
1111
0100
0111
1101
0
1111
0100
1011
1101
0
Z flag
1
0
0
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
AND r,i
Logical AND immediate data i with r-register
Source Format:
AND r,i
Operation:
OP-Code:
r ← r ∧ i3 to i0
1
1
0
0
1
0
r1 r0 i3 i2 i1 i0
LSB
C80H to CBFH
MSB
Type:
Clock Cycles:
Flag:
II
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a logical AND operation between immediate data i and the contents of
the r-register. The result is stored in the r-register.
AND A,5
AND MX,3
A register
Memory (MX)
C flag
0110
1000
1
0100
1000
1
0100
0000
1
Z flag
0
0
1
AND r,q
Logical AND q-register with r-register
Source Format:
Operation:
AND r,q
r ← r ∧ q
OP-Code:
1
MSB
0
1
0
1
1
0
0
r1 r0 q1 q0
LSB
AC0H to ACFH
Type:
Clock Cycles:
Flag:
IV
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a logical AND operation between the contents of the q-register and the
contents of the r-register. The result is stored in the r-register.
AND MX,A
AND B,MY
A register
B register
Memory (MX)
Memory (MY)
C flag
0100
1011
1010
0010
0
0100
1011
0000
0010
0
0100
0010
0000
0010
0
Z flag
0
1
0
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
CALL s
Call subroutine
Source Format:
CALL s
Operation:
M(SP-1) ← PCP, M(SP-2) ← PCSH, M(SP-3) ← PCSL + 1, SP ← SP - 3,
PCP ← NPP, PCS ← s7 to s0
OP-Code:
0
1
0
0 s7 s6 s5 s4 s3 s2 s1 s0
LSB
400H to 4FFH
MSB
Type:
I
Clock Cycles:
7
Flag:
C– Not affected
Z – Not affected
D– Not affected
I – Not affected
Description:
Pushes the program counter (PCP, PCS) onto the stack as the return address,
then calls the subroutine addressed by NPP and the 8-bit operand.
Example:
PSET 06H
CALL 10H
PCP
PCS
NPP
SP
0011
0010 1100
0001
C0
0011
0010 1100
0110
0110
0001 0000
0110
BD
C0
Memory (SP-1)
Memory (SP-2)
Memory (SP-3)
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0011
0010
1101
CALZ s
Call subroutine at page zero
Source Format:
Operation:
CALZ s
M(SP-1) ← PCP, M(SP-2) ← PCSH, M(SP-3) ← PCSL + 1, SP ← SP - 3,
PCP ← 0, PCS ← s7 to s0
OP-Code:
0
1
0
1 s7 s6 s5 s4 s3 s2 s1 s0
LSB
500H to 5FFH
MSB
Type:
I
Clock Cycles:
7
Flag:
C– Not affected
Z – Not affected
D– Not affected
I – Not affected
Description:
Pushes the program counter (PCP, PCS) onto the stack as the return address,
then calls the subroutine addressed by the 8-bit operand. As NPP is reset to 0H,
only a subroutine in page 0 can be called.
Example:
CALZ 10H
PCP
PCS
SP
1010
0010 1110
CA
0000
0001 0000
C7
Memory (SP-1)
Memory (SP-2)
Memory (SP-3)
xxxx
xxxx
xxxx
1010
0010
1111
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3 INSTRUCTION SET
CP r,i
Compare immediate data i with r-register
Source Format:
CP r,i
Operation:
OP-Code:
r - i3 to i0
1
1
0
1
1
1
r1 r0 i3 i2 i1 i0
LSB
DC0H to DFFH
MSB
Type:
Clock Cycles:
Flag:
II
7
C – Set if r < i3 to i0; otherwise, reset.
Z – Set if r = i3 to i0; otherwise, reset.
D – Not affected
I – Not affected
Description:
Compares immediate data i to the r-register by subtracting i from the contents of r.
The r-register remains unchanged.
1. When Z = 0 and C = 0 then i < r
2. When Z = 1 and C = 0 then i = r
3. When Z = 0 and C = 1 then i > r
Example:
CP A,4
CP MX,7
CP B,2
A register
B register
Memory (MX)
C flag
0100
0100
1010
0010
0
0100
1010
0010
1
0100
1010
0010
1
1010
0010
0
Z flag
0
1
0
0
CP r,q
Compare q-register with r-register
Source Format:
CP r,q
Operation:
r - q
OP-Code:
1
MSB
1
1
1
0
0
0
0
r1 r0 q1 q0
LSB
F00H to F0FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if r < q; otherwise, reset.
Z – Set if r = q; otherwise, reset.
D – Not affected
I – Not affected
Description:
Compares the q-register to the r-register by subtracting the contents of q from the
contents of r. The registers remain unchanged.
1. When Z = 0 and C = 0 then q < r
2. When Z = 1 and C = 0 then q = r
3. When Z = 0 and C = 1 then q > r
Example:
CP A,B
CP MY,A
A register
B register
Memory (MY)
C flag
1000
1000
0100
0111
0
1000
0100
0111
1
0100
0111
0
Z flag
0
0
0
S1C6200/6200A CORE CPU MANUAL
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35
3 INSTRUCTION SET
CP XH,i
Compare immediate data i with XH
Source Format:
CP XH,i
Operation:
XH - i3 to i0
OP-Code:
1
MSB
0
1
0
0
1
0
0
i3 i2 i1 i0
LSB
A40H to A4FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if XH < i3 to i0; otherwise, reset.
Z – Set if XH = i3 to i0; otherwise, reset.
D – Not affected
I – Not affected
Description:
Compares immediate data i to XH by subtracting i from the contents of XH. XH
remains unchanged.
1. When Z = 0 and C = 0 then i < XH
2. When Z = 1 and C = 0 then i = XH
3. When Z = 0 and C = 1 then i > XH
Example:
CP XH,2
CP XH,4
CP XH,9
XH register
C flag
Z flag
0100
1
0
0100
0
0
0100
0
1
0100
1
0
CP XL,i
Compare immediate data i with XL
Source Format:
CP XL,i
Operation:
XL - i3 to i0
OP-Code:
1
MSB
0
1
0
0
1
0
1
i3 i2 i1 i0
LSB
A50H to A5FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if XL < i3 to i0; otherwise, reset.
Z – Set if XL = i3 to i0; otherwise, reset.
D – Not affected
I – Not affected
Description:
Compares immediate data i to XL by subtracting i from the contents of XL. XL
remains unchanged.
1. When Z = 0 and C = 0 then i < XL
2. When Z = 1 and C = 0 then i = XL
3. When Z = 0 and C = 1 then i > XL
Example:
CP XL,7
CP XL,9
CP XL,0AH
XL register
C flag
Z flag
1001
0
0
1001
0
0
1001
0
1
1001
1
0
36
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
CP YH,i
Compare immediate data i with YH
Source Format:
CP YH,i
Operation:
OP-Code:
YH - i3 to i0
1
0
1
0
0
1
1
0
i3 i2 i1 i0
LSB
A60H to A6FH
MSB
Type:
Clock Cycles:
Flag:
IV
7
C – Set if YH < i3 to i0; otherwise, reset.
Z – Set if YH = i3 to i0; otherwise, reset.
D – Not affected
I – Not affected
Description:
Compares immediate data i to YH by subtracting i from the contents of YH. YH
remains unchanged.
1. When Z = 0 and C = 0 then i < YH
2. When Z = 1 and C = 0 then i = YH
3. When Z = 0 and C = 1 then i > YH
Example:
CP YH,0AH
CP YH,3
CP YH,0FH
YH register
C flag
Z flag
1010
1
0
1010
0
1
1010
0
0
1010
1
0
CP YL,i
Compare immediate data i with YL
Source Format:
CP YL,i
Operation:
YL - i3 to i0
OP-Code:
1
MSB
0
1
0
0
1
1
1
i3 i2 i1 i0
LSB
A70H to A7FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if YL < i3 to i0; otherwise, reset.
Z – Set if YL = i3 to i0; otherwise, reset.
D – Not affected
I – Not affected
Description:
Compares immediate data i to YL by subtracting i from the contents of YL. YL
remains unchanged.
1. When Z = 0 and C = 0 then i < YL
2. When Z = 1 and C = 0 then i = YL
3. When Z = 0 and C = 1 then i > YL
Example:
CP YL,5
CP YL,1
CP YL,4
YL register
C flag
Z flag
0100
0
1
0100
1
0
0100
0
0
0100
0
1
S1C6200/6200A CORE CPU MANUAL
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37
3 INSTRUCTION SET
DEC Mn
Decrement memory
Source Format:
DEC Mn
Operation:
M(n3 to n0) ← M(n3 to n0) - 1
OP-Code:
1
MSB
1
1
1
0
1
1
1 n3 n2 n1 n0
LSB
F70H to F7FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a borrow is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Decrements the contents of the data memory location addressed by Mn by 1.
DEC M0
DEC M2
DEC M0FH
Memory (00H)
Memory (02H)
Memory (0FH)
C flag
1001
1000
0000
0001
0
1000
1111
0001
1
1000
1111
0000
0
0000
0001
1
Z flag
0
0
0
1
DEC SP
Decrement stack pointer
Source Format:
Operation:
DEC SP
SP ← SP - 1
OP-Code:
1
1
1
1
1
1
0
0
1
0
1
1
FCBH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the contents of the stack pointer by 1. This operation does not affect
the flags.
DEC SP
Memory (SP)
C flag
Z flag
1011 0001
1011 0000
0
1
0
1
38
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
DI
Disable interrupts
Source Format:
Operation:
DI
I ← 0
OP-Code:
1
1
1
1
0
1
0
1
0
1
1
1
F57H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Not affected
D – Not affected
I – Reset
Description:
Example:
Disables all interrupts.
DI
C flag
Z flag
D flag
I flag
0
1
0
1
0
1
0
0
EI
Enable interrupts
Source Format:
Operation:
EI
I ← 1
OP-Code:
1
1
1
1
0
1
0
0
1
0
0
0
F48H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Not affected
D – Not affected
I – Set
Description:
Example:
Enables all interrupts.
EI
C flag
Z flag
D flag
I flag
1
0
0
0
1
0
0
1
S1C6200/6200A CORE CPU MANUAL
EPSON
39
3 INSTRUCTION SET
FAN r,i
Logical AND immediate data i with r-register for flag check
Source Format:
FAN r,i
Operation:
r ∧ i3 to i0
OP-Code:
1
MSB
1
0
1
1
0
r1 r0 i3 i2 i1 i0
LSB
D80H to DBFH
Type:
Clock Cycles:
Flag:
II
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a logical AND operation between immediate data i and the contents of
the r-register. Only the Z flag is affected. The r-register remains unchanged.
FAN A,7
FAN MY,9
FAN B,2
A register
B register
Memory (MY)
C flag
1000
0100
1000
1
1000
1000
0100
1000
1
1000
0100
1000
1
0100
1000
1
Z flag
0
1
0
1
FAN r,q
Logical AND q-register with r-register for flag check
Source Format:
Operation:
FAN r,q
r ∧ q
OP-Code:
1
MSB
1
1
1
0
0
0
1
r1 r0 q1 q0
LSB
F10H to F1FH
Type:
Clock Cycles:
Flag:
IV
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a logical AND operation between the contents of the q-register and the
contents of the r-register. Only the Z flag is affected. The registers remains
unchanged.
FAN A,B
FAN MX,B
FAN A,MY
A register
B register
Memory (MX)
Memory (MY)
C flag
1000
1010
0101
1110
0
1000
1000
1010
0101
1110
0
1000
1010
0101
1110
0
1010
0101
1110
0
Z flag
0
0
1
0
40
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
HALT
Halt
Source Format:
HALT
Operation:
OP-Code:
Stops CPU
1
1
1
1
1
1
1
1
1
0
0
0
FF8H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Stops the CPU. When an interrupt occurs, PCP and PCS are pushed onto the
stack as the return address and the interrupt service routine is executed.
Instruction
State
RUN
PCP
PCS
I flag
HALT
0001
0011 0011
1
HALT
Interrupt
0001
0011 0100
1
0
RUN
0001 Interrupt vector address
INC Mn
Increment memory by 1
Source Format:
Operation:
INC Mn
M(n3 to n0) ← M(n3 to n0) + 1
OP-Code:
1
MSB
1
1
1
0
1
1
0 n3 n2 n1 n0
LSB
F60H to F6FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a carry is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
The contents of the data memory location addressed by Mn is incremented by 1.
INC M1
INC M3
INC M0DH
Memory (01H)
Memory (03H)
Memory (0DH)
C flag
0100
0101
1111
0111
0
0101
0000
0111
1
0101
0000
1000
0
1111
0111
0
Z flag
1
0
1
0
S1C6200/6200A CORE CPU MANUAL
EPSON
41
3 INSTRUCTION SET
INC SP
Increment stack pointer by 1
Source Format:
INC SP
Operation:
SP ← SP + 1
OP-Code:
1
1
1
1
1
1
0
1
1
0
1
1
FDBH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Increments the contents of the stack pointer by 1. This operation does not affect
the flags.
INC SP
SP
1110 1111
1111 0000
C flag
Z flag
0
0
0
0
INC X
Increment X-register by 1
Source Format:
Operation:
INC X
X ← X + 1
OP-Code:
1
1
1
0
1
1
1
0
0
0
0
0
EE0H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Increments the contents of register X by 1. This operation does not affect the
flags.
INC X
X register
C flag
Z flag
1111 1110
1111 1111
1
0
1
0
42
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
INC Y
Increment Y-register by 1
Source Format:
INC Y
Operation:
OP-Code:
Y ← Y + 1
1
1
1
0
1
1
1
1
0
0
0
0
EF0H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Increments the contents of register Y by 1. This operation does not affect the
flags.
INC Y
Y register
C flag
Z flag
1011 0111
1011 1000
1
0
1
0
JPBA
Indirect jump using registers A and B
Source Format:
Operation:
JPBA
PCB ← NBP, PCP ← NPP, PCSH ← B, PCSL ← A
OP-Code:
1
1
1
1
1
1
1
0
1
0
0
0
FE8H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Uses the contents of a- and b-registers to specify the destination address of the
jump. The b-register contains the four high-order bits of the address and the a-
register contains the four low-order bits of the address.
PSET 15H
JPBA
PCB
NBP
0
0
0
1
1
1
PCP
NPP
PCS
A register
B register
1000
0001
1001 0000
0110
0000
1000
0101
1001 0001
0110
0000
0101
0101
0000 0110
0110
0000
S1C6200/6200A CORE CPU MANUAL
EPSON
43
3 INSTRUCTION SET
JP C,s
Jump if carry flag is set
Source Format:
JP C,s
Operation:
PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if C = 1
OP-Code:
0
MSB
0
1
0 s7 s6 s5 s4 s3 s2 s1 s0
LSB
200H to 2FFH
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Jumps to the destination address specified by the 8-bit operand when the carry
flag is set.
ADD A,8
PSET 06H
JP C,10H
PCB
NBP
0
0
0
0
0
0
0
0
PCP
NPP
PCS
A register
C flag
0010
0001
0011 1100
1000
0
0010
0001
0011 1101
0000
0010
0110
0011 1110
0000
1
0110
0110
0001 0000
0000
1
1
JP NC,s
Jump if not carry
Source Format:
Operation:
JP NC,s
PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if C = 0
OP-Code:
0
MSB
0
1
1 s7 s6 s5 s4 s3 s2 s1 s0
LSB
300H to 3FFH
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Jumps to the destination address specified by the 8-bit operand when the carry
flag is not set.
PSET 11H
JP NC,10H
PCB
NBP
PCP
NPP
PCS
C flag
0
0
0
1
1
1001
0001
1001 0000
0
1
0001
0001
0001 0000
0
1001
0001
1000 1111
0
44
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
JP NZ,s
Jump if not zero
Source Format:
JP NZ,s
Operation:
OP-Code:
PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if Z = 0
0
1
1
1 s7 s6 s5 s4 s3 s2 s1 s0
LSB
700H to 7FFH
MSB
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Jumps to the destination address specified by the 8-bit operand when the zero flag
is not set.
JP NZ,10H
PCB
NBP
PCP
NPP
PCS
Z flag
1
1
1
0000
0000
0000 0111
0
1
0000
0000
0001 0000
0
JP s
Jump
Source Format:
Operation:
JP s
PCB ← NBP, PCP ← NPP, PCS ← s7 to s0
OP-Code:
0
MSB
0
0
0 s7 s6 s5 s4 s3 s2 s1 s0
LSB
000H to 0FFH
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Unconditional jump to the destination address specified by the 8-bit operand.
PSET 0AH
JP 10H
PCB
NBP
PCP
NPP
PCS
0
0
0
0
0
0
0000
0001
0100 0010
0000
1010
0100 0011
1010
1010
0001 0000
S1C6200/6200A CORE CPU MANUAL
EPSON
45
3 INSTRUCTION SET
JP Z,s
Jump if zero
Source Format:
JP Z,s
Operation:
PCB ← NBP, PCP ← NPP, PCS ← s7 to s0 if Z = 1
OP-Code:
0
MSB
1
1
0 s7 s6 s5 s4 s3 s2 s1 s0
LSB
600H to 6FFH
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Jumps to the destination address specified by the 8-bit operand when the zero flag
is set.
SUB A,B
PSET 1BH
JP Z,10H
PCB
NBP
0
0
0
0
0
1
1
1
PCP
NPP
PCS
A register
B register
Z flag
0101
0001
0000 0010
0110
0110
0
0101
0001
0000 0011
0000
0110
1
0101
1011
0000 0100
0000
0110
1
1011
1011
0001 0000
0000
0110
1
LBPX MX,e
Load immediate data e to memory, and increment X by 2
Source Format:
Operation:
LBPX MX,e
M(X) ← e3 to e0, M(X+1) ← e7 to e4, X ← X + 2
OP-Code:
1
MSB
0
0
1 e7 e6 e5 e4 e3 e2 e1 e0
LSB
900H to 9FFH
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Stores 8-bit immediate data e in two, consecutive 4-bit locations in data memory.
The X-register is incremented by 2. An overflow in X does not affect the flags.
LBPX MX,18H
LBPX MX,36H
0010 0010
1000
X register
0001 1110
0010
0010 0000
Memory (1EH)
Memory (1FH)
Memory (20H)
Memory (21H)
1000
0001
0000
0111
1111
0000
0111
0001
0110
0011
46
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD A,Mn
Load memory into A-register
Source Format:
LD A,Mn
Operation:
OP-Code:
A ← M(n3 to n0)
1
1
1
1
1
0
1
0 n3 n2 n1 n0
LSB
FA0H to FAFH
MSB
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by Mn into the A-
register.
LD A,M5
0100
LD A,M6
0100
A register
1111
1111
0100
Memory (05H)
Memory (06H)
1111
0100
1111
0100
LD B,Mn
Load memory into B-register
Source Format:
Operation:
LD B,Mn
B ← M(n3 to n0)
OP-Code:
1
MSB
1
1
1
1
0
1
1 n3 n2 n1 n0
LSB
FB0H to FBFH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by Mn into the B-
register.
LD B,M7
0100
LD B,M8
1010
B register
0110
0110
1010
Memory (07H)
Memory (08H)
0110
1010
0110
1010
S1C6200/6200A CORE CPU MANUAL
EPSON
47
3 INSTRUCTION SET
LD Mn,A
Load A-register into memory
Source Format:
LD Mn,A
Operation:
M(n3 to n0) ← A
OP-Code:
1
MSB
1
1
1
1
0
0
0 n3 n2 n1 n0
LSB
F80H to F8FH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the A-register into the location addressed by Mn.
LD M0AH,A
0110
LD M0BH,A
0110
A register
0110
0110
1011
Memory (0AH)
Memory (0BH)
0100
1011
0110
0110
LD Mn,B
Load B-register into memory
Source Format:
Operation:
LD Mn,B
M(n3 to n0) ← B
OP-Code:
1
MSB
1
1
1
1
0
0
1 n3 n2 n1 n0
LSB
F90H to F9FH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the B-register into the data memory location addressed by
Mn.
LD M0,B
0100
LD M1,B
0100
B register
0100
0100
1111
Memory (00H)
Memory (01H)
1011
1111
0100
0100
48
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LDPX MX,i
Load immediate data i into MX, increment X by 1
Source Format:
LDPX MX,i
Operation:
M(X) ← i3 to i0, X ← X + 1
OP-Code:
1
MSB
1
1
0
0
1
1
0
i3 i2 i1 i0
LSB
E60H to E6FH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads immediate data i into the data memory location addressed by IX. X is
incremented by 1. Incrementing X does not affect the flags.
LDPX MX,7
1000 0011
0010
LDPX MX,0AH
X register
Memory (83H)
Memory (84H)
1000 0100
1000 0101
0111
0111
1001
1001
1010
LDPX r,q
Load q-register into r-register, increment X by 1
Source Format:
Operation:
LDPX r,q
r ← q, X ← X + 1
OP-Code:
1
MSB
1
1
0
1
1
1
0
r1 r0 q1 q0
LSB
EE0H to EEFH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the q-register into the r-register. X is incremented by 1.
Incrementing X does not affect the flags.
LDPX A,B
LDPX B,MY
X register
A register
B register
Memory (MY)
0100 1001
0100 1010
0100 1011
1101
0000
1010
1101
0000
1101
1101
0000
0000
S1C6200/6200A CORE CPU MANUAL
EPSON
49
3 INSTRUCTION SET
LDPY MY,i
Load immediate data i into MY, increment Y by 1
Source Format:
LDPY MY,i
Operation:
M(Y) ← i3 to i0, Y ← Y + 1
OP-Code:
1
MSB
1
1
0
0
1
1
1
i3 i2 i1 i0
LSB
E70H to E7FH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads immediate data i into the data memory location addressed by IY. Y is
incremented by 1. Incrementing Y does not affect the flags.
LDPY MY,7
0010 1101
1010
LDPY MY,0
0010 1111
0111
Y register
Memory (2DH)
Memory (2EH)
0010 1110
0111
0010
0010
0000
LDPY r,q
Load q-register into r-register, increment Y by 1
Source Format:
Operation:
LDPY r,q
r ← q, Y ← Y + 1
OP-Code:
1
MSB
1
1
0
1
1
1
1
r1 r0 q1 q0
LSB
EF0H to EFFH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the q-register into the r-register. Y is incremented by 1.
Incrementing Y does not affect the flags.
LDPY A,B
LDPY MX,B
Y register
A register
B register
Memory (MX)
0100 1000
0100 1001
0100 1010
1000
1000
1010
1000
0010
1000
1000
0010
1000
50
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD r,i
Load immediate data i into r-register
Source Format:
LD r,i
Operation:
OP-Code:
r ← i3 to i0
1
1
1
0
0
0
r1 r0 i3 i2 i1 i0
LSB
E00H to E3FH
MSB
Type:
Clock Cycles:
Flag:
II
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads immediate data i into the r-register.
LD A,6
LD MY,0
A register
Memory (MY)
0101
1001
0110
1001
0110
0000
LD r,q
Load q-register into r-register
Source Format:
Operation:
LD r,q
r ← q
OP-Code:
1
MSB
1
1
0
1
1
0
0
r1 r0 q1 q0
LSB
EC0H to ECFH
Type:
Clock Cycles:
Flag:
IV
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
The contents of the q-register are loaded into the r-register.
LD A,B
0010
0000
0110
LD B,MY
0000
A register
B register
Memory (MY)
0000
0000
0110
0110
0110
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
LD r,SPH
Load SPH into r-register
Source Format:
LD r,SPH
Operation:
r ← SPH
OP-Code:
1
MSB
1
1
1
1
1
1
0
0
1
r1 r0
LSB
FE4H to FE7H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the four high-order bits of the stack pointer into the r-register.
LD MX,SPH
0111
LD A,SPH
0111
SPH
0111
0000
0111
A register
Memory (MX)
0000
1100
0111
0111
LD r,SPL
Load SPL into r-register
Source Format:
Operation:
LD r,SPL
r ← SPL
OP-Code:
1
MSB
1
1
1
1
1
1
1
0
1
r1 r0
LSB
FF4H to FF7H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the four low-order bits of the stack pointer into the r-register.
LD A,SPL
1001
LD MY,SPL
1001
SPL
1001
1001
0000
A register
Memory (MY)
0010
0000
1001
1001
52
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD r,XH
Load XH into r-register
Source Format:
LD r,XH
Operation:
OP-Code:
r ← XH
1
1
1
0
1
0
1
0
0
1
r1 r0
LSB
EA4H to EA7H
MSB
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the four high-order bits of register X into the r-register.
LD B,XH
1010
LD MX,XH
1010
XH register
B register
1010
1010
0000
0010
1010
Memory (MX)
0000
1010
LD r,XL
Load XL into r-register
Source Format:
Operation:
LD r,XL
r ← XL
OP-Code:
1
MSB
1
1
0
1
0
1
0
1
0
r1 r0
LSB
EA8H to EABH
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the four low-order bits of register X into the r-register.
LD MY,XL
0000
LD A,XL
0000
XL register
A register
0000
1101
0000
1101
0000
Memory (MY)
0001
0000
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
LD r,XP
Load XP into r-register
Source Format:
LD r,XP
Operation:
r ← XP
OP-Code:
1
MSB
1
1
0
1
0
1
0
0
0
r1 r0
LSB
EA0H to EA3H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the 4-bit page part of index register IX into the r-register.
LD MX,XP
1111
LD A,XP
1111
XP register
A register
1111
0010
1111
0010
1111
Memory (MX)
0101
1111
LD r,YH
Load YH into r-register
Source Format:
Operation:
LD r,YH
r ← YH
OP-Code:
1
MSB
1
1
0
1
0
1
1
0
1
r1 r0
LSB
EB4H to EB7H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the four high-order bits of register Y into the r-register.
LD A,YH
1010
LD MY,YH
1010
YH register
A register
1010
1010
1110
1100
1010
Memory (MY)
1110
1010
54
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD r,YL
Load YL into r-register
Source Format:
LD r,YL
Operation:
OP-Code:
r ← YL
1
1
1
0
1
0
1
1
1
0
r1 r0
LSB
EB8H to EBBH
MSB
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the four low-order bits of register Y into the r-register.
LD B,YL
0000
LD MX,YL
0000
YL register
B register
0000
0000
1011
0110
0000
Memory (MX)
1011
0000
LD r,YP
Load YP into r-register
Source Format:
Operation:
LD r,YP
r ← YP
OP-Code:
1
MSB
1
1
0
1
0
1
1
0
0
r1 r0
LSB
EB0H to EB3H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the 4-bit page part of index register IY into the r-register.
LD MY,YP
1010
LD B,YP
1010
YP register
B register
1010
1100
1010
1100
1010
Memory (MY)
0110
1010
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
LD SPH,r
Load r-register into SPH
Source Format:
LD SPH,r
Operation:
SPH ← r
OP-Code:
1
MSB
1
1
1
1
1
1
0
0
0
r1 r0
LSB
FE0H to FE3H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the four high-order bits of the stack
pointer.
LD SPH,A
1001
LD SPH,MY
1100
SPH
0011
0011
1100
A register
Memory (MY)
0011
1100
0011
1100
LD SPL,r
Load r-register into SPL
Source Format:
Operation:
LD SPL,r
SPL ← r
OP-Code:
1
MSB
1
1
1
1
1
1
1
0
0
r1 r0
LSB
FF0H to FF3H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the four low-order bits of the stack pointer.
LD SPL,B
1011
LD SPL,MX
1111
SPL
0111
0111
1111
B register
Memory (MX)
0111
1111
0111
1111
56
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD X,e
Load immediate data e into X-register
Source Format:
LD X,e
Operation:
OP-Code:
XH ← e7 to e4, XL ← e3 to e0
1
0
1
1 e7 e6 e5 e4 e3 e2 e1 e0
LSB
B00H to BFFH
MSB
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads 8-bit immediate data e into register X.
LD X,6FH
XH register
XL register
0000
1011
0110
1111
LD XH,r
Load r-register into XH
Source Format:
Operation:
LD XH,r
XH ← r
OP-Code:
1
MSB
1
1
0
1
0
0
0
0
1
r1 r0
LSB
E84H to E87H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the four high-order bits of register X.
LD XH,A
0000
LD XH,MY
0110
XH register
A register
1011
1011
0110
1011
1011
Memory (MY)
0110
0110
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
LD XL,r
Load r-register into XL
Source Format:
LD XL,r
Operation:
XL ← r
OP-Code:
1
MSB
1
1
0
1
0
0
0
1
0
r1 r0
LSB
E88H to E8BH
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the four low-order bits of register X.
LD XL,MY
0000
LD XL,A
1011
XL register
A register
0010
1011
0010
1011
1011
Memory (MY)
0010
0010
LD XP,r
Load r-register into XP
Source Format:
Operation:
LD XP,r
XP ← r
OP-Code:
1
MSB
1
1
0
1
0
0
0
0
0
r1 r0
LSB
E80H to E83H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the 4-bit page part of index register IX.
LD XP,B
1001
LD XP,MX
1011
XP register
B register
0001
0001
1011
0001
0001
Memory (MX)
1011
1011
58
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD Y,e
Load immediate data e into Y-register
Source Format:
LD Y,e
Operation:
OP-Code:
YH ← e7 to e4, YL ← e3 to e0
1
0
0
0 e7 e6 e5 e4 e3 e2 e1 e0
LSB
800H to 8FFH
MSB
Type:
Clock Cycles:
Flag:
I
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads 8-bit immediate data e into register Y.
LD Y,E1H
YH register
YL register
0001
1100
1110
0001
LD YH,r
Load r-register into YH
Source Format:
Operation:
LD YH,r
YH ← r
OP-Code:
1
MSB
1
1
0
1
0
0
1
0
1
r1 r0
LSB
E94H to E97H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the four high-order bits of register Y.
LD YH,B
0000
LD YH,MX
0101
YH register
B register
0110
0110
0101
0110
0110
Memory (MX)
0101
0101
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
LD YL,r
Load r-register into YL
Source Format:
LD YL,r
Operation:
YL ← r
OP-Code:
1
MSB
1
1
0
1
0
0
1
1
0
r1 r0
LSB
E98H to E9BH
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the four low-order bits of register Y.
LD YL,B
1011
LD YL,MX
0111
YL register
B register
1010
1010
0111
1010
1010
Memory (MX)
0111
0111
LD YP,r
Load r-register into YP
Source Format:
Operation:
LD YP,r
YP ← r
OP-Code:
1
MSB
1
1
0
1
0
0
1
0
0
r1 r0
LSB
E90H to E93H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the r-register into the 4-bit page part of index register IY.
LD YP,MX
0011
LD YP,A
0100
YP register
A register
0000
0100
0000
0100
0100
Memory (MX)
0000
0000
60
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
NOP5
No operation for 5 clock cycles
Source Format:
NOP5
Operation:
OP-Code:
No operation (5 clock cycles)
1
1
1
1
1
1
1
1
1
0
1
1
FFBH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Increments the program counter by 1. Has no other effect for 5 clock cycles.
NOP5
PCB
PCP
PCS
0
0
0011
0001 0011
0011
0001 0100
NOP7
No operation for 7 clock cycles
Source Format:
Operation:
NOP7
No operation (7 clock cycles)
OP-Code:
1
1
1
1
1
1
1
1
1
1
1
1
FFFH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Increments the program counter by 1. Has no other effect for 7 clock cycles.
NOP7
PCB
PCP
PCS
0
0
1010
1001 1001
1010
1001 1010
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
NOT r
NOT r-register (one's complement)
Source Format:
NOT r
Operation:
r ← r
OP-Code:
1
1
0
1
0
0
r1 r0
1
1
1
1
D0FH to D3FH
MSB
LSB
Type:
Clock Cycles:
Flag:
II
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a one's complement operation on the contents of the r-register.
NOT A
1001
1111
0
NOT MY
0110
0000
1
A register
Memory (MY)
Z flag
0110
1111
0
OR r,i
Logical OR immediate data i with r-register
Source Format:
Operation:
OR r,i
r ← r ∨ i3 to i0
OP-Code:
1
MSB
1
0
0
1
1
r1 r0 i3 i2 i1 i0
LSB
CC0H to CFFH
Type:
Clock Cycles:
Flag:
II
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a logical OR operation between immediate data i and the contents of the
r-register. The result is stored in the r-register.
OR B,5
OR MX,0BH
B register
Memory (MX)
Z flag
0100
0011
0
0101
0011
0
0101
0111
0
62
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
OR r,q
Logical OR q-register with r-register
Source Format:
OR r,q
Operation:
OP-Code:
r ← r ∨ q
1
0
1
0
1
1
0
1
r1 r0 q1 q0
LSB
AD0H to ADFH
MSB
Type:
Clock Cycles:
Flag:
IV
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs a logical OR operation between the contents of the q-register and the
contents of the r-register. The result is stored in the r-register.
OR MY,0
OR A,0CH
A register
Memory (MY)
Z flag
0011
0000
0
0011
0000
1
1111
0000
0
POP F
Pop stack data into flags
Source Format:
Operation:
POP F
F ← M(SP), SP ← SP + 1
OP-Code:
1
1
1
1
1
1
0
1
1
0
1
0
FDAH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Set or Reset by M(SP) data
Z – Set or Reset by M(SP) data
D – Set or Reset by M(SP) data
I – Set or Reset by M(SP) data
Description:
Example:
Replaces the flags (F) with the contents of the data memory location addressed by
the stack pointer. SP is incremented by 1.
3
2
1
0
M(SP) =
POP F
2 2 2 2
SP
C0
1001
0001
C1
1001
1001
C flag
Z flag
D flag
I flag
Memory (C0H)
Flags (I,D,Z,C)
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
POP r
Pop stack data into r-register
Source Format:
POP r
Operation:
r ← M(SP), SP ← SP + 1
OP-Code:
1
MSB
1
1
1
1
1
0
1
0
0 r1 r0
LSB
FD0H to FD3H
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into the r-register. SP is incremented by 1.
3
2
1
0
M(SP) =
2 2 2 2
POP B
20
21
22
23
SP
C0
1001
0101
C1
1001
1001
Memory (C0H)
B register
= r-register
POP XH
Pop stack data into XH
Source Format:
Operation:
POP XH
XH ← M(SP), SP ← SP + 1
OP-Code:
1
1
1
1
1
1
0
1
0
1
0
1
FD5H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into XH, the four high-order bits of X. SP is incremented by 1.
3
2
1
0
M(SP) =
2 2 2 2
POP XH
20
21
22
23
SP
CE
0110
0010
CF
0110
0110
= XH
Memory (CEH)
XH register
64
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
POP XL
Pop stack data into XL
Source Format:
POP XL
Operation:
OP-Code:
XL ← M(SP), SP ← SP + 1
1
1
1
1
1
1
0
1
0
1
1
0
FD6H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into XL, the four low-order bits of X. SP is incremented by 1.
3
2
1
0
M(SP) =
2 2 2 2
POP XL
20
21
22
23
SP
C0
0001
1101
C1
0001
0001
Memory (C0H)
XL register
= XL
POP XP
Pop stack data into XP
Source Format:
Operation:
POP XP
XP ← M(SP), SP ← SP + 1
OP-Code:
1
1
1
1
1
1
0
1
0
1
0
0
FD4H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into XP, the 4-bit page part of IX. SP is incremented by 1.
3
2
1
0
POP XP
M(SP) =
2 2 2 2
SP
B4
0101
0111
B5
0101
0101
20
21
22
23
Memory (B4H)
XP register
= XP
S1C6200/6200A CORE CPU MANUAL
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65
3 INSTRUCTION SET
POP YH
Pop stack data into YH
Source Format:
POP YH
Operation:
YH ← M(SP), SP ← SP + 1
OP-Code:
1
1
1
1
1
1
0
1
1
0
0
0
FD8H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into YH, the four high-order bits of Y. SP is incremented by 1.
3
2
1
0
M(SP) =
2 2 2 2
POP YH
20
21
22
23
SP
C1
1101
0010
C2
1101
1101
Memory (C1H)
YH register
= YH
POP YL
Pop stack data into YL
Source Format:
Operation:
POP YL
YL ← M(SP), SP ← SP + 1
OP-Code:
1
1
1
1
1
1
0
1
1
0
0
1
FD9H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into YL, the four low-order bits of Y. SP is incremented by 1.
3
2
1
0
POP YL
M(SP) =
2 2 2 2
SP
CA
0100
0101
CB
0100
0100
20
21
22
23
Memory (CAH)
YL register
= YL
66
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
POP YP
Pop stack data into YP
Source Format:
POP YP
Operation:
OP-Code:
YP ← M(SP), SP ← SP + 1
1
1
1
1
1
1
0
1
0
1
1
1
FD7H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the contents of the data memory location addressed by the stack pointer
into YP, the 4-bit page part of IY. SP is incremented by 1.
3
2
1
0
M(SP) =
2 2 2 2
POP YP
20
21
22
23
SP
C0
0000
0001
C1
0000
0000
Memory (C0H)
YP register
= YP
PSET p
Page set
Source Format:
Operation:
PSET p
NBP ← p4, NPP ← p3 to p0
OP-Code:
1
MSB
1
1
0
0
1
0 p4 p3 p2 p1 p0
LSB
E40H to E5FH
Type:
Clock Cycles:
Flag:
III
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Loads the most-significant bit of the 5-bit immediate data p to the new bank
pointer (NBP) and the four low-order bits to the new page pointer (NPP).
PSET 1FH
JP 00H
PCB
NBP
PCP
NPP
PCS
0
0
0
1
1
1
1000
0001
0010 0011
1000
1111
0010 0100
1111
1111
0000 0000
S1C6200/6200A CORE CPU MANUAL
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67
3 INSTRUCTION SET
PUSH F
Push flag onto stack
Source Format:
PUSH F
Operation:
SP' ← SP - 1, M(SP') ← F
OP-Code:
1
1
1
1
1
1
0
0
1
0
1
0
FCAH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the flags (F) into the data memory
location addressed by SP.
3
2
1
0
M(SP) =
2 2 2 2
PUSH F
C flag
Z flag
D flag
I flag
SP
D0
0100
0001
CF
0001
0001
Memory (CFH)
Flags (I,D,Z,C)
PUSH r
Push r-register onto stack
Source Format:
Operation:
PUSH r
SP' ← SP - 1, M(SP') ← r
OP-Code:
1
1
1
1
1
1
0
0
0
0 r1 r0
FC0H to FC3H
MSB
LSB
Type:
Clock Cycles:
Flag:
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of the r-register into the
data memory location addressed by SP.
3
2
1
0
M(SP) =
PUSH A
2 2 2 2
SP
D0
1000
0010
CF
0010
0010
20
21
22
23
Memory (CFH)
A register
= r-register
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3 INSTRUCTION SET
PUSH XH
Push XH onto stack
Source Format:
PUSH XH
Operation:
OP-Code:
SP' ← SP - 1, M(SP') ← XH
1
1
1
1
1
1
0
0
0
1
0
1
FC5H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of XH, the four high-
order bits of XHL, into the data memory location addressed by SP.
3
2
1
0
M(SP) =
2 2 2 2
PUSH XH
20
21
22
23
SP
CC
0000
1000
CB
1000
1000
Memory (CBH)
XH register
= XH
PUSH XL
Push XL onto stack
Source Format:
Operation:
PUSH XL
SP' ← SP - 1, M(SP') ← XL
OP-Code:
1
1
1
1
1
1
0
0
0
1
1
0
FC6H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of XL, the four low-order
bits of XHL, into the data memory location addressed by SP.
3
2
1
0
M(SP) =
PUSH XL
2 2 2 2
SP
D0
1111
0110
CF
0110
0110
20
21
22
23
Memory (CFH)
XL register
= XL
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
PUSH XP
Push XP onto stack
Source Format:
PUSH XP
Operation:
SP' ← SP - 1, M(SP') ← XP
OP-Code:
1
1
1
1
1
1
0
0
0
1
0
0
FC4H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of XP, the page part of
IX, into the data memory location addressed by SP.
3
2
1
0
M(SP) =
2 2 2 2
PUSH XP
20
21
22
23
SP
D0
0011
0000
CF
0000
0000
Memory (CFH)
XP register
= XP
PUSH YH
Push YH onto stack
Source Format:
Operation:
PUSH YH
SP' ← SP - 1, M(SP') ← YH
OP-Code:
1
1
1
1
1
1
0
0
1
0
0
0
FC8H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of YH, the four high-
order bits of YHL, into the data memory location addressed by SP.
3
2
1
0
M(SP) =
PUSH YH
2 2 2 2
20
21
22
23
SP
BF
0100
0001
BE
0001
0001
Memory (BEH)
YH register
= YH
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3 INSTRUCTION SET
PUSH YL
Push YL onto stack
Source Format:
PUSH YL
Operation:
OP-Code:
SP' ← SP - 1, M(SP') ← YL
1
1
1
1
1
1
0
0
1
0
0
1
FC9H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of YL, the four low-order
bits of YHL, into the data memory location addressed by SP.
3
2
1
0
M(SP) =
2 2 2 2
PUSH YL
20
21
22
23
SP
D0
0001
0111
CF
0111
0111
Memory (CFH)
YL register
= YL
PUSH YP
Push YP onto stack
Source Format:
Operation:
PUSH YP
SP' ← SP - 1, M(SP') ← YP
OP-Code:
1
1
1
1
1
1
0
0
0
1
1
1
FC7H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Decrements the stack pointer by 1 and loads the contents of YP, the page part of
IY, into the data memory location addressed by SP.
3
2
1
0
M(SP) =
PUSH YP
2 2 2 2
SP
C0
1111
0000
BF
0000
0000
20
21
22
23
Memory (BFH)
YP register
= YP
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3 INSTRUCTION SET
RCF
Reset carry flag
Source Format:
RCF
Operation:
C ← 0
OP-Code:
1
1
1
1
0
1
0
1
1
1
1
0
F5EH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Reset
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Resets the C (carry) flag.
ADD A,4
RCF
A register
C flag
1101
0
0001
1
0001
0
RDF
Reset decimal flag
Source Format:
Operation:
RDF
D ← 0
OP-Code:
1
1
1
1
0
1
0
1
1
0
1
1
F5BH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Not affected
D – Reset
I – Not affected
Description:
Example:
Resets the D (decimal) flag.
ADD A,8
RDF
LD A,6
ADD A,8
A register
D flag
C flag
0110
0100
0100
0110
1110
1
0
0
1
1
0
0
1
0
0
1
0
0
0
0
Z flag
72
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3 INSTRUCTION SET
RET
Return from subroutine
Source Format:
RET
Operation:
OP-Code:
PCSL ← M(SP), PCSH ← M(SP+1), PCP ← M(SP+2), SP ← SP + 3
1
1
1
1
1
1
0
1
1
1
1
1
FDFH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Jumps to the return address that was pushed onto the stack when the subroutine
was called.
RET
PCP
PCS
SP
1101
1000 1101
BD
0010
0010 1101
C0
Memory (SP)
Memory (SP+1)
Memory (SP+2)
1101
0010
0010
1101
0010
0010
RETD e
Load immediate data e to memory, and increment X by 2, then return
Source Format:
Operation:
RETD e
PCSL ← M(SP), PCSH ← M(SP+1), PCP ← M(SP+2), SP ← SP + 3,
M(X) ← e3 to e0, M(X+1) ← e7 to e4, X ← X + 2
OP-Code:
0
0
0
1 e7 e6 e5 e4 e3 e2 e1 e0
LSB
100H to 1FFH
MSB
Type:
I
Clock Cycles:
12
Flag:
C– Not affected
Z – Not affected
D– Not affected
I – Not affected
Description:
Loads 8-bit immediate data e into the data memory location addressed by IX and
executes the RET command. X is incremented by 2.
Example:
RETD F5H
PCP
PCS
SP
0000
1010 1011
BD
0010
0010 1101
C0
Memory (SP)
Memory (SP+1)
Memory (SP+2)
X register
Memory (2AH)
Memory (2BH)
1101
0010
0010
0010 1010
0000
1101
0010
0010
0010 1100
0101
0000
1111
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3 INSTRUCTION SET
RETS
Return then skip an instruction
Source Format:
RETS
Operation:
PCSL ← M(SP), PCSH ← M(SP+1), PCP ← M(SP+2), SP ← SP + 3, PC ← PC + 1
OP-Code:
1
1
1
1
1
1
0
1
1
1
1
0
FDEH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
12
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Jumps to the return address that was pushed onto the stack when the subroutine
was called and then skips one instruction.
RETS
PCP
PCS
SP
0110
1001 0000
B0
0000
0000 0111
B3
Memory (SP)
Memory (SP+1)
Memory (SP+2)
0110
0000
0000
0110
0000
0000
RLC r
Rotate r-register left with carry
Source Format:
Operation:
RLC r
d3 ← d2, d2 ← d1, d1 ← d0, d0 ← C, C ← d3
OP-Code:
1
MSB
0
1
0
1
1
1
1
r1 r0 r1 r0
LSB
AF0H to AFFH
Type:
Clock Cycles:
Flag:
IV
7
C – Set when the high-order bit of the r-register is 1; otherwise, reset.
Z – Not affected
D – Not affected
I – Not affected
Description:
Shifts the contents of the r-register one bit to the left. The high-order bit is shifted
into the carry flag and the carry bit becomes the low-order bit of the r-register.
C
C
r-register
C
d
r-register
d
3
d
2
d
1
d
0
3
d
2
d
1
d
0
C
Example:
RLC A
A register
C flag
0011
1
0111
0
74
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3 INSTRUCTION SET
RRC r
Rotate r-register right with carry
Source Format:
RRC r
Operation:
OP-Code:
d3 ← C, d2 ← d3, d1 ← d2, d0 ← d1, C ← d0
1
1
1
0
1
0
0
0
1
1 r1 r0
LSB
E8CH to E8FH
MSB
Type:
Clock Cycles:
Flag:
V
5
C – Set when the low-order bit of the r-register is 1; otherwise, reset.
Z – Not affected
D – Not affected
I – Not affected
Description:
Shifts the contents of the r-register one bit to the right. The low-order bit is shifted
into the carry flag and the carry bit becomes the high-order bit of the r-register.
r-register
C
C
C
d
d
3
d
2
d
1
d
0
2
1
0
Example:
RRC MY
Memory (MY)
C flag
1010
1
1101
0
RST F,i
Reset flags using immediate data i
Source Format:
Operation:
RST F,i
F ← F ∧ i3 to i0
OP-Code:
1
MSB
1
1
1
0
1
0
1
i3 i2 i1 i0
LSB
F50H to F5FH
Type:
Clock Cycles:
Flag:
IV
7
C – Reset if i0 is zero; otherwise, not affected.
Z – Reset if i1 is zero; otherwise, not affected.
D – Reset if i2 is zero; otherwise, not affected.
I – Reset if i3 is zero; otherwise, not affected.
Description:
Example:
Performs a logical AND operation between immediate data i and the contents of
the flags. The result is stored in each respective flag.
RST F,2
Flags (I,D,Z,C)
1010
0010
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
RZF
Reset zero flag
Source Format:
RZF
Operation:
Z ← 0
OP-Code:
1
1
1
1
0
1
0
1
1
1
0
1
F5DH
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Reset
D – Not affected
I – Not affected
Description:
Example:
Resets the Z (zero) flag.
ADD A,3
RZF
Z flag
0
1
0
A register
1101
0000
0000
SBC r,i
Subtract with carry immediate data i from r-register
Source Format:
Operation:
SBC r,i
r ← r - i3 to i0 - C
OP-Code:
1
MSB
1
0
1
0
1
r1 r0 i3 i2 i1 i0
LSB
D40H to D7FH
Type:
Clock Cycles:
Flag:
II
7
C – Set if a borrow is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Subtracts the carry flag and immediate data i from the r-register.
SBC A,9
SBC MY,0DH
A register
Memory (MY)
C flag
1000
1110
0
1111
1110
1
1111
0000
0
Z flag
0
0
1
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3 INSTRUCTION SET
SBC r,q
Subtract with carry q-register from r-register
Source Format:
SBC r,q
Operation:
OP-Code:
r ← r - q - C
1
0
1
0
1
0
1
1
r1 r0 q1 q0
LSB
AB0H to ABFH
MSB
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a borrow is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Subtracts the carry flag and the contents of the q-register from the r-register.
SBC A,B
SBC MY,MX
A register
B register
Memory (MX)
Memory (MY)
C flag
1110
0010
1001
0100
1
1011
0010
1001
0100
0
1011
0010
1001
1011
1
Z flag
0
0
0
SCF
Set carry flag
Source Format:
Operation:
SCF
C ← 1
OP-Code:
1
1
1
1
0
1
0
0
0
0
0
1
F41H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Set
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Sets the C (carry) flag.
SCF
C flag
0
1
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
SCPX MX,r
Subtract with carry r-register from M(X) and increment X by 1
Source Format:
SCPX MX,r
Operation:
M(X) ← M(X) - r - C, X ← X + 1
OP-Code:
1
MSB
1
1
1
0
0
1
1
1
0 r1 r0
LSB
F38H to F3BH
Type:
Clock Cycles:
Flag:
V
7
C – Set if a borrow is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Subtracts the carry flag and the contents of the r-register from the data memory
location addressed by IX. X is incremented by 1. Incrementing X does not affect
the flags.
SCPX MX,B
X register
Memory (50H)
B register
C flag
0101 0000
0101 0001
0110
0010
0
0100
0010
0
Z flag
0
0
SCPY MY,r
Subtract with carry r-register from M(Y) and increment Y by 1
Source Format:
Operation:
SCPY MY,r
M(Y) ← M(Y) - r - C, Y ← Y + 1
OP-Code:
1
MSB
1
1
1
0
0
1
1
1
1 r1 r0
LSB
F3CH to F3FH
Type:
Clock Cycles:
Flag:
V
7
C – Set if a borrow is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Subtracts the carry flag and the contents of the r-register from the data memory
location addressed by IY. Y is incremented by 1. Incrementing Y does not affect
the flags.
SCPY MY,A
Y register
Memory (FFH)
A register
C flag
1111 1111
0000 0000
0111
0010
1
0100
0010
0
Z flag
1
0
78
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3 INSTRUCTION SET
SDF
Set decimal flag
Source Format:
SDF
Operation:
OP-Code:
D ← 1
1
1
1
1
0
1
0
0
0
1
0
0
F44H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Not affected
D – Set
I – Not affected
Description:
Example:
Sets the D (decimal) flag.
SDF
D flag
0
1
SET F,i
Set flags using immediate data i
Source Format:
Operation:
SET F,i
F ← F ∨ i3 to i0
OP-Code:
1
MSB
1
1
1
0
1
0
0
i3 i2 i1 i0
LSB
F40H to F4FH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if i0 is 1; otherwise, not affected.
Z – Set if i1 is 1; otherwise, not affected.
D – Set if i2 is 1; otherwise, not affected.
I – Set if i3 is 1; otherwise, not affected.
Description:
Example:
Performs a logical OR operation between immediate data i and the contents of the
flags. The results are stored in each respective flag.
SET F,0DH
Flags (C,Z,D,I)
0011
1111
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
SLP
Sleep
Source Format:
SLP
Operation:
Stop CPU and peripheral oscillator
OP-Code:
1
1
1
1
1
1
1
1
1
0
0
1
FF9H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Description:
Example:
Stops the CPU and the peripheral oscillator. When an interrupt occurs PCP and
PCS are pushed onto the stack as the return address and the interrupt service
routine is executed.
Instruction
State
PCP
PCS
I flag
RUN
0100 0011 0000
0100 0011 0001
1
1
SLP
SLEEP
RUN
Interrupt →
NOP5
0001 0000 0001
0
SUB r,q
Subtract q-register from r-register
Source Format:
Operation:
SUB r,q
r ← r - q
OP-Code:
1
MSB
0
1
0
1
0
1
0
r1 r0 q1 q0
LSB
AA0H to AAFH
Type:
Clock Cycles:
Flag:
IV
7
C – Set if a borrow is generated; otherwise, reset.
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Subtracts the contents of the q-register from the r-register.
SUB A,B
A register
B register
C flag
1100
0011
1
1001
0011
0
Z flag
0
0
80
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S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
SZF
Set zero flag
Source Format:
SZF
Operation:
Z ← 1
OP-Code:
1
1
1
1
0
1
0
0
0
0
1
0
F42H
MSB
LSB
Type:
Clock Cycles:
Flag:
VI
7
C – Not affected
Z – Set
D – Not affected
I – Not affected
Description:
Example:
Sets the Z (zero) flag.
SZF
Z flag
0
1
XOR r,i
Exclusive-OR immediate data i with r-register
Source Format:
XOR r,i
Operation:
OP-Code:
r ← r ∀ i3 to i0
1
1
0
1
0
0
r1 r0 i3 i2 i1 i0
LSB
D00H to D3FH
MSB
Type:
Clock Cycles:
Flag:
II
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs an exclusive-OR operation between immediate data i and the contents
of the r-register. The result is stored in the r-register.
XOR A,12
XOR MX,1
A register
Memory (MX)
Z flag
0110
0001
0
1010
0001
0
1010
0000
1
S1C6200/6200A CORE CPU MANUAL
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3 INSTRUCTION SET
XOR r,q
Exclusive-OR q-register with r-register
Source Format:
XOR r,q
Operation:
r ← r ∀ q
OP-Code:
1
MSB
0
1
0
1
1
1
0
r1 r0 q1 q0
LSB
AE0H to AEFH
Type:
Clock Cycles:
Flag:
IV
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Description:
Example:
Performs an exclusive-OR operation between the contents of the q-register and
the contents of the r-register. The result is stored in the r-register.
XOR A,MY
0100
XOR MX,B
1100
A register
B register
Memory (MX)
Memory (MY)
Z flag
1100
1111
0111
1000
0
1111
1111
0111
1000
1000
1000
0
0
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3 INSTRUCTION SET
ABBREVIATIONS
A............. A register (4 bits)
B............. B register (4 bits)
M(SP) ..... Contents of the data memory location whose address is specified by stack pointer SP (4 bits)
M(X) ....... Contents of the data memory location whose address is specified by IX (4 bits)
M(Y) ....... Contents of the data memory location whose addressisspecified by IY (4 bits)
M(n3-0) .... Contents of the data memory location within the register area 00H to 0FH (4 bits)
MX.......... Data memory location whose address is specified by IX
MY.......... Data memory location whose address is specified by IY
NBP ........ New Bank Pointer (1 bit)
NPP ........ New Page Pointer (4 bits)
PCB ........ Program Counter-Bank (1 bit)
PCP ........ Program Counter-Page (4 bits)
PCS ........ Program Counter-Step (8 bits)
PCSH ..... Four high-order bits of PCS
PCSL...... Four low-order bits of PCS
RP .......... Register Pointer (4 bits)
SP .......... Stack Pointer (8 bits)
SPH ........ Four high-order bits of SP
SPL ........ Four low-order bits of SP
X............. Eight low-order bits of IX, that is, XHL
XH .......... Four high-order bits of X
XL........... Four low-order bits of X
XP .......... Four high-order bits of IX (page part)
Y............. Eight low-order bits of IY, that is, YHL
YH .......... Four high-order bits of Y
YL........... Four low-order bits of Y
YP .......... Four high-order bits of IY (page part)
+ ............. Addition
– ............. Subtraction
∧............... Logical AND
∨ ............. Logical OR
∀............. Exclusive-OR
↓ ............. Reset flag
↑ ............. Set flag
↕ ............. Set/reset flag
∗ ............. Decimal addition/subtraction
S1C6200/6200A CORE CPU MANUAL
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APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU
APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU
S1C6200A is an improved version of the S1C6200. In this section, S1C6200A is described only in
terms of its differences with S1C6200. It is recommended that users of S1C6200A read this section.
S1C6200A is a Core CPU which has been made easier to integrate software by improving the parts of the
S1C6200 CPU which are difficult to use.
This section lists its differences with S1C6200; for items which are not included here, refer to the corre-
sponding section in this manual.
A1 Outline of Differences
• The D (decimal) flag is set to "0" during initial reset.
• Modifications of the interrupt circuit
- The interrupt timing has been shifted to 0.5 clock later.
- <Reference> In the 1-chip micro controller which uses S1C6200A, writing on the interrupt mask register
and reading the interrupt factor flag during EI (enable interrupt flag) are possible. (However, consult
the respective hardware manuals to find out whether these are possible with the CPU peripheral
circuits.)
A2 Detailed Description of the Differences
A2.1 Initial reset
The D (decimal) flag will be set as follows through initial reset:
Table A2.1.1 D (decimal) flag initial setting
CPU Core
D (decimal) flag setting
S1C6200A
S1C6200
0
Undefined
Owing to this, bugs due to omission of D (decimal) flag setting during software development can now be
easily prevented.
For the values of other registers and flags during initial reset, see Section 2.5.4, "Initial reset".
A2.2 Interrupt
Operation during interrupt issuance
The time it takes to complete interrupt processing by hardware after the Core CPU receives the interrupt
request has changed as follows:
Table A2.2.1 Required interrupt processing time
S1C6200A
(clock cycles)
12.5 to 24.5
12.5 to 19.5
12.5 to 17.5
14 to 15
S1C6200
(clock cycles)
13 to 25
Item
a) During instruction execution
b) At HALT mode
12-cycle instruction execution
7-cycle instruction execution
5-cycle instruction execution
13 to 20
13 to 18
14 to 15
c) During PSET instruction execution
PSET + CALL
PSET + JP
12.5 to 24.5
12.5 to 22.5
13 to 25
13 to 23
Figure A2.2.1 shows the timing chart of the S1C6200A interrupt.
84
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S1C6200/6200A CORE CPU MANUAL
APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU
Clock
Status
5-clock Instrruction
12-clock Instrruction
Interrupt
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt processing: 12-clock instruction ... 12.5 to 24.5 clock cycles
7-clock instruction ... 12.5 to 19.5 clock cycles
5-clock instruction ... 12.5 to 17.5 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
a) During instruction execution
System clock
CPU clock
Status
5-clock Instrruction
HALT
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt
Interrupt processing: 14 to 15 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
b) At HALT mode
Clock
Status
PSET
CALL
Interrupt
INT1 (*1)
INT2 (*1)
JP (*2)
Instruction
Interrupt processing: PSET + CALL ... 12.5 to 24.5 clock cycles
PSET + JP ... 12.5 to 22.5 clock cycles
Status:
Fetch
Execute
Note:
(*1) INT1 and INT2 are dummy instructions
(*2) Branches to the top of the interrupt service routine
c) During "PSET" instruction execution
Fig. A2.2.1 Timing chart of S1C6200A interrupt
S1C6200/6200A CORE CPU MANUAL
EPSON
85
APPENDIX A. S1C6200A (ADVANCED S1C6200) CORE CPU
<Reference 1> Writing on the interrupt mask register during EI
This section describes the operation for writing on the interrupt mask register during EI (enable interrupt
flag) in the regular 1-chip micro controller which uses S1C6200 Core CPU and in the regular 1-chip micro
controller which uses S1C6200A Core CPU. For information on accurate operation, see the respective
hardware manuals of the S1C62 Family.
Table A2.2.2 Writing on the interrupt mask register at EI
CPU Core
S1C6200A
S1C6200
Writing on the interrupt mask register at EI
Possible
Not possible
The operation during the instruction execution for writing "0" (i.e., to mask the interrupt factor) on the
interrupt mask register at EI is shown in Figure A2.2.2. At this point, the interrupt is masked 0.5 clock
before the start of the instruction execution through the 0.5 clock advance operation.
Moreover, during the instruction execution for writing "1" (i.e., to cancel the interrupt mask) on the mask
register at EI, it is the same as the ordinary interrupt timing as shown in Figure A2.2.2. In other words, if
the interrupt factor flag value is set to "1", the interrupt processing by hardware will start in the next
instruction execution cycle 0.5 clock before the completion of the instruction execution.
Clock
Fetch
Execute
Fetch
Execute
Fetch
Execute
Fetch
Status
Instruction
"0" is written to the interrupt mask register
Execute next instruction
"1" is written to the interrupt mask register INT1(interrupt processing)
Corresponding
interrupt factor flag
Interrupt request
Fig. A2.2.2 Writing on the interrupt mask register and interrupt request generation
<Reference 2> Reading the interrupt factor flag during EI
This section describes the operation for reading the interrupt factor flag during EI (enable interrupt flag) in
the regular 1-chip micro controller which uses S1C6200 Core CPU and in the regular 1-chip micro control-
ler which uses S1C6200A Core CPU. For information on accurate operation, see the respective hardware
manuals of the S1C62 Family.
Table A2.2.3 Reading the interrupt factor flag at EI
CPU Core
S1C6200A
S1C6200
Reading the interrupt factor flag at EI
Possible
Not possible
At EI, reading the interrupt factor flag is possible but caution must be observed in the following case: when
the value of the interrupt mask register corresponding to the interrupt factor flag which is to be read is set
to "1" (unmasked). In this case, interrupt request may be issued to the CPU due to the timing by which the
interrupt factor flag is set to "1", or the interrupt factor flag may be cleared by reading it and hence inter-
rupt request will not be issued.
Particularly when there are multiple interrupt factor flags in the same address, extra caution is required.
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S1C6200/6200A CORE CPU MANUAL
APPENDIX B. INSTRUCTION INDEX
APPENDIX B. INSTRUCTION INDEX
ACPX MX,r Add with carry r-register to M(X), increment X by 1 ........................... 28
A
ACPY MY,r Add with carry r-register to M(Y), increment Y by 1 ........................... 28
ADC r,i
Add with carry immediate data i to r-register...................................... 29
Add with carry q-register to r-register.................................................29
Add with carry immediate data i to XH................................................30
Add with carry immediate data i to XL ................................................30
Add with carry immediate data i to YH ................................................31
Add with carry immediate data i to YL ................................................31
Add immediate data i to r-register ....................................................... 32
Add q-register to r-register ..................................................................32
Logical AND immediate data i with r-register.....................................33
Logical AND q-register with r-register................................................33
ADC r,q
ADC XH,i
ADC XL,i
ADC YH,i
ADC YL,i
ADD r,i
ADD r,q
AND r,i
AND r,q
CALL s
CALZ s
CP r,i
Call subroutine .....................................................................................34
Call subroutine at page zero ................................................................34
Compare immediate data i with r-register ........................................... 35
Compare q-register with r-register ......................................................35
Compare immediate data i with XH .....................................................36
Compare immediate data i with XL......................................................36
Compare immediate data i with YH .....................................................37
Compare immediate data i with YL ......................................................37
C
D
CP r,q
CP XH,i
CP XL,i
CP YH,i
CP YL,i
DEC Mn
DEC SP
DI
Decrement memory ..............................................................................38
Decrement stack pointer....................................................................... 38
Disable interrupts.................................................................................39
EI
Enable interrupts ..................................................................................39
E
F
FAN r,i
FAN r,q
Logical AND immediate data i with r-register for flag check.............. 40
Logical AND q-register with r-register for flag check.........................40
HALT
Halt ....................................................................................................... 41
H
I
INC Mn
INC SP
INC X
Increment memory by 1 ........................................................................41
Increment stack pointer by 1 ................................................................42
Increment X-register by 1.....................................................................42
Increment Y-register by 1 .....................................................................43
INC Y
JPBA
Indirect jump using registers A and B..................................................43
Jump if carry flag is set ........................................................................44
Jump if not carry ..................................................................................44
Jump if not zero ....................................................................................45
Jump .....................................................................................................45
Jump if zero ..........................................................................................46
J
JP C,s
JP NC,s
JP NZ,s
JP s
JP Z,s
S1C6200/6200A CORE CPU MANUAL
EPSON
87
APPENDIX B. INSTRUCTION INDEX
LBPX MX,e Load immediate data e to memory, and increment X by 2 ................... 46
L
LD A,Mn
LD B,Mn
LD Mn,A
LD Mn,B
Load memory into A-register ............................................................... 47
Load memory into B-register ............................................................... 47
Load A-register into memory ............................................................... 48
Load B-register into memory ............................................................... 48
LDPX MX,i Load immediate data i into MX, increment X by 1............................... 49
LDPX r,q Load q-register into r-register, increment X by 1 ................................49
LDPY MY,i Load immediate data i into MY, increment Y by 1 ............................... 50
LDPY r,q
LD r,i
Load q-register into r-register, increment Y by 1 ................................50
Load immediate data i into r-register .................................................. 51
Load q-register into r-register .............................................................51
Load SPH into r-register ......................................................................52
Load SPL into r-register ......................................................................52
Load XH into r-register ........................................................................53
Load XL into r-register ........................................................................53
Load XP into r-register ........................................................................54
Load YH into r-register ........................................................................54
Load YL into r-register.........................................................................55
Load YP into r-register ........................................................................55
Load r-register into SPH ......................................................................56
Load r-register into SPL ......................................................................56
Load immediate data e into X-register.................................................57
Load r-register into XH ........................................................................57
Load r-register into XL ........................................................................58
Load r-register into XP ........................................................................58
Load immediate data e into Y-register .................................................59
Load r-register into YH ........................................................................59
Load r-register into YL.........................................................................60
Load r-register into YP ........................................................................60
LD r,q
LD r,SPH
LD r,SPL
LD r,XH
LD r,XL
LD r,XP
LD r,YH
LD r,YL
LD r,YP
LD SPH,r
LD SPL,r
LD X,e
LD XH,r
LD XL,r
LD XP,r
LD Y,e
LD YH,r
LD YL,r
LD YP,r
NOP5
NOP7
NOT r
No operation for 5 clock cycles ............................................................61
No operation for 7 clock cycles ............................................................61
NOT r-register (one's complement)......................................................62
N
OR r,i
OR r,q
Logical OR immediate data i with r-register ....................................... 62
Logical OR q-register with r-register ..................................................63
O
P
POP F
Pop stack data into flags ......................................................................63
Pop stack data into r-register............................................................... 64
Pop stack data into XH.........................................................................64
Pop stack data into XL .........................................................................65
Pop stack data into XP .........................................................................65
Pop stack data into YH .........................................................................66
Pop stack data into YL .........................................................................66
Pop stack data into YP .........................................................................67
Page set ................................................................................................67
Push flag onto stack .............................................................................68
POP r
POP XH
POP XL
POP XP
POP YH
POP YL
POP YP
PSET p
PUSH F
88
EPSON
S1C6200/6200A CORE CPU MANUAL
APPENDIX B. INSTRUCTION INDEX
PUSH r
Push r-register onto stack ....................................................................68
Push XH onto stack ..............................................................................69
Push XL onto stack ............................................................................... 69
Push XP onto stack............................................................................... 70
Push YH onto stack ..............................................................................70
Push YL onto stack ............................................................................... 71
Push YP onto stack ............................................................................... 71
P
R
PUSH XH
PUSH XL
PUSH XP
PUSH YH
PUSH YL
PUSH YP
RCF
Reset carry flag ....................................................................................72
Reset decimal flag ................................................................................72
Return from subroutine ........................................................................73
Load immediate data e to memory, and increment X by 2, then return73
Return then skip an instruction ............................................................74
Rotate r-register left with carry ........................................................... 74
Rotate r-register right with carry .........................................................75
Reset flags using immediate data i ....................................................... 75
Reset zero flag ......................................................................................76
RDF
RET
RETD e
RETS
RLC r
RRC r
RST F,i
RZF
SBC r,i
SBC r,q
SCF
Subtract with carry immediate data i from r-register .......................... 76
Subtract with carry q-register from r-register .....................................77
Set carry flag ........................................................................................77
S
X
SCPX MX,r Subtract with carry r-register from M(X) and increment X by 1 .........78
SCPY MY,r Subtract with carry r-register from M(Y) and increment Y by 1.......... 78
SDF
Set decimal flag ....................................................................................79
Set flags using immediate data i........................................................... 79
Sleep .....................................................................................................80
Subtract q-register from r-register....................................................... 80
Set zero flag ..........................................................................................81
SET F,i
SLP
SUB r,q
SZF
XOR r,i
XOR r,q
Exclusive-OR immediate data i with r-register ....................................81
Exclusive-OR q-register with r-register ............................................... 82
S1C6200/6200A CORE CPU MANUAL
EPSON
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S1C6200/6200A
Core CPU Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
First issue February, 1989
M
Printed February, 2001 in Japan
A
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