Regulatory Agency Warnings & Notices
The Emerson ATCA-9305 meets the requirements set forth by the Federal Communications
Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information
is provided as required by this agency.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must
accept any interference received, including interference that may cause undesired opera-
tion.
FCC RULES AND REGULATIONS — PART 15
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason-
able protection against harmful interference when the equipment is operated in a commer-
cial environment. This equipment generates, uses and can radiate radio frequency energy
and, if not installed and used in accordance with the instructions, may cause harmful inter-
ference to radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case the user will be required to correct the interfer-
ence at his own expense.
Caution: Making changes or modifications to the ATCA-9305 hardware without the explicit consent
of Emerson Network Power could invalidate the user’s authority to operate this equipment.
!
EMC COMPLIANCE
The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a
front panel assembly from Emerson Network Power.
Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
!
electromagnetic interference (EMI) shielding to maintain EMC compliance.
GR-1089-CORE STANDARD
Caution: WARNING: The intra-building port(s) of the equipment or subassembly is suitable for
connection to intrabuilding or unexposed wiring or cabling only. The intra-building port(s)
!
of the equipment or subassembly MUST NOT be metallically connected to interfaces that
connect to the OSP or its wiring. These interfaces are designed for use as intra-building
interfaces only (Type 2 or Type 4 ports as described in GR-1089-CORE, Issue 4) and require
isolation from the exposed OSP cabling. The addition of Primary Protectors is not sufficient
protection in order to connect these interfaces metallically to OSP wiring.
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Regulatory Agency Warnings & Notices (continued)
EC Declaration of Conformity
According to EN 45014:1998
Manufacturer’s Name:
Manufacturer’s Address:
Emerson Network Power
Embedded Computing
8310 Excelsior Drive
Madison, Wisconsin 53717
Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC
Directive and 1999/5/EC, RTTE Directive and their amending directives,
Product:
ATCA Blade
Model Name/Number:
ATCA-9305/10009986-xx
has been designed and manufactured to the following specifications:
EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement
EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement
EN300386 V.1.3.2:2003-5 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements
As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an inter-
nal production control system that ensures compliance between the manufactured products and
the technical documentation.
Bill Fleury
Compliance Engineer
Issue date: April 7, 2009
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ATCA-9305 User’s Manual
10009109-01
Contents
Management Processor Header and Serial
Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Diagnostic Tests During Power-up and
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
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Contents (continued)
Watchdog Timer Use Field and
Expiration Flags . . . . . . . . . . . . . . . . 7-12
Using the Timer Use Field and
Expiration Flags . . . . . . . . . . . . 7-13
Monitor Support for Watchdog
Cavium 1 C_MUL Clock Divisor Control
5-11
Timer . . . . . . . . . . . . . . . . . . . . . 7-13
Get LED Color Capabilities Command .
7-19
Cavium 2 C_MUL Clock Divisor Control
5-11
Get Payload Communication Time-Out
7-32
MPC8548 Management Processor Ethernet
Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Set Payload Communication Time-Out
7-32
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Contents (continued)
HPM.1 Reliable Field Upgrade
Procedure . . . . . . . . . . . . . . . . . . . . .7-53
9 Management Processor
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Figures
General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
ATCA-9305 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Component Map, Top (Rev. 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Component Map, Bottom (Rev. 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
LED, Fuse and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
LED and Switch Locations, Bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Configuration Header, J9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Air Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Serial Number and Product ID on Top Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Cavium Processor Complex Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
CN5860 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Example Cavium CN5860 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Power-up/Reset CN5860 Boot Sequence Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
MPC8548 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
MPC8548 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Ethernet Switching Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
IPMC Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Extension Command Request Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Extension Command Response Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Boot Device Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
IPMB Entity Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-47
Zone 1 Connector, P10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Zone 2 and 3 Connectors; J23, J30-J31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Zone 3 Connector, J33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Example MPC8548 Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
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Tables
Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Typical Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
CN5860 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Cavium Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Standard Cavium Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Cavium NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
CN5860 Processor COP/JTAG Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
CN5860 Processor Debug Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
MPC8548 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
MPC8548 Address Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Device Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
PCI Device Interrupts and ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
I2C Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
MPC8548 NVRAM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Serial Debug Connector, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Serial Debug Connector, P7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
PLD Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Low Frequency Timer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Ethernet Switch Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
VLAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Ethernet Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Front Panel Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Completion Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
IPMC IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Emerson Boot Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
IPMC Watchdog Timer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Reset Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Set Watchdog Timer Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Get Watchdog Timer Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
FRU LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Get FRU LED Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Get LED Color Capabilities Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
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Tables (continued)
Set FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Get FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Vendor Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
Get Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Get Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Set Serial Interface Properties Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
Get Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
Set Debug Level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
Get Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
Set Hardware Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
Get Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Set Handle Switch Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Get Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
Set Payload Communication Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
Enable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
Disable Payload Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Reset IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Hang IPMC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Bused Resource Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Bused Resource Status Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
Graceful Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Diagnostic Interrupt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Get Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Set Payload Shutdown Time-Out Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Set Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
Get Local FRU LED State Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
Update Discrete Sensor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Update Threshold Sensor Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
Add Message Listener Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Remove Message Listener Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44
Get Message Listener List Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-45
Update System Firmware Progress Sensor Command . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
IPMI Threshold Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
IPMI Discrete Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
FRU Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-50
Link Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
IPMP CPLD JP1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53
IPMP EIA-232 P4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53
Zone 1 Connector, P10 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Zone 2 Connector, J23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
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Tables (continued)
Zone 3 Connector, J30 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Zone 3 Connector, J31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Zone 3 Connector, J33 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Debug LED Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
POST Diagnostic Results–Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Monitor Address per Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Static IP Ethernet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
DHCP Ethernet Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
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Registers
Register 3-1: Data 31:24 (0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Register 3-2: Data 23:16 (0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3-3: Data 15:8 (0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3-4: Data 7:0 (0x3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Register 3-5: Address 9:8 (0x4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Register 3-6: Address 7:0 (0x5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Register 3-7: Control (0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Register 3-8: Version (0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Register 3-9: Scratch (0x8-0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Register 5-1: Product ID (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Register 5-2: Hardware Version (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Register 5-3: PLD Version (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Register 5-4: PLL Reset Configuration (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Register 5-5: Hardware Configuration 0 (0x10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Register 5-6: Jumper Settings (0x18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Register 5-7: LED (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Register 5-8: Reset Event (0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Register 5-9: Reset Command 1 (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-10: Reset Command 2 (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-11: Reset Command 3 (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Register 5-12: Reset Command 4 (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-13: Reset Command 5 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Register 5-14: Reset Command Sticky #1 (0x38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-15: Reset Command Sticky #2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Register 5-16: Boot Device Redirection (0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-17: Miscellaneous Control (0x54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Register 5-18: RTM GPIO State (0x60). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-19: RTM GPIO Control (0x64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Register 5-20: RTM Control (0x68). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-23: JTAG (0x78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-24: Cavium GPIO Control (0x80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Register 5-25: Cavium GPIO Data Out (0x84) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 5-26: Cavium GPIO Data In (0x88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Register 5-27: IPMP/IPMC GPIO Control (0x8C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 5-28: LPC Bus (0xD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Register 5-29: LPC Data (0xD4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 5-30: Serial IRQ Interrupts 1 (0xD8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Register 5-31: Serial IRQ Interrupts 2 (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
i
10009109-01
ATCA-9305 User’s Manual
Section 1
Overview
The ATCA-9305 is an Advanced Telecom Computing Architecture (AdvancedTCA®, ATCA®)
blade based on dual Cavium OCTEON™ CN5860 processors and the Freescale™ Semicon-
ductor MPC8548 management processor. This blade is targeted at security and packet-pro-
cessing applications in the wireless and transport market segments. These markets include
data-plane packet-processor, security co-processor, video compression, and pattern match-
ing.
The ATCA-9305 complies with the SCOPE recommended profile for central office ATCA sys-
tems, PICMG® 3.0 ATCA mechanical specifications, E-keying, and Hot Swap.
COMPONENTS AND FEATURES
The following is a brief summary of the ATCA-9305 hardware components and features:
Cavium Processor : The Cavium CN5860 processor is a highly programmable, high-performance 16-core archi-
tecture operating up to 800 MHz.
Management Processor:
The Freescale PowerQUICC™ III MPC8548 processor is a 32-bit enhanced e500 core operat-
ing at 1 GHz.
Ethernet Switch: The Broadcom® BCM56802 is a sixteen-port, 10 GbE switch which interconnects the pro-
cessors using SPI to XAUI™ bridges. The functionality includes both 10-Gbps XAUI and 1-
Gbps SGMII PHY interfaces.
Stratix™ GX Bridge: There are two packet routing Altera® SPI-4.2 high-speed interconnect to XAUI bridges per
CN5860 processor.
Ethernet: 10/100/1000BASE-T Ethernet ports are accessible via the front panel RJ45 connectors and
through the base channel on the back panel. The 10 GbE ports route to the back panel
through the fabric and RTM connectors.
Serial Port: The front panel serial port (MGT CSL) connects to the MPC8548 management processor.
System Management: This product supports an Intelligent Platform Management Controller (IPMC) based on a
proprietary BMR-H8S-AMCc® reference design from Pigeon Point Systems. The IPMC has
an inter-integrated circuit (I2C) controller to support an Intelligent Management Platform
Bus (IPMB) that routes to the AdvancedTCA connector. The IPMB allows for features such as
remote shutdown, remote reset, payload voltage monitoring, temperature monitoring,
and access to Field Replaceable Unit (FRU) data.
PCI/PCIe: The PCI bus allows for read/write memory access between the MPC8548 processor, Ether-
net switch, and Cavium processors. The four lane PCI Express® (PCIe) routes between the
MPC8548 and the optional RTM.
1-1
10009109-01
ATCA-9305 User’s Manual
Overview: Components and Features
Real-time Clock: The STMicroelectronics M41T00S RTC provides counters for seconds, minutes, hours, day,
2
date, month, years, and century. The M41T00S serial interface supports I C bus and has a
super-cap backup capable of maintaining the clock for a minimum of two hours.
Software: The Cavium CN5860 processor provides a GNU compiler that implements the MIPS64 Rel 2
instruction set in addition to the specialized instructions and a Linux® Board Specific Pack-
age (BSP) including the IP-stack optimization. The CN5860 also provides libraries that take
advantage of the chip’s hardware acceleration for certain security protocols.
RTM (optional): This blade supports a custom Rear Transition Module (RTM) with the following I/O:
• Either two or six 10GbE connections
• One x4 PCI Express port from the MPC8548
• Connections for an MMC to control Hot Swap
• MPC8548 console port
For more detailed information, see the ATCA-9305 Rear Transition Module User’s Manual.
1-2
ATCA-9305 User’s Manual
10009109-01
Overview: Functional Overview
FUNCTIONAL OVERVIEW
The following block diagram provides a functional overview for the ATCA-9305:
Figure 1-1: General System Block Diagram
Console
Socketed
ROM
RJ45
RJ45
512KB
x 8
KSL
CPLD
Console
Console
(ENG use only)
(ENG use only)
Mag
Mag
Latched Adrs
A/D
NOR
Flash
4M
BCM5461S BCM5461S
x 16
NAND
Flash
1GB
Adrs/Data
COP/JTAG
x 16
MPC8548
Management
Processor
I2C
EEPROM
NOR
Flash
512Mb or
64MB x 16
PQ DDR2
SDRAM
I2C
EEPROM
P2 DDR2
SDRAM
COP/
JTAG
COP/
JTAG
P1 DDR
SDRAM
PCIe x4
RTC
BCM5461S
PCI Bus
D1_DDR2 Serial 0
I2C
Serial 0 D1_DDR2
I2C
PCI
Bus
IDSEL11
PCI
Bus
IDSEL12
I2C
I2C
Serial CFG
EEPROM
3
4
PCI Bus
SGMII
SGMII
IDSEL13
I2C
EEPROM
I2C
EEPROM
Cavium
Octeon
CN5860
Cavium
Octeon
CN5860
Stratix II GX
#3
SPI-0
6 XAUI
SPI-0
XAUI 13
Stratix II GX
#1
BCM56802
XAUI 10 Gb
Switch
Processor 1
Processor 2
RLDRAM
64MB
RLDRAM
64MB
SPI-1
5 XAUI
Stratix II GX
#2
Stratix II GX
#4
XAUI 14
To RTM
XAUI
SPI-1
Local Bus
Addr/Data
Serial 1
Local Bus
Addr/Data
RLDRAM
64MB
RLDRAM
64MB
SGMII
2
SGMII
1
XAUI
8
7
11-12 15 -18
Serial 1
RLDRAM
64MB
RLDRAM
64MB
Socketed
ROM
512K
x 8
Socketed
ROM
512K
x 8
NOR
Flash
4M
NOR
Flash
4M
BCM5482
10G - 4 PORTS
10G - 2 PORTS
IPMB
RLDRAM
64MB
RLDRAM
64MB
x 8
x 8
Mag
Mag
RTM RST
1
2
3
2
FC2
1
0
3
2
FC1
1
0
12V Hot Swap
RTM Console
PQ I2C
Base
10G Fabric
P10
J23
J30
J31
J33
1-3
10009109-01
ATCA-9305 User’s Manual
Overview: Additional Information
ADDITIONAL INFORMATION
This section lists the ATCA-9305 hardware’s regulatory certifications and briefly discusses
the terminology and notation conventions used in this manual. It also lists general technical
references.
Mean time between failures (MTBF) has been calculated at 439,924 hours using the Telcor-
dia SR-332, Issue 1 (Reliability Prediction for Electronic Equipment), method 2 at 30° C.
Product Certification
The ATCA-9305 hardware has been tested to comply with various safety, immunity, and
emissions requirements as specified by the Federal Communications Commission (FCC),
Underwriters Laboratories (UL), and others. The following table summarizes this compli-
ance:
Table 1-1: Regulatory Agency Compliance
Type:
Specification:
Safety
IEC60950/EN60950 – Safety of Information Technology Equipment
(Western Europe)
UL60950, CSA C22.2 No. 60950 – Safety of Information Technology
Equipment, including Electrical Business Equipment (BI-National)
GR1089-CORE
Global IEC – CB Scheme Report IEC 60950, all country deviations
Environmental
NEBS: Telecordia GR-63 –
Section 4.1.1 Transportation and Storage Environmental Criteria;
Section 4.1.2 Operating Temperature and Humidity;
Section 4.1.3 Altitude;
Section 4.1 4 Temperature Margins;
Section 4.4.1 Earthquake Environment;
Section 4.4.4 Office Vibration:
Section 4.4.5 Transportation Vibration
1-4
ATCA-9305 User’s Manual
10009109-01
Overview: Additional Information
Type:
Specification:
(continued)
EMC
FCC Part 15, Class A– Title 47, Code of Federal Regulations, Radio
Frequency Devices
ICES 003, Class A – Radiated and Conducted Emissions, Canada
NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack
level testing only)
EN55022 – Information Technology Equipment, Radio Disturbance
Characteristics, Limits and Methods of Measurement
EN55024 – Information Technology Equipment, Immunity
Characteristics, Limits and Methods of Measurement
ETSI EN300386 – Electromagnetic Compatibility and Radio Spectrum
Matters (ERM), Telecommunication Network Equipment,
Electromagnetic Compatibility (EMC) Requirements
AS/NZS 3548 003, Class A – Standard for radiated and conducted
emissions for Australia and New Zealand
Emerson maintains test reports that provide specific information regarding the methods
and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or
a poorly grounded chassis may adversely affect the ATCA-9305 hardware’s ability to comply
with any of the stated specifications.
The UL web site at ul.com has a list of Emerson’s UL certifications. To find the list, search in
the online certifications directory using Emerson’s UL file number, E190079. There is a list
for products distributed in the United States, as well as a list for products shipped to Can-
ada. To find the ATCA-9305, search in the list for 10009986-xx, where xx changes with each
revision of the printed circuit board.
The Ethernet connection of the equipment or subassembly must be connected with
shielded cables that are grounded at both ends.
RoHS Compliance
The ATCA-9305 is compliant with the European Union’s RoHS (Restriction of use of Hazard-
ous Substances) directive created to limit harm to the environment and human health by
restricting the use of harmful substances in electrical and electronic equipment. Effective
July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexava-
lent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers
(PBDEs) and lead (Pb). Configurations that are RoHS compliant are built with lead-free sol-
der.
To obtain a certificate of conformity (CoC) for the ATCA-9305, send an e-mail to
[email protected] or call 1-800-356-9602. Have the part number(s)
(e.g., C000####-##) for your configuration(s) available when contacting Emerson.
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10009109-01
ATCA-9305 User’s Manual
Overview: Additional Information
Terminology and Notation
Active low signals: An active low signal is indicated with an asterisk * after the signal name.
Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to
32 bits, double long word refers to 64 bits.
PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also
known as FPGA, CPLD, EPLD, etc.).
Radix 2 and 16: Hexadecimal numbers end with a subscript 16. Binary numbers are shown with a
subscript 2.
Technical References
Further information on basic operation and programming of the ATCA-9305 components
Table 1-2: Technical References
Device /
Interface:
1
Document:
ATCA
AdvancedTCA® Base Specification
(PICMG® 3.0 Revision 2.0 March 18, 2005)
Engineering Change Notice 3.0-1.0-001
(PICMG® 3.0 R2.0: ECN 3.0-2.0-001 June 15, 2005)
Ethernet/Fibre Channel for AdvancedTCA™ Systems
(PICMG® 3.1 Revision 1.0 January 22, 2003)
CPU
Cavium Networks OCTEON™ Plus CN58XX Hardware Reference Manual
CN5860
MPC8548
(Cavium Networks, CN58XX-HM-1.2 Sept. 2008)
MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual
(Freescale™ Semiconductor, Inc. MPC8548ERM Rev.2, 02/2007
DRAM
576Mb: x9, x18, x36 2.5V VEXT, 1.8C VDD, HSTL, CIO,RLDRAM II Data Sheet
(Micron Technology, Inc. 576Mb_RLDRAM_II_CIO_D1.fm - Rev C 9/07 EN)
http://www.micron.com
EEPROM
Atmel® 2-Wire Serial EEPROM 64K (8192 x 8) Preliminary Data Sheet
(Atmel Corporation, 5174C-SEEPR-6/07)
Ethernet
10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet
BCM5461S
BCM5482
(Broadcom® Corporation, Document 5461S-DS17-R 5/12/08)
10/100/1000BASE-T Gigabit Ethernet Transceiver Data Sheet
(Broadcom® Corporation, Document 5482-DS04-R 10/18/07)
1-6
ATCA-9305 User’s Manual
10009109-01
Overview: Additional Information
Device /
Interface:
1
Document:
(continued)
Flash
32 Mbit (x8/x16) Concurrent SuperFlash Data Sheet
(Silicon Storage Technology, Inc., S71270-01-000 9/05)
mDOC H3 Embedded Flash Drive (EFD) featuring Embedded TrueFFS® Flash Management
Software Preliminary Data Sheet
(msystems 92-DS-1205-10 Rev. 0.2 June 2006)
StrataFlash® Embedded Memory (P33) Data Sheet
(Intel®, Order Number: 314749-004 November 2007)
4. Serial Configuration Devices (EPCS1, EPCA4, EPCS16, & EPCS64)
(Altera® Corporation CS1014-2.0 April 2007)
IPMI
IPMI — Intelligent Platform Management Interface Specification v2.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.0, Feb. 12, 2004)
IPMI — Intelligent Platform Management Bus Communications Protocol Specification v1.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.0, November 15, 1999)
IPMI — Platform Management FRU Storage Definition v1.0
(Intel Hewlett-Packard NEC Dell, Rev. 1.1, September 27, 1999)
Hardware Platform Management IPM Controller Firmware Upgrade Specification v1.0
(PICMG HPM.1 R1.0 May 4, 2007)
RTC
Serial Access Real-Time Clock Data Sheet
M41T00S
(STMicroelectronics December 2004)
Switch
BCM56800 Series 20-Port 10-Gigabit Ethernet Multilayer Switch Preliminary Data Sheet
BCM56802
(Broadcom® Corporation, Document 56800-DS03-R 12/28/07)
1. Frequently, the most current information regarding addenda/errata for specific documents may be
found on the corresponding web site.
1-7
10009109-01
ATCA-9305 User’s Manual
Section 2
Setup
This chapter describes the physical layout of the boards, the setup process, and how to
check for proper operation once the boards have been installed. This chapter also includes
troubleshooting, service, and warranty information.
ELECTROSTATIC DISCHARGE
Before you begin the setup process, please remember that electrostatic discharge (ESD) can
easily damage the components on the ATCA-9305 hardware. Electronic devices, especially
those with programmable parts, are susceptible to ESD, which can result in operational fail-
ure. Unless you ground yourself properly, static charges can accumulate in your body and
cause ESD damage when you touch the board.
Caution: Use proper static protection and handle ATCA-9305 boards only when absolutely
necessary. Always wear a wriststrap to ground your body before touching a board. Keep
!
your body grounded while handling the board. Hold the board by its edges–do not touch
any components or circuits. When the board is not in an enclosure, store it in a static-
shielding bag.
To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a static-
shielding bag does not provide any protection–place it on a grounded dissipative mat. Do
not place the board on metal or other conductive surfaces.
ATCA-9305 CIRCUIT BOARD
The ATCA-9305 circuit board is an ATCA blade assembly and complies with the PICMG 3.0
ATCA mechanical specification. It uses a 16-layer printed circuit board with the following
dimensions:
Table 2-1: Circuit Board Dimensions
Width:
Depth:
Height:
Weight (typical):
12.687 in.
(322.25 mm)
11.024 in.
(280.01 mm)
< .84 in.
(<21.33 mm)
4.2 lb.
(1.91 kg)1
1. This is the typical weight for the ATCA-9305. Board weight varies slightly per configuration; contact
Technical Support if you require a specific configuration weight.
The following figures show the front panel, component maps, and LED locations for the
ATCA-9305 circuit board.
2-1
10009109-01
ATCA-9305 User’s Manual
Setup: ATCA-9305 Circuit Board
Figure 2-1: ATCA-9305 Front Panel
Ethernet Speed (top LED)
Off = 10 Mbps
MGT ETH
SPD
Yellow = 100 Mbps
Green = 1000Mbps
Port 1
Port 2
LINK
ACT
O
O
S
Red/Amber = Out of Service (OOS)
Green = In Service (2)
SPD
2
3
Ethernet Link/Activity (bottom LED)
Off = No Link
On= Link, No Activity
Blink = Link/Activity
LINK
ACT
SWITCH
ETH
Amber = User Defined (3)
MGT CSL
Management Console
RST
H/S
Reset
Blue Hot Swap
ATCA-9035
Note: The electromagnetic compatibility (EMC) tests used an ATCA-9305 model that includes a front panel assem-
bly from Emerson Network Power, Embedded Computing.
Caution: For applications where the ATCA-9305 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
!
electromagnetic interference (EMI) shielding to maintain CE compliance.
2-2
ATCA-9305 User’s Manual
10009109-01
Setup: ATCA-9305 Circuit Board
Figure 2-2: Component Map, Top (Rev. 01)
R1
C2146
C2109
C3
C7
C8
C13
C9
C10
C14
U1
C5
Polar Key
C4
C6
C12
C11
U2
ATCA Guide
U4
J1
F1
U3S
U5
L1
U6
M1
M2
C33
R20
C41
R21
C42
R23
R24
R25
R22
J33
U7
C52
C344
C53
R26
C54
R37
R38
L2
24-pin ATCA
Connector
U8
R35
R36
U9
C69
C58
C2119
C68
C2108
C75
R43
R44
R45
R46
U10
C2116
C74
C82
C73
R47
R48
C85
C92
C77
C78
C86
R1010
C79
C76
L4
C80
C87
SPI-XAUI
Bridge
C81
C90
R49
R51
L6
R52
C98
C93
C107
R50
L7
C106
C126
C113
R54
R60
C114
C115
C116
CR5
CR6
CR7
CR8
C112
R55
C117
P1
C118
C2145
C119
C2147
RJ45
C2110
C128
U11
C129
C131
C132
R72
F2
R68
C133
C134
C148
C149
C165
C166
C180
C181
C190
C191
C202
C203
C217
C218
C229
C230
C135
C136
C150
C151
C167
C168
C182
C183
C192
C193
C204
C205
C219
C220
C231
C232
C137
C138
C152
C153
C169
C170
C184
C185
C194
C195
C206
C207
C221
C222
C233
C234
C139
C140
C154
C155
C171
C172
C186
C187
C196
C197
C208
C209
C223
C224
C235
C236
R69
R73
U12
R74
R75
R76
R78
R79
R80
R77
R81
J31
80-pin
C141
C157
C173
C163
U13
C158
C174
C159
C176
C160
C177
C161
C178
C162
C175
P2
SPI-XAUI
Bridge
U15
CN58x0
Processor 2
C198
C214
C199
C215
C200
C216
C201
L8
C227
C240
C247
C255
C271
R82
Zone 3
ATCA
P3
U14
R83
C212
C211
C225
C213
R84
R86
R85
R87
R334
R332
CR9
RJ45
C228
C241
C248
C256
C272
C226
C238
C239
CR10
CR11
CR12
J3 J4 J5 J6
R88
R89
R90
R91
C243
C244
C245
C246
C254
Connector
R92
R93
R94
R95
C242
C250
R1060
C249
C257
C259
C261
C262
C277
C278
C295
C296
C263
C264
C279
C280
C297
C298
C313
C314
C323
C324
C335
C336
C354
C355
C359
C360
C258
C273
C274
C291
C292
C307
C308
C260
C275
C276
C293
C294
C309
C310
C251
C252
C253
C267
C268
C269
C270
J30
C265
C289
C290
R96
R97
C300
C301
C302
C303
C304
C305
C306
C311
80-pin
C299
C312
C321
C322
C333
C334
C352
C353
C357
C358
C317
C319
C320
C327
R2
C367
C332
C350
C356
C318
C326
Zone 3
ATCA
Y1
C331
C341
C342
R101
C2104
C2113
C368
U16
Connector
C370
C369
C375
C371
R108
C373
R109
C374
C372
R1
1
1
C376
R112
R115
R116
U19
C383
U17
U18
C386
C397
C392
C393
C387
MPC8548
Processor
C398
Y2
C399
C403
C400
C404
SO-CDIMM
U20
L11
C437
C417
C423
C436
U21
C412
R123
R141
C413
C414
C415
C416
C345
C418
C419
C420
C421
C422
C434
C435
Polar Key
RN5
RN6
RN7
ATCA Guide
Y9
C440
CR13
CR14
CR16
RN8
RN9
C449
C460
C451
C450
R160
R161
R162
R167
L23
L24
R1041
C455
U24
KSL
C462
R163
CR15
C461
C465
R166
R164
R168
R169
C480
C481
R165
U23S
CR18
CR19
CR21
CR22
C468
C469
C482
C483
C470
C471
C484
C485
C488
C489
C490
C491
C464
C474
CR17
R170
C467
Y3
R171
R174
L25
L33
J9
Y7
CR20
R173
L26
L29
L32
L34
CPLD
CR31
CR32
CR33
L31
L27
L30
L28
U25
U26
C492
Y5
U29
RN11
RN12
U34
U28
U30
Y4
U27
L35
CR34
U32
U31
R183
R184
R192
R193
R181
R182
R190
R191
L37
L38
L39
BCM5680x
Switch
U33
U40
U41
U42
U36 U37 U38
U39
U35S
P5
L41
Y6
R1050
SPI-XAUI
Bridge
SPI-XAUI
Bridge
C499
C500
C501
C526
C527
C528
C529
C531
L43
L45
L46
L48
L42
L44
R197
R196
R200
F3
L47
U43
U44
P6
P7
Y8
Mini-B
C581
R208
L58
L59
C580
U47
R210
R213
R214
R217
U45
R21
1
USB
C590
C591
C597
C598
C603
C604
C607
C608
U48
L60
L61
R212
R215
R216
U46
C602
C606
Micro-
U50
R219
C605
U51 U52
R218
R1056
controller
PHY
R1057
R220
R221
U53
L64
R225
R226
C618
R228
C619
C620
C621
R227
C712
C624
C626
C625
C633
U54
R241
R242
C635
J23
+
C636
C638
C639
C642
C640
C641
C643
C637
80-pin
Zone 2
C644
U55
12V
C650
C651
C652
C653
C654
C655
C656
L65
ATCA
C649
U56
CN58x0
Processor 1
C660
C659
Power Supply
R246
Connector
R245
C662
C670
C663
C671
C664
C672
C665
R244
C661
C673
R247
C674
R251
R252
C669
C668
U58
R250
C678
C676
C2118
R1059
J11 J12 J13 J14
C677
C681
C682
C683
C684
C690
C2106
C2111
C680
C731
C792
C686
C692
C698
C700
R259
C693
R260
R261
R262
R258
C691
+
C687
C688
C689
U59 U60
C685 C697
C694
C695
C696
C2149
C702
C703
C704
C705
C706
C707
C708
C699
C701
C709
C723
F4
F5
C719
C2148
R268
C720
R269
C721
C710
C722
C732
C730
C734
C2107
C2117
+
C767
C733
C2120
R273
R274
C743
F6
U62
P10
R275
U61
C744
R278
R279
R280
C775
30-pin
Zone 13
ATCA
C748
L66
C751
C794
R281
C763
R283
R284
C764
C765
C766
L67
F7
F8
C776
C782
C790
C777
C783
C791
L68
C768
F10
+
Connector
C787
C788
C789
C793
U63
L69
F9
U65
C796
C797
C800
C801
R295
R296
C2112
C2105
2-3
10009109-01
ATCA-9305 User’s Manual
Setup: ATCA-9305 Circuit Board
Figure 2-3: Component Map, Bottom (Rev. 01)
C2100
J16
R1005
R1003
R1000
R999
R1002
R1001
R998
R997
C2096
C2099
U82
U81
C2094
C2092
C2091
C2090
C2089
C2087
C2085
R979
R978
R976
R975
R974
R973
C2086
R972
R971
R970
R966
C2070
C2069
C2082
C2080
C2081
C2068
C2067
C2075
C2076
Q5
C2079
C2066
C2065
C2078
C2063
C2064
C2077
C2061
C2062
C2074
C2057
C2056
C2073
C2054
C2055
C2072
C2053
C2052
C2071
C2051
C2050
C2059
C2060
R968
R967
R965
R964
R959
R958
R950
R949
R943
R942
R936
R935
R929
R928
R921
R920
R916
R915
R963
R962
R957
R956
R948
R947
R941
R940
R913
R933
R927
R926
R919
R918
R914
C2046
R961
R960
R934
R955
R954
R946
R953
R952
R945
C2022
R951
SW2
R1037
R937
C1954
C1951
C1948
C1945
C1942
C1939
C1936
C1933
C1930
C1926
R939
R932
R931
R925
R924
R938
R930
C1901
C1879
C1925
R923
R922
R917
C1878
C1840
C1839
C1838
C1875
C1837
C1836
C1872
C1835
C1834
C1869
C1833
C1832
C1866
C1831
C1830
C1861
C1829
C1828
C1858
C1827
C1826
C1842
C1822
C1825
C1824
C1823
C1841
R911
R910
R909
R904
R903
R908
R905
C1821
C1815
C1817
C1816
C1810
C1809
U80
L100
C1807
C1806
R880
R879
R878
R867
R866
R850
R849
R841
R840
R1042
R877
R851
C1793
R852
R847
R848
R838
R837
R846
R835
R843
R842
R834
R833
R836
R845
R844
C1788
C1787
C1790
C1789
R831
R830
C1784
C1783
C1782
C1759
R832
R828
U79 U78
C1761
R827
R826
R1051
R1052
C1760
R820
C1756
C1755
C1752
C1751
R825
C1753
C1750
C1749
C1748
C1747
C1746
C1742
C1741
R802
R1046
R122
L96
C1743
C2154
C2180
C2187
C2185
C1728
C1724
C1727
C1725
C1721
C1700
C1678
C1651
C2179
R784
C1726
C1722
C1723
R783
R780
R779
C1701
R758
C1714
C1709
C1708
C1707
C1705
C1704
C1703
C1680
C1657
C1702
C2126
C1712
C2128
C1690
R781
C1710
R782
C1706
R775
R774
R777
C1685
C1679
C1696
R778
R776
C1684
C1683
C1682
C1681
R760
C1687
C1665
C1686
C1664
C1659
C1654
R768
R767
C1718
R764
R763
C1713
R1015
R1016
C1660
C1663
C1629
C1662
C1661
C1658
C1656
C1655
C1653
C1652
R766
R1028
C1624
C1642
C1643
R762
R1029
C1641
C2127
R756
R752
R751
R750
C1627
R749
R748
C1628
C1626
C2157
L103
L101
L94
R754
R745
R744
C2153
C2151
C2155
L95
R741
R740
C1599
C1598
C1596
C1597
C1594
C1592
C1591
C1589
C1590
C1609
C1608
C1607
C1604
C1601
C1602
C1588
C1586
C1617
C1625
C2191
C1585
C1549
C1513
C1485
C1467
R746
C1606
C1603
C1595
C1552
C1517
C1497
C1593
C1587
C1600
R747
C1605
C1550
C1553
C1518
C1519
C1498
C1474
C1454
R1033
C1557
C1556
C1521
C1554
C1555
C1551
C1581
C1547
C1546
C1545
C1578
C1543
C1542
C1544
C1575
C1541
C1568
C1534
C1561
C1529
C1530
R739
C1515
R718
R738
R737
R726
R725
R716
C1537
R736
R735
C1522
C1516
C1514
R729
C1524
C1523
C1503
C1539
C1540
C1510
C1531
C1532
R730
C1520
C1499
C1548
C1512
C1538
C1525
R721
R720
C1481
R713
R712
R728
R723
R722
C1502
C1501
C1500
C1494
C1495
C1472
C1493
C1492
C1491
C1488
C151
1
C1506
R719
C1487
C1486
C1504
C1496
C1473
C1490
C1489
C1469
R717
R711
C1482
C1477
C1475
C1476
C1457
C1479
C1462
R715
R714
R701
C1478
C1458
C1471
C1451
C1470
C1450
C1468
R710
R704
R703
R702
R695
C1459
C1447
R693
C1456
C1438
C1452
C1453
C1449
C1448
C1466
R694
C1446
C1432
C1408
C1396
C2186
C1460
C1455
C1437
C2176
R691
R690
R675
C1441
C1440
C1439
C1434
C1433
C1445
C1444
C1442
R692
L93
C1416
C1415
C1412
C1409
C1419
C1420
C1413
C1414
C1411
C1410
C1418
C1417
C1407
C1406
C1405
C1403
C1388
R672
C1402
C1400
C1398
C1397
R673
R668
R665
R664
C1404
C1399
C1391
R671
R667
R669
C1390
C1386
C1385
C1384
C1383
C1382
C1381
C1380
C1379
R666
C1372
U76
C1377
U77
R661
R660
R656
R655
R648
R659
R658
R654
R653
R647
C1368
C1357
R662
R657
R652
R646
StrataFlash
PHY
R645
R642
R641
R638
R637
R629
R628
R620
R619
C1353
C1355
R644
R643
C1347
C1351
C1349
C1348
C1345
C1344
R640
R639
C1346
C1343
U75
NAND
Flash
C1337
C1336
C1335
R632
R631
R623
R622
R616
C1340
C1315
C1334
C1332
C1331
C1328
C1327
C1339
C1313
C1297
R630
C1338
C1317
C1323
C1320
C1319
C1318
R621
R615
R611
C1312
C1311
C1309
C1305
C1306
C1295
C1296
C1279
C1280
C1281
C1262
C1263
C1303
C1304
C1293
C1294
C1276
C1277
C1278
C1260
C1261
C1301
C1300
U74 U73
C1310
C1308
C1307
C1282
C1299
C1290
R610
R609
R608
R606
R607
C1291
C1289
C1272
C1287
C1284
C1283
C1285
C1271
R602
C1288
C1268
C1286
C1274
C1273
R605
R604
R598
R597
R592
R591
R586
R585
R570
R569
C1267
C1266
C1265
C1258
C1259
R600
R599
R594
R593
R588
R587
R580
R579
R566
R565
C1257
C1250
R603
R596
R595
R590
R589
R584
R583
R568
R567
R601
C1255
C1256
C1251
C1248
C1249
C1241
C1242
C1240
R582
R581
C1238
C1232
C1233
C1237
C1231
C1230
C1226
R1022
R1021
R564
C1225
C1224
U72
U70
U69
R539
U71
PHY
C1221
L86
C1220
C1219
R520
R502
R519
R501
R517
R499
L85
R500
R497
R496
R481
R480
R498
R495
R494
R479
R478
R464
R463
C1217
C1216
L84
C1214
C1213
C1212
C1196
C1195
C121
1
C1210
C1187
C1188
C1209
C1208
C1184
C1207
C1205
C1204
C1176
C1203
C1202
C1201
C1200
C1170
C1198
C1199
C1167
R482
C1192
C1191
C1206
C1181
C2193
C2188
R468
R467
R458
R457
R451
R450
R441
R440
R430
R429
R420
R419
R409
R408
R397
R396
R393
R466
R465
R456
R455
R449
R406
R439
R438
R428
R427
R418
R417
R407
C1173
R469
C2177
C1159
R459
R453
R452
R442
R454
R447
R446
Q4 Q3
R1048
L82
L81
C1 15
1
R444
R433
R443
R431
R422
R436
R448
R1038
R435
C1052
R425
C1
1
12
C1109
C1106
C1103
C1100
C1097
C1094
C1091
C1088
R445
R434
R412
R401
C1083
C1080
R1013
R1014
C1076
C1078
C1082
C1051
R432
R424
R426
R414
R413
R403
C1077
C1042
C2129
R416
R421
C1044
C1009
C1010
C1043
C1006
C1007
C1041
C1040
C1002
C1001
C1000
C942
C1039
C2132
C999
R415
R405
R404
C1050
C1017
R423
L79
C1016
C1005
C1003
R411
L78
C2158
C940
C2160
R 4 0 2
C101
1
C1008
C947
C946
C1004
L106
C956
C955
R400
R399
C948
C949
C945
C944
C941
R395
R394
R392
C939
C938
C908
C907
C937
C936
C906
C935
C934
C905
C933
C932
C904
C931
C930
C903
C928
C927
C902
C925
C926
C901
R398
C943
C2130
C912
C910
C894
C900
C899
C898
C913
C917
C909
C896
C895
Q2 Q1
R385
R388
R387
R386
R383
R382
L76
C893
R384
R380
R381
C892
C891
C890
C889
C888
R377
R376
R378
R358
R339
C2175
C886
C885
R357
R356
R340
R336
R335
C884
C883
R338
R337
R331
R330
R325
R324
C882
L75
L72
C881
C2135
C866
C 8 6 4
C 8 6 5
C 8 4 9
C 8 4 8
C 8 3 2
C 8 3 3
C870
C869
C853
C852
C836
C837
C868
C867
C851
C850
C834
C835
C862
C863
C846
C847
C831
C830
U68
C859
L108
C2163
C2165
L73
PHY
C838
R323
U67 U66
C826
R322
R320
R321
C820
C812
R318
R319
R316
R315
C2170
C2167
C2182
R309
R307
R306
R305
R304
R298
C807
C806
C805
C804
R299
R297
2-4
ATCA-9305 User’s Manual
10009109-01
Setup: ATCA-9305 Circuit Board
Figure 2-4: LED, Fuse and Switch Locations, Top
CR1 - P2_LED_GPIO12-R
J1
CR2 - P2_LED_GPIO13-R
CR3 - P2_LED_GPIO14-R
CR4 - P2_LED_GPIO15-R
F1
F1 - .75 Amp Fuse
(self resetting)
F2
F2 - .75 Amp Fuse
(self resetting)
P2
MPC8548
CR13 - PQ_GREENLED_R*
CR14 - PQ_CKSTP_OUT_R*
CR16 - PQ_REDLED_R*
Debug
CR18 - DEBUG_LED1_R*
CR19 - DEBUG_LED2_R*
CR21 - DEBUG_LED3_R*
CR22 - DEBUG_LED43_R*
Boot Device
CR31 - FL0_LED_R*
CR32 - FL1_LED_R*
CR33 - SKT_LED_R*
CR13
CR14
CR16
Ethernet
CR15 - TSEC2_ACTIVITY
CR15
CR18
CR19
CR21
CR22
J9
CR31
CR32
CR33
CR23 - MIP1_LED1_R
CR24 - MIP1_LED2_R
CR25 - MIP1_LED3_R
CR26 - MIP1_LED4_R
SW1 - IPMC Reset
F3
Ethernet
CR44 - BC1_LINKSPD1/2
CR45 - BC1_LINKSPD1/2
CR46 - BC1_ACT*
CR47 - BC2_LINKSPD1/2
CR48 - BC2_LINKSPD1/2
CR49 - BC2_ACT*
F3 - .75 Amp Fuse
(self resetting)
IPMP State
CR35 - STATE_LED8
+
CR36 - STATE_LED7
CR37 - STATE_LED6
CR38 - STATE_LED5
CR39 - STATE_LED4
CR40 - STATE_LED3
CR41 - STATE_LED2
CR42 - STATE_LED1
+
CR43 - STATE_LED0
F4
F5
F6
+
F4 - 1 Amp Fuse
F5 - 1 Amp Fuse
F6 - 10 Amp Fuse
F7 - 8 Amp Fuse
F8 - 10 Amp Fuse
F7
F8
CR50 - P1_LED_GPIO12_R1
CR51 - P1_LED_GPIO13_R1
CR52 - P1_LED_GPIO14_R1
CR53 - P1_LED_GPIO15_R1
F9 - 8 Amp Fuse
+
F9
F10
F10 - .75 Amp Fuse
(self resetting)
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Setup: ATCA-9305 Circuit Board
Figure 2-5: LED and Switch Locations, Bottom
J16
Hot Swap
CR57 - BLUE_LED_CONN_K
SW2
SW2 - Front Panel Reset
Front Panel
CR54 - Red = LED1R_CONN
Amber = LED1A_CONN
CR55 - LED2_CONN
CR56 - LED3_CONN
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Setup: ATCA-9305 Circuit Board
Connectors
The ATCA-9305 circuit board has various connectors and headers (see the figures beginning
on page 2-3), summarized as follows:
J3-J6: These 240-pin sockets are installed for the CN5860 processor 1 DDR2 SDRAM memory.
J9: This 14-pin configuration header allows selection of boot device, and MPC8548 configura-
J11-J14: These 240-pin sockets are installed for the CN5860 processor 2 DDR2 SDRAM memory.
J23: The 80-pin Zone 2 connector provides 1 GB and 10 GB Ethernet access to the backplane, see
J33: The 24-pin Zone 3 connector routes the reset, Hot Swap, MPC8548 console, power, and
2
JP1: This is the 10-pin programming header for the IPMP, CPLD, and SPI 10G (1-4) devices, see
P1: This 14-pin RJ45 connector with LEDs routes the Three-speed Ethernet Controller (TSEC1)
P3: This 14-pin RJ45 connector with LEDs routes Ethernet (FP1) between the switch and the
P5, P6: These 5-pin vertical mini-B USBs are the CN5860 console and for factory debug use only.
P7: This 5-pin mini-B USB is the console serial port for the MPC8548 management processor,
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Setup: ATCA-9305 Setup
Configuration Header
There are a total of seven jumper pairs on J9 (pins 11-14 are spare posts). See figure Fig. 2-2
ister.
Figure 2-6: Configuration Header, J9
13 11 9 7 5 3 1
14 12 10 8 6 4 2
BT SKT: A shunt on pins 1-2 selects the 512 KB socketed ROM as the boot device for the MPC8548.
IG SROM: If the serial ROM configuration jumper is installed (pins 3-4), the ATCA-9305 will not try to
configure (IGNORE_SROM*) from the MPC8548 serial ROM.
REDIR EN: A shunt installed on pins 5-6 disables the boot redirection, see page 7-41 for more informa-
tion.
BOOT: A shunt on pins 7-8 causes both Cavium CN5860s to boot from their local bus and not boot
over PCI.
STAND: A shunt on pins 9-10, IPMC stand alone mode, allows the board to boot without manage-
ment control.
PROG: Installing a shunt on pins 11-12 puts the IPMC controller into programming mode. This is
only used in the factory to configure the IPMC.
BT FLASH: If BOOT shunt is installed (booting from local bus), this shunt determines whether the boot
is from local flash or socket. When this BT FLASH shunt is installed, the ATCA-9305 boots
from flash. Otherwise, it boots from the socket.
ATCA-9305 SETUP
You need the following items to set up and check the operation of the Emerson ATCA-9305:
ATCA chassis and power supply
MPC8548 Console cable for EIA-232 port, Emerson part # C0007662-00
Computer terminal
Save the antistatic bag and box for future shipping or storage.
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Setup: ATCA-9305 Setup
Power Requirements
The ATCA-9305 circuit board uses —48 volts from the backplane to derive 3.3 volts for the
IPMC and 12 volts for payload power.
Table 2-2: Typical Power Requirements
Configuration:
Power:
1.0 GHz MPC8548 and 800 MHz Cavium processors,
board running at room temperature with all
processors at U-Boot prompt
135 watts
The exact power requirements for the ATCA-9305 circuit board depend upon the specific
configuration of the board, including the CPU frequency and amount of memory installed
on the board. Please contact Emerson Technical Support at 1-800-327-1251 if you have
specific questions regarding the board’s power requirements.
Environmental Considerations
As with any printed circuit board, be sure that air flow to the board is adequate. Chassis con-
straints and other factors greatly affect the air flow rate. The environmental requirements
are as follows:
Table 2-3: Environmental Requirements
Environment:
Range:
Relative Humidity:
Operating Temperature
Storage Temperature
Altitude
0° to +55° Centigrade, ambient
(at board)
Not to exceed 85% (non-
condensing)
—40° to 85° Centigrade
Not to exceed 95%
(non-condensing)
0 to 4,000 meters above sea
level
—
Air Flow
Requires 30 CFM at 55° Centigrade at sea level. Meets thermal
performance requirements of CP-TA ATCA ICD Book 1.1Class B-2
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Setup: ATCA-9305 Setup
Figure 2-7: Air Flow Graph
Hot Swap
The ATCA-9305 can be Hot Swapped, as defined in the AdvancedTCA specification (see ref-
in a typical AdvancedTCA system. (These procedures assume the system is using a shelf
manager.)
Note: The ATCA-9305 Rear Transistion Module (RTM) has its own Hot Swap LED and switch, and it can be Hot
Swapped in/out independently of the front board. If the front board is not present, then the RTM will not be
powered. If the front board is Hot Swapped out, the RTM’s blue LED will illuminate. In either case, the RTM can
be safely removed.
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Setup: Troubleshooting
Insert a board:
1
2
Insert the ATCA-9305 into an available slot.
Push in the front panel handle (tab).
board insertion is in progress and system management software is activating the slot. Then
the blue LED turns off, indicating the insertion process is complete, and payload power is
present.
Remove a board:
1
2
Pull out the handle (tab) on the ATCA-9305 front panel one click.
A short blink indicates the board is requesting permission for extraction.
Remove the board when the blue LED on the front panel is on (no payload power).
Caution: Do not remove the ATCA-9305 while the blue LED is blinking.
!
TROUBLESHOOTING
In case of difficulty, use the following checklist:
Be sure the ATCA-9305 circuit board is seated firmly in the carrier.
Be sure the system is not overheating.
Check the cables and connectors to be certain they are secure.
Check that your terminal is connected to a console port.
Technical Support
• version and part number of the operating system (if applicable)
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Setup: Troubleshooting
• whether your board has been customized for options such as a higher processor speed or
additional memory
• license agreements (if applicable)
If you do not have internet access, please call Emerson for further assistance:
(800) 327-1251 or (608) 826-8006 (US)
44-131-475-7070 (UK)
Figure 2-8: Serial Number and Product ID on Top Side
Serial Number
Product ID
Product Repair
[email protected] to obtain a Return Merchandise Authorization (RMA) number. We
will ask you to list which items you are returning and the board serial number, plus your pur-
chase order number and billing information if your ATCA-9305 hardware is out of warranty.
Contact our Test and Repair Services Department for any warranty questions. If you return
the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally
shipped. Send it prepaid to:
Emerson Network Power, Embedded Computing
Test and Repair Services Department
8310 Excelsior Drive
Madison, WI 53717
RMA #____________
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ATCA-9305 User’s Manual
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Setup: Troubleshooting
Please put the RMA number on the outside of the package so we can handle your problem
efficiently. Our service department cannot accept material received without an RMA num-
ber.
Comments and Suggestions
We welcome and appreciate your comments on our documentation. We want to know
what you think about our manuals and how we can make them better.
http://www.emersonnetworkpowerembeddedcomputing.com/ Contact Us > Online Form
In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part
number, and revision of the manual and tell us how you used it.
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ATCA-9305 User’s Manual
Section 3
Cavium Processor Complex
The ATCA-9305 provides two Cavium processor complexes. The major devices on each
complex consist of the Cavium CN5860 processor, two StratixGX bridges, SDRAM,
2
RLDRAM®, an I C EEPROM, socketed ROM, Flash, and the PCI bus interface.
Figure 3-1: Cavium Processor Complex Block Diagram
Console
Console
(ENG use only)
(ENG use only)
P2 DDR2
SDRAM
COP/
JTAG
COP/
JTAG
P1 DDR
SDRAM
PCI Bus
D1_DDR2 Serial 0
I2C
Serial 0 D1_DDR2
I2C
PCI
Bus
IDSEL11
PCI
Bus
IDSEL12
I2C
I2C
Serial CFG
EEPROM
PCI Bus
IDSEL13
I2C
EEPROM
I2C
EEPROM
Stratix II GX
#3
SPI-0
6 XAUI
5 XAUI
SPI-0
XAUI 13
XAUI 14
Stratix II GX
#1
Cavium
Octeon
CN5860
Cavium
Octeon
CN5860
BCM56802
XAUI 10 Gb
Switch
RLDRAM
64MB
RLDRAM
64MB
Processor 1 SPI-1
Processor 2
Stratix II GX
#2
Stratix II GX
#4
SPI-1
Local Bus
Addr/Data
Local Bus
Addr/Data
RLDRAM
64MB
RLDRAM
64MB
Socketed
ROM
512K x8
Socketed
ROM
512K x8
RLDRAM
64MB
RLDRAM
64MB
RLDRAM
64MB
NOR
Flash
4M x8
NOR
Flash
4M x8
RLDRAM
64MB
Serial 1
Serial 1
Cavium Processor Complex 1
Cavium Processor Complex 2
CAVIUM CN5860 PROCESSOR
The main features of the CN5860 include:
Table 3-1: CN5860 Features
Feature:
Description:
Processor Core
Up to 16 cnMIPS™ cores
Core Speed
up to 800 MHz, processing up to 30 million packets per second
Network Services Processor (NSP)
System Packet Interface
Two SPI-4.2 ports
L2 Cache
DRAM
RLDRAM
PCI
2 MB, eight-way set associative
144-bit DDR2 DRAM interface
18-bit RLDRAM, low-latency memory direct access
64-bit, PCI 2.3 compatible
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Cavium Processor Complex: PCI
The CN5860 and switch route packets using SPI-4.2 and control information flow using PCI.
The CN5860 has two SPI-4.2 interfaces with each one supporting up to 16 ports. Two high-
speed SPI-4.2 Altera (Stratix™ GX) FPGAs function as the SPI-to-XAUI bridge for each pro-
cessor to switch complex. The PCI interface supports up to four ports, consequently a total
of 36 ports can be supported internally by each CN5860.
Cavium Memory Map
Although the Cavium processors are 64-bit, the ATCA-9305 uses a 49-bit implementation.
Refer to the Cavium Networks OCTEON Plus CN58xx Hardware Reference Manual for more
detailed information on the memory map.
Table 3-2: Cavium Address Summary
Hex Physical
Address:
Register Description:
reserved
1,2000,0000,0000
1,1F00,0000,0000
1,1E00,0000,0000
1,1D00,0000,0000
1,1C00,0000,0000
1,1B00,0000,0000
1,1A00,0000,0000
1,1910,0000,0000
1,1900,0000,0000
1,0700,0000,0000
1,0001,0000,0000
1,0000,0000,0000
0,0004,1000,0000
0,0004,0000,0000
0,0000,2000,0000
0,0000,1000,0000
0,0000,0000,0000
Cavium Hardware registers
PCI Memory Space (6)
PCI Memory Space (5)
PCI Memory Space (4)
PCI Memory Space (3)
PCI I/O Space
reserved
PCI Special Space
CN58xx Registers
reserved
Local Boot Bus
DDR2 SDRAM, middle block (256-512 MB)
reserved
DDR2 SDRAM, upper block (512 MB-2 GB)1
reserved
DDR2 SDRAM, bottom block (256 MB)
1. This depends on how much memory is installed.
PCI
The Cavium is a slave device on the PCI bus. The Cavium U-boot monitor image is provided
by the MPC8548 management processor via PCI. The MPC8548 monitors the Cavium boot
status and has the ability to try alternate boot images if the current one fails.
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Cavium Processor Complex: PCI
The CN5860 processor is designed such that another PCI device can initialize its memory
interface, copy code over PCI into its local memory space, and then write a boot release reg-
ister.
CN5860 Boot Over PCI
The PCI bus is configured to run at 66 MHz in 64-bit conventional PCI mode. On power-up,
the CN5860 processor’s 16 internal cores are held in reset. The MPC8548 management pro-
cessor performs the following steps:
1
2
3
4
5
Initialize the CN5860 RAM.
Copy the CN5860 U-boot to the CN5860 RAM.
Copy boot code to the reset vector to jump to the U-boot code in RAM.
Release the CN5860 processor cores from reset.
Receive return codes from the CN5860 that indicate any boot or POST errors and take the
appropriate action.
The management processor (MPC8548) monitor implements a utility to load non-volatile
memory redundant U-boot images for the CN5860 processors. The utility tags each copy as
primary or secondary.
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Cavium Processor Complex: PCI
Cavium Reset
Each CN5860 can be reset independently of the other processor without affecting its opera-
tion. This task is performed by the MPC8548 management processor.
Figure 3-2: CN5860 Reset Diagram
3_3V_MP
33MHz
P1_RESET*
P1_PCI_RST*
P1_PWRGD
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
CN5860
Cavium
Processor 1
IPMP
CPLD
1_0V_PWRGD
PQ_CORE_PWRGD
P1_CORE_PWRGD
P2_CORE_PWRGD
P2_RESET*
P2_PCI_RST*
P2_PWRGD
CN5860
Cavium
Processor 2
PWRGD_OK
3_3V_MP
Front
Panel
Reset
3_3V
Voltage
Monitor
Delay
P1_DDR_RST*
P2_DDR_RST*
3_3V_MP
MC Reset
P1 DDR
SDRAM
POR_RST*
Voltage
Monitor
Delay
KSL
CPLD
P2 DDR
SDRAM
I2C IO L_PAYLOAD_RST*
Port
MIP1_RST*
MIP2_RST*
MIP3_RST*
MIP4_RST*
Stratix II GX
XAUI#1
3_3V_MP
Hot Swap
Switch
Stratix II GX
XAUI#2
E_HANDLE
IPMC
Stratix II GX
XAUI#3
48A_OK
48B_OK
Stratix II GX
XAUI#4
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Cavium Processor Complex: Cavium Ethernet
CAVIUM ETHERNET
The Ethernet address for your board is a unique identifier on a network. The address con-
sists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:
00 80 F9 xx yy zz
00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte); 0x99(SPI 1), 0x9A (SPI 2), 0x9B (SPI 3), or 0x9C (SPI 4), followed by the serial
number (two byte hexadecimal). The ATCA-9305 Cavium has been assigned the Ethernet
Table 3-3: Ethernet Port Address
Offset:
MAC:
Description:
Ethernet Identifier (hex):
Byte 5
15:0
LSB of (serial number in hex)
MSB of (serial number in hex)
—
—
Byte 4
Byte 3
23:16
47:24
SPI 1
SPI 2
SPI 3
SPI 4
0x99
0x9A
0x9B
0x9C
Byte 2
Byte 1
Byte 0
Assigned to Emerson by IEEE
0xF9
0x80
0x00
The last two bytes, MAC[15:0], are calculated from the serial number stored in the Cavium
EEPROM. This corresponds to the following formula: n —1000, where n is the unique serial
number assigned to each board. So if an ATCA-9305 serial number is 1032, the calculated
value is 32 (20 ), and the default Ethernet port addresses are:
16
• Cavium 1 SPI 1 MAC address is: 0x00 0x80 0xF9 0x99 0x00 0x20
• Cavium 1 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9A 0x00 0x20
• Cavium 2 SPI 1 MAC address is: 0x00 0x80 0xF9 0x9B 0x00 0x20
• Cavium 2 SPI 2 MAC address is: 0x00 0x80 0xF9 0x9C 0x00 0x20
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Cavium Processor Complex: Cavium Monitor
CAVIUM MONITOR
The primary function of the monitor software is to transfer control of the hardware to the
user’s application. Secondary responsibilities include:
• low-level initialization of the hardware
• diagnostic tests
• low-level monitor commands/functions to aid in debug
Start-up Display
At power-up or after a reset, the Cavium monitor runs diagnostics and reports the results in
configures the board according to the environment variables (see “MPC8548 Environment
Variables” on page 9-26). If the configuration indicates that autoboot is enabled, the moni-
tor attempts to load the application from the specified device. If the monitor is not config-
ured for autoboot or a failure occurs during power-up, the monitor enters normal
hardware boot of the ATCA-9305.
Figure 3-3: Example Cavium CN5860 Monitor Start-up Display
U-Boot 1.1.1 (Jan 16 2009 - 14:26:14)0.9
OCTEON CN58XX-NSP revision: 1
Hardware initialization
Core clock: 750 MHz
DDR clock: 266 MHz (533 Mhz data rate)
DRAM: 4096 MB
Flash: 4 MB
Clearing DRAM........ done
PCI console init succeeded, 1 consoles, 1024 bytes each
Net:
octspi0, octspi1
RLDRAM not present
Octeon BIST Passed
POST i2c PASSED
POST memory PASSED
2 ATCA-9305 (Mon 0.9)=>
Monitor command prompt
Note: There will be either a 1 or 2 in front of the monitor prompt indicating which Cavium processor is prompting.
Power-up/Reset Sequence
the operating system or application software. At power-up or board reset, the monitor per-
forms hardware initialization, diagnostic routines, autoboot procedures, and if necessary,
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Cavium Processor Complex: Cavium Monitor
Figure 3-4: Power-up/Reset CN5860 Boot Sequence Flowchart
Power-up or Reset
Cavium Hardware
Wait for PCI load of U-boot
U-Boot Monitor
Default Board Initialization
U-Boot Monitor
Execute POST
U-Boot Monitor
Start Autoboot Sequence
(Boot Operating System)
Operating System Boot
Boot OS image
according to
configuration parameters
Diagnostic Tests During Power-up and Reset
The Cavium monitor diagnostic tests can be executed during power-up or invoked from the
monitor’s command prompt. This is accomplished by changing the state of the monitor
configuration parameters that define power-up and reset diagnostics mode. If the poweron-
diags parameter is set to “on”, the monitor invokes the diagnostic tests after a reset of the
hardware. Results are displayed to the console including whether the test passed or failed.
POST Diagnostic Results
The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
memory accessible by the management console at location 0x80080A6C. Each bit indicates
the result of a specific test, so this field can store the results of up to 32 diagnostic tests.
Table 3-4 assigns the bits to specific tests.
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Cavium Processor Complex: Cavium Monitor
Table 3-4: POST Diagnostic Results–Bit Assignments
Diagnostic
Bit:
0-1
2
Test:
Reserved
DRAM
Description:
Value:
Verify address and data lines are intact
-
0
1
Passed the test
Failure detected
3
Cavium BIST
I2C
4
Verify all local I2C devices are connected
to the I2C bus
5-31
Reserved
Cavium Environment Variables
The following table lists the standard Cavium environment variables:
Table 3-5: Standard Cavium Environment Variables
Default
Variable:
Value:
Description:
baudrate
115200
Console port baud rate
Valid rates: 9600, 14400, 19200, 38400, 57600, 115200
bootcmd
bootdelay
" "
0
Command to execute when auto-booting or executing
the ‘bootd’ command
Choose the number of seconds the Monitor counts down
before booting user application code
Valid options: time in seconds, -1 to disable autoboot
bootfile
" "
Path to boot file on server (used with TFTP)—set this to
“path/file.bin” to specify filename and location of the file
to load.
ethaddr
eth1addr
ethact
undefined
undefined
octspi0
SPI 1 MAC address
SPI 2 MAC address
Specifies Ethernet port to use
Select the network gateway machine IP address
Target hostname
gatewayip
hostname
ipaddr
0.0.0.0
none
0.0.0.0
Board IP address
loadaddr
0x20000000
Define the address to download user application code
(used with TFTP)
netmask
0.0.0.0
off
Board sub-network mask
powerondiags
Turns POST diagnostics on or off after power-on/reset
Valid options: on, off
rootpath
serial#
eng/
Path name of the NFS’ server root file system
Board serial number
xxxxx
0.0.0.0
serial
serverip
stderr
Boot server IP address
Sets the standard destination for console error reporting
Valid options: serial, pci
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Cavium Processor Complex: Memory
Default
Variable:
Value:
Description: (continued)
stdin
serial
Sets the standard source for console input
Valid options: serial, pci
stdout
serial
Sets the standard destination for console output
Valid options: serial, pci
MEMORY
The processor complex supports DDR2 Synchronous DRAM (SDRAM) and Reduced Latency
DRAM (RLDRAM) memory devices.
DDR2 SDRAM
The ATCA-9305 supports up to 16 gigabytes of 144-bit wide DDR2 SDRAM per processor
complex. The SDRAM interface clock speed frequency is 400 MHz. The four low-profile,
dual-inline memory modules (buffered DIMM) are installed in 240-pin very low profile (VLP)
sockets to reduce board density and routing constraints. A 2 KB EEPROM on the DIMM pro-
vides the serial presence detection (SPD). On-card SDRAM occupies physical addresses
from 0,0000,0000,0000 to 0,0003,FFFF,FFFF
.
16
16
Each processor memory bus is operating in 144-bit mode. Error-correcting Code (ECC) is
performed on the memory bus so that the CN5860 detects all double-bit errors, multi-bit
errors within a nibble, and corrects all single-bit errors.
RLDRAM
Each CN5860 supports 256 MB Common I/O (CIO) RLDRAM operating up to 400 MHz
(depends on the processor speed). The Micron RLDRAM II is organized as 32Mx18x8 internal
banks. The DDR I/O interface transfers two data words per clock cycle. Output data is refer-
enced to the free-running output data clock. Read and write accesses to the RLDRAM are
burst-oriented. RLDRAM is accessed by using Cavium-specific instructions which operate on
MIPS Coprocessor 2.
I2C EEPROM
Each Cavium processor complex has one user EEPROM device for parameter storage located
2
2
on the I C bus, address 0xA8. The I C bus for each processor is completely independent
2
from the other CN5860 processor and MPC8548 processor I C buses. The Atmel two-wire
serial EEPROM on each CN5860 processor I C interface consists of the Serial Clock (SCL)
2
input and the Serial Data (SDA) bidirectional lines.
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Cavium Processor Complex: StratixGX Interconnect
Table 3-6: Cavium NVRAM Memory Map
Address Offset
(hex):
0x1E00-0x1FFF
0x0000-0x1D36
Window
Size (bytes)
256
Description:
Monitor parameters
User defined
79F
Flash, 512 KB x 8
The 512 KB of 32-pin PLCC socketed flash starts at physical address1D46,0000 and is used
16
for Engineering code. The StrataFlash features high-performance fast asynchronous access
times, low power, and flexible security options.
Flash, 4 MB x 16
The 4 MB soldered NOR flash starts at physical address 1D05,0000 The 32-Mbit device
16.
provides CN5860 code storage and non-volatile memory.
STRATIXGX INTERCONNECT
The Altera StratixGX FPGA provides the high-speed SPI-4.2 interconnect. Each complex has
dual SPI-to-XAUI bridges connected to the XAUI Ethernet switch ports.
PLD Registers
The FPGA bridge is located at address 0x1D030000. Use the following registers to access
Data Registers
Register 3-1: Data 31:24 (0x0)
Bits:
7
R/W:
R/W
Function:
Data 31
Data 30
Data 29
Data 28
Data 27
Data 26
Data 25
Data 24
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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ATCA-9305 User’s Manual
10009109-01
Cavium Processor Complex: StratixGX Interconnect
Register 3-2: Data 23:16 (0x1)
Bits:
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function:
Data 23
Data 22
Data 21
Data 20
Data 19
Data 18
Data 17
Data 16
7
6
5
4
3
2
1
0
Register 3-3: Data 15:8 (0x2)
Bits:
R/W:
Function:
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data 8
Register 3-4: Data 7:0 (0x3)
Bits:
R/W:
Function:
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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ATCA-9305 User’s Manual
Cavium Processor Complex: StratixGX Interconnect
Address Registers
Register 3-5: Address 9:8 (0x4)
Bits:
R/W:
Function:
7
6
5
4
3
2
1
0
—
Reserved
—
—
—
—
—
R/W
R/W
Address 9
Address 8
Register 3-6: Address 7:0 (0x5)
Bits:
R/W:
Function:
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control Register
The write only Control register performs two functions:
• Writing a value of 0x01 causes the contents of the Data registers to be written to the
FPGA bridge at the location specified by the Address registers.
• Writing a value of 0x02 causes the contents of the Data registers to be overwritten by the
contents of the FPGA bridge at the location specified by the Address registers.
Note: Writing any other value to the Control register will be ignored.
Register 3-7: Control (0x6)
Bits:
R/W:
Function:
7
6
5
4
3
2
—
—
—
—
—
—
Reserved
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10009109-01
Cavium Processor Complex: StratixGX Interconnect
Bits:
1
0
R/W:
W
Function:
Read
W
Write
Version Register
This read-only register tracks the PLD versions. The version is hard coded in the PLD and
changes with every released code change. Version starts at 01
.
16
Register 3-8: Version (0x7)
Bits:
R/W:
Function:
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
0x01
Scratch Register
All registers in this range act as the same register.
Register 3-9: Scratch (0x8-0x3F)
Bits:
R/W:
Function:
7
R/W
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Example: To read the FPGA bridge SPI_COMMAND register at 0x204, use the following commands.
Set address bits 9:8.
=>write64b 1d030004 02
Set address bits 7:0.
=>write64b 1d030005 04
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ATCA-9305 User’s Manual
Cavium Processor Complex: Headers and Connectors
Perform a read.
=>write64b 1d030006 02
Display the results.
=>read64l 1d030000
Write Example: To write to the FPGA bridge MAC_CMD_CFG register at 0x00C, use the following com-
mands.
Set data bits 31:24.
=>write64b 1d030000 a9
Set data bits 23:16.
=>write64b 1d030001 b8
Set data bits 15:8.
=>write64b 1d030002 c7
Set data bits 7:0.
=>write64b 1d030003 d6
Set address bits 9:8.
=>write64b 1d030004 00
Set address bits 7:0.
=>write64b 1d030005 0c
Perform a write.
=>write64b 1d030006 01
HEADERS AND CONNECTORS
COP/JTAG Headers
The CN5860 processor complex uses headers J1 and J15 for debug.
Table 3-7: CN5860 Processor COP/JTAG Headers
Pin:
J1 (processor 2):
P2_ETRST*
ground
J15 (processor 1):
P1_ETRST*
ground
1
2
3
4
P2_TDI
P1_TDI
ground
ground
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ATCA-9305 User’s Manual
10009109-01
Cavium Processor Complex: Headers and Connectors
Pin:
5
J1 (processor 2):
P2_ETDO
J15 (processor 1): (continued)
P1_ETDO
6
ground
ground
7
P2_TMS
P1_TMS
8
ground
ground
9
P2_TCK
P1_TCK
10
11
12
13
14
ground
ground
P2_EJTAG_RST
key (pin not installed)
P2_EJTAG_DINT
P2_COP_PWR (3.3V)
P1_EJTAG_RST
key (pin not installed)
P1_EJTAG_DINT
P1_COP_PWR (3.3V)
Console Serial Ports (optional)
Connectors P6 (processor P1) and P5 (processor P2) access the CN5860 processors for Engi-
neering debug use only. The supported baud rates for these ports operate at 9600, 14400,
19200, 38400, 57600, and 115200 bps. (The default rate is 115200 bps.)
Table 3-8: CN5860 Processor Debug Headers
Pin:
P6:
P5:
1
no connect
no connect
P2_SER1_RXD
P2_SER1_TXD
no connect
signal ground
signal ground
2
P1_SER1_RXD
P1_SER1_TXD
no connect
signal ground
shield
3
4
5
6-7
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ATCA-9305 User’s Manual
Section 4
Management Complex
The ATCA-9305 management complex is comprised of the Freescale MPC8548 processor,
2
CPLD, SDRAM, flash, I C EEPROM, Real-time Clock, and PCI bus interface. Board power-up,
booting and monitoring the Cavium processors, PCI bus arbitration, interrupt servicing,
memory persistence functionality, and other board level management tasks are imple-
mented using the MPC8548 processor. The MPC8548 stores the Cavium operating system
and monitor code in its local memory and then uses the boot over PCI functionality to bring
Chapter 9 for the Management Processor Monitor.
The management complex connects to the Broadcom Ethernet switch via a 1000BASE-T
Ethernet port. This connection uses the TSEC2 interface operating in SGMII mode. See
Figure 4-1: MPC8548 Management Processor Complex Block Diagram
Console
RJ45
RJ45
Socketed
ROM
Management Processor Complex
512KB
x 8
PHY
PHY
KSL
CPLD
Latched Adrs
NOR
Flash
4M
A/D
x 16
NAND
Flash
1GB
Adrs/Data
COP/JTAG
x 16
MPC8548
Management
Processor
I2C
EEPROM
NOR
Flash
512Mb or
64MB x 16
PQ DDR2
SDRAM
I2C
EEPROM
PCIe x4
RTC
PHY
To Cavium
Processor 1
PCI Bus
To Cavium
Processor 2
& Ethernet Switch
3
4
PCI Bus
SGMII
SGMII
IDSEL13
BCM56802
XAUI 10 Gb
Switch
J30
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ATCA-9305 User’s Manual
Management Complex: MPC8548 Processor
MPC8548 PROCESSOR
The MPC8548 processor has the following features:
Table 4-1: MPC8548 Features
Feature:
Description:
L1 Cache
32-kilobyte data and instruction caches with parity protection, 32-
byte line, eight-way set associative
L2 Cache
512 kilobytes, eight-way set associative
1 GHz with a 400 MHz DDR2 bus
CPU Core Speed
DDR2 Memory Controller
64-bit data interface, four banks of memory supported (each up to 4
GB), full ECC support
Two-wire interface, master or slave I2C support
Loads configuration data from serial ROM at reset via the I2C interface
Dual I2C Controllers
Boot Sequencer
Ethernet
Four 10/100/1000 enhanced three-speed controllers (eTSECs), full-
/half-duplex support, MAC address recognition
Local Bus Controller (LBC)
DDR2 SDRAM memory controller, General Purpose Chip Select
Machine (GPCM), three User-Programmable Machines (UPM), eight
chip selects support eight external slaves
PCI
64-bit, PCI 2.2 compatible
PCI Express
Single x4 PCIe high-speed interconnect, complies with PCI Express™
Base Specification Revision 1.0a
JTAG
Complies with IEEE Std. 1149.1
For more detailed information, reference the Freescale MPC8548E PowerQUICC™ III Inte-
grated Processor Family Reference Manual.
MPC8548 Memory Map
The monitor can boot from either the soldered flash (Bank 1, default) or the socketed PLCC
16
4-2
ATCA-9305 User’s Manual
10009109-01
Management Complex: MPC8548 Processor
Figure 4-2: MPC8548 Memory Map
Hex Address
Serial IRQ Interrupt 2
Serial IRQ Interrupt 1
LPC Data
FC40,00DC
FC40,00D8
FC40,00D4
FC40,00D0
FC40,008C
FC40,0088
FC40,0084
FC40,0080
FC40,0078
FC40,0074
FC40,0070
FC40,0068
FC40,0064
FC40,0060
FC40,0054
FC40,0050
FC40,0040
FC40,003C
FC40,0038
FC40,0034
FC40,0030
FC40,002C
FC40,0028
FC40,0024
FC40,0020
FC40,001C
FC40,0018
FC40,0014
FC40,0010
FC40,000C
FC40,0008
FC40,0004
FC40,0000
Address Range
FFFF,FFFF
FFF0,0000
FFEF,FFFF
FF80,0000
FF7F,FFFF
LPC Bus Control
Boot Window (512 KB)
Reserved (7.5 MB)
IPMP/IPMC GPIO Control
Cavium GPIO Data Input
Cavium GPIO Data Output
Cavium GPIO Control
Altera JTAG Software Control
Cavium 2 Clock Divisor Control
Cavium 1 Clock Divisor Control
RTM Control
RTM GPIO Control
RTM GPIO State
Miscellaneous Control
Boot Device Redirection
Scratch #1
Reset Command Sticky #2
Reset Command Sticky #1
Reset Command #5
Reset Command #4
Reset Command #3
Reset Command #2
Reset Command #1
Reset Event
MPC8548 CCSRBAR (1 MB)
Reserved (46 MB)
FF70,0000
FF6F,FFFF
FC88,0000
FC87,FFFF
Socketed Flash, optional (512 KB)
Reserved (3.5 MB)
FC80,0000
FC7F,FFFF
FC48,0000
FC47,FFFF
CPLD Registers (512 KB)
Reserved (2.9 MB)
FC40,0000
FC3F,FFFF
FC11,0000
FC10,FFFF
LPC Interface (64 KB)
Reserved (992 KB)
FC10,0000
FC0F,FFFF
FC00,8000
FC00,7FFF
NAND Flash (32 KB)
FC00,0000
LED
Jumper Setting
reserved
FBFF,FFFF
Reserved (64 MB)
F800,0000
F7FF,FFFF
Hardware Configuration 0
PLL Configuration
PLD Version
Soldered Flash Bank 4 (32 MB)
Soldered Flash Bank 3 (32 MB)
Reserved (56 MB)
F600,0000
F5FF,FFFF
F400,0000
F3FF,FFFF
Hardware Version
Product ID
F080,0000
F3FF,FFFF
Soldered Flash Bank 2 (4 MB)
Soldered Flash Bank 1 (4 MB)
PCI Express I/O (16 MB)
PCI Express (256 MB)
PCI (1.5 GB)
F3C0,0000
F3BF,FFFF
F380,0000
F0FF,FFFF
F000,0000
EFFF,FFFF
E000,0000
DFFF,FFFF
8000,0000
7FFF,FFFF
0000,0000
SDRAM DDR2 (2 GB)
Table 4-2: MPC8548 Address Summary
Hex Physical
Address:
FFF8,0000
FF80.0000
FF70,0000
FC88,0000
Access
Mode:
R/W
—
See
Page:
—
Register Description:
Boot window (512 KB)
reserved (7.5 MB)
R/W
—
MPC8548 CCSRBAR (1MB)
reserved (46 MB)
—
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ATCA-9305 User’s Manual
Management Complex: MPC8548 Processor
Hex Physical
Address:
Access
Mode:
R/W
—
See
Page:
Register Description: (continued)
Socketed flash, optional (512 KB)
reserved (3.5 MB)
FC80,0000
FC48,0000
FC40,00DC0
FC40,00D8
FC40,00D4
FC40,00D0
FC40,008C
FC40,0088
FC40,0084
FC40,0080
FC40,0078
FC40,0074
FC40,0070
FC40,0068
FC40,0064
FC40,0060
FC40,0054
FC40,0050
FC40,0040
FC40,003C
FC40,0038
FC40,0034
FC40,0030
FC40,002C
FC40,0028
FC40,0024
FC40,0020
FC40,001C
FC40,0018
FC40,0014
FC40,0010
FC40,000C
FC40,0008
FC40,0004
FC40,0000
FC11,0000
FC10,0000
FC00,8000
FC00,0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Serial IRQ Interrupt 2
Serial IRQ Interrupt 1
LPC Data
Low Pin Count (LPC) Bus Control
IPMP/IPMC GPIO Control
Cavium GPIO Data Input
Cavium GPIO Data Output
Cavium GPIO Control
Altera JTAG Chain Software Control
Cavium 2 C_MUL Clock Divisor Control
Cavium 1 C_MUL Clock Divisor Control
RTM Control
RTM GPIO Control
RTM GPIO State
Miscellaneous Control (SIO, I2C, Test Clock)
Boot Device Redirection
Scratch #1
—
Reset Command Sticky #2
Reset Command Sticky #1
Reset Command #5
W
Reset Command #4
W
Reset Command #3
W
Reset Command #2
W
Reset Command #1
R/W
R/W
R/W
—
Reset Event
LED
Jumper Setting
reserved
—
R/W
R/W
R/W
R/W
R/W
Hardware Configuration 0
PLL Configuration
PLD Version
Hardware Version
Product ID (CPLD 512 KB)
reserved (2.9 MB)
R/W
—
LPC Interface (64 KB)
reserved (992 KB)
R/W
NAND flash (32 KB)
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ATCA-9305 User’s Manual
10009109-01
Management Complex: MPC8548 Processor
Hex Physical
Address:
Access
Mode:
—
See
Page:
Register Description: (continued)
reserved (64 MB)
F800,0000
F600,0000
F400,0000
F080,0000
F3C0,0000
F380,0000
F000,0000
E000,0000
8000,0000
0000,0000
R/W
R/W
—
Soldered flash bank 4 (32 MB)
Soldered flash bank 3 (32 MB)
reserved (56 MB)
R/W
R/W
R/W
R/W
R/W
R/W
Soldered flash bank 2 (4 MB)
Soldered flash bank 1 (4 MB)
PCI Express I/O space (16 MB)
PCI Express (256 MB)
PCI (1.5 GB)
SDRAM DDR2 (2 GB)
Chip Selects
The MPC8548 memory controller functions as a chip select (CS) generator to access on-
board memory devices. In order to select one device over another, the following chip
selects have been established.
Table 4-3: Device Chip Selects
Pin:
Signal:
0
1
2
3
4
5
6
7
Boot bank 1
Soldered flash boot bank 1 (default)
Soldered flash boot bank 2
Socketed flash (optional)
KSL CPLD registers
NAND flash
Soldered NOR flash boot banks 3 and 4
LPC interface
1. Boot bank can be either socketed flash, flash 1, or flash 2;
4-5
10009109-01
ATCA-9305 User’s Manual
Management Complex: MPC8548 Processor
Reset Diagram
Figure 4-3: MPC8548 Reset Diagram
3_3V_MP
33MHz
PQ_HRESET*
PQ_SRESET*
PQ_TRST*
MPC8548
Manageement
Processor
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
IPMP
CPLD
1_0V_PWRGD
RESET_INDICATION*
Reset to IPMC
PQ_CORE_PWRGD*
P1_CORE_PWRGD*
P2_CORE_PWRGD*
I2C1
I2C2
PWRGD_OK
NOR
Flash
4M
FLASH_RST*
NAND_RST*
x 16
3_3V_MP
Front
Panel
Reset
3_3V
NAND
Voltage
Monitor
Delay
3_3V_MP
IPMC Reset
NAND_WARM_RST*
Flash
1GB
x 16
POR_RST*
Voltage
Monitor
Delay
PQ_DDR_RST*
KSL
CPLD
PQ DDR2
SOODIMM
Module
BOOT_REDIR
BOOT_SEL0
BOOT_SEL1
I2C IO
Port
TSEC1_RST*
Ethernet Port
BCM5461S
L_PAYLOAD_RST*
3_3V_MP
TSEC2_RST*
FP1_RST*
BC_RST*
Ethernet Port
BCM5461S
Hot Swap
Switch
E_HANDLE
Ethernet Port
BCM5461S
IPMC
48A_OK
48B_OK
Ethernet Port
BCM5482
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ATCA-9305 User’s Manual
10009109-01
Management Complex: Memory
MEMORY
The memory devices in the management complex consist of:
• 1 GB DDR2 SDRAM
• 512 KB socketed flash
• 8 MB soldered NOR flash (two redundant banks of 4 MB each)
• 1 GB soldered NAND flash
• 512 Mb or 64 MB soldered NOR flash
SDRAM
This is a specialized, socketed, 200-pin, small outline, clocked, dual in- line, memory mod-
ule (SO-CDIMM). It provides Error-correcting Code (ECC) on the SDRAM memory bus oper-
ating at 200 MHz. The MPC8548 detects all double-bit errors, multi-bit errors within a
nibble and corrects all single-bit errors.
The 128M X 72 DDR2 SDRAM is a high-density, un-buffered SO-CDIMM. This module con-
sists of nine 128x8-bit with eight banks DDR2 SDRAMs, a zero delay phase-lock loop (PLL)
clock, and a 2 KB serial presence detect (SPD) EEPROM. The SDRAM starts at physical
address 0000,0000
.
16
Flash
There are several flash devices on the local bus interfacing the CPLD and MPC8548 proces-
sor. The four soldered flash banks are labeled 1 through 4:
used in the boot redirection scheme, see “Boot Device Redirection (BDR).”
• Banks 3 and 4 are physically one device, but appear in the software as two banks of 32
512 KB x 8 (optional)
The 512 KB of 32-pin PLCC socketed flash starts at physical address FC80,0000 and is used
16
for Engineering code. The StrataFlash (P33) features high-performance fast asynchronous
access times, low power, and flexible security options.
4M x 16
The two 4 MB soldered flash devices are used for MPC8548 boot code. This redundant bank
configuration allows booting from either bank in case of corruption in one bank. See “Boot
Device Redirection (BDR)” on page 7-41. The SST NOR flash devices are organized as 4Mx8
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ATCA-9305 User’s Manual
Management Complex: PCI
in a dual-bank architecture for concurrent read/write operation with hardware and software
data protection schemes. These devices start at physical addresses F000,0000 (boot bank
16
1) and F040,0000 (boot bank 2).
16
1 GB x 16
The ATCA-9305 uses 1 GB of M-Systems DiskOnChip (mDOC H3) NAND flash starting at
physical address FC00,0000 for non-volatile RAM storage and True Flash File System
16
(TFFS). This memory incorporates an embedded flash controller and memory, and includes
hardware protection and security-enabling features, an enhanced programmable boot
block enabling eXecution In Place (XIP) functionality using 16-bit access, user-controlled
One Time Programmable (OTP) partitions, and 6-bit Error Detection Code/Error Correction
Code (EDC/ECC).
64 MB x 16
The 64 MB soldered NOR flash starts at physical address F400,0000 (bank 3) The 64-Mbit
16
.
P33 device provides CN5860 code storage and non-volatile memory.
PCI
The MPC8548 performs all the functions of a PCI host and monarch, and handles all arbitra-
tion and enumeration functions. PCI starts at physical address 8000,0000
.
16
The PCI bus connects to both Cavium processors, the MPC8548 processor and the Broad-
and perform 64-bit transactions in conventional PCI mode except for the Broadcom switch.
The switch has a 32-bit PCI bus.
The MPC8548 stores the Cavium CN5860 operating system and monitor code in local
memory and then uses the boot over PCI functionality to bring up the CN5860 processor
complexes.
Table 4-4: PCI Device Interrupts and ID Assignments
PCI Device:
Interrupt:
IRQ6
IDSEL:
Cavium processor 1
Cavium processor 2
Ethernet switch
MPC8548
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
IRQ5
IRQ4
—
PCI Express
The four lane PCIe routes between the MPC8548 and the optional rear transition module
(zone 3 connector). PCIe starts at physical address E000,0000
.
16
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Management Complex: I2C Interface
I2C INTERFACE
2
The I C interface consists of the MPC8548 initialization EEPROM, user (storage) NVRAM,
SO-CDIMM, and the Real-time Clock (RTC). The two Atmel two-wire serial EEPROMs on the
2
I C interface consist of the Serial Clock (SCL) input and the Serial Data (SDA) bidirectional
lines.
Table 4-5: I2C Device Addresses
2
I C Device:
Address:
0xA0
MPC8548 Initialization (EEPROM-2)
User NVRAM (EEPROM-1)
DDR2 SDRAM (SO-CDIMM)
M41T00 RTC
0xA2
0xA4
0xD0
The two EEPROMs store non-volatile information such as board, monitor, and operating sys-
tem configurations as well as customer specific items.
Table 4-6: MPC8548 NVRAM Memory Map
Address Offset
(hex):
Window
Size (bytes)
16
EEPROM:
EEPROM-1
0xA2
(write
protected)
Description:
0x1FF0-0x1FFF
0x1FE0-0x1FEF
0x1EE0-0x1FDF
0x0000-x1EDF
0x0900-0x1FFF
0x0800-0x08FF
0x07F0-0x07FF
0x0000-0x07EF
Boot verify secondary area (monitor)
Boot verify primary area (monitor)
Operating system parameters (monitor)
User defined
16
256
7903
5887
256
EEPROM-2
0xA0
(write
Emerson reserved area
Miscellaneous
Power-on Self-test (POST)
User defined
16
protected)
2032
Note: Both EEPROMs are write-protected.
MANAGEMENT PROCESSOR HEADER AND SERIAL PORT
JTAG/COP Interface (optional)
The management complex uses header P2 for debug purposes.
Table 4-7: Serial Debug Connector, P2
Pin:
Signal:
Description:
1
PQ_TDO
Test Data Output is the serial data output as well as test and
programming data.
2
no connect
—
4-9
10009109-01
ATCA-9305 User’s Manual
Management Complex: Management Processor Header and Serial
Pin:
Signal:
Description: (continued)
3
PQ_TDI
Test Data Input is the serial input pin for instructions as well as test and
programming data.
4
5
6
7
DEBUG_TRST*
no connect
Test Reset input signal resets the test access port.
—
PQ_JTAG_PWR
PQ_TCK_R
3.3 volt power
Test Clock Input is the clock input to the boundary scan test (BST)
circuitry.
8
9
no connect
PQ_TMS
—
Test Mode Select input pin provides the control signal to determine
the transitions of the TAP controller state machine.
10
11
no connect
—
DEBUG_SRESET*
Soft Reset input signal indicates that the MPC8548 must initiate a
System Reset interrupt.
12
13
ground
—
DEBUG_HRESET*
Hard Reset input signal indicates that a complete Power-on Reset must
be initiated by the MPC8548.
14
15
no connect
—
PQ_CKSTP_OUT*
Checkstop Out indicates the MPC8548 has detected a checkstop
condition and has ceased operation.
16
ground
—
Serial Debug Port
The console port for the management processor is accessible via the front panel mini-B USB
connector P7. The supported baud rates for these ports operate at 9600, 14400, 19200,
38400, 57600, and 115200 bps.
Table 4-8: Serial Debug Connector, P7
Pin:
Signal:
1
no connect
2
3
4
5
6
7
PQ_CONSOLE_RX_C
PQ_CONSOLE_TX_C
no connect
signal ground
chassis ground
chassis ground
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Section 5
Management Processor CPLD
The ATCA-9305 uses a Programmable Logic Device (PLD) to provide control logic for the
local bus. The PLD implements various registers for reset, hardware, and LPC bus communi-
cation between the processors.
MPC8548 PLD REGISTER SUMMARY
The PLD registers start at address FC40,0000 . As a rule, registers retain their values
16
isters followed by the register bit descriptions.
Table 5-1: PLD Register Summary
Address
Offset (hex): Mnemonic:
Register Name:
Product ID
See Page:
0x00
0x04
0x08
0x0C
0x10
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x70
0x74
0x78
0x80
PIDR
HVR
Hardware Version
PVR
PLD Version
PLLCR
HCR00
JSR
PLL Configuration
Hardware Configuration 0
Jumper Setting
LEDR
RER
LED
Reset Event
RCR1
RCR2
RCR3
RCR4
RCR5
RCRS1
RCRS2
SCR1
BDRR
MISC
LFTR1
LFTR2
RGSR
RGCR
RTMCR
CMUL1
CMUL2
JTAG
Reset Command #1
Reset Command #2
Reset Command #3
Reset Command #4
Reset Command #5
Reset Command Sticky #1
Reset Command Sticky #2
Scratch #11
—
Boot Device Redirection
Miscellaneous Control (SIO, I2C, Test Clock)
Low Frequency Timer 1
Low Frequency Timer 2
RTM GPIO State
RTM GPIO Control
RTM Control
Cavium 1 C_MUL Clock Divisor Control
Cavium 2 C_MUL Clock Divisor Control
Altera JTAG Chain Software Control
Cavium GPIO Control
CGCR
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Management Processor CPLD: MPC8548 PLD Register
Address
Offset (hex): Mnemonic:
Register Name:
(continued)
See Page:
0x84
0x88
0x8C
0xD0
0xD4
0xD8
0xDC
CGDO
CGDI
Cavium GPIO Data Out
Cavium GPIO Data In
IPMP/IPMC GPIO Control
IGCR
LPC1
Low Pin Count (LPC) Bus Control
LPC Data
LPCD
SIRQI1
SIRQI2
Serial IRQ Interrupt 1 [15:8]
Serial IRQ Interrupt 2 [7:0]
1. Scratch 1 (0x40) is a read/write register for storage only.
Product ID
This read-only register identifies the board as ATCA-9305, and is used for PLD coding.
Register 5-1: Product ID (0x00)
Bits:
Function:
Description:
7
CAVF1
Cavium Frequency 1
Cavium Frequency 0
Product ID
6
5
4
3
2
1
0
CAVF0
0
0
0
0
HC1
HC0
Hardware Configuration 1
Hardware Configuration 0
Hardware Version
This read-only register tracks hardware revisions.
Register 5-2: Hardware Version (0x04)
Bits:
Function:
Description:
7
0
6
5
4
3
2
1
0
0
0
0
HVN (3)
HVN (2)
HVN (1)
HVN (0)
Hardware Version Number is hard coded in the PLD and changes
with every major PCB artwork version.
Version starts at 0016
.
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Management Processor CPLD: MPC8548 PLD Register
PLD Version
This read-only register tracks PLD revisions.
Register 5-3: PLD Version (0x08)
Bits:
Function:
Description:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
This is hard coded in the PLD and changes with every released code
change. Version starts at 0016
.
PLL Reset Configuration
Write to this register to reconfigure the SYSCLK to CCB clock ratio and the CCB to CORE
clock ratio using valid values from the MPC8548E PowerQUICC™ III Integrated Processor Family
Reference Manual. The changes take affect when the processor is reset (for example, the
software hard reset command or watchdog timer expires). Default values are restored
when the board is power-cycled, front panel reset is pressed, or receives a PCI reset that was
not the result of the MPC8548 software initiating a PCI RSTOUT command.
Register 5-4: PLL Reset Configuration (0x0C)
Bits:
Function:
Description:
7
reserved
6
5
4
3
2
1
0
CCCB2
CCB2 to CORE clock ratio
CCCB1
CCB1 to CORE clock ratio
CCCB0
CCB0 to CORE clock ratio
CCBSYS3
CCBSYS2
CCBSYS1
CCBSYS0
SYSCLOCK3 to CCB clock ratio
SYSCLOCK2 to CCB clock ratio
SYSCLOCK1 to CCB clock ratio
SYSCLOCK0 to CCB clock ratio
Hardware Configuration 0
The read-only HCR0 allows the MPC8548 monitor software to easily determine specific
hardware configurations, such as the processor clock and MPC8548 DDR memory.
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Management Processor CPLD: MPC8548 PLD Register
Register 5-5: Hardware Configuration 0 (0x10)
Bits:
Function:
0
Description:
7
6
5
4
3
2
1
0
P33P
P33 (StrataFlash) is Present
Clear the Reset Indication to the IPMC controller
Cavium Frequency 1
RST_IND_CLR
CAVF1
CAVF0
Cavium Frequency 0
PQCF1
PQCF0
PQDDRF
MPC8548 Core Frequency 1
MPC8548 Core Frequency 0
MPC8548 DDR SDRAM Fast
Jumper Settings
These read-only bits may be read by software to determine the current jumper settings. See
the jumper descriptions on page 2-8.
Register 5-6: Jumper Settings (0x18)
Bits:
Function:
Description:
7
0
6
5
4
0
0
SJ
Cavium Boot Flash Jumper
0
1
Installed, Cavium processors boot from soldered flash
Not installed, Cavium processors boot from socket
3
2
1
BOOT
Boot PCI Jumper
0
1
Installed, boot from flash (socket or soldered per bit 4)
Not installed, boot over PCI from the MPC8548
REDIR
IG ROM
Boot Redirect Jumper
0
1
Installed, disables boot redirection
Not installed, enables boot redirection
Ignore SROM
0
1
Not installed, SROM is used for initialization (default)
Installed, disables SROM, uses default values in monitor
code
0
BT SKT
Boot from Socket
0
Not installed, enables MPC8548 to boot from soldered
flash (default)
Installed, enables MPC8548 to boot from socketed flash
1
LED
Writing a one to an LED bit lights that LED. During monitor power-up, the debug LEDs are
used to display the software progress.
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Management Processor CPLD: MPC8548 PLD Register
Register 5-7: LED (0x1C)
Bits:
Function:
Description:
7
PQRED
MPC8548 red LED
Lit on power-up and turned off when the monitor finishes boot
up and Power-on Self Testing (POST)
6
5
4
3
2
1
0
PQGREEN
MPC8548 green LED
Ethernet Switch LED Clock
Ethernet Switch LED Data
LED CR22
SWLEDCLK
SWLEDDAT
DEBUGLED3
DEBUGLED2
DEBUGLED1
DEBUGLED0
LED CR21
LED CR19
LED CR18
Reset Event
This read-only register contains the bit corresponding to the most recent event which
caused a reset. When power is first applied, the FP_PSH_BUTTN reset event is not latched
into the Reset Event register, this is the Power-on Reset (POR) event. Front panel reset
events which occur after power-up will be latched.
Note: At power-up, the FRST_PWR_UP defaults to 1.
Register 5-8: Reset Event (0x20)
Bits:
7
6
Function:
RTMPB
SHR
Description:
RTM push button
Software Hard Reset Set to 1 when the last reset was caused
by a write to the Reset Command register
5
4
CPUHRR
COPSR
CPU Hard Reset Request
Set to 1 when a COP header or software-issued Soft Reset
(SRESET) has occurred
3
2
1
COPHR
PAYR
SBR
Set to 1 when a COP header Hard Reset (HRESET) has occurred
Set to 1 when a Payload Reset from the IPMC has occurred
Software Board Reset
Set to 1 when the IPMC software issued the board (payload)
reset
0
FPPB
Front Panel Push Button (FP_PSH_BUTTN, POR_RST)
Reset Command 1
The write-only Reset Command 1 register forces one of several types of resets, as shown
below. A reset sequence is first initiated by writing a one to a single valid bit, then the PLD
performs that particular reset, and the bit is automatically cleared.
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Management Processor CPLD: MPC8548 PLD Register
Register 5-9: Reset Command 1 (0x24)
Bits:
Function:
WBR
Description:
Reset the Whole Board
7
6
5
4
3
2
1
0
PQCR
Reset the MPC8548 Complex
Reset the Cavium CN5860 1 Complex
Reset the Cavium CN5860 2 Complex
Reset the switch BCM5680x Complex
Reset the I2C on the MPC8548
Reset the (optional) RTM
CAV1CR
CAV2CR
SWICR
I2C R
RTMR
reserved
Reset Command 2
The write-only Reset Command 2 register forces one of several types of MPC8548 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-10: Reset Command 2 (0x28)
Bits:
Function:
Description:
7
PQHR
MPC8548 Hardware Reset
MPC8548 Software Reset
MPC8548 DDR SDRAM Reset
MPC8548 Flash reset
6
5
4
3
2
1
0
PQSR
PQDR
PQF
NANDR
NANDWR
reserved
reserved
MPC8548 NAND flash Reset
MPC8548 NAND flash Warm Reset
Reset Command 3
The write-only Reset Command 3 register forces one of several types of Cavium 1 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-11: Reset Command 3 (0x2C)
Bits:
Function:
Description:
7
CAV1R
Cavium 1 Reset
6
5
4
3
2
CAV1PR
CAV1DR
CAV1F
Cavium 1 PCI Reset
Cavium 1 DDR SDRAM Reset
Cavium 1 4 MB Flash (Cavium local bus) reset
Cavium 1 MIP1 reset
CAV1M1
CAV1M2
Cavium 1 MIP2 reset
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Management Processor CPLD: MPC8548 PLD Register
Bits:
1
0
Function:
reserved
reserved
Description: (continued)
Reset Command 4
The write-only Reset Command 4 register forces one of several types of Cavium 2 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-12: Reset Command 4 (0x30)
Bits:
Function:
Description:
7
CAV2R
Cavium 2 Reset
6
5
4
3
2
1
0
CAV2PR
CAV2DR
CAV2F
Cavium 2 PCI Reset
Cavium 2 DDR SDRAM Reset
Cavium 2 4 MB Flash (Cavium local bus) reset
Cavium 2 MIP3 reset
CAV2M3
CAV2M4
reserved
reserved
Cavium 2 MIP4 reset
Reset Command 5
The write-only Reset Command 5 register forces one of several types of BCM5680x Ethernet
switch resets, as shown below. A reset sequence is first initiated by writing a one to a single
valid bit, then the PLD performs that particular reset, and the bit is automatically cleared.
Register 5-13: Reset Command 5 (0x34)
Bits:
Function:
Description:
7
SWIR
Switch Reset
6
5
4
3
2
1
0
TSEC1R
TSEC2R
FPIR
TSEC1 Ethernet to front panel PHY Reset
TSEC2 Ethernet to switch PHY Reset
FPI Ethernet to front panel PHY Reset
Ethernet dual PHY to backplane Base Channel reset
BCR
reserved
reserved
reserved
Reset Command Sticky #1
The read/write Reset Command Sticky #1 register forces one of several types of the group-
complex resets, as shown below. A reset sequence is first initiated by writing a one to one or
more bits, then the PLD performs that particular reset. The bit will persist until cleared.
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Management Processor CPLD: MPC8548 PLD Register
Note: The board powers down and powers back up when the Cavium processors power is back up (bits 0 or 1 are
cleared).
Register 5-14: Reset Command Sticky #1 (0x38)
Bits:
7
Function:
CAV1C
Description:
Cavium 1 Complex reset
CAV2C
Cavium 2 Complex reset
6
SWIC
Switch Complex reset
5
CAV1CF
CAV2CF
NANDF
Cavium 1 Complex 4MB Flash reset
Cavium 2 Complex 4MB Flash reset
NAND Flash reset
4
3
2
CAV2RPD
CAV1RPD
Reset and power down the Cavium 2 core
Reset and power down the Cavium 1 core
1
0
Reset Command Sticky #2
The read/write Reset Command Sticky #2 register forces one of several types of the PHY
reset command, as shown below. A reset sequence is first initiated by writing a one to one
or more bits, then the PLD performs that particular reset. The bit will persist until cleared.
Register 5-15: Reset Command Sticky #2 (0x3C)
Bits:
Function:
Description:
7
TSEC1R
TSEC1 Ethernet to front panel PHY Reset
TSEC2 Ethernet to switch PHY Reset
FPI Ethernet from switch to front panel PHY Reset
Ethernet dual PHY to backplane Base Channel Reset
SPI to XAUI bridge #1 on Cavium 1
SPI to XAUI bridge #2 on Cavium 1
SPI to XAUI bridge #3 on Cavium 2
SPI to XAUI bridge #4 on Cavium 2
6
5
4
3
2
1
0
TSEC2R
FPIR
BCR
MIP1
MIP2
MIP3
MIP4
Boot Device Redirection
The read/write Boot Device Redirection register (BDRR) allows the user to determine which
of three boot devices the MPC8548 CPU is using as the boot device. Several bits also indi-
cate which device was set as the initial boot device. The Boot Redirected bit is set to a 1
when the current boot device does not match the initial default boot device. This indicates
to the user that the image in the default device was bad, the MPC8548 watch dog timer
expired, and the next device was tried. The boot device redirection order is determined by
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Management Processor CPLD: MPC8548 PLD Register
Register 5-16: Boot Device Redirection (0x50)
Bits:
Function:
SELFRS
Description:
Self Refresh Started
7
6
5
4
BOOTSEL1
reserved
BSJ
IPMC successful boot indication (BOARD_BOOTED)
Boot from Socket Jumper A shunt on J9 [1:2] selects the
3
2
1
0
NFBS
BDS
Nand Flash Busy Signal
Active boot device is socket
Active boot device is flash 2
Active boot device is flash 1
BDF1
BDF0
Miscellaneous Control
This register includes two bits for manually toggling the MPC8548 I C bus.
2
Register 5-17: Miscellaneous Control (0x54)
Bits:
Function:
Description:
7
P33WP
0
1
Write Protect disabled (default until the monitor boots)
Write Protect enabled
6
5
4
3
2
1
SROM1WP
SROM0WP
FLASH1WP
FLASH0WP
NANDWP
I2CSDA
0
1
Write Protect disabled
Write Protect enabled (default)
0
1
Write Protect disabled
Write Protect enabled (default)
0
1
Write Protect disabled (default until the monitor boots)
Write Protect enabled
0
1
Write Protect disabled (default until the monitor boots)
Write Protect enabled
0
1
Write Protect disabled
Write Protect enabled (default)
I2C Data line
0
1
Drive a 0 onto the I2C SDA line
Drive a 1 onto the I2C SDA line
0
I2CSCL
I2C Clock line
0
1
Drive a 0 onto the I2C SCL line
Drive a 1 onto the I2C SCL line
Low Frequency Timer 1 and 2
Registers LFTR1 (0x58) and LFTR2 (0x5C) are timers. They determine how many 50 μs inter-
vals you want before the next interrupt on Cavium GPIO5.
Note: Unless the frequency is set to 0, there is always one 50 μs interval. This is the reason for the register setting
being 1 less than an even hundred, for example 199 rather than 200.
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Management Processor CPLD: MPC8548 PLD Register
Table 5-2: Low Frequency Timer Settings
Frequency:
0
Set Register:
Off
Comments:
Never interrupts
1 Hz
19999 (0x4E1F)
1999 (0x7CF)
199 (0xC7)
19 (0x13)
1
These frequencies require the use of both registers
10 Hz
100 Hz
1 KHz
10 KHz
This equals two 50 μs time units (default)
RTM GPIO State
This read-only register reads the current state of the GPIO pins.
Register 5-18: RTM GPIO State (0x60)
Bits:
Function:
Description:
7
RTM_GPIO 7
6
5
4
3
2
1
0
RTM_GPIO 6
RTM_GPIO 5
RTM_GPIO 4
RTM_GPIO 3
RTM_GPIO 2
RTM_GPIO 1
RTM_GPIO 0
RTM GPIO Control
This register sets the state of the GPIO pins. These signals are implemented as open collec-
tor signals.
Register 5-19: RTM GPIO Control (0x64)
Bits:
Function:
Description:
7
RTM_GPIO 7
0
1
Causes the corresponding bit to be driven to 0
Tristates the signal; this will either be read by the RTM as a 1
6
5
4
3
2
1
0
RTM_GPIO 6
RTM_GPIO 5
RTM_GPIO 4
RTM_GPIO 3
RTM_GPIO 2
RTM_GPIO 1
RTM_GPIO 0
or can be driven by the RTM to any value
RTM Status
The RTM identification (ID) is determined by factory installed configuration resistors.
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Management Processor CPLD: MPC8548 PLD Register
Register 5-20: RTM Control (0x68)
Bits:
Function:
0
Description:
7
6
5
4
3
2
1
0
0
0
RTMP
RTMID3
RTMID2
RTMID1
RTMID0
RTM is Present
RTM Identification bits 3:0
0000 = Test RTM (factory only)
1000 = 20GbE I/O RTM
1100 = 18GbE and 2x10GbE I/O RTM
1010 = Storage RTM
Cavium 1 C_MUL Clock Divisor Control
Use the C_MUL1 register to reduce the speed of the Cavium CN5860 processor 1 core.
Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).
!
Register 5-21: Cavium 1 C_MULL Clock Divisor Control (0x70)
Bits:
Function:
Description:
7
6
CAVF
Cavium Frequency resistor set bit (read-only)
00 600
01 750
10 800
11 reserved
5
4
3
2
1
0
CMULOE
C_MUL Output Enable
P1CMUL4
P1CMUL3
P1CMUL2
P1CMUL1
P1CMUL0
These bits drive directly to the Cavium 1. The core clock speed
is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).
Cavium 2 C_MUL Clock Divisor Control
Use the C_MUL2 register to reduce the speed of the Cavium CN5860 processor 2 core.
Caution: Do not over-clock the Cavium frequency (bits 6:7 hard strapped).
!
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Management Processor CPLD: MPC8548 PLD Register
Register 5-22: Cavium 2 C_MULL Clock Divisor Control (0x74)
Bits:
Function:
Description:
7
CAVF1
Cavium 1 Frequency resistor set bit (read-only, see Register
6
5
4
3
2
1
0
CAVF0
Cavium 0 Frequency resistor set bit (read-only)
C_MUL Output Enable
CMULOE
P1CMUL4
P1CMUL3
P1CMUL2
P1CMUL1
P1CMUL0
These bits drive directly to the Cavium 2. The core clock speed
is the number multiplied by 50 MHz. For example, the 800 MHz
core is set to 16(0x10).
JTAG
This register allows for manual reprogramming of the PLDs on the board. Changes to this
register do not take effect until after a full board reset.
Register 5-23: JTAG (0x78)
Bits:
Function:
reserved
Description:
7
6
5
4
reserved
JTAGOEN
JTAGTCKSEL
JTAG Output Enable
JTAG Test Clock Select changes from header to PLD as the TCK
source
3
2
1
0
JTAGTCK
JTAGTMS
JTAGTDO
JTAGTDI
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Output
JTAG Test Data Input (read only)
Cavium GPIO Control
Each Cavium processor has three GPIO control bits connected to the PLD. This register
determines whether the PLD is driving or receiving on these lines. Setting a bit to 1 causes
the PLD to drive the corresponding line.
Register 5-24: Cavium GPIO Control (0x80)
Bits:
Function:
Description:
7
reserved
6
5
reserved
P2GPIO5OE
Processor 2 GPIO5 Output Enable (enabled is the default)
Output enable is set for the TIC timer output to the Cavium
4
P2GPIO4OE
Processor 2 GPIO4 Output Enable
This is an input from the Cavium to reset the MIP4
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Management Processor CPLD: MPC8548 PLD Register
Bits:
Function:
Description: (continued)
3
P2GPIO3OE
Processor 2 GPIO3 Output Enable
This is an input from the Cavium to reset the MIP3
2
1
0
P1GPIO5OE
P1GPIO4OE
P1GPIO3OE
Processor 1 GPIO5 Output Enable (enabled is the default)
Output enable is set for the TIC timer output to the Cavium
Processor 1 GPIO4 Output Enable
This is an input from the Cavium to reset the MIP2
Processor 1 GPIO3 Output Enable
This is an input from the Cavium to reset the MIP1
Cavium GPIO Data Out
This register is the data that will be driven on the GPIO line when the Output enable is set.
Register 5-25: Cavium GPIO Data Out (0x84)
Bits:
Function:
Description:
7
reserved
6
5
4
3
2
1
0
reserved
reserved
P2GPIO4
P2GPIO3
reserved
P1GPIO4
P1GPIO3
Set the value of the Cavium 2 GPIO bit 4
Set the value of the Cavium 2 GPIO bit 3
Set the value of the Cavium 1 GPIO bit 4
Set the value of the Cavium 1 GPIO bit 3
Cavium GPIO Data In
This register reads the value on the GPIO lines connected to each Cavium.
Register 5-26: Cavium GPIO Data In (0x88)
Bits:
Function:
Description:
7
reserved
6
5
4
3
2
1
0
reserved
reserved
P2GPIO4
P2GPIO3
reserved
P1GPIO4
P1GPIO3
Read the value of the Cavium 2 GPIO bit 4
Read the value of the Cavium 2 GPIO bit 3
Read the value of the Cavium 1 GPIO bit 4
Read the value of the Cavium 1 GPIO bit 3
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Management Processor CPLD: MPC8548 PLD Register
IPMP/IPMC GPIO Control
This register provides access (if required) to signals between the KSL CPLD and the IPMP, as
well as to signals between the KSL CPLD and the IPMC. The lower two bits can request
request the power down of a Cavium core from the sticky reset register.
Register 5-27: IPMP/IPMC GPIO Control (0x8C)
Bits:
Function:
IPMC2KSL4
IPMC2KSL3
IPMC2KSL2
IPMC2KSL1
IPMP2KSL4
IPMP2KSL3
IPMP2KSL2
Description:
Input only
7
6
5
4
3
2
1
Output only
Output only
Power-down signal for Cavium 2 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
0
IPMP2KSL1
Power-down signal for Cavium 1 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
LPC Bus Control
This is the control register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU.
Register 5-28: LPC Bus (0xD0)
Bits:
Function:
Description:
7
6
5
4
3
2
1
0
LPCIE
LPCS
LPC Interrupt Enable
LPC State (internal use only)
LPCIOE
SYNCE
SYNCT
LPC I/O Error
SYNC Error
SYNC Time-out
LPC Data
This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.
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Management Processor CPLD: MPC8548 PLD Register
Register 5-29: LPC Data (0xD4)
Bits:
Function:
Description:
7:0
-
LPC Data
Serial IRQ Interrupt 1
This is interrupt register1 for the LPC bus.
Register 5-30: Serial IRQ Interrupts 1 (0xD8)
Bits:
Function:
Description:
7:0
-
Interrupts
Serial IRQ Interrupt 2
This is interrupt register2 for the LPC bus.
Register 5-31: Serial IRQ Interrupts 2 (0xDC)
Bits:
Function:
Description:
7:0
-
Interrupts
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Section 6
Ethernet Interface
The ATCA-9305 supports multiple Ethernet interfaces. This chapter describes the Broadcom
BCM56802 switch, PHYS BCM5482 and BCM5461S, Ethernet address, LEDs and connec-
tors.
BROADCOM BCM56802 SWITCH
The BCM56802 is a 16-port, 10-GbE multi-layer switch based on the StrataXGS® architec-
ture. The switch operates at 66 MHz with a 32-bit PCI bus for processor communication.
SERDES functionality includes 10-Gbps XAUI and 1-Gbps SGMII PHY interfaces.
One 10/100/1000BASE-T Ethernet (SGMII) port is routed to a front panel RJ45 connector
Two XAUI ports process packets to and from each CN5860 processor. Six 10 GbE XAUI ports
ments.
Note: Proprietary information on the Broadcom switch is not available in this user’s manual. Refer to their web site
for available documentation.
ETHERNET SWITCHING
The base interface Ethernet ports are provided by the Broadcom BCM56802 16-port, 10
gigabit (GbE) switch. The SerDes functionality includes 10-Gbps XAUI and 1-Gbps SGMII
PHY interfaces. The integrated SerDes complies with the CX-4 standard and PICMG 3.1
standard. The Fabric interface is compliant with PICMG 3.1 Revision 1.0, specifically link
option 9 (one 10GBASE-BX4). Switch connectivity consists of the following devices:
• Two 10GbE ports to CN5860 processor complex 1
• Two 10GbE ports to CN5860 processor complex 2
• One GbE port to the front panel (RJ45 connector)
• One GbE port to the MPC8548 management processor complex, then out the front
panel (RJ45 connector)
• Two 10 GbE ports to the fabric interface
• Two 1 GbE ports to the base interface
• Two or six 10 GbE ports to the Zone 3 connector (optional RTM)
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Ethernet Interface: Ethernet Switching
Figure 6-1: Ethernet Switching Interface Diagram
RJ45
RJ45
BCM5461S
BCM5461S
MPC8548
Management
Processor
BCM5461S
3
4
SGMII
SGMII
Stratix II GX
#1
Stratix II GX
#3
SPI-0
6 XAUI
5 XAUI
SPI-0
SPI-1
XAUI 13
XAUI 14
Cavium
Octeon
CN5860
Cavium
Octeon
CN5860
BCM56802
XAUI 10 Gb
Switch Ports
Processor 1 SPI-1
Processor 2
Stratix II GX
#2
Stratix II GX
#4
SGMII
2
SGMII
1
XAUI
XAUI
8
7
11-12 15 -18
BCM5482
Base
10G Fabric
J23
To Optional RTM
J31
J30
Note: The phyiscal port numbering starts at 1, as indicated in the figure. However, the software port numbering
starts at 0. Therefore, to issue a command to a port, you must subtract 1 from the port numbers shown in the
figure.
Ethernet Transceivers
The BCM5461S is a 10/100/1000BASE-T GbE Ethernet transceiver using the SGMII interface.
The BCM5482 consists of two complete 10/100/1000BASE-T GbE transceivers supporting
both voice and data simultaneously.
Ethernet Switch Ports
Table 6-1: Ethernet Switch Ports
Port:
1
2
Interface:
SGMII 1 GB
SGMII 1 GB
Connection:
PHY to backplane BASE
PHY to backplane BASE
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Ethernet Interface: MPC8548 Management Processor Ethernet
Port:
3
Interface:
SGMII 1 GB
SGMII 1 GB
XAUI 10 GB
XAUI 10 GB
XAUI 10 GB
XAUI 10 GB
—
Connection: (continued)
Switch PHY to front panel RJ45 connector
Management processor PHYs to front panel RJ45 connector
Stratix II GX bridge 2
4
5
6
Stratix II GX bridge 1
7
Back plane Fabric
8
Back plane Fabric
9
not used
10
11
12
13
14
15
16
17
18
—
not used
XAUI 10 GB
BCM56802 to J30 to optional RTM
XAUI 10 GB
XAUI 10 GB
XAUI 10 GB
Stratix II GX bridge 3
Stratix II GX bridge 4
BCM56802 to J31 to optional RTM
VLAN Setup
command.
Table 6-2: VLAN Configuration
VLAN:
Ports:
1
2
3
4
5
1, 3, 4
6, 7
8, 13
5, 11
12, 14
MPC8548 MANAGEMENT PROCESSOR ETHERNET ADDRESS
The Ethernet address for your board is a unique identifier on a network. The address con-
sists of 48 bits (MAC [47:0]) divided into two equal parts. The upper 24 bits define a unique
identifier that has been assigned to Emerson Network Power, Embedded Computing by
IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.
The Ethernet address for the ATCA-9305 is a binary number referenced as 12 hexadecimal
digits separated into pairs, with each pair representing eight bits. The address assigned to
the ATCA-9305 has the following form:
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Ethernet Interface: MPC8548 Management Processor Ethernet
00 80 F9 xx yy zz
00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address consist of the
port (one byte), 0x97(port 1) or 0x98 (port 2), followed by the serial number (two byte
hexadecimal). The ATCA-9305 has been assigned the Ethernet address range
Table 6-3: Ethernet Port Address
Offset:
Byte 5
Byte 4
Byte 3
MAC:
15:0
Description:
LSB of (serial number in hex)
MSB of (serial number in hex)
Ethernet Identifier (hex):
—
—
23:16
47:24
Port 1 (TSEC_1)
Port 2 (TSEC_2)
0x97
0x98
Byte 2
Byte 1
Byte 0
Assigned to Emerson by IEEE
0xF9
0x80
0x00
The last two bytes, MAC[15:0], correspond to the following formula: n —1000, where n is
the unique serial number assigned to each board. So if an ATCA-9305 serial number is 1032,
the calculated value is 32 (20 ), and the default Ethernet port addresses are:
16
• TSEC_1 MAC address is: 0x00 0x80 0xF9 0x97 0x00 0x20
• TSEC_2 MAC address is: 0x00 0x80 0xF9 0x98 0x00 0x20
Front Panel Ethernet Ports
One MPC8548 PHY (TSEC1) routes to front panel RJ45 connector, P1. The BCM56802 switch
PHY (port 3) routes to front panel RJ45 connector, P3. The Ethernet port LEDs (green or yel-
Table 6-4: Front Panel Ethernet Ports
Pin:
P1 Signal:
P3 Signal:
1
TSEC1_TRD0_P
FP1_TRD0_P
2
TSEC1_TRD0_N
FP1_TRD0_N
3
TSEC1_TRD1_P
FP1_TRD1_P
4
TSEC1_TRD2_P
FP1_TRD2_P
5
TSEC1_TRD2_N
FP1_TRD2_N
6
TSE1C_TRD1_N
FP1_TRD1_N
7
TSEC1_TRD3_P
FP1_TRD3_P
8
TSEC1_TRD3_N
FP1_TRD3_N
9
TSEC1_ACTIVITY (green LED 1)
2_5V (yellow LED 1)
TSEC1_LINKSPD1 (green LED 2)
FP1_ACTIVITY (green LED1)
2_5V (yellow LED 1)
FP1_LINKSPD1 (green LED 2)
10
11
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Ethernet Interface: MPC8548 Management Processor Ethernet
Pin:
12
P1 Signal:
TSEC1_LINKSPD2 (yellow LED 2)
TSEC1_CHSGND
P3 Signal: (continued)
FP1_LINKSPD2 (yellow LED 2)
FP1_CHSGND
13
14
TSEC1_CHSGND
FP1_CHSGND
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ATCA-9305 User’s Manual
Section 7
System Management
The ATCA-9305 provides an intelligent hardware management system, as defined in the
AdvancedTCA Base Specification (PICMG® 3.0). This system implements an Intelligent Plat-
form Management Controller (IPMC) based on the BMR-H8S-AMCc® reference design from
2
Pigeon Point Systems. It also has an inter-integrated circuit (I C) controller to support an
Intelligent Platform Management Bus (IPMB) that routes to the ATCA backplane.
The IPMC implements all the standard Intelligent Platform Management Interface (IPMI)
commands and provides hardware interfaces for other system management features such
as Hot Swap control, LED control, power negotiation, and temperature and voltage moni-
toring. The IPMC also supports an EIA-232 interface for serial communications via the Serial
Interface Protocol Lite (SIPL) IPMI commands.
IPMC OVERVIEW
The basic features for the IPMC implementation include:
• Conformance with AdvancedTCA Base Specification (PICMG® 3.0)
• Geographical addressing according to PICMG® 3.0
• Ability to read and write Field Replaceable Unit (FRU) data
• Ability to reset IPMC from IPMB
• Ability to read inlet and outlet airflow temperature sensors
• Ability to read payload voltage/current levels
• Ability to send event messages to a specified receiver
• All sensors generate assertion and/or de-assertion event messages
• Support for fault tolerant HPM.1 firmware upgrades
• Support for field updates of firmware via IPMB-0 or the payload interface
• Redundant boot bank capability
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System Management: IPMI Messaging
Figure 7-1: IPMC Connections Block Diagram
UART
& LPC
IPMI MESSAGING
All IPMI messages contain a Network Function Code field, which defines the category for a
particular command. Each category has two codes assigned to it–one for requests and one
for responses. The code for a request has the least significant bit of the field set to zero,
while the code for a response has the least significant bit of the field set to one. Table 7-1 lists
the network function codes (as defined in the IPMI specification) used by the IPMC.
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System Management: IPMI Messaging
Table 7-1: Network Function Codes
Hex Code
Value(s):
Name:
Type:
Name:
00, 01
Chassis
chassis device
00 = command/request, 01 = response:
requests/responses
common chassis control and status functions
02, 03
Bridge
bridge
02 = request, 03 = response:
requests/responses
message contains data for bridging to the next
bus. Typically, the data is another message,
which also may be a bridging message. This
function is only present on bridge nodes.
04, 05
06, 07
08, 09
0A, 0B
Sensor/
Event
sensor and event
requests/responses
04 = command/request, 05 = response:
for configuration and transmission of Event
Messages and system Sensors. This function
may be present on any node.
App
application
requests/responses
06 = command/request, 07 = response:
message is implementation-specific for a
particular device, as defined by the IPMI
specification
Firmware
Storage
firmware transfer
requests/responses
08 = command/request, 09 = response:
firmware transfer messages match the format
of application messages, as determined by the
particular device
non-volatile
storage
requests/responses
0A = command/request, 0B = response:
may be present on any node that provides
nonvolatile storage and retrieval services
0C-2F
30-3F
reserved
OEM
–
–
reserved: 30 network functions (15 pairs)
30 = command/request, 3F = response:
vendor specific: 16 network functions (8 pairs).
The vendor defines functional semantics for
cmd and data fields. The cmd field must hold the
same value in requests and responses for a
given operation to support IPMI message
handling and transport mechanisms. The
controller’s Manufacturer ID value identifies the
vendor or group.
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System Management: IPMI Messaging
IPMI Completion Codes
All IPMI response messages contain a hexadecimal Completion Code field that indicates the
status of the operation.
Table 7-2: Completion Codes
Code:
Description:
Generic Completion Codes 00, C0-FF
00
C0
Command completed normally
Node busy–command could not be processed because command-processing resources
are temporarily unavailable
C1
C2
C3
C4
Invalid command–indicates an unrecognized or unsupported command
Command invalid for given LUN
Time-out while processing command, response unavailable
Out of space–command could not be completed because of a lack of storage space
required to execute the given command operation
C5
C6
C7
C8
C9
Reservation canceled or invalid Reservation ID
Request data truncated
Request data length invalid
Request data field length limit exceeded
Parameter out of range–one or more parameters in the data field of the Request are out
of range. This is different from Invalid data field code (CC) because it indicates that the
erroneous field(s) has a contiguous range of possible values.
CA
CB
CC
CD
CE
CF
Cannot return number of requested data bytes
Requested sensor, data, or record not present
Invalid data field in Request
Command illegal for specified sensor or record type
Command response could not be provided
Cannot execute duplicated request–for devices that cannot return the response returned
for the original instance of the request. These devices should provide separate commands
that allow the completion status of the original request to be determined. An Event
Receiver does not use this completion code, but returns the 00 completion code in the
response to (valid) duplicated requests.
D0
D1
D2
Command response could not be provided, SDR Repository in update mode
Command response could not be provided, device in firmware update mode
Command response could not be provided, Baseboard Management Controller (BMC)
initialization or initialization agent in progress
D3
Destination unavailable–cannot deliver request to selected destination. (This code can be
returned if a request message is targeted to SMS, but receive message queue reception is
disabled for the particular channel.)
D4
D5
FF
Cannot execute command, insufficient privilege level
Cannot execute command, parameter(s) not supported in present state
Unspecified error
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System Management: IPMB Protocol
Code:
Description:
(continued)
Device-Specific (OEM) Codes 01-7E
01-7E
Device specific (OEM) completion codes–command-specific codes (also specific for a
particular device and version). Interpretation of these codes requires prior knowledge of
the device command set.
Command-Specific Codes 80-BE
80-BE Standard command-specific codes–reserved for command-specific completion codes
(described in this chapter)
IPMB PROTOCOL
The IPMB message protocol is designed to be robust and support many different physical
interfaces. The IPMC supports messages over the IPMB interface. Messages are defined as
either a request or a response, as indicated by the least significant bit in the Network Func-
tion Code of the message.
Table 7-3: Format for IPMI Request Message
Byte:
Bits:
7
6
5
4
3
2
1
0
1
rsSA
Network Function (netFn)
2
rsLUN
3
Checksum
rqSA
4
5
rqSeq
rqLUN
6
Command
Data
7:N
N+1
Checksum
• The first byte contains the responder’s Slave Address, rsSA.
• The second byte contains the Network Function Code, netFn, and the responder’s
Logical Unit Number, rsLUN.
• The third byte contains the two’s-complement checksum for the first two bytes.
• The fourth byte contains the requester’s Slave Address, rqSA.
• The fifth byte contains the requester’s Sequence Number, rqSeq, and requester’s Logical
Unit Number, rqLUN. The Sequence number may be used to associate a specific response
to a specific request.
• The sixth byte contains the Command Number.
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System Management: SIPL Protocol
• The seventh byte and beyond contain parameters for specific commands (if required).
• The final byte is the two’s-complement checksum of all of the message data after the
first checksum.
difference is that the seventh byte contains the Completion Code, and the eighth byte and
beyond hold data received from the controller (rather than data to send to the controller).
Also, the Slave Address and Logical Unit Number for the requester and responder are
swapped.
Table 7-4: Format for IPMI Response Message
Byte:
Bits:
7
6
5
4
3
2
1
0
1
rqSA
Network Function (netFn)
2
rqLUN
3
Checksum
rsSA
4
5
rsSeq
rsLUN
6
Command
Completion Code
Data
7
8:N
N+1
Checksum
SIPL PROTOCOL
The IPMC supports the Serial Interface Protocol Lite (SIPL) protocol. It supports raw IPMI
messages in SIPL and handles these messages the same way as it handles IPMI messages
from the IPMB-0 bus, except that the replies route to either the payload or serial debug
interface. Messages are entered as case-insensitive hex-ASCII pairs, separated optionally by
a space, as shown in the following examples:
[18 00 22]<newline>
[180022]<newline>
The IPMC does not, however, support SIPL ASCII text commands, as defined by the IPMI
specification.
The IPMC does support Pigeon Point Systems extension commands, implemented as OEM
IPMI commands. These commands use Network Function Codes 2E/2F (hex), and the mes-
sage body is transferred similarly to raw IPMI messages, as described previously.
The following figures show an example of an extension command request and response,
respectively.
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System Management: Message Bridging
Figure 7-2: Extension Command Request Example
[B8 00 01 0A 40 00 12]
Data
Pigeon Point IANA
Command Code
rqSeq (0016) / Bridge (002)
NetFn Code (2E16) / LUN (002)
Figure 7-3: Extension Command Response Example
[BC 00 01 00 0A 40 00 34]
Data
Pigeon Point IANA
Completion Code
Command Code
rqSeq (0016) / Bridge (002)
NetFn Code (2F16) / LUN (002)
MESSAGE BRIDGING
The Message Bridging facility is responsible for bridging messages between various inter-
faces of the ATCA-9305 IPMI. The message bridging is implemented via the standard Send
Message command.
The ATCA-9305 IPMC also supports message bridging between the Payload Interface and
IPMB-0, which allows the payload to send custom messages to and receive them from other
shelf entities, such as the shelf manager. Message bridging is implemented using the
Send/Get Message commands and also via LUN 10 of the ATCA-9305 IPMC.
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System Management: Message Bridging
The following example illustrates how the Send/Get Message and Get Address Info com-
mands can be used by the payload software to get the physical location of the board in the
shelf:
1
2
3
The payload software sends the Get Address Info command to the BMR-H8S-AMCc,
requesting address information for FRU device 0. Using the SIPL protocol:
[B0 xx 01 00]
The BMR-H8S-AMCc returns its IPMB address in the Get Address Info reply. In this example,
72 is the IPMB-0 address of the IPMC.
16
{B4 00 01 00 00 FF 72 FF 00 01 07]
The payload software composes a Get Address Info command requesting the responder to
provide its addressing information for FRU device 0. The request is composed in the IPMB
format. The responder address is set to 20 (for the shelf manager). The requester address
16
is set to the value obtained in the previous step.
{20 B0 30 72 00 01 00 8D]
4
5
The payload software forwards the command composed in the previous step to the shelf
manager using the Send Message command. The Send/Get Message in SIPL format is:
[18 xx 34 40 20 B0 30 72 00 01 00 8D]
The BMR-H8S-AMCc firmware sends the Get Address Info request to the shelf manager,
waits for a reply to this request, and sends this reply to the payload software in the Send/Get
Message response.
[1C 00 34 00 72 B4 DA 20 00 01 00 00 41 82 FF 00 FF 00 1E]
6
The payload software extracts the Get Address info reply from the Send/Get Message
response and retrieves the physical address of the board from it.
The second message bridging implementation, bridging via LUN 10, allows the payload to
receive responses to requests sent to IPMB-0 via the Send Message command with request
tracking disabled, as well as receive requests from IPMB-0. To provide this functionality, the
ATCA-9305 IPMC places all messages coming to LUN 10 from IPMB-0 in a dedicated Receive
Message Queue, and those messages are processed by the payload instead of the IPMC
firmware. To read messages from the Receive Message Queue, the payload software uses
the standard Get Message command. The payload software is notified about messages
coming to LUN 10 via the Get Status command of the SIPL protocol and the payload notifi-
cation mechanism, or, if the LPC/KCS-based Payload Interface is used, using the KCS inter-
rupt. The Receive Message Queue of the ATCA-9305 IPMC is limited to 128 bytes, which is
sufficient for storing at least three IPMB messages, but may be not enough for a larger num-
ber of messages. Taking this into account, the payload software must read messages from
the queue as fast as possible, caching them on the on-carrier payload side for further han-
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System Management: Standard Commands
dling, if it is necessary. If the Receive Message Queue is full, the ATCA-9305 IPMC rejects all
requests coming to LUN 10 with the C0h (Node Busy) completion code and discards all
responses coming to this LUN.
STANDARD COMMANDS
The Intelligent Peripheral Management Controller (IPMC) supports standard IPMI com-
mands to query board information and to control the behavior of the board. These com-
mands provide a means to:
• identify the controller
• reset the controller
• return the controller’s self-test results
• read and write the controller’s SROMs
• read the temperature, voltage, and watchdog sensors
• get specific information, such as thresholds, for each sensor
• read and write the Field Replaceable Unit (FRU) data
• reserve and read the Sensor Data Record (SDR) repository
• configure event broadcasts
• bridge an IPMI request to the public IPMB and return the response
Table 7-5 lists the IPMI commands supported by the IPMC along with the hexadecimal values
for each command’s Network Function Code (netFn), Logical Unit Number (LUN), and Com-
mand Code (Cmd):
Table 7-5: IPMC IPMI Commands
Command:
netFn:
Chassis
LUN:
Cmd:
07
Set System Boot Options
Get System Boot Options
Set Event Receiver
01, 01
01, 01
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
Chassis
08
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
00
Get Event Receiver
01
Platform Event (Event Message)
Get Device SDR Information
Get Device SDR
02
20
21
Reserve Device SDR Repository
Get Sensor Reading Factors
Set Sensor Hysteresis
22
23
24
Get Sensor Hysteresis
25
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System Management: Standard Commands
Command:
(continued)
netFn:
LUN:
Cmd:
26
27
28
29
2A
2B
2D
2E
Set Sensor Thresholds
Get Sensor Thresholds
Set Sensor Event Enable
Get Sensor Event Enable
Rearm Sensor Events
Get Sensor Event Status
Get Sensor Reading
Set Sensor Type
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Sensor/Event
Application
Application
Application
Application
Application
Application
Application
Application
Application
Application
Storage
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
04, 05
06, 07
06, 07
06, 07
06, 07
06, 07
06, 07
06, 07
06, 07
06, 07
06, 07
0A, 0B
0A, 0B
0A, 0B
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
2C, 2D
Get Sensor Type
2F
Get Device ID
01
01
02
03
04
08
22
24
25
34
10
11
12
00
01
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Broadcast 'Get Device ID'
Cold Reset
Warm Reset
Get Self Test Results
Get Device GUID
Reset Watchdog Timer
Set Watchdog Timer
Get Watchdog Timer
Send Message
Get FRU Inventory Area Info
Read FRU Data
Storage
Write FRU Data
Storage
Get PICMG Properties
Get Address Info
PICMG
PICMG
FRU Control
PICMG
Get FRU LED Properties
Get LED Color Capabilities
Set FRU LED State
PICMG
PICMG
PICMG
Get FRU LED State
Set IPMB State
PICMG
PICMG
Set FRU Activation Policy
Get FRU Activation Policy
Set FRU Activation
Get Device Locator Record ID
Set Port State
PICMG
PICMG
PICMG
PICMG
PICMG
Get Port State
PICMG
Compute Power Properties
Set Power Level
PICMG
10
11
PICMG
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System Management: OEM Boot Options
Command:
Get Power Level
(continued)
netFn:
PICMG
PICMG
LUN:
2C, 2D
2C, 2D
Cmd:
12
Bused Resource
17
(Release, Query, Force, Bus Free)
The IPMC implements many standard IPMI commands. For example, software can use the
watchdog timer commands to monitor the system’s health. Normally, the software resets
the watchdog timer periodically to prevent it from expiring. The IPMI specification allows
for different actions such as reset, power off, and power cycle, to occur if the timer expires.
The watchdog’s ‘timer use’ fields can keep track of which software (Operating System, Sys-
tem Management, etc.) started the timer. Also, the time-out action and ‘timer use’ infor-
mation can be logged automatically to the System Event Log (SEL) when the time-out
request and response data. The IPMC also implements ATCA commands, see the ATCA Base
Specification (PICMG 3.0).
OEM BOOT OPTIONS
The Set System Boot Options and Get System Boot Options commands provide a means to
set/retrieve the boot options. The IPMI specification defines a set of standard boot option
parameters. In addition, the specification includes a range of numbers (96-127) for OEM
extensions. Emerson utilizes this area for OEM function extensions, such as boot bank selec-
tion and POST configuration. The following table describes these extensions:
Table 7-6: Emerson Boot Option Parameters
Parameter:
#
Parameter Data:
Boot Bank
(non-volatile)
96
data 1 — Set Selector. This is the processor ID for which the
boot option is to be set.
data 2 — Boot Bank Selector. This parameter is used to
indicate the boot bank from which the payload will boot.
00h = Primary (i.e., default) Boot Bank is selected.
01h = Secondary Boot Bank is selected.
02h-FFh = unused
POST Type
(non-volatile)
97
data 1 — Set Selector. This is the processor ID for which the
boot option is to be set.
data 2 — PSOT Type Selector. This parameter is used to
specify the POST type that the payload boot firmware will
execute.
00h = Short POST
01h = Long POST
02h-FFh = unused
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System Management: IPMC Watchdog Timer Commands
IPMC WATCHDOG TIMER COMMANDS
The IPMC implements a standardized ‘Watchdog Timer’ that can be used for a number of
system time-out functions by System Management Software (SMS) or by the monitor. Set-
ting a time-out value of zero allows the selected time-out action to occur immediately. This
provides a standardized means for devices on the IPMB to perform emergency recovery
actions.
Table 7-7: IPMC Watchdog Timer Commands
Command:
See Page:
Optional/Mandatory:
Reset Watchdog Timer
Set Watchdog Timer
Get Watchdog Timer
M
M
M
Watchdog Timer Actions
The following actions are available on expiration of the Watchdog Timer:
• System Reset
• System Power Off
The System Reset and System Power Off on time-out selections are mutually exclusive. The
watchdog timer is stopped whenever the system is powered down. A command must be
sent to start the timer after the system powers up.
Watchdog Timer Use Field and Expiration Flags
The watchdog timer provides a ‘timer use’ field that indicates the current use assigned to
the watchdog timer. The watchdog timer provides a corresponding set of ‘timer use expira-
tion’ flags that are used to track the type of time-out(s) that had occurred.
The time-out use expiration flags retain their state across system resets and power cycles, as
long as the IPMC remains powered. The flags are normally cleared solely by the Set Watch-
dog Timer command; with the exception of the “don’t log” flag, which is cleared after every
system hard reset or timer time-out.
The Timer Use fields indicate:
Monitor FRB-2 Time-out:
A Fault-resilient Booting, level 2 (FRB-2) time-out has occurred. This indicates that the last
system reset or power cycle was due to the system time-out during POST, presumed to be
caused by a failure or hang related to the bootstrap processor.
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Monitor POST Time-out:
In this mode, the time-out occurred while the watchdog timer was being used by the moni-
tor for some purpose other than FRB-2 or OS Load Watchdog.
OS Load Time-out: The last reset or power cycle was caused by the timer being used to ‘watchdog’ the interval
from ‘boot’ to OS up and running. This mode requires system management software, or OS
support. The monitor should clear this flag if it starts this timer during POST.
SMS ‘OS Watchdog’ Time-out:
This indicates that the timer was being used by System Management Software (SMS). Dur-
ing run-time, SMS starts the timer, then periodically resets it to keep it from expiring. This
periodic action serves as a ‘heartbeat’ that indicates that the OS (or at least the SMS task) is
still functioning. If SMS hangs, the timer expires and the IPMC generates a system reset.
When SMS enables the timer, it should make sure the ‘SMS’ bit is set to indicate that the
timer is being used in its ‘OS Watchdog’ role.
OEM: This indicates that the timer was being used for an OEM-specific function.
Using the Timer Use Field and Expiration Flags
The software that sets the Timer Use field is responsible for managing the associated Timer
Use Expiration flag. For example, if System Management Software (SMS) sets the timer use
to “SMS/OS Watchdog,” then that same SMS is responsible for acting on and clearing the
associated Timer Use Expiration flag.
In addition, software should only interpret or manage the expiration flags for watchdog
timer uses that it set. For example, the monitor should not report watchdog timer expira-
tions or clear the expiration flags for non-monitor uses of the timer. This is to allow the soft-
ware that did set the Timer Use to see that a matching expiration occurred.
Watchdog Timer Event Logging
By default, the IPMC will automatically log the corresponding sensor-specific watchdog sen-
sor event when a timer expiration occurs. A “don’t log” bit is provided to temporarily disable
the automatic logging. The “don’t log” bit is automatically cleared (logging re-enabled)
whenever a timer expiration occurs.
Monitor Support for Watchdog Timer
If a system “Warm Reset” occurs, the watchdog timer may still be running while the moni-
tor executes POST. Therefore, the monitor should take steps to stop or restart the watchdog
timer early in POST. Otherwise, the timer may expire later during POST or after the OS has
booted.
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System Management: IPMC Watchdog Timer Commands
Reset Watchdog Timer Command
The Reset Watchdog Timer command is used for starting and restarting the Watchdog
Timer from the initial countdown value that was specified in the Set Watchdog Timer com-
mand.
If a pretime-out interrupt has been configured, the Reset Watchdog Timer command will
not restart the timer once the pretime-out interval has been reached. The only way to stop
the timer once it has reached this point is via the Set Watchdog Timer command.
Table 7-8: Reset Watchdog Timer Command
Type:
Request Data
Response Data
Byte:
—
1
Data Field:
—
Completion Code
Set Watchdog Timer Command
The Set Watchdog Timer command is used for initializing and configuring the watchdog
timer. The command is also used for stopping the timer.
If the timer is already running, the Set Watchdog Timer command stops the timer (unless
the “don’t stop” bit is set) and clears the Watchdog pretime-out interrupt flag (see Get Mes-
sage Flags command in the IPMI specification v1.5). IPMC hard resets, system hard resets,
and the Cold Reset command also stop the timer and clear the flag.
Byte 1: This selects the timer use and configures whether an event will be logged on expiration.
Byte 2: This selects the time-out action and pretime-out interrupt type.
Byte 3: This sets the pretime-out interval. If the interval is set to zero, the pretime-out action occurs
concurrently with the time-out action.
Byte 4: This clears the Timer Use Expiration flags. A bit set in byte 4 of this command clears the cor-
responding bit in byte 5 of the Get Watchdog Timer command.
Bytes 5 and 6: These hold the least significant and most significant bytes, respectfully, of the countdown
value. The Watchdog Timer decrement is one count/100 ms. The counter expires when the
count reaches zero. If the counter is loaded with zero and the Reset Watchdog command is
issued to start the timer, the associated timer events occur immediately.
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System Management: IPMC Watchdog Timer Commands
Table 7-9: Set Watchdog Timer Command
Type:
Byte:
Data Field:
Request Data
1
Timer Use
[7] 1b=don’t log
[6] 1b=the don’t stop timer on Set Watchdog Timer command
(new for IPMI v1.5) new parameters take effect
immediately. If timer is already running, countdown value
will get set to given value and countdown will continue
from that point. If timer is already stopped, it will remain
stopped. If the pretime-out interrupt bit is set, it will get
1
cleared.
0b=timer stops automatically when Set Watchdog Timer
command is received
[5:3] reserved
[2:0] timer use (logged on expiration when “don’t log” bit = 0b)
000b=reserved
001b=Monitor FRB-2
010b=Monitor/POST
011b=OS Load
100b=SMS/OS
101b=OEM
110b-111b=reserved
2
Timer Actions
[7] reserved
[6:4] pretime-out interrupt (logged on expiration when “don’t
log” bit = 0b)
000b=none
001b=SMI
010b=NMI/Diagnostic Interrupt
011b=Messaging Interrupt (this is the same interrupt as
allocated to the messaging interface)
100b, 111b =reserved
[3] reserved
[2:0] time-out action
000b=no action
001b=Hard Reset
010b=Power Down
011b=Power Cycle
100b, 111b=reserved
3
Pretime-out interval in seconds, ‘1’ based
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System Management: IPMC Watchdog Timer Commands
Type:
Byte:
Data Field: (continued)
Request Data
(continued)
4
Timer Use Expiration flags clear
(0b=leave alone, 1b=clear timer use expiration bit)
[7] reserved
[6] reserved
[5] OEM
[4] SMS/OS
[3] OS Load
[2] Monitor/POST
[1] Monitor FRB-2
[0] reserved
5
6
1
Initial countdown value, lsbyte (100 ms/count)
Initial countdown value, msbyte
Completion Code
Response Data
1. Potential race conditions exist with implementation of this option. If the Set Watchdog Timer command is
sent just before a pretime-out interrupt or time-out is set to occur, the time-out could occur before the
command is executed. To avoid this condition, it is recommended that software set this value no closer
than three counts before the pretime-out or time-out value is reached.
Get Watchdog Timer Command
This command retrieves the current settings and present countdown of the watchdog
timer. The Timer Use Expiration flags in byte 5 retain their states across system resets and
system power cycles. With the exception of bit 6 in the Timer Use byte, the Timer Use Expi-
ration flags are cleared using the Set Watchdog Timer command. They may also become
cleared because of a loss of IPMC power, firmware update, or other cause of IPMC hard
reset. Bit 6 of the Timer Use byte is automatically cleared to 0b whenever the timer times
out, is stopped when the system is powered down, enters a sleep state, or is reset.
Table 7-10: Get Watchdog Timer Command
Type:
Request Data
Response Data
Byte:
—
Data Field:
—
1
Completion Code
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System Management: IPMC Watchdog Timer Commands
Type:
Byte:
Data Field: (continued)
Response Data
2
Timer Use
[7] 1b=don’t log
[6] 1b=timer is started (running)
0b=timer is stopped
[5:3] reserved
[2:0] timer use (logged on expiration if “don’t log” bit = 0)
000b=reserved
001b=Monitor FRB-2
010b=Monitor/POST
011b=OS Load
100b=SMS/OS
101b=OEM
110b, 111b=reserved
3
Timer Actions
[7] reserved
[6:4] pretime-out interrupt
000b=none
001b=SMI
010b=NMI/Diagnostic Interrupt
011b=Messaging Interrupt (this would be the same interrupt
as allocated to the messaging interface)
100b, 111b =reserved
[3] reserved
[2:0] time-out action
000b=no action
001b=Hard Reset
010b=Power Down
011b=Power Cycle
100b, 111b=reserved
4
5
Pretime-out interval in seconds, ‘1’based
Timer Use Expiration flags (1b=timer expired while associated ‘use’
was selected)
[7] reserved
[6] reserved
[5] OEM
[4] SMS/OS
[3] OS Load
[2] Monitor/POST
[1] Monitor FRB-2
[0] reserved
6
7
Initial countdown value, lsbyte (100 ms/count)
Initial countdown, msbyte
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System Management: FRU LEDs
Type:
Byte:
Data Field: (continued)
Response Data
8
Present countdown value, lsbyte. The initial countdown value and
present countdown values should match immediately after the
countdown is initialized via a Set Watchdog Timer command and
after a Reset Watchdog Timer has been executed.
Note that internal delays in the IPMC may require software to delay
up to 100 ms before seeing the countdown value change and be
reflected in the Get Watchdog Timer command.
9
Present countdown value, msbyte
FRU LEDS
This section describes the front panel LEDs controlled by the IPMC and documents how to
control each LED with the standard FRU LED commands. Reference the PICMG® 3.0 Revision
2.0 AdvancedTCA® Base Specification for more detailed information.
their location.
Table 7-11: FRU LEDs
ID
Reference
LEDs:
(hex):
Designator:
Description:
Hot
Swap
00
CR57
The blue Hot Swap LED displays four states:
On—the board can be safely extracted
Off—the board is operating and not safe for
extraction,
Long blink—insertion is in progress
Short blink—requesting permission for
extraction
OOS
01
CR54
The Out Of Service programmable LED
controlled by the IPMI controller is either red
(North America) or amber (Europe). When lit,
this LED indicates the ATCA-9305 is in a failed
state.
2
3
02
03
CR55
CR56
The green LED is user defined, but frequently is
used as an In Service indicator. When used as an
In Service indicator, a lit LED indicates that the
ATCA-9305 is functioning properly.
The amber LED is user defined.
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System Management: FRU LEDs
Get FRU LED Properties Command
This command allows software to determine which LEDs are under IPMC control.
Table 7-12: Get FRU LED Properties Command
Type:
Byte:
Data Field:
Request Data
1
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2
1
2
FRU Device ID
Response Data
Completion Code
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
3
4
General Status LED Properties—indicates the FRU’s ability to control
the four general status LEDs. When a bit is set, the FRU can control
the associated LED.
Bits [7:4] reserved, set to 0
Bit [3] LED3
Bit [2] LED2
Bit [1] LED1
Bit [0] Blue LED
Application Specific LED Count—is the number of application
specific LEDs under IPMC control.
00h-FBh Number of application-specific LEDs under IPMC
control. If none are present, this field is 00h.
FCh-FFh reserved
Get LED Color Capabilities Command
LED 1 can be either red or amber, this command is used to determine the valid color prior to
issuing a Set FRU LED State command.
Table 7-13: Get LED Color Capabilities Command
Type:
Byte:
Data Field:
Request Data
1
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2
3
FRU Device ID
LED ID
FFh reserved
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System Management: FRU LEDs
Type:
Byte:
Data Field: (continued)
Response Data
1
Completion Code
CCh If the LED ID contained in the Request data is not present
on the FRU
2
3
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
LED Color Capabilities—when a bit is set, the LED supports the
color.
Bit [7] reserved, set to 0
Bit [6] LED supports white
Bit [5] LED supports orange
Bit [4] LED supports amber
Bit [3] LED supports green
Bit [2] LED supports red
Bit [1] LED supports blue
Bit [0] reserved, set to 0
4
Default LED Color in Local Control State
Bit [7] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
5
Default LED Color in Override State
Bit [7] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
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System Management: FRU LEDs
Set FRU LED State Command
The Set FRU LED State command allows the state of the FRU LEDs to be controlled by the
management system.
Table 7-14: Set FRU LED State Command
Type:
Byte:
Data Field:
Request Data
1
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2
3
FRU Device ID
LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh Lamp Test (all LEDs under management control are
addressed)
4
LED Function
00h LED off override
01h-FAh LED blinking override
FBh Lamp Test state Turn on LED specified in byte 3 for the
duration specified in byte 5, then return to the highest
priority state.
FCh LED state restored to Local Control state
FDh-FEh reserved
FFh LED on override
5
On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
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System Management: FRU LEDs
Type:
Byte:
Data Field: (continued)
Request Data
6
Color When Illuminated—sets the override color when LED Function
is 01h-FAh and FFh. This byte sets the Local Control color when LED
Function is FCh. This byte may be ignored during Lamp Test or may
be used to control the color during the lamp test when LED
Function is FBh.
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Use Blue
2h Use Red
3h Use Green
4h Use Amber
5h Use Orange
6h Use White
7h-Dh reserved
Eh Do not change
Fh Use default color
Response Data
1
2
Completion Code
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
Get FRU LED State Command
The Get FRU LED State command allows the state of the FRU LEDs to be controlled by the
management system.
Table 7-15: Get FRU LED State Command
Type:
Byte:
Data Field:
Request Data
1
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
2
3
FRU Device ID
LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh reserved
Response Data
1
2
Completion Code
PICMG Identifier—indicates that this is a PICMG defined group
extension command. Use value 00h.
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System Management: FRU LEDs
Type:
Byte:
Data Field: (continued)
Response Data
3
LED States
Bits [7:3] reserved, set to 0
Bit [2] 1b if Lamp Test has been enabled
Bit [1] 1b if override state has been enabled
Bit [2] 1b if IPMC has a Local control state
4
Local Control LED Function
00h LED is off (default if Local Control not supported)
01h-FAh LED is blinking Off duration specified by this byte,
on duration specified by byte 5 (in tens of
milliseconds)
FBh-FEh reserved
FFh LED is on
5
6
On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
Local Control Color
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
7
8
Override State LED Function—is required if either override state or
Lamp Test is in effect.
00h LED override state is off
01h-FAh LED override state is blinking Off duration is
specified by this byte, on duration specified by
byte 8 (in tens of milliseconds)
FBh-FEh reserved
FFh LED override state is on
Override State On Duration—is required if either override state or
Lamp Test is in effect (in tens of milliseconds).
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System Management: Vendor Commands
Type:
Byte:
Data Field: (continued)
Response Data
9
Override State Color
Bits [7:4] reserved, set to 0
Bits [3:0]
0h reserved
1h Blue
2h Red
3h Green
4h Amber
5h Orange
6h White
7h-Fh reserved
10
Lamp Test Duration—is optional if Lamp Test is not in effect
(hundreds of milliseconds).
VENDOR COMMANDS
The IPMC supports additional IPMI commands that are specific to Pigeon Point and/or
Emerson. This section provides detailed descriptions of those extension or SIPL commands.
Table 7-16: Vendor Command Summary
Command:
Get Status
netFn:
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
LUN:
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
2E, 2F
Cmd:
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
Get Serial Interface Properties
Set Serial Interface Properties
Get Debug Level
Set Debug Level
Get Hardware Address
Set Hardware Address
Get Handle Switch
Set Handle Switch
Get Payload Communication Time-Out
Set Payload Communication Time-Out
Enable Payload Control
Disable Payload Control
Reset IPMC
Hang IPMC
Bused Resource Control
Bused Resource Status
Graceful Reset
0F
10
11
12
15
16
Diagnostic Interrupt Results
Get Payload Shutdown Time-Out
Set Payload Shutdown Time-Out
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Command:
Set Local FRU LED State
(continued)
netFn:
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
OEM
LUN:
2E, 2F
2E, 2F
2E, 2F
2E, 2F
30, 31
30, 31
30, 31
30, 31
30, 31
Cmd:
18
Get Local FRU LED State
Update Discrete Sensor
19
1A
1B
Update Threshold Sensor
Reserved for Message Listeners
Add Message Listener
10
11
Remove Message Listener
Get Message Listener List
Update Firmware Progress Sensor
12
13
F0
Get Status
The IPMC firmware notifies the payload about changes of all status bits except for bits 0-2
by sending an unprintable character (ASCII 07, BELL) over the Payload Interface. The pay-
load is expected to use the Get Status command to identify pending events and other SIPL
commands to provide a response (if necessary). The event notification character is sent in a
synchronous manner, and does not appear in the contents of SIPL messages sent to the pay-
load.
Table 7-17: Get Status Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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System Management: Vendor Commands
Type:
Byte:
Data Field:
(continued)
Response Data
5
Bit [7] Graceful Reboot Request
If set to 1, indicates that the payload is requested to initiate the
graceful reboot sequence
Bit [6] Diagnostic Interrupt Request
If set to 1, indicates that a payload diagnostic interrupt request
has arrived
Bit [5] Shutdown Alert
If set to 1, indicates that the payload is going to be shutdown
Bit [4] Reset Alert
If set to 1, indicates that the payload is going to be reset
Bit [3] Sensor Alert
If set to 1, indicates that at least one of the IPMC sensors detects
threshold crossing
Bits [2:1] Mode
The current IPMC modes are defined as:
0 Normal
1 Standalone
2 Manual Standalone
Bit [0] Control
If set to 0, the IPMC control over the payload is disabled
6
Bits [4:7] Metallic Bus 2 Events
These bits indicate pending Metallic Bus 2 requests arrived from
the carrier controller:
0 Metallic Bus 2 Query
1 Metallic Bus 2 Release
2 Metallic Bus 2 Force
3 Metallic Bus 2 Free
Bits [0:3] Metallic Bus 1 Events
These bits indicate pending Metallic Bus 1 requests arrived from
the carrier controller:
0 Metallic Bus 1 Query
1 Metallic Bus 1 Release
2 Metallic Bus 1 Force
3 Metallic Bus 1 Free
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System Management: Vendor Commands
Type:
Byte:
Data Field:
(continued)
Response Data
7
Bits [4:7] Clock Bus 2 Events
These bits indicate pending Clock Bus 2 requests arrived from
the carrier controller:
0 Clock Bus 2 Query
1 Clock Bus 2 Release
2 Clock Bus 2 Force
3 Clock Bus 2 Free
Bits [0:3] Clock Bus 1 Events
These bits indicate pending Clock Bus 1 requests arrived from
the carrier controller:
0 Clock Bus 1 Query
1 Clock Bus 1 Release
2 Clock Bus 1 Force
3 Clock Bus 1 Free
8
Bits [4:7] reserved
Bits [0:3] Clock Bus 3 Events
These bits indicate pending Clock Bus 3 requests arrived from
the carrier controller:
0 Clock Bus 3 Query
1 Clock Bus 3 Release
2 Clock Bus 3 Force
3 Clock Bus 3 Free
Get Serial Interface Properties
The Get Serial Interface Properties command is used to get the properties of a particular
serial interface.
Table 7-18: Get Serial Interface Properties Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Interface ID
0 Serial Debug Interface
1 Payload Interface
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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System Management: Vendor Commands
Type:
Byte:
Data Field:
(continued)
Response Data
5
Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial
interface
Bits [6:4] reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0 9600 bps
1 19200 bps
2 38400 bps
3 57600 bps (unsupported)
4 115200 bps (unsupported)
Set Serial Interface Properties
The Set Serial Interface Properties command is used to set the properties of a particular
serial interface.
Table 7-19: Set Serial Interface Properties Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
5
Interface ID
0 Serial Debug Interface
1 Payload Interface
Bit [7] Echo On
If this bit is set, the IPMC enables echo for the given serial
interface
Bits [6:4] reserved
Bits [3:0] Baud Rate ID
The baud rate ID defines the interface baud rate as follows:
0 9600 bps
1 19200 bps
2 38400 bps
3 57600 bps (unsupported)
4 115200 bps (unsupported)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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Get Debug Level
The Get Debug Level command gets the current debug level of the IPMC firmware.
Table 7-20: Get Debug Level Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5
Bits [7:5] reserved
Bit [4] IPMB Dump Enable
If set to 1, the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-0 or IPMB -L
Bit [3] Payload Logging Enable
If set to 1, the IPMC provides a trace of SIPL activity on the
Payload interface onto the Serial Debug interface
Bit [2] Alert Logging Enable
If set to 1, the IPMC outputs important alert messages onto the
Serial Debug interface
Bit [1] Low-level Error Logging Enable
If set to 1, the IPMC outputs low-level error/diagnostic messages
onto the Serial Debug interface
Bit [0] Error Logging Enable
If set to 1, the IPMC outputs error/diagnostic messages onto the
Serial Debug interface
Set Debug Level
The Set Debug Level command sets the current debug level of the IPMC firmware.
Table 7-21: Set Debug Level Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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System Management: Vendor Commands
Type:
Byte:
Data Field:
(continued)
Request Data
4
Bits [7:5] reserved
Bit [4] IPMB Dump Enable
If set to 1, the IPMC provides a trace of IPMB messages that are
arriving to/going from the IPMC via IPMB-0 or IPMB-L
Bit [3] Payload Logging Enable
If set to 1, the IPMC provides a trace of SIPL activity on the
Payload interface onto the Serial Debug interface
Bit [2] Alert Logging Enable
If set to 1, the IPMC outputs important alert messages onto the
Serial Debug interface
Bit [1] Low-level Error Logging Enable
If set to 1, the IPMC outputs low-level error/diagnostic
messages onto the Serial Debug interface
Bit [0] Error Logging Enable
If set to 1, the IPMC outputs error/diagnostic messages onto the
Serial Debug interface
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Get Hardware Address
The Get Hardware Address command reads the hardware address of the IPMC.
Table 7-22: Get Hardware Address Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5
Hardware Address
Set Hardware Address
The Set Hardware Address command allows overriding of the hardware address read from
hardware when the IPMC operates in (Manual) Standalone mode.
Table 7-23: Set Hardware Address Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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Type:
Byte:
Data Field:
(continued)
4
Hardware Address
If set to 00, the ability to override the hardware address is
disabled
NOTE: A hardware address change only takes effect after an
IPMC reset. See “Reset IPMC” on page 7-33.
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Get Handle Switch
The Get Handle Switch command reads the state of the Hot Swap handle of the IPMC. Over-
riding of the handle switch state is allowed only if the IPMC operates in (Manual) Standalone
mode.
Table 7-24: Get Handle Switch Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5
Handle Switch Status
0x00 The handle switch is open
0x01 The handle switch is closed
0x02 The handle switch state is read from hardware
Set Handle Switch
The Set Handle Switch command sets the state of the Hot Swap handle switch in (Manual)
Standalone mode.
Table 7-25: Set Handle Switch Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Handle Switch Status
0x00 The handle switch is open
0x01 The handle switch is closed
0x02 The handle switch state is read from hardware
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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System Management: Vendor Commands
Get Payload Communication Time-Out
The Get Payload Communication Time-Out command reads the payload communication
time-out value.
Table 7-26: Get Payload Communication Time-Out Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5
Payload Time-out
Payload communication time-out measured in hundreds of
milliseconds. Thus, the payload communication time-out
may vary from 0.1 to 25.5 seconds.
Set Payload Communication Time-Out
The Set Payload Communication Time-Out command sets the payload communication
time-out value.
Table 7-27: Set Payload Communication Time-Out Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Payload Time-out
Payload communication time-out measured in hundreds of
milliseconds. Thus, the payload communication time-out
may vary from 0.1 to 25.5 seconds.
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Enable Payload Control
The Enable Payload Control command enables payload control from the Serial Debug inter-
face.
Table 7-28: Enable Payload Control Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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Disable Payload Control
The Disable Payload Control command disables payload control from the Serial Debug
interface.
Table 7-29: Disable Payload Control Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Reset IPMC
The Reset IPMC command allows the payload to reset the IPMC over the SIPL.
Table 7-30: Reset IPMC Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Reset Type Code
0x00 Cold IPMC reset to the current mode
0x01 Cold IPMC reset to the Normal mode
0x02 Cold IPMC reset to the Standalone mode
0x03 Cold IPMC reset to the Manual Standalone mode
0x04 Reset the IPMC and enter Upgrade mode
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Hang IPMC
The IPMC provides a means to test the watchdog timer support by implementing the Hang
IPMC command, which simulates firmware hanging by entering an endless loop.
Table 7-31: Hang IPMC Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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Bused Resource
To send a Bused Resource command to the carrier controller, the payload uses the Bused
Resource command of the SIPL.
Table 7-32: Bused Resource Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Command Types for Carrier Controller to Board
0 Query if board has control of the bus
1 Release requests a board to release control of the bus
2 Force board to release control of bus immediately
3 Bus Free informs board that the bus is available
Command Types for Board to Carrier Controller
0 Request to seize control of the bus
1 Relinquish control of the bus, carrier controller can reassign
control of bus
2 Notify carrier controller that control of the bused resource has
been transferred to this board from another authorized board
5
Bused Resource ID
0 Metallic Test Bus pair #1
1 Metallic Test Bus pair #2
2 Synch clock group 1 (CLK1A and CLK1B pairs)
3 Synch clock group 2 (CLK2A and CLK2B pairs)
3 Synch clock group 3 (CLK3A and CLK3B pairs)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5
Status
0 Ack; carrier controller acknowledges that board has control
1 Error; same as Ack, but carrier controller believes board should
not have been given control of the resource (optional)
2 Deny; carrier controller denies control of resource by the board
Bused Resource Status
If the IPMC receives a Bused Resource command from IPMB-0, it asserts an appropriate
event and notifies the payload which uses the Bused Resource Status command over the
SIPL. When the IPMC receives a Bused Resource Status command, the respective bit in the
IPMC status is cleared.
The payload must issue a Bused Resource Status command before the payload communica-
tion time-out time. If the payload does not issue such a command before the payload com-
munication time-out time, the IPMC sends the 0xC3 completion code (Time-Out) in the
appropriate Bused Resource command reply.
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Table 7-33: Bused Resource Status Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Command Types for Carrier Controller to Board
0 Query if board has control of the bus
(0=In control, 1= No control)
1 Release request a board to release control of the bus
(0=Ack, 1=Refused, 2=No control)
2 Force board to release control of bus immediately
(0=Ack, 1=No control)
3 Bus Free informs board that the bus is available
(0=Accept, 1=Not needed)
Command Types for Board to Carrier Controller
0 Request to seize control of the bus
(0=Grant, 1=Busy, 2=Defer, 3=Deny)
1 Relinquish control of the bus, carrier controller can reassign
control of bus (0=Ack, 1=Error)
2 Notify carrier controller that control of the bused resource has
been transferred to this board from another authorized board
(0=Ack, 1=Error, 2=Deny)
5
6
Bused Resource ID
0 Metallic Test Bus pair #1
1 Metallic Test Bus pair #2
2 Synch clock group 1 (CLK1A and CLK1B pairs)
3 Synch clock group 2 (CLK2A and CLK2B pairs)
4 Synch clock group 3 (CLK3A and CLK3B pairs)
Status
0 Ack; carrier controller acknowledges that board has control
1 Error; same as Ack, but carrier controller believes board should
not have been given control of the resource (optional)
2 Deny; carrier controller denies control of resource by the board
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Graceful Reset
The IPMC supports the Graceful Reboot option of the FRU Control command. On receiving
such a command, the IPMC sets the Graceful Reboot Request bit of the IPMC status, sends a
status update notification to the payload, and waits for the Graceful Reset command from
the payload. If the IPMC receives such a command before the payload communication time-
out time, it sends the 0x00 completion code (Success) to the carrier controller. Otherwise
the 0xC3 completion code (Time-Out) is sent.
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The IPMC does not reset the payload on receiving the Graceful Reset command or time-out.
If the IPMC participation is necessary, the payload must request the IPMC to perform a pay-
load reset. The Graceful Reset command is also used to notify the IPMC about the comple-
tion of the payload shutdown sequence.
Table 7-34: Graceful Reset Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Diagnostic Interrupt Results
The IPMC supports the Issue Diagnostic Interrupt feature of the FRU Control command. The
payload is notified about a diagnostic interrupt over the SIPL. The payload is expected to
return diagnostic interrupt results before the payload communication time-out using the
Diagnostic Interrupt Results command of the SIPL.
Table 7-35: Diagnostic Interrupt Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
If the payload responds before the payload communication
time-out, the diagnostic interrupt return code is forwarded to the
carrier controller as the completion code of the FRU Control
command response. Otherwise, the 0xC3 completion code (Time-
Out) is returned.
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Get Payload Shutdown Time-Out
When the carrier controller commands the IPMC to shut down the payload (i.e. sends the
Set Power Level (0) command), the IPMC notifies the payload by asserting an appropriate
alert and sending an alert notification to the payload. Upon receiving this notification, the
payload software is expected to initiate the payload shutdown sequence. After performing
this sequence, the payload should send the Graceful Reset command to the IPMC over the
Payload interface to notify the IPMC that the payload shutdown is complete.
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To avoid deadlocks that may occur if the payload software does not respond, the IPMC pro-
vides a special time-out for the payload shutdown sequence. If the payload does not send
the Graceful Reset command within a definite period of time, the IPMC assumes that the
payload shutdown sequence is finished, and sends a Module Quiesced Hot Swap event to
the ATCA-9305 controller.
Table 7-36: Get Payload Shutdown Time-Out Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5:6
Time-Out measured in hundreds of milliseconds, LSB first
Set Payload Shutdown Time-Out
The Set Payload Shutdown Time-Out command is defined as follows:
Table 7-37: Set Payload Shutdown Time-Out Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4:5
1
Time-Out measured in hundreds of milliseconds, LSB first
Completion Code
Response Data
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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Set Local FRU LED State
The Set Local FRU LED State command is used to change the local state of a FRU LED.
Table 7-38: Set Local FRU LED State Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
5
FRU Device ID
LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh Lamp Test (all LEDs under management control are
addressed)
6
LED Function
00h LED off override
01h-FAh LED blinking override
FBh Lamp Test state Turn on LED specified in byte 3 for the
duration specified in byte 5, then return to the highest
priority state.
FCh LED state restored to Local Control state
FDh-FEh reserved
FFh LED on override
7
On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
8
9
Color parameter specifies the color of the LED in the local state for
multi-color LEDs
If the off-first flag parameter is 0, the on part of the blink cycle of
the LED precedes the off part of the cycle. Otherwise, the off part
of the blink cycle precedes the on part of the cycle.
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
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Get Local FRU LED State
The Get Local FRU LED State command is used to read the local state of a FRU LED.
Table 7-39: Get Local FRU LED State Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
5
FRU Device ID
LED ID
00h Blue LED (Hot Swap)
01h LED 1 (OOS)
02h LED 2
03h LED 3
04h-FEh OEM defined LEDs
FFh reserved (all LEDs under management control are
addressed)
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
5
Local Control LED Function
00h LED is off (default if Local Control not supported)
01h-FAh LED is blinking Off duration specified by this byte,
on duration specified by byte 5 (in tens of
milliseconds)
FBh-FEh reserved
FFh LED is on
6
Local Control On Duration
LED on-time is measured in tens of milliseconds
Lamp Test time in hundreds of milliseconds if byte 4=FBh, time
value must be less than 128. Other values when Byte 4=FBh are
reserved. Otherwise, this field is ignored and shall be set to 0h.
7
8
Color parameter specifies the color of the LED in the local state for
multi-color LEDs
If the off-first flag parameter is 0, the on part of the blink cycle of
the LED precedes the off part of the cycle. Otherwise, the off part
of the blink cycle precedes the on part of the cycle.
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System Management: Vendor Commands
Update Discrete Sensor
The Update Discrete Sensor command is used to change the state of a discrete sensor con-
trolled by the payload.
Table 7-40: Update Discrete Sensor Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
5
Sensor ID identifies the payload-controlled discrete sensor that has
to be updated
Update flags
0 0=sensor initialization is complete
1=sensor is in the initial update state
1:2 reserved, set to 0
3 0=globally disable events from the sensor
1=leave the global event enable bit intact
4 0=globally enable events from the sensor
1=leave the global event enable bit intact
5 0=globally disable sensor scanning
1=leave the global scanning enable bit intact
6 0=globally enable sensor scanning
1=leave the global scanning enable bit intact
7 reserved, set to 0
6:7
New status LSB and new status MSB are the least and most
significant bytes of the new sensor state
Response Data
1
Completion Code
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
Update Threshold Sensor
The Update Threshold Sensor command is used to change the state of a threshold sensor
controlled by the payload.
Table 7-41: Update Threshold Sensor Command
Type:
Byte:
Data Field:
Request Data
1:3
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
4
Sensor ID parameter identifies the payload-controlled threshold
sensor that has to be updated
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System Management: Boot Device Redirection (BDR)
Type:
Byte:
Data Field:
(continued)
Request Data
5
Update flags
0 0=sensor initialization is complete
1=sensor is in the initial update state
1:2 reserved, set to 0
3 0=globally disable events from the sensor
1=leave the global event enable bit intact
4 0=globally enable events from the sensor
1=leave the global event enable bit intact
5 0=globally disable sensor scanning
1=leave the global scanning enable bit intact
6 0=globally enable sensor scanning
1=leave the global scanning enable bit intact
7 reserved, set to 0
6
New raw reading of the sensor
Completion Code
Response Data
1
2:4
PPS IANA Private Enterprise ID, MS Byte first
0x00400A = 16394 (Pigeon Point Systems)
BOOT DEVICE REDIRECTION (BDR)
The IPMC enables the ATCA-9305 to recover from monitor corruption by booting from a
redundant copy in another flash device. The mechanism relies on an IPMC software internal
watchdog to expire when corrupted code fails to reset the timer. This watchdog begins
counting down as soon as the payload is power cycled or reset. If the timer expires (approxi-
mately 30 seconds), the boot redirection will activate and the board will reset. Following
this automatic reset, IPMC will attempt to boot from the next flash device according to
Fig. 7-4. This sequence will continue until a valid boot image clears the watchdog.
shunt is present on J9 [1:2}, the ATCA-9305 boots from socket. When forcing boot from the
socket, use bootdev and reset from the command line to test boot from a flash device. If
shunt is not installed on J9 [1:2], the ATCA-9305 follows the default boot redirection shown
Note: The System Management IPMC can override the BDFR and swap the flash banks (from 1 to 2, or 2 to 1).
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System Management: Boot Device Redirection (BDR)
Figure 7-4: Boot Device Diagram
512 KB socketed
flash installed on
ATCA-9305?
No
Initial boot attempt is from
ATCA-9305 soldered
flash bank 1
Yes
Yes
No
Jumper J11 [1:2]
shunt installed?
Flash bank 2
fail?
Flash bank 1
fail?
No
No
Yes
Yes
Secondary boot
attempt is from ATCA-
9305 soldered
Boot device is 512
KB socketed flash
BDR Watchdog
disabled
Boot from
flash bank 2
Boot from
flash bank 1
flash bank 2
Note: The Boot Device Redirection mechanism is disabled when booting from the 512 KB socketed flash.
Figure 7-5: Boot Redirection Control Diagram
Payload Reset
Monitor Booted
Management
Controller
Power Good
Force Boot Socket
Payload
Payload Reset Indication
Boot Select [ ]
I2C Port
Expander
Payload Reset Indication Clear
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Management Controller:
The controller provides a signals to reset the payload.
Payload: This provides signals to the controller indicating when the payload has reset for any reason,
that the payload is powered, and that the payload has finished its monitor booting
sequence. By default, a powered payload enables the watchdog and disables when the pay-
load is not powered.
2
2
I C Port Expander: The I C port expander provides signals to the payload to define the boot device selection
2
(boot select [1 and 2]) and to clear the payload reset indication. The I C port expander com-
municates with the controller via a private I C.
2
Payload Reset: This signal is used by the management controller to reset the payload.
Monitor Booted: This signal indicates to the management controller that a valid monitor image has finished
booting and the watchdog can be disabled.
Power Good: This signal indicates to the management controller that the payload is powered. When pay-
load power is applied, the BMC watchdog will start.
Force Boot Socket: If a shunt is present on J9 [1:2], the controller sets the boot location to socket flash with this
signal.
Payload Reset Indication:
When reset, this signal is held high by the payload until it is cleared by the IPMC using the
payload reset indication clear signal.
Boot Select [ ]: These signals select the boot device.
Payload Reset Indication Clear:
This signal clears the payload reset indication.
MESSAGE LISTENERS
Payload port dynamic control can be implemented via message listeners. The payload can
add itself as a message listener to any message destined for the IPMC target either over
IPMB-0 or the payload serial interface. When the IPMC receives a subscribed message, the
IPMC firmware copies the message into the payload’s LUN-10 Receive Message Queue and
notifies the payload via an unprintable character (ASCII 07, BELL). The payload receives the
long. The payload can add/remove/get list at any time.
Note: The message listener list is not persistent across IPMC reboots.
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System Management: Message Listeners
Add Message Listener
The Add Message Listener command adds a specified Network Function and Command to
the Message Listener List. The command returns completion code (0x00) and IANA. If this
command does not complete successfully (e.g., due to a full list), it returns 0xCD and IANA.
Table 7-42: Add Message Listener Command
Type:
Byte:
Data Field:
Request Data
1:3
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
4
Network function to add
Command to add
5
Response Data
1
Completion Code
2:4
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
Remove Message Listener
The Remove Message Listener command removes a specified Network Function and Com-
mand from the Message Listener List. The command returns completion code (0x00) and
IANA. If this command does not complete successfully (e.g., if the Network Function and
Command are not in the list), it returns 0xCD and IANA.
Table 7-43: Remove Message Listener Command
Type:
Byte:
Data Field:
Request Data
1:3
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
4
Network function to remove
Command to remove
Completion Code
5
Response Data
1
2:4
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
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System Management: System Firmware Progress Sensor
Get Message Listener List
The Get Message Listener List command returns the entire list of subscribed Message Lis-
teners. The command returns completion code (0x00) and IANA.
Table 7-44: Get Message Listener List Command
Type:
Byte:
Data Field:
Request Data
1:3
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
Response Data
1
Completion Code
2:4
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
5
Network function for listener 0
Command for listener 0
6
7
Network function for listener 1
Command for listener 1
8
9
Network function for listener 2
Command for listener 2
10
11
12
13
14
15
16
17
18
19
20
Network function for listener 3
Command for listener 3
Network function for listener 4
Command for listener 4
Network function for listener 5
Command for listener 5
Network function for listener 6
Command for listener 6
Network function for listener 7
Command for listener 7
SYSTEM FIRMWARE PROGRESS SENSOR
The Update System Firmware Progress Sensor command sets the values for the Firmware
Progress Sensor using sensor codes from the IPMI Intelligent Platform Management Inter-
face Specification, specifically (System Firmware Progress” within Table 42-3 in Section 42.2
“Sensor Type Codes and Data.”
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ATCA-9305 User’s Manual
System Management: Entities and Entity Associations
The command returns 0xC0 when the IPMC is busy and will retry until the command is suc-
cessful. If this command returns 0xCC, the sensor ID is invalid. There is only one sensor on
the board, so the sensor ID should always be “0”. When updated, the shelf manager is noti-
fied.
Table 7-45: Update System Firmware Progress Sensor Command
Type:
Byte:
Data Field:
Request Data
1:3
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 1 = CD, byte 2 = 65, byte 3 = 00
4
5
6
7
0 (The sensor ID)
Flags: reserved to 0
Offset in specification Valid offsets: 0, 1, 2
Event Data 2; content to be added into the second byte of event data
per the IPMI specification
Response Data
1
Completion Code
2:4
Emerson Network Power, Embedded Computing Inc. IANA Private
Enterprise ID
0x0065CD = 26061 (Emerson Network Power, Embedded
Computing Inc.)
LSB Byte first:byte 2 = CD, byte 3 = 65, byte 4 = 00
ENTITIES AND ENTITY ASSOCIATIONS
uses Entity IDs and Instances to describe physical components associated with FRUs.
Device-relative Entities are unique to a specific IPMC and are referenced as follows in the
specification:
r(<ipmb>,<lun>,<Entity ID>,<Entity Instance - 60>)
Using this terminology, a ATCA-9305 installed in Logical Slot 1 has the following description
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System Management: Entities and Entity Associations
Figure 7-6: IPMB Entity Structure
FRU 0 r(82, 0, A0, 0)
Inflow Temp
Outflow Temp
Hot Swap
IPMB Physical
BMC Watchdog
F/W Progress
SDRAM POST
IIC Bus POST
Flash POST
EthSwitch POST
Version change
Async Pld Rst
Payload Power
r(82, 0, 03, 0) - Cavium 1
Cavium 1 Temp
Cav1 SDRAM POST
Cav1 IIC POST
Cav1 Boot
r(82, 0, 03, 1) - Cavium 2
Cavium 2 Temp
Cav2 SDRAM POST
Cav2 IIC POST
Cav2 Boot
r(82, 0, 14, 0) - Power Module
-48V
-48V Curr
-48V Src A
-48V Src B
+3.3V Mgmt
+12V Payload
+12V Curr
FRU 1 r(82, 0, C0, 1) RTM
RTM Hot Swap
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System Management: Sensors and Sensor Data Records
SENSORS AND SENSOR DATA RECORDS
The ATCA-9305 implements a number of sensors as described in the following tables. All
values are hexadecimal.
Table 7-46: IPMI Threshold Sensors
Sensor
Type:
Event Reading
Type:
Enity
ID:
Entity
Instance: Gen:
Event
Name:
Inflow Temp
Outflow Temp
Cavium 1 Temp
Cavium 2 Temp
-48V
Temperature = 01
Temperature = 01
Temperature = 01
Temperature = 01
Voltage = 02
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
Threshold = 01
0xA0
0xA0
0x03
0x03
0x14
0x14
0x14
0x14
0x14
0x14
0x14
0x60
0x60
0x60
0x61
0x60
0x60
0x60
0x60
0x60
0x60
0x60
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-48V Curr
Current = 03
-48V Src A
Voltage = 02
-48V Src B
Voltage = 02
+3.3V Mgmt
+12V Payload
+12V Curr
Voltage = 02
Voltage = 02
Current = 03
Table 7-47: IPMI Discrete Sensors
Sensor
Type:
Event Reading
Type:
Enity
ID:
Entity
Instance: Gen:
Event
Name:
Hot Swap
Hot Swap = F0
Hot Swap = F0
IPMB Link = F1
Watchdog2 = 23
Sensor specific
discrete = 6F
0xA0
0xC0
0xA0
0xA0
0xA0
0xA0
0xA0
0xA0
0xA0
0x03
0x60
0x61
0x60
0x60
0x60
0x60
0x60
0x60
0x60
0x60
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RTM Hot Swap
IPMB Physical
BMC Watchdog
F/W Progress
SDRAM POST
IIC Bus POST
Flash POST
Sensor specific
discrete = 6F
Sensor specific
discrete = 6F
Sensor specific
discrete = 6F
System Firmware
Progress = 0F
Sensor specific
discrete = 6F
Memory = 0C
Processor = 07
Memory = 0C
Chip Set
Sensor specific
discrete = 6F
Predictive-failure
Discrete = 04
Sensor specific
discrete = 6F
EthSwitch POST
Predictive-failure
Discrete = 04
Cav1 SDRAM
POST
Memory = 0C
Sensor specific
discrete = 6F
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System Management: Sensors and Sensor Data Records
Sensor
Type:
Event Reading
Type:
Enity
ID:
Entity
Instance: Gen:
Event
Name:
Cav1 IIC POST
Processor = 07
Processor = 07
Memory = 0C
Predictive-failure
Discrete = 04
0x03
0x03
0x03
0x03
0x03
0xA0
0xA0
0xA0
0x60
0x60
0x61
0x61
0x61
0x60
0x60
0x60
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Cav1 Boot
Predictive-failure
Discrete = 04
Cav2 SDRAM
POST
Sensor specific
discrete = 6F
Cav2 IIC POST
Processor = 07
Processor = 07
Version Change
Power Supply = 08
Power Supply = 08
Predictive-failure
Discrete = 04
Cav2 Boot
Predictive-failure
Discrete = 04
Version change
Async Pld Rst
Payload Power
Sensor specific
discrete = 6F
Digital Discrete
= 03
Digital Discrete
= 03
The IPMC implements a Device Sensor Data Record (SDR) Repository that contains SDRs for
the IPMC, the FRU device, and each sensor. A system management controller may use the
Get Device SDR command to read the repository and dynamically discover the capabilities
using Sensor Data Records and the Device SDR Repository.
Under certain circumstances, some sensors connected to the IPMC can generate Event Mes-
sages for the system management controller. To enable these messages, the system man-
agement controller must send a Set Event Receiver command to the IPMC, along with the
Table 7-48: Event Message Format
1
Byte:
Field:
Description:
0
1
RsSA
Responder’s Slave Address (Address of Event Receiver)
NetFn/RsLUN
Net Function Code (0x04) in upper 6 bits; Responder’s LUN in lower 2
bits
2
3
4
Chk 1
Checksum #1
RqSA
Requester’s Slave Address (Address of our board on IPMB)
RqSeq/RqLUN
Request Sequence number in upper 6 bits; Requester’s LUN in lower 2
bits
5
6
7
8
Cmd
Command (Always 0x02 for event message)
EvMRev
Event Message Revision (0x04 for IPMI 1.5)
Sensor Type
Sensor Number
Indicates event class or type of sensor that generated the message
A unique number indicating the sensor that generated the message
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System Management: FRU Inventory
1
Byte:
Field:
Description:
(continued)
9
Event Dir/Event
Type
Upper bit indicates direction (0 = Assert, 1= Deassert); Lower 7 bits
indicate type of threshold crossing or state transition
10
11
12
13
Event Data 0
Event Data 1
Event Data 2
Chk2
Data for sensor and event type
(Optional) Data for sensor and event type
(Optional) Data for sensor and event type
Checksum #2
1. Each byte has eight bits.
Event-generating sensors with a Threshold Event/Reading Type (0x01) initiate an event mes-
sage when a sensor reading crosses the defined threshold. The default thresholds for a par-
ticular sensor are retrieved by sending the IPMC a Get Sensor Thresholds command. The
system management controller must send the IPMC a Get Sensor Reading command to
plete details on using these commands.
FRU INVENTORY
The IPMC stores Field Replaceable Unit (FRU) information in its boot memory (SROM). The
data structure contains information such as the product name, part number, serial number,
manufacturing date, and E-keying information. Refer to the IPMI specification for complete
FRU information:
Table 7-49: FRU Definition
Item:
Description:
Common Header
Version
Version number of the overall FRU data structure defined by the IPMI
FRU specification
Internal Use Area
Version
Version number of the Internal Use Area data structure defined by
the IPMI FRU specification
Internal Use Size
Board Information Area
Version
0x100 bytes are allocated for customer use in this area
Version number of the Board Information Area data structure
defined by the IPMI FRU specification
Language Code
0x01 = English
Manufacturing Date/Time
Variable, expressed as the number of minutes since 12:00 AM on
January 1, 1996
Board Manufacturer
Board Product Name
“Emerson”
“ATCA-9305”
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System Management: E-Keying
Item:
Description: (continued)
Board Serial Number
Board Part Number
FRU File ID
Variable, formatted as “730-XXXX”
Variable, formatted as “10XXXXXX-YY-Z”
Variable, for example: “fru-info.inf”
Product Information Area
Version
Version number of the Product Information Area data structure
defined by the IPMI FRU specification
Language Code
0x01 = English
Manufacturer Name
Product Name
“Emerson”
“ATCA-9305”
Product Part/Model Number
Product Version
Variable, formatted as “10XXXXXX-YY-Z”
Not used, same information is provided by the part number
Variable, formatted as “730-XXXX”
Not Used
Product Serial Number
Asset Tag
FRU File ID
Variable, for example: “fru-info.inf”
MultiRecord Area
E-Keying records
Maximum Internal Current
“12.5 Amps”
E-KEYING
This section details the interfaces governed by E-keying and the protocols they support.
Specifically, this includes the interfaces implemented by this product and the E-keying defi-
nition that corresponds to each interface.
The IPMC supports E-keying for the ATCA-9305 per PICMG® ATCA 3.0, Revision 2.0 and
PICMG 3.1, Revision 1.0 specifications The E-keying information is stored in the ATCA Point-
to-Point Connectivity Record located in the Multi-Record area of the FRU Inventory Informa-
Descriptor list, where each Link Descriptor details one type of point-to-point protocol sup-
ported by the referenced channels.
The ATCA channel descriptors define the ATCA channels implemented on a module. Each
channel has an arbitrary set of up to four ports. Channel descriptors map physical ports to
Note: Certain Ethernet core switch and fat pipe switch module GbE switch ports are disabled due to lack of e-keying
support in the monitor.
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System Management: HPM.1 Firmware Upgrade
Base Point-to-Point Connectivity
The ATCA-9305 supports two 10/100/1000BASE-T ports on Base Interface Channels 0 and
1, and two 10 GbE XAUI ports to the Fabric channels. Depending on the board configura-
tion, either two or six 10 GbE XAUI ports route to the optional rear transition module (RTM).
Table 7-50 shows the Point-to-point Connectivity Record Link Descriptors for the ATCA-
9305.
Note: For actual Point-to-Point connectivity Records for your configuration, query the IPMI controller.
Table 7-50: Link Description
1
Field:
Value:
Description:
Link Descriptor
Link Type
000100000000b
Port 0 Enabled; Base Interface; Channel 1
PICMG 3.0 Base Interface 10/100/1000BASE-T
01h
Link Type Extension
Link Grouping ID
Link Designator
Link Type
000b
00h
Independent Channel
000100000001b
Port 0 Enabled; Base Interface; Channel 2
PCIMG 3.0 Base Interface 10/100/1000BASE-T
01h
Link Type Extension
Link Grouping ID
Link Designator
Link Type
0000b
00h
Independent Channel
000110000001b
Port 0 Enabled; Update Channel Interface; Channel 1
PICMG 3.1 Ethernet Fabric Interface
Fixed 1000BASE-BX
01h
Link Type Extension
Link GroupingID
0000b
00h
Independent Channel
1. h = hexadecimal, b = binary
HPM.1 FIRMWARE UPGRADE
The ATCA-9305 IPMC firmware supports a reliable field upgrade procedure compliant with
the HPM.1 specification. The prominent features of the firmware upgrade procedure are:
• The upgrade can be performed either over the payload serial interface or IPMB-0.
• The upgrade procedure is performed while the ATCA-9305 is online and operating
normally.
• The upgrades are reliable. A failure in the download (error or interruption) does not
disturb the ATCA-9305’s ability to continue using the “old” firmware or its ability to
restart the download process.
• The upgrades are reversible. The ATCA-9305 IPMC automatically reverts back to the
previous firmware if there is a problem when first running the new code, and can be
reverted manually using the HPM.1-defined Manual Rollback command.
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System Management: IPMC Headers
HPM.1 Reliable Field Upgrade Procedure
The HPM.1 upgrade procedure is managed by a utility called the Upgrade Agent. The
Impitool utility is used as an Upgrade Agent for upgrading the ATCA-9305 IPMC firmware.
The Upgrade Agent communicates with the IPMC firmware via the payload serial interface
or IPMC-0, and uses the AdvancedTCA commands that are described in the HPM.1 specifica-
tion for upgrading the firmware. Updated firmware is packed into an image formatted in
compliance with the HPM.1 specification. That image is used by Upgrade Agent to prepare
and upgrade the IPMC firmware. The HPM.1 upgrade procedure includes the following
steps:
Preparation: This step erases the region in the flash memory where the component image will be writ-
ten.
Component Upload: This step is designed to upload the component image via IPMB or payload interface and
write it into the flash memory.
Component Activation: This step activates the previously upgraded component. This step can be deferred and per-
formed later.
IPMC HEADERS
This JTAG header (JP1) is available for in-system programming of the CPLD.
Table 7-51: IPMP CPLD JP1 Pin Assignments
Pin:
Signal:
Direction:
Pin: Signal:
1
3
5
7
9
CPLD_TCK
CPLD_TDI
CPLD_TMS
no connect
CPLD_TDO
out
in
2
ground
4
3_3V (fused)
no connect
no connect
ground
out
—
6
8
out
10
The EIA-232 debug serial port is accessible via the mini-B USB connector P4. Default port
settings are: 115200 baud (optional 9600), 8 data bits, 1 stop bit, no parity, no flow control.
Table 7-52: IPMP EIA-232 P4 Pin Assignments
Pin:
Signal:
Pin: Signal:
1
no connect
2
4
6
IPMP_RS_232_Rx
3
5
7
IPMP_RS_232_Tx
ground
no connect
ground
ground
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Section 8
Back Panel Connectors
back panel connectors, Zones 1 through 3, are described in this chapter. Whether individual
back panel connectors are populated on the ATCA-9305 depends on the specific product
configuration.
ZONE 1
Connector P10 provides the AdvancedTCA Zone 1 power (dual redundant -48 VDC) and sys-
tem management connections. Four levels of sequential mating provide proper functional-
Figure 8-1: Zone 1 Connector, P10
21
17 13
33
30
28
25
26
32
27
34
31
29
24
20 16
4
Table 8-1: Zone 1 Connector, P10 Pin Assignments
Pin:
1
Signal:
reserved
reserved
reserved
reserved
HA0
Insertion Sequence:
NA
2
NA
3
NA
4
NA
5
third
third
third
third
third
third
third
third
third
third
third
third
third
6
HA1
7
HA2
8
HA3
9
HA4
10
11
12
13
14
15
16
17
HA5
HA6
HA7 (odd parity bit)
IPMBA_SCL
IPMBA_SDA
IPMBB_SCL
IPMBB_SDA
no connect
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ATCA-9305 User’s Manual
Back Panel Connectors: Zone 2
Pin:
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal:
Insertion Sequence:
no connect
no connect
no connect
no connect
no connect
no connect
no connect
P10_CHS_GND
Logic ground
ENABLE_B
-48RTNA
third
third
third
third
third
third
third
first
first
fourth
first
-48RTNB
first
no connect
no connect
ENABLE_ A
-48A
first
first
fourth
second
third
-48B
ZONE 2
Zone 2 (ZD) defines backplane connector J23, which supports the data transport interface.
The Zone 2 connector array supports four interfaces to the AdvancedTCA backplane:
• Base Node Interface (J23) supports two Base channels (10/100/1000 BASE-T)
• Fabric Interface (J23) supports two Fabric channels (10GbE)
Figure 8-2: Zone 2 and 3 Connectors; J23, J30-J31
Row H
Row G
Row F
Row E
Row D
Row C
Row B
Row A
10
6
5
1
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ATCA-9305 User’s Manual
10009109-01
Back Panel Connectors: Zone 3
Table 8-2: Zone 2 Connector, J23 Pin Assignments
Row:
Interface:
AB:
CD:
EF:
GH:
1
2
3
4
5
Fabric
Channel 2
TX2+
TX0+
TX2+
TX0+
TRD0+
TX2-
RX2+
RX0+
RX2+
RX0+
TRD1+
RX2-
TX3+
TX1+
TX3+
TX1+
TRD2+
TX3-
TX1-
TX3-
TX1-
TRD2-
RX3+
RX1+
RX3+
RX1+
TRD3+
RX3-
TX0-
TX2-
TX0-
TRD0-
RX0-
RX2-
RX0-
TRD1-
RX1-
RX3-
RX1-
TRD3-
Fabric
Channel 1
Base
Channel 1
6
Base
TRD0+
TRD0-
TRD1+
TRD1-
TRD2+
TRD2-
TRD3+
TRD3-
Channel 2
7-10
na
no connect
ZONE 3
These optional Zone 3 type A connectors, J30, J31, and J33, support a Rear Transition Mod-
ule (RTM). I/O signals are routed through Zone 3 connectors to the RTM to allow servicing
the ATCA-9305 without using cable assemblies. Connectors J30 and J31 use the same ZD
Table 8-3: Zone 3 Connector, J30 Pin Assignments
A:
B:
C:
D:
E:
F:
G:
H:
1
RTM_10G1
_ RX0_P
RTM_10G1
_ RX0_N
PQ_PCIE_
RXD3_P
PQ_PCIE_
RXD3_N
RTM_10G2
_ RX0_P
RTM_10G2
_ RX0_N
PQ_PCIE_
TXD3_P
PQ_PCIE_
TXD3_N
2
RTM_10G1
_ RX1_P
RTM_10G1
_ RX1_N
PQ_PCIE_
RXD2_P
PQ_PCIE_
RXD2_N
RTM_10G2
_ RX1_P
RTM_10G2
_ RX1_N
PQ_PCIE_
TXD2_P
PQ_PCIE_
TXD2_N
3
RTM_10G1
_ RX2_P
RTM_10G1
_ RX2_N
PQ_PCIE_
RXD1_P
PQ_PCIE_
RXD1_N
RTM_10G2
_ RX2_P
RTM_10G2
_ RX2_N
PQ_PCIE_
TXD1_P
PQ_PCIE_
TXD1_N
4
RTM_10G1
_ RX3_P
RTM_10G1
_ RX3_N
PQ_PCIE_
RXD0_P
PQ_PCIE_
RXD0_N
RTM_10G2
_ RX3_P
RTM_10G2
_ RX3_N
PQ_PCIE_
TXD0_P
PQ_PCIE_
TXD0_N
5
RTM_10G1
_TX0_P
RTM_10G1
_ TX0_P
PCIE_
REFCLKF_P
PCIE_
REFCLKF_N
RTM_10G2
_ TX0_P
RTM_10G2
_ TX0_N
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
6
RTM_10G1
_ TX1_P
RTM_10G1
_ TX1_N
no connect
no connect
no connect
no connect
SW_MDC
no connect
no connect
no connect
no connect
SW_MDIO
RTM_10G2
_ TX1_P
RTM_10G2
_ TX1_N
7
RTM_10G1
_ TX2_P
RTM_10G1
_ TX2_N
RTM_10G2
_ TX2_P
RTM_10G2
_ TX2_N
8
RTM_10G1
_ TX3_P
RTM_10G1
_ TX3_N
RTM_10G2
_ TX3_P
RTM_10G2
_ TX3_N
9
RTM_ID3
RTM_ID2
RTM_
GPIO3
RTM_
GPIO2
RTM_
GPIO7
RTM_
GPIO6
10
RTM_ID1
RTM_ID0
RTM_
RTM_
RTM_
RTM_
GPIO1
GPIO0
GPIO5
GPIO4
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ATCA-9305 User’s Manual
Back Panel Connectors: Zone 3
Table 8-4: Zone 3 Connector, J31 Pin Assignments
A:
B:
C:
D:
E:
F:
G:
H:
1
2
3
4
5
6
7
8
RTM_10G3
_ RX0_P
RTM_10G3
_ RX0_N
RTM_10G5
_ RX0_P
RTM_10G5
_ RX0_N
RTM_10G4
_ RX0_P
RTM_10G4
_ RX0_N
RTM_10G6
_ RX0_P
RTM_10G6
_ RX0_N
RTM_10G3
_ RX1_P
RTM_10G3
_ RX1_N
RTM_10G5
_ RX1_P
RTM_10G5
_ RX1_N
RTM_10G4
_ RX1_P
RTM_10G4
_ RX1_N
RTM_10G6
_ RX1_P
RTM_10G6
_ RX1_N
RTM_10G3
_ RX2_P
RTM_10G3
_ RX2_N
RTM_10G5
_ RX2_P
RTM_10G5
_ RX2_N
RTM_10G4
_ RX2_P
RTM_10G4
_ RX2_N
RTM_10G6
_ RX2_P
RTM_10G6
_ RX2_N
RTM_10G3
_ RX3_P
RTM_10G3
_ RX3_N
RTM_10G5
_ RX3_P
RTM_10G5
_ RX3_N
RTM_10G4
_ RX3_P
RTM_10G4
_ RX3_N
RTM_10G6
_ RX3_P
RTM_10G6
_ RX3_N
RTM_10G3
_ TX0_P
RTM_10G3
_ TX0_N
RTM_10G5
_ TX0_P
RTM_10G5
_ TX0_N
RTM_10G4
_ TX0_P
RTM_10G4
_ TX0_N
RTM_10G6
_ TX0_P
RTM_10G6
_ TX0_N
RTM_10G3
_ TX1_P
RTM_10G3
_ TX1_N
RTM_10G5
_ TX1_P
RTM_10G5
_ TX1_N
RTM_10G4
_ TX1_P
RTM_10G4
_ TX1_N
RTM_10G6
_ TX1_P
RTM_10G6
_ TX1_N
RTM_10G3
_ TX2_P
RTM_10G3
_ TX2_N
RTM_10G5
_ TX2_P
RTM_10G5
_ TX2_N
RTM_10G4
_ TX2_P
RTM_10G4
_ TX2_N
RTM_10G6
_ TX2_P
RTM_10G6
_ TX2_N
RTM_10G3
_ TX3_P
RTM_10G3
_TX3_N
RTM_10G5
_ TX3_P
RTM_10G5
_ TX3_N
RTM_10G4
_ TX3_P
RTM_10G4
_ TX3_N
RTM_10G6
_ TX3_P
RTM_10G6
_ TX3_N
9
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
no connect
10
Figure 8-3: Zone 3 Connector, J33
1
6
D
C
B
A
Table 8-5: Zone 3 Connector, J33 Pin Assignments
Pin:
1
A:
B:
C:
D:
RTM_ENABLE
RTM_PP_PWRGD
RTM_MP_PWRGD
no connect
RTM_PS1_CONN*
RTM_HS_LED
PQ_CONSOLE_RX_M
PQ_CONSOLE_TX_M
no connect
RTM_PB_RST*
RTM_E_HANDLE
RTM_RST*
2
3
IPMB_RTM_SCL_BUFF
IPMB_RTM_SDA_BUFF
ground
4
3_3V_MP_RTM
ground
3_3V_MP_RTM
ground
5
ground
6
12V_RTM
12V_RTM
12V_RTM
12V_RTM
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Section 9
Management Processor Monitor
Project program, available under the GNU General Public License (GPL). For instructions on
how to obtain the source code for this GPL program, please visit http://www.emersonem-
This chapter describes the monitor’s basic features, operation, and configuration
sequences. This chapter also serves as a reference for the monitor commands and func-
tions.
COMMAND-LINE FEATURES
The ATCA-9305 monitor uses a command-line interface with the following features:
Auto-Repeat: After entering a command, you can re-execute it simply by pressing the ENTER or RETURN
key.
Command History: Recall previously entered commands using the up and down arrow keys.
TFTP Boot: You can use the TFTP protocol to load application images via Ethernet into the ATCA-9305’s
memory.
Auto-Boot: You can store specific boot commands in the environment to be executed automatically
after reset.
Flash Programming: You can write application images into flash via the U-Boot command line. The upper 1 MB at
the base of flash and 128 KB of each flash bank is reserved for the monitor and environment
the monitor and default environment variables.
At power-up or after a reset, the monitor runs diagnostics and reports the results in the
board according to the environment variables (see “MPC8548 Environment Variables” on
page 9-26). If the configuration indicates that autoboot is enabled, the monitor attempts to
load the application from the specified device. If the monitor is not configured for autoboot
or a failure occurs during power-up, the monitor enters normal command-line mode. Also,
the optional “e-keying” environment variable enables connections at power-up, for debug
purposes only, to the Update Channel and payload ports that go off the ATCA-9305. See
Table 9-7 for more information.
ATCA-9305.
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Management Processor Monitor: Command-Line Features
Figure 9-1: Example MPC8548 Monitor Start-up Display
U-Boot 1.1.4 (Jan 8 2007 - 16:07:48)1.0
Hardware initialization
CPU:
8548_E, Version: 2.0, (0x80390020)
Core: E500, Version: 2.0, (0x80210020)
Clock Configuration:
CPU: 999 MHz, CCB: 399 MHz,
DDR: 199 MHz, LBC: 49 MHz
Board: ATCA-9305 ATCA Blade
Emerson Network Power, Embedded Computing Inc.
cPLD Ver: 2
I2C:
ready
Clearing ALL of memory
................
DRAM: 512 MB
Testing Top 1M Area of DRAM........PASSED
Relocating code to RAM
FLASH: [4MB@e0000000][4MB@e1000000]8 MB
L2 cache: enabled
In:
Out:
Err:
serial
serial
serial
Ser#: 1096
Diags Mem:
Diags I2C:
Diags Flash:
BootDev: Socket
I-cache enabled
PASSED
PASSED
PASSED
D-cache enabled (write-through)
L2 cache enabled. (L2CTL: 0xa0000000)
(write-through)
IPMC: v0.1.1
DOC:
Net:
Turbo Mode
eTSEC1, eTSEC2
Monitor command prompt
ATCA-9305 (Mon 1.0)=>
This prompt is also displayed as an indication that the monitor has finished executing a
command or function invoked at the command prompt (except when the command loads
and jumps to a user application). The hardware product name (ATCA-9305), and current
software version number are displayed in the prompt.
Prior to the console port being available, the monitor will display a four-bit hexadecimal
the debug LED locations. In the event of a specific initialization error, the LED pattern will be
displayed and the board initialization will halt.
Table 9-1: Debug LED Codes
LED Code:
BOARD_PRE_INIT
SERIAL_INIT
Power-up Status:
start booting, setup BATs done
console init done
LED Value:
0x01
0x02
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Management Processor Monitor: Basic Operation
LED Code:
Power-up Status:
get processor and bus speeds done
RAM / ECC init done
LED Value:
0x03
CHECKBOARD
SDRAM_INIT
AFTER_RELOC
MISC_R
0x04
U-Boot relocated to RAM done
final init including Ethernet done
—
0x05
0x06
GONE_TO_PROMPT
0x00
BASIC OPERATION
The monitor performs various configuration tasks upon power-up or reset. This section
describes the monitor operation during initialization of the ATCA-9305 board. The flow-
environment variables).
Power-up/Reset Sequence
ating system or application software. At power-up or board reset, the monitor performs
hardware initialization, diagnostic routines, autoboot procedures, free memory initializa-
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Management Processor Monitor: Basic Operation
Figure 9-2: Power-up/Reset Sequence Flowchart
Power-up or Reset
U-Boot Monitor
Default Board Initialization
U-Boot Monitor
PCI Monarch, Enumerate
U-Boot Monitor
Configure Ethernet Switch
Initialize IPMC
Execute POST
Boot Caviums
Boot Cavium processor
according to
configuration parameters
U-Boot Monitor
Start Autoboot Sequence
(Boot Operating System)
Operating System Boot
Boot OS image
according to
configuration parameters
POST Diagnostic Results
The ATCA-9305 Power-On Self-Test (POST) diagnostic results are stored as a 32-bit value in
2
I C NVRAM at the offset 0x07F0-0x07FF. Each bit indicates the result of a specific test,
to specific tests.
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Management Processor Monitor: Monitor Recovery and
Table 9-2: POST Diagnostic Results–Bit Assignments
Bit:
0
Diagnostic Test:
SDRAM
Description:
Verify address and data lines are intact
Value:
1
Flash
Verify size and initialization of soldered
flash
2
I2C
Verify all local I2C devices are connected
to the I2C bus
3
4
5
6
Ethernet Switch
Reserved
Verify PCI communication with switch
PCIe enumeration skipped by user
0
1
Passed the test
Failure detected
PCIe Time-out
DOC Embedded Flash
Drive (EFD)
Verify presence and ability to access
configuration space of DOC
7
Cavium 1 Presence
Cavium 2 Presence
Reserved
Verify presence and ability to
communicate via PCI bus with Cavium 1
8
Verify presence and ability to
communicate via PCI bus with Cavium 2
9-31
Monitor SDRAM Usage
Monitor SDRAM usage is typically around 1 MB for monitor code and stack support. Please
note that the monitor stack grows downward from below where the monitor code resides
(in the upper 512 KB). The monitor C stack will typically not grow beyond 512 KB, therefore
the upper 1 MB of SDRAM is reserved for monitor use.
Note: The monitor has the ability to preserve (not overwrite) areas of memory defined by the pram environment
variable.
Caution: Any writes to these areas can cause unpredictable operation of the monitor.
!
MONITOR RECOVERY AND UPDATES
This section describes how to recover and/or update the monitor, given one or more of the
following conditions:
• If there is no console output, the monitor may be corrupted and need recovering (see
• If the monitor still functions, but is not operating properly, then you may need to reset
• If you are having Ethernet problems in the monitor, you may need to set the serial
number, since the MAC address is calculated from the serial number variable.
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Management Processor Monitor: Monitor Recovery and
Recovering the Monitor
Make sure that a monitor ROM device is installed in the PLCC socket on the ATCA-9305.
1
2
3
Verify there is a shunt on J9, across pins 1 and 2.
Issue the following command, where serial_number is the board’s serial number, at the
monitor prompt:
ATCA-9305 (1.0) => moninit serial_number
moninit will also reset environment variables to the default state.
4
To boot from soldered flash, power down the board and remove the shunt from J9, pins 1
and 2.
The monitor always resides in the top 512 KB block of NOR flash (banks 1 and 2) as shown in
Table 9-3: Monitor Address per Flash Device
Address Range (hex):
F3F8,0000-F400,0000
F3B8,0000-F3C0,0000
F3B7,0000-F3B7,1000
F3F7,0000-F3F7,1000
Device:
Monitor Location in Flash Bank2 (4 MB)
Monitor Location in Flash Bank1 (4 MB)
Environment Variables
Redundant Environment Variables
Resetting Environment Variables
To restore the monitor’s standard environment variables, execute the following commands
and insert the appropriate data in the italicized fields:
ATCA-9305 (1.0) => moninit serial_number noburn
Note: Press the ‘s’ key on the keyboard during reset to force the default environment variables to be loaded. See
“MPC8548 Environment Variables” for more information.
Optionally, save your settings:
ATCA-9305 (1.0) => saveenv
Updating the Monitor via TFTP
To update the monitor via TFTP, ensure that an appropriate VLAN is set up in the Ethernet
switch (see the ATCA-9305 Quick Start Guide, #10009110-xx) and execute the following
commands, inserting the appropriate data in the italicized fields:
If necessary, edit your network settings:
ATCA-9305 (1.0) => setenv ipaddr 192.168.1.100
ATCA-9305 (1.0) => setenv gatewayip 192.168.1.1
ATCA-9305 (1.0) => setenv netmask 255.255.255.0
ATCA-9305 (1.0) => setenv serverip 10.64.16.168
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Management Processor Monitor: Monitor Command
ATCA-9305 (1.0) => setenv ethport eTSEC1
Optionally, save your settings:
ATCA-9305 (1.0) => saveenv
TFTP the new monitor (binary) image to memory location 0x100000:
ATCA-9305 (1.0) => tftpboot 100000 path_to_file_on_tftp_server
Update the monitor:
ATCA-9305 (1.0) => moninit serial_number 100000
MONITOR COMMAND REFERENCE
This section describes the syntax and typographic conventions for the ATCA-9305 monitor
commands. Subsequent sections in this chapter describe individual commands, which fall
into the following categories: boot, memory, flash, environment variables, test, and other
commands.
Command Syntax
The monitor uses the following basic command syntax:
<Command> <argument 1> <argument 2> <argument 3>
• The command line accepts three different argument formats: string, numeric, and
symbolic. All command arguments must be separated by spaces with the exception of
argument flags, which are described below.
• Monitor commands that expect numeric arguments assume a hexadecimal base.
• All monitor commands are case sensitive.
• Some commands accept flag arguments. A flag argument is a single character that
begins with a period (.). There is no white space between an argument flag and a
command. For example, md.b 80000 is a valid monitor command, while md .b 80000
is not.
• Some commands may be abbreviated by typing only the first few characters that
uniquely identify the command. For example, you can type h instead of help. However,
commands cannot be abbreviated when accessing online help. You must type help and
the full command name.
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Management Processor Monitor: Boot Commands
Command Help
Access all available monitor commands by pressing the ? key or entering help. Access the
monitor online help for individual commands by typing help <command>. The full com-
mand name must be entered to access the online help.
Typographic Conventions
In the following command descriptions, text in Courier shows the command format.
Square brackets [ ] enclose optional arguments, and angled brackets < > enclose required
arguments. Italic type indicates a variable or field that requires input.
BOOT COMMANDS
The boot commands provide facilities for booting application programs and operating sys-
tems from various devices.
bootd
Execute the command stored in the bootcmd environment variable.
Definition: bootd
bootelf
The bootelf command boots from an ELF image in memory, where address is the load
address of the ELF image.
Definition: bootelf [ address ]
bootm
The bootm command boots an application image stored in memory, passing any entered
arguments to the called application. When booting a Linux kernel, arg can be the address of
an initrd image. If addr is not specified, the environment variable loadaddr is used as the
default.
Definition: bootm [addr [arg …]]
bootp
The bootp command boots an image via a network connection using the BootP/TFTP pro-
tocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr and
bootfile are used as the default.
Definition: bootp [loadAddress] [bootfilename]
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Management Processor Monitor: Boot Commands
To use network download commands (e.g., bootp, bootvx, rarpboot, tftpboot), the envi-
ment variables must be specified through the command line interface.
Table 9-4: Static IP Ethernet Configuration
Environment Variable:
ipaddr
Description:
Local IP address for the board
TFTP/NFS server address
Net mask
serverip
netmask
gatewayip
ethport
Gateway IP address
eTSEC1 default
ethaddr1
MAC address
1. Ensure that each MAC address on the network is unique.
bootv
The bootv command checks the checksum on the primary image (in flash) and boots it, if
valid. If it is not valid, it checks the checksum on the secondary image (in flash) and boots it,
if valid. If neither checksum is valid, the command returns back to the monitor prompt.
Definition: Verify bootup.
bootv
Write image to flash and update NVRAM.
bootv <primary|secondary> write <source> <dest> <size>
Update NVRAM based on image already in flash.
bootv <primary|secondary> update <source> <size>
Check validity of images in flash.
bootv <primary|secondary> check
bootvx
The bootvx command boots VxWorks® from an ELF image, where address is the load
address of the VxWorks ELF image. To use this command, the environment variables listed
Definition: bootvx [ address ]
dhcp
The dhcp command invokes a Dynamic Host Configuration Protocol (DHCP) client to obtain
IP and boot parameters by sending out a DHCP request and waiting for a response from a
server.
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Management Processor Monitor: Boot Commands
Definition: dhcp [loadaddress] [bootfilename]
To use the dhcp command, your DHCP server must be configured with the variables desig-
Table 9-5: DHCP Ethernet Configuration
Environment
Variable:
1
Description:
Value :
ipaddr
Local IP address for the board, configured by DHCP
e.g., 192.168.1.1
e.g., 192.168.1.2
serverip
TFTP/NFS server address value must be configured
after the DHCP IP address is acquired2
netmask
gatewayip
ethport
Net mask, obtained by DHCP
Gateway IP address, obtained by DHCP
eTSEC1 default
—
—
—
ethaddr3
autoload4
MAC address
00:80:F9:xx:xx:xx
no
Boot image from TFTP server after DHCP acquisition
1. Values for ethaddr, netdev and autoload are set by the user.
2. The value obtained by the DHCP server may not be applicable to your development application.
3. Ensure that each MAC address on the network is unique.
4. If autoload is not set or configured to “yes,” ensure that the DHCP provides proper information for
autoboot. If proper autoboot information is not provided, an error may occur.
rarpboot
The rarpboot command boots an image via a network connection using the RARP/TFTP
protocol. If loadaddress or bootfilename is not specified, the environment variables loadaddr
and bootfile are used as the default. To use this command, the environment variables listed
Definition: rarpboot [loadaddress] [bootfilename]
tftpboot
The tftpboot command loads an image via a network connection using the TFTP protocol.
The environment variable’s ipaddr and serverip are used as additional parameters to this
command. If loadaddress or bootfilename is not specified, the environment variables load-
addr and bootfile are used as the default. To use this command, the environment variables
The port used is defined by the ethport environment variable. If allis selected for ethport,
the TFTP process will cycle through each port until a connection is found or all ports have
failed.
Definition: tftpboot [loadaddress] [bootfilename]
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Management Processor Monitor: File Load Commands
FILE LOAD COMMANDS
The file load commands load files over the serial port.
loadb
The loadb command loads a binary file over the serial port. The command takes two
optional parameters:
offset: The address offset parameter allows the file to be stored in a location different than what is
indicated within the binary file by adding the value off to the file’s absolute address.
baudrate: The baudrate parameter allows the file to be loaded at baud instead of the monitor’s con-
sole baudrate.
The file is not automatically executed, the loadb command only loads the file into memory.
Definition: loadb [off] [baud]
loads
The loads command loads an S-Record file over the serial port. The command takes two
optional parameters:
offset: The address offset parameter allows the file to be stored in a location different than what is
indicated within the S-Record file by adding the value off to the file’s absolute address.
baudrate: The baudrate parameter allows the file to be loaded at baud instead of the monitor’s con-
sole baudrate.
The file is not automatically executed, the loads command only loads the file into memory.
Definition: loads [off] [baud]
MEMORY COMMANDS
The memory commands allow you to manipulate specific regions of memory. For some
memory commands, the data size is determined by the following flags:
Definition: The flag .b is for data in 8-bit bytes.
Definition: The flag .w is for data in 16-bit words.
Definition: The flag .l is for data in 32-bit long words.
These flags are optional arguments and describe the objects on which the command oper-
ates. If you do not specify a flag, memory commands default to 32-bit long words. Numeric
arguments are in hexadecimal.
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Management Processor Monitor: Memory Commands
cmp
The cmp command compares count objects between addr1 and addr2. Any differences are
displayed on the console display.
Definition: cmp [.b, .w, .l] addr1 addr2 count
cp
The cp command copies count objects located at the source address to the target address.
Note: If the target address is located in the range of the flash device, it will program the flash with count objects
from the source address. The cp command does not erase the flash region prior to copying the data. The flash
region must be manually erased using the erase command prior to using the cp command.
Definition: cp [.b, .w, .l] source target count
Example: In this example, the cp command is used to copy 0x1000, 32-bit values from address
0x100000 to address 0x80000.
=> cp 100000 80000 1000
find
The find command searches from base_addr to top_addr looking for pattern. For the find
command to work properly, the size of pattern must match the size of the object flag. The -a
option searches for the absence of the specified pattern.
Definition: find [.b, .w, .l] [-a] base_addr top_addr pattern
Example: In this example, the find command is used to search for the 32-bit pattern 0x12345678 in
the address range starting at 0x40000, and ending at 0x80000.
=> find.1 40000 80000 12345678
Searching from 0x00040000 to 0x00080000
Match found: data = 0x12345678 Adrs = 0x00050a6c
=>
md
The command md displays the contents of memory starting at address. The number of
objects displayed can be defined by an optional third argument, # of objects. The memory’s
numerical value and its ASCII equivalent is displayed.
Definition: md [.b, .w, .l] address [# of objects]
Example: In this example, the md command is used to display thirty-two 16-bit words starting at the
physical address 0x80000.
=> md.w 80000 20
00080000: ffff ffff ffff ffff ffff ffff ffff ffff
00080010: ffff ffff ffff ffff ffff ffff ffff ffff
00080020: ffff ffff ffff ffff ffff ffff ffff ffff
................
................
................
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Management Processor Monitor: Memory Commands
00080030: ffff ffff ffff ffff ffff ffff ffff ffff
................
mm
The mm command modifies memory one object at a time. Once started, the command line
prompts for a new value at the starting address. After a new value is entered, pressing
ENTER auto-increments the address to the next location. Pressing ENTER without entering a
new value leaves the original value for that address unchanged. To exit the mm command,
enter a non-valid hexadecimal value (such as x) followed by ENTER.
Definition: mm [.b, .w, .l] address
Example: In this example, the mm command is used to write random 8-bit data starting at the physi-
cal address 0x80000.
=> mm.b 80000
00080000: ff ? 12
00080001: ff ? 23
00080002: ff ? 34
00080003: ff ? 45
00080004: ff ?
00080005: ff ? x
=> md.b 80000 6
00080000: 12 23 34 45 ff ff
=>
.#4E
nm
The nm command modifies a single object repeatedly. Once started, the command line
prompts for a new value at the selected address. After a new value is entered, pressing
ENTER modifies the value in memory and then the new value is displayed. The command
line then prompts for a new value to be written at the same address. Pressing ENTER with-
out entering a new value leaves the original value unchanged. To exit the nm command,
enter a non-valid hexadecimal value (such as x) followed by ENTER.
Definition: nm [.b, .w, .l] address
mw
The command mw writes value to memory starting at address. The number of objects mod-
ified can be defined by an optional fourth argument, count.
Definition: mw [.b, .w, .l] address value [count]
Example: In this example, the mw command is used to write the value 0xabba three times starting at
the physical address 0x80000.
=> mw.w 80000 abba 3
=> md 80000
00080000: abbaabba abbaffff ffffffff ffffffff
00080010: ffffffff ffffffff ffffffff ffffffff
................
................
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Management Processor Monitor: Flash Commands
00080020: ffffffff ffffffff ffffffff ffffffff
00080030: ffffffff ffffffff ffffffff ffffffff
00080040: ffffffff ffffffff ffffffff ffffffff
00080050: ffffffff ffffffff ffffffff ffffffff
00080060: ffffffff ffffffff ffffffff ffffffff
00080070: ffffffff ffffffff ffffffff ffffffff
................
................
................
................
................
................
FLASH COMMANDS
The flash commands affect the StrataFlash devices on the ATCA-9305 circuit board. There
accessed by:
• the individual bank (1, 2, 3 or 4), or
• the address, where both banks are regarded as one contiguous address space
The following flash commands access the individual flash bank as flash bank 1. To access the
individual sectors within each flash bank, the sector numbers start at 0 and end at one less
than the total number of sectors in the bank. For a flash bank with 128 sectors, the follow-
ing flash commands access the individual sectors as 0 through 127.
cp
The cp command can be used to copy data into the flash device. For the cp command syn-
tax, refer to “Memory Commands” on page 9-11.
erase
The erase command erases the specified area of flash memory.
Definition: Erase all of the sectors in the address range from start to end.
erase start end
Erase all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
erase N:SF[-SL]
Erase all of the sectors in flash bank # N.
erase bank N
Erase all of the sectors in all of the flash banks.
erase all
flinfo
The flinfo command prints out the flash device’s manufacturer, part number, size, number
of sectors, and starting address of each sector.
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Management Processor Monitor: EEPROM/I2C Commands
Definition: Print information for all flash memory banks.
flinfo
Print information for the flash memory in bank # N.
flinfo N
protect
The protect command enables or disables the flash sector protection for the specified flash
sector. Protection is implemented using software only. The protection mechanism inside
the physical flash part is not being used.
Definition: Protect all of the flash sectors in the address range from start to end.
protect on start end
Protect all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
protect on N:SF[-SL]
Protect all of the sectors in flash bank # N.
protect on bank N
Protect all of the sectors in all of the flash banks.
protect on all
Remove protection on all of the flash sectors in the address range from start to end.
protect off start end
Remove protection on all of the sectors SF (first sector) to SL (last sector) in flash bank # N.
protect off N:SF[-SL]
Remove protection on all of the sectors in flash bank # N.
protect off bank N
Remove protection on all of the sectors in all of the flash banks.
protect off all
EEPROM/I2C COMMANDS
This section describes commands that allow you to read and write memory on the serial
2
EEPROMs and I C devices.
eeprom
The eeprom command reads and writes from the EEPROM. For example:
eeprom read 53 100000 1800 100
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Management Processor Monitor: EEPROM/I2C Commands
reads 100 bytes from offset 0x1800 in serial EEPROM 0x53 (right-shifted 7-bit address) and
places it in memory at address 0x100000.
Definition: Read/write cnt bytes from devaddr EEPROM at offset off.
eeprom read devaddr addr off cnt
eeprom write devaddr addr off cnt
icrc32
The icrc32 computes a CRC32 checksum.
Definition: icrc32 chip address[.0, .1, .2] count
iloop
The iloop command reads in an infinite loop on the specified address range.
Definition: iloop chip address[.0, .1, .2] [# of objects]
imd
2
The imd command displays the primary I C bus memory. For example:
imd 53 1800.2 100
2
displays 100 bytes from offset 0x1800 of I C device 0x53 (right-shifted 7-bit address). The
.2at the end of the offset is the length, in bytes, of the offset information sent to the
device. The serial EEPROMs all have two-byte offset lengths. The Real-Time Clock (RTC) has
a one-byte offset length. The temperature sensors have zero-byte offset lengths.
Definition: imd chip address[.0, .1, .2] [# of objects]
imm
2
The imm command modifies the primary I C memory and automatically increments the
address.
Definition: imm chip address[.0, .1, .2]
imw
The imw command writes (fills) memory.
Definition: imw chip address[.0, .1, .2] value [count]
inm
2
The inm command modifies I C memory, reads it, and keeps the address.
Definition: inm chip address[.0, .1, .2]
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Management Processor Monitor: IPMC Commands
iprobe
2
The iprobe command probes to discover valid primary I C bus chip addresses.
Definition: iprobe
IPMC COMMANDS
IPMI Baseboard Management Controller (BMC) watchdog is supported and serviced
throughout the monitor boot process. The BMC watchdog is disabled if the monitor goes to
the monitor prompt.
bootdev
The bootdev command gets or sets the initial boot bank. Get prints out the flash bank set as
initial boot device.
Definition: bootdev get
The IPMC sets the hardware strapping for the initial boot device.
bootdev set <bank>
Where <bank> is either b0 or b1 for the corresponding flash bank, or b3 to boot from socket
and if a shunt is installed on J9 [1:2].
fru
The fru command opens, closes, saves, sets, shows, dumps, and loads fru data to and from
the IPMC.
Definition: fru <command> [ arg1 arg2 … ]
command := [ open | close | save | set | show | dump | load | create ]
fru open <id>
fru close
fru save
fru set <section [chassis|board|product]><field><value>
fru set <section> <field> <value>
section := [ chassis | board | product ]
fru set chassis <field> <value>
field := [ type | part | serial ]
fru set board <field> <value>
field := [ date | maker | name | serial | part | file ]
fru set product <field> <value>
field := [ maker | name | part | version |serial | asset | file ]
fru show
fru dump <address>
fru load <address><size>
Set data in the internal use area.
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fru set internal <source addr> <internal use offset> <count>
The fru create command loads a default fru image to a blank fru device.
fru create <id> default <product name>
fru create <id> <address> <size> <product name>
fruinit
The fruinit command initializes the following fru data fields: part number, build date, and
serial number in the board and product sections.
Definition: fruinit <fru id> <part number> <build date> [ serial number ]
fruled
The fruled command allows the application programmer to get the status of the red out-of-
service LED or to turn the LED on or off when an application fails to load.
Definition: fruled get <fru id> <led id> <led state> <led function (on/off)> <on time> <color>
fruled set <fru id> <led id> <led function (on/off)> <on time> <color>
Example: Turns the red out-of-service LED on.
fruled set 0 1 0xff 0 2
Turns the red out-of-service LED off.
fruled set 0 1 0 0 2
ipmchpmfw
The ipmchpmfw command restores the previous IPMC firmware from the backup IPMC
firmware stored in the controller. The upgrade argument upgrades the IPMC firmware with
the upgrade image held in memory.
Definition: ipmchpmfw [restore] [upgrade <source address>]
sensor
The sensor command probes, reads, and prints the sensor information from the IPMI.
Definition: sensor [probe|read|dump]
Sensor probe prints out each sensor number and name.
sensor probe <sensor number>
Sensor read prints out the sensor reading for sensor.
sensor read <sensor number>
Sensor dump prints out the raw Sensor Data Record (SDR) information for sensor.
sensor dump <sensor number>
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Management Processor Monitor: Environment Parameter
ENVIRONMENT PARAMETER COMMANDS
The monitor uses on-board, non-volatile memory for the storage of environment parame-
ters. Environment parameters are stored as ASCII strings with the following format.
<Parameter Name>=<Parameter Value>
Some environment variables are used for board configuration and identification by the
monitor. The environment parameter commands deal with the reading and writing of these
environment variables.
Redundant environment parameters allow you to store a “backup” copy of environment
parameters should they ever become corrupt. The redundant environment parameters are
only used if the main parameters are corrupt.
To save environment variables:
1
Use moninit to save default environment variables to both primary and secondary
environment parameters.
2
3
Use saveenv to save to the primary environment variables.
Set the next save to the secondary image.
printenv
The printenv command displays all of the environment variables and their current values to
the display.
Definition: Print the values of all environment variables.
printenv
Print the values of all environment variable (exact match) ‘name’.
printenv name …
saveenv
The saveenv command writes the environment variables to non-volatile memory.
Definition: saveenv
setenv
The setenv command adds new environment variables, sets the values of existing environ-
ment variables, and deletes unwanted environment variables.
Definition: Set the environment variable name to value or adds the new variable name and value to the
environment.
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Management Processor Monitor: Test Commands
setenv name value
Removes the environment variable name from the environment.
setenv name
TEST COMMANDS
The commands described in this section perform diagnostic and memory tests.
diags
The diags command runs the Power-on Self-test (POST).
Definition: diags
mtest
The mtest command performs a simple SDRAM read/write test.
Definition: mtest [start [end [pattern]]]
um
The um command is a destructive memory test. Press the ‘q’ key to quit this test; the moni-
tor completes running the most recent iteration, and exits to the default prompt after dis-
playing cumulative results for the completed iterations.
Definition: um [.b, .w, .l] base_addr [top_addr]
OTHER COMMANDS
This section describes all the remaining commands supported by the ATCA-9305 monitor.
autoscr
The autoscr command runs a script, starting at address addr, from memory.
A valid autoscr header must be present.
Definition: autoscr [addr]
base
The base command prints or sets the address offset for memory commands.
Definition: Displays the address offset for the memory commands.
base
Sets the address offset for the memory commands to off.
base off
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Management Processor Monitor: Other Commands
bdinfo
The bdinfo command displays the Board Information Structure.
Definition: bdinfo
coninfo
The coninfo command displays the information for all available console devices.
Definition: coninfo
crc32
The crc32 command computes a CRC32 checksum on count bytes starting at address.
Definition: crc32 address count
date
The date command will set or get the date and time, and reset the RTC device.
Definition: Set the date and time.
date [MMDDhhmm[[CC]YY][.ss]]
Display the date and time.
date
Reset the RTC device.
date reset
echo
The echo command echoes args to console.
Definition: echo [args..]
enumpci
The enumpci command enumerates the PCI bus (when the hardware is the PCI Root Com-
plex in the system).
Definition: enumpci
go
The go command runs an application at address addr, passing the optional argument arg to
the called application.
Definition: go addr [arg…]
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Management Processor Monitor: Other Commands
help
The help (or ?) command displays the online help. Without arguments, all commands are
displayed with a short usage message for each. To obtain more detailed information for a
specific command, enter the desired command as an argument.
Definition: help [command …]
iminfo
The iminfo command displays the header information for an application image that is
loaded into memory at address addr. Verification of the image contents (magic number,
header, and payload checksums) are also performed.
Definition: iminfo addr [addr …]
isdram
The isdram command displays the SDRAM configuration information (valid chip values
range from 50 to 57).
Definition: isdram addr
loop
The loop command executes an infinite loop on address range.
Definition: loop [.b, .w, .l] address number_of_objects
memmap
The memmap command displays the board’s memory map layout.
Definition: memmap
moninit
The moninit command resets the NVRAM and serial number, and writes the monitor to
flash. The ATCA-9305 must be booted from the boot socket for this command to function in
the default state. The proper region of flash memory will be unlocked and erased prior to
copying the monitor software into it.
The command flags, .1 or .2, force the monitor to be programmed to a single (.1) bank of
flash or dual (.2) banks of flash. If the command flags are not used, then moninit checks for
the number of banks of flash. If there are two banks of flash, then moninit automatically
programs both banks for redundancy. Also, the serial number can be obtained from the fru
data if “fru” is used as a parameter.
Definition: Initialize environment variables and serial number in NVRAM and copy the monitor from the
socket to NOR (soldered) flash.
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Management Processor Monitor: Other Commands
moninit[.1, .2] <serial# or “fru”>
Initialize environment variables and serial number in NVRAM but do not update the monitor
in NOR flash.
moninit[.1, .2] <serial# or “fru”> noburn
Initialize environment variables and serial number in NVRAM and copy the monitor from
<src_address> into NOR flash.
moninit[.1, .2] <serial# or “fru”> <src_address>
pci
The pci command enumerates the PCI bus. It displays enumeration information about each
detected device. The pci command allows you to display values for and access the PCI Con-
figuration Space.
Definition: Display a short or long list of PCI devices on the bus specified by bus.
pci [bus] [long]
Show the header of PCI device bus.device.function.
pci header b.d.f
Display the PCI configuration space (CFG).
pci display[.b, .w, .l] b.d.f [address] [# of objects]
Modify, read, and keep the CFG address.
pci next[.b, .w, .l] b.d.f address
Modify, automatically increment the CFG address.
pci modify[.b, .w, .l] b.d.f address
Write to the CFG address.
pci write[.b, .w, .l] b.d.f address value
phy
The phy command reads or writes to the contents of the PHY registers. The values changed
via this command are not persistent and clear after a hard or soft reset. The port options are
all, eTSEC1, eTSEC2, and base1 and base2 via the switch. “R” reads the register contents at
the address specified. “W” writes the address value to the register address specified. “A”
reads the contents of all registers.
Definition: phy [port] [R|W|A] (address) (value)
Example: The following is an example of a read from register address 0x1a.
phy eTSEC2 r 0x1a
The following is an example of a write to register address 0x1a where 0 is the data to write.
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Management Processor Monitor: Other Commands
phy eTSEC2 w 0x1a 0
ping
The ping command sends a ping over Ethernet to check if the host can be reached. The port
used is defined by the ethport environment variable. If allis selected for ethport, the ping
process cycles through each port until a connection is found or all ports have failed.
Definition: ping host
reset
The reset command performs a hard reset of the CPU by writing to the reset register on the
board. Without any arguments, the ATCA-9305 CPU is reset.
Definition: reset
run
The run command runs the commands in an environment variable var.
Definition: run var [ … ]
Use $ for variable substitution; the syntax “$(variable_name)” should be used for variable
expansion.
Example: => setenv cons_opts console=tty0 console=ttyS0,\$(baudrate)
=> printenv cons_opts cons_opts=console=tty0 console=ttyS0,$(baudrate)
Use the \ character to escape execution of the $ as seen in the setenv command above. In
this example, the value for baudrate will be inserted when cons_opts is executed.
script
The script command runs a list of monitor commands out of memory. The list is an ASCII
string of commands separated by the ; character and terminated with the ;; charac-
ters. <script address> is the starting location of the script.
Note: A script is limited to 1000 characters.
Definition: script <script address>
showmac
The showmac command displays the Processor MAC addresses assigned to each Ethernet
port.
Definition: showmac
showpci
The showpci command scans the PCI bus and lists the base address of the devices.
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Management Processor Monitor: Other Commands
Definition: showpci
sleep
The sleep command executes a delay of N seconds.
Definition: Delay execution for N seconds (N is a decimal value).
sleep N
switch_reg
The switch_reg command reads or writes to the Ethernet core switch registers. The values
changed via this command are not persistent and clear after a hard or soft reset. Option val-
ues are as follows: switch (core or fp), port (0 - 25), block (1-7), and sub-block (0-15). “R”
reads the register contents at the address specified. “W” writes the address value to the reg-
ister address specified.
Definition: switch_reg [switch] [port op | block sub-block op [R|W]] (address) (value)
Example: The following is an example of a read of register address 0x1a.
switch_reg core 0 r 0x1a
The following is an example of a write to register address 0x1a where 0 is the data to write.
switch_reg core 0 w 0x1a 0
version
The version command displays the monitor’s current version number.
Definition: version
vlan
The vlan command creates one or more new VLANs using vid as the VLAN identification
(VID) value and deletes one or more existing VLANs whose VLAN ID matches the VLAN ID
value vid. These variables are set using a comma-separated list of port names. This com-
mand sets an untagged port-based VLAN and the VLAN table entry with the port’s default
VID. In this configuration, each port is assigned to one VLAN.
Definition: vlan add <vid1>=portlist1> <vid2>=<portlist2>…
vlan delete <vid1> <vid2>…
vlan show
Example: To create VLAN 1 on the core switch:
vlan add 1=14,15
To delete VLAN 1 on the core switch:
vlan delete 1
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Management Processor Monitor: MPC8548 Environment
MPC8548 ENVIRONMENT VARIABLES
Press the ‘s’ key on the keyboard during reset to force the default monitor environment vari-
ables to be loaded during hardware initialization but before diagnostic testing.
Table 9-6: Standard Environment Variables
Default
Variable:
Value:
Description:
baudrate
115200
Console port baud rate
Valid rates: 9600, 14400, 19200, 38400, 57600, 115200
bmc_wd_timeout
-1
This sets the time-out in seconds for the BMC watchdog
before booting the OS. If set to -1, then the BMC watchdog
is disabled before booting the OS.
Valid options: -1, 1-65535
bootcmd
bootdelay
" "
1
Command to execute when auto-booting or executing the
‘bootd’ command
Choose the number of seconds the Monitor counts down
before booting user application code
Valid options: time in seconds, -1 to disable autoboot
bootfile
" "
Path to boot file on server (used with TFTP)—set this to
“path/file.bin” to specify filename and location of the file to
load.
bootretry
-1
Set the number of seconds the Monitor counts down before
booting user application code (used only with autoboot). If
the boot commands fails, it will try again after bootretry
seconds.
Valid options: time in seconds, -1 to disable bootretry
bootstopkey
clearmem
h
Press during power-up/reset initialization to terminate the
monitor autoboot sequence and go to the monitor prompt.
on
Select whether to clear unused SDRAM (memory used by
monitor is excluded) on power-up and reset.
Valid options: on, off
dcache
on
on
off
Enables the processor L1 data cache
Valid options: on, off
ecc
Enable ECC initialization—all of memory is cleared during
ECC initialization. Valid options: on, off
ecc_1bit_report
Select the reporting of single bit, correctable ECC errors to
the console (errors of 2 or more bits are always reported)
Valid options: on, off
ethaddr
00:80:F9:
97:00:00-
00:80:F9:
97:FF:FF
ATCA-9305 board Ethernet address for TSEC_1 port, the last
digits are the board serial number in hex.
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Management Processor Monitor: MPC8548 Environment
Default
Variable:
Value:
Description: (continued)
eth1addr
00:80:F9:
98:00:00-
00:80:F9:
98:FF:FF
ATCA-9305 board Ethernet address for TSEC_2 port, the last
digits are the board serial number in hex.
fru_id
undefined
Corresponds to ATCA-9305 processing resources
Valid options: Not defined in default configuration—
reported at bootup from the IPMC
gatewayip
hostname
0.0.0.0
Select the network gateway machine IP address
Target hostname
EMERSON
_ATCA-
9305
icache
on
Enables the processor L1 instruction cache
Valid options: on, off
ipaddr
0.0.0.0
on
Board IP address
l2cache
Enables the L2 cache
Valid options: on, off
loadaddr
model
ncip
0x100000
Define the address to download user application code (used
with TFTP)
ATCA-
9305
Board model number
undefined
Sets the IP address and the destination port, format is
<ip_addr>;<port>
netmask
0.0.0.0
on
Board sub-network mask
powerondiags
Turns POST diagnostics on or off after power-on/reset
Valid options: on, off
preboot
undefined
Command to execute immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-
boot command entering the interactive mode
rootpath
eng/
Path name of the NFS’ server root file system
emerson/
serial#
xxxxx
Board serial number
Boot server IP address
serverip
tftp_port
0.0.0.0
eTSEC_1
Selects which Ethernet port will be used for tftp
Valid options: eTSEC_1, eTSEC_2
The monitor supports optional environment variables that enable additional functionality.
sets the standard environment variables to the default values. All optional environment vari-
ables are removed after moninit. However, it can clear all optional variables.
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Management Processor Monitor: Troubleshooting
Table 9-7: Optional Environment Variables
1
Variable :
Description:
app_lock_base
Assigns where to start block lock protection at the base of NOR (soldered) flash.
If assigned region does not fall within the NOR flash area, no user/application
locking will occur, except for the monitor block-locking protection.
app_lock_size
bootverifycmd
Size of user NOR (soldered) flash protection area.
Sets the U-Boot boot command that is used to execute the primary and
secondary application images when using the bootv command. If not defined,
bootv uses the U-Boot go command as the default.
carrier_num
This is a slot within a shelf defined by the zone 1 hardware address
corresponding to the logical slot address.
e_keying
Determines whether switch ports should be configured.
pci_memsize
Sets the amount of SDRAM memory made available on the PCI bus. The
minimum setting is 16 megabytes. If not set, 128 MB of SDRAM are available
over PCI. This parameter takes a hex value.
Valid options: all, size in hex (0x8000000=128 MB)
pram
This memory region is at the very top of memory and can be reserved—not to be
cleared on start-up or reset. Default size of the protected memory region is 0.
pram is defined in kilobytes and is a base 10 number. The smallest allowable size
is 4 (4 KB) and the largest recommended size is 32768 (32 MB). pram should be 4
KB aligned, otherwise U-Boot will round pram to the next 4 KB size.
sec_bootargs
shelf_addr
Sets the boot arguments that are passed into the secondary application images
when using the bootv command. If not defined, bootv will pass the bootargs
configuration parameters into both the primary and secondary application
images.
ATCA chassis shelf address provided by shelf-manager
Not defined in default configuration—reported at bootup from the IPMC
1. The moninit command does not initialize these variables. Each parameter is only defined if a change
from the default setting is desired and is not defined after initialization of the environment variables.
TROUBLESHOOTING
To bypass the full board initialization sequence, attach a terminal to the console located on
the front of the ATCA-9305. Configure the terminal parameters to be:
9600 bps, no parity, 8 data bits, 1 stop bit
Reset the ATCA-9305 while holding down the ‘s’ key. Pressing the ‘s’ key forces a configura-
tion based on default environment variables.
DOWNLOAD FORMATS
The ATCA-9305 monitor supports binary and Motorola® S-Record download formats, as
described in the following sections.
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Management Processor Monitor: Download Formats
Binary
The binary formats (and associated commands) include:
• Executable binary files (go)
• VxWorks and QNX® ELF (bootm, bootvx, or bootelf)
• Compressed (gzipped) VxWorks and QNX ELF (bootm)
• Linux kernel images (bootm)
• Compressed (gzipped) Linux kernel images (bootm)
Motorola S-Record
S-Record download uses the standard Motorola S-Record format. This includes load
address, section size, and checksum all embedded in an ASCII file.
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Section 10
Acronyms
Advanced Mezzanine Card
American Standard Code for Information Interchange
Advanced Telecom Computing Architecture or AdvancedTCA
Baseboard Management Controller
Common I/O (RLDRAM)
AMC
ASCII
ATCA
BMC
CIO
Command code
Cmd
CPU
CRC
CSA
DDR
EC
Central Processing Unit
Cyclic Redundancy Code
Canadian Standards Association
Double Data Rate
European Community
Error-correcting Code
ECC
EIA
Electronic Industries Alliance
Electromagnetic Compatibility
Electrostatic Discharge
EMC
ESD
ETSI
EXP
FCC
FRU
GbE
GNU
GPL
European Telecommunications Standards Institute
Extreme Processor
Federal Communications Commission
Field Replaceable Unit
Gigabit Ethernet
GNU’s Not Unix
General Public License
2
Inter-integrated Circuit
I C
International Electrotechnical Commission
Intelligent Platform Management Bus
Intelligent Platform Management Interface
In-system Programmable
IEC
IPMB
IPMI
ISP
In-target Probe
ITP
Joint Test Action Group
JTAG
KCS
LED
Keyboard Controller Style
Light-emitting Diode
Low Pin Count
LPC
Logical Unit Number
LUN
MAC
NEBS
netFn
NSP
Medium/media Access Control/controller
Network Equipment-Building System
Network Function Code
Network Services Processor
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Acronyms: (continued)
Original Equipment Manufacturer
OEM
PCI
Peripheral Component Interconnect
PCI Express
PCIe
Physical Interface
PHY
Programmable Logic Device
Power-on Self Test
PLD
POST
RLDRAM
RMA
SCP
Reduced Latency Dynamic Random Access Memory
Return Merchandise Authorization
Secure Communications Processor
Sensor Data Record
SDR
Synchronous Dynamic Random Access Memory
System Event Log
SDRAM
SEL
Serializer/deserializer
SERDES
SIO
Separate I/O (RLDRAM)
Small-outline Clocked Dual In-line Memory
System Packet Interface level 4 phase 2
Serial Read Only Memory
SO-CDIMM
SPI-4.2
SROM
TBD
To Be Determined
Universal Asynchronous Receiver/transmitter
Underwriters Laboratories
Universal Serial Bus
UART
UL
USB
Very Low Profile
VLP
10 Gigabit Attachment Unit Interface
XAUI
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Index
A
E
L
air flow rate . . . . . . . . . . . . . . . . . . . 2-9
environment parameter commands,
equipment for setup. . . . . . . . . . . . 2-8
Ethernet
LEDs
B
binary download format . . . . . . . .9-29
block diagram
general system . . . . . . . . . . . . . . 1-3
boot redirection
M
management complex
RJ45 connectors . . . . . . . . . . . . . 6-4
console port . . . . . . . . . . . . . . . 4-10
mean time between failures (MTBF)1-4
memory
memory map
Cavium NVRAM . . . . . . . . . . . . 3-10
monitor
flow diagram. . . . . . . . . . . . . . .7-42
F
features
components . . . . . . . . . . . . . . . . 1-1
file load commands, monitor . . . . 9-11
flash
management devices. . . . . . . . . 4-7
C
caution statements
front panel EMI . . . . . . . . . . . . . . 2-2
over-clocking Cavium . . . . . . . .5-11
static protection . . . . . . . . . . . . . 2-1
Cavium complexes
CN5860 features. . . . . . . . . . . . . 3-1
PLD registers. . . . . . . . . . . . . . .3-10
reset diagram . . . . . . . . . . . . . . . 3-4
SPI-4.2 interconnect . . . . . . . . .3-10
comments and suggestions . . . . .2-13
compliance . . . . . . . . . . . . . . . . . . . 1-4
component map
connectors
J30, J31, J33. . . . . . . . . . . . . . . . . 8-3
G
H
environment parameter commands
file load commands . . . . . . . . . 9-11
flash commands. . . . . . . . . . . . 9-14
memory commands. . . . . . . . . 9-11
other commands . . . . . . . . . . . 9-20
I
I2C addresses . . . . . . . . . . . . . . . . . 4-9
installation of the board . . . . . . . . . 2-8
IPMI
completion codes. . . . . . . . . . . . 7-4
entity IDs and instances . . . . . . 7-46
FRU information . . . . . . . . . . . . 7-50
message bridging. . . . . . . . . . . . 7-7
network function codes . . . . . . . 7-2
request/response messages. . . . 7-5
vendor commands . . . . . . . . . . 7-24
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Index (continued)
test commands. . . . . . . . . . . . .9-20
troubleshooting . . . . . . . . . . . .9-28
typographic conventions . . . . . . 9-8
monitor commands
switch_reg . . . . . . . . . . . . . . . . 9-25
ipmchpmfw . . . . . . . . . . . . . . .9-18
N
notation conventions . . . . . . . . . . . 1-6
P
S
PCI
specifications
device interrupts and ID . . . . . . . 4-8
product repair. . . . . . . . . . . . . . . . 2-12
switches
R
references and data books . . . . . . . 1-6
registers
Address7-0 . . . . . . . . . . . . . . . . 3-12
Data 15-8 . . . . . . . . . . . . . . . . . 3-11
Data 23-16 . . . . . . . . . . . . . . . . 3-11
Data 31-24 . . . . . . . . . . . . . . . . 3-10
T
tables, list of . . . . . . . . . . . . . . . . . .iv-xi
technical support . . . . . . . . . . . . . 2-11
test commands, monitor . . . . . . . 9-20
troubleshooting
i-2
ATCA-9305 User’s Manual
10009109-01
Notes
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10009109-01
ATCA-9305 User’s Manual
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