Cypress MoBL USB CY7C68053 User Manual

CY7C68053  
MoBL-USB™ FX2LP18 USB Microcontroller  
1.0  
CY7C68053 Features  
• USB 2.0 – USB-IF High-Speed and Full-Speed Compliant  
(TID# 40000188)  
• Integrated, industry standard enhanced 8051  
— 48 MHz, 24 MHz, or 12 MHz CPU operation  
— Four clocks per instruction cycle  
— Three counter/timers  
— Expanded interrupt system  
— Two data pointers  
• Single-chip integrated USB 2.0 transceiver, smart SIE, and  
enhanced 8051 microprocessor  
• Ideal for mobile applications (cell phone, smart phones,  
PDAs, MP3 players)  
— Ultra low power  
— Suspend current: 20 µA (typical)  
• Software: 8051 code runs from:  
• 1.8V core operation  
• 1.8V - 3.3V IO operation  
• Vectored USB interrupts and GPIF/FIFO interrupts  
— Internal RAM, which is loaded from EEPROM  
• 16 kBytes of on-chip Code/Data RAM  
• Separate data buffers for the Set-up and Data portions of a  
CONTROL transfer  
• Four programmable BULK/INTERRUPT/ISOCHRONOUS  
endpoints  
2
• Integrated I C™ controller, runs at 100 or 400 kHz  
• Four integrated FIFO’s  
— Buffering options: double, triple, and quad  
• Additional programmable (BULK/INTERRUPT) 64-byte  
endpoint  
— Integrated glue logic and FIFO’s lower system cost  
— Automatic conversion to and from 16-bit buses  
— Master or slave operation  
• 8- or 16-bit external data interface  
— Uses external clock or asynchronous strobes  
Easy interface to ASIC and DSP IC’s  
• Available in Industrial temperature grade  
• Available in one lead-free package with up to 24 GPIO’s  
— 56-pin VFBGA (24 GPIO’s)  
• Smart Media Standard ECC generation  
• GPIF (General Programmable Interface)  
— Allows direct connection to most parallel interface  
— Programmable waveform descriptors and configuration  
registers to define waveforms  
— SupportsmultipleReady(RDY)inputsandControl(CTL)  
outputs  
Block Diagram  
High-performance micro  
using standard tools  
24 MHz  
Ext. XTAL  
with lower-power options  
MoBL-USB FX2LP18  
2
I
C
/0.5  
/1.0  
/2.0  
8051 Core  
12/24/48 MHz,  
Four Clocks/Cycle  
x20  
PLL  
Master  
VCC  
Abundant I/O  
Additional I/Os (24)  
1.5K  
Connected for  
Full-Speed  
D+  
D–  
General  
Programmable I/F  
To Baseband processors/  
Application processors/  
ASICS/DSPs  
GPIF  
USB  
2.0  
XCVR  
CY  
Smart  
USB  
1.1/2.0  
Engine  
16 KB  
RAM  
RDY (2)  
CTL (3)  
ECC  
Integrated  
Full- and High-speed  
XCVR  
Up to 96 MBytes/sec  
Burst Rate  
4 KB  
FIFO  
8/16  
Enhanced USB Core  
Simplifies 8051 Code  
“Soft Configuration”  
Easy Firmware Changes  
FIFO and Endpoint Memory  
(master or slave operation)  
Cypress Semiconductor Corporation  
Document # 001-06120 Rev *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 9th 2006  
CY7C68053  
Table 3-1. Special Function Registers  
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x  
IOA  
9x  
IOB  
Ax  
IOC  
Bx  
Cx  
Dx  
Ex  
Fx  
IOD  
SCON1  
SBUF1  
PSW  
ACC  
B
SP  
EXIF  
INT2CLR  
IOE  
DPL0  
DPH0  
DPL1  
DPH1  
DPS  
MPAGE  
OEA  
OEB  
OEC  
OED  
OEE  
PCON  
TCON  
TMOD  
TL0  
SCON0  
SBUF0  
IE  
IP  
T2CON  
EICON  
EIE  
EIP  
AUTOPTRH1  
AUTOPTRL1  
Reserved  
EP2468STAT  
EP24FIFOFLGS  
EP68FIFOFLGS  
EP01STAT  
GPIFTRIG  
RCAP2L  
RCAP2H  
TL2  
TL1  
TH0  
TH1  
AUTOPTRH2  
AUTOPTRL2  
Reserved  
GPIFSGLDATH  
GPIFSGLDATLX  
TH2  
CKCON  
AUTOPTRSET-UP GPIFSGLDATLNOX  
2
plugged in, with no hint that the initial download step has  
occurred.  
3.3  
I C™ Bus  
2
FX2LP18 supports the I C bus as a master only at 100-/400-  
KHz. SCL and SDA pins have open-drain outputs and  
hysteresis inputs. These signals must be pulled up to either  
Two control bits in the USBCS (USB Control and Status)  
register control the ReNumeration process: DISCON and  
RENUM. To simulate a USB disconnect, the firmware sets  
DISCON to 1. To reconnect, the firmware clears DISCON to 0.  
2
V
or V  
, even if no I C device is connected.(Connecting  
CC  
CC_IO  
to V  
may be more convenient.)  
CC_IO  
Before reconnecting, the firmware sets or clears the RENUM  
bit to indicate whether the firmware or the Default USB Device  
handles device requests over endpoint zero: if RENUM = 0,  
the Default USB Device handles device requests; if  
RENUM = 1, the firmware does.  
3.4  
Buses  
This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional  
data bus, multiplexed on IO ports B and D.  
3.5  
USB Boot Methods  
3.7  
Bus-powered Applications  
2
During the power-up sequence, internal logic checks the I C  
port for the connection of an EEPROM whose first byte is  
0xC2. If found, it boot-loads the EEPROM contents into  
internal RAM (0xC2 load). If no EEPROM is present, an  
external processor must emulate an I C slave. The FX2LP18  
does not enumerate using internally stored descriptors (for  
example, Cypress’ VID/PID/DID is not used for enumer-  
The FX2LP18 fully supports bus-powered designs by enumer-  
ating with less than 100 mA as required by the USB 2.0 speci-  
fication.  
2
3.8  
Interrupt System  
The FX2LP18 interrupts are described in this section.  
ation).  
3.8.1  
INT2 Interrupt Request and Enable Registers  
3.6  
ReNumeration™  
FX2LP18 implements an autovector feature for INT2. There  
are 27 INT2 (USB) vectors. See the MoBL-USB™ Technical  
Reference Manual (TRM) for more details.  
Because the FX2LP18’s configuration is soft, one chip can  
take on the identities of multiple distinct USB devices.  
When first plugged into USB, the FX2LP18 enumerates  
automatically and downloads firmware and USB descriptor  
tables over the USB cable. Next, the FX2LP18 enumerates  
again, this time as a device defined by the downloaded infor-  
3.8.2  
USB Interrupt Autovectors  
The main USB interrupt is shared by 27 interrupt sources. To  
save the code and processing time that is normally required to  
identify the individual USB interrupt source, the FX2LP18  
provides a second level of interrupt vectoring, called ‘Autovec-  
toring.’ When a USB interrupt is asserted, the FX2LP18  
mation.  
This  
patented  
two-step  
process,  
called  
ReNumeration, happens instantly when the device is  
Note  
2
1. The I C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.  
Document # 001-06120 Rev *F  
Page 3 of 39  
   
CY7C68053  
pushes the program counter onto its stack then jumps to  
address 0x0043, where it expects to find a ‘jump’ instruction to  
the USB interrupt service routine.  
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP  
register), the FX2LP18 substitutes its INT2VEC byte.  
Therefore, if the high byte (‘page’) of a jump-table address is  
preloaded at location 0x0044, the automatically-inserted  
INT2VEC byte at 0x0045 directs the jump to the correct  
address out of the 27 addresses within the page.  
The FX2LP18 jump instruction is encoded as shown in  
Table 3-2. INT2 USB Interrupts  
USB INTERRUPT TABLE FOR INT2  
Source  
Priority  
1
INT2VEC Value  
Notes  
00  
04  
08  
0C  
10  
14  
18  
1C  
20  
24  
28  
2C  
30  
34  
38  
3C  
40  
44  
48  
4C  
50  
54  
58  
5C  
60  
64  
68  
6C  
70  
74  
78  
7C  
SUDAV  
SOF  
Set-up Data Available  
Start of Frame (or microframe)  
Set-up Token Received  
USB Suspend request  
Bus reset  
2
3
SUTOK  
4
SUSPEND  
USB RESET  
HISPEED  
EP0ACK  
5
6
Entered high-speed operation  
7
FX2LP18 ACK’d the CONTROL Handshake  
Reserved  
8
9
EP0-IN  
EP0-OUT  
EP1-IN  
EP1-OUT  
EP2  
EP0-IN ready to be loaded with data  
EP0-OUT has USB data  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
EP1-IN ready to be loaded with data  
EP1-OUT has USB data  
IN: buffer available. OUT: buffer has data  
IN: buffer available. OUT: buffer has data  
IN: buffer available. OUT: buffer has data  
IN: buffer available. OUT: buffer has data  
IN-Bulk-NAK (any IN endpoint)  
Reserved  
EP4  
EP6  
EP8  
IBN  
EP0PING  
EP1PING  
EP2PING  
EP4PING  
EP6PING  
EP8PING  
ERRLIMIT  
EP0 OUT was Pinged and it NAK’d  
EP1 OUT was Pinged and it NAK’d  
EP2 OUT was Pinged and it NAK’d  
EP4 OUT was Pinged and it NAK’d  
EP6 OUT was Pinged and it NAK’d  
EP8 OUT was Pinged and it NAK’d  
Bus errors exceeded the programmed limit  
Reserved  
Reserved  
EP2ISOERR  
EP4ISOERR  
EP6ISOERR  
EP8ISOERR  
ISO EP2 OUT PID sequence error  
ISO EP4 OUT PID sequence error  
ISO EP6 OUT PID sequence error  
ISO EP8 OUT PID sequence error  
Document # 001-06120 Rev *F  
Page 4 of 39  
 
CY7C68053  
Figure 3-2. Reset Timing Plots  
RESET#  
RESET#  
V
IL  
V
IL  
1.8V  
1.8V  
1.62V  
V
V
CC  
CC  
0V  
0V  
T
T
RESET  
RESET  
Power on Reset  
Powered Reset  
The FX2LP18 exits the power-down (USB suspend) state  
using one of the following methods:  
3.9  
Reset and Wakeup  
The reset and wakeup pins are described in detail in this  
section.  
• USB bus activity (if D+/D– lines are left floating, noise on  
these lines may indicate activity to the FX2LP18 and initiate  
a wakeup)  
3.9.1  
Reset Pin  
• External logic asserts the WAKEUP pin  
• External logic asserts the PA3/WU2 pin  
The input pin, RESET#, resets the FX2LP18 when asserted.  
This pin has hysteresis and is active LOW. When a crystal is  
used with the CY7C68053, the reset period must allow for the  
stabilization of the crystal and the PLL. This reset period must  
be approximately 5 ms after VCC has reached 3.0V. If the  
crystal input pin is driven by a clock signal the internal PLL  
The second wakeup pin, WU2, can also be configured as a  
general purpose IO pin. This allows a simple external R-C  
network to be used as a periodic wakeup source. Note that  
WAKEUP is by default active LOW.  
stabilizes in 200 µs after VCC has reached 3.0V . Figure 3-2  
shows a power on reset condition and a reset applied during  
operation. A power on reset is defined as the time reset is  
asserted while power is being applied to the circuit. A powered  
reset is defined to be when the FX2LP18 has previously been  
powered on and operating and the RESET# pin is asserted.  
3.9.3  
Lowering Suspend Current  
Good design practices for CMOS circuits dictate that any  
unused input pins must not be floating between V and V .  
Floating input pins will not damage the chip, but can substan-  
tially increase suspend current. To achieve the lowest suspend  
current, any unused port pins must be configured as outputs.  
Any unused input pins must be tied to ground. Some examples  
of pins that need attention during suspend are:  
IL  
IH  
Cypress provides an application note which describes and  
recommends power on reset implementation and can be found  
on the Cypress web site. For more information on reset imple-  
mentation for the MoBL-USB™ family of products, visit the  
Cypress web site at http://www.cypress.com.  
• Port pins. For Port A, B, D pins, extra care must be taken in  
shared bus situations.  
— Completely unused pins must be pulled to V  
GND.  
or  
CC_IO  
Table 3-3. Reset Timing Values  
Condition  
T
In a single-master system, the firmware must output en-  
able all the port pins and drive them high or low, before  
FX2LP18 enters the suspend state.  
RESET  
Power on Reset with crystal  
5 ms  
Power on Reset with external 200 µs + Clock stability time  
— In a multi-master system (FX2LP18 and another proces-  
sor sharing a common data bus), when FX2LP18 is sus-  
pended, the external master must drive the pins high or  
low. The external master may not let the pins float.  
clock  
Powered Reset  
200 µs  
• CLKOUT. If CLKOUT is not used, it must be tri-stated during  
normal operation, but driven during suspend.  
3.9.2 Wakeup Pins  
The 8051 puts itself and the rest of the chip into a power-down  
mode by setting PCON.0 = 1. This stops the oscillator and PLL.  
When WAKEUP is asserted by external logic, the oscillator  
restarts, after the PLL stabilizes, and then the 8051 receives a  
wakeup interrupt. This applies whether or not FX2LP18 is  
connected to the USB.  
• IFCLK, RDY0, RDY1. These pins must be pulled to V  
or GND or driven by another chip.  
CC_IO  
• CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be  
pulled to V or GND or driven by another chip.  
CC_IO  
• RESET#, WAKEUP#. These pins must be pulled to V  
or GND or driven by another chip during suspend.  
CC_IO  
Note  
2. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 µs.  
Document # 001-06120 Rev *F  
Page 5 of 39  
     
CY7C68053  
3.11  
Register Addresses  
Figure 3-3. FX2LP18 Internal Code Memory  
Figure 3-4. Register Address Memory  
FFFF  
FFFF  
7.5 kBytes  
USB regs and  
4K FIFO buffers  
4 kBytes EP2-EP8  
buffers  
(8 x 512)  
E200  
E1FF  
0.5 kBytes RAM  
F000  
EFFF  
Data  
E000  
2 kBytes RESERVED  
.
.
.
E800  
E7FF  
64 Bytes EP1IN  
E7C0  
E7BF  
E780  
E77F  
64 Bytes EP1OUT  
64 Bytes EP0 IN/OUT  
E740  
E73F  
3FFF  
64 Bytes RESERVED  
E700  
E6FF  
8051 Addressable Registers  
(512)  
16 kBytes RAM  
Code and Data  
E500  
E4FF  
E480  
Reserved (128)  
E47F  
128 Bytes GPIF Waveforms  
E400  
E3FF  
E200  
0000  
Reserved (512)  
E1FF  
512 Bytes  
8051 xdata RAM  
E000  
3.10  
Program/Data RAM  
This section describes the FX2LP18 RAM.  
3.12  
Endpoint RAM  
3.10.1 Size  
This section describes the FX2LP18 Endpoint RAM.  
The FX2LP18 has 16 kBytes of internal program/data RAM.  
No USB control registers appear in this space.  
3.12.1 Size  
Memory maps are shown in Figure 3-3 and Figure 3-4.  
• 3 × 64 bytes (Endpoints 0, 1)  
• 8 × 512 bytes (Endpoints 2, 4, 6, 8)  
3.10.2 Internal Code Memory  
3.12.2 Organization  
• EP0  
This mode implements the internal 16-kByte block of RAM  
(starting at 0) as combined code and data memory. Only the  
internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces  
have the following access:  
• Bidirectional endpoint zero, 64-byte buffer  
• EP1IN, EP1OUT  
• USB download  
• USB upload  
• 64-byte buffers: bulk or interrupt  
• EP2, 4, 6, 8  
• Set-up data pointer  
• Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4  
and EP8 can be double buffered, while EP2 and 6 can be  
double, triple, or quad buffered. For high-speed endpoint  
configuration options, see Figure 3-5.  
2
• I C interface boot load  
3.12.3 Set-up Data Buffer  
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the set-up  
data from a CONTROL transfer.  
3.12.4 Endpoint Configurations (High-speed Mode)  
Endpoints 0 and 1 are the same for every configuration.  
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can  
be either BULK or INTERRUPT. The endpoint buffers can be  
configured in any one of the 12 configurations shown in the  
Document # 001-06120 Rev *F  
Page 6 of 39  
   
CY7C68053  
vertical columns of Figure 3-5. When operating in full-speed  
BULK mode only the first 64 bytes of each buffer are used. For  
example, in high-speed the maximum packet size is 512 bytes,  
but in full-speed it is 64 bytes. Even though a buffer is  
configured to be a 512 byte buffer, in full-speed only the first  
64 bytes are used. The unused endpoint buffer space is not  
available for other operations. An example endpoint configu-  
ration is:  
EP2–1024 double buffered; EP6–512 quad buffered  
(column 8).  
Figure 3-5. Endpoint Configuration  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
64  
EP0 IN&OUT  
EP1 IN  
EP1 OUT  
EP2  
EP2  
512  
EP2  
EP2 EP2  
EP2 EP2  
EP2  
512  
EP2  
EP2  
512  
EP2  
EP2  
512  
512  
512  
512  
512  
512  
512  
1024  
1024  
1024  
1024  
512  
512  
512  
512  
512  
1024  
EP4  
512  
EP4 EP4  
512  
512  
512  
512  
512  
512  
512  
512  
EP6  
1024  
1024  
1024  
1024  
1024  
512  
512  
512  
512  
EP6  
512  
EP6  
512  
EP6  
EP6 EP6  
EP6  
EP6  
EP6 EP6  
512  
512  
1024  
1024  
512  
512  
512  
512  
512  
512  
1024  
1024  
1024  
512  
512  
512  
512  
EP8  
512  
EP8  
512  
EP8  
512  
EP8  
512  
EP8  
512  
1024  
512  
512  
512  
512  
512  
512  
1024  
1024  
1024  
512  
512  
512  
512  
512  
10  
11  
12  
9
4
5
8
1
2
3
6
7
3.12.5 Default Full-Speed Alternate Settings  
Table 3-4. Default Full-Speed Alternate Settings  
Alternate Setting  
0
64  
0
1
2
3
ep0  
64  
64  
64  
ep1out  
ep1in  
ep2  
64 bulk  
64 bulk  
64 int  
64 int  
64 int  
64 int  
0
0
64 bulk out (2×)  
64 bulk out (2×)  
64 bulk in (2×)  
64 bulk in (2×)  
64 int out (2×)  
64 bulk out (2×)  
64 int in (2×)  
64 iso out (2×)  
64 bulk out (2×)  
64 iso in (2×)  
ep4  
0
ep6  
0
ep8  
0
64 bulk in (2×)  
64 bulk in (2×)  
Notes  
3. ‘0’ means ‘not implemented.’  
4. ‘2×’ means ‘double buffered.’  
Document # 001-06120 Rev *F  
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CY7C68053  
3.12.6 Default High-Speed Alternate Settings  
[3, 4]  
Table 3-5. Default High-Speed Alternate Settings  
Alternate Setting  
0
1
2
3
ep0  
64  
0
64  
64  
64  
ep1out  
ep1in  
ep2  
512 bulk  
512 bulk  
64 int  
64 int  
64 int  
64 int  
0
0
512 bulk out (2×)  
512 bulk out (2×)  
512 bulk in (2×)  
512 bulk in (2×)  
512 int out (2×)  
512 bulk out (2×)  
512 int in (2×)  
512 iso out (2×)  
512 bulk out (2×)  
512 iso in (2×)  
512 bulk in (2×)  
ep4  
0
ep6  
0
ep8  
0
512 bulk in (2×)  
In Slave (S) mode, the FX2LP18 accepts either an internally  
derived clock or externally supplied clock (IFCLK, maximum  
frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE,  
PKTEND signals from external logic. When using an external  
IFCLK, the external clock must be present before switching to  
the external clock with the IFCLKSRC bit. Each endpoint can  
individually be selected for byte or word operation by an  
internal configuration bit, and a Slave FIFO Output Enable  
signal (SLOE) enables data of the selected width. External  
logic must insure that the output enable signal is inactive when  
writing data to a slave FIFO. The slave interface can also  
operate asynchronously, where the SLRD and SLWR signals  
act directly as strobes, rather than a clock qualifier as in  
synchronous mode. The signals SLRD, SLWR, SLOE and  
PKTEND are gated by the signal SLCS#.  
3.13  
External FIFO Interface  
The architecture, control signals, and clock rates are  
presented in this section.  
3.13.1 Architecture  
The FX2LP18 slave FIFO architecture has eight 512-byte  
blocks in the endpoint RAM that directly serve as FIFO  
memories and are controlled by FIFO control signals (such as  
IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).  
In operation, some of the eight RAM blocks fill or empty from  
the SIE while the others are connected to the IO transfer logic.  
The transfer logic takes two forms: the GPIF for internally  
generated control signals or the slave FIFO interface for exter-  
nally controlled transfers.  
3.13.3 GPIF and FIFO Clock Rates  
3.13.2 Master/Slave Control Signals  
An 8051 register bit selects one of two frequencies for the inter-  
nally supplied interface clock: 30 MHz and 48 MHz. Alterna-  
tively, an externally supplied clock of 5 MHz – 48 MHz feeding  
the IFCLK pin can be used as the interface clock. IFCLK can  
be configured to function as an output clock when the GPIF  
and FIFO’s are internally clocked. An output enable bit in the  
IFCONFIG register turns this clock output off. Another bit  
within the IFCONFIG register will invert the IFCLK signal  
whether internally or externally sourced.  
The FX2LP18 endpoint FIFO’s are implemented as eight  
physically distinct 256x16 RAM blocks. The 8051/SIE can  
switch any of the RAM blocks between two domains, the USB  
(SIE) domain and the 8051-IO Unit domain. This switching is  
instantaneous, giving zero transfer time between ‘USB FIFO’s’  
and ‘Slave FIFO’s.’ Since they are physically the same  
memory, no bytes are actually transferred between buffers.  
At any given time, some RAM blocks are filling and emptying  
with USB data under SIE control, while other RAM blocks are  
available to the 8051 and/or the IO control unit. The RAM  
blocks operate as single port in the USB domain, and dual port  
in the 8051-IO domain. The blocks can be configured as  
single, double, triple, or quad buffered as previously shown.  
3.14  
GPIF  
The GPIF is a flexible 8- or 16-bit parallel interface driven by a  
user programmable finite state machine. It allows the  
CY7C68053 to perform local bus mastering, and can  
implement a wide variety of protocols such as ATA interface,  
parallel printer port, and Utopia.  
The IO control unit implements either an internal master (M for  
master) or external master (S for Slave) interface.  
In Master (M) mode, the GPIF internally controls  
FIFOADR[1:0] to select a FIFO. The two RDY pins can be  
used as flag inputs from an external FIFO or other logic. The  
GPIF can be run from either an internally derived clock or  
externally supplied clock (IFCLK), at a rate that transfers data  
up to 96 Megabytes/s (48 MHz IFCLK with 16-bit interface).  
The GPIF has three programmable control outputs (CTL), and  
two general purpose ready inputs (RDY). The data bus width  
can be 8 or 16 bits. Each GPIF vector defines the state of the  
control outputs, and determines what state a ready input (or  
multiple inputs) must be before proceeding. The GPIF vector  
can be programmed to advance a FIFO to the next data value,  
advance an address, and so on. A sequence of the GPIF  
vectors make up a single waveform that is executed to perform  
the desired data move between the FX2LP18 and the external  
device.  
Notes  
5. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.  
Document # 001-06120 Rev *F  
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CY7C68053  
3.14.1 Three Control OUT Signals  
3.16  
USB Uploads and Downloads  
The 56-pin package brings out three of these signals,  
CTL0–CTL2. The 8051 programs the GPIF unit to define the  
CTL waveforms. CTLx waveform edges can be programmed  
to make transitions as fast as once per clock cycle (20.8 ns  
using a 48 MHz clock).  
The core has the ability to directly edit the data contents of the  
internal 16-kByte RAM and of the internal 512-byte scratch  
pad RAM via a vendor-specific command. This capability is  
normally used when ‘soft’ downloading user code and is  
available only to and from internal RAM, only when the 8051  
is held in reset. The available RAM spaces are 16 kBytes from  
0x0000–0x3FFF (code/data) and 512 bytes from  
3.14.2 Two Ready IN Signals  
0xE000–0xE1FF (scratch pad data RAM).  
The FX2LP18 package brings out all two Ready inputs  
(RDY0–RDY1). The 8051 programs the GPIF unit to test the  
RDY pins for GPIF branching.  
3.17  
Autopointer Access  
FX2LP18 provides two identical autopointers. They are similar  
to the internal 8051 data pointers, but with an additional  
feature: they can optionally increment after every memory  
access.The autopointers are available in external FX2LP18  
registers, under control of a mode bit (AUTOPTRSET-UP.0).  
Using the external FX2LP18 autopointer access (at 0xE67B –  
0xE67C) allows the autopointer to access all RAM. Also, the  
autopointers can point to any FX2LP18 register or endpoint  
buffer space.  
3.14.3 Long Transfer Mode  
In master mode, the 8051 appropriately sets GPIF transaction  
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or  
GPIFTCB0) for unattended transfers of up to 2 transactions.  
The GPIF automatically throttles data flow to prevent under or  
overflow until the full number of requested transactions  
complete. The GPIF decrements the value in these registers  
to represent the current status of the transaction.  
32  
2
3.15  
ECC Generation[6]  
3.18  
I C Controller  
2
FX2LP18 has one I C port that is driven by two internal  
controllers. One automatically operates at boot time to load the  
VID/PID/DID, configuration byte, and firmware and a second  
controller that the 8051, once running, uses to control external  
The MoBL-USB can calculate Error Correcting Codes (ECC’s)  
on data that passes across its GPIF or Slave FIFO interfaces.  
There are two ECC configurations: two ECC’s, each calculated  
over 256 bytes (SmartMedia Standard) and one ECC calcu-  
lated over 512 bytes.  
2
2
I C devices. The I C port operates in master mode only.  
The ECC can correct any 1-bit error or detect any 2-bit error.  
2
3.18.1 I C Port Pins  
2
The I C pins SCL and SDA must have external 2.2K ohm pull  
3.15.1 ECC Implementation  
up resistors even if no EEPROM is connected to the FX2LP18.  
The value of the pull up resistors required may vary, depending  
The two ECC configurations are selected by the ECCM bit.  
on the combination of V  
EEPROM. The pull up resistors used must be such that when  
the EEPROM pulls SDA low, the voltage level meets the V  
specification of the FX2LP18. For example, if the EEPROM  
runs off a 3.3V supply and V is 1.8V, the pull up resistors  
and the supply used for the  
CC_IO  
3.15.1.1 ECCM = 0  
Two 3-byte ECC’s are each calculated over a 256-byte block  
of data. This configuration conforms to the SmartMedia  
Standard.  
IL  
CC_IO  
recommended are 10K ohm. This requirement may also vary  
This configuration writes any value to ECCRESET, then  
passes data across the GPIF or Slave FIFO interface. The  
ECC for the first 256 bytes of data is calculated and stored in  
ECC1. The ECC for the next 256 bytes is stored in ECC2. After  
the second ECC is calculated, the values in the ECCx registers  
do not change until ECCRESET is written again, even if more  
data is subsequently passed across the interface.  
2
depending on the devices being run on the I C pins. Refer to  
2
the I C specifications for details.  
External EEPROM device address pins must be configured  
properly. See Table 3-6 for configuring the device address  
pins.  
2
If no EEPROM is connected to the I C port, EEPROM  
emulation is required by an external processor.This is because  
the FX2LP18 comes out of reset with the DISCON bit set, so  
the device will not enumerate without an EEPROM (C2 load)  
or EEPROM emulation.  
3.15.1.2 ECCM = 1  
One 3-byte ECC is calculated over a 512-byte block of data.  
This configuration writes any value to ECCRESET then  
passes data across the GPIF or Slave FIFO interface. The  
ECC for the first 512 bytes of data is calculated and stored in  
ECC1; ECC2 is unused. After the ECC is calculated, the value  
in ECC1 does not change until ECCRESET is written again,  
even if more data is subsequently passed across the interface.  
Notes  
6. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.  
7. After the data has been downloaded from the host, a ‘loader’ can execute from internal RAM in order to transfer downloaded data to external memory.  
Document # 001-06120 Rev *F  
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CY7C68053  
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The  
8051 is reset. I C interface boot loads only occur after power  
on reset.  
Table 3-6. Strap Boot EEPROM Address Lines to These  
Values  
2
Bytes  
16  
Example EEPROM  
A2  
N/A  
0
A1  
N/A  
0
A0  
N/A  
0
[8]  
2
24AA00  
3.18.3 I C Interface General Purpose Access  
2
128  
256  
4K  
24AA01  
24AA02  
24AA32  
24AA64  
24AA128  
The 8051 can control peripherals connected to the I C bus  
2
using the I2CTL and I2DAT registers. FX2LP18 provides I C  
0
0
0
2
master control only, it is never an I C slave.  
0
0
1
8K  
0
0
1
4.0  
Pin Assignments  
16K  
0
0
1
Figure 4-1 identifies all signals for the package. It is followed  
by the pin diagram.Three modes are available: Port, GPIF  
master, and Slave FIFO. These modes define the signals on  
the right edge of the diagram. The 8051 selects the interface  
mode using the IFCONFIG[1:0] register bits. Port mode is the  
power on default configuration.  
2
3.18.2 I C Interface Boot Load Access  
2
At power on reset the I C interface boot loader loads the  
VID/PID/DID and configuration bytes and up to 16 kBytes of  
program/data. The available RAM spaces are 16 kBytes from  
Figure 4-1. Signals  
Port  
GPIF Master  
Slave FIFO  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
PB7  
PB6  
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
FD[15]  
FD[14]  
FD[13]  
FD[12]  
FD[11]  
FD[10]  
FD[9]  
FD[8]  
FD[7]  
FD[6]  
FD[5]  
FD[4]  
FD[3]  
FD[2]  
FD[1]  
FD[0]  
FD[15]  
FD[14]  
FD[13]  
FD[12]  
FD[11]  
FD[10]  
FD[9]  
FD[8]  
FD[7]  
FD[6]  
FD[5]  
FD[4]  
FD[3]  
FD[2]  
FD[1]  
FD[0]  
XTALIN  
XTALOUT  
RESET#  
WAKEUP#  
SCL  
SDA  
SLRD  
SLWR  
RDY0  
RDY1  
FLAGA  
FLAGB  
FLAGC  
CTL0  
CTL1  
CTL2  
INT0#/PA0  
INT1#/PA1  
PA2  
WU2/PA3  
PA4  
INT0#/PA0  
INT1#/PA1  
SLOE  
INT0#/PA0  
INT1#/PA1  
PA2  
WU2/PA3  
PA4  
PA5  
PA6  
IFCLK  
CLKOUT  
WU2/PA3  
FIFOADR0  
FIFOADR1  
PKTEND  
DPLUS  
DMINUS  
PA5  
PA6  
PA7  
PA7/FLAGD/SLCS#  
PA7  
Note  
8. This EEPROM does not have address pins.  
Document # 001-06120 Rev *F  
Page 10 of 39  
     
CY7C68053  
Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view  
1
2
3
4
5
6
7
8
1A  
1B  
1C  
2A  
2B  
2C  
3A  
3B  
3C  
4A  
4B  
4C  
5A  
5B  
5C  
6A  
6B  
6C  
7A  
7B  
7C  
8A  
8B  
8C  
A
B
C
D
1D  
2D  
7D  
8D  
1E  
1F  
1G  
1H  
2E  
2F  
2G  
2H  
7E  
7F  
7G  
7H  
8E  
8F  
8G  
8H  
E
3F  
4F  
5F  
6F  
F
G
H
3G  
3H  
4G  
4H  
5G  
5H  
6G  
6H  
Document # 001-06120 Rev *F  
Page 11 of 39  
CY7C68053  
4.1  
CY7C68053 Pin Descriptions  
Table 4-1. FX2LP18 Pin Descriptions  
56 VFBGA  
Name  
Type  
Default  
Description  
2D  
AV  
Power  
N/A  
Analog VCC. Connect this pin to 3.3V power source. This signal provides  
power to the analog section of the chip.  
CC  
Appropriate bulk/bypass capacitance should be provided for this  
supply rail.  
1D  
2F  
1F  
AV  
Power  
Ground  
Ground  
N/A  
N/A  
N/A  
Analog VCC. Connect this pin to 3.3V power source. This signal provides  
power to the analog section of the chip.  
CC  
AGND  
AGND  
Analog Ground. Connect this pin to ground with as short a path as  
possible.  
Analog Ground. Connect to this pin ground with as short a path as  
possible.  
1E  
2E  
8B  
DMINUS  
DPLUS  
I/O/Z  
I/O/Z  
Input  
Z
Z
USB D– Signal. Connect this pin to the USB D– signal.  
USB D+ Signal. Connect this pin to the USB D+ signal.  
RESET#  
N/A  
Active LOW Reset. This pin resets the entire chip. See Section 3.9 ”Reset  
and Wakeup” on page 5 for more details.  
1C  
XTALIN  
Input  
N/A  
N/A  
Crystal Input. Connect this signal to a 24 MHz parallel resonant, funda-  
mental mode crystal and load capacitor to GND.  
It is also correct to drive XTALIN with an external 24-MHz square wave  
derived from another clock source.  
2C  
2B  
XTALOUT  
CLKOUT  
Output  
O/Z  
Crystal Output. Connect this signal to a 24 MHz parallel resonant, funda-  
mental mode crystal and load capacitor to GND.  
If an external clock is used to drive XTALIN, leave this pin open.  
12 MHz CLKOUT. 12-, 24- or 48-MHz clock, phase locked to the 24 MHz input  
clock. The 8051 defaults to 12 MHz operation. The 8051 may tri-state this  
output by setting CPUCS.1 = 1.  
Port A  
8G  
PA0 or  
INT0#  
I/O/Z  
I/O/Z  
I
Multiplexed pin whose function is selected by PORTACFG.0  
PA0 is a bidirectional IO port pin.  
INT0# is the active LOW 8051 INT0 interrupt input signal, which is either  
edge triggered (IT0 = 1) or level triggered (IT0 = 0).  
(PA0)  
6G  
8F  
7F  
PA1 or  
INT1#  
I
Multiplexed pin whose function is selected by:  
PORTACFG.1  
PA1 is a bidirectional IO port pin.  
INT1# is the active LOW 8051 INT1 interrupt input signal, which is either  
edge triggered (IT1 = 1) or level triggered (IT1 = 0).  
(PA1)  
PA2 or  
SLOE  
I/O/Z  
I/O/Z  
I
Multiplexed pin whose function is selected by two bits:  
IFCONFIG[1:0].  
PA2 is a bidirectional IO port pin.  
SLOE is an input-only output enable with programmable polarity  
(FIFOPINPOLAR.4) for the slave FIFO’s connected to FD[7:0] or FD[15:0].  
(PA2)  
PA3 or  
WU2  
I
Multiplexed pin whose function is selected by:  
WAKEUP.7 and OEA.3  
(PA3)  
PA3 is a bidirectional IO port pin.  
WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit  
(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in  
suspend and WU2EN = 1, a transition on this pin starts up the oscillator  
and interrupts the 8051 to allow it to exit the suspend mode. Asserting this  
pin inhibits the chip from suspending, if WU2EN = 1.  
Note  
9. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and  
in standby. Note also that no pins should be driven while the device is powered down  
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CY7C68053  
[9]  
Table 4-1. FX2LP18 Pin Descriptions (continued)  
56 VFBGA  
Name  
PA4 or  
FIFOADR0  
Type  
Default  
Description  
6F  
I/O/Z  
I
Multiplexed pin whose function is selected by:  
IFCONFIG[1:0].  
(PA4)  
PA4 is a bidirectional IO port pin.  
FIFOADR0 is an input-only address select for the slave FIFO’s connected  
to FD[7:0] or FD[15:0].  
8C  
PA5 or  
FIFOADR1  
I/O/Z  
I
Multiplexed pin whose function is selected by:  
IFCONFIG[1:0].  
(PA5)  
PA5 is a bidirectional IO port pin.  
FIFOADR1 is an input-only address select for the slave FIFO’s connected  
to FD[7:0] or FD[15:0].  
7C  
6C  
PA6 or  
PKTEND  
I/O/Z  
I/O/Z  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.  
PA6 is a bidirectional IO port pin.  
PKTEND is an input used to commit the FIFO packet data to the endpoint  
(PA6)  
and whose polarity is programmable using FIFOPINPOLAR.5.  
PA7 or  
FLAGD or  
SLCS#  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
PORTACFG.7 bits.  
PA7 is a bidirectional IO port pin.  
(PA7)  
FLAGD is a programmable slave FIFO output status flag signal.  
SLCS# gates all other slave FIFO enable/strobes  
Port B  
3H  
PB0 or  
FD[0]  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB0 is a bidirectional IO port pin.  
(PB0)  
FD[0] is the bidirectional FIFO/GPIF data bus.  
4F  
4H  
4G  
5H  
5G  
5F  
6H  
PB1 or  
FD[1]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB1 is a bidirectional IO port pin.  
(PB1)  
FD[1] is the bidirectional FIFO/GPIF data bus.  
PB2 or  
FD[2]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB2 is a bidirectional IO port pin.  
(PB2)  
FD[2] is the bidirectional FIFO/GPIF data bus.  
PB3 or  
FD[3]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB3 is a bidirectional IO port pin.  
(PB3)  
FD[3] is the bidirectional FIFO/GPIF data bus.  
PB4 or  
FD[4]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB4 is a bidirectional IO port pin.  
(PB4)  
FD[4] is the bidirectional FIFO/GPIF data bus.  
PB5 or  
FD[5]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB5 is a bidirectional IO port pin.  
(PB5)  
FD[5] is the bidirectional FIFO/GPIF data bus.  
PB6 or  
FD[6]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
PB6 is a bidirectional IO port pin.  
(PB6)  
FD[6] is the bidirectional FIFO/GPIF data bus.  
PB7 or  
FD[7]  
I
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
(PB7)  
PB7 is a bidirectional IO port pin.  
FD[7] is the bidirectional FIFO/GPIF data bus.  
Document # 001-06120 Rev *F  
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CY7C68053  
[9]  
Table 4-1. FX2LP18 Pin Descriptions (continued)  
56 VFBGA  
PORT D  
8A  
Name  
Type  
Default  
Description  
PD0 or  
FD[8]  
I/O/Z  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
(PD0)  
FD[8] is the bidirectional FIFO/GPIF data bus.  
7A  
6B  
6A  
3B  
3A  
3C  
2A  
PD1 or  
FD[9]  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I/O/Z  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
FD[9] is the bidirectional FIFO/GPIF data bus.  
(PD1)  
PD2 or  
FD[10]  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
FD[10] is the bidirectional FIFO/GPIF data bus.  
(PD2)  
PD3 or  
FD[11]  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
FD[11] is the bidirectional FIFO/GPIF data bus.  
(PD3)  
PD4 or  
FD[12]  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
FD[12] is the bidirectional FIFO/GPIF data bus.  
(PD4)  
PD5 or  
FD[13]  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
FD[13] is the bidirectional FIFO/GPIF data bus.  
(PD5)  
PD6 or  
FD[14]  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
FD[14] is the bidirectional FIFO/GPIF data bus.  
(PD6)  
PD7 or  
FD[15]  
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and  
EPxFIFOCFG.0 (wordwide) bits.  
(PD7)  
FD[15] is the bidirectional FIFO/GPIF data bus.  
1A  
1B  
7H  
7G  
8H  
RDY0 or  
SLRD  
Input  
Input  
O/Z  
N/A  
N/A  
H
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
RDY0 is a GPIF input signal.  
SLRD is the input only read strobe with programmable polarity (FIFOPIN-  
POLAR.3) for the slave FIFO’s connected to FD[7:0] or FD[15:0].  
RDY1 or  
SLWR  
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
RDY1 is a GPIF input signal.  
SLWR is the input only write strobe with programmable polarity (FIFOPIN-  
POLAR.2) for the slave FIFO’s connected to FD[7:0] or FD[15:0].  
CTL0 or  
FLAGA  
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
CTL0 is a GPIF control output.  
FLAGA is a programmable slave FIFO output status flag signal.  
Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.  
CTL1 or  
FLAGB  
O/Z  
H
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
CTL1 is a GPIF control output.  
FLAGB is a programmable slave FIFO output status flag signal.  
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.  
CTL2 or  
FLAGC  
O/Z  
H
Multiplexed pin whose function is selected by the following bits:  
IFCONFIG[1:0].  
CTL2 is a GPIF control output.  
FLAGC is a programmable slave FIFO output status flag signal.  
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.  
Document # 001-06120 Rev *F  
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CY7C68053  
[9]  
Table 4-1. FX2LP18 Pin Descriptions (continued)  
56 VFBGA  
Name  
IFCLK  
Type  
Default  
Description  
2G  
I/O/Z  
Z
Interface Clock, used for synchronously clocking data into or out of the  
slave FIFO’s. IFCLK also serves as a timing reference for all slave FIFO  
controlsignalsandGPIF. Wheninternalclockingisused(IFCONFIG.7 = 1)  
the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5  
and IFCONFIG.6. IFCLK may be inverted, whether internally or externally  
sourced, by setting the bit IFCONFIG.4 =1.  
7B  
WAKEUP  
Input  
N/A  
USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the  
oscillator and interrupts the 8051 to allow it to exit the suspend mode.  
Holding WAKEUP asserted inhibits the MoBL-USB chip from  
suspending. This pin has programmable polarity (WAKEUP.4).  
2
3F  
SCL  
SDA  
OD  
OD  
Z
Z
Clock for the I C interface. Connect to V  
or V with a 2.2K - 10K  
CC_IO CC  
2
pull up resistor. (An I C peripheral is required).  
2
3G  
Data for the I C interface. Connect to V  
up resistor. (An I C peripheral is required).  
or V with a 2.2K - 10K pull  
CC_IO CC  
2
5A  
V
Power  
N/A  
VCC. Connect this pin to 1.8V to 3.3V power source.  
Appropriate bulk/bypass capacitance should be provided for this  
supply rail.  
CC_IO  
5B  
7E  
8E  
5C  
V
V
V
V
Power  
Power  
Power  
Power  
N/A  
N/A  
N/A  
N/A  
VCC. Connect this pin to 1.8V to 3.3V power source  
VCC. Connect this pin to 1.8V to 3.3V power source.  
VCC. Connect this pin to 1.8V to 3.3V power source.  
CC_IO  
CC_IO  
CC_IO  
CC_D  
VCC. Connect this pin to 1.8V power source.(Supplies power to internal  
digital 1.8V circuits)  
Appropriate bulk/bypass capacitance should be provided for this  
supply rail.  
1G  
V
Power  
N/A  
VCC. Connect this pin to 1.8V power source.(Supplies power to internal  
analog 1.8V circuits)  
CC_A  
1H  
2H  
4A  
4B  
4C  
7D  
8D  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
Ground  
Ground  
Ground  
Ground  
Ground  
Ground  
Ground  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
Ground.  
Ground.  
Ground.  
Ground.  
Ground.  
Ground.  
Ground.  
Document # 001-06120 Rev *F  
Page 15 of 39  
CY7C68053  
5.0  
Register Summary  
FX2LP18 register bit definitions are described in the MoBL-USB TRM in greater detail.  
Table 5-1. FX2LP18 Register Summary  
Hex Size Name  
Description  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Default  
Access  
GPIF Waveform Memories  
E400 128 WAVEDATA  
GPIF Waveform  
Descriptor 0, 1, 2, 3 data  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
xxxxxxxx RW  
E480 128 Reserved  
GENERAL CONFIGURATION  
E50D  
GPCR2  
General Purpose Configu- Reserved  
ration Register 2  
Reserved  
Reserved FULL_SPEE Reserved  
D_ONLY  
Reserved  
Reserved  
Reserved 00000000 R  
E600  
E601  
1
1
CPUCS  
CPU Control & Status  
0
0
PORTCSTB CLKSPD1 CLKSPD0  
CLKINV  
GSTATE  
CLKOE  
IFCFG1  
8051RES 00000010 rrbbbbbr  
IFCFG0 10000000 RW  
IFCONFIG  
Interface Configuration  
(Ports, GPIF, slave  
FIFO’s)  
IFCLKSRC  
3048MHZ  
IFCLKOE  
IFCLKPOL  
ASYNC  
[10]  
[10]  
E602  
E603  
E604  
1
1
1
PINFLAGSAB  
Slave FIFO FLAGA and  
FLAGB Pin Configuration  
FLAGB3  
FLAGD3  
NAKALL  
FLAGB2  
FLAGD2  
0
FLAGB1  
FLAGD1  
0
FLAGB0  
FLAGD0  
0
FLAGA3  
FLAGC3  
EP3  
FLAGA2  
FLAGC2  
EP2  
FLAGA1  
FLAGC1  
EP1  
FLAGA0 00000000 RW  
FLAGC0 00000000 RW  
PINFLAGSCD  
Slave FIFO FLAGC and  
FLAGD Pin Configuration  
[10]  
FIFORESET  
Restore FIFO’s to default  
state  
EP0  
xxxxxxxx  
W
E605  
E606  
E607  
E608  
E609  
1
1
1
1
1
BREAKPT  
Breakpoint Control  
Breakpoint Address H  
Breakpoint Address L  
Reserved  
0
A15  
A7  
0
0
A14  
A6  
0
0
A13  
0
A12  
A4  
BREAK  
A11  
BPPULSE  
A10  
BPEN  
A9  
0
00000000 rrrrbbbr  
xxxxxxxx RW  
BPADDRH  
BPADDRL  
A8  
A0  
0
A5  
A3  
A2  
A1  
xxxxxxxx RW  
Reserved  
0
0
0
0
0
00000000 rrrrrrbb  
00000000 rrbbbbbb  
FIFOPINPOLAR  
Slave FIFO Interface pins  
polarity  
0
0
PKTEND  
SLOE  
SLRD  
SLWR  
EF  
FF  
E60A  
E60B  
1
1
REVID  
Chip Revision  
rv7  
0
rv6  
0
rv5  
0
rv4  
0
rv3  
0
rv2  
0
rv1  
rv0  
RevA  
R
00000001  
REVCTL  
Chip Revision Control  
dyn_out  
enh_pkt 00000000 rrrrrrbb  
UDMA  
E60C  
1
3
GPIFHOLDAMOUNT MSTB Hold Time  
(for UDMA)  
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb  
Reserved  
ENDPOINT CONFIGURATION  
E610  
E611  
1
1
EP1OUTCFG  
Endpoint 1-OUT  
Configuration  
VALID  
VALID  
0
0
TYPE1  
TYPE1  
TYPE0  
TYPE0  
0
0
0
0
0
0
0
0
10100000 brbbrrrr  
10100000 brbbrrrr  
EP1INCFG  
Endpoint 1-IN  
Configuration  
E612  
E613  
E614  
E615  
1
1
1
1
2
1
EP2CFG  
Endpoint 2 Configuration  
Endpoint 4 Configuration  
Endpoint 6 Configuration  
Endpoint 8 Configuration  
VALID  
VALID  
VALID  
VALID  
DIR  
DIR  
DIR  
DIR  
TYPE1  
TYPE1  
TYPE1  
TYPE1  
TYPE0  
TYPE0  
TYPE0  
TYPE0  
SIZE  
0
0
0
0
0
BUF1  
0
BUF0  
0
10100010 bbbbbrbb  
10100000 bbbbrrrr  
11100010 bbbbbrbb  
11100000 bbbbrrrr  
EP4CFG  
EP6CFG  
SIZE  
0
BUF1  
0
BUF0  
0
EP8CFG  
Reserved  
EP2FIFOCFG  
[10]  
[10]  
[10]  
[10]  
E618  
E619  
E61A  
E61B  
Endpoint 2/slave FIFO  
configuration  
0
0
0
0
INFM1  
INFM1  
INFM1  
INFM1  
OEP1  
OEP1  
OEP1  
OEP1  
AUTOOUT  
AUTOOUT  
AUTOOUT  
AUTOOUT  
AUTOIN ZEROLENIN  
AUTOIN ZEROLENIN  
AUTOIN ZEROLENIN  
AUTOIN ZEROLENIN  
0
0
0
0
WORDWIDE 00000101 rbbbbbrb  
WORDWIDE 00000101 rbbbbbrb  
WORDWIDE 00000101 rbbbbbrb  
WORDWIDE 00000101 rbbbbbrb  
1
1
1
EP4FIFOCFG  
EP6FIFOCFG  
EP8FIFOCFG  
Reserved  
Endpoint 4/slave FIFO  
configuration  
Endpoint 6/slave FIFO  
configuration  
Endpoint 8/slave FIFO  
configuration  
E61C  
E620  
4
1
EP2AUTOINLENH Endpoint 2 AUTOIN  
0
PL7  
0
0
PL6  
0
0
PL5  
0
0
PL4  
0
0
PL3  
0
PL10  
PL2  
0
PL9  
PL1  
PL9  
PL1  
PL9  
PL1  
PL9  
PL1  
PL8  
PL0  
PL8  
PL0  
PL8  
PL0  
PL8  
PL0  
00000010 rrrrrbbb  
00000000 RW  
Packet Length H  
[10]  
E621  
E622  
E623  
E624  
E625  
E626  
E627  
1
1
1
1
1
1
1
EP2AUTOINLENL  
Endpoint 2 AUTOIN  
Packet Length L  
EP4AUTOINLENH Endpoint 4 AUTOIN  
00000010 rrrrrrbb  
00000000 RW  
]
Packet Length H  
[10]  
EP4AUTOINLENL  
Endpoint 4 AUTOIN  
Packet Length L  
PL7  
0
PL6  
0
PL5  
0
PL4  
0
PL3  
0
PL2  
PL10  
PL2  
0
EP6AUTOINLENH Endpoint 6 AUTOIN  
00000010 rrrrrbbb  
00000000 RW  
]
Packet Length H  
[10]  
EP6AUTOINLENL  
Endpoint 6 AUTOIN  
Packet Length L  
PL7  
0
PL6  
0
PL5  
0
PL4  
0
PL3  
0
EP8AUTOINLENH Endpoint 8 AUTOIN  
00000010 rrrrrrbb  
00000000 RW  
]
Packet Length H  
[10]  
EP8AUTOINLENL  
Endpoint 8 AUTOIN  
Packet Length L  
PL7  
PL6  
PL5  
PL4  
PL3  
PL2  
E628  
E629  
E62A  
E62B  
1
1
1
1
ECCCFG  
ECCRESET  
ECC1B0  
ECC Configuration  
ECC Reset  
0
x
0
0
0
x
0
0
x
0
ECCM  
x
00000000 rrrrrrrb  
00000000 W  
00000000 R  
x
x
x
x
ECC1 Byte 0 Address  
ECC1 Byte 1 Address  
LINE15  
LINE7  
LINE14  
LINE6  
LINE13  
LINE5  
LINE12  
LINE4  
LINE11  
LINE3  
LINE10  
LINE2  
LINE9  
LINE1  
LINE8  
LINE0  
ECC1B1  
00000000 R  
Note  
10. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for ‘Synchronization Delay.’  
Document # 001-06120 Rev *F  
Page 16 of 39  
 
CY7C68053  
Table 5-1. FX2LP18 Register Summary (continued)  
Hex Size Name  
Description  
b7  
b6  
b5  
b4  
b3  
b2  
COL0  
LINE10  
LINE2  
COL0  
0
b1  
LINE17  
LINE9  
LINE1  
0
b0  
LINE16  
LINE8  
LINE0  
0
Default  
Access  
E62C  
E62D  
E62E  
E62F  
1
1
1
1
1
ECC1B2  
ECC1 Byte 2 Address  
ECC2 Byte 0 Address  
ECC2 Byte 1 Address  
ECC2 Byte 2 Address  
COL5  
LINE15  
LINE7  
COL5  
DECIS  
COL4  
LINE14  
LINE6  
COL4  
COL3  
LINE13  
LINE5  
COL3  
COL2  
LINE12  
LINE4  
COL2  
COL1  
LINE11  
LINE3  
COL1  
00000000 R  
ECC2B0  
00000000 R  
ECC2B1  
00000000 R  
ECC2B2  
00000000 R  
E630  
H.S.  
EP2FIFOPFH  
Endpoint 2/slave FIFO  
Programmable Flag H  
PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]  
OUT:PFC12 OUT:PFC11 OUT:PFC10  
PFC9  
PFC8  
10001000 bbbbbrbb  
E630  
F.S.  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EP2FIFOPFH  
Endpoint 2/slave FIFO  
Programmable Flag H  
DECIS  
PFC7  
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10  
0
PFC2  
PFC2  
0
PFC9  
PFC1  
PFC1  
0
IN:PKTS[2] 10001000 bbbbbrbb  
OUT:PFC8  
[10]  
[10]  
E631  
H.S.  
EP2FIFOPFL  
EP2FIFOPFL  
Endpoint 2/slave FIFO  
Programmable Flag L  
PFC6  
PFC5  
PFC5  
0
PFC4  
PFC4  
PFC3  
PFC3  
PFC0  
PFC0  
PFC8  
PFC8  
PFC0  
PFC0  
PFC8  
00000000 RW  
E631  
F.S  
Endpoint 2/slave FIFO  
Programmable Flag L  
IN:PKTS[1] IN:PKTS[0]  
OUT:PFC7 OUT:PFC6  
00000000 RW  
E632  
H.S.  
EP4FIFOPFH  
Endpoint 4/slave FIFO  
Programmable Flag H  
DECIS  
DECIS  
PFC7  
PKTSTAT  
PKTSTAT  
PFC6  
IN: PKTS[1] IN: PKTS[0]  
OUT:PFC10 OUT:PFC9  
10001000 bbrbbrrb  
10001000 bbrbbrrb  
00000000 RW  
E632  
F.S  
EP4FIFOPFH  
Endpoint 4/slave FIFO  
Programmable Flag H  
0
OUT:PFC10 OUT:PFC9  
0
0
[10]  
[10]  
E633  
H.S.  
EP4FIFOPFL  
EP4FIFOPFL  
Endpoint 4/slave FIFO  
Programmable Flag L  
PFC5  
PFC5  
PFC4  
PFC4  
PFC3  
PFC3  
PFC2  
PFC2  
0
PFC1  
PFC1  
PFC9  
PFC9  
PFC1  
PFC1  
0
E633  
F.S  
Endpoint 4/slave FIFO  
Programmable Flag L  
IN: PKTS[1] IN: PKTS[0]  
OUT:PFC7 OUT:PFC6  
00000000 RW  
E634  
H.S.  
EP6FIFOPFH  
Endpoint 6/slave FIFO  
Programmable Flag H  
DECIS  
DECIS  
PFC7  
PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]  
OUT:PFC12 OUT:PFC11 OUT:PFC10  
00001000 bbbbbrbb  
E634  
F.S  
EP6FIFOPFH  
Endpoint 6/slave FIFO  
Programmable Flag H  
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10  
0
IN:PKTS[2] 00001000 bbbbbrbb  
OUT:PFC8  
[10]  
[10]  
E635  
H.S.  
EP6FIFOPFL  
EP6FIFOPFL  
Endpoint 6/slave FIFO  
Programmable Flag L  
PFC6  
PFC5  
PFC5  
0
PFC4  
PFC4  
PFC3  
PFC3  
PFC2  
PFC2  
0
PFC0  
PFC0  
PFC8  
PFC8  
PFC0  
PFC0  
00000000 RW  
E635  
F.S  
Endpoint 6/slave FIFO  
Programmable Flag L  
IN:PKTS[1] IN:PKTS[0]  
OUT:PFC7 OUT:PFC6  
00000000 RW  
E636  
H.S.  
EP8FIFOPFH  
Endpoint 8/slave FIFO  
Programmable Flag H  
DECIS  
DECIS  
PFC7  
PKTSTAT  
PKTSTAT  
PFC6  
IN: PKTS[1] IN: PKTS[0]  
OUT:PFC10 OUT:PFC9  
00001000 bbrbbrrb  
00001000 bbrbbrrb  
00000000 RW  
E636  
F.S  
EP8FIFOPFH  
Endpoint 8/slave FIFO  
Programmable Flag H  
0
OUT:PFC10 OUT:PFC9  
0
0
[10]  
[10]  
E637  
H.S.  
EP8FIFOPFL  
EP8FIFOPFL  
Reserved  
Endpoint 8/slave FIFO  
Programmable Flag L  
PFC5  
PFC5  
PFC4  
PFC4  
PFC3  
PFC3  
PFC2  
PFC2  
PFC1  
PFC1  
E637  
F.S  
Endpoint 8/slave FIFO  
Programmable Flag L  
IN: PKTS[1] IN: PKTS[0]  
OUT:PFC7 OUT:PFC6  
00000000 RW  
8
1
E640  
E641  
E642  
E643  
EP2ISOINPKTS  
EP4ISOINPKTS  
EP6ISOINPKTS  
EP8ISOINPKTS  
Reserved  
EP2 (if ISO) IN Packets  
per frame (1-3)  
AADJ  
AADJ  
AADJ  
AADJ  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INPPF1  
INPPF1  
INPPF1  
INPPF1  
INPPF0 00000001 brrrrrbb  
INPPF0 00000001 brrrrrrr  
INPPF0 00000001 brrrrrbb  
INPPF0 00000001 brrrrrrr  
1
1
1
EP4 (if ISO) IN Packets  
per frame (1-3)  
EP6 (if ISO) IN Packets  
per frame (1-3)  
EP8 (if ISO) IN Packets  
per frame (1-3)  
E644  
E648  
E649  
4
1
7
INPKTEND  
Force IN Packet End  
Skip  
Skip  
0
0
0
0
0
0
EP3  
EP3  
EP2  
EP2  
EP1  
EP1  
EP0  
EP0  
xxxxxxxx  
xxxxxxxx  
W
W
[10]  
OUTPKTEND  
Force OUT Packet End  
INTERRUPTS  
E650  
E651  
E652  
E653  
E654  
E655  
E656  
E657  
E658  
E659  
E65A  
E65B  
1
1
1
1
1
1
1
1
1
1
1
1
EP2FIFOIE  
Endpoint 2 slave FIFO  
Flag Interrupt Enable  
0
0
0
0
0
0
0
0
EDGEPF  
PF  
PF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EP1  
EP1  
0
FF  
FF  
00000000 RW  
[10,11]  
EP2FIFOIRQ  
Endpoint 2 slave FIFO  
Flag Interrupt Request  
0
EDGEPF  
0
00000000 rrrrrbbb  
00000000 RW  
EP4FIFOIE  
Endpoint 4 slave FIFO  
Flag Interrupt Enable  
0
0
0
0
PF  
FF  
[10,11]  
[10,11]  
[10,11]  
EP4FIFOIRQ  
Endpoint 4 slave FIFO  
Flag Interrupt Request  
0
0
0
0
PF  
FF  
00000000 rrrrrbbb  
00000000 RW  
EP6FIFOIE  
Endpoint 6 slave FIFO  
Flag Interrupt Enable  
0
0
0
0
EDGEPF  
0
PF  
FF  
EP6FIFOIRQ  
Endpoint 6 slave FIFO  
Flag Interrupt Request  
0
0
0
0
PF  
FF  
00000000 rrrrrbbb  
00000000 RW  
EP8FIFOIE  
EP8FIFOIRQ  
IBNIE  
Endpoint 8 slave FIFO  
Flag Interrupt Enable  
0
0
0
0
EDGEPF  
0
PF  
FF  
Endpoint 8 slave FIFO  
Flag Interrupt Request  
0
0
0
0
PF  
FF  
00000000 rrrrrbbb  
00000000 RW  
IN-BULK-NAK Interrupt  
Enable  
0
0
EP8  
EP8  
EP4  
EP4  
EP6  
EP6  
EP2  
EP2  
EP4  
EP2  
EP2  
EP0  
EP0  
EP0  
EP0  
IBN  
IBN  
[11]  
IBNIRQ  
IN-BULK-NAK interrupt  
Request  
0
0
EP4  
00xxxxxx rrbbbbbb  
00000000 RW  
NAKIE  
Endpoint Ping-NAK/IBN  
Interrupt Enable  
EP8  
EP8  
EP6  
EP6  
EP1  
NAKIRQ  
Endpoint Ping-NAK/IBN  
Interrupt Request  
EP1  
0
xxxxxx0x bbbbbbrb  
E65C  
E65D  
1
1
USBIE  
USB Int Enables  
0
0
EP0ACK  
EP0ACK  
HSGRANT  
HSGRANT  
URES  
URES  
SUSP  
SUSP  
SUTOK  
SUTOK  
SOF  
SOF  
SUDAV 00000000 RW  
USBIRQ  
USB Interrupt Requests  
SUDAV 0xxxxxxx rbbbbbbb  
Note  
11. The register can only be reset, it cannot be set.  
Document # 001-06120 Rev *F  
Page 17 of 39  
 
CY7C68053  
Table 5-1. FX2LP18 Register Summary (continued)  
Hex Size Name  
Description  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Default  
Access  
E65E  
1
EPIE  
Endpoint Interrupt  
Enables  
EP8  
EP6  
EP4  
EP2  
EP1OUT  
EP1IN  
EP0OUT  
EP0IN  
00000000 RW  
[10]  
E65F  
1
EPIRQ  
Endpoint Interrupt  
Requests  
EP8  
EP6  
EP4  
EP2  
EP1OUT  
EP1IN  
EP0OUT  
EP0IN  
0
RW  
E660  
E661  
E662  
1
1
1
GPIFIE  
GPIF Interrupt Enable  
GPIF Interrupt Request  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIFWF  
GPIFWF  
0
GPIFDONE 00000000 RW  
GPIFDONE 000000xx RW  
ERRLIMIT 00000000 RW  
GPIFIRQ  
USBERRIE  
USB Error Interrupt  
Enables  
ISOEP8  
ISOEP6  
ISOEP4  
ISOEP2  
E663  
E664  
1
1
USBERRIRQ  
ERRCNTLIM  
USB Error Interrupt  
Requests  
ISOEP8  
EC3  
ISOEP6  
EC2  
ISOEP4  
EC1  
ISOEP2  
EC0  
0
0
0
ERRLIMIT 0000000x bbbbrrrb  
USB Error counter and  
limit  
LIMIT3  
LIMIT2  
LIMIT1  
LIMIT0  
xxxx0100 rrrrbbbb  
xxxxxxxx  
E665  
E666  
1
1
CLRERRCNT  
INT2IVEC  
Clear Error Counter EC3:0  
x
x
x
x
x
x
x
x
W
Interrupt 2 (USB)  
Autovector  
0
I2V4  
I2V3  
I2V2  
I2V1  
I2V0  
0
0
00000000 R  
E667  
E668  
E669  
1
1
7
Reserved  
1
0
0
0
0
0
0
0
0
0
0
0
0
10000000 R  
INTSET-UP  
Reserved  
Interrupt 2&4 set-up  
AV2EN  
Reserved  
AV4EN  
00000000 RW  
INPUT/OUTPUT  
PORTACFG  
E670  
E671  
E672  
1
1
1
I/O PORTA Alternate  
Configuration  
FLAGD  
GPIFA7  
GPIFA8  
SLCS  
GPIFA6  
T2EX  
0
0
0
0
INT1  
INT0  
00000000 RW  
PORTCCFG  
PORTECFG  
I/O PORTC Alternate  
Configuration  
GPIFA5  
INT6  
GPIFA4  
GPIFA3  
GPIFA2  
T2OUT  
GPIFA1  
T1OUT  
GPIFA0 00000000 RW  
I/O PORTE Alternate  
Configuration  
RXD1OUT RXD0OUT  
T0OUT  
00000000 RW  
E673  
E677  
E678  
4
1
1
Reserved  
Reserved  
I2CS  
I²C Bus  
START  
d7  
STOP  
d6  
LASTRD  
ID1  
d4  
0
ID0  
d3  
0
BERR  
d2  
ACK  
d1  
DONE  
d0  
000xx000 bbbrrrrr  
xxxxxxxx RW  
Control & Status  
E679  
E67A  
E67B  
E67C  
1
1
1
1
I2DAT  
I²C Bus  
Data  
d5  
0
I2CTL  
I²C Bus  
Control  
0
0
0
STOPIE  
D1  
400KHZ 00000000 RW  
XAUTODAT1  
XAUTODAT2  
UDMA CRC  
Autoptr1 MOVX access,  
when APTREN=1  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D0  
D0  
xxxxxxxx RW  
xxxxxxxx RW  
Autoptr2 MOVX access,  
when APTREN=1  
D7  
D1  
[10]  
E67D  
E67E  
E67F  
1
1
1
UDMACRCH  
UDMA CRC MSB  
UDMA CRC LSB  
UDMA CRC Qualifier  
CRC15  
CRC7  
CRC14  
CRC6  
0
CRC13  
CRC5  
0
CRC12  
CRC4  
0
CRC11  
CRC3  
CRC10  
CRC2  
CRC9  
CRC1  
CRC8  
CRC0  
01001010 RW  
10111010 RW  
UDMACRCL  
UDMACRC-  
QUALIFIER  
QENABLE  
QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb  
USB CONTROL  
USBCS  
E680  
E681  
E682  
E683  
E684  
E685  
E686  
E687  
E688  
1
1
1
1
1
1
1
1
2
USB Control & Status  
Put chip into suspend  
Wakeup Control & Status  
Toggle Control  
HSM  
x
0
x
0
0
DISCON NOSYNSOF RENUM  
SIGRSUME x0000000 rrrrbbbb  
SUSPEND  
WAKEUPCS  
TOGCTL  
x
x
WUPOL  
IO  
x
0
x
x
WU2EN  
EP1  
x
xxxxxxxx  
W
WU2  
Q
WU  
S
WU2POL  
DPEN  
EP2  
FC10  
FC2  
MF2  
FA2  
WUEN  
EP0  
FC8  
FC0  
MF0  
FA0  
xx000101 bbbbrbbb  
x0000000 rrrbbbbb  
00000xxx R  
R
0
EP3  
0
USBFRAMEH  
USBFRAMEL  
MICROFRAME  
FNADDR  
USB Frame count H  
USB Frame count L  
Microframe count, 0-7  
USB Function address  
0
0
0
FC9  
FC7  
0
FC6  
0
FC5  
0
FC4  
0
FC3  
0
FC1  
xxxxxxxx  
00000xxx R  
0xxxxxxx R  
R
MF1  
FA1  
0
FA6  
FA5  
FA4  
FA3  
Reserved  
ENDPOINTS  
[10]  
E68A  
E68B  
E68C  
E68D  
1
1
1
1
EP0BCH  
Endpoint 0 Byte Count H  
Endpoint 0 Byte Count L  
(BC15)  
(BC7)  
(BC14)  
BC6  
(BC13)  
BC5  
(BC12)  
BC4  
(BC11)  
BC3  
(BC10)  
BC2  
(BC9)  
BC1  
(BC8)  
BC0  
xxxxxxxx RW  
xxxxxxxx RW  
EP0BCL  
Reserved  
EP1OUTBC  
Endpoint 1 OUT Byte  
Count  
0
BC6  
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
0xxxxxxx RW  
E68E  
E68F  
E690  
E691  
E692  
E694  
E695  
E696  
E698  
E699  
E69A  
E69C  
E69D  
E69E  
E6A0  
1
1
1
1
2
1
1
2
1
1
2
1
1
2
1
Reserved  
EP1INBC  
Endpoint 1 IN Byte Count  
Endpoint 2 Byte Count H  
Endpoint 2 Byte Count L  
0
0
BC6  
0
BC5  
0
BC4  
0
BC3  
0
BC2  
BC10  
BC2  
BC1  
BC9  
BC1  
BC0  
BC8  
BC0  
0xxxxxxx RW  
00000xxx RW  
xxxxxxxx RW  
[10]  
EP2BCH  
EP2BCL  
BC7/SKIP  
BC6  
BC5  
BC4  
BC3  
Reserved  
[10]  
EP4BCH  
Endpoint 4 Byte Count H  
Endpoint 4 Byte Count L  
0
0
0
0
0
0
BC9  
BC1  
BC8  
BC0  
000000xx RW  
xxxxxxxx RW  
EP4BCL  
BC7/SKIP  
BC6  
BC5  
BC4  
BC3  
BC2  
Reserved  
[10]  
EP6BCH  
Endpoint 6 Byte Count H  
Endpoint 6 Byte Count L  
0
0
0
0
0
BC10  
BC2  
BC9  
BC1  
BC8  
BC0  
00000xxx RW  
xxxxxxxx RW  
EP6BCL  
BC7/SKIP  
BC6  
BC5  
BC4  
BC3  
Reserved  
[10]  
EP8BCH  
Endpoint 8 Byte Count H  
Endpoint 8 Byte Count L  
0
0
0
0
0
0
BC9  
BC1  
BC8  
BC0  
000000xx RW  
xxxxxxxx RW  
EP8BCL  
BC7/SKIP  
BC6  
BC5  
BC4  
BC3  
BC2  
Reserved  
EP0CS  
Endpoint 0 Control and  
Status  
HSNAK  
0
0
0
0
0
BUSY  
STALL  
10000000 bbbbbbrb  
Document # 001-06120 Rev *F  
Page 18 of 39  
CY7C68053  
Table 5-1. FX2LP18 Register Summary (continued)  
Hex Size Name  
Description  
b7  
0
b6  
0
b5  
0
b4  
0
b3  
0
b2  
0
b1  
b0  
Default  
Access  
E6A1  
E6A2  
E6A3  
E6A4  
E6A5  
E6A6  
E6A7  
E6A8  
E6A9  
E6AA  
E6AB  
E6AC  
E6AD  
E6AE  
E6AF  
E6B0  
E6B1  
E6B2  
E6B3  
E6B4  
E6B5  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EP1OUTCS  
Endpoint 1 OUT Control  
and Status  
BUSY  
STALL  
00000000 bbbbbbrb  
00000000 bbbbbbrb  
00101000 rrrrrrrb  
00101000 rrrrrrrb  
00000100 rrrrrrrb  
00000100 rrrrrrrb  
00000010 R  
EP1INCS  
Endpoint 1 IN Control and  
Status  
0
0
0
0
0
NPAK0  
NPAK0  
NPAK0  
NPAK0  
0
0
FULL  
FULL  
FULL  
FULL  
0
0
EMPTY  
EMPTY  
EMPTY  
EMPTY  
PF  
BUSY  
0
STALL  
STALL  
STALL  
STALL  
STALL  
FF  
EP2CS  
Endpoint 2 Control and  
Status  
NPAK2  
NPAK1  
EP4CS  
Endpoint 4 Control and  
Status  
0
0
NPAK1  
0
EP6CS  
Endpoint 6 Control and  
Status  
0
NPAK2  
NPAK1  
0
EP8CS  
Endpoint 8 Control and  
Status  
0
0
0
NPAK1  
0
EP2FIFOFLGS  
EP4FIFOFLGS  
EP6FIFOFLGS  
EP8FIFOFLGS  
EP2FIFOBCH  
EP2FIFOBCL  
EP4FIFOBCH  
EP4FIFOBCL  
EP6FIFOBCH  
EP6FIFOBCL  
EP8FIFOBCH  
EP8FIFOBCL  
SUDPTRH  
Endpoint 2 slave FIFO  
Flags  
0
0
0
EF  
Endpoint 4 slave FIFO  
Flags  
0
0
0
0
PF  
EF  
FF  
00000010 R  
Endpoint 6 slave FIFO  
Flags  
0
0
0
0
0
PF  
EF  
FF  
00000110 R  
Endpoint 8 slave FIFO  
Flags  
0
0
0
0
0
PF  
EF  
FF  
00000110 R  
Endpoint 2 slave FIFO  
total byte count H  
0
0
0
BC12  
BC4  
0
BC11  
BC3  
0
BC10  
BC2  
BC10  
BC2  
BC10  
BC2  
BC10  
BC2  
A10  
BC9  
BC1  
BC9  
BC1  
BC9  
BC1  
BC9  
BC1  
A9  
BC8  
BC0  
BC8  
BC0  
BC8  
BC0  
BC8  
BC0  
A8  
00000000 R  
Endpoint 2 slave FIFO  
total byte count L  
BC7  
0
BC6  
0
BC5  
0
00000000 R  
Endpoint 4 slave FIFO  
total byte count H  
00000000 R  
Endpoint 4 slave FIFO  
total byte count L  
BC7  
0
BC6  
0
BC5  
0
BC4  
0
BC3  
BC11  
BC3  
0
00000000 R  
Endpoint 6 slave FIFO  
total byte count H  
00000000 R  
Endpoint 6 slave FIFO  
total byte count L  
BC7  
0
BC6  
0
BC5  
0
BC4  
0
00000000 R  
Endpoint 8 slave FIFO  
total byte count H  
00000000 R  
Endpoint 8 slave FIFO  
total byte count L  
BC7  
A15  
A7  
0
BC6  
A14  
A6  
0
BC5  
A13  
A5  
0
BC4  
A12  
A4  
BC3  
A11  
A3  
00000000 R  
Set-up Data Pointer high  
address byte  
xxxxxxxx RW  
xxxxxxx0 bbbbbbbr  
SUDPTRL  
Set-up Data Pointer low  
address byte  
A2  
A1  
0
SUDPTRCTL  
Set-up Data Pointer Auto  
Mode  
0
0
0
0
SDPAUTO 00000001 RW  
2
8
Reserved  
E6B8  
SET-UPDAT  
8 bytes of set-up data  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
xxxxxxxx  
R
SET-UPDAT[0] =  
bmRequestType  
SET-UPDAT[1] =  
bmRequest  
SET-UPDAT[2:3] = wVal-  
ue  
SET-UPDAT[4:5] = wInd-  
ex  
SET-UPDAT[6:7] =  
wLength  
GPIF  
E6C0  
E6C1  
1
1
GPIFWFSELECT  
GPIFIDLECS  
Waveform Selector  
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0  
FIFORD1  
0
FIFORD0 11100100 RW  
IDLEDRV 10000000 RW  
GPIF Done, GPIF IDLE  
drive mode  
DONE  
0
0
0
0
0
E6C2  
E6C3  
E6C4  
E6C5  
1
1
1
1
GPIFIDLECTL  
GPIFCTLCFG  
Reserved  
Inactive Bus, CTL states  
CTL Drive Type  
0
0
0
0
0
0
0
0
0
CTL2  
CTL2  
CTL1  
CTL1  
CTL0  
CTL0  
11111111 RW  
00000000 RW  
00000000  
TRICTL  
Reserved  
00000000  
FLOWSTATE  
FLOWSTATE  
E6C6  
1
Flowstate Enable and  
Selector  
FSE  
0
0
0
0
FS2  
FS1  
FS0  
00000000 brrrrbbb  
E6C7  
E6C8  
1
1
FLOWLOGIC  
Flowstate Logic  
LFUNC1  
CTL0E3  
LFUNC0  
CTL0E2  
TERMA2  
CTL0E1  
TERMA1  
CTL0E0  
TERMA0  
0
TERMB2  
CTL2  
TERMB1  
CTL1  
TERMB0 00000000 RW  
FLOWEQ0CTL  
CTL-Pin States in  
Flowstate  
(when Logic = 0)  
CTL0  
00000000 RW  
E6C9  
E6CA  
E6CB  
E6CC  
1
1
1
1
FLOWEQ1CTL  
FLOWHOLDOFF  
FLOWSTB  
CTL-Pin States in Flow-  
state (when Logic = 1)  
CTL0E3  
CTL0E2  
CTL0E1  
CTL0E0  
0
CTL2  
HOCTL2  
MSTB2  
0
CTL1  
CTL0  
00000000 RW  
Holdoff Configuration  
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE  
0
HOCTL1  
MSTB1  
FALLING  
HOCTL0 00010010 RW  
MSTB0 00100000 RW  
RISING 00000001 rrrrrrbb  
Flowstate Strobe  
Configuration  
SLAVE  
RDYASYNC CTLTOGL  
SUSTAIN  
0
FLOWSTBEDGE  
Flowstate Rising/Falling  
Edge Configuration  
0
0
0
0
0
E6CD  
E6CE  
1
1
FLOWSTBPERIOD Master-Strobe Half-Period  
[10]  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
00000010 RW  
00000000 RW  
GPIFTCB3  
GPIF Transaction Count  
Byte 3  
TC31  
TC30  
TC29  
TC28  
TC27  
TC26  
TC25  
TC24  
Document # 001-06120 Rev *F  
Page 19 of 39  
CY7C68053  
Table 5-1. FX2LP18 Register Summary (continued)  
Hex Size Name  
Description  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Default  
Access  
[10]  
[10]  
[10]  
E6CF  
E6D0  
E6D1  
1
1
1
2
GPIFTCB2  
GPIFTCB1  
GPIFTCB0  
GPIF Transaction Count  
Byte 2  
TC23  
TC22  
TC21  
TC20  
TC19  
TC18  
TC17  
TC16  
00000000 RW  
00000000 RW  
00000001 RW  
00000000 RW  
GPIF Transaction Count  
Byte 1  
TC15  
TC7  
TC14  
TC6  
TC13  
TC5  
TC12  
TC4  
TC11  
TC3  
TC10  
TC2  
TC9  
TC1  
TC8  
TC0  
GPIF Transaction Count  
Byte 0  
Reserved  
Reserved  
Reserved  
E6D2  
E6D3  
E6D4  
1
1
EP2GPIFFLGSEL  
Endpoint 2 GPIF Flag  
select  
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1  
0
FS0  
00000000 RW  
EP2GPIFPFSTOP Endpoint 2 GPIF stop  
FIFO2FLAG 00000000 RW  
transaction on prog. flag  
1
3
EP2GPIFTRIG  
Reserved  
Endpoint 2 GPIF Trigger  
x
x
xxxxxxxx  
W
Reserved  
Reserved  
E6DA  
E6DB  
E6DC  
1
1
EP4GPIFFLGSEL  
Endpoint 4 GPIF Flag  
select  
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1  
0
FS0  
00000000 RW  
EP4GPIFPFSTOP Endpoint 4 GPIF stop  
FIFO4FLAG 00000000 RW  
transaction on GPIF Flag  
1
3
EP4GPIFTRIG  
Reserved  
Endpoint 4 GPIF Trigger  
x
x
xxxxxxxx  
W
Reserved  
Reserved  
E6E2  
E6E3  
E6E4  
1
1
EP6GPIFFLGSEL  
Endpoint 6 GPIF Flag  
select  
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1  
0
FS0  
00000000 RW  
EP6GPIFPFSTOP Endpoint 6 GPIF stop  
FIFO6FLAG 00000000 RW  
transaction on prog. flag  
1
3
EP6GPIFTRIG  
Reserved  
Endpoint 6 GPIF Trigger  
x
x
xxxxxxxx  
W
Reserved  
Reserved  
E6EA  
E6EB  
E6EC  
1
1
EP8GPIFFLGSEL  
Endpoint 8 GPIF Flag  
select  
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1  
0
FS0  
00000000 RW  
EP8GPIFPFSTOP Endpoint 8 GPIF stop  
FIFO8FLAG 00000000 RW  
transaction on prog. flag  
1
3
1
EP8GPIFTRIG  
Reserved  
Endpoint 8 GPIF Trigger  
x
x
xxxxxxxx  
W
E6F0  
E6F1  
E6F2  
E6F3  
XGPIFSGLDATH  
GPIF Data H  
(16-bit mode only)  
D15  
D7  
D14  
D6  
D13  
D5  
D12  
D4  
D4  
0
D11  
D3  
D3  
0
D10  
D2  
D2  
0
D9  
D1  
D1  
0
D8  
D0  
D0  
0
xxxxxxxx RW  
xxxxxxxx RW  
1
1
1
XGPIFSGLDATLX  
Read/Write GPIF Data L &  
trigger transaction  
XGPIFSGLDATL-  
NOX  
Read GPIF Data L, no  
transaction trigger  
D7  
D6  
D5  
xxxxxxxx  
R
GPIFREADYCFG  
InternalRDY,Sync/Async,  
RDY pin states  
INTRDY  
SAS  
TCXRDY5  
00000000 bbbrrrrr  
E6F4  
E6F5  
E6F6  
1
1
2
GPIFREADYSTAT  
GPIFABORT  
GPIF Ready Status  
0
x
0
x
0
x
0
x
0
x
0
x
RDY1  
x
RDY0  
x
00xxxxxx R  
Abort GPIF Waveforms  
xxxxxxxx  
W
Reserved  
ENDPOINT BUFFERS  
E740 64 EP0BUF  
EP0-IN/-OUT buffer  
EP1-OUT buffer  
EP1-IN buffer  
D7  
D7  
D7  
D6  
D6  
D6  
D5  
D5  
D5  
D4  
D4  
D4  
D3  
D3  
D3  
D2  
D2  
D2  
D1  
D1  
D1  
D0  
D0  
D0  
xxxxxxxx RW  
xxxxxxxx RW  
xxxxxxxx RW  
RW  
E780 64 EP10UTBUF  
E7C0 64 EP1INBUF  
E800 2048 Reserved  
F000 1024 EP2FIFOBUF  
512/1024-byte EP 2/slave  
FIFO buffer (IN or OUT)  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
xxxxxxxx RW  
F400 512 EP4FIFOBUF  
512 byte EP 4/slave FIFO  
buffer (IN or OUT)  
xxxxxxxx RW  
F600 512 Reserved  
F800 1024 EP6FIFOBUF  
512/1024-byte EP 6/slave  
FIFO buffer (IN or OUT)  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
xxxxxxxx RW  
xxxxxxxx RW  
FC00 512 EP8FIFOBUF  
512 byte EP 8/slave FIFO  
buffer (IN or OUT)  
FE00 512 Reserved  
xxxx  
I²C Configuration Byte  
Special Function Registers (SFRs)  
0
DISCON  
D6  
0
0
0
0
0
400KHZ xxxxxxxx n/a  
80  
1
IOA  
Port A (bit addressable)  
D7  
D5  
D4  
D3  
D2  
D1  
D0  
xxxxxxxx RW  
Notes  
12. SFRs not part of the standard 8051 architecture.  
13. If no EEPROM is detected by the SIE then the default is 00000000.  
Document # 001-06120 Rev *F  
Page 20 of 39  
   
CY7C68053  
Table 5-1. FX2LP18 Register Summary (continued)  
Hex Size Name  
Description  
b7  
D7  
b6  
D6  
A6  
A14  
A6  
A14  
0
b5  
D5  
A5  
A13  
A5  
A13  
0
b4  
D4  
A4  
A12  
A4  
A12  
0
b3  
D3  
A3  
A11  
A3  
A11  
0
b2  
D2  
A2  
A10  
A2  
A10  
0
b1  
D1  
A1  
A9  
A1  
A9  
0
b0  
D0  
Default  
Access  
81  
82  
83  
84  
85  
86  
87  
88  
1
1
1
1
1
1
1
1
SP  
Stack Pointer  
00000111 RW  
00000000 RW  
00000000 RW  
00000000 RW  
00000000 RW  
00000000 RW  
00110000 RW  
00000000 RW  
DPL0  
DPH0  
Data Pointer 0 L  
Data Pointer 0 H  
Data Pointer 1 L  
Data Pointer 1 H  
Data Pointer 0/1 select  
Power Control  
A7  
A0  
A15  
A7  
A8  
DPL1  
DPH1  
A0  
[12]  
A15  
0
A8  
DPS  
SEL  
IDLE  
IT0  
PCON  
TCON  
SMOD0  
TF1  
x
1
1
x
x
x
Timer/Counter Control  
(bit addressable)  
TR1  
TF0  
TR0  
IE1  
IT1  
IE0  
89  
1
TMOD  
Timer/Counter Mode  
Control  
GATE  
CT  
M1  
M0  
GATE  
CT  
M1  
M0  
00000000 RW  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
1
1
1
1
1
1
1
1
1
TL0  
Timer 0 reload L  
Timer 1 reload L  
Timer 0 reload H  
Timer 1 reload H  
Clock Control  
D7  
D7  
D15  
D15  
x
D6  
D6  
D14  
D14  
x
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
00000000 RW  
00000000 RW  
00000000 RW  
00000000 RW  
00000001 RW  
TL1  
TH0  
D13  
D13  
T2M  
D12  
D12  
T1M  
D11  
D11  
T0M  
D10  
D10  
MD2  
D9  
D8  
TH1  
D9  
D8  
[12]  
CKCON  
MD1  
MD0  
Reserved  
IOB  
Port B (bit addressable)  
External Interrupt Flag(s)  
D7  
IE5  
A15  
D6  
IE4  
A14  
D5  
I²CINT  
A13  
D4  
USBNT  
A12  
D3  
1
D2  
0
D1  
0
D0  
0
xxxxxxxx RW  
00001000 RW  
00000000 RW  
EXIF  
[12]  
MPAGE  
Upper Addr Byte of MOVX  
using @R0/@R1  
A11  
A10  
A9  
A8  
93  
98  
5
1
Reserved  
SCON0  
Serial Port 0 Control  
(bit addressable)  
SM0_0  
SM1_0  
SM2_0  
REN_0  
TB8_0  
RB8_0  
TI_0  
RI_0  
00000000 RW  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A8  
1
1
1
1
1
1
1
1
1
1
5
1
SBUF0  
Serial Port 0 Data Buffer  
Autopointer 1 Address H  
Autopointer 1 Address L  
D7  
A15  
A7  
D6  
A14  
A6  
D5  
A13  
A5  
D4  
A12  
A4  
D3  
A11  
A3  
D2  
A10  
A2  
D1  
A9  
A1  
D0  
A8  
A0  
00000000 RW  
00000000 RW  
00000000 RW  
[12]  
AUTOPTRH1  
AUTOPTRL1  
Reserved  
[12]  
AUTOPTRH2  
Autopointer 2 Address H  
Autopointer 2 Address L  
A15  
A7  
A14  
A6  
A13  
A5  
A12  
A4  
A11  
A3  
A10  
A2  
A9  
A1  
A8  
A0  
00000000 RW  
00000000 RW  
AUTOPTRL2  
Reserved  
[12]  
IOC  
Port C (bit addressable)  
Interrupt 2 clear  
D7  
x
D6  
x
D5  
x
D4  
x
D3  
x
D2  
x
D1  
x
D0  
x
xxxxxxxx RW  
INT2CLR  
xxxxxxxx  
xxxxxxxx  
W
W
Reserved  
Reserved  
IE  
x
x
x
x
x
x
x
x
Interrupt Enable  
(bit addressable)  
EA  
ES1  
ET2  
ES0  
ET1  
EX1  
ET0  
EX0  
00000000 RW  
A9  
AA  
1
1
Reserved  
EP2468STAT  
Endpoint 2,4,6,8 status  
flags  
EP8F  
EP8E  
EP4PF  
EP8PF  
EP6F  
EP4EF  
EP8EF  
EP6E  
EP4FF  
EP8FF  
EP4F  
EP4E  
EP2PF  
EP6PF  
EP2F  
EP2EF  
EP6EF  
EP2E  
EP2FF  
EP6FF  
01011010 R  
00100010 R  
01100110 R  
AB  
AC  
1
1
EP24FIFOFLGS  
Endpoint 2,4 slave FIFO  
status flags  
0
0
0
0
EP68FIFOFLGS  
Endpoint 6,8 slave FIFO  
status flags  
AD  
AF  
B0  
B1  
2
1
1
1
Reserved  
AUTOPTRSETUP  
Autopointer 1&2 set-up  
Port D (bit addressable)  
0
0
0
0
0
APTR2INC APTR1INC  
APTREN 00000110 RW  
[12]  
IOD  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
xxxxxxxx RW  
xxxxxxxx RW  
IOE  
Port E  
(NOT bit addressable)  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
1
1
1
1
1
1
1
OEA  
Port A Output Enable  
Port B Output Enable  
Port C Output Enable  
Port D Output Enable  
Port E Output Enable  
D7  
D7  
D7  
D7  
D7  
D6  
D6  
D6  
D6  
D6  
D5  
D5  
D5  
D5  
D5  
D4  
D4  
D4  
D4  
D4  
D3  
D3  
D3  
D3  
D3  
D2  
D2  
D2  
D2  
D2  
D1  
D1  
D1  
D1  
D1  
D0  
D0  
D0  
D0  
D0  
00000000 RW  
00000000 RW  
00000000 RW  
00000000 RW  
00000000 RW  
OEB  
[12]  
OEC  
[12]  
OED  
OEE  
Reserved  
IP  
Interrupt Priority (bit ad-  
dressable)  
1
PS1  
PT2  
PS0  
PT1  
PX1  
PT0  
PX0  
10000000 RW  
B9  
BA  
BB  
1
1
1
Reserved  
EP01STAT  
Endpoint 0&1 Status  
0
0
0
0
0
0
0
0
0
EP1INBSY EP1OUTBSY EP0BSY 00000000 R  
GPIFTRIG  
Endpoint 2,4,6,8 GPIF  
slave FIFO Trigger  
DONE  
RW  
EP1  
EP0  
10000xxx brrrrbbb  
BC  
BD  
1
1
Reserved  
GPIFSGLDATH  
GPIF Data H (16-bit mode  
only)  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
xxxxxxxx RW  
xxxxxxxx RW  
BE  
BF  
1
1
GPIFSGLDATLX  
GPIFSGLDATL-  
GPIF Data L w/Trigger  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
GPIF Data L w/No Trigger  
xxxxxxxx  
R
[12]  
NOX  
C0  
1
SCON1  
Serial Port 1 Control (bit  
addressable)  
SM0_1  
D7  
SM1_1  
D6  
SM2_1  
D5  
REN_1  
D4  
TB8_1  
D3  
RB8_1  
D2  
TI_1  
D1  
RI_1  
D0  
00000000 RW  
00000000 RW  
C1  
C2  
C8  
1
6
1
SBUF1  
Serial Port 1 Data Buffer  
Reserved  
T2CON  
Timer/Counter 2 Control  
(bit addressable)  
TF2  
EXF2  
RCLK  
TCLK  
EXEN2  
TR2  
CT2  
CPRL2  
00000000 RW  
Document # 001-06120 Rev *F  
Page 21 of 39  
CY7C68053  
Table 5-1. FX2LP18 Register Summary (continued)  
Hex Size Name  
Description  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Default  
Access  
C9  
CA  
1
1
Reserved  
RCAP2L  
Capture for Timer 2, auto-  
reload, up-counter  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
00000000 RW  
00000000 RW  
CB  
1
RCAP2H  
Capture for Timer 2, auto-  
reload, up-counter  
CC  
CD  
CE  
D0  
1
1
2
1
TL2  
Timer 2 reload L  
Timer 2 reload H  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D9  
D0  
D8  
00000000 RW  
00000000 RW  
TH2  
D15  
D14  
D13  
D12  
D11  
D10  
Reserved  
PSW  
Program Status Word (bit  
addressable)  
CY  
AC  
F0  
RS1  
RS0  
OV  
F1  
P
00000000 RW  
D1  
D8  
D9  
E0  
7
1
7
1
Reserved  
[12]  
EICON  
External Interrupt Control  
SMOD1  
D7  
1
ERESI  
D5  
RESI  
D4  
INT6  
D3  
0
0
0
01000000 RW  
00000000 RW  
Reserved  
ACC  
Accumulator (bit address-  
able)  
D6  
D2  
D1  
D0  
E1  
E8  
7
1
Reserved  
EIE  
External Interrupt En-  
able(s)  
1
1
1
EX6  
EX5  
EX4  
EI²C  
EUSB  
11100000 RW  
E9  
F0  
F1  
F8  
7
1
7
1
Reserved  
B
B (bit addressable)  
D7  
1
D6  
1
D5  
1
D4  
D3  
D2  
D1  
D0  
00000000 RW  
11100000 RW  
Reserved  
EIP  
External Interrupt Priority  
Control  
PX6  
PX5  
PX4  
PI²C  
PUSB  
F9  
7
Reserved  
Ledgend  
R = all bits read-only  
W = all bits write-only  
r = read-only bit  
w = write-only bit  
b = both read/write bit  
Document # 001-06120 Rev *F  
Page 22 of 39  
CY7C68053  
6.0  
Absolute Maximum Ratings  
Storage Temperature ...........................................................................................................................................– 65°C to +150°C  
Ambient Temperature with Power Supplied  
Industrial ................................................................................................................................................................– 40°C to +85°C  
Supply Voltage to Ground Potential  
For 3.3V Power domain ..........................................................................................................................................0.5V to +4.0V  
For 1.8V Power domain ..........................................................................................................................................0.5V to +2.0V  
DC Input Voltage to Any Input Pin  
For pins under 3.3V Power Domain.................................................................................................................................... 3.6V  
For pins under 1.8V - 3.3V Power Domain (GPIO’s) ............................................................................................1.89V to 3.6V  
(The GPIO’s are not over voltage tolerant, except the SCL and SDA pins, which are 3.3V tolerant)  
DC Voltage Applied to Outputs in High Z State............................................................................................ – 0.5V to VCC + 0.5V  
Maximum Power Dissipation  
From AVcc Supply ............................................................................................................................................................... 90 mW  
From IO Supply....................................................................................................................................................................36 mW  
From Core Supply................................................................................................................................................................95 mW  
Static Discharge Voltage....................................................................................................................................................> 2000V  
(I2C SCL and SDA pins only ... >1500V)  
Maximum Output Current, per I/O port .................................................................................................................................10 mA  
7.0  
Operating Conditions  
T (Ambient Temperature Under Bias)  
A
Industrial ............................................................................................................................................................... – 40°C to +85°C  
Supply Voltage  
3.3V Power Supply ......................................................................................................................................................3.0V to 3.6V  
1.8V Power Supply ...................................................................................................................................................1.71V to1.89V  
Ground Voltage........................................................................................................................................................................... 0V  
F
(Oscillator or Crystal Frequency)............................................................................................................. 24 MHz ± 100 ppm  
OSC  
............................................................................................................................................................................ Parallel Resonant  
...........................................................................................................................................................................500 µW drive level  
Load capacitors 12 pF  
Note  
14. It is recommended to not power I/O when chip power is off.  
Document # 001-06120 Rev *F  
Page 23 of 39  
 
CY7C68053  
8.0  
DC Characteristics  
Table 8-1. DC Characteristics  
Parameter Description  
Conditions  
Min.  
3.00  
1.71  
1.71  
1.71  
Typ.  
3.3  
1.8  
1.8  
1.8  
Max.  
3.60  
3.60  
1.89  
1.89  
Unit  
V
AV  
3.3 V supply (to Osc. and PHY)  
1.8V to 3.3V supply (to I/O)  
1.8 V supply to Analog Core  
1.8 V supply to Digital Core  
Input HIGH Voltage  
CC  
CC_IO  
CC_A  
CC_D  
IH  
V
V
V
V
V
V
V
V
V
V
V
+10%  
0.6*V  
V
CC_IO  
CC_IO  
Input LOW Voltage  
0
0.3*V  
V
IL  
CC_IO  
Crystal Input HIGH Voltage  
Crystal Input LOW Voltage  
Hysteresis  
2.0  
–0.5  
50  
3.60  
V
IH_X  
IL_X  
0.8  
V
mV  
µA  
V
I
Input Leakage Current  
Output Voltage HIGH  
Output LOW Voltage  
0< V < V  
±10  
I
IN  
CC_IO  
V
V
I
I
= 4 mA  
V
– 0.4  
OH  
OUT  
OUT  
CC_IO  
= –4 mA  
0.4  
4
V
OL  
I
I
Output Current HIGH  
Output Current LOW  
mA  
mA  
pF  
pF  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
ms  
µs  
OH  
OL  
4
C
Input Pin Capacitance  
Except D+/D–  
10  
15  
IN  
D+/D–  
I
Suspend Current  
Connected  
220  
20  
15  
10  
3
380  
150  
SUSP  
Disconnected  
I
I
I
Supply Current (AV  
)
CC  
8051 running, connected to USB HS  
8051 running, connected to USB FS  
8051 running, connected to USB HS  
8051 running, connected to USB FS  
8051 running, connected to USB HS  
8051 running, connected to USB FS  
VCC min = 3.0V  
25  
CC_AVcc  
CC_IO  
20  
10  
5
Supply Current (V  
Supply Current (V  
)
CC_IO  
1
)
CC_CORE  
32  
24  
50  
40  
CC_CORE  
T
Reset Time after Valid Power  
Pin Reset after powered on  
5.0  
RESET  
200  
Notes  
15. The pins for this supply can be floated in low-power mode.  
16. Measured at Maximum V , 25°C.  
CC  
Document # 001-06120 Rev *F  
Page 24 of 39  
   
CY7C68053  
9.0  
9.1  
AC Electrical Characteristics  
USB Transceiver  
USB 2.0-compliant in full- and high-speed modes.  
9.2 GPIF Synchronous Signals  
Figure 9-1. GPIF Synchronous Signals Timing Diagram  
t
IFCLK  
IFCLK  
A  
RDY  
X
t
SRY  
t
RYH  
DATA(input)  
valid  
t
SGD  
t
DAH  
CTLX  
t
XCTL  
DATA(output)  
N
N+1  
t
XGD  
[17,18]  
Table 9-1. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK  
Parameter Description Min.  
Max.  
Unit  
ns  
t
t
t
t
t
t
t
IFCLK Period  
RDY to Clock Set-up Time  
20.83  
8.9  
0
IFCLK  
ns  
SRY  
RYH  
SGD  
DAH  
XGD  
XCTL  
X
Clock to RDY  
ns  
X
GPIF Data to Clock Set-up Time  
GPIF Data Hold Time  
9.2  
0
ns  
ns  
Clock to GPIF Data Output Propagation Delay  
11  
ns  
Clock to CTL Output Propagation Delay  
6.7  
ns  
X
8
Table 9-2. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK  
Parameter Description Min.  
Max.  
Unit  
ns  
t
t
t
t
t
t
t
IFCLK Period  
RDY to Clock Set-up Time  
20.83  
2.9  
200  
IFCLK  
ns  
SRY  
RYH  
SGD  
DAH  
XGD  
XCTL  
X
Clock to RDY  
3.7  
ns  
X
GPIF Data to Clock Set-up Time  
GPIF Data Hold Time  
3.2  
ns  
4.5  
ns  
Clock to GPIF Data Output Propagation Delay  
15  
ns  
Clock to CTL Output Propagation Delay  
13.06  
ns  
X
Notes  
17. Dashed lines denote signals with programmable polarity.  
18. GPIF asynchronous RDY signals have a minimum set-up time of 50 ns when using internal 48 MHz IFCLK.  
x
19. IFCLK must not exceed 48 MHz.  
Document # 001-06120 Rev *F  
Page 25 of 39  
     
CY7C68053  
9.3  
Slave FIFO Synchronous Read  
Figure 9-2. Slave FIFO Synchronous Read Timing Diagram  
t
IFCLK  
IFCLK  
SLRD  
t
RDH  
t
SRD  
t
XFLG  
FLAGS  
DATA  
N+1  
N
t
t
XFD  
OEon  
t
OEoff  
SLOE  
Table 9-3. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK  
Parameter  
Description  
Min.  
20.83  
18.7  
0
Max.  
Unit  
ns  
t
t
t
t
t
t
t
IFCLK Period  
IFCLK  
SLRD to Clock Set-up Time  
ns  
SRD  
Clock to SLRD Hold Time  
ns  
RDH  
OEon  
OEoff  
XFLG  
XFD  
SLOE Turn-on to FIFO Data Valid  
SLOE Turn-off to FIFO Data Hold  
Clock to FLAGS Output Propagation Delay  
Clock to FIFO Data Output Propagation Delay  
10.5  
10.5  
9.5  
ns  
2.15  
ns  
ns  
11  
ns  
Table 9-4. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK  
Parameter  
Description  
Min.  
20.83  
12.7  
3.7  
Max.  
Unit  
ns  
t
t
t
t
t
t
t
IFCLK Period  
200  
IFCLK  
SLRD to Clock Set-up Time  
ns  
SRD  
Clock to SLRD Hold Time  
ns  
RDH  
OEon  
OEoff  
XFLG  
XFD  
SLOE Turn-on to FIFO Data Valid  
SLOE Turn-off to FIFO Data Hold  
Clock to FLAGS Output Propagation Delay  
Clock to FIFO Data Output Propagation Delay  
10.5  
10.5  
ns  
2.15  
ns  
13.5  
ns  
17.31  
ns  
Document # 001-06120 Rev *F  
Page 26 of 39  
CY7C68053  
9.4  
Slave FIFO Asynchronous Read  
Figure 9-3. Slave FIFO Asynchronous Read Timing Diagram  
t
RDpwh  
SLRD  
t
RDpwl  
t
XFLG  
t
FLAGS  
XFD  
DATA  
SLOE  
N+1  
N
t
t
OEoff  
OEon  
Table 9-5. Slave FIFO Asynchronous Read Parameters  
Parameter Description  
SLRD Pulse Width LOW  
SLRD Pulse Width HIGH  
SLRD to FLAGS Output Propagation Delay  
Min.  
50  
Max.  
Unit  
ns  
t
t
t
t
t
t
RDpwl  
50  
ns  
RDpwh  
XFLG  
XFD  
70  
15  
ns  
SLRD to FIFO Data Output Propagation Delay  
SLOE Turn-on to FIFO Data Valid  
ns  
10.5  
10.5  
ns  
OEon  
OEoff  
SLOE Turn-off to FIFO Data Hold  
2.15  
ns  
Note  
20. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.  
Document # 001-06120 Rev *F  
Page 27 of 39  
 
CY7C68053  
9.5  
Slave FIFO Synchronous Write  
Figure 9-4. Slave FIFO Synchronous Write Timing Diagram  
t
IFCLK  
IFCLK  
SLWR  
t
WRH  
t
SWR  
DATA  
N
Z
Z
t
t
FDH  
SFD  
FLAGS  
t
XFLG  
Table 9-6. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK  
Parameter  
Description  
Min.  
20.83  
18.1  
0
Max.  
Unit  
ns  
t
t
t
t
t
t
IFCLK Period  
IFCLK  
SLWR to Clock Set-up Time  
ns  
SWR  
WRH  
SFD  
Clock to SLWR Hold Time  
ns  
FIFO Data to Clock Set-up Time  
Clock to FIFO Data Hold Time  
Clock to FLAGS Output Propagation Time  
10.64  
0
ns  
ns  
FDH  
9.5  
ns  
XFLG  
Table 9-7. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK  
Parameter  
Description  
Min.  
20.83  
12.1  
3.6  
Max.  
Unit  
ns  
t
t
t
t
t
t
IFCLK Period  
200  
IFCLK  
SLWR to Clock Set-up Time  
ns  
SWR  
WRH  
SFD  
Clock to SLWR Hold Time  
ns  
FIFO Data to Clock Set-up Time  
Clock to FIFO Data Hold Time  
Clock to FLAGS Output Propagation Time  
3.2  
ns  
4.5  
ns  
FDH  
13.5  
ns  
XFLG  
Document # 001-06120 Rev *F  
Page 28 of 39  
CY7C68053  
9.6  
Slave FIFO Asynchronous Write  
Figure 9-5. Slave FIFO Asynchronous Write Timing Diagram  
t
WRpwh  
SLWR/SLCS#  
t
WRpwl  
t
t
FDH  
SFD  
DATA  
t
XFD  
FLAGS  
Table 9-8. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK  
Parameter  
Description  
Min.  
50  
Max.  
Unit  
ns  
t
t
t
t
t
SLWR Pulse LOW  
SLWR Pulse HIGH  
WRpwl  
70  
ns  
WRpwh  
SFD  
SLWR to FIFO DATA Set-up Time  
FIFO DATA to SLWR Hold Time  
10  
ns  
10  
ns  
FDH  
SLWR to FLAGS Output Propagation Delay  
70  
ns  
XFD  
9.7  
Slave FIFO Synchronous Packet End Strobe  
Figure 9-6. Slave FIFO Synchronous Packet End Strobe Timing Diagram  
IFCLK  
t
PEH  
PKTEND  
FLAGS  
t
SPE  
t
XFLG  
Table 9-9. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK  
Parameter  
Description  
Min.  
20.83  
14.6  
0
Max.  
Unit  
ns  
t
t
t
t
IFCLK Period  
IFCLK  
PKTEND to Clock Set-up Time  
ns  
SPE  
Clock to PKTEND Hold Time  
ns  
PEH  
XFLG  
Clock to FLAGS Output Propagation Delay  
9.5  
ns  
Table 9-10. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK  
Parameter  
Description  
Min.  
20.83  
8.6  
Max.  
Unit  
ns  
t
t
t
t
IFCLK Period  
200  
IFCLK  
PKTEND to Clock Set-up Time  
ns  
SPE  
Clock to PKTEND Hold Time  
3.04  
ns  
PEH  
XFLG  
Clock to FLAGS Output Propagation Delay  
13.5  
ns  
Document # 001-06120 Rev *F  
Page 29 of 39  
CY7C68053  
There is no specific timing requirement that needs to be met  
for asserting the PKTEND pin with regards to asserting SLWR.  
PKTEND can be asserted with the last data value clocked into  
the FIFO’s or thereafter. The only consideration is that the set-  
one clock cycle after the rising edge that caused the last  
byte/word to be clocked into the previous auto committed  
packet. Figure 9-7 shows this scenario. X is the value the  
AUTOINLEN register is set to when the IN endpoint is  
configured to be in auto mode.  
up time t  
and the hold time t  
must be met.  
SPE  
PEH  
Although there are no specific timing requirements for the  
PKTEND assertion, there is a specific corner case condition  
that needs attention while using the PKTEND to commit a one  
byte/word packet. There is an additional timing requirement  
that needs to be met when the FIFO is configured to operate  
in auto mode and you want to send two packets back to back:  
a full packet (full defined as the number of bytes in the FIFO  
meeting the level set in AUTOINLEN register) committed  
automatically followed by a short one byte/word packet  
committed manually using the PKTEND pin. In this particular  
scenario, the user must make sure to assert PKTEND at least  
Figure 9-7 shows a scenario where two packets are being  
committed. The first packet gets committed automatically  
when the number of bytes in the FIFO reaches X (value set in  
AUTOINLEN register) and the second one byte/word short  
packet is committed manually using PKTEND. Note that there  
is at least one IFCLK cycle timing between the assertion of  
PKTEND and clocking of the last byte of the previous packet  
(causing the packet to be committed automatically). Failing to  
adhere to this timing, results in the FX2LP18 failing to send the  
one byte/word short packet.  
Figure 9-7. Slave FIFO Synchronous Write Sequence and Timing Diagram  
t
IFCLK  
IFCLK  
t
t
SFA  
FAH  
FIFOADR  
>= t  
WRH  
>= t  
SWR  
SLWR  
DATA  
t
t
t
FDH  
t
t
t
FDH  
t
t
t
FDH  
t
SFD  
FDH  
SFD  
t
SFD  
t
FDH  
SFD  
SFD  
SFD  
FDH  
X-4  
X-2  
X-1  
1
X-3  
X
At least one IFCLK cycle  
t
SPE  
t
PEH  
PKTEND  
9.8  
Slave FIFO Asynchronous Packet End Strobe  
Figure 9-8. Slave FIFO Asynchronous Packet End Strobe Timing Diagram  
t
PEpwh  
PKTEND  
FLAGS  
t
PEpwl  
t
XFLG  
Table 9-11. Slave FIFO Asynchronous Packet End Strobe Parameters  
Parameter Description  
PKTEND Pulse Width LOW  
Min.  
50  
Max.  
Unit  
ns  
t
t
t
PEpwl  
PKTEND Pulse Width HIGH  
50  
ns  
PWpwh  
XFLG  
PKTEND to FLAGS Output Propagation Delay  
115  
ns  
Document # 001-06120 Rev *F  
Page 30 of 39  
 
CY7C68053  
9.9  
Slave FIFO Output Enable  
Figure 9-9. Slave FIFO Output Enable Timing Diagram  
SLOE  
DATA  
t
OEoff  
t
OEon  
Table 9-12. Slave FIFO Output Enable Parameters  
Parameter  
Description  
SLOE Assert to FIFO DATA Output  
SLOE Deassert to FIFO DATA Hold  
Min.  
Max.  
10.5  
10.5  
Unit  
ns  
t
t
OEon  
OEoff  
2.15  
ns  
9.10  
Slave FIFO Address to Flags/Data  
Figure 9-10. Slave FIFO Address to Flags/Data Timing Diagram  
FIFOADR [1.0]  
t
XFLG  
FLAGS  
DATA  
t
XFD  
N
N+1  
Table 9-13. Slave FIFO Address to Flags/Data Parameters  
Parameter Description  
FIFOADR[1:0] to FLAGS Output Propagation Delay  
FIFOADR[1:0] to FIFODATA Output Propagation Delay  
Min.  
Max.  
10.7  
14.3  
Unit  
ns  
t
t
XFLG  
XFD  
ns  
Document # 001-06120 Rev *F  
Page 31 of 39  
CY7C68053  
9.11  
Slave FIFO Synchronous Address  
Figure 9-11. Slave FIFO Synchronous Address Timing Diagram  
IFCLK  
SLCS/FIFOADR [1:0]  
t
t
FAH  
SFA  
Table 9-14. Slave FIFO Synchronous Address Parameters  
Parameter Description  
Interface Clock Period  
Min.  
20.83  
25  
Max.  
Unit  
ns  
t
t
t
200  
IFCLK  
FIFOADR[1:0] to Clock Set-up Time  
Clock to FIFOADR[1:0] Hold Time  
ns  
SFA  
FAH  
10  
ns  
9.12  
Slave FIFO Asynchronous Address  
Figure 9-12. Slave FIFO Asynchronous Address Timing Diagram  
SLCS/FIFOADR [1:0]  
t
FAH  
t
SFA  
SLRD/SLWR/PKTEND  
Slave FIFO Asynchronous Address Parameters  
Parameter Description  
Min.  
Max.  
Unit  
ns  
t
t
FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time  
RD/WR/PKTEND to FIFOADR[1:0] Hold Time  
10  
10  
SFA  
FAH  
ns  
Document # 001-06120 Rev *F  
Page 32 of 39  
CY7C68053  
9.13  
Sequence Diagram  
Various sequence diagrams and examples are presented in this section.  
9.13.1 Single and Burst Synchronous Read Example  
Figure 9-13. Slave FIFO Synchronous Read Sequence and Timing Diagram  
t
IFCLK  
IFCLK  
t
t
SFA  
SFA  
t
t
FAH  
FAH  
FIFOADR  
t=0  
T=0  
t
t
>= t  
SRD  
>= t  
RDH  
RDH  
SRD  
SLRD  
SLCS  
t=3  
t=2  
T=3  
T=2  
t
XFLG  
FLAGS  
DATA  
SLOE  
t
t
XFD  
t
t
XFD  
XFD  
XFD  
N+4  
Data Driven: N  
OEon  
N+2  
N+3  
N+1  
N+1  
t
t
t
OEon  
t
OEoff  
OEoff  
t=4  
T=4  
T=1  
t=1  
Figure 9-14. Slave FIFO Synchronous Sequence of Events Diagram  
IFCLK  
N
IFCLK  
N
IFCLK  
N+1  
IFCLK  
N+1  
IFCLK  
N+1  
IFCLK  
N+2  
IFCLK  
N+3  
IFCLK  
N+4  
IFCLK  
N+4  
IFCLK  
N+4  
FIFO POINTER  
SLOE  
SLRD  
SLOE  
SLRD  
SLOE  
SLRD  
SLRD  
N+4  
SLOE  
FIFO DATA BUS Not Driven  
Driven: N  
N+1  
Not Driven  
N+1  
N+2  
N+3  
N+4  
Not Driven  
Figure 9-13 shows the timing relationship of the SLAVE FIFO  
signals during a synchronous FIFO read using IFCLK as the  
synchronizing clock. The diagram illustrates a single read  
followed by a burst read.  
with SLRD, or before SLRD is asserted (for example, the  
SLCS and SLRD signals must both be asserted to start a  
valid read condition).  
• The FIFO pointer is updated on the rising edge of the IFCLK  
while SLRD is asserted. This starts the propagation of data  
from the newly addressed location to the data bus. After a  
• At t = 0 the FIFO address is stable and the signal SLCS is  
asserted (SLCS may be tied low in some applications).  
Note t  
has a minimum of 25 ns. This means that when  
propagation delay of t  
(measured from the rising edge  
SFA  
XFD  
IFCLK is running at 48 MHz, the FIFO address set-up time  
is more than one IFCLK cycle.  
of IFCLK) the new data value is present. N is the first data  
value read from the FIFO. In order to have data on the FIFO  
data bus, SLOE MUST also be asserted.  
• At t = 1, SLOE is asserted. SLOE is an output enable only  
whose sole function is to drive the data bus. The data that  
is driven on the bus is the data that the internal FIFO pointer  
is currently pointing to. In this example it is the first data  
valueintheFIFO. NoteThedataispre-fetchedandisdriven  
on the bus when SLOE is asserted.  
The same sequence of events is shown for a burst read and is  
marked with the time indicators of T = 0 through 5. Note For  
the burst mode, the SLRD and SLOE are left asserted during  
the entire duration of the read. In the burst read mode, when  
SLOE is asserted, data indexed by the FIFO pointer is on the  
data bus. During the first read cycle on the rising edge of the  
clock, the FIFO pointer is updated and increments to point to  
address N+1. For each subsequent rising edge of IFCLK while  
the SLRD is asserted, the FIFO pointer is incremented and the  
next data value is placed on the data bus.  
• At t = 2, SLRD is asserted. SLRD must meet the set-up  
time of t  
(time from asserting the SLRD signal to the  
SRD  
rising edge of the IFCLK) and maintain a minimum hold time  
of t (time from the IFCLK edge to the deassertion of the  
RDH  
SLRDsignal). IftheSLCSsignalisused, itmustbeasserted  
Document # 001-06120 Rev *F  
Page 33 of 39  
 
CY7C68053  
9.13.2 Single and Burst Synchronous Write  
Figure 9-15. Slave FIFO Synchronous Write Sequence and Timing Diagram  
t
IFCLK  
IFCLK  
t
t
SFA  
t
SFA  
t
FAH  
FAH  
FIFOADR  
>= t  
t=0  
WRH  
t
t
>= t  
T=0  
SWR  
WRH  
SWR  
SLWR  
SLCS  
T=2  
T=5  
t=2  
t=3  
t
XFLG  
t
XFLG  
FLAGS  
DATA  
t
t
t
t
t
FDH  
t
t
t
SFD  
SFD  
FDH  
FDH  
SFD  
SFD  
FDH  
N+1  
N+3  
N
N+2  
T=4  
T=3  
t=1  
T=1  
t
SPE  
t
PEH  
PKTEND  
Figure 9-15 shows the timing relationship of the SLAVE FIFO  
signals during a synchronous write using IFCLK as the  
synchronizing clock. The diagram illustrates a single write  
followed by burst write of 3 bytes and committing all 4 bytes as  
a short packet using the PKTEND pin.  
of IFCLK. The FIFO pointer is updated on each rising edge of  
IFCLK. In Figure 9-15, once the four bytes are written to the  
FIFO, SLWR is deasserted. The short 4-byte packet can be  
committed to the host by asserting the PKTEND signal.  
There is no specific timing requirement that needs to be met  
for asserting the PKTEND signal with regards to asserting the  
SLWR signal. PKTEND can be asserted with the last data  
value or thereafter. The only requirement is that the set-up time  
• At t = 0 the FIFO address is stable and the signal SLCS is  
asserted. (SLCS may be tied low in some applications)  
Note t  
has a minimum of 25 ns. This means that when  
SFA  
IFCLK is running at 48 MHz, the FIFO address set-up time  
is more than one IFCLK cycle.  
t
and the hold time t  
must be met. In the scenario of  
SPE  
PEH  
Figure 9-15, the number of data values committed includes the  
last value written to the FIFO. In this example, both the data  
value and the PKTEND signal are clocked on the same rising  
edge of IFCLK. PKTEND can also be asserted in subsequent  
clock cycles. The FIFOADDR lines must be held constant  
during the PKTEND assertion.  
• At t = 1, the external master/peripheral must outputthe data  
value onto the data bus with a minimum set-up time of t  
before the rising edge of IFCLK.  
SFD  
• At t = 2, SLWR is asserted. The SLWR must meet the set-  
up time of t (time from asserting the SLWR signal to the  
SWR  
Although there are no specific timing requirements for the  
PKTEND assertion, there is a specific corner case condition  
that needs attention while using the PKTEND to commit a one  
byte/word packet. Additional timing requirements exist when  
the FIFO is configured to operate in auto mode and you want  
to send two packets: a full packet (full defined as the number  
of bytes in the FIFO meeting the level set in AUTOINLEN  
register) committed automatically followed by a short one  
byte/word packet committed manually using the PKTEND pin.  
In this case, the external master must make sure to assert the  
PKTEND pin at least one clock cycle after the rising edge that  
caused the last byte/word to be clocked into the previous auto  
committed packet (the packet with the number of bytes equal  
to what is set in the AUTOINLEN register). Refer to Figure 9-7  
for further details on this timing.  
rising edge of IFCLK) and maintain a minimum hold time of  
(time from the IFCLK edge to the deassertion of the  
SLWRsignal). IftheSLCSsignalisused, itmustbeasserted  
with SLWR or before SLWR is asserted. (for example, the  
SLCS and SLWR signals must both be asserted to start a  
valid write condition).  
t
WRH  
• While the SLWR is asserted, data is written to the FIFO and  
on the rising edge of the IFCLK, the FIFO pointer is incre-  
mented. The FIFO flag is also updated after a delay of t  
XFLG  
from the rising edge of the clock.  
The same sequence of events is also shown for a burst write  
and is marked with the time indicators of T = 0 through 5.  
Note For the burst mode, SLWR and SLCS are left asserted  
for the entire duration of writing all the required data values. In  
this burst write mode, once the SLWR is asserted, the data on  
the FIFO data bus is written to the FIFO on every rising edge  
Document # 001-06120 Rev *F  
Page 34 of 39  
 
CY7C68053  
9.13.3 Sequence Diagram of a Single and Burst Asynchronous Read  
Figure 9-16. Slave FIFO Asynchronous Read Sequence and Timing Diagram  
t
t
t
t
FAH  
SFA  
SFA  
FAH  
FIFOADR  
t=0  
t
t
t
t
t
RDpwh  
t
t
RDpwh  
t
T=0  
RDpwl  
RDpwh  
RDpwl  
RDpwl  
RDpwl  
RDpwh  
SLRD  
SLCS  
t=3  
t=2  
T=2  
T=3  
T=5  
T=4  
T=6  
t
XFLG  
t
XFLG  
FLAGS  
DATA  
SLOE  
t
t
XFD  
t
XFD  
XFD  
t
XFD  
Data (X)  
Driven  
N+3  
N
N+1  
N+2  
N
t
t
OEon  
t
t
OEoff  
OEoff  
OEon  
t=4  
T=1  
T=7  
t=1  
Figure 9-17. Slave FIFO Asynchronous Read Sequence of Events Diagram  
SLOE  
SLRD  
SLRD  
SLOE  
SLOE  
SLRD  
N+1  
SLRD  
N+1  
SLRD  
N+2  
SLRD  
N+2  
SLOE  
FIFO POINTER  
N
N
N
N
N+1  
N
N+1  
N+3  
N+3  
FIFO DATA BUS Not Driven  
Driven: X  
Not Driven  
N
N+1  
N+1  
N+2  
N+2  
Not Driven  
Figure 9-16 illustrates the timing relationship of the SLAVE  
FIFO signals during an asynchronous FIFO read. It shows a  
single read followed by a burst read.  
• The data that is driven, after asserting SLRD, is the updated  
data from the FIFO. This data is valid after a propagation  
delay of t  
from the activating edge of SLRD. In Figure 9-  
XFD  
16, data N is the first valid data read from the FIFO. For data  
toappearonthedatabusduringthereadcycle(forexample,  
SLRD is asserted), SLOE MUST be in an asserted state.  
SLRD and SLOE can also be tied together.  
• At t = 0, the FIFO address is stable and the SLCS signal is  
asserted.  
• At t = 1, SLOE is asserted. This results inthe data bus being  
driven. The data that is driven on to the bus is previous data;  
it is data that was in the FIFO from a prior read cycle.  
The same sequence of events is also shown for a burst read  
marked with T = 0 through 5. Note In burst read mode, during  
SLOE assertion, the data bus is in a driven state and outputs  
the previous data. Once SLRD is asserted, the data from the  
FIFO is driven on the data bus (SLOE must also be asserted)  
and then the FIFO pointer is incremented.  
• At t = 2, SLRD is asserted. The SLRD must meet the min-  
imum active pulse of t  
and minimum de-active pulse  
RDpwl  
width of t  
. If SLCS is used then, SLCS must be as-  
RDpwh  
serted with SLRD or before SLRD is asserted (for example,  
the SLCS and SLRD signals must both be asserted to start  
a valid read condition).  
Document # 001-06120 Rev *F  
Page 35 of 39  
 
CY7C68053  
9.13.4 Sequence Diagram of a Single and Burst Asynchronous Write  
Figure 9-18. Slave FIFO Asynchronous Write Sequence and Timing Diagram  
t
t
t
FAH  
t
SFA  
SFA  
FAH  
FIFOADR  
t=0  
T=0  
t
t
t
t
t
t
t
t
WRpwh  
WRpwl  
WRpwh  
WRpwl  
WRpwl  
WRpwh  
WRpwh  
WRpwl  
SLWR  
SLCS  
t=3  
t =1  
T=1  
T=4  
T=3  
T=7  
T=6  
T=9  
t
XFLG  
t
XFLG  
FLAGS  
DATA  
t
t
t
t
t
t
t
SFD  
t
SFD FDH  
SFD FDH  
SFD FDH  
FDH  
N
N+1  
N+2  
N+3  
t=2  
T=8  
T=2  
T=5  
t
t
PEpwl  
PEpwh  
PKTEND  
Figure 9-18 illustrates the timing relationship of the SLAVE  
FIFO write in an asynchronous mode. The diagram shows a  
single write followed by a burst write of 3 bytes and committing  
the 4-byte-short packet using PKTEND.  
incremented. The FIFO flag is also updated after t  
the deasserting edge of SLWR.  
from  
XFLG  
The same sequence of events is shown for a burst write and  
is indicated by the timing marks of T = 0 through 5. Note In the  
burst write mode, once SLWR is deasserted, the data is written  
to the FIFO and then the FIFO pointer is incremented to the  
next byte in the FIFO. The FIFO pointer is post incremented.  
• At t = 0 the FIFO address is applied, ensuring that it meets  
the set-up time of t  
. If SLCS is used, it must also be  
SFA  
asserted (SLCS may be tied low in some applications).  
• At t = 1 SLWR is asserted. SLWR must meet the minimum  
In Figure 9-18 once the four bytes are written to the FIFO and  
SLWR is deasserted, the short 4-byte packet can be  
committed to the host using the PKTEND. The external device  
must be designed to not assert SLWR and the PKTEND signal  
at the same time. It must be designed to assert the PKTEND  
after SLWR is deasserted and meet the minimum deasserted  
pulse width. The FIFOADDR lines are to be held constant  
during the PKTEND assertion.  
active pulse of t  
and minimum de-active pulse width  
WRpwl  
of t  
. If the SLCS is used, it must be asserted with  
WRpwh  
SLWR or before SLWR is asserted.  
• At t = 2, data must be present on the bus t  
deasserting edge of SLWR.  
before the  
SFD  
• At t = 3, deasserting SLWR causes the data to be written  
from the data bus to the FIFO and then the FIFO pointer is  
Document # 001-06120 Rev *F  
Page 36 of 39  
 
CY7C68053  
10.0  
Ordering Information  
Table 10-1. Ordering Information  
8051  
Address/Data  
Ordering Code  
Package Type  
RAM Size  
# Prog I/Os  
24  
Busses  
CY7C68053-56BAXI  
56 VFBGA– Lead-Free  
16K  
Development Tool Kit  
CY3687  
MoBL-USB FX2LP18 Development Kit  
11.0  
Package Diagram  
The FX2LP18 is available in a 56-pin VFBGA package.  
Figure 11-1. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56  
TOP VIEW  
BOTTOM VIEW  
Ø0.05 M C  
Ø0.15 M C A B  
A1 CORNER  
PIN A1 CORNER  
Ø0.30 0.05(56X)  
1
2
3
4
5
6
6
8
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
0.50  
3.50  
-B-  
-A-  
5.00 0.10  
SIDE VIEW  
5.00 0.10  
0.10(4X)  
REFERENCE JEDEC: MO-195C  
PACKAGE WEIGHT: 0.02 grams  
-C-  
SEATING PLANE  
001-03901-*B  
Document # 001-06120 Rev *F  
Page 37 of 39  
CY7C68053  
• Bypass/flyback caps on VBus, near connector, are recom-  
mended.  
12.0  
PCB Layout Recommendations  
The following recommendations must be followed to ensure  
reliable high-performance operation.  
• DPLUS and DMINUS trace lengths must be kept to within  
2 mm of each other in length, with preferred length of  
20–30 mm.  
• At least a four-layer impedance controlled board is required  
to maintain signal quality.  
• Maintain a solid ground plane under the DPLUS and  
DMINUS traces. Do not allow the plane to be split under  
these traces.  
• Specify impedance targets (ask your board vendor what  
they can achieve).  
To control impedance, maintain trace widths and trace spac-  
ing to within specifications.  
• It is preferable to have no vias placed on the DPLUS or  
DMINUS trace routing.  
• Minimize stubs to minimize reflected signals.  
• Isolate the DPLUS and DMINUS traces from all other signal  
traces by no less than 10 mm.  
• Connections between the USB connector shell and signal  
ground must be done near the USB connector.  
2
Purchase of I C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips  
2
2
2
I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification  
as defined by Philips. MoBL-USB FX2LP18, EZ-USB FX2LP and ReNumeration are trademarks, and MoBL-USB is a registered  
trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trade-  
marks of their respective holders.  
Document # 001-06120 Rev *F  
Page 38 of 39  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C68053  
Document History Page  
Document Title: CY7C68053 MoBL-USB FX2LP18 USB Microcontroller  
Document Number: 001-06120  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
430449  
434754  
03/03/06  
03/24/06  
OSG  
OSG  
New data sheet  
*A  
In Section 3.3, stated that SCL and SDA pins can be connected to V or  
CC  
V
CC_IO  
Changed sections 3.5, 3.18.1 and pin descriptions of SCL, SDA to indicate that  
since DISCON=1 after reset, an EEPROM or EEPROM emulation is required  
on the I C interface  
2
In pin description table, renamed pin 2H (Reserved) to Ground  
In Section 6, added statement “The GPIO’s are not over voltage tolerant,  
except the SCL and SDA pins, which are 3.3V tolerant“  
In Section 8,added a footnote to the DC char table stating that AVcc can be  
floated in low power mode  
In Section 8, changed V max in DC char table from 3.6V to V  
+ 10%  
IH  
CC_IO  
2
*B  
*C  
465471  
484726  
See ECN  
See ECN  
OSG  
ARI  
Changed the recommendation for the pull up resistors on I C  
Split Icc into 4 different values, corresponding to the different voltage supplies  
Changed Isus typical to 20uA and 220uA  
Added section 3.9.3 on suspend current considerations  
Removed all references the part number CY7C68055. Corrected the bullet in  
Features to state that 24 GPIO’s are available. Added the Test ID (TID#) to the  
Features on the front page. Made changes to the block diagram on the first  
page (this is now a Visio drawing instead of a Framemaker drawing). Corrected  
the Ambient Temperature with Power Supplied. Moved figure titles to meet the  
new template. Checked grammar. Took out 9-bit address bus from the block  
diagram on the first page. Corrected Figure 4.1  
*D  
*E  
*F  
492009  
500408  
502115  
See ECN  
See ECN  
See ECN  
OSG  
OSG  
OSG  
Added Icc data in DC Characteristics and Maximum Power dissipation  
Changed ESD spec to 1500V  
Changed ESD spec to 2000V and 1500V only for SCL and SDA pins.  
Added min spec for t  
OEoff  
Changed Icc and power dissipation numbers  
Document # 001-06120 Rev *F  
Page 39 of 39  

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