Cypress FLEx36 CY7C0852AV User Manual

CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
FLEx36™ 3.3V 32K/64K/128K/256K x 36  
Synchronous Dual-Port RAM  
Features  
Functional Description  
True dual-ported memory cells that allow simultaneous access  
of the same memory location  
The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,  
synchronous, true dual-port static RAMs that are high-speed,  
low-power 3.3V CMOS. Two ports are provided, permitting  
independent, simultaneous access to any location in memory.  
The result of writing to the same location by more than one port  
at the same time is undefined. Registers on control, address, and  
data lines allow for minimal setup and hold time.  
Synchronous pipelined operation  
Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices  
Pipelined output mode allows fast operation  
0.18-micron CMOS for optimum speed and power  
High-speed clock to data access  
During a Read operation, data is registered for decreased cycle  
time. Each port contains a burst counter on the input address  
register. After externally loading the counter with the initial  
address, the counter increments the address internally (more  
details to follow). The internal Write pulse width is independent  
of the duration of the R/W input signal. The internal Write pulse  
is self-timed to allow the shortest possible cycle times.  
3.3V low power  
Active as low as 225 mA (typ)  
Standby as low as 55 mA (typ)  
Mailbox function for message passing  
Global master reset  
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down  
the internal circuitry to reduce the static power consumption. One  
cycle with chip enables asserted is required to reactivate the  
outputs.  
Separate byte enables on both ports  
Commercial and industrial temperature ranges  
IEEE 1149.1-compatible JTAG boundary scan  
172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)  
176-Pin TQFP (24 mm × 24 mm × 1.4 mm)  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
Counter wrap around control  
The CY7C0853AV device in this family has limited features.  
Internal mask register controls counter wrap-around  
Counter-interrupt flags to indicate wrap-around  
Memory block retransmit operation  
Counter readback on address lines  
Mask register readback on address lines  
Dual Chip Enables on both ports for easy depth expansion  
Table 1. Product Selection Guide  
1-Mbit  
2-Mbit  
4-Mbit  
9-Mbit  
Density  
(32K x 36)  
CY7C0850AV  
167  
(64K x 36)  
(128K x 36)  
(256K x 36)  
Part Number  
CY7C0851AV  
CY7C0852AV  
CY7C0853AV  
133  
Max. Speed (MHz)  
167  
4.0  
167  
4.0  
Max. Access Time - Clock to Data (ns)  
Typical operating current (mA)  
Package  
4.0  
4.7  
225  
225  
225  
270  
176TQFP  
172FBGA  
176TQFP  
172FBGA  
176TQFP  
172FBGA  
172FBGA  
Cypress Semiconductor Corporation  
Document #: 38-06070 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 29, 2008  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Pin Configurations  
Figure 1. 172-Ball BGA (Top View)  
1
DQ32L  
A0L  
2
3
CNTINTL  
DQ29L  
DQ31L  
DQ35L  
CE1L  
A7L  
4
VSS  
5
6
7
8
9
10  
DQ13R  
DQ14R  
INTR  
11  
VSS  
12  
CNTINTR  
DQ29R  
DQ31R  
DQ35R  
CE1R  
A7R  
13  
DQ30R  
DQ33R  
A1R  
14  
DQ32R  
A0R  
DQ30L  
DQ33L  
A1L  
DQ13L  
DQ14L  
INTL  
VDD  
DQ11L  
DQ9L  
DQ10L  
VSS  
DQ11R  
DQ9R  
DQ10R  
VSS  
VDD  
A
B
C
D
E
F
DQ17L  
DQ27L  
DQ34L  
B0L  
DQ12L  
DQ15L  
DQ16L  
VSS  
DQ12R  
DQ15R  
DQ16R  
VDD  
DQ17R  
DQ27R  
DQ34R  
B0R  
NC  
NC  
A2L  
A3L  
DQ28L  
VDD  
DQ28R  
VDD  
A3R  
A2R  
A4L  
A5L  
A5R  
A4R  
VDD  
A6L  
B1L  
VDD  
VSS  
B1R  
A6R  
VDD  
CY7C0850AV  
CY7C0851AV  
CY7C0852AV  
OEL  
B2L  
B3L  
CE0L  
CLKL  
ADSL  
CNTRSTL  
DQ26L  
DQ18L  
DQ6L  
VSS  
CE0R  
CLKR  
ADSR  
B3R  
B2R  
OER  
G
H
J
VSS  
R/WL  
A10L  
A12L  
A13L  
A14L  
DQ20L  
DQ21L  
A8L  
A8R  
R/WR  
A10R  
A12R  
A13R  
A14R  
DQ20R  
DQ21R  
VSS  
A9L  
VSS  
VSS  
VDD  
VDD  
VDD  
MRST  
A9R  
[2]  
A11L  
CNT/MSKL  
A15L  
VDD  
DQ19L  
DQ7L  
DQ3L  
VDD  
VSS  
DQ19R  
DQ7R  
DQ3R  
VDD  
CNTRSTR A15R  
A11R  
CNT/MSKR  
K
L
CNTENL  
DQ22L  
DQ8L  
DQ25L  
TDI  
VSS  
VSS  
DQ25R  
TCK  
DQ26R  
DQ18R  
DQ6R  
VSS  
CNTENR  
A16L  
DQ2L  
DQ0L  
DQ1L  
DQ2R  
DQ0R  
DQ1R  
DQ22R  
DQ8R  
TMS  
A16R  
M
N
P
DQ24L  
DQ23L  
DQ5L  
DQ4L  
DQ5R  
DQ4R  
DQ24R  
DQ23R  
TDO  
Note  
2. For CY7C0851AV, pins M1 and M14 are NC. For CY7C0850AV, pins K3, K12 M1, and M14 are NC  
Document #: 38-06070 Rev. *H  
Page 3 of 32  
 
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Pin Configurations (continued)  
Figure 2. 172-Ball BGA (Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
DQ32L  
A0L  
DQ30L  
DQ33L  
A1L  
NC  
VSS  
DQ13L  
DQ14L  
INTL  
VDD  
DQ11L  
DQ9L  
DQ10L  
VSS  
DQ11R  
DQ9R  
VDD  
DQ13R  
VSS  
NC  
DQ30R DQ32R  
A
B
C
D
E
F
DQ29L  
DQ31L  
DQ35L  
VDD  
A7L  
DQ17L  
DQ27L  
DQ34L  
B0L  
DQ12L  
DQ15L  
DQ16L  
VSS  
DQ12R DQ14R DQ17R DQ29R DQ33R  
A0R  
A17R  
A2R  
A17L  
A2L  
DQ10R DQ15R  
INTR  
DQ27R DQ31R  
A1R  
A3R  
A3L  
DQ28L  
VDD  
VSS  
DQ16R DQ28R DQ34R DQ35R  
A4L  
A5L  
VDD  
VDD  
VSS  
B0R  
B1R  
VDD  
A7R  
A5R  
A4R  
VDD  
OEL  
A6L  
B1L  
VDD  
A6R  
VDD  
OER  
VSS  
A9R  
CY7C0853AV  
B2L  
B3L  
VSS  
VSS  
CLKR  
VSS  
VDD  
B3R  
B2R  
G
H
J
VSS  
R/WL  
A10L  
A12L  
A13L  
A14L  
DQ20L  
DQ21L  
A8L  
CLKL  
VSS  
A8R  
R/WR  
A10R  
A12R  
A13R  
A14R  
A9L  
VSS  
VSS  
VDD  
VDD  
VDD  
MRST  
A15R  
VSS  
A11L  
VDD  
A16L  
DQ24L  
DQ23L  
A15L  
VSS  
VDD  
VDD  
VSS  
A11R  
VDD  
A16R  
K
L
DQ26L  
DQ18L  
DQ6L  
VSS  
DQ25L  
TDI  
DQ19L  
DQ7L  
DQ3L  
VDD  
VSS  
DQ2L  
DQ0L  
DQ1L  
VSS  
DQ19R DQ25R DQ26R  
DQ22L  
DQ8L  
TDO  
DQ2R  
DQ0R  
DQ1R  
DQ7R  
DQ3R  
VDD  
TCK  
DQ18R DQ22R  
M
N
P
DQ5L  
DQ4L  
DQ5R  
DQ4R  
DQ6R  
VSS  
DQ8R  
TMS  
DQ20R DQ24R  
DQ21R DQ23R  
Document #: 38-06070 Rev. *H  
Page 4 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Pin Configurations (continued)  
Figure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View)  
DQ  
DQ  
NC  
34R  
35R  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
1
2
DQ  
DQ  
34L  
35L  
3
NC  
A
0R  
4
A
0L  
A
1R  
5
A
1L  
A
2R  
6
A
2L  
A
V
3R  
7
A
V
3L  
SS  
DD  
SS  
8
V
DD  
9
V
A
A
A
A
4R  
5R  
6R  
7R  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
A
A
A
A
4L  
5L  
6L  
7L  
B
0R  
1R  
B
0L  
1L  
B
B
CE  
1R  
CE  
1L  
B
B
2R  
3R  
B
B
2L  
3L  
OE  
CE  
R
OE  
CE  
L
0R  
CY7C0850AV  
CY7C0851AV  
CY7C0852AV  
0L  
V
DD  
V
DD  
V
DD  
V
DD  
V
SS  
V
SS  
V
SS  
V
SS  
R/W  
CLK  
R
R/W  
L
R
CLK  
L
MRST  
ADS  
V
SS  
R
ADS  
L
CNTEN  
R
CNTEN  
L
CNTRST  
R
CNTRST  
L
CNT/MSK  
R
CNT/MSK  
L
A
A
8R  
A
A
8L  
9R  
9L  
A
10R  
11R  
12R  
A
10L  
11L  
12L  
A
A
98  
A
A
97  
V
SS  
96  
V
SS  
DD  
13L  
V
A
DD  
95  
V
A
13R  
94  
A
A
14R  
93  
A
14L  
15L  
16L  
[2]  
[2]  
[2]  
15R  
16R  
92  
A
A
[2]  
A
91  
DQ  
DQ  
24R  
90  
DQ  
DQ  
24L  
20L  
89  
20R  
Document #: 38-06070 Rev. *H  
Page 5 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Pin Definitions  
Left Port  
Right Port  
Description  
[1]  
A
–A  
A
–A  
Address Inputs.  
0L  
17L  
0R  
17R  
ADS  
ADS  
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for  
the part using the externally supplied address on the address pins and for loading this address  
into the burst address counter.  
L
R
CE0  
CE0  
Active LOW Chip Enable Input.  
L
R
CE1  
CLK  
CE1  
CLK  
Active HIGH Chip Enable Input.  
L
R
Clock Signal. Maximum clock input rate is f  
.
L
R
MAX  
CNTEN  
CNTEN  
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its  
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are  
asserted LOW.  
L
R
CNTRST  
CNTRST  
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst  
L
R
address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN.  
CNT/MSK  
CNT/MSK  
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to  
the mask register. When tied HIGH, the mask register is not accessible and the address counter  
operations are enabled based on the status of the counter control signals.  
L
R
DQ –DQ  
DQ –DQ  
Data Bus Input/Output.  
0L  
35L  
0R  
35R  
OE  
OE  
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data  
pins during Read operations.  
L
R
INTL  
INTR  
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper  
two memory locations can be used for message passing. INT is asserted LOW when the right  
L
port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is  
deasserted HIGH when it reads the contents of its mailbox.  
CNTINT  
CNTINT  
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter  
L
R
is incremented to all “1s.”  
R/W  
R/W  
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port  
memory array.  
L
R
B
–B  
B
–B  
3R  
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-  
sponding bytes of the memory array.  
0L  
3L  
0R  
MRST  
TMS  
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting  
MRST LOW performs all of the reset functions as described in the text. A MRST operation is  
required at power up.  
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State  
machine transitions occur on the rising edge of TCK.  
TDI  
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.  
TCK  
TDO  
JTAG Test Clock Input.  
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally  
three-stated except when captured data is shifted out of the JTAG TAP.  
V
V
Ground Inputs.  
SS  
Power Inputs.  
DD  
Note  
3. These pins are not available for CY7C0853AV device.  
Document #: 38-06070 Rev. *H  
Page 6 of 32  
 
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
in order to set the INT flag, a Write operation by the left port to  
Master Reset  
R
address 3FFFF asserts INT LOW. At least one byte has to be  
R
active for a Write to generate an interrupt. A valid Read of the  
The FLEx36 family devices undergo a complete reset by taking  
its MRST input LOW. The MRST input can switch asynchro-  
nously to the clocks. The MRST initializes the internal burst  
counters to zero, and the counter mask registers to all ones  
(completely unmasked). The MRST also forces the Mailbox  
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags  
HIGH. The MRST must be performed on the FLEx36 family  
devices after power up.  
3FFFF location by the right port resets INT HIGH. At least one  
R
byte has to be active in order for a Read to reset the interrupt.  
When one port Writes to the other port’s mailbox, the INT of the  
port that the mailbox belongs to is asserted LOW. The INT is  
reset when the owner (port) of the mailbox Reads the contents  
of the mailbox. The interrupt flag is set in a flow-thru mode (i.e.,  
it follows the clock edge of the writing port). Also, the flag is reset  
in a flow-thru mode (i.e., it follows the clock edge of the reading  
port).  
Mailbox Interrupts  
Each port can read the other port’s mailbox without resetting the  
interrupt. And each port can write to its own mailbox without  
setting the interrupt. If an application does not require message  
passing, INT pins should be left open.  
The upper two memory locations may be used for message  
passing and permit communications between ports. Table 2  
shows the interrupt operation for both ports of CY7C0853AV.  
The highest memory location, 3FFFF is the mailbox for the right  
port and 3FFFE is the mailbox for the left port. Table 2 shows that  
Table 2. Interrupt Operation Example  
Left Port  
Function  
Right Port  
R/W  
CE  
L
A
INT  
X
R/W  
CE  
X
A
INT  
L
L
L
0L–17L  
L
R
R
0R–17R  
R
Set Right INT Flag  
L
X
X
H
3FFFF  
X
X
H
L
X
R
Reset Right INT Flag  
X
X
L
3FFFF  
3FFFE  
X
H
R
Set Left INT Flag  
X
X
L
L
X
L
Reset Left INT Flag  
L
3FFFE  
H
X
X
X
L
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)  
CLK MRST CNT/MSK  
CNTRST  
ADS  
CNTEN  
Operation  
Description  
X
L
X
X
X
X
Master Reset  
Reset address counter to all 0s and mask  
register to all 1s.  
H
H
H
H
L
X
L
X
L
Counter Reset  
Counter Load  
Reset counter unmasked portion to all 0s.  
H
Load counter with external address value  
presented on address lines.  
H
H
H
L
H
Counter Readback Read out counter internal value on address  
lines.  
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.  
H
Counter Hold  
Constantly hold the address value for  
multiple clock cycles.  
H
H
L
L
L
X
L
X
L
Mask Reset  
Mask Load  
Reset mask register to all 1s.  
H
Load mask register with value presented on  
the address lines.  
H
H
L
L
H
H
L
H
X
Mask Readback  
Reserved  
Read out mask register value on address  
lines.  
H
Operation undefined  
Notes  
4. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and  
0
1
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.  
5. OE is “Don’t Care” for mailbox operation.  
6. At least one of B0, B1, B2, or B3 must be LOW.  
7. A16x is a NC for CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses  
are 7FFF and 6FFF.  
8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.  
9. Counter operation and mask register operation is independent of chip enables.  
Document #: 38-06070 Rev. *H  
Page 7 of 32  
               
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
will reset the counter and mirror registers to 00000, as will master  
reset (MRST).  
Address Counter and Mask Register  
Operations  
Counter Load Operation  
This section  
describes the features only apply to  
The address counter and mirror registers are both loaded with  
the address value presented at the address lines.  
CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not to  
the CY7C0853AV device. Each port of these devices has a  
programmable burst address counter. The burst counter  
contains three registers: a counter register, a mask register, and  
a mirror register.  
Counter Readback Operation  
The internal value of the counter register can be read out on the  
address lines. Readback is pipelined; the address is valid t  
The counter register contains the address used to access the  
RAM array. It is changed only by the Counter Load, Increment,  
Counter Reset, and by master reset (MRST) operations.  
CA2  
after the next rising edge of the port’s clock. If address readback  
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the  
data lines (DQs) is three-stated. Figure 4 on page 10 shows a  
block diagram of the operation.  
The mask register value affects the Increment and Counter  
Reset operations by preventing the corresponding bits of the  
counter register from changing. It also affects the counter  
interrupt output (CNTINT). The mask register is changed only by  
the Mask Load and Mask Reset operations, and by the MRST.  
The mask register defines the counting range of the counter  
register. It divides the counter register into two regions: zero or  
more “0s” in the most significant bits define the masked region,  
one or more “1s” in the least significant bits define the unmasked  
region. Bit 0 may also be “0,” masking the least significant  
counter bit and causing the counter to increment by two instead  
of one.  
Counter Increment Operation  
Once the address counter register is initially loaded with an  
external address, the counter can internally increment the  
address value, potentially addressing the entire memory array.  
Only the unmasked bits of the counter register are incremented.  
The corresponding bit in the mask register must be a “1” for a  
counter bit to change. The counter register is incremented by 1  
if the least significant bit is unmasked, and by 2 if it is masked. If  
all unmasked bits are “1,” the next increment wraps the counter  
back to the initially loaded value. If an Increment results in all the  
unmasked bits of the counter being “1s,” a counter interrupt flag  
(CNTINT) is asserted. The next Increment returns the counter  
register to its initial value, which was stored in the mirror register.  
The mirror register is used to reload the counter register on  
increment operations (see “retransmit,” below). It always  
contains the value last loaded into the counter register, and is  
changed only by the Counter Load operation, and by the MRST.  
The counter address can instead be forced to loop to 00000 by  
externally connecting CNTINT to CNTRST.  
An increment that  
Table 3 on page 7 summarizes the operation of these registers  
and the required input control signals. The MRST control signal  
is asynchronous. All the other control signals in Table 3 on page  
7 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the  
port’s CLK. All these counter and mask operations are  
independent of the port’s chip enable inputs (CE0 and CE1).  
results in one or more of the unmasked bits of the counter being  
“0” deasserts the counter interrupt flag. The example in Figure 5  
on page 11 shows the counter mask register loaded with a mask  
value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB  
and bit “16” as the MSB. The maximum value the mask register  
can be loaded with is 1FFFFh. Setting the mask register to this  
value allows the counter to access the entire memory space. The  
address counter is then loaded with an initial value of 8h. The  
base address bits (in this case, the 6th address through the 16th  
address) are loaded with an address value but do not increment  
once the counter is configured for increment operation. The  
counter address starts at address 8h. The counter increments its  
internal address value till it reaches the mask register value of  
3Fh. The counter wraps around the memory block to location 8h  
at the next count. CNTINT is issued when the counter reaches  
its maximum value.  
Counter enable (CNTEN) inputs are provided to stall the  
operation of the address input and utilize the internal address  
generated by the internal counter for fast, interleaved memory  
applications. A port’s burst counter is loaded when the port’s  
address strobe (ADS) and CNTEN signals are LOW. When the  
port’s CNTEN is asserted and the ADS is deasserted, the  
address counter increments on each LOW to HIGH transition of  
that port’s clock signal. This will Read/Write one word from/into  
each successive address location until CNTEN is deasserted.  
The counter can address the entire memory array, and loops  
back to the start. Counter reset (CNTRST) is used to reset the  
unmasked portion of the burst counter to 0s. A counter-mask  
register is used to control the counter wrap.  
Counter Hold Operation  
The value of all three registers can be constantly maintained  
unchanged for an unlimited number of clock cycles. Such  
operation is useful in applications where wait states are needed,  
or when address is available a few cycles ahead of data in a  
shared bus interface.  
Counter Reset Operation  
All unmasked bits of the counter are reset to “0.” All masked bits  
remain unchanged. The mirror register is loaded with the value  
of the burst counter. A Mask Reset followed by a Counter Reset  
Notes  
10. This section describes the CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851AV has 16 address bits, register lengths  
of 16 bits, and a maximum address value of FFFF. The CY7C0850AV has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF.  
11. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.  
Document #: 38-06070 Rev. *H  
Page 8 of 32  
     
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Counter Interrupt  
Mask Load Operation  
The counter interrupt (CNTINT) is asserted LOW when an  
increment operation results in the unmasked portion of the  
counter register being all “1s.” It is deasserted HIGH when an  
Increment operation results in any other value. It is also  
de-asserted by Counter Reset, Counter Load, Mask Reset and  
Mask Load operations, and by MRST.  
The mask register is loaded with the address value presented at  
the address lines. Not all values permit correct increment opera-  
n
n
tions. Permitted values are of the form 2 – 1 or 2 – 2. From the  
most significant bit to the least significant bit, permitted values  
have zero or more “0s,” one or more “1s,” or one “0.” Thus  
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,  
003FC, and 00000 are not.  
Retransmit  
Mask Readback Operation  
Retransmit is a feature that allows the Read of a block of memory  
more than once without the need to reload the initial address.  
This eliminates the need for external logic to store and route  
data. It also reduces the complexity of the system design and  
saves board space. An internal “mirror register” is used to store  
the initially loaded address counter value. When the counter  
unmasked portion reaches its maximum value set by the mask  
register, it wraps back to the initial value stored in this “mirror  
register.” If the counter is continuously configured in increment  
mode, it increments again to its maximum value and wraps back  
to the value initially stored into the “mirror register.” Thus, the  
repeated access of the same data is allowed without the need  
for any external logic.  
The internal value of the mask register can be read out on the  
address lines. Readback is pipelined; the address is valid t  
CM2  
after the next rising edge of the port’s clock. If mask readback  
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the  
data lines (DQs) is three-stated. Figure 4 on page 10 shows a  
block diagram of the operation.  
Counting by Two  
When the least significant bit of the mask register is “0,” the  
counter increments by two. This may be used to connect the  
CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single  
port SRAM in which the counter of one port counts even  
addresses and the counter of the other port counts odd  
addresses. This even-odd address scheme stores one half of the  
72-bit data in even memory locations, and the other half in odd  
memory locations.  
Mask Reset Operation  
The mask register is reset to all “1s,” which unmasks every bit of  
the counter. Master reset (MRST) also resets the mask register  
to all “1s.”  
Document #: 38-06070 Rev. *H  
Page 9 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Figure 4. Counter, Mask, and Mirror Logic Block Diagram  
CNT/MSK  
CNTEN  
ADS  
Decode  
Logic  
CNTRST  
MRST  
Bidirectional  
Address  
Lines  
Mask  
Register  
Counter/  
Address  
Register  
Address  
Decode  
RAM  
Array  
CLK  
Load/Increment  
17  
17  
From  
Address  
Lines  
Mirror  
Counter  
To Readback  
and Address  
Decode  
1
0
1
0
From  
Increment  
Logic  
Mask  
Register  
17  
Wrap  
17  
17  
17  
Bit 0  
From  
Mask  
From  
Counter  
+1  
+2  
Wrap  
Detect  
Wrap  
To  
1
0
17  
1
0
Counter  
Document #: 38-06070 Rev. *H  
Page 10 of 32  
 
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Figure 5. Programmable Counter-Mask Register Operation  
CNTINT  
H
Example:  
Load  
Counter-Mask  
Register = 3F  
0
0
0s  
0
1
1
1
1
1
1
16 15  
6
5
4
3
2
1
0
Mask  
2
2
2
2
2
2
2
2
2
Register  
bit-0  
Masked Address  
Unmasked Address  
Load  
Address  
Counter = 8  
H
L
X
X
Xs  
Xs  
Xs  
X
0
0
1
0
0
0
16 15  
6
6
5
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
Address  
Counter  
bit-0  
Max  
Address  
Register  
X
X
X
2
1
1
1
1
1
1
16 15  
4
3
2
1
0
2
2
2
2
2
2
2
Max + 1  
Address  
Register  
H
X
X
X
0
0
1
0
0
0
16 15  
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
Document #: 38-06070 Rev. *H  
Page 11 of 32  
 
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
IEEE 1149.1 Serial Boundary Scan (JTAG) [13]  
Performing a TAP Reset  
A reset is performed by forcing TMS HIGH (V ) for five rising  
DD  
The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV  
incorporates an IEEE 1149.1 serial boundary scan test access  
port (TAP). The TAP controller functions in a manner that does  
not conflict with the operation of other devices using  
edges of TCK. This reset does not affect the operation of the  
devices, and may be performed while the devices are operating.  
An MRST must be performed on the devices after power up.  
Performing a Pause/Restart  
1149.1-compliant  
TAPs.  
The  
TAP  
operates  
using  
JEDEC-standard 3.3V I/O logic levels. It is composed of three  
input connections and one output connection required by the test  
logic defined by the standard.  
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan  
chain outputs the next bit in the chain twice. For example, if the  
value expected from the chain is 1010101, the device outputs a  
11010101. This extra bit causes some testers to report an  
erroneous failure for the devices in a scan test. Therefore the  
tester should be configured to never enter the PAUSE-DR state.  
Table 4. Identification Register Definitions  
Instruction Field  
Revision Number (31:28)  
Cypress Device ID (27:12)  
Value  
0h  
Description  
Reserved for version number.  
C001h  
C002h  
C092h  
034h  
1
Defines Cypress part number for the CY7C0851AV  
Defines Cypress part number for the CY7C0852AV and CY7C0853AV  
Defines Cypress part number for the CY7C0850AV  
Allows unique identification of the DP family device vendor.  
Indicates the presence of an ID register.  
Cypress JEDEC ID (11:1)  
ID Register Presence (0)  
Table 5. Scan Registers Sizes  
Register Name  
Bit Size  
Instruction  
Bypass  
4
1
Identification  
Boundary Scan  
32  
n
Table 6. Instruction Identification Codes  
Instruction  
EXTEST  
Code  
0000  
1111  
1011  
0111  
Description  
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.  
Places the BYR between TDI and TDO.  
BYPASS  
IDCODE  
HIGHZ  
Loads the IDR with the vendor ID code and places the register between TDI and TDO.  
Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/  
CY7C0853AV output drivers to a High-Z state.  
CLAMP  
0100  
1000  
1100  
Controls boundary to 1/0. Places BYR between TDI and TDO.  
SAMPLE/PRELOAD  
NBSRST  
Captures the input/output ring contents. Places BSR between TDI and TDO.  
Resets the non-boundary scan logic. Places BYR between TDI and TDO.  
RESERVED  
All other codes Other combinations are reserved. Do not use other than the above.  
Notes  
12. The “X” in this diagram represents the counter upper bits.  
13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.  
14. See details in the device BSDL files.  
Document #: 38-06070 Rev. *H  
Page 12 of 32  
     
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
DC Input Voltage .............................. –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Output Current into Outputs (LOW)............................. 20 mA  
Exceeding maximum ratings  
device. These user guidelines are not tested.  
may impair the useful life of the  
Static Discharge Voltage........................................... > 2000V  
(JEDEC JESD22-A114-2000B)  
Storage Temperature................................ –65°C to + 150°C  
Ambient Temperature with  
Latch-up Current .................................................... > 200 mA  
Power Applied ........................................... –55°C to + 125°C  
Operating Range  
Supply Voltage to Ground Potential...............–0.5V to + 4.6V  
Range  
Commercial  
Industrial  
Ambient Temperature  
V
DD  
DC Voltage Applied to  
0°C to +70°C  
–40°C to +85°C  
3.3V ± 165 mV  
3.3V ± 165 mV  
Outputs in High-Z State ......................... –0.5V to V + 0.5V  
DD  
Electrical Characteristics  
Over the Operating Range  
-167  
-133  
-100  
Parameter  
Description  
Output HIGH Voltage (V = Min., I = –4.0 mA) 2.4  
Unit  
Min Typ. Max Min Typ. Max Min Typ. Max  
V
V
V
V
I
2.4  
2.4  
V
V
OH  
OL  
IH  
DD  
OH  
Output LOW Voltage (V = Min., I = +4.0 mA)  
0.4  
0.4  
0.4  
DD  
OL  
Input HIGH Voltage  
Input LOW Voltage  
2.0  
2.0  
2.0  
V
0.8  
10  
10  
0.8  
10  
10  
0.8  
10  
10  
V
IL  
Output Leakage Current  
–10  
–10  
–0.1  
–10  
–10  
–10  
–10  
μA  
μA  
OZ  
I
I
I
Input Leakage Current Except TDI, TMS, MRST  
Input Leakage Current TDI, TMS, MRST  
IX1  
1.0 –0.1  
225 300  
1.0 –0.1  
225 300  
1.0 mA  
mA  
IX2  
CC  
Operating Current for  
(V = Max.,I = 0 mA),  
Outputs Disabled  
CY7C0850AV  
CY7C0851AV  
CY7C0852AV  
DD  
OUT  
CY7C0853AV  
270 400  
90 115  
200 310  
90 115 mA  
I
I
I
I
I
Standby Current (Both Ports TTL Level)  
90  
160 210  
55 75  
115  
SB1  
SB2  
SB3  
SB4  
SB5  
CE and CE V , f = f  
L
R
IH  
MAX  
Standby Current (One Port TTL Level)  
160 210  
55 75  
160 210  
70 100  
160 210 mA  
55 75 mA  
160 210 mA  
CE | CE V , f = f  
L
R
IH  
MAX  
Standby Current (Both Ports CMOS Level)  
CE and CE V – 0.2V, f = 0  
L
R
DD  
Standby Current (One Port CMOS Level)  
160 210  
CE | CE V , f = f  
L
R
IH  
MAX  
Operating Current  
(V = Max, I  
CY7C0853AV  
70  
100 mA  
= 0 mA, f = 0)  
OUT  
DD  
Outputs Disabled  
Capacitance  
Part Number  
Parameter  
Description  
Test Conditions  
Max  
13  
Unit  
pF  
CY7C0850AV,  
CY7C0851AV, CY7C0852AV  
C
C
C
C
Input Capacitance  
Output Capacitance  
Input Capacitance  
Output Capacitance  
T = 25°C, f = 1 MHz,  
IN  
A
V
= 3.3V  
DD  
10  
pF  
OUT  
IN  
CY7C0853AV  
22  
pF  
20  
pF  
OUT  
Notes  
15. The voltage on any input or I/O pin can not exceed the power pin during power up.  
16. Pulse width < 20 ns.  
17. C  
also references C  
.
OUT  
I/O  
18. I  
, I  
, I  
and I  
are not applicable for CY7C0853AV because it can not be powered down by using chip enable pins.  
SB1 SB2 SB3  
SB4  
Document #: 38-06070 Rev. *H  
Page 13 of 32  
       
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Figure 6. AC Test Load and Waveforms  
3.3V  
Z0 = 50Ω  
R = 50Ω  
OUTPUT  
R1 = 590 Ω  
OUTPUT  
C = 10 pF  
C = 5 pF  
R2 = 435 Ω  
VTH = 1.5V  
(a) Normal Load (Load 1)  
(b) Three-state Delay (Load 2)  
3.0V  
90%  
10%  
90%  
10%  
ALL INPUT PULSES  
VSS  
< 2 ns  
< 2 ns  
Switching Characteristics  
Over the Operating Range  
-167  
-133  
-100  
CY7C0850AV CY7C0850AV  
CY7C0851AV CY7C0851AV CY7C0853AV CY7C0853AV Unit  
CY7C0852AV CY7C0852AV  
Parameter  
Description  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Operating Frequency  
Clock Cycle Time  
167  
133  
133  
100  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MAX2  
CYC2  
CH2  
6.0  
2.7  
2.7  
7.5  
3.0  
3.0  
7.5  
3.0  
3.0  
10.0  
4.0  
Clock HIGH Time  
Clock LOW Time  
4.0  
CL2  
Clock Rise Time  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
3.0  
3.0  
R
F
Clock Fall Time  
Address Setup Time  
Address Hold Time  
Byte Select Setup Time  
Byte Select Hold Time  
Chip Enable Setup Time  
Chip Enable Hold Time  
R/W Setup Time  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.3  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
2.5  
0.6  
NA  
NA  
2.5  
0.6  
2.5  
0.6  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
3.0  
0.6  
3.0  
0.6  
NA  
NA  
3.0  
0.6  
3.0  
0.6  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
SA  
HA  
SB  
HB  
SC  
HC  
SW  
R/W Hold Time  
HW  
SD  
Input Data Setup Time  
Input Data Hold Time  
ADS Setup Time  
HD  
SAD  
HAD  
SCN  
HCN  
SRST  
HRST  
SCM  
HCM  
ADS Hold Time  
CNTEN Setup Time  
CNTEN Hold Time  
CNTRST Setup Time  
CNTRST Hold Time  
CNT/MSK Setup Time  
CNT/MSK Hold Time  
Note  
19. Except JTAG signals (t and t < 10 ns [max.]).  
r
f
Document #: 38-06070 Rev. *H  
Page 14 of 32  
 
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Characteristics  
Over the Operating Range (continued)  
-167  
-133  
-100  
CY7C0850AV CY7C0850AV  
CY7C0851AV CY7C0851AV CY7C0853AV CY7C0853AV Unit  
CY7C0852AV CY7C0852AV  
Parameter  
Description  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
t
t
t
t
t
t
t
t
t
t
t
t
t
Output Enable to Data Valid  
OE to Low Z  
4.0  
4.4  
4.7  
5.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
OE  
0
0
0
0
0
0
0
0
OLZ  
OHZ  
OE to High Z  
4.0  
4.0  
4.0  
4.0  
4.4  
4.4  
4.4  
4.4  
4.7  
4.7  
NA  
NA  
5.0  
5.0  
NA  
NA  
Clock to Data Valid  
CD2  
CA2  
CM2  
DC  
Clock to Counter Address Valid  
Clock to Mask Register Readback Valid  
Data Output Hold After Clock HIGH  
Clock HIGH to Output High Z  
Clock HIGH to Output Low Z  
Clock to INT Set Time  
1.0  
0
1.0  
0
1.0  
0
1.0  
0
4.0  
4.0  
6.7  
6.7  
5.0  
5.0  
4.4  
4.4  
7.5  
7.5  
5.7  
5.7  
4.7  
4.7  
7.5  
7.5  
NA  
NA  
5.0  
5.0  
10  
CKHZ  
CKLZ  
1.0  
0.5  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
0.5  
0.5  
1.0  
0.5  
0.5  
NA  
NA  
1.0  
0.5  
0.5  
NA  
NA  
SINT  
Clock to INT Reset Time  
Clock to CNTINT Set Time  
Clock to CNTINT Reset time  
10  
RINT  
NA  
NA  
SCINT  
RCINT  
Port to Port Delays  
t
Clock to Clock Skew  
5.2  
6.0  
6.0  
8.0  
ns  
CCS  
Master Reset Timing  
t
t
t
t
t
Master Reset Pulse Width  
7.0  
6.0  
6.0  
7.5  
6.0  
7.5  
7.5  
6.0  
7.5  
10.0  
8.5  
ns  
ns  
ns  
ns  
ns  
RS  
Master Reset Setup Time  
RSS  
Master Reset Recovery Time  
Master Reset to Outputs Inactive  
10.0  
RSR  
10.0  
10.0  
10.0  
10.0  
10.0  
NA  
10.0  
NA  
RSF  
Master Reset to Counter Interrupt Flag  
Reset Time  
RSCNTINT  
Notes  
20. This parameter is guaranteed by design, but it is not production tested.  
21. Test conditions used are Load 2.  
Document #: 38-06070 Rev. *H  
Page 15 of 32  
   
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
JTAG Timing  
167/133/100  
Unit  
Parameter  
Description  
Min  
Max  
f
t
t
t
t
t
t
t
t
t
Maximum JTAG TAP Controller Frequency  
TCK Clock Cycle Time  
10  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
JTAG  
TCYC  
TH  
100  
40  
40  
10  
10  
10  
10  
TCK Clock HIGH Time  
TCK Clock LOW Time  
TL  
TMS Setup to TCK Clock Rise  
TMS Hold After TCK Clock Rise  
TDI Setup to TCK Clock Rise  
TDI Hold After TCK Clock Rise  
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
TMSS  
TMSH  
TDIS  
TDIH  
TDOV  
TDOX  
30  
0
Figure 7. JTAG Switching Waveform  
t
t
TL  
TH  
Test Clock  
TCK  
t
TCYC  
t
TMSS  
t
TMSH  
Test Mode Select  
TMS  
t
TDIS  
t
TDIH  
Test Data-In  
TDI  
Test Data-Out  
TDO  
t
TDOX  
t
TDOV  
Document #: 38-06070 Rev. *H  
Page 16 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms  
Figure 8. Master Reset  
tRS  
MRST  
tRSF  
ALL  
ADDRESS/  
DATA  
tRSS  
INACTIVE  
LINES  
tRSR  
ALL  
OTHER  
INPUTS  
ACTIVE  
TMS  
CNTINT  
INT  
TDO  
Figure 9. Read Cycle  
tCYC2  
tCH2  
tCL2  
CLK  
CE  
tSC  
tHC  
tSC  
tHC  
tSB  
tHB  
B0–B3  
R/W  
tSW  
tSA  
tHW  
tHA  
ADDRESS  
DATAOUT  
An  
An+1  
An+2  
An+3  
tDC  
1 Latency  
tCD2  
Qn  
Qn+1  
Qn+2  
tOHZ  
tCKLZ  
tOLZ  
OE  
t
OE  
Notes  
22. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.  
23. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.  
24. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.  
IH  
25. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.  
IL  
IH  
Numbers are for reference only.  
Document #: 38-06070 Rev. *H  
Page 17 of 32  
       
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 10. Bank Select Read  
t
CYC2  
t
t
CL2  
CH2  
CLK  
t
t
t
HA  
SA  
A
3
A
4
ADDRESS  
A
5
A
A
A
2
(B1)  
0
1
t
HC  
SC  
CE  
(B1)  
t
t
t
t
CKHZ  
t
t
t
CD2  
CD2  
CD2  
HC  
CKHZ  
SC  
Q
Q
Q
3
DATA  
1
0
OUT(B1)  
t
t
HA  
SA  
t
t
t
CKLZ  
DC  
DC  
A
A
4
A
ADDRESS  
A
0
A
A
3
5
(B2)  
1
2
t
t
HC  
SC  
CE  
(B2)  
t
t
t
CD2  
t
CD2  
CKHZ  
t
SC  
HC  
DATA  
OUT(B2)  
Q
Q
4
2
t
t
CKLZ  
CKLZ  
[25, 28, 29, 30, 31]  
Figure 11. Read-to-Write-to-Read (OE = LOW)  
tCYC2  
tCH2  
tCL2  
CLK  
CE  
tSC  
tHC  
tSW  
tHW  
R/W  
tSW  
tHW  
An  
An+1  
An+2  
An+2  
An+3  
An+4  
ADDRESS  
DATAIN  
tSD tHD  
tSA  
tHA  
Dn+2  
tCD2  
tCD2  
tCD2  
tCKHZ  
Qn  
Qn+3  
Qn+1  
DATAOUT  
tCKLZ  
READ  
NO OPERATION  
WRITE  
READ  
Notes  
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851AV/CY7C0852AV device from this data  
sheet. ADDRESS = ADDRESS  
.
(B2)  
(B1)  
27. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.  
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.  
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.  
30. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.  
0
1
31. CE = B0 – B3 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed  
0
1
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.  
Document #: 38-06070 Rev. *H  
Page 18 of 32  
           
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 12. Read-to-Write-to-Read (OE Controlled)  
tCYC2  
tCH2  
tCL2  
CLK  
CE  
tSC  
tHC  
tHW  
tSW  
R/W tSW  
tHW  
An  
An+1  
An+2  
An+3  
An+4  
An+5  
ADDRESS  
tSA  
tHA  
tSD tHD  
Dn+2  
DATAIN  
Dn+3  
tCD2  
tCD2  
tCD2  
DATAOUT  
Qn  
Qn+4  
Qn+1  
tOHZ  
OE  
READ  
WRITE  
READ  
Figure 13. Read with Address Counter Advance  
tCYC2  
tCL2  
tCH2  
CLK  
tSA  
tHA  
ADDRESS  
An  
tSAD  
tHAD  
ADS  
tSAD  
tHAD  
CNTEN  
tSCN  
tHCN  
tSCN  
tHCN  
tCD2  
Qx–1  
Qx  
tDC  
Qn  
Qn+1  
COUNTER HOLD  
Qn+2  
DATAOUT  
Qn+3  
READ  
READ WITH COUNTER  
READ WITH COUNTER  
EXTERNAL  
ADDRESS  
Document #: 38-06070 Rev. *H  
Page 19 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 14. Write with Address Counter Advance  
tCYC2  
tCL2  
tCH2  
CLK  
tSA  
tHA  
An  
ADDRESS  
INTERNAL  
ADDRESS  
An  
An+1  
An+2  
An+3  
An+4  
tSAD  
tHAD  
ADS  
CNTEN  
DATAIN  
tSCN  
tHCN  
Dn  
Dn+1  
Dn+1  
Dn+2  
Dn+3  
Dn+4  
tSD  
tHD  
WRITE EXTERNAL  
ADDRESS  
WRITE WITH WRITE COUNTER  
COUNTER HOLD  
WRITE WITH COUNTER  
Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write  
tCYC2  
tCL2  
tCH2  
CLK  
tSC  
tHC  
CE  
tSW  
tHW  
R/W  
tSW tHW  
tHA  
tHA  
tSA  
tSA  
An+4  
An  
An+3  
An+1  
An+2  
ADDRESS  
OE  
tHD  
tSD  
DATAIN  
Dn+3  
tCD2  
DATAOUT  
Qn+1  
Qn  
Qn+2  
DISABLED  
READ  
READ  
READ  
WRITE  
READ  
Document #: 38-06070 Rev. *H  
Page 20 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 16. Disabled-to-Write-to-Read-to-Write-to-Read  
tCYC2  
tCH2  
tCL2  
CLK  
tSC  
tHC  
CE  
tHW  
tSW  
R/W  
tSA  
tHA  
An+4  
An+3  
An+2  
ADDRESS  
OE  
An  
An+1  
tOE  
tHD  
tSD  
Dn  
DATAIN  
Dn+2  
tCD2  
Qn+3  
Qn+1  
DATAOUT  
DISABLED  
WRITE  
READ  
READ  
READ  
WRITE  
Figure 17. Disabled-to-Read-to-Disabled-to-Write  
t
CYC2  
t
t
CL2  
CH2  
CLK  
CE  
t
t
HC  
SC  
R/W  
t
t
HW  
SW  
A
A
ADDRESS  
A
A
A
n+4  
n+3  
n+2  
n+1  
n
t
t
HA  
SA  
t
OE  
OE  
t
OHZ  
t
t
HD  
SD  
DATAIN  
D
n+2  
t
CD2  
DATAOUT  
Qn+3  
Q
n
DISABLED  
READ  
DISABLED  
WRITE  
READ  
READ  
Document #: 38-06070 Rev. *H  
Page 21 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 18. Read-to-Readback-to-Read-to-Read (R/W = HIGH)  
tCYC2  
tCH2  
tCL2  
CLK  
ADS  
tHAD  
tSAD  
CNTEN  
tSCN  
tHCN  
tSA  
tHA  
An+1  
ADDRESS  
COUNTER  
INTERNAL  
ADDRESS  
An  
An+1  
An+2  
An+3  
An+4  
OE  
DATAOUT  
Qn+1  
Qn+3  
Qn+2  
READ  
INCREMENT  
NO OPERATION  
READ  
READ  
READ  
READBACK  
INCREMENT  
INCREMENT  
INCREMENT  
Document #: 38-06070 Rev. *H  
Page 22 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 19. Counter Reset  
tCYC2  
tCH2 tCL2  
CLK  
tHA  
Am  
tSA  
Ap  
An  
ADDRESS  
INTERNAL  
Ax  
Ap  
An  
1
0
Am  
ADDRESS  
tHW  
tSW  
R/W  
ADS  
CNTEN  
CNTRST  
tHRST  
tSRST  
tHD  
tSD  
DATAIN  
D0  
tCD2  
tCD2  
DATAOUT  
Q0  
Qn  
Q1  
tCKLZ  
READ  
ADDRESS 0  
READ  
ADDRESS 1  
READ  
ADDRESS An  
COUNTER  
RESET  
WRITE  
ADDRESS 0  
READ  
ADDRESS Am  
Notes  
32. CE = B0 – B3 = LOW; CE = MRST = CNT/MSK = HIGH.  
0
1
33. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.  
34. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.  
Document #: 38-06070 Rev. *H  
Page 23 of 32  
     
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 20. Readback State of Address Counter or Mask Register  
tCYC2  
tCH2 tCL2  
CLK  
tCA2 or tCM2  
tSA  
tHA  
EXTERNAL  
An*  
An  
ADDRESS  
A0–A16  
INTERNAL  
ADDRESS  
A
A
A
A
n+4  
n+3  
A
n+1  
n+2  
n
tSAD  
tHAD  
ADS  
CNTEN  
tSCN  
tHCN  
tCD2  
tCKHZ  
Qn  
tCKLZ  
DATAOUT  
Qn+1  
Qx-1  
Qn+2  
Qx-2  
Q
n+3  
LOAD  
EXTERNAL  
ADDRESS  
READBACK  
COUNTER  
INTERNAL  
ADDRESS  
INCREMENT  
Notes  
35. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.  
0
1
36. Address in output mode. Host must not be driving address bus after t  
in next clock cycle.  
CKLZ  
37. Address in input mode. Host can drive address bus after t  
.
CKHZ  
38. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.  
Document #: 38-06070 Rev. *H  
Page 24 of 32  
       
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read  
tCYC2  
tCL2  
tCH2  
CLKL  
tHA  
tSA  
L_PORT  
ADDRESS  
An  
tSW  
tHW  
R/WL  
tCKHZ  
tSD  
tHD  
tCKLZ  
L_PORT  
DATAIN  
Dn  
tCCS  
tCYC2  
tCL2  
CLKR  
tCH2  
tSA  
tHA  
R_PORT  
ADDRESS  
An  
R/WR  
tCD2  
R_PORT  
DATAOUT  
Qn  
tDC  
Notes  
39. CE = OE = ADS = CNTEN = B0 – B3 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.  
0
1
40. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t  
is violated, indeterminate data is Read out.  
CCS  
41. If t  
< minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * t  
+ t  
) after the rising edge of R_Port's clock. If t  
CCS  
CYC2  
CD2 CCS  
> minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t  
+ t  
) after the rising edge of R_Port's clock.  
CYC2  
CD2  
Document #: 38-06070 Rev. *H  
Page 25 of 32  
     
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 22. Counter Interrupt and Retransmit  
tCYC2  
tCL2  
tCH2  
CLK  
tSCM  
tHCM  
CNT/MSK  
ADS  
CNTEN  
COUNTER  
INTERNAL  
ADDRESS  
1FFFE  
tSCINT  
1FFFC  
Last_Loaded  
1FFFD  
1FFFF  
tRCINT  
Last_Loaded +1  
CNTINT  
Notes  
42. CE = OE = B0 – B3 = LOW; CE = R/W = CNTRST = MRST = HIGH.  
0
1
43. CNTINT is always driven.  
44. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.  
45. The mask register assumed to have the value of 1FFFFh.  
Document #: 38-06070 Rev. *H  
Page 26 of 32  
       
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Switching Waveforms (continued)  
Figure 23. MailBox Interrupt Timing  
tCYC2  
tCL2  
tCH2  
CLKL  
tSA tHA  
3FFFF  
L_PORT  
ADDRESS  
An+1  
An  
An+2  
An+3  
tSINT  
tRINT  
INTR  
tCYC2  
tCL2  
tCH2  
CLKR  
tSA tHA  
Am  
R_PORT  
ADDRESS  
Am+1  
3FFFF  
Am+3  
Am+4  
Table 7. Read/Write and Enable Operation (Any Port)  
Inputs  
Outputs  
Operation  
OE  
CLK  
CE  
CE  
R/W  
DQ DQ  
0
1
0
35  
X
H
X
X
High-Z  
Deselected  
Deselected  
Write  
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z  
D
IN  
H
X
D
Read  
OUT  
H
X
High-Z  
Outputs Disabled  
Notes  
46. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.  
0
1
47. Address “3FFFF” is the mailbox location for R_Port of a 9M device.  
48. L_Port is configured for Write operation, and R_Port is configured for Read operation.  
49. At least one byte enable (B0 – B3) is required to be active during interrupt operations.  
50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.  
51. OE is an asynchronous input signal.  
52. When CE changes state, deselection and Read happen after one cycle of latency.  
Document #: 38-06070 Rev. *H  
Page 27 of 32  
             
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Ordering Information  
256K  
×
36 (9M) 3.3V Synchronous CY7C0853AV Dual-Port SRAM  
Package  
Speed  
(MHz)  
Operating  
Range  
Ordering Code  
Package Type  
Diagram  
133 CY7C0853AV-133BBC  
CY7C0853AV-133BBI  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch (Pb-Free)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
Commercial  
Industrial  
CY7C0853AV-133BBXI  
100 CY7C0853AV-100BBC  
CY7C0853AV-100BBI  
Commercial  
Industrial  
128K  
×
36 (4M) 3.3V Synchronous CY7C0852AV Dual-Port SRAM  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
167 CY7C0852AV-167BBC  
CY7C0852AV-167AC  
CY7C0852AV-167AXC  
133 CY7C0852AV-133BBC  
CY7C0852AV-133AC  
CY7C0852AV-133AXC  
CY7C0852AV-133BBI  
CY7C0852AV-133AI  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm) (Pb-Free)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm) (Pb-Free)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm) (Pb-Free)  
Commercial  
Commercial  
Industrial  
CY7C0852AV-133AXI  
64K  
×
36 (2M) 3.3V Synchronous CY7C0851AV Dual-Port SRAM  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
167 CY7C0851AV-167BBC  
CY7C0851AV-167BBXC  
CY7C0851AV-167AC  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch (Pb-Free)  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm) (Pb-Free)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm) (Pb-Free)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm) (Pb-Free)  
Commercial  
CY7C0851AV-167AXC  
133 CY7C0851AV-133BBC  
CY7C0851AV-133AC  
Commercial  
Industrial  
CY7C0851AV-133AXC  
CY7C0851AV-133BBI  
CY7C0851AV-133AI  
CY7C0851AV-133AXI  
32K  
×
36 (1M) 3.3V Synchronous CY7C0850AV Dual-Port SRAM  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
167 CY7C0850AV-167BBC  
CY7C0850AV-167AC  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
51-85114 172-Ball Grid Array (15 x 15 x 1.25 mm) with 1 mm pitch  
51-85132 176-Pin Thin Quad Flat Pack (24 x 24 x 1.4 mm)  
Commercial  
Commercial  
Industrial  
133 CY7C0850AV-133BBC  
CY7C0850AV-133AC  
CY7C0850AV-133BBI  
CY7C0850AV-133AI  
Document #: 38-06070 Rev. *H  
Page 28 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Package Diagrams  
Figure 24. 172-Ball FBGA (15 x 15 x 1.25 mm) (51-85114)  
51-85114-*B  
Document #: 38-06070 Rev. *H  
Page 29 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Package Diagrams  
Figure 25. 176-Pin Thin Quad Flat Pack (24 × 24 × 1.4 mm) (51-85132)  
51-85132-**  
Document #: 38-06070 Rev. *H  
Page 30 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Document History Page  
Document Title: CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36  
Synchronous Dual-Port RAM  
Document Number: 38-06070  
Submis-  
sion Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
127809  
08/04/03  
SPN  
This data sheet has been extracted from another data sheet: the 2M/4M/9M  
data sheet. The following changes have been made from the original as  
pertains to this device:  
Updated capacitance values  
Updated “Read-to-Write-to-Read (OE Controlled)” waveform  
Revised static discharge voltage  
Corrected 0853 pins L3 and L12  
Added discussion of Pause/Restart for JTAG boundary scan  
Power up requirements added to Maximum Ratings information  
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns  
Updated Icc numbers  
Updated tHA, tHB, tHD for -100 speed  
Separated out from the 4M data sheet  
Added 133-MHz Industrial device to Ordering Information table  
*A  
*B  
*C  
210948  
216190  
231996  
See ECN  
YDT  
Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.  
See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change  
See ECN  
YDT  
Removed “A particular port can write to a certain location while another port is  
reading that location.” from Functional Description.  
*D  
238938  
See ECN  
WWZ  
Merged 0853 (9Mx36) with 0852 (4Mx36) and 0851(2Mx36), add 0850 (1M x36),  
to the data sheet.  
Added product selection table.  
Added JTAG ID code for 1M device.  
Added note 14.  
Updated boundary scan section.  
Updated function description for the merge and addition.  
*E  
*F  
329122  
389877  
See ECN  
See ECN  
SPN  
KGH  
Updated Marketing part numbers  
Updated Read-to-Write-to-Read timing diagram to reflect accurate bus  
turnaround scheme.  
Added I  
Changed t  
Changed t  
SB5  
to 10ns  
to 10ns  
RSCNTINT  
RSF  
Added figure Disabled-to-Read-to-Read-to-Read-to-Write  
Added figure Disabled-to-Write-to-Read-to-Write-to-Read  
Added figure Disabled-to-Read-to-Disabled-to-Write  
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)  
Updated Read-to-Write-to-Read timing diagram to correct the data out schemes  
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to correct  
the chip enable, data in, and data out schemes  
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to correct  
the chip enable and output enable schemes  
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the  
chip enable and output enable schemes  
*G  
*H  
391597  
See ECN  
SPN  
Updated counter reset section to reflect mirror register behavior  
2544945  
07/29/08 VKN/AESA Updated Template. Updated ordering information  
Document #: 38-06070 Rev. *H  
Page 31 of 32  
CY7C0850AV, CY7C0851AV  
CY7C0852AV, CY7C0853AV  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
psoc.cypress.com/solutions  
psoc.cypress.com/low-power  
psoc.cypress.com/precision-analog  
psoc.cypress.com/lcd-drive  
psoc.cypress.com/can  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
psoc.cypress.com/usb  
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used  
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use  
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support  
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-06070 Rev. *H  
Revised July 29, 2008  
Page 32 of 32  
FLEx36 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.  

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