Cypress CY8C23433 User Manual

CY8C23433, CY8C23533  
PSoC® Programmable System-on-Chip™  
Features  
Powerful Harvard Architecture Processor  
M8C Processor Speeds to 24 MHz  
8x8 Multiply, 32-Bit Accumulate  
Complete Development Tools  
Free Development Software (PSoC Designer™)  
Full-Featured In-Circuit Emulator and Programmer  
Full Speed Emulation  
Low Power at High Speed  
3.0 to 5.25V Operating Voltage  
Complex Breakpoint Structure  
Industrial Temperature Range: -40°C to +85°C  
128K Bytes Trace Memory  
Advanced Peripherals (PSoC Blocks)  
4 Rail-to-Rail analog PSoC Blocks Provide:  
• Up to 14-Bit ADCs  
Logic Block Diagram  
• Up to 8-Bit DACs  
Analog  
Port 3 Port 2 Port 1 Port 0  
Drivers  
• Programmable Gain Amplifiers  
• Programmable Filters and Comparators  
4 Digital PSoC Blocks Provide:  
• 8 to 32-Bit Timers, Counters, and PWMs  
• CRC and PRS Modules  
PSoC CORE  
System Bus  
• Full-Duplex UART  
Global Digital Interconnect  
Global Analog Interconnect  
• Multiple SPIMasters or Slaves  
• Connectable to All GPIO Pins  
SRAM  
256 Bytes  
SROM  
Flash 8K  
Complex Peripherals by Combining Blocks  
High-Speed 8-Bit SAR ADC Optimized for Motor Control  
Sleep and  
Watchdog  
CPUCore(M8C)  
Interrupt  
Controller  
Precision, Programmable Clocking  
Internal ±2.5% 24/48 MHz Oscillator  
MultipleClockSources  
(IncludesIMO,ILO, PLL, andECO)  
High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL  
Optional External Oscillator, up to 24 MHz  
Internal Oscillator for Watchdog and Sleep  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref  
Digital  
Block  
Array  
Analog  
Flexible On-Chip Memory  
Block Array  
8K Bytes Flash Program Storage 50,000 Erase/Write Cycles  
256 Bytes SRAM Data Storage  
In-System Serial Programming (ISSP)  
Partial Flash Updates  
2 Columns  
4 Blocks  
1 Row  
4 Blocks  
Analog  
Input  
Muxing  
SAR8 ADC  
Flexible Protection Modes  
EEPROM Emulation in Flash  
Programmable Pin Configurations  
25 mA Sink on all GPIO  
Pull up, Pull Down, High Z, Strong, or Open Drain Drive  
Modes on All GPIO  
Up to Ten Analog Inputs on GPIO  
Two 30 mA Analog Outputs on GPIO  
Configurable Interrupt on All GPIO  
Internal  
Voltage  
Ref.  
Digital  
Clocks  
Multiply  
Accum.  
POR and LVD  
System Resets  
I2C  
Decimator  
SYSTEM RESOURCES  
Additional System Resources  
2
I CSlave, Master, and Multi-Master to 400 kHz  
Watchdog and Sleep Timers  
User-Configurable Low Voltage Detection  
Integrated Supervisory Circuit  
On-chip Precision Voltage Reference  
Cypress Semiconductor Corporation  
Document Number: 001-44369 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 05, 2008  
 
CY8C23433, CY8C23533  
Figure 2. Analog System Block Diagram  
Analog System  
P0[7]  
P0[6]  
P0[4]  
The Analog system consists of an 8-bit SAR ADC and four  
configurable blocks. The programmable 8-bit SAR ADC is an  
optimized ADC that runs up to 300 Ksps, with monotonic  
guarantee. It also has the features to support a motor control  
application.  
P0[5]  
P0[3]  
P0[1]  
P0[2]  
P0[0]  
Each analog block consists of an opamp circuit allowing the  
creation of complex analog signal flows. Analog peripherals are  
very flexible and can be customized to support specific  
application requirements. Some of the more common PSoC  
analog functions (most available as user modules) are:  
P2[6]  
P2[4]  
P2[3]  
P2[1]  
P2[2]  
P2[0]  
Filters (2 band pass, low-pass)  
Amplifiers (up to 2, with selectable gain to 48x)  
Instrumentation amplifiers (1 with selectable gain to 93x)  
Comparators (1, with 16 selectable thresholds)  
DAC (6 or 9 -bit DAC)  
Array Input Configuration  
Multiplying DAC (6 or 9 -bit DAC)  
High current output drivers (two with 30 mA drive)  
1.3V reference (as a System Resource)  
DTMF dialer  
ACI0[1:0]  
ACI1[1:0]  
Block Array  
ACB00 ACB01  
Modulators  
ASD11  
ASC21  
Correlators  
Peak detectors  
Many other topologies possible  
P0[7:0]  
Analog blocks are arranged in a column of three, which includes  
one CT (Continuous Time) and two SC (Switched Capacitor)  
blocks. The Analog Column 0 contains the SAR8 ADC block  
rather than the standard SC blocks.  
ACI2[3:0]  
8-Bit SAR ADC  
Analog Reference  
Interface to  
Digital System  
Re fere nce  
Generators  
Ref Hi  
RefLo  
AGND  
AGNDIn  
Ref In  
Bandgap  
M8C Interface (Address Bus, Data Bus, Etc.)  
Document Number: 001-44369 Rev. *B  
Page 3 of 37  
CY8C23433, CY8C23533  
Additional System Resources  
Getting Started  
System Resources, some of which are listed in the previous  
sections, provide additional capability useful to complete  
systems. Additional resources include a multiplier, decimator,  
low voltage detection, and power on reset. Brief statements  
describing the merits of each system resource follow:  
The quickest path to understanding the PSoC silicon is by  
reading this data sheet and using the PSoC Designer Integrated  
Development Environment (IDE). This data sheet is an overview  
of the PSoC integrated circuit and presents specific pin, register,  
and electrical specifications. For in-depth information, along with  
detailed programming information, refer the PSoC Mixed-Signal  
Array Technical Reference Manual.  
Digital clock dividers provide three customizable clock  
frequencies for use in applications. The clocks can be routed  
to both the digital and analog systems. Additional clocks can  
be generated using digital PSoC blocks as clock dividers.  
For latest Ordering, Packaging, and Electrical Specification  
information, refer the latest PSoC device data sheets on the web  
A multiply accumulate (MAC) provides a fast 8-bit multiplier  
with 32-bit accumulate, to assist in both general math and  
digital filters.  
To determine which PSoC device meets your requirements,  
navigate through the PSoC Decision Tree in the Application Note  
AN2209 at http://www.cypress.com and select Application Notes  
under the Design Resources.  
The decimator provides a custom hardware filter for digital  
signal processing applications including the creation of Delta  
Sigma ADCs.  
Development Kits  
TheI2Cmoduleprovides100and400kHzcommunicationover  
two wires. Slave, master, and multi-master modes are all  
supported.  
Development Kits are available from the following distributors:  
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store  
contains development kits, C compilers, and all accessories for  
PSoC development. Go to the Cypress Online Store web site at  
Low Voltage Detection (LVD) interrupts can signal the  
application of falling voltage levels, while the advanced POR  
(Power On Reset) circuit eliminates the need for a system  
supervisor.  
Technical Training Modules  
Free PSoC technical training modules are available for users  
new to PSoC. Training modules cover designing, debugging,  
An internal 1.3V reference provides an absolute reference for  
the analog system, including ADCs and DACs.  
advanced  
analog  
and  
CapSense.  
Go  
to  
PSoC Device Characteristics  
Consultants  
Depending on the PSoC device characteristics, the digital and  
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or  
3 analog blocks. The following table lists the resources available  
for specific PSoC device groups.  
Certified PSoC Consultants offer everything from technical  
assistance to completed PSoC designs. To contact or become a  
PSoC Consultant go to http://www.cypress.com, click on Design  
Support located at the top of the web page, and select CYPros  
Consultants.  
Table 1. PSoC Device Characteristics  
Technical Support  
PSoC Part  
Number  
PSoC application engineers take pride in fast and accurate  
response. They can be reached with a 4-hour guaranteed  
CY8C29x66 upto 4  
64  
16 12  
4
4
4
4
12  
12  
No  
No  
Application Notes  
CY8C27x43 upto 2  
44  
8
12  
A long list of application notes can assist you in every aspect of  
your design effort. To view the PSoC application notes, go to  
CY8C24x94 56  
1
4
4
48  
12  
2
2
2
6
4
No  
CY8C23X33 upto 1  
26  
Yes  
CY8C24x23A upto 1  
24  
4
4
12  
28  
2
0
2
2
6
No  
No  
[2]  
CY8C21x34 upto 1  
28  
4
[2]  
[3]  
CY8C21x23 16  
1
4
0
8
0
0
2
0
4
3
No  
No  
CY8C20x34 upto 0  
28  
28  
Notes  
1. One complete column, plus one Continuous Time Block.  
2. Limited analog functionality.  
3. Two analog blocks and one CapSense.  
Document Number: 001-44369 Rev. *B  
Page 4 of 37  
       
CY8C23433, CY8C23533  
PSoC Designer Software Subsystems  
Development Tools  
PSoC Designer is a Microsoft® Windows-based, integrated  
Device Editor  
development  
environment  
for  
the  
Programmable  
The Device Editor subsystem allows the user to select different  
onboard analog and digital components called user modules  
using the PSoC blocks. Examples of user modules are ADCs,  
DACs, Amplifiers, and Filters.  
System-on-Chip (PSoC) devices. The PSoC Designer IDE and  
application runs on Windows NT 4.0, Windows 2000, Windows  
Millennium (Me), or Windows XP (refer section PSoC Designer  
The device editor also supports easy development of multiple  
configurations and dynamic reconfiguration. Dynamic  
configuration allows for changing configurations at run time.  
PSoC Designer helps the customer to select an operating  
configuration for the PSoC, write application code that uses the  
PSoC, and debug the application. This system provides design  
database management by project, an integrated debugger with  
In-Circuit Emulator, in-system programming support, and the  
CYASM macro assembler for the CPUs.  
PSoC Designer sets up power on initialization tables for selected  
PSoC block configurations and creates source code for an  
application framework. The framework contains software to  
operate the selected components and, if the project uses more  
than one operating configuration, contains routines to switch  
between different sets of PSoC block configurations at run time.  
PSoC Designer can print out a configuration sheet for a given  
project configuration for use during application programming in  
conjunction with the Device Data Sheet. Once the framework is  
generated, the user can add application-specific code to flesh  
out the framework. It is also possible to change the selected  
components and regenerate the framework.  
PSoC Designer also supports a high-level C language compiler  
developed specifically for the devices in the family.  
Figure 3. PSoC Designer Subsystems  
Context  
Sensitive  
Help  
Graphical Designer  
PSoC  
Designer  
Interface  
Design Browser  
The Design Browser allows users to select and import  
preconfigured designs into the user’s project. Users can easily  
browse  
a
catalog of preconfigured designs to facilitate  
time-to-design. Examples provided in the tools include a  
300-baud modem, LIN Bus master and slave, fan controller, and  
magnetic card reader.  
Importable  
Design  
Database  
Application Editor  
PSoC  
Configuration  
Sheet  
Device  
Database  
In the Application Editor you can edit your C language and  
Assembly language source code. You can also assemble,  
compile, link, and build.  
PSoC  
Designer  
Core  
Application  
Database  
Assembler. The macro assembler allows the assembly code to  
be merged seamlessly with C code. The link libraries  
automatically use absolute addressing or can be compiled in  
relative mode, and linked with other software modules to get  
absolute addressing.  
Manufacturing  
Information  
File  
Engine  
Project  
Database  
User  
Modules  
Library  
C Language Compiler. A C language compiler is available that  
supports the PSoC family of devices. Even if you have never  
worked in the C language before, the product quickly allows you  
to create complete C programs for the PSoC family devices.  
The embedded, optimizing C compiler provides all the features  
of C tailored to the PSoC architecture. It comes complete with  
embedded libraries providing port and bus operations, standard  
keypad and display support, and extended math functionality.  
Emulation  
Pod  
In-Circuit  
Emulator  
Device  
Programmer  
Document Number: 001-44369 Rev. *B  
Page 5 of 37  
 
CY8C23433, CY8C23533  
Debugger  
of resolution. The user module parameters permit you to  
establish the pulse width and duty cycle. User modules also  
provide tested software to cut your development time. The user  
module application programming interface (API) provides high  
level functions to control and respond to hardware events at  
run-time. The API also provides optional interrupt service  
routines that you can adapt as needed.  
The PSoC Designer Debugger subsystem provides hardware  
in-circuit emulation, allowing the designer to test the program in  
a physical system while providing an internal view of the PSoC  
device. Debugger commands allow the designer to read and  
program and read and write data memory, read and write IO  
registers, read and write CPU registers, set and clear  
breakpoints, and provide program run, halt, and step control. The  
debugger also allows the designer to create a trace buffer of  
registers and memory locations of interest.  
The API functions are documented in user module data sheets  
that are viewed directly in the PSoC Designer IDE. These data  
sheets explain the internal operation of the user module and  
provide performance specifications. Each data sheet describes  
the use of each user module parameter and documents the  
setting of each register controlled by the user module.  
Online Help System  
The online help system displays online, context-sensitive help  
for the user. Designed for procedural and quick reference, each  
functional subsystem has its own context-sensitive help. This  
system also provides tutorials and links to FAQs and an Online  
Support Forum to aid the designer in getting started.  
The development process starts when you open a new project  
and bring up the Device Editor, a graphical user interface (GUI)  
for configuring the hardware. You pick the user modules you  
need for your project and map them onto the PSoC blocks with  
point-and-click simplicity. Next, you build signal chains by  
interconnecting user modules to each other and the IO pins. At  
this stage, you also configure the clock source connections and  
enter parameter values directly or by selecting values from  
drop-down menus. When you are ready to test the hardware  
configuration or move on to developing code for the project, you  
perform the “Generate Application” step. This causes PSoC  
Designer to generate source code that automatically configures  
the device to your specification and provides the high-level user  
module API functions.  
Hardware Tools  
In-Circuit Emulator  
A low cost, high functionality ICE (In-Circuit Emulator) is  
available for development support. This hardware has the  
capability to program single devices.  
The emulator consists of a base unit that connects to the PC by  
way of a USB port. The base unit is universal and can operate  
with all PSoC devices. Emulation pods for each device family are  
available separately. The emulation pod takes the place of the  
PSoC device in the target board and performs full speed (24  
MHz) operation.  
Figure 4. User Module/Source Code Development Flows  
Device Editor  
Designing with User Modules  
Placement  
User  
Module  
Selection  
Source  
Code  
Generator  
and  
Parameter  
-ization  
The development process for the PSoC device differs from that  
of a traditional fixed function microprocessor. The configurable  
analog and digital hardware blocks give the PSoC architecture a  
unique flexibility that pays dividends in managing specification  
change during development and by lowering inventory costs.  
These configurable resources, called PSoC Blocks, have the  
ability to implement a wide variety of user-selectable functions.  
Each block has several registers that determine its function and  
connectivity to other blocks, multiplexers, buses and to the IO  
pins. Iterative development cycles permit you to adapt the  
hardware and the software. This substantially lowers the risk of  
having to select a different part to meet the final design  
requirements.  
Generate  
Application  
Application Editor  
Source  
Code  
Editor  
Project  
Manager  
Build  
Manager  
To speed the development process, the PSoC Designer  
Integrated Development Environment (IDE) provides a library of  
pre-built, pre-tested hardware peripheral functions, called “User  
Modules.” User modules make selecting and implementing  
peripheral devices simple, and come in analog, digital, and  
mixed signal varieties. The standard User Module library  
contains over 50 common peripherals such as ADCs, DACs  
Timers, Counters, UARTs, and other uncommon peripherals  
such as DTMF Generators and Bi-Quad analog filter sections.  
Build  
All  
Debugger  
Event &  
Breakpoint  
Manager  
Interface  
to ICE  
Storage  
Each user module establishes the basic register settings that  
implement the selected function. It also provides parameters that  
allow you to tailor its precise configuration to your particular  
application. For example, a Pulse Width Modulator User Module  
configures one or more digital PSoC blocks, one for each 8 bits  
Inspector  
Document Number: 001-44369 Rev. *B  
Page 6 of 37  
CY8C23433, CY8C23533  
The next step is to write your main program, and any  
sub-routines using PSoC Designer’s Application Editor  
subsystem. The Application Editor includes a Project Manager  
that allows you to open the project source code files (including  
all generated code files) from a hierarchal view. The source code  
editor provides syntax coloring and advanced edit features for  
both C and assembly language. File search capabilities include  
simple string searches and recursive “grep-style” patterns. A  
single mouse click invokes the Build Manager. It employs a  
professional-strength “makefile” system to automatically analyze  
all file dependencies and run the compiler and assembler as  
necessary. Project-level options control optimization strategies  
used by the compiler and linker. Syntax errors are displayed in a  
console window. Double clicking the error message takes you  
directly to the offending line of source code. When all is correct,  
the linker builds a HEX file image suitable for programming.  
Table 2. Acronyms Used (continued)  
Acronym  
PWM  
RAM  
Description  
pulse width modulator  
random access memory  
read only memory  
ROM  
SC  
switched capacitor  
Units of Measure  
A units of measure table is located in the section Electrical  
abbreviations used to measure the PSoC devices.  
Numeric Naming  
Hexadecimal numbers are represented with all letters in  
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or  
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’  
prefix, the C coding convention. Binary numbers have an  
appended lowercase ‘b’ (for example, 01010100b’ or  
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.  
The last step in the development process takes place inside the  
PSoC Designer’s Debugger subsystem. The Debugger  
downloads the HEX image to the In-Circuit Emulator (ICE) where  
it runs at full speed. Debugger capabilities rival those of systems  
costing many times more. In addition to traditional single-step,  
run-to-breakpoint and watch-variable features, the Debugger  
provides a large trace buffer and allows you define complex  
breakpoint events that include monitoring address and data bus  
values, memory locations and external signals.  
Document Conventions  
Acronyms Used  
The following table lists the acronyms that are used in this  
document.  
Table 2. Acronyms Used  
Acronym  
AC  
Description  
alternating current  
ADC  
API  
analog-to-digital converter  
application programming interface  
central processing unit  
continuous time  
CPU  
CT  
DAC  
DC  
digital-to-analog converter  
direct current  
EEPROM electrically erasable programmable read-only  
memory  
FSR  
GPIO  
IO  
full scale range  
general purpose IO  
input/output  
IPOR  
LSb  
imprecise power on reset  
least-significant bit  
low voltage detect  
most-significant bit  
program counter  
LVD  
MSb  
PC  
POR  
PPOR  
PSoC®  
power on reset  
precision power on reset  
Programmable System-on-Chip™  
Document Number: 001-44369 Rev. *B  
Page 7 of 37  
CY8C23433, CY8C23533  
Pinouts  
The PSoC CY8C23X33 is available in 32-pin QFN and 28-pin SSOP packages. Every port pin (labeled with a “P”), except for Vss and  
Vdd in the following table and figure, is capable of Digital IO.  
32-Pin Part Pinout  
Table 3. Pin Definitions - 32-Pin (QFN)  
Type  
Figure 5. CY8C23533 32-Pin PSoC Device  
Pin  
No.  
Pin  
Name  
Description  
Digital Analog  
1
2
IO  
IO  
P2[7] GPIO  
P2[5] GPIO  
3
IO  
IO  
IO  
I
I
P2[3] Direct Switched Capacitor Block Input  
GPIO, P2[7]  
GPIO, P2[5]  
A, I, P2[3]  
A, I, P2[1]  
AVref, P3[0]  
NC  
1
2
3
4
5
6
7
8
P0[2], A, I  
P0[0], A, I  
24  
23  
22  
21  
20  
19  
18  
4
P2[1] Direct Switched Capacitor Block Input  
P2[6], Vref  
P2[4], AGnd  
P2[2], A, I  
P2[0], A, I  
XRES  
QFN  
(Top View)  
5
AVref P3[0] GPIO/ADC Vref (optional)  
NC No Connection  
6
I2C SCL, P1[7]  
I2C SDA, P1[5]  
7
IO  
IO  
P1[7] I2C Serial Clock (SCL)  
P1[5] I2C Serial Data (SDA)  
NC No Connection  
17 P1[6], GPIO  
8
9
10  
11  
IO  
IO  
P1[3] GPIO  
P1[1] GPIO, Crystal Input (XTALin), I2C Serial Clock  
(SCL), ISSP-SCLK*  
12  
13  
Power  
Vss Ground Connection  
IO  
P1[0] GPIO, Crystal Output (XTALout), I2C Serial Data  
(SDA), ISSP-SDATA*  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
IO  
IO  
P1[2] GPIO  
P1[4] GPIO, External Clock IP  
NC No Connection  
IO  
P1[6] GPIO  
Input  
XRES Active High External Reset with Internal Pull Down  
P2[0] Direct Switched Capacitor Block Input  
P2[2] Direct Switched Capacitor Block Input  
P2[4] External Analog Ground (AGnd)  
P2[6] External Voltage Reference (VRef)  
P0[0] Analog Column Mux Input and ADC Input  
P0[2] Analog Column Mux Input and ADC Input  
NC No Connection  
IO  
IO  
IO  
IO  
IO  
IO  
I
I
I
I
IO  
IO  
I
I
P0[4] Analog Column Mux Input and ADC Input  
P0[6] Analog Column Mux Input and ADC Input  
Vdd Supply Voltage  
Power  
IO  
IO  
I
P0[7] Analog Column Mux Input and ADC Input  
IO  
P0[5] Analog Column Mux Input, Column Output and  
ADC Input  
31  
32  
IO  
IO  
IO  
I
P0[3] Analog Column Mux Input, Column Output and  
ADC Input  
P0[1] Analog Column Mux Input.and ADC Input  
LEGEND: A = Analog, I = Input, and O = Output.  
Note  
4. Even though P3[0] is an odd port, it resides on the left side of the pinout.  
Document Number: 001-44369 Rev. *B  
Page 8 of 37  
 
CY8C23433, CY8C23533  
28-Pin Part Pinout  
Table 4. Pin Definitions - 28-Pin (SSOP)  
Figure 6. CY8C23433 28-Pin PSoC Device  
Description  
AIO, P0[7]  
IO, P0[5]  
IO, P0[3]  
AIO, P0[1]  
1
2
3
4
28  
27  
26  
25  
Vdd  
P0[6], AIO, AnColMux and ADC IP  
P0[4], AIO, AnColMux and ADC IP  
P0[2], AIO, AnColMux and ADC IP  
P0[0], AIO, AnColMux and ADC IP  
P2[6], VREF  
1
2
IO  
I
P0[7]  
P0[5]  
Analog Column Mux IP and ADC IP  
5
6
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
IO, P2[7]  
IO, P2[5]  
IO IO  
Analog Column Mux IP and Column  
O/P and ADC IP  
AIO, P2[3]  
7
P2[4], AGND  
P2[2], AIO  
P2[0], AIO  
SSOP  
AIO, P2[1]  
8
AVref, IO, P3[0]  
I2C SCL, IO, P1[7]  
9
3
IO IO  
P0[3]  
Analog Column Mux IP and Column  
O/P and ADC IP  
10  
P3[1], IO  
I2C SDA, IO, P1[5]  
11  
12  
13  
14  
P1[6], IO  
IO, P1[3]  
I2C SCL,ISSP SCL,XTALin,IO, P1[1]  
Vss  
P1[4], IO, EXTCLK  
P1[2], IO  
4
5
6
7
8
9
IO  
IO  
IO  
IO  
IO  
I
P0[1]  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
Analog Column Mux IP and ADC IP  
GPIO  
P1[0],IO,XTALout,ISSP SDA,I2C SDA  
GPIO  
I
I
Direct Switched Capacitor Input  
Direct Switched Capacitor Input  
GPIO/ADC Vref (optional)  
IO AVref  
P3[0]  
P1[7]  
P1[5]  
P1[3]  
10 IO  
11 IO  
12 IO  
13 IO  
I2C SCL  
I2C SDA  
GPIO  
GPIO, Xtal Input, I2C SCL, ISSP SCL  
P1[1]  
Vss  
14 Power  
15 IO  
Ground Pin  
GPIO, Xtal Output, I2C SDA, ISSP  
SDA  
P1[0]  
16 IO  
17 IO  
18 IO  
19 IO  
P1[2]  
P1[4]  
P1[6]  
GPIO  
GPIO, External Clock IP  
GPIO  
GPIO  
P3[1]  
P2[0]  
P2[2]  
P2[4]  
P2[6]  
P0[0]  
P0[2]  
P0[4]  
P0[6]  
Vdd  
20 IO  
21 IO  
22 IO  
23 IO  
24 IO  
25 IO  
26 IO  
27 IO  
I
I
Direct Switched Capacitor Input  
Direct Switched Capacitor Input  
External Analog Ground (AGnd)  
Analog Voltage Reference (VRef)  
Analog Column Mux IP and ADC IP  
Analog Column Mux IP and ADC IP  
Analog Column Mux IP and ADC IP  
Analog Column Mux IP and ADC IP  
Supply Voltage  
I
I
I
I
28 Power  
LEGEND: A = Analog, I = Input, and O = Output.  
Notes  
5. Even though P3[0] is an odd port, it resides on the left side of the pinout.  
6. ISSP pin, which is not High Z at POR.  
7. Even though P3[1] is an even port, it resides on the right side of the pinout.  
Document Number: 001-44369 Rev. *B  
Page 9 of 37  
     
CY8C23433, CY8C23533  
Register Mapping Tables  
Register Reference  
The PSoC device has a total register address space of 512  
bytes. The register space is referred to as IO space and is  
divided into two banks. The XOI bit in the Flag register (CPU_F)  
determines which bank the user is currently in. When the XOI bit  
is set the user is in Bank 1.  
This section lists the registers of the CY8C23433 PSoC device  
by using mapping tables, in offset order.  
Register Conventions  
Abbreviations Used  
Note In the following register mapping tables, blank fields are  
reserved and must not be accessed.  
The register conventions specific to this section are listed in the  
following table.  
Table 5. Abbreviations  
Convention  
Description  
Read register or bits  
R
W
L
Write register or bits  
Logical register or bits  
Clearable register or bits  
Access is bit specific  
C
#
Document Number: 001-44369 Rev. *B  
Page 10 of 37  
CY8C23433, CY8C23533  
Table 6. Register Map Bank 0 Table: User Space  
PRT0DR  
PRT0IE  
PRT0GS  
PRT0DM2  
PRT1DR  
PRT1IE  
PRT1GS  
PRT1DM2  
PRT2DR  
PRT2IE  
PRT2GS  
PRT2DM2  
PRT3DR  
PRT3IE  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
C0  
C1  
C2  
C3  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
RW  
RW  
RW  
RW  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
PRT3GS  
PRT3DM2  
ASC21CR0  
ASC21CR1  
ASC21CR2  
ASC21CR3  
RW  
RW  
RW  
RW  
I2C_CFG  
I2C_SCR  
I2C_DR  
I2C_MSCR  
INT_CLR0  
INT_CLR1  
RW  
#
RW  
#
RW  
RW  
INT_CLR3  
INT_MSK3  
RW  
RW  
DBB00DR0  
DBB00DR1  
DBB00DR2  
DBB00CR0  
DBB01DR0  
DBB01DR1  
DBB01DR2  
DBB01CR0  
DCB02DR0  
DCB02DR1  
DCB02DR2  
DCB02CR0  
DCB03DR0  
DCB03DR1  
DCB03DR2  
DCB03CR0  
#
W
RW  
#
AMX_IN  
RW  
INT_MSK0  
INT_MSK1  
INT_VC  
RES_WDT  
DEC_DH  
RW  
RW  
RC  
W
RC  
RC  
RW  
RW  
W
W
R
R
RW  
RW  
RW  
RW  
ARF_CR  
CMP_CR0  
ASY_CR  
CMP_CR1  
SARADC_DL  
RW  
#
#
RW  
RW  
#
W
RW  
#
DEC_DL  
DEC_CR0  
DEC_CR1  
MUL0_X  
#
W
RW  
#
SARADC_CR0  
SARADC_CR1  
#
RW  
MUL0_Y  
MUL0_DH  
MUL0_DL  
ACC0_DR1  
ACC0_DR0  
ACC0_DR3  
ACC0_DR2  
#
TMP_DR0  
TMP_DR1  
TMP_DR2  
TMP_DR3  
ACB00CR3  
ACB00CR0  
ACB00CR1  
ACB00CR2  
ACB01CR3  
ACB01CR0  
ACB01CR1 *  
ACB01CR2 *  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
W
RW  
#
RDI0RI  
RDI0SYN  
RDI0IS  
RDI0LT0  
RDI0LT1  
RDI0RO0  
RDI0RO1  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
CPU_F  
RL  
F9  
FA  
FB  
FC  
FD  
Gray fields are reserved.  
# Access is bit specific.  
Document Number: 001-44369 Rev. *B  
Page 11 of 37  
CY8C23433, CY8C23533  
Table 6. Register Map Bank 0 Table: User Space (continued)  
3E  
3F  
7E  
7F  
BE  
BF  
CPU_SCR1  
CPU_SCR0  
FE  
FF  
#
#
Gray fields are reserved.  
# Access is bit specific.  
Table 7. Register Map Bank 1 Table: Configuration Space  
PRT0DM0  
PRT0DM1  
PRT0IC0  
PRT0IC1  
PRT1DM0  
PRT1DM1  
PRT1IC0  
PRT1IC1  
PRT2DM0  
PRT2DM1  
PRT2IC0  
PRT2IC1  
PRT3DM0  
PRT3DM1  
PRT3IC0  
PRT3IC1  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
80  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
ASD11CR0  
ASD11CR1  
ASD11CR2  
ASD11CR3  
RW  
RW  
RW  
RW  
GDI_O_IN  
GDI_E_IN  
GDI_O_OU  
GDI_E_OU  
RW  
RW  
RW  
RW  
ASC21CR0  
ASC21CR1  
ASC21CR2  
ASC21CR3  
RW  
RW  
RW  
RW  
OSC_GO_EN  
OSC_CR4  
OSC_CR3  
OSC_CR0  
OSC_CR1  
OSC_CR2  
VLT_CR  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
R
DBB00FN  
DBB00IN  
DBB00OU  
RW  
RW  
RW  
CLK_CR0  
CLK_CR1  
ABF_CR0  
AMD_CR0  
RW  
RW  
RW  
RW  
DBB01FN  
DBB01IN  
DBB01OU  
RW  
RW  
RW  
VLT_CMP  
AMD_CR1  
ALT_CR0  
RW  
RW  
DCB02FN  
DCB02IN  
DCB02OU  
RW  
RW  
RW  
SARADC_TRS  
SARADC_TRCL  
SARADC_TRCH  
SARADC_CR2  
SARADC_LCR  
RW  
RW  
RW  
#
IMO_TR  
ILO_TR  
BDG_TR  
ECO_TR  
W
W
RW  
W
DCB03FN  
DCB03IN  
DCB03OU  
RW  
RW  
RW  
TMP_DR0  
TMP_DR1  
TMP_DR2  
TMP_DR3  
ACB00CR3  
ACB00CR0  
ACB00CR1  
ACB00CR2  
ACB01CR3  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RDI0RI  
RDI0SYN  
RDI0IS  
RDI0LT0  
RDI0LT1  
RW  
RW  
RW  
RW  
RW  
F1  
F2  
F3  
F4  
Gray fields are reserved.  
# Access is bit specific.  
Document Number: 001-44369 Rev. *B  
Page 12 of 37  
CY8C23433, CY8C23533  
Table 7. Register Map Bank 1 Table: Configuration Space (continued)  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
ACB01CR0  
ACB01CR1  
ACB01CR2 *  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
RW  
RW  
RW  
RDI0RO0  
RDI0RO1  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
RW  
RW  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
CPU_F  
RL  
FLS_PR1  
RW  
CPU_SCR1  
CPU_SCR0  
#
#
Gray fields are reserved.  
# Access is bit specific.  
Document Number: 001-44369 Rev. *B  
Page 13 of 37  
CY8C23433, CY8C23533  
Electrical Specifications  
This section presents the DC and AC electrical specifications of the CY8C23433 PSoC device. For the latest electrical specifications,  
visit http://www.cypress.com/psoc. Specifications are valid for -40°C T 85°C and T 100°C, except where noted. Refer to  
A
J
Table 24 on page 25 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.  
Figure 7. Voltage versus CPU Frequency  
Figure 8. IMO Frequency Trim Options  
5.25  
4.75  
5.25  
4.75  
SLIMO  
Mode=1  
SLIMO  
Mode=0  
3.60  
3.00  
SLIMO  
Mode=0  
SLIMO  
Mode=1  
3.00  
93 kHz 3 MHz  
CPU Frequency  
12 MHz  
24 MHz  
93 kHz  
6 MHz  
12 MHz  
24 MHz  
IMO Frequency  
The following table lists the units of measure that are used in this section.  
Table 8. Units of Measure  
Symbol  
°C  
Unit of Measure  
degree Celsius  
Symbol  
μW  
mA  
ms  
mV  
nA  
Unit of Measure  
micro watts  
dB  
decibels  
milli-ampere  
milli-second  
milli-volts  
fF  
femto farad  
hertz  
Hz  
KB  
1024 bytes  
1024 bits  
nano ampere  
nanosecond  
nanovolts  
Kbit  
kHz  
kΩ  
ns  
kilohertz  
nV  
kilohm  
W
ohm  
MHz  
MΩ  
μA  
megahertz  
megaohm  
pA  
pico ampere  
pico farad  
peak-to-peak  
pF  
micro ampere  
micro farad  
micro henry  
microsecond  
micro volts  
micro volts root-mean-square  
pp  
μF  
ppm  
ps  
parts per million  
picosecond  
μH  
μs  
sps  
s
samples per second  
sigma: one standard deviation  
volts  
μV  
μVrms  
V
Document Number: 001-44369 Rev. *B  
Page 14 of 37  
     
CY8C23433, CY8C23533  
Absolute Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.  
Table 9. Absolute Maximum Ratings  
Symbol  
Description  
Storage Temperature  
Min  
Typ  
Max  
Units  
Notes  
T
-55  
25  
+100  
°C Higher storage temperatures  
reduce data retention time.  
Recommended storage  
STG  
temperature is +25°C ± 25°C.  
Extended duration storage  
temperatures above 65°C  
degrade reliability.  
T
Ambient Temperature with Power Applied  
Supply Voltage on Vdd Relative to Vss  
DC Input Voltage  
-40  
-0.5  
+85  
+6.0  
°C  
V
A
Vdd  
V
V
Vss - 0.5  
Vss - 0.5  
-25  
Vdd + 0.5  
Vdd + 0.5  
+50  
V
IO  
IOZ  
MIO  
DC Voltage Applied to Tri-state  
Maximum Current into any Port Pin  
Electro Static Discharge Voltage  
Latch-up Current  
V
I
mA  
ESD  
LU  
2000  
V
Human Body Model ESD.  
200  
mA  
Operating Temperature  
Table 10. Operating Temperature  
Symbol  
Description  
Min  
-40  
-40  
Typ  
Max  
+85  
Units  
Notes  
T
Ambient Temperature  
Junction Temperature  
°C  
A
T
+100  
°C The temperature rise from  
ambient to junction is package  
specific. See Thermal Imped-  
The user must limit the power  
consumption to comply with this  
requirement.  
J
Document Number: 001-44369 Rev. *B  
Page 15 of 37  
CY8C23433, CY8C23533  
DC Electrical Characteristics  
DC Chip-Level Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 11. DC Chip-Level Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
Vdd  
Supply Voltage  
Supply Current  
3.0  
5.25  
V
I
I
I
5
3.3  
3
8
mA Conditions are Vdd = 5.0V,  
DD  
T =25°C, CPU=3MHz, SYSCLK  
A
doubler disabled,  
VC1 = 1.5 MHz, VC2 = 93.75 kHz,  
VC3 = 93.75 kHz,  
analog power = off.  
SLIMO mode = 0. IMO = 24 MHz.  
Supply Current  
6.0  
6.5  
mA Conditions are Vdd = 3.3V,  
DD3  
T =25°C, CPU=3MHz, SYSCLK  
A
doubler disabled,  
VC1 = 1.5 MHz, VC2 = 93.75 kHz,  
VC3 = 93.75 kHz, analog power =  
off. SLIMO mode = 0.  
IMO = 24 MHz.  
Sleep (Mode) Current with POR, LVD, Sleep  
Timer, and WDT.  
μA Conditions are with internal slow  
SB  
speed oscillator, Vdd = 3.3V,  
-40°C T 55°C,  
A
analog power = off.  
I
I
Sleep (Mode) Current with POR, LVD, Sleep  
Timer, and WDT at high temperature.  
4
4
25  
μA Conditions are with internal slow  
SBH  
speed oscillator, Vdd = 3.3V, 55°C  
< T 85°C, analog power = off.  
A
Sleep (Mode) Current with POR, LVD, Sleep  
7.5  
μA Conditions are with properly  
SBXTL  
[8]  
Timer, WDT, and external crystal.  
loaded, 1 μW max, 32.768 kHz  
crystal. Vdd = 3.3V, -40°C T ≤  
A
55°C, analog power = off.  
I
Sleep (Mode) Current with POR, LVD, Sleep  
Timer, WDT, and external crystal at high  
temperature.  
5
26  
μA Conditions are with properly  
SBXTLH  
loaded, 1μW max, 32.768 kHz  
[8]  
crystal. Vdd = 3.3 V, 55°C < T ≤  
85°C, analog power = off.  
A
V
Reference Voltage (Bandgap)  
1.28  
1.30  
1.33  
V
Trimmed for appropriate Vdd.  
Vdd > 3.0V  
REF  
Note  
8. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar  
functions enabled.  
Document Number: 001-44369 Rev. *B  
Page 16 of 37  
 
CY8C23433, CY8C23533  
DC General Purpose IO Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 12. 5V and 3.3V DC GPIO Specifications  
Symbol  
Description  
Min  
Typ  
5.6  
5.6  
Max  
Units  
kΩ  
Notes  
R
Pull up Resistor  
4
4
8
8
PU  
PD  
OH  
R
Pull down Resistor  
High Output Level  
kΩ  
V
Vdd - 1.0  
V
IOH = 10 mA, Vdd = 4.75 to  
5.25V(maximum40mAoneven  
port pins (for example, P0[2],  
P1[4]), maximum 40 mA on odd  
port pins (for example, P0[3],  
P1[5])). 80 mA maximum  
combined IOH budget.  
V
Low Output Level  
0.75  
0.8  
V
IOL = 25 mA, Vdd = 4.75 to  
5.25V (maximum 100 mA on  
even port pins (for example,  
P0[2], P1[4]), maximum 100 mA  
on odd port pins (for example,  
P0[3],P1[5])).100mAmaximum  
combined IOH budget.  
OL  
V
V
V
I
Input Low Level  
2.1  
V
V
Vdd = 3.0 to 5.25  
Vdd = 3.0 to 5.25  
IL  
IH  
H
Input High Level  
Input Hysterisis  
60  
1
mV  
Input Leakage (Absolute Value)  
Capacitive Load on Pins as Input  
nA Gross tested to 1 μA  
IL  
C
3.5  
10  
pF Package and pin dependent.  
Temp = 25°C  
IN  
C
Capacitive Load on Pins as Output  
3.5  
10  
pF Package and pin dependent.  
Temp = 25°C  
OUT  
Document Number: 001-44369 Rev. *B  
Page 17 of 37  
CY8C23433, CY8C23533  
DC Operational Amplifier Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC  
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at  
25°C and are for design guidance only.  
Table 13. 5V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
OSOA  
1.6  
1.3  
1.2  
10  
8
7.5  
mV  
mV  
mV  
TCV  
Average Input Offset Voltage Drift  
7.0  
20  
35.0  
μV/°C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA Gross tested to 1 μA  
EBOA  
C
4.5  
9.5  
pF Package and pin dependent.  
Temp = 25°C  
INOA  
V
Common Mode Voltage Range  
Common Mode Voltage Range (high power or high  
opamp bias)  
0.0  
0.5  
Vdd  
Vdd - 0.5  
V
The common-mode input  
voltage range is measured  
through an analog output  
buffer. The specification  
includes the limitations  
imposed by the character-  
istics of the analog output  
buffer.  
CMOA  
G
Open Loop Gain  
dB Specification is applicable at  
high power. For all other bias  
modes (except high power,  
highopampbias), minimumis  
60 dB.  
OLOA  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
60  
60  
80  
V
V
High Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
OHIGHOA  
OLOWOA  
SOA  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.5  
V
V
V
Low Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
0.2  
0.2  
0.5  
V
V
V
I
Supply Current (including associated AGND buffer)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = Low  
300  
600  
1200  
2400  
4600  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
Power = High, Opamp Bias = High  
PSRR  
Supply Voltage Rejection Ratio  
52  
80  
dB Vss VIN (Vdd - 2.25) or  
OA  
(Vdd - 1.25V) VIN Vdd  
Document Number: 001-44369 Rev. *B  
Page 18 of 37  
CY8C23433, CY8C23533  
Table 14. 3.3V DC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Input Offset Voltage (absolute value)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = High  
High Power is 5 Volts Only  
OSOA  
1.65  
1.32  
10  
8
mV  
mV  
TCV  
Average Input Offset Voltage Drift  
7.0  
20  
35.0  
μV/°C  
OSOA  
I
Input Leakage Current (Port 0 Analog Pins)  
Input Capacitance (Port 0 Analog Pins)  
pA Gross tested to 1 μA.  
EBOA  
C
4.5  
9.5  
pF Package and pin dependent.  
Temp = 25°C  
INOA  
V
Common Mode Voltage Range  
0.2  
Vdd - 0.2  
V
The common-mode input  
voltage range is measured  
through an analog output  
buffer. The specification  
includes the limitations  
imposed by the character-  
istics of the analog output  
buffer.  
CMOA  
G
Open Loop Gain  
dB Specification is applicable at  
high power. For all other bias  
modes (except high power,  
high opamp bias), minimum is  
60 dB.  
OLOA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High, Opamp Bias = Low  
60  
60  
80  
V
V
High Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High is 5V only  
OHIGHOA  
OLOWOA  
SOA  
Vdd - 0.2  
Vdd - 0.2  
Vdd - 0.2  
V
V
V
Low Output Voltage Swing (internal signals)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = Low  
Power = High, Opamp Bias = Low  
0.2  
0.2  
0.2  
V
V
V
I
Supply Current (including associated AGND buffer)  
Power = Low, Opamp Bias = High  
Power = Medium, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = Low  
300  
600  
1200  
2400  
4600  
400  
800  
1600  
3200  
6400  
μA  
μA  
μA  
μA  
μA  
Power = High, Opamp Bias = High  
PSRR  
Supply Voltage Rejection Ratio  
52  
80  
dB Vss VIN (Vdd - 2.25) or  
OA  
(Vdd - 1.25V) VIN Vdd  
DC Low Power Comparator Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 15. DC Low Power Comparator Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
V
Low power comparator (LPC) reference voltage  
range  
0.2  
Vdd - 1  
V
REFLPC  
I
LPC supply current  
LPC voltage offset  
10  
40  
30  
μA  
SLPC  
V
2.5  
mV  
OSLPC  
Document Number: 001-44369 Rev. *B  
Page 19 of 37  
CY8C23433, CY8C23533  
DC Analog Output Buffer Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 16. 5V DC Analog Output Buffer Specifications  
Symbol  
Description  
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
Min  
Typ  
3
Max  
12  
Units  
mV  
Notes  
V
OSOB  
TCV  
+6  
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vdd - 1.0  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
V
High Output Voltage Swing (Load = 32 ohms to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vdd+ 1.1  
0.5 x Vdd+ 1.1  
V
V
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.3  
0.5 x Vdd - 1.3  
V
V
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
Power = High  
1.1  
2.6  
5.1  
8.8  
mA  
mA  
PSRR  
Supply Voltage Rejection Ratio  
52  
64  
dB  
V
>(Vdd - 1.25)  
OB  
OUT  
Table 17. 3.3V DC Analog Output Buffer Specifications  
Symbol  
Description  
Input Offset Voltage (Absolute Value)  
Average Input Offset Voltage Drift  
Common-Mode Input Voltage Range  
Min  
Typ  
3
Max  
12  
Units  
mV  
Notes  
V
OSOB  
TCV  
+6  
-
μV/°C  
V
OSOB  
CMOB  
V
0.5  
Vdd - 1.0  
R
Output Resistance  
Power = Low  
Power = High  
OUTOB  
1
1
W
W
V
High Output Voltage Swing (Load = 1k ohms to Vdd/2)  
Power = Low  
Power = High  
OHIGHOB  
OLOWOB  
SOB  
0.5 x Vdd + 1.0  
0.5 x Vdd + 1.0  
V
V
V
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)  
Power = Low  
Power = High  
0.5 x Vdd - 1.0  
0.5 x Vdd - 1.0  
V
V
I
Supply Current Including Bias Cell (No Load)  
Power = Low  
Power = High  
0.8  
2.0  
2.0  
4.3  
mA  
mA  
PSRR  
Supply Voltage Rejection Ratio  
52  
64  
dB  
V
> (Vdd - 1.25)  
OB  
OUT  
Document Number: 001-44369 Rev. *B  
Page 20 of 37  
CY8C23433, CY8C23533  
DC Analog Reference Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to  
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control  
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.  
Reference control power is high.  
Table 18. 5V DC Analog Reference Specifications  
Symbol  
Description  
Bandgap Voltage Reference  
AGND = Vdd/2  
Min  
1.28  
Typ  
1.30  
Max  
1.33  
Units  
BG  
V
V
V
V
V
V
V
Vdd/2 - 0.04  
2 x BG - 0.048  
P2[4] - 0.011  
BG - 0.009  
1.6 x BG - 0.022  
-0.034  
Vdd/2 - 0.01  
2 x BG - 0.030  
P2[4]  
Vdd/2 + 0.007  
2 x BG + 0.024  
P2[4] + 0.011  
BG + 0.016  
1.6 x BG + 0.018  
0.034  
AGND = 2 x BandGap  
AGND = P2[4] (P2[4] = Vdd/2)  
AGND = BandGap  
BG + 0.008  
1.6 x BG - 0.010  
0.000  
AGND = 1.6 x BandGap  
AGND Block to Block Variation  
(AGND = Vdd/2)  
RefHi = Vdd/2 + BandGap  
RefHi = 3 x BandGap  
Vdd/2 + BG - 0.10  
3 x BG - 0.06  
Vdd/2 + BG  
3 x BG  
Vdd/2 + BG + 0.10  
3 x BG + 0.06  
V
V
V
RefHi = 2 x BandGap + P2[6]  
(P2[6] = 1.3V)  
2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130  
P2[4] + BG - 0.016  
P2[4] + BG + 0.098  
V
V
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,  
P2[6] = 1.3V)  
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100  
RefHi = 3.2 x BandGap  
RefLo = Vdd/2 – BandGap  
RefLo = BandGap  
3.2 x BG - 0.112  
Vdd/2 - BG - 0.04  
BG - 0.06  
3.2 x BG  
Vdd/2 - BG + 0.024  
BG  
3.2 x BG + 0.076  
Vdd/2 - BG + 0.04  
BG + 0.06  
V
V
V
V
RefLo = 2 x BandGap - P2[6]  
(P2[6] = 1.3V)  
2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134  
P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107  
P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110  
RefLo = P2[4] – BandGap  
(P2[4] = Vdd/2)  
V
V
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,  
P2[6] = 1.3V)  
Table 19. 3.3V DC Analog Reference Specifications  
Symbol  
Description  
Bandgap Voltage Reference  
AGND = Vdd/2  
Min  
1.28  
Typ  
1.30  
Max  
1.33  
Units  
BG  
V
V
Vdd/2 - 0.03  
Vdd/2 - 0.01  
Vdd/2 + 0.005  
AGND = 2 x BandGap  
AGND = P2[4] (P2[4] = Vdd/2)  
AGND = BandGap  
Not Allowed  
P2[4] - 0.008  
BG - 0.009  
P2[4] + 0.001  
BG + 0.005  
1.6 x BG - 0.010  
0.000  
P2[4] + 0.009  
BG + 0.015  
1.6 x BG + 0.018  
0.034  
V
V
AGND = 1.6 x BandGap  
1.6 x BG - 0.027  
-0.034  
V
AGND Column to Column Variation  
(AGND = Vdd/2)  
mV  
RefHi = Vdd/2 + BandGap  
RefHi = 3 x BandGap  
Not Allowed  
Not Allowed  
Document Number: 001-44369 Rev. *B  
Page 21 of 37  
CY8C23433, CY8C23533  
Table 19. 3.3V DC Analog Reference Specifications (continued)  
Symbol  
Description  
Min  
Typ  
Max  
Units  
RefHi = 2 x BandGap + P2[6]  
(P2[6] = 0.5V)  
Not Allowed  
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)  
Not Allowed  
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,  
P2[6] = 0.5V)  
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057  
V
RefHi = 3.2 x BandGap  
RefLo = Vdd/2 - BandGap  
RefLo = BandGap  
Not Allowed  
Not Allowed  
Not Allowed  
Not Allowed  
RefLo = 2 x BandGap - P2[6] (P2[6] =  
0.5V)  
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)  
Not Allowed  
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] P2[4] - P2[6] - 0.048  
= 0.5V)  
P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092  
V
DC Analog PSoC Block Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 20. DC Analog PSoC Block Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
kΩ  
R
Resistor Unit Value (Continuous Time)  
Capacitor Unit Value (Switch Cap)  
12.2  
CT  
SC  
C
fF  
80  
DC POR and LVD Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical  
Reference Manual for more information on the VLT_CR register.  
Table 21. DC POR and LVD Specifications  
Symbol  
Description  
Vdd Value for PPOR Trip  
PORLEV[1:0] = 01b  
PORLEV[1:0] = 10b  
Min  
Typ  
Max  
Units  
Notes  
Vdd must be greater than or equal  
to 2.5V during startup or reset from  
Watchdog.  
V
2.82  
4.55  
2.95  
4.70  
V
V
PPOR1  
PPOR2  
V
Vdd Value for LVD Trip  
VM[2:0] = 001b  
VM[2:0] = 010b  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
VM[2:0] = 110b  
VM[2:0] = 111b  
0
0
0
V
V
V
V
V
V
V
2.85  
2.95  
3.06  
4.37  
4.50  
4.62  
4.71  
2.92  
3.02  
3.13  
4.48  
4.64  
4.73  
4.81  
2.99  
V
LVD1  
LVD2  
LVD3  
LVD4  
LVD5  
LVD6  
LVD7  
0
3.09  
3.20  
4.55  
4.75  
4.83  
4.95  
V
0
V
0
V
0
V
V
V
Notes  
9.  
C
is a design guarantee parameter, not tested value  
SC  
10. Always greater than 50 mV above V  
(PORLEV=01) for falling supply.  
PPOR  
Document Number: 001-44369 Rev. *B  
Page 22 of 37  
     
CY8C23433, CY8C23533  
DC Programming Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 22. DC Programming Specifications  
Symbol  
Vdd  
Description  
Min  
2.7  
Typ  
Max  
Units  
V
Notes  
Supply Voltage for Flash Write Operations  
Supply Current During Programming or Verify  
IWRITE  
DDP  
I
5
25  
mA  
V
V
Input Low Voltage During Programming or  
Verify  
0.8  
ILP  
V
Input High Voltage During Programming or  
Verify  
2.1  
0.2  
V
IHP  
I
I
Input Current when Applying Vilp to P1[0] or  
P1[1] During Programming or Verify  
mA Driving internal pull down  
resistor  
ILP  
Input Current when Applying Vihp to P1[0] or  
P1[1] During Programming or Verify  
1.5  
mA Driving internal pull down  
resistor  
IHP  
V
V
Output Low Voltage During Programming or  
Verify  
Vss + 0.75  
Vdd  
V
OLV  
Output High Voltage During Programming or  
Verify  
Vdd - 1.0  
V
OHV  
Flash  
Flash  
Flash Endurance (per block)  
50,000  
Erase/write cycles per block  
Erase/write cycles  
ENPB  
1,800,000  
Flash Endurance (total)  
ENT  
Flash  
Flash Data Retention  
10  
Years  
DR  
Note  
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks  
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees  
more than 50,000 cycles).  
Refer to 0xthe Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.  
Document Number: 001-44369 Rev. *B  
Page 23 of 37  
 
CY8C23433, CY8C23533  
SAR8 ADC DC Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 23. SAR8 ADC DC Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
V
Reference voltageatpin P3[0] when configured  
as ADC reference voltage  
3.0  
5.25  
V
The voltage level at P3[0]  
(when configured as ADC  
reference voltage) must  
always be maintained to be  
less than chip supply voltage  
level on Vdd pin.  
ADCVREF  
V
< Vdd.  
ADCVREF  
I
Current when P3[0] is configured as ADC V  
Integral Non-linearity  
3
mA  
ADCVREF  
REF  
INL  
-1.5  
+1.5  
+1.2  
LSB  
INL  
(limited  
Integral Non-linearity accommodating a shift in  
the offset at 0x80  
LSB The maximum LSB is over a  
sub-range not exceeding  
1/16 of the full-scale range.  
0x7F and 0x80 points specs  
are excluded here  
-1.2  
range)  
DNL  
Differential Non-linearity  
-2.3  
-1  
+2.3  
+1  
LSB ADC conversion is  
monotonic over full range  
DNL  
(limited  
range)  
Differential Non-linearity excluding 0x7F-0x80  
transition  
LSB ADC conversion is  
monotonic over full range.  
0x7Fto0x80transitionspecs  
are excluded here.  
Notes  
12. SAR converters require a stable input voltage during the sampling period. If the voltage into the SAR8 changes by more than 1 LSB during the sampling period then  
the accuracy specifications may not be met  
Document Number: 001-44369 Rev. *B  
Page 24 of 37  
 
CY8C23433, CY8C23533  
AC Electrical Characteristics  
AC Chip-Level Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 24. 5V and 3.3V AC Chip-Level Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Notes  
F
Internal Main Oscillator Frequency for 24  
MHz  
23.4  
24  
MHz Trimmed for 5V or 3.3V  
operation using factory trim  
SLIMO mode = 0.  
IMO24  
24.6  
F
Internal Main Oscillator Frequency for 6 MHz  
5.75  
6
MHz Trimmed for 5V or 3.3V  
operation using factory trim  
SLIMO mode = 1.  
IMO6  
6.35  
F
F
F
CPU Frequency (5V Nominal)  
CPU Frequency (3.3V Nominal)  
Digital PSoC Block Frequency  
0.093  
0.093  
0
24  
12  
48  
MHz  
MHz  
CPU1  
CPU2  
48M  
24.6  
12.3  
MHz Refer to the AC Digital Block  
Specifications.  
49.2  
F
Digital PSoC Block Frequency  
0
24  
MHz  
kHz  
24M  
24.6  
F
F
Internal Low Speed Oscillator Frequency  
External Crystal Oscillator  
15  
32  
75  
32K1  
32.768  
kHz Accuracyiscapacitorandcrystal  
dependent. 50% duty cycle.  
32K2  
F
PLL Frequency  
23.986  
MHz Is a multiple (x732) of crystal  
frequency.  
PLL  
Jitter24M2  
24 MHz Period Jitter (PLL)  
0.5  
0.5  
600  
10  
ps  
ms  
ms  
ms  
T
T
T
T
PLL Lock Time  
PLLSLEW  
PLLSLEWSLOW  
OS  
PLL Lock Time for Low Gain Setting  
External Crystal Oscillator Startup to 1%  
External Crystal Oscillator Startup to 100 ppm  
50  
1700  
2800  
2620  
3800  
ms The crystal oscillator frequency  
iswithin100ppmofits finalvalue  
OSACC  
by the end of the T  
period.  
osacc  
Correct operation assumes a  
properly loaded 1 uW maximum  
drive level 32.768 kHz crystal.  
3.0V Vdd 5.5V, -40 °C T ≤  
A
85°C.  
Jitter32k  
32 kHz Period Jitter  
10  
40  
100  
ns  
μs  
T
External Reset Pulse Width  
24 MHz Duty Cycle  
60  
XRST  
DC24M  
50  
%
Step24M  
Fout48M  
24 MHz Trim Step Size  
48 MHz Output Frequency  
50  
kHz  
46.8  
48.0  
MHz Trimmed. Using factory trim  
values.  
49.2  
Jitter24M1R  
24 MHz Period Jitter (IMO) Root Mean  
Squared  
0
600  
12.3  
ps  
MHz  
μs  
F
Maximum frequency of signal on row input or  
row output.  
MAX  
T
Supply Ramp Time  
RAMP  
Notes  
13. 4.75V < Vdd < 5.25V.  
14. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.  
15. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation  
at 3.3V.  
16. See the individual user module data sheets for information on maximum frequencies for user modules.  
Document Number: 001-44369 Rev. *B  
Page 25 of 37  
         
CY8C23433, CY8C23533  
Figure 9. PLL Lock Timing Diagram  
PLL  
Enable  
T
24 MHz  
PLLSLEW  
FPLL  
PLL  
Gain  
0
Figure 10. PLL Lock for Low Gain Setting Timing Diagram  
PLL  
Enable  
T
24 MHz  
PLLSLEWLOW  
FPLL  
PLL  
Gain  
1
Figure 11. External Crystal Oscillator Startup Timing Diagram  
32K  
Select  
32 kHz  
T
OS  
F32K2  
Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram  
Jitter24M1  
F24M  
Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram  
Jitter32k  
F32K2  
Document Number: 001-44369 Rev. *B  
Page 26 of 37  
CY8C23433, CY8C23533  
AC General Purpose IO Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 25. 5V and 3.3V AC GPIO Specifications  
Symbol  
Description  
Min  
0
Typ  
Max  
12.3  
18  
18  
Units  
Notes  
F
GPIO Operating Frequency  
MHz Normal Strong Mode  
GPIO  
TRiseF  
Rise Time, Normal Strong Mode, Cload = 50 pF  
Fall Time, Normal Strong Mode, Cload = 50 pF  
Rise Time, Slow Strong Mode, Cload = 50 pF  
Fall Time, Slow Strong Mode, Cload = 50 pF  
3
ns  
ns  
ns  
ns  
Vdd = 4.5 to 5.25V, 10% - 90%  
TFallF  
TRiseS  
TFallS  
2
Vdd = 4.5 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
Vdd = 3 to 5.25V, 10% - 90%  
10  
10  
27  
22  
Figure 14. GPIO Timing Diagram  
90%  
GPIO  
Pin  
Output  
Voltage  
10%  
TRiseF  
TRiseS  
TFallF  
TFallS  
AC Operational Amplifier Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.  
Power = High and Opamp Bias = High is not supported at 3.3V.  
Table 26. 5V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
ROA  
3.9  
0.72  
0.62  
μs  
μs  
μs  
Power = High, Opamp Bias = High  
T
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
SOA  
5.9  
0.92  
0.72  
μs  
μs  
μs  
Power = High, Opamp Bias = High  
SR  
SR  
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
ROA  
0.15  
1.7  
6.5  
V/μs  
V/μs  
V/μs  
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
FOA  
0.01  
0.5  
4.0  
V/μs  
V/μs  
V/μs  
BW  
Gain Bandwidth Product  
OA  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
Power = High, Opamp Bias = High  
0.75  
3.1  
5.4  
MHz  
MHz  
MHz  
Document Number: 001-44369 Rev. *B  
Page 27 of 37  
CY8C23433, CY8C23533  
Table 27. 3.3V AC Operational Amplifier Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
ROA  
3.92  
0.72  
μs  
μs  
T
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
SOA  
5.41  
0.72  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
ROA  
0.31  
2.7  
V/μs  
V/μs  
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
FOA  
0.24  
1.8  
V/μs  
V/μs  
BW  
Gain Bandwidth Product  
Power = Low, Opamp Bias = Low  
Power = Medium, Opamp Bias = High  
OA  
0.67  
2.8  
MHz  
MHz  
Document Number: 001-44369 Rev. *B  
Page 28 of 37  
CY8C23433, CY8C23533  
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up  
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.  
Figure 15. Typical AGND Noise with P2[4] Bypass  
dBV/rtHz  
10000  
0
0.01  
0.1  
1.0  
10  
1000  
100  
0.001  
0.01  
0.1 Freq (kHz)  
1
10  
100  
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high  
frequencies, increased power level reduces the noise spectrum level.  
Figure 16. Typical Opamp Noise  
nV/rtHz  
10000  
PH_BH  
PH_BL  
PM_BL  
PL_BL  
1000  
100  
10  
0.001  
0.01  
0.1  
1
10  
100  
Freq (kHz)  
Document Number: 001-44369 Rev. *B  
Page 29 of 37  
CY8C23433, CY8C23533  
AC Low Power Comparator Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 28. AC Low Power Comparator Specifications  
Symbol Description  
LPC response time  
Min  
Typ  
Max  
Units  
Notes  
T
50  
μs  
50 mV overdrive comparator  
RLPC  
reference set within V  
REFLPC  
AC Digital Block Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 29. 5V and 3.3V AC Digital Block Specifications  
Symbol Description  
Timer Capture Pulse Width  
Min  
Typ  
Max  
Units  
Notes  
ns  
50  
Maximum Frequency, No Capture  
Maximum Frequency, With Capture  
Enable Pulse Width  
49.2  
24.6  
MHz 4.75V < Vdd < 5.25V  
MHz  
ns  
Counter  
50  
Maximum Frequency, No Enable Input  
Maximum Frequency, Enable Input  
49.2  
24.6  
MHz 4.75V < Vdd < 5.25V  
MHz  
Dead Band Kill Pulse Width:  
Asynchronous Restart Mode  
20  
ns  
ns  
Synchronous Restart Mode  
Disable Mode  
50  
50  
ns  
Maximum Frequency  
49.2  
49.2  
MHz 4.75V < Vdd < 5.25V  
MHz 4.75V < Vdd < 5.25V  
CRCPRS  
(PRS  
Mode)  
Maximum Input Clock Frequency  
CRCPRS  
(CRC  
Mode)  
Maximum Input Clock Frequency  
24.6  
8.2  
MHz  
SPIM  
Maximum Input Clock Frequency  
Maximum Input Clock Frequency  
MHz Maximum data rate at 4.1 MHz due  
to 2 x over clocking.  
SPIS  
4.1  
MHz  
ns  
Width of SS_ Negated Between  
Transmissions  
50  
Transmitter Maximum Input Clock Frequency  
24.6  
49.2  
MHz Maximum data rate at 3.08 MHz due  
to 8 x over clocking.  
MHz Maximum data rate at 6.15 MHz due  
to 8 x over clocking.  
Maximum Input Clock Frequency with Vdd ≥  
4.75V, 2 Stop Bits  
Receiver  
Maximum Input Clock Frequency  
24.6  
49.2  
MHz Maximum data rate at 3.08 MHz due  
to 8 x over clocking.  
MHz Maximum data rate at 6.15 MHzdue  
to 8 x over clocking.  
Maximum Input Clock Frequency with Vdd ≥  
4.75V, 2 Stop Bits  
Note  
17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).  
Document Number: 001-44369 Rev. *B  
Page 30 of 37  
 
CY8C23433, CY8C23533  
AC Analog Output Buffer Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 30. 5V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
2.5  
2.5  
μs  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
SOB  
2.2  
2.2  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
0.65  
0.65  
V/μs  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
FOB  
0.65  
0.65  
V/μs  
V/μs  
BW  
BW  
Small Signal Bandwidth, 20mV , 3 dB BW, 100 pF Load  
Power = Low  
Power = High  
OB  
pp  
0.8  
0.8  
MHz  
MHz  
Large Signal Bandwidth, 1V , 3 dB BW, 100 pF Load  
OB  
pp  
Power = Low  
Power = High  
300  
300  
kHz  
kHz  
Table 31. 3.3V AC Analog Output Buffer Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
3.8  
3.8  
μs  
μs  
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load  
Power = Low  
Power = High  
SOB  
2.6  
2.6  
μs  
μs  
SR  
SR  
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
ROB  
FOB  
0.5  
0.5  
V/μs  
V/μs  
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load  
Power = Low  
Power = High  
0.5  
0.5  
V/μs  
V/μs  
BW  
BW  
Small Signal Bandwidth, 20mV , 3 dB BW, 100 pF Load  
Power = Low  
Power = High  
OB  
OB  
pp  
0.7  
0.7  
MHz  
MHz  
Large Signal Bandwidth, 1V , 3 dB BW, 100 pF Load  
pp  
Power = Low  
Power = High  
200  
200  
kHz  
kHz  
Document Number: 001-44369 Rev. *B  
Page 31 of 37  
CY8C23433, CY8C23533  
AC External Clock Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 32. 5V AC External Clock Specifications  
Symbol  
Description  
Min  
0.093  
20.6  
20.6  
150  
Typ  
Max  
24.6  
5300  
Units  
MHz  
ns  
F
Frequency  
OSCEXT  
High Period  
Low Period  
ns  
Power Up IMO to Switch  
μs  
Table 33. 3.3V AC External Clock Specifications  
Symbol  
OSCEXT  
OSCEXT  
Description  
Min  
Typ  
Max  
Units  
F
F
0.093  
12.3  
MHz  
Frequency with CPU Clock divide by 1  
0.186  
24.6  
MHz  
Frequency with CPU Clock divide by 2 or greater  
High Period with CPU Clock divide by 1  
Low Period with CPU Clock divide by 1  
Power Up IMO to Switch  
41.7  
41.7  
150  
5300  
ns  
ns  
μs  
AC Programming Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 34. AC Programming Specifications  
Symbol  
Description  
Min  
1
Typ  
Max Units  
Notes  
T
T
T
T
F
T
T
T
T
Rise Time of SCLK  
Fall Time of SCLK  
20  
20  
ns  
ns  
RSCLK  
FSCLK  
SSCLK  
HSCLK  
SCLK  
1
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
Flash Erase Time (Block)  
20  
20  
ERASEB  
WRITE  
DSCLK  
DSCLK3  
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK  
Data Out Delay from Falling Edge of SCLK  
45  
50  
ns Vdd > 3.6  
ns 3.0 Vdd 3.6  
SAR8 ADC AC Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V  
and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and  
A
A
are for design guidance only.  
Table 35. SAR8 ADC AC Specifications[20]  
Symbol  
Description  
Min  
Typ  
Max  
3.075  
3.075  
Units  
MHz  
MHz  
Freq  
Input clock frequency 3V  
Input clock frequency 5V  
3
5
Freq  
Notes  
18. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.  
19. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the  
fifty percent duty cycle requirement is met.  
20. The max sample rate in this R2R ADC is 3.0/8=375KSPS  
Document Number: 001-44369 Rev. *B  
Page 32 of 37  
     
CY8C23433, CY8C23533  
2
AC I C Specifications  
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to  
5.25V and -40°C T 85°C, or 3.0V to 3.6V and -40°C T 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C  
A
A
and are for design guidance only.  
2
Table 36. AC Characteristics of the I C SDA and SCL Pins for Vdd > 3.0V  
Standard Mode  
Fast Mode  
Symbol  
Description  
Units  
Min  
0
Max  
100  
Min  
Max  
400  
F
T
SCL Clock Frequency  
0
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this period, the  
first clock pulse is generated.  
4.0  
0.6  
μs  
HDSTAI2C  
T
T
T
T
T
LOW Period of the SCL Clock  
HIGH Period of the SCL Clock  
Setup Time for a Repeated START Condition  
Data Hold Time  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
μs  
μs  
μs  
μs  
ns  
LOWI2C  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
Data Setup Time  
250  
100  
T
T
T
Setup Time for STOP Condition  
4.0  
4.7  
0.6  
1.3  
0
μs  
μs  
ns  
SUSTOI2C  
BUFI2C  
SPI2C  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter.  
50  
2
Table 37. AC Characteristics of the I C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)  
Standard Mode  
Fast Mode  
Symbol  
Description  
Units  
Min  
0
Max  
100  
Min  
Max  
F
T
SCL Clock Frequency  
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this period, the  
first clock pulse is generated.  
4.0  
μs  
HDSTAI2C  
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock  
4.7  
4.0  
4.7  
0
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
LOWI2C  
HIGH Period of the SCL Clock  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
SUSTOI2C  
BUFI2C  
Setup Time for a Repeated START Condition  
Data Hold Time  
Data Setup Time  
250  
4.0  
4.7  
Setup Time for STOP Condition  
Bus Free Time Between a STOP and START Condition  
Pulse Width of spikes are suppressed by the input filter.  
SPI2C  
2
Figure 17. Definition for Timing for Fast/Standard Mode on the I C Bus  
SDA  
SCL  
TSPI2C  
T
LOWI2C  
TSUDATI2C  
THDSTAI2C  
TBUFI2C  
TSUSTOI2C  
TSUSTAI2C  
THDDATI2C  
THDSTAI2C  
THIGHI2C  
S
Sr  
P
S
Note  
21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t  
250 ns must then be met. This is automatically the case  
SU;DAT  
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the  
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.  
SU;DAT  
SDA line t  
+ t  
rmax  
Document Number: 001-44369 Rev. *B  
Page 33 of 37  
 
CY8C23433, CY8C23533  
Packaging Information  
This section illustrates the packaging specifications for the CY8C23x33 PSoC device, along with the thermal impedances for each  
package, solder reflow peak temperature, and the typical package capacitance on crystal pins.  
Figure 19. 32-Pin (5x5 mm) QFN  
SEE NOTE 1  
TOP VIEW  
BOTTOM VIEW  
SIDE VIEW  
NOTES:  
1.  
HATCH AREA IS SOLDERABLE EXPOSED PAD  
2. BASED ON REF JEDEC # MO-248  
3. PACKAGE WEIGHT: 0.0388g  
001-42168*C
4. DIMENSIONS ARE IN MILLIMETERS  
Document Number: 001-44369 Rev. *B  
Page 34 of 37  
CY8C23433, CY8C23533  
Figure 20. 28-Pin (210-Mil) SSOP  
51-85079 *C  
Thermal Impedances  
Capacitance on Crystal Pins  
Table 39. Typical Package Capacitance on Crystal Pins  
Package Package Capacitance  
2.0 pF  
2.8 pF  
Table 38. Thermal Impedances by Package  
JA  
Package  
Typical θ  
19.4°C/W  
95°C/W  
32 QFN  
32 QFN  
28 SSOP  
28 SSOP  
Solder Reflow Peak Temperature  
Following is the minimum solder reflow peak temperature to achieve good solderability.  
Table 40. Solder Reflow Peak Temperature  
Package  
Minimum Peak Temperature  
Maximum Peak Temperature  
32 QFN  
240°C  
240°C  
260°C  
260°C  
28 SSOP  
Notes  
22. T = T + POWER x θJA.  
J
A
o
o
23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.  
Refer to the solder manufacturer specifications.  
Document Number: 001-44369 Rev. *B  
Page 35 of 37  
     
CY8C23433, CY8C23533  
Ordering Information  
The following table lists the CY8C23X33 PSoC device family key package features and ordering codes.  
Table 41. CY8C23X33 PSoC Device Family Key Features and Ordering Information  
32 Pin QFN  
CY8C23533-24LQXI  
8
8
8
8
256 -40°C to +85°C  
256 -40°C to +85°C  
256 -40°C to +85°C  
256 -40°C to +85°C  
4
4
4
4
4
4
4
4
26  
26  
26  
26  
12  
12  
12  
12  
2
2
2
2
Yes  
Yes  
No  
32 Pin QFN (Tape and Reel) CY8C23533-24LQXIT  
28 Pin (210 Mil) SSOP  
CY8C23433-24PVXI  
CY8C23433-24PVXIT  
28 Pin (210 Mil) SSOP  
(Tape and Reel)  
No  
Document Number: 001-44369 Rev. *B  
Page 36 of 37  
CY8C23433, CY8C23533  
Document History Page  
®
Document Title: CY8C23433, CY8C23533 PSoC Programmable System-on-Chip™  
Document Number: 001-44369  
Orig. of  
Change  
Submission  
Date  
Revision  
ECN  
Description of Change  
**  
2044848  
KIY/AESA  
01/30/2008 Data sheet creation  
*A  
2482967 HMI/AESA  
05/14/2008 Moved from Preliminary to Final. Part number changed to CY8C23433,  
CY8C23533. Adjusted placement of the block diagram; updated description  
of DAC; updated package pinout description, updated POR and LVD spec,  
Added Csc , Flash Vdd, SAR ADC spec. Updated package diagram  
001-42168 to *A. Updated data sheet template.  
®
*B  
2616862 OGNE/AESA 12/05/2008  
Changed title to: “CY8C23433, CY8C23533 PSoC Programmable  
System-on-Chip™”  
Updated package diagram 001-42168 to *C.  
Changed names of registers on page 11.  
"SARADC_C0" to "SARADC_CR0"  
"SARADC_C1" to "SARADC_CR1"  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-44369 Rev. *B  
Revised December 05, 2008  
Page 37 of 37  
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered  
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the  
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names  
mentioned in this document may be the trademarks of their respective holders.  

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