Cypress CY7C68024 User Manual

CY7C68023/CY7C68024  
EZ-USB NX2LP™ USB 2.0 NAND  
Flash Controller  
• 43-mA Typical Active Current  
1.0  
Features  
Space-saving and lead-free 56-QFN package (8 mm ×  
• High (480-Mbps) or full (12-Mbps) speed USB support  
• Both common NAND page sizes supported  
512bytes—Up to 1 Gbit Capacity  
— 2K bytes—Up to 8 Gbit Capacity  
• 8 chip enable pins  
8 mm)  
• Support for board-level manufacturing test via USB  
interface  
• 3.3V NAND Flash operation  
• NAND Flash power management support  
— Up to 8 NAND Flash single-device chips  
— Up to 4 NAND Flash dual-device chips  
• Industry standard ECC NAND Flash correction  
— 1 bit per 256 correction  
2.0  
Introduction  
The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND  
Flash controller. This controller adheres to the Mass Storage  
Class Bulk-Only Transport Specification. The USB port of the  
NX2LP is connected to a host computer directly or via the  
downstream port of a USB hub. Host software issues  
commands and data to the NX2LP and receives status and  
data from the NX2LP using standard USB protocol.  
—2 bit error detection  
• Industry standard (SmartMedia) page management for  
wear leveling algorithm, bad block handling, and  
Physical to Logical management.  
• Supports 8-bit NAND Flash interfaces  
The NX2LP supports industry leading 8-bit NAND Flash inter-  
faces and both common NAND page sizes of 512 and 2k  
bytes. Eight chip enable pins allow the NX2LP to be connected  
to up to eight single- or four dual-device NAND Flash chips.  
• Supports 30-ns, 50-ns, 100-ns NAND Flash timing  
• Complies with USB Mass Storage Class Specification  
rev 1.0  
• CY7C68024 complies with USB 2.0 Specification for  
Bus-Powered Devices (TID# 40460274)  
Certain NX2LP features are configurable, enabling the NX2LP  
to meet the needs of different designs’ requirements.  
Write Protect  
LED2#  
Chip Reset  
LED1#  
24 MHz  
PLL  
Xtal  
EZ-USB NX2LP  
Internal Control Logic  
Control  
NAND Control Signals  
Chip Enable Signals  
8-bit Data Bus  
NAND Flash  
Interface  
Logic  
Smart HS/  
FS USB  
Engine  
VBUS  
D+  
D-  
USB 2.0  
Xceiver  
Data  
Figure 1-1. NX2LP Block Diagram  
Cypress Semiconductor Corporation  
Document #: 38-08055 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 5, 2005  
CY7C68023/CY7C68024  
3.2  
Pin  
Pin Descriptions (continued)  
Name  
Reserved  
VCC  
Type  
N/A  
PWR  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
PWR  
GND  
O
Default State at Start-up  
Description  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
N/A  
PWR  
Z
Must be tied HIGH (no pull-up resistor required)  
3.3V supply  
Data 0  
DDO  
DD1  
Z
Data 1  
DD2  
Z
Data 2  
DD3  
Z
Data 3  
DD4  
Z
Data 4  
DD5  
Z
Data 5  
DD6  
Z
Data 6  
DD7  
Z
Data 7  
GND  
GND  
PWR  
GND  
H
Ground  
VCC  
3.3V supply  
Ground  
GND  
WE#  
Write enable  
Read Enable 0  
Read Enable 1  
3.3V supply  
Command latch enable  
Address latch enable  
Data activity LED sink  
Chip active LED sink  
Write-protect NAND Flash  
Write-protect switch input  
No connect  
RE0#  
RE1#  
VCC  
O
H
O
H
PWR  
O
PWR  
Z
CLE  
ALE  
O
Z
LED1#  
LED2#  
WP_NF#  
WP_SW#  
N/C  
O
Z
O
Z
O
Z
I
Z
N/A  
N/A  
GND  
I
N/A  
N/A  
GND  
Z
N/C  
No connect  
GND  
Ground  
RESET#  
VCC  
NX2LP chip reset  
3.3V supply  
Must be tied HIGH  
Chip enable 0  
Chip enable 1  
Chip enable 2  
Chip enable 3  
Chip enable 4  
Chip enable 5  
Chip enable 6  
Chip enable 7  
Ground  
PWR  
N/A  
O
PWR  
N/A  
Z
Reserved  
CE0#  
CE1#  
CE2#  
CE3#  
CE4#  
CE5#  
CE6#  
CE7#  
GND  
O
Z
O
Z
O
Z
O
Z
O
Z
O
Z
O
Z
GND  
N/A  
PWR  
GND  
GND  
N/A  
PWR  
GND  
N/C  
No connect  
VCC  
3.3V supply  
Ground  
GND  
Document #: 38-08055 Rev. *B  
Page 3 of 9  
CY7C68023/CY7C68024  
step on each falling edge of the Read Enable pulse. A 10k pull-  
up is an option For RE1-0#.  
3.3  
Additional Pin Descriptions  
3.3.1  
DPLUS, DMINUS  
3.3.7  
CLE  
DPLUS and DMINUS are the USB signaling pins, and they  
should be tied to the D+ and D– pins of the USB connector.  
Because they operate at high frequencies, the USB signals  
require special consideration when designing the layout of the  
PCB. General guidelines are given at the end of this  
document.  
The Command Latch Enable output pin is used to indicate that  
the data on the I/O bus is a command. The data is latched into  
the NAND Flash control register on the rising edge of WE#  
when CLE is HIGH.  
3.3.8  
ALE  
3.3.2  
XTALIN, XTALOUT  
The Address Latch Enable output pin is used to indicate that  
the data on the I/O bus is an address. The data is latched into  
the NAND Flash address register on the rising edge of WE#  
when ALE is HIGH.  
24-MHz Xtal  
3.3.9  
LED1#  
12 pF  
12 pF  
The Data Activity LED output pin is used to indicate data  
transfer activity. LED1# is asserted LOW at the beginning of a  
data transfer, and set to a high-Z state when the transfer is  
complete. If this functionality is not utilized, leave LED1#  
floating.  
12-pF capacitor  
values assume a  
trace capacitance  
of 3 pF per side on a  
four-layer FR4 PCB  
3.3.10 LED2#  
The Chip Active LED output pin is used to indicate proper  
device operation. LED2# is asserted LOW when the NX2LP is  
powered and initialized. It is placed in a high-Z state under all  
other conditions. If this functionality is not utilized, leave  
LED2# floating.  
XTALIN  
XTALOUT  
Figure 3-2. XTALIN, XTALOUT Diagram  
3.3.11 WP_NF#  
The Write-protect NAND Flash output pin is used to control the  
write-protect pins on NAND Flash devices. This pin should be  
tied to the Write Protect pins of the NAND Flash devices. If  
WP_SW# is asserted LOW during a data transfer, or if internal  
operations are still pending, the NX2LP will wait until the  
operation is complete before asserting WP_NF# to ensure that  
there is no data loss or risk of OS error.  
The NX2LP requires a 24-MHz (±100 ppm) signal to derive  
internal timing. Typically, a 24-MHz (20-pF, 500-µW, parallel-  
resonant fundamental mode) crystal is used, but a 24-MHz  
square wave from another source can also be used. If a crystal  
is used, connect its pins to XTALIN and XTALOUT, and also  
through 12-pF capacitors to GND. If an alternate clock source  
is used, apply it to XTALIN and leave XTALOUT open.  
3.3.12 WP_SW#  
3.3.3  
Data[7-0]  
The Write-protect Switch input pin is used to select whether or  
not NAND Flash write-protection is enabled by the NX2LP.  
When the pin is asserted LOW, the NX2LP will report to the  
host that the NAND Flash is write-protected, the WP_NF# will  
be driven LOW, and any attempts to write to the configuration  
data memory area will be blocked by the NX2LP. If this pin is  
asserted LOW during a data transfer, or if internal operations  
are still pending, the NX2LP will wait until the operation is  
complete before asserting WP_NF# to ensure that there is no  
data loss or risk of OS error.  
The Data[7-0] I/O pins provide an 8-bit interface to a NAND  
Flash device. These pins are used to transfer address,  
command, and read/write data between the NX2LP and NAND  
Flash.  
3.3.4  
R_B[2-1]#  
The Ready/Busy input pins are used to determine the state of  
the currently selected NAND Flash device. These pins must  
be pulled HIGH through a 2k-4k resistor. These pins are pulled  
LOW by the NAND Flash when it is busy.  
3.3.13 CE[7-0]#  
3.3.5  
WE#  
The Chip Enable output pins are used to select the NAND  
Flash that the NX2LP will interface. Unused Chip Enable pins  
should be left floating.  
The Write Enable output pin is used by the NAND Flash to  
latch commands, address, and data during the rising edge of  
the pulse.  
3.3.14 RESET#  
3.3.6  
RE[1-0]#  
Asserting RESET# for 10 ms will reset the NX2LP. A reset  
and/or watchdog chip is recommended to ensure that startup  
and brownout conditions are properly handled.  
The Read Enable output pins are used to control the data flow  
from the NAND Flash devices. The device presents valid data  
and will increment its internal column address counter by one  
Document #: 38-08055 Rev. *B  
Page 4 of 9  
CY7C68023/CY7C68024  
A unique USB serial number is required for each device in  
order to comply with the USB Mass Storage specification.  
Also, Cypress requires designers to use their own Vendor ID  
for final products. The Vendor ID is obtained through regis-  
tration with the USB Implementor’s Forum (USB-IF), and the  
Product ID is determined by the designer.  
4.0  
Applications  
The NX2LP is a high-speed USB 2.0 peripheral device that  
connects NAND Flash devices to a USB host using the USB  
Mass Storage Class protocol.  
4.1  
Additional Resources  
Cypress provides all the software tools and drivers necessary  
for properly programming and testing the NX2LP. Please refer  
to the documentation in the development or reference design  
kit for more information on these topics.  
• CY3685 EZ-USB NX2LP Development Kit  
• CY4618 EZ-USB NX2LP Reference Design Kit  
• USB Specification version 2.0  
• USBMassStorageClassBulkOnlyTransportSpecification,  
usbmassbulk_10.pdf.  
Start-up  
5.0  
Functional Overview  
USB Signaling Speed  
NAND Flash  
Present?  
Yes  
No  
5.1  
The NX2LP operates at two of the three rates defined in the  
USB Specification Revision 2.0 dated April 27, 2000:  
• Full speed, with a signaling bit rate of 12 Mbits/sec  
• High speed, with a signaling bit rate of 480 Mbits/sec.  
The NX2LP does not support the low-speed signaling rate of  
1.5 Mbits/sec.  
NAND Flash  
Programmed?  
No  
5.2  
NAND Flash Interface  
During normal operation the NX2LP supports an 8-bit I/O  
interface, eight chip enable pins, and other control signals  
compatible with industry standard NAND Flash devices.  
Yes  
Load Custom  
Descriptors and  
Configuration Data  
Load Default  
Descriptors and  
Configuration Data  
6.0  
Enumeration  
During the start-up sequence, internal logic checks for the  
presence of NAND Flash with valid configuration data in the  
configuration data memory area. If valid configuration data is  
found, the NX2LP uses the values stored in NAND Flash to  
configure the USB descriptors for normal operation as a USB  
mass storage device. If no NAND Flash is detected, or if no  
valid configuration data is found in the configuration data  
memory area, the NX2LP uses the default values from internal  
ROM space for manufacturing mode operation. The two  
modes of operation are described in sections 6.1 and 6.2  
below.  
Enumerate As  
USB Mass  
Storage Device  
Enumerate As  
Generic NX2LP  
Device  
6.1  
Normal Operation Mode  
Normal Operation  
Mode  
Manufacturing  
Mode  
In Normal Operation Mode, the NX2LP behaves as a USB 2.0  
Mass Storage Class NAND Flash controller. This includes all  
typical USB device states (powered, configured, etc.). The  
USB descriptors are returned according to the data stored in  
the configuration data memory area. Normal read and write  
access to the NAND Flash is available in this mode.  
Figure 6-1. NX2LP Enumeration Process  
6.3  
Configuration Data  
Certain features in the NX2LP can be configured by the  
designer to disable unneeded features, and to comply with the  
USB 2.0 specification’s descriptor requirements for mass  
storage devices. Table 6-1 lists the variable configuration data  
and the default values that are stored in internal ROM space.  
The default ROM values are returned by an unprogrammed  
NX2LP device.  
6.2  
Manufacturing Mode  
In Manufacturing mode, the NX2LP enumerates using the  
default descriptors and configuration data that are stored in  
internal ROM. This mode allows for first-time programming of  
the configuration data memory area, as well as board-level  
manufacturing tests.  
Document #: 38-08055 Rev. *B  
Page 5 of 9  
   
CY7C68023/CY7C68024  
Table 6-1. Variable Configuration Data And Default ROM Values  
Configuration Data  
Vendor ID  
Description  
USB Vendor ID (Assigned by USB-IF)  
USB Product ID (Assigned by designer)  
USB serial number  
Default ROM Value  
0x04B4 (Cypress)  
Product ID  
0x6813  
N/A  
Serial Number  
Manufacturer String  
Product String  
Manufacturer string in USB descriptors  
Product string in USB descriptors  
N/A  
N/A  
Enable Write Protection Enables write protection capability  
SCSI Device Name String shown in the device manager properties  
Enabled  
N/A  
• Maintain a solid ground plane under the DPLUS and DMI-  
NUS traces. Do not allow the plane to be split under these  
traces.  
7.0  
DesignNotesForTheQuadFlatNoLead  
(QFN) Package  
The NX2LP comes in a 56-pin QFN package, which utilizes a  
metal pad on the bottom to aid in heat dissipation. The low-  
power operation of the NX2LP makes the thermal pad on the  
bottom of the QFN package unnecessary. Because of this,  
PCB layout may utilize the space under the NX2LP for routing  
signals as needed, provided that any traces or vias under the  
thermal pad are covered by solder mask or other material to  
prevent shorting. Standard PCB layout recommendations for  
USB devices still apply.  
• Place no vias on the DPLUS or DMINUS trace routing.  
• Isolate the DPLUS and DMINUS traces from all other signal  
traces (use >10 mm. spacing for best signal quality).  
Source for recommendations:  
• EZ-USB FX2 PCB Design Recommendations, www.cy-  
press.com/cfuploads/support/app_notes/FX2_PCB.pdf.  
• High-speed USB Platform Design Guidelines,  
For further information on this package design, please refer to  
the application note from AMKOR titled “Surface Mount  
Assembly of AMKOR’s MicroLeadFrame (MLF) Technology.”  
This application note provides detailed information on board  
mounting guidelines, soldering flow, rework process, etc.  
9.0  
Absolute Maximum Ratings  
Storage Temperature...................................65°C to +150°C  
Ambient Temperature with Power  
Supplied............................................................ 0°C to +70°C  
8.0  
PCB Layout Recommendations  
Supply Voltage to Ground Potential................–0.5V to +4.0V  
DC Input Voltage to Any Input Pin................................ 5.25V  
The following recommendations should be followed to ensure  
reliable High-speed USB performance operation.  
DC Voltage Applied to Outputs  
in High-Z State..................................... –0.5V to VCC + 0.5V  
• A four-layer impedance controlled board is recommended  
to ensure best signal quality.  
Power Dissipation..................................................... 300 mW  
Static Discharge Voltage.............................................. 2000V  
Max Output Current per IO port................................... 10 mA  
• Specify impedance targets (ask your board vendor what  
they can achieve).  
• Maintain trace widths and trace spacing to control imped-  
ance.  
Operating Conditions[2]  
• Minimize stubs on DPLUS and DMINUS to avoid reflected  
signals.  
10.0  
T (Ambient Temperature Under Bias)............. 0°C to +70°C  
A
• Place any connections between the USB connector shell  
and signal ground near the USB connector.  
Supply Voltage............................................+3.00V to +3.60V  
Ground Voltage.................................................................. 0V  
• Use bypass/flyback caps on VBUS, placed near connector.  
• Keep DPLUS and DMINUS trace lengths to within 2 mm of  
each other in length, with preferred length of 20–30 mm.  
F
(Oscillator or Crystal Frequency) ... 24 MHz ± 100 ppm  
Parallel Resonant  
OSC  
Note:  
2. If an alternate clock source is input on XTALIN, it must be supplied with standard 3.3V signaling characteristics and XTALOUT must be left floating.  
Document #: 38-08055 Rev. *B  
Page 6 of 9  
   
CY7C68023/CY7C68024  
11.0  
DC Characteristics  
Parameter  
Description  
Conditions  
Min.  
3.0  
200  
2
Typ.  
Max.  
Unit  
V
V
V
V
V
Supply Voltage  
Ramp Supply Ramp-up 0V to 3.3V  
Input High Voltage  
3.3  
3.6  
CC  
CC  
IH  
µs  
V
5.25  
0.8  
Input Low Voltage  
–0.5  
V
IL  
I
Input Leakage Current  
0 < V < V  
±10  
5.25  
0.8  
µA  
V
I
IN  
CC  
V
V
V
V
Crystal Input HIGH Voltage  
Crystal Input LOW Voltage  
Output Voltage High  
2
IH_X  
IL_X  
OH  
–0.5  
2.4  
V
I
I
= 4 mA  
V
OUT  
Output Voltage Low  
= –4 mA  
0.4  
4
V
OL  
OUT  
I
I
Output Current High  
Output Current Low  
mA  
mA  
pF  
pF  
mA  
mA  
mA  
mA  
µA  
µA  
mA  
OH  
OL  
4
C
Input Pin Capacitance  
All but D+/D–  
Only D+/D–  
10  
15  
IN  
I
Supply Current  
USB High Speed  
USB Full Speed  
50  
35  
CC  
I
Suspend Current CY7C68023 Connected  
Disconnected  
0.5  
0.3  
300  
100  
43  
1.2  
SUSP  
1.0  
CY7C68024 Connected  
Disconnected  
380  
150  
I
Unconfigured Current  
Before current requested in USB  
descriptors is granted by the host  
UNCONFIG  
T
Reset Time After Valid Power  
Pin Reset After Valid Startup  
V
> 3.0V  
CC  
5.0  
mS  
RESET  
200  
µS  
12.0  
12.1  
AC Electrical Characteristics  
USB Transceiver  
The NX2LP’s USB interface complies with the USB 2.0 speci-  
fication for bus-powered devices.  
12.2  
NAND Flash Timing  
The NX2LP supports 30-ns, 50-ns, and 100-ns NAND Flash  
devices.  
13.0  
Ordering Information  
Part Number  
Package Type  
CY7C68023-56LFXC 56-pin QFN Lead-free For Self/Bus Power  
CY7C68024-56LFXC 56-pin QFN Lead-free For Battery Power  
CY3685  
CY4618  
EZ-USB NX2LP Development Kit  
EZ-USB NX2LP Reference Design Kit  
Note:  
3. Measured at Max V , 25°C.  
CC  
Document #: 38-08055 Rev. *B  
Page 7 of 9  
 
CY7C68023/CY7C68024  
14.0  
Package Diagram  
56-Lead QFN 8 x 8 MM LF56A  
TOP VIEW  
BOTTOM VIEW  
SIDE VIEW  
0.08[0.003]  
C
1.00[0.039] MAX.  
0.80[0.031] MAX.  
7.90[0.311]  
A
8.10[0.319]  
0.05[0.002] MAX.  
0.18[0.007]  
0.28[0.011]  
7.70[0.303]  
7.80[0.307]  
0.20[0.008] REF.  
PIN1 ID  
N
N
0.20[0.008] R.  
1
1
2
2
0.45[0.018]  
0.80[0.031]  
DIA.  
E-PAD  
(PAD SIZE VARY  
BY DEVICE TYPE)  
0.30[0.012]  
0.50[0.020]  
0.24[0.009]  
(4X)  
0.60[0.024]  
0°-12°  
0.50[0.020]  
6.45[0.254]  
6.55[0.258]  
C
SEATING  
PLANE  
Dimensions in mm  
E-Pad Size 4.3 x 5.0 mm (typ.)  
51-85144-*D  
Figure 14-1. 56-lead Quad Flatpack No Lead (8 x 8 mm) LF56  
15.0  
Disclaimers, Trademarks, and Copyrights  
EZ-USB NX2LP is a trademark, and EZ-USB is a registered trademark, of Cypress Semiconductor Corporation. All product and  
company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-08055 Rev. *B  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C68023/CY7C68024  
Document History Page  
Description Title: CY7C68023/CY7C68024 EZ-USB NX2LP™ USB 2.0 NAND Flash Controller  
Document Number: 38-08055  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
286009  
334796  
397024  
Description of Change  
New Data Sheet (Preliminary Information).  
SEE ECN  
SEE ECN  
SEE ECN  
GIR  
GIR  
GIR  
*A  
Adjusted default VID/PID; released as final.  
*B  
Changed Vcc to ±10% in DC Characteristics table. Changed the supply  
voltage tolerance to ±10% in the Operating Conditions section. Added new  
logo.  
Document #: 38-08055 Rev. *B  
Page 9 of 9  

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