Cypress CY7C63413C User Manual
CY7C63413C  
CY7C63513C  
CY7C63613C  
Low-Speed High I/O, 1.5-Mbps USB Controller  
• Operating voltage from 4.0V to 5.5V DC  
Features  
• Operating temperature from 0 to 70 degrees Celsius  
• Low-cost solution for low-speed applications with high  
I/O requirements such as keyboards, keyboards with  
integrated pointing device, gamepads, and many  
others  
• CY7C63413C available in 40-pin PDIP, 48-pin SSOP, 48-  
pin SSOP - Tape reel, all in Lead-Free versions for  
production  
• CY7C63513C available in 48-pin SSOP Lead-Free  
packages for production  
• USB Specification Compliance  
— Conforms to USB Specification, Versions 1.1 and 2.0  
— Conforms to USB HID Specification, Version 1.1  
— Supports 1 device address and 3 data endpoints  
— Integrated USB transceiver  
• CY7C63613C available in 24-pin SOIC Lead-Free  
packages for production  
• Industry-standard programmer support  
Functional Overview  
• 8-bit RISC microcontroller  
— Harvard architecture  
The CY7C63413C/513C/613C are 8-bit RISC One Time  
Programmable (OTP) microcontrollers. The instruction set has  
been optimized specifically for USB operations, although the  
microcontrollers can be used for a variety of non-USB  
embedded applications.  
— 6-MHz external ceramic resonator  
— 12-MHz internal CPU clock  
• Internal memory  
The CY7C63413C/513C features 32 General-Purpose I/O  
(GPIO) pins to support USB and other applications. The I/O  
pins are grouped into four ports (Port 0 to 3) where each port  
can be configured as inputs with internal pull-ups, open drain  
outputs, or traditional CMOS outputs. The CY7C63413C/513C  
have 24 GPIO pins (Ports 0 to 2) that are rated at 7 mA typical  
sink current. The CY7C63413C/513C has 8 GPIO pins (Port  
3) that are rated at 12 mA typical sink current, which allows  
these pins to drive LEDs.  
— 256 bytes of RAM  
— 8 Kbytes of EPROM  
• Interface can auto-configure to operate as PS2 or USB  
• I/O port  
— The CY7C63413C/513C have 24 General Purpose I/O  
(GPIO) pins (Port 0 to 2) capable of sinking 7 mA per  
pin (typical)  
— The CY7C63613C has 12 General Purpose I/O (GPIO)  
pins (Port 0 to 2) capable of sinking 7 mA per pin  
(typical)  
The CY7C63613C features 16 General-Purpose I/O (GPIO)  
pins to support USB and other applications. The I/O pins are  
grouped into four ports (Port 0 to 3) where each port can be  
configured as inputs with internal pull-ups, open drain outputs,  
or traditional CMOS outputs. The CY7C63613C has 12 GPIO  
pins (Ports 0 to 2) that are rated at 7 mA typical sink current.  
The CY7C63613C has 4 GPIO pins (Port 3) that are rated at  
12 mA typical sink current, which allows these pins to drive  
LEDs.  
— The CY7C63413C/513C have eight GPIO pins (Port  
3) capable of sinking 12 mA per pin (typical) which  
can drive LEDs  
— TheCY7C63613ChasfourGPIOpins(Port3)capable  
of sinking 12 mA per pin (typical) which can drive  
LEDs  
Multiple GPIO pins can be connected together to drive a single  
output for more drive current capacity. Additionally, each I/O  
pin can be used to generate a GPIO interrupt to the microcon-  
troller. Note the GPIO interrupts all share the same “GPIO”  
interrupt vector.  
— Higher current drive is available by connecting  
multiple GPIO pins together to drive a common  
output  
— Each GPIO port can be configured as inputs with  
internal pull-ups or open drain outputs or traditional  
CMOS outputs  
The CY7C63513C features an additional 8 I/O pins in the DAC  
port. Every DAC pin includes an integrated 14-Kohm pull-up  
resistor. When a “1” is written to a DAC I/O pin, the output  
current sink is disabled and the output pin is driven high by the  
internal pull-up resistor. When a “0” is written to a DAC I/O pin,  
the internal pull-up is disabled and the output pin provides the  
programmed amount of sink  
— The CY7C63513C has an additional eight I/O pins on  
a DAC port which has programmable current sink  
outputs  
— Maskable interrupts on all I/O pins  
• 12-bit free-running timer with one microsecond clock  
ticks  
current. A DAC I/O pin can  
be used as an input with an  
internal pull-up by writing a  
“1” to the pin.  
• Watch Dog Timer (WDT)  
• Internal Power-On Reset (POR)  
• Improved output drivers to reduce EMI  
Cypress Semiconductor Corporation  
Document #: 38-08027 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 6, 2006  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
.
Pin Configuration  
Logic Block Diagram  
CY7C63513C  
48-pin SSOP  
CY7C63413C  
48-pin SSOP  
6-MHz ceramic resonator  
D+  
1
2
3
4
48  
47  
46  
V
CC  
Vss  
D+  
1
2
3
4
48  
47  
46  
V
CC  
Vss  
D–  
P3[7]  
P3[5]  
P3[3]  
P3[1]  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
NC  
D–  
P3[7]  
P3[5]  
P3[3]  
P3[1]  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
DAC[7]  
DAC[5]  
P0[7]  
P0[5]  
P0[3]  
P0[1]  
DAC[3]  
DAC[1]  
OSC  
P3[6]  
P3[4]  
P3[2]  
P3[0]  
P2[6]  
P2[4]  
P3[6]  
P3[4]  
P3[2]  
P3[0]  
P2[6]  
P2[4]  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
5
6
7
8
12 MHz 6 MHz  
5
6
7
8
9
P2[2]  
P2[0]  
P1[6]  
P1[4]  
P1[2]  
P1[0]  
NC  
9
P2[2]  
P2[0]  
P1[6]  
P1[4]  
P1[2]  
P1[0]  
DAC[6]  
DAC[4]  
P0[6]  
P0[4]  
P0[2]  
P0[0]  
DAC[2]  
DAC[0]  
XTAL  
12-MHz  
8-bit  
CPU  
USB  
PS/2  
PORT  
USB  
Transceiver  
D+  
D–  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
NC  
NC  
P0[7]  
P0[5]  
P0[3]  
P0[1]  
NC  
P0[6]  
P0[4]  
P0[2]  
P0[0]  
NC  
NC  
XTAL  
XTAL  
USB  
SIE  
EPROM  
4/6/8 Kbyte  
NC  
V
V
PP  
OUT  
IN  
PP  
OUT  
Vss  
Vss  
XTAL  
IN  
RAM  
Interrupt  
256 byte  
Controller  
CY7C63413C  
40-pin PDIP  
CY7C63613C  
24-pin SOIC  
See Note 1  
P0[0]  
D+  
1
40 VCC  
39 VSS  
38  
37 P3[4]  
36  
35 P3[0]  
34 P2[6]  
33 P2[4]  
32 P2[2]  
31 P2[0]  
30 P1[6]  
D+  
1
24  
VCC  
12-bit  
Timer  
GPIO  
PORT 0  
D–  
P3[7]  
P3[5]  
P3[3]  
P3[1]  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
P0[7]  
P0[5]  
P0[3]  
P0[1]  
VPP  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
D–  
P3[7]  
P3[5]  
P1[3]  
P1[1]  
P0[7]  
P0[5]  
P0[3]  
P0[1]  
VPP  
2
3
4
5
6
7
8
9
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VSS  
P0[7]  
P3[6]  
P3[6]  
P3[4]  
P1[2]  
P1[0]  
P0[6]  
P0[4]  
P0[2]  
P0[0]  
P3[2]  
P1[0]  
P1[7]  
GPIO  
PORT 1  
10  
11  
12  
XTALOUT  
XTALIN  
29  
28  
27  
26  
25  
24  
23  
P1[4]  
P1[2]  
P1[0]  
P0[6]  
P0[4]  
P0[2]  
P0[0]  
Vss  
P2[0]  
P2[7]  
GPIO  
PORT 2  
CY7C63413C  
48-Pad Die  
Watch Dog  
Timer  
22 XTALOUT  
21 XTALIN  
P3[0]  
P3[7]  
GPIO  
PORT 3  
Vss  
High Current  
Outputs  
P3[3]  
P3[1]  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
P3[2]  
P3[0]  
P2[6]  
P2[4]  
P2[2]  
P2[0]  
DAC[0]  
Power-on  
Reset  
DAC  
PORT  
CY7C63513C only  
P1[6]  
P1[4]  
P1[2]  
P1[0]  
DAC[6]  
DAC[4]  
P0[6]  
P0[4]  
DAC[7]  
DAC[7]  
DAC[5]  
P0[7]  
0
P0[5]  
Note:  
1. CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 12  
for firmware code needed for unused GPIO pins.  
.
Document #: 38-08027 Rev. *B  
Page 3 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Pin Definitions  
CY7C63413C  
40-Pin 48-Pin  
1,2 1,2  
CY7C63513C CY7C63613C  
Name  
I/O  
Die  
48-Pin  
24-Pin  
Description  
D+, D–  
I/O  
1,2  
1,2  
1,2  
USB differential data; PS/2 clock and  
data signals  
P0[7:0]  
P1[3:0]  
P2  
I/O  
15,26,16 17,32,18 17,32,18, 17,32,18,31, 7, 18, 8, 17, 9, GPIO port 0 capable of sinking 7 mA  
25,17,24 31,19,30 31,19,30, 19,30,20,29  
16, 10, 15  
(typical)  
18,23 20,29 20,29  
I/O 11,30,12, 11,38,12, 11,38,12, 11,38,12,37,  
29,13,28, 37,13,36, 37,13,36, 13,36,14,35  
5, 20, 6, 19  
GPIO Port 1 capable of sinking 7 mA  
(typical).  
14,27  
14,35  
14,35  
I/O  
I/O  
I/O  
7,34,8,  
33,9,32,  
10,31  
7,42,8,  
41,9,40,  
10,39  
7,42,8,  
41,9,40,  
10,39  
7,42,8,41,9,  
40,10,39  
n/a  
3, 22, 4, 21  
n/a  
GPIO Port 2 capable of sinking 7 mA  
(typical).  
P3[7:4]  
DAC  
3,38,4,  
37,5,36,  
6,35  
3,46,4,  
45,5,44,  
6,43  
3,46,4,  
45,5,44,  
6,43  
3,46,4,45,5,  
44,6,43  
GPIO Port 3 capable of sinking 12 mA  
(typical).  
n/a  
n/a  
15,34,16, 15,34,16,33,  
33,21,28, 21,28,22,27  
22,27  
DAC I/O Port with programmable  
current sink outputs. DAC[1:0] offer a  
programmable range of 3.2 to 16 mA  
typical. DAC[7:2] have a program-  
mable sink current range of 0.2 to 1.0  
mA typical. DAC I/O Port not bonded  
out on CY7C63613C. See note on  
page 12 for firmware code needed for  
unused pins.  
XTAL  
XTAL  
21  
25  
25  
25  
13  
6-MHz ceramic resonator or external  
clock input  
IN  
IN  
OUT  
22  
19  
26  
23  
26  
23  
26  
23  
14  
11  
6-MHz ceramic resonator  
OUT  
V
Programming voltage supply, ground  
during operation  
PP  
V
40  
48  
48  
48  
24  
Voltage supply  
Ground  
CC  
Vss  
20,39  
24,47  
24,47  
24,47  
12, 23  
Please note the program counter cannot be accessed directly  
by the firmware. The program stack can be examined by  
reading SRAM from location 0x00 and up.  
Programming Model  
14-bit Program Counter (PC)  
The 14-bit Program Counter (PC) allows access for up to 8  
kilobytes of EPROM using the CY7C63413C/513C/613C  
architecture. The program counter is cleared during reset,  
such that the first instruction executed after a reset is at  
address 0x0000. This is typically a jump instruction to a reset  
handler that initializes the application.  
8-bit Accumulator (A)  
The accumulator is the general purpose, do everything  
register in the architecture where results are usually calcu-  
lated.  
8-bit Index Register (X)  
The lower eight bits of the program counter are incremented  
as instructions are loaded and executed. The upper six bits of  
the program counter are incremented by executing an XPAGE  
instruction. As a result, the last instruction executed within a  
256-byte “page” of sequential code should be an XPAGE  
instruction. The assembler directive “XPAGEON” will cause  
the assembler to insert XPAGE instructions automatically. As  
instructions can be either one or two bytes long, the assembler  
may occasionally need to insert a NOP followed by an XPAGE  
for correct execution.  
The index register “X” is available to the firmware as an  
auxiliary accumulator. The X register also allows the processor  
to perform indexed operations by loading an index value into  
X.  
8-bit Program Stack Pointer (PSP)  
During a reset, the Program Stack Pointer (PSP) is set to zero.  
This means the program “stack” starts at RAM address 0x00  
and “grows” upward from there. Note the program stack  
pointer is directly addressable under firmware control, using  
the MOV PSP,A instruction. The PSP supports interrupt  
service under hardware control and CALL, RET, and RETI  
instructions under firmware control.  
The program counter of the next instruction to be executed,  
carry flag, and zero flag are saved as two bytes on the program  
stack during an interrupt acknowledge or a CALL instruction.  
The program counter, carry flag, and zero flag are restored  
from the program stack only during a RETI instruction.  
Document #: 38-08027 Rev. *B  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
During an interrupt acknowledge, interrupts are disabled and  
the 14-bit program counter, carry flag, and zero flag are written  
as two bytes of data memory. The first byte is stored in the  
memory addressed by the program stack pointer, then the  
PSP is incremented. The second byte is stored in memory  
addressed by the program stack pointer and the PSP is incre-  
mented again. The net effect is to store the program counter  
and flags on the program “stack” and increment the program  
stack pointer by two.  
Data  
The “Data” address mode refers to a data operand that is  
actually a constant encoded in the instruction. As an example,  
consider the instruction that loads A with the constant 0xE8:  
• MOV A,0E8h  
This instruction will require two bytes of code where the first  
byte identifies the “MOV A” instruction with a data operand as  
the second byte. The second byte of the instruction will be the  
constant “0xE8”. A constant may be referred to by name if a  
prior “EQU” statement assigns the constant value to the name.  
For example, the following code is equivalent to the example  
shown above:  
The Return From Interrupt (RETI) instruction decrements the  
program stack pointer, then restores the second byte from  
memory addressed by the PSP. The program stack pointer is  
decremented again and the first byte is restored from memory  
addressed by the PSP. After the program counter and flags  
have been restored from stack, the interrupts are enabled. The  
effect is to restore the program counter and flags from the  
program stack, decrement the program stack pointer by two,  
and re-enable interrupts.  
• DSPINIT: EQU 0E8h  
• MOV A,DSPINIT  
Direct  
“Direct” address mode is used when the data operand is a  
variable stored in SRAM. In that case, the one byte address of  
the variable is encoded in the instruction. As an example,  
consider an instruction that loads A with the contents of  
memory address location 0x10:  
The Call Subroutine (CALL) instruction stores the program  
counter and flags on the program stack and increments the  
PSP by two.  
The Return From Subroutine (RET) instruction restores the  
program counter, but not the flags, from program stack and  
decrements the PSP by two.  
• MOV A, [10h]  
In normal usage, variable names are assigned to variable  
addresses using “EQU” statements to improve the readability  
of the assembler source code. As an example, the following  
code is equivalent to the example shown above:  
8-bit Data Stack Pointer (DSP)  
The Data Stack Pointer (DSP) supports PUSH and POP  
instructions that use the data stack for temporary storage. A  
PUSH instruction will pre-decrement the DSP, then write data  
to the memory location addressed by the DSP. A POP  
instruction will read data from the memory location addressed  
by the DSP, then post-increment the DSP.  
• buttons: EQU 10h  
• MOV A,[buttons]  
Indexed  
During a reset, the Data Stack Pointer will be set to zero. A  
PUSH instruction when DSP equal zero will write data at the  
top of the data RAM (address 0xFF). This would write data to  
the memory area reserved for a FIFO for USB endpoint 0. In  
non-USB applications, this works fine and is not a problem.  
For USB applications, it is strongly recommended that the  
DSP is loaded after reset just below the USB DMA buffers.  
“Indexed” address mode allows the firmware to manipulate  
arrays of data stored in SRAM. The address of the data  
operand is the sum of a constant encoded in the instruction  
and the contents of the “X” register. In normal usage, the  
constant will be the “base” address of an array of data and the  
X register will contain an index that indicates which element of  
the array is actually addressed:  
• array: EQU 10h  
• MOV X,3  
Address Modes  
The CY7C63413C/513C/613C microcontrollers support three  
addressing modes for instructions that require data operands:  
data, direct, and indexed.  
• MOV A,[x+array]  
This would have the effect of loading A with the fourth element  
of the SRAM “array” that begins at address 0x10. The fourth  
element would be at address 0x13.  
Document #: 38-08027 Rev. *B  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Instruction Set Summary  
MNEMONIC  
HALT  
operand  
opcode  
00  
cycles  
MNEMONIC  
operand  
acc  
opcode  
20  
cycles  
7
NOP  
4
4
4
7
8
4
4
7
8
5
5
4
4
5
5
5
5
5
6
7
8
7
8
7
8
6
4
4
4
4
4
8
4
4
8
ADD A,expr  
ADD A,[expr]  
ADD A,[X+expr]  
ADC A,expr  
ADC A,[expr]  
ADC A,[X+expr]  
SUB A,expr  
SUB A,[expr]  
SUB A,[X+expr]  
SBB A,expr  
SBB A,[expr]  
SBB A,[X+expr]  
OR A,expr  
data  
direct  
index  
data  
01  
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
5
7
8
4
5
6
4
5
INC A  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
70  
72  
73  
02  
INC X  
x
03  
INC [expr]  
INC [X+expr]  
DEC A  
direct  
index  
acc  
04  
direct  
index  
data  
05  
06  
DEC X  
x
07  
DEC [expr]  
DEC [X+expr]  
IORD expr  
IOWR expr  
POP A  
direct  
index  
address  
address  
direct  
index  
data  
08  
09  
0A  
direct  
index  
data  
0B  
0C  
0D  
0E  
POP X  
PUSH A  
OR A,[expr]  
OR A,[X+expr]  
AND A,expr  
AND A,[expr]  
AND A,[X+expr]  
XOR A,expr  
XOR A,[expr]  
XOR A,[X+expr]  
CMP A,expr  
CMP A,[expr]  
CMP A,[X+expr]  
MOV A,expr  
MOV A,[expr]  
MOV A,[X+expr]  
MOV X,expr  
MOV X,[expr]  
reserved  
direct  
index  
data  
PUSH X  
0F  
SWAP A,X  
SWAP A,DSP  
MOV [expr],A  
MOV [X+expr],A  
OR [expr],A  
OR [X+expr],A  
AND [expr],A  
AND [X+expr],A  
XOR [expr],A  
XOR [X+expr],A  
IOWX [X+expr]  
CPL  
10  
direct  
index  
data  
11  
direct  
index  
direct  
index  
direct  
index  
direct  
index  
index  
12  
13  
direct  
index  
data  
14  
15  
16  
direct  
index  
data  
17  
18  
19  
direct  
index  
data  
1A  
1B  
ASL  
1C  
1D  
1E  
ASR  
direct  
RLC  
RRC  
XPAGE  
1F  
4
RET  
MOV A,X  
40  
4
DI  
MOV X,A  
41  
4
EI  
MOV PSP,A  
CALL  
60  
4
RETI  
addr  
addr  
addr  
addr  
addr  
50-5F  
80-8F  
90-9F  
A0-AF  
B0-BF  
10  
5
JMP  
JC  
addr  
addr  
addr  
addr  
C0-CF  
D0-DF  
E0-EF  
F0-FF  
5
5
7
CALL  
10  
5
JNC  
JZ  
JACC  
INDEX  
JNZ  
5
14  
Document #: 38-08027 Rev. *B  
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CY7C63513C  
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Memory Organization  
Program Memory Organization  
after reset  
Address  
0x0000  
14-bit PC  
Program execution begins here after a reset  
USB Bus Reset interrupt vector  
128-µs timer interrupt vector  
1.024-ms timer interrupt vector  
USB address A endpoint 0 interrupt vector  
USB address A endpoint 1 interrupt vector  
USB address A endpoint 2 interrupt vector  
Reserved  
0x0002  
0x0004  
0x0006  
0x0008  
0x000A  
0x000C  
0x000E  
0x0010  
0x0012  
0x0014  
0x0016  
0x0018  
0x001A  
Reserved  
Reserved  
DAC interrupt vector  
GPIO interrupt vector  
Reserved  
Program Memory begins here  
(8K - 32 bytes)  
0x1FDF  
8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C)  
Figure 1. Program Memory Space with Interrupt Vector Table  
Document #: 38-08027 Rev. *B  
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Data Memory Organization  
into four areas: program stack, data stack, user variables and  
USB endpoint FIFOs as shown below:  
The CY7C63413C/513C/613C microcontrollers provide 256  
bytes of data RAM. In normal usage, the SRAM is partitioned  
after reset  
8-bit PSP  
Address  
0x00  
Program Stack begins here and grows upward  
8-bit DSP  
user  
Data Stack begins here and grows downward  
The user determines the amount of memory required  
User Variables  
0xE8  
0xF0  
USB FIFO for Address A endpoint 2  
USB FIFO for Address A endpoint 1  
USB FIFO for Address A endpoint 0  
0xF8  
0xFF  
Top of RAM Memory  
Document #: 38-08027 Rev. *B  
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I/O Register Summary  
lator to the selected port. Indexed I/O Write (IOWX) adds the  
contents of X to the address in the instruction to form the port  
address and writes data from the accumulator to the specified  
port. Note that specifying address 0 (e.g., IOWX 0h) means  
the I/O port is selected solely by the contents of X.  
I/O registers are accessed via the I/O Read (IORD) and I/O  
Write (IOWR, IOWX) instructions. IORD reads the selected  
port into the accumulator. IOWR writes data from the accumu-  
Table 1. I/O Register Summary  
Register Name  
Port 0 Data  
I/O Address  
0x00  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
0x07  
0x08  
0x10  
0x11  
Read/Write  
Function  
R/W  
R/W  
R/W  
R/W  
W
GPIO Port 0  
GPIO Port 1  
GPIO Port 2  
GPIO Port 3  
Port 1 Data  
Port 2 Data  
Port 3 Data  
Port 0 Interrupt Enable  
Port 1 Interrupt Enable  
Port 2 Interrupt Enable  
Port 3 Interrupt Enable  
GPIO Configuration  
USB Device Address A  
EP A0 Counter Register  
EP A0 Mode Register  
EP A1 Counter Register  
EP A1 Mode Register  
EP A2 Counter Register  
EP A2 Mode Register  
USB Status & Control  
Global Interrupt Enable  
Endpoint Interrupt Enable  
Timer (LSB)  
Interrupt enable for pins in Port 0  
W
Interrupt enable for pins in Port 1  
W
Interrupt enable for pins in Port 2  
W
Interrupt enable for pins in Port 3  
R/W  
R/W  
R/W  
R/W  
R/W  
R/C  
R/W  
R/C  
R/W  
R/W  
R/W  
R
GPIO Ports Configurations  
USB Device Address A  
USB Address A, Endpoint 0 counter register  
USB Address A, Endpoint 0 configuration register  
USB Address A, Endpoint 1 counter register  
USB Address A, Endpoint 1 configuration register  
USB Address A, Endpoint 2 counter register  
USB Address A, Endpoint 2 configuration register  
USB upstream port traffic status and control register  
Global interrupt enable register  
0x12  
0x13  
0x14  
0x15  
0x16  
0x1F  
0x20  
0x21  
0x24  
0x25  
USB endpoint interrupt enables  
Lower eight bits of free-running timer (1 MHz)  
Timer (MSB)  
R
Upper four bits of free-running timer that are latched  
when the lower eight bits are read.  
WDR Clear  
0x26  
0x30  
W
R/W  
W
Watch Dog Reset clear  
[2]  
DAC Data  
DAC I/O  
DAC Interrupt Enable  
DAC Interrupt Polarity  
DAC Isink  
0x31  
Interrupt enable for each DAC pin  
0x32  
W
Interrupt polarity for each DAC pin  
0x38-0x3F  
0xFF  
W
One four bit sink current register for each DAC pin  
Microprocessor status and control  
Processor Status & Control  
R/W  
Note:  
2. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused GPIO pins.  
Document #: 38-08027 Rev. *B  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Clock Distribution  
XTALOUT  
XTALIN  
clk1x  
(to USB SIE)  
Clock  
Doubler  
clk2x  
(to Microcontroller)  
30 pF  
30 pF  
Figure 2. Clock Oscillator On-chip Circuit  
processing does NOT push the program counter, carry flag,  
and zero flag onto program stack. That means the reset  
handler in firmware should initialize the hardware and begin  
executing the “main” loop of code. Attempting to execute either  
a RET or RETI in the reset handler will cause unpredictable  
execution results.  
Clocking  
The XTAL and XTAL  
are the clock pins to the microcon-  
OUT  
IN  
troller. The user can connect a low-cost ceramic resonator or  
an external oscillator can be connected to these pins to  
provide a reference frequency for the internal clock distribution  
and clock doubler.  
Power-On Reset (POR)  
An external 6-MHz clock can be applied to the XTAL pin if  
IN  
Power-On Reset (POR) occurs every time the V voltage to  
the XTAL  
pin is left open. Please note that grounding the  
CC  
OUT  
the device ramps from 0V to an internally defined trip voltage  
(Vrst) of approximately 1/2 full supply voltage. In addition to the  
normal reset initialization noted under “Reset,” bit 4 (PORS) of  
the Processor Status and Control Register is set to “1” to  
indicate to the firmware that a Power-On Reset occurred. The  
POR event forces the GPIO ports into input mode (high  
impedance), and the state of Port 3 bit 7 is used to control how  
the part will respond after the POR releases.  
XTAL  
pin is not permissible as the internal clock is effec-  
OUT  
tively shorted to ground.  
Reset  
The USB Controller supports three types of resets. All  
registers are restored to their default states during a reset. The  
USB Device Addresses are set to 0 and all interrupts are  
disabled. In addition, the Program Stack Pointer (PSP) and  
Data Stack Pointer (DSP) are set to 0x00. For USB applica-  
tions, the firmware should set the DSP below 0xE8 to avoid a  
memory conflict with RAM dedicated to USB FIFOs. The  
assembly instructions to do this are shown below:  
If Port 3 bit 7 is HIGH (pulled to V ) and the USB IO are at  
CC  
the idle state (DM HIGH and DP LOW) the part will go into a  
semi-permanent power down/suspend mode, waiting for the  
USB IO to go to one of Bus Reset, K (resume) or SE0. If Port  
3 bit 7 is still HIGH when the part comes out of suspend, then  
a 128-µs timer starts, delaying CPU operation until the ceramic  
resonator has stabilized.  
Mov A, E8h  
; Move 0xE8 hex into Accumulator  
Swap A,dsp ; Swap accumulator value into dsp register  
The three reset types are:  
If Port 3 bit 7 was LOW (pulled to V ) the part will start a 96-  
SS  
ms timer, delaying CPU operation until V  
then continuing to run as reset.  
has stabilized,  
CC  
1. Power-On Reset (POR)  
2. Watch Dog Reset (WDR)  
Firmware should clear the POR Status (PORS) bit in register  
0xFF before going into suspend as this status bit selects the  
128-µs or 96-ms start-up timer value as follows: IF Port 3 bit 7  
is HIGH then 128-µs is always used; ELSE if PORS is HIGH  
then 96-ms is used; ELSE 128-µs is used.  
3. USB Bus Reset (non hardware reset)  
The occurrence of a reset is recorded in the Processor Status  
and Control Register located at I/O address 0xFF. Bits 4, 5,  
and 6 are used to record the occurrence of POR, USB Reset,  
and WDR respectively. The firmware can interrogate these bits  
to determine the cause of a reset.  
Watch Dog Reset (WDR)  
The Watch Dog Timer Reset (WDR) occurs when the Most  
Significant Bit (MSB) of the 2-bit Watch Dog Timer Register  
transitions from LOW to HIGH. In addition to the normal reset  
The microcontroller begins execution from ROM address  
0x0000 after a POR or WDR reset. Although this looks like  
interrupt vector 0, there is an important difference. Reset  
8.192 ms  
to 14.336 ms  
2.048 ms  
At least 8.192 ms  
WDR goes high  
for 2.048 ms  
Figure 3. Watch Dog Reset (WDR)  
Execution begins at  
Reset Vector 0X00  
since last write to WDT  
Document #: 38-08027 Rev. *B  
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initialization noted under “Reset,” bit 6 of the Processor Status  
and Control Register is set to “1” to indicate to the firmware  
that a Watch Dog Reset occurred.  
General Purpose I/O Ports  
Ports 0 to 2 provide 24 GPIO pins that can be read or written.  
Each port (8 bits) can be configured as inputs with internal pull-  
ups, open drain outputs, or traditional CMOS outputs. Please  
note an open drain output is also a high-impedance (no pull-  
up) input. All of the I/O pins within a given port have the same  
configuration. Ports 0 to 2 are considered low current drive  
with typical current sink capability of 7 mA.  
The Watch Dog Timer is a 2-bit timer clocked by a 4.096-ms  
clock (bit 11) from the free-running timer. Writing any value to  
the write-only Watch Dog Clear I/O port (0x26) will clear the  
Watch Dog Timer.  
In some applications, the Watch Dog Timer may be cleared in  
the 1.024-ms timer interrupt service routine. If the 1.024-ms  
timer interrupt service routine does not get executed for 8.192  
ms or more, a Watch Dog Timer Reset will occur. A Watch Dog  
Timer Reset lasts for 2.048 ms after which the microcontroller  
begins execution at ROM address 0x0000. The USB trans-  
mitter is disabled by a Watch Dog Reset because the USB  
Device Address Register is cleared. Otherwise, the USB  
Controller would respond to all address 0 transactions. The  
USB transmitter remains disabled until the MSB of the USB  
address register is set.  
The internal pull-up resistors are typically 7 kΩ. Two factors  
govern the enabling and disabling of the internal pull-up  
resistors: the port configuration selected in the GPIO Configu-  
ration register and the state of the output data bit. If the GPIO  
Configuration selected is “Resistive” and the output data bit is  
“1,” then the internal pull-up resistor is enabled for that GPIO  
pin. Otherwise, Q1 is turned off and the 7-kΩ pull-up is  
disabled. Q2 is “ON” to sink current whenever the output data  
bit is written as a “0.” Q3 provides “HIGH” source current when  
the GPIO port is configured for CMOS outputs and the output  
data bit is written as a “1”. Q2 and Q3 are sized to sink and  
source, respectively, roughly the same amount of current to  
support traditional CMOS outputs with symmetric drive.  
V
CC  
GPIO  
CFG  
mode  
2 bits  
Q3  
Q1  
Data  
Out  
Latch  
Internal  
Data Bus  
7 kΩ  
Port Write  
GPIO  
Pin  
Q2  
ESD  
Internal  
Buffer  
Port Read  
to Interrupt  
Controller  
Interrupt  
Enable  
Figure 4. Block Diagram of a GPIO Line  
.
Table 2. Port 0 Data  
Addr: 0x00  
Port 0 Data  
P0[7]  
R/W  
P0[6]  
R/W  
P0[5]  
P0[4]  
R/W  
P0[3]  
R/W  
P0[2]  
R/W  
P0[1]  
R/W  
P0[0]  
R/W  
R/W  
Table 3. Port 1 Data  
Addr: 0x01  
P1[7]  
Port 1 Data  
P1[6]  
R/W  
P1[5]  
R/W  
P1[4]  
R/W  
P1[3]  
R/W  
P1[2]  
R/W  
P1[1]  
R/W  
P1[0]  
R/W  
R/W  
Table 4. Port 2 Data  
Addr: 0x02  
P2[7]  
R/W  
Port 2 Data  
P2[6]  
R/W  
P2[5]  
R/W  
P2[4]  
R/W  
P2[3]  
R/W  
P2[2]  
R/W  
P2[1]  
R/W  
P2[0]  
R/W  
Document #: 38-08027 Rev. *B  
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Table 5. Port 3 Data  
Addr: 0x03  
Port 3 Data  
P3[4]  
R/W  
P3[7]  
R/W  
P3[6]  
R/W  
P3[5]  
R/W  
P3[3]  
R/W  
P3[2]  
R/W  
P3[1]  
R/W  
P3[0]  
R/W  
Table 6. DAC Port Data  
Addr: 0x30  
DAC Port Data  
Low current outputs  
0.2 mA to 1.0 mA typical  
High current outputs  
3.2 mA to 16 mA typical  
DAC[7]  
R/W  
DAC[6]  
R/W  
DAC[5]  
R/W  
DAC[4]  
R/W  
DAC[3]  
R/W  
DAC[2]  
R/W  
DAC[1]  
R/W  
DAC[0]  
R/W  
Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured  
as inputs with internal pull-ups, open drain outputs, or tradi-  
tional CMOS outputs. An open drain output is also a high-  
impedance input. Port 3 offers high current drive with a typical  
current sink capability of 12 mA. The internal pull-up resistors  
are typically 7 kΩ.  
During reset, all of the bits in the GPIO to a default configu-  
ration of Open Drain output, positive interrupt polarity for all  
GPIO ports.  
GPIO Interrupt Enable Ports  
During a reset, GPIO interrupts are disabled by clearing all of  
the GPIO interrupt enable ports. Writing a “1” to a GPIO  
Interrupt Enable bit enables GPIO interrupts from the corre-  
sponding input pin.  
Note: Special care should be exercised with any unused GPIO  
data bits. An unused GPIO data bit, either a pin on the chip or  
a port bit that is not bonded on a particular package, must not  
be left floating when the device enters the suspend state. If a  
GPIO data bit is left floating, the leakage current caused by the  
floating bit may violate the suspend current limitation specified  
by the USB Specification. If a ‘1’ is written to the unused data  
bit and the port is configured with open drain outputs, the  
unused data bit will be in an indeterminate state. Therefore, if  
an unused port bit is programmed in open-drain mode, it must  
be written with a ‘0.’ Notice that the CY7C63613C will always  
require that data bits P1[7:4], P2[7:0], P3[3:0] and DAC[7:0] be  
written with a ‘0’.  
GPIO Configuration Port  
Every GPIO port can be programmed as inputs with internal  
pull-ups, open drain outputs, and traditional CMOS outputs. In  
addition, the interrupt polarity for each port can be pro-  
grammed. With positive interrupt polarity, a rising edge (“0” to  
“1”) on an input pin causes an interrupt. With negative polarity,  
a falling edge (“1” to “0”) on an input pin causes an interrupt.  
As shown in the table below, when a GPIO port is configured  
with CMOS outputs, interrupts from that port are disabled. The  
GPIO Configuration Port register provides two bits per port to  
program these features. The possible port configurations are  
as shown in Table 11.  
Table 7. Port 0 Interrupt Enable  
Addr: 0x04  
P0[7]  
Port 0 Interrupt Enable  
P0[6]  
W
P0[5]  
W
P0[4]  
W
P0[3]  
W
P0[2]  
W
P0[1]  
W
P0[0]  
W
W
Table 8. Port 1 Interrupt Enable  
Addr: 0x05  
Port 1 Interrupt Enable  
P1[7]  
W
P1[6]  
W
P1[5]  
W
P1[4]  
W
P1[3]  
W
P1[2]  
W
P1[1]  
W
P1[0]  
W
Table 9. Port 2 Interrupt Enable  
Addr: 0x06  
Port 2 Interrupt Enable  
P2[7]  
W
P2[6]  
W
P2[5]  
W
P2[4]  
W
P2[3]  
W
P2[2]  
W
P2[1]  
W
P2[0]  
W
Table 10.Port 3 Interrupt Enable  
Addr: 0x07  
Port 3 Interrupt Enable  
P3[7]  
W
P3[6]  
W
P3[5]  
W
P3[4]  
W
P3[3]  
W
P3[2]  
W
P3[1]  
W
P3[0]  
W
Document #: 38-08027 Rev. *B  
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Table 11.Possible Port Configurations  
Port Configuration bits  
Pin Interrupt Bit  
Driver Mode  
Resistive  
Interrupt Polarity  
11  
10  
10  
01  
00  
X
0
-
CMOS Output  
Open Drain  
Open Drain  
Open Drain  
disabled  
disabled  
-
1
X
X
+ (default)  
In “Resistive” mode, a 7-kΩ pull-up resistor is conditionally  
enabled for all pins of a GPIO port. The resistor is enabled for  
any pin that has been written as a “1.” The resistor is disabled  
on any pin that has been written as a “0.” An I/O pin will be  
driven high through a 7-kΩ pull-up resistor when a “1” has  
been written to the pin. Or the output pin will be driven LOW,  
with the pull-up disabled, when a “0” has been written to the  
pin. An I/O pin that has been written as a “1” can be used as  
an input pin with an integrated 7-kΩ pull-up resistor. Resistive  
mode selects a negative (falling edge) interrupt polarity on all  
pins that have the GPIO interrupt enabled.  
direction. If a port’s associated Interrupt Mask bits are cleared,  
those port bits are strictly outputs. If the Interrupt Mask bits are  
set then those bits will be open drain inputs. As open drain  
inputs, if their data output values are ‘1’ those port pins will be  
CMOS inputs (HIGH Z output).  
In “Open Drain” mode the internal pull-up resistor and CMOS  
driver (HIGH) are both disabled. An I/O pin that has been  
written as a “1” can be used as either a high-impedance input  
or a three-state output. An I/O pin that has been written as a  
“0” will drive the output LOW. The interrupt polarity for an open  
drain GPIO port can be selected as either positive (rising  
edge) or negative (falling edge).  
In “CMOS” mode, all pins of the GPIO port are outputs that are  
actively driven. The current source and sink capacity are  
roughly the same (symmetric output drive). A CMOS port is not  
a possible source for interrupts.  
During reset, all of the bits in the GPIO Configuration Register  
are written with “0.” This selects the default configuration:  
Open Drain output, positive interrupt polarity for all GPIO  
ports.  
A port configured in CMOS mode has interrupt generation  
disabled, yet the interrupt mask bits serve to control port  
Addr: 0x08  
GPIO Configuration Register  
7
6
5
4
3
2
1
0
Port 3  
Config Bit 1  
Port 3  
Config Bit 0  
Port 2  
Config Bit 1  
Port 2  
Config Bit 0  
Port 1  
Config Bit 1  
Port 1  
Config Bit 0  
Port 0  
Config Bit 1  
Port 0  
Config Bit 0  
W
W
W
W
W
W
W
W
Table 12.GPIO Configuration Register  
DAC Port  
V
CC  
Q1  
Data  
Out  
Latch  
Internal  
Data Bus  
14 KΩ  
DAC Write  
DAC  
I/O Pin  
4 bits  
Isink  
DAC  
Isink  
Register  
ESD  
Internal  
Buffer  
DAC Read  
Interrupt  
Enable  
to Interrupt  
Controller  
Interrupt  
Polarity  
Figure 5. Block Diagram of DAC Port  
Document #: 38-08027 Rev. *B  
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Table 13.DAC Port Data  
Addr: 0x30  
DAC Port Data  
Low current outputs  
0.2 mA to 1.0 mA typical  
High current outputs  
3.2 mA to 16 mA typical  
DAC[7]  
R/W  
DAC[6]  
R/W  
DAC[5]  
R/W  
DAC[4]  
R/W  
DAC[3]  
R/W  
DAC[2]  
R/W  
DAC[1]  
R/W  
DAC[0]  
R/W  
The DAC port provides the CY7C63513C with 8 program-  
mable current sink I/O pins. Writing a “1” to a DAC I/O pin  
disables the output current sink (Isink DAC) and drives the I/O  
pin HIGH through an integrated 14 Kohm resistor. When a “0”  
is written to a DAC I/O pin, the Isink DAC is enabled and the  
pull-up resistor is disabled. A “0” output will cause the Isink  
DAC to sink current to drive the output LOW. The amount of  
sink current for the DAC I/O pin is programmable over 16  
values based on the contents of the DAC Isink Register for that  
output pin. DAC[1:0] are the two high current outputs that are  
programmable from a minimum of 3.2 mA to a maximum of 16  
mA (typical). DAC[7:2] are low current outputs that are  
programmable from a minimum of 0.2 mA to a maximum of 1.0  
mA (typical).  
this feature with an interrupt mask bit for each DAC I/O pin.  
Writing a “1” to a bit in this register enables interrupts from the  
corresponding bit position. Writing a “0” to a bit in the DAC Port  
Interrupt Enable register disables interrupts from the corre-  
sponding bit position. All of the DAC Port Interrupt Enable  
register bits are cleared to “0” during a reset.  
As an additional benefit, the interrupt polarity for each DAC pin  
is programmable with the DAC Port Interrupt Polarity register.  
Writing a “0” to a bit selects negative polarity (falling edge) that  
will cause an interrupt (if enabled) if a falling edge transition  
occurs on the corresponding input pin. Writing a “1” to a bit in  
this register selects positive polarity (rising edge) that will  
cause an interrupt (if enabled) if a rising edge transition occurs  
on the corresponding input pin. All of the DAC Port Interrupt  
Polarity register bits are cleared during a reset.  
When a DAC I/O bit is written as a “1,” the I/O pin is either an  
output pulled high through the 14 Kohm resistor or an input  
with an internal 14 Kohm pull-up resistor. All DAC port data bits  
are set to “1” during reset.  
DAC Isink Registers  
Each DAC I/O pin has an associated DAC Isink register to  
program the output sink current when the output is driven  
LOW. The first Isink register (0x38) controls the current for  
DAC[0], the second (0x39) for DAC[1], and so on until the Isink  
register at 0x3F controls the current to DAC[7].  
DAC Port Interrupts  
A DAC port interrupt can be enabled/disabled for each pin  
individually. The DAC Port Interrupt Enable register provides  
Table 14.DAC Port Interrupt Enable  
Addr: 0x31  
DAC Port Interrupt Enable  
DAC[7]  
DAC[6]  
W
DAC[5]  
W
DAC[4]  
W
DAC[3]  
W
DAC[2]  
W
DAC[1]  
W
DAC[0]  
W
W
Table 15.DAC Port Interrupt Polarity  
Addr: 0x32  
DAC Port Interrupt Polarity  
DAC[7]  
W
DAC[6]  
W
DAC[5]  
W
DAC[4]  
W
DAC[3]  
W
DAC[2]  
W
DAC[1]  
W
DAC[0]  
W
Table 16.DAC Port Isink  
Addr: 0x38-0x3F  
DAC Port Interrupt Polarity  
Reserved  
Isink Value  
Isink[3]  
W
Isink[2]  
W
Isink[1]  
W
Isink[0]  
W
Document #: 38-08027 Rev. *B  
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7. The USB Controller decodes the request and retrieves the  
Device descriptor from the program memory.  
USB Serial Interface Engine (SIE)  
The SIE allows the microcontroller to communicate with the  
USB host. The SIE simplifies the interface between the micro-  
controller and USB by incorporating hardware that handles the  
following USB bus activity independently of the microcon-  
troller:  
8. The host performs a control read sequence and the USB  
Controller responds by sending its Device descriptor over  
the USB bus.  
9. The host generates control reads to the USB Controller to  
request the Configuration and Report descriptors.  
• Bit stuffing/unstuffing  
• Checksum generation/checking  
• ACK/NAK  
10.The USB Controller retrieves the descriptors from its  
program space and returns the data to the host over the  
USB.  
• Token type identification  
• Address checking  
PS/2 Operation  
PS/2 operation is possible with the CY7C63413C/513C/613C  
series through the use of firmware and several operating  
modes. The first enabling feature:  
Firmware is required to handle the rest of the USB interface  
with the following tasks:  
1. USB Bus reset on D+ and D− is an interrupt that can be  
• Coordinate enumeration by responding to set-up packets  
• Fill and empty the FIFOs  
disabled;  
2. USB traffic can be disabled via bit 7 of the USB register;  
• Suspend/Resume coordination  
3. D+ and D− can be monitored and driven via firmware as  
independent port bits.  
• Verify and select Data toggle values  
USB Enumeration  
Bits 5 and 4 of the Upstream Status and Control register are  
directly connected to the D+ and D− USB pins of the  
CY7C63413C/513C/613C. These pins constantly monitor the  
levels of these signals with CMOS input thresholds. Firmware  
can poll and decode these signals as PS/2 clock and data.  
The enumeration sequence is shown below:  
1. The host computer sends a Setup packet followed by a  
Data packet to USB address 0 requesting the Device de-  
scriptor.  
Bits [2:0] defaults to ‘000’ at reset which allows the USB SIE  
to control output on D+ and D−. Firmware can override the SIE  
and directly control the state of these pins via these 3 control  
bits. Since PS/2 is an open drain signaling protocol, these  
modes allow all 4 PS/2 states to be generated on the D+ and  
D− pins  
2. The USB Controller decodes the request and retrieves its  
Device descriptor from the program memory space.  
3. The host computer performs a control read sequence and  
the USB Controller responds by sending the Device  
descriptor over the USB bus.  
4. After receiving the descriptor, the host computer sends a  
Setup packet followed by a Data packet to address 0  
assigning a new USB address to the device.  
USB Port Status and Control  
USB status and control is regulated by the USB Status and  
Control Register located at I/O address 0x1F as shown in  
Figure 17. This is a read/write register. All reserved bits must  
be written to zero. All bits in the register are cleared during  
reset.  
5. The USB Controller stores the new address in its USB  
Device Address Register after the no-data control  
sequence is complete.  
6. The host sends a request for the Device descriptor using  
the new USB address.  
Table 17.USB Status and Control Register  
Addr:0x1F  
USB Status and Control Register  
7
6
5
4
3
2
1
0
Reserved  
Reserved  
D+  
D–  
Bus Activity  
Control  
Bit 2  
Control  
Bit 1  
Control  
Bit 0  
R
R
R/W  
R/W  
R/W  
R/W  
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The Bus Activity bit is a “sticky” bit that indicates if any non-idle  
USB event has occurred on the USB bus. The user firmware  
should check and clear this bit periodically to detect any loss  
of bus activity. Writing a “0” to the Bus Activity bit clears it while  
writing a “1” preserves the current value. In other words, the  
firmware can clear the Bus Activity bit, but only the SIE can set  
it. The 1.024-ms timer interrupt service routine is normally  
used to check and clear the Bus Activity bit. The following table  
shows how the control bits are encoded for this register.  
are cleared during a reset, setting the USB device address to  
zero and marking this address as disabled. Figure 18 shows  
the format of the USB Address Register.  
Bit 7 (Device Address Enable) in the USB Device Address  
Register must be set by firmware before the serial interface  
engine (SIE) will respond to USB traffic to this address. The  
Device Address in bits [6:0] must be set by firmware during the  
USB enumeration process to an address assigned by the USB  
host that does not equal zero. This register is cleared by a  
hardware reset or the USB bus reset.  
Control  
Bits  
000  
001  
010  
011  
100  
101  
110  
111  
Control Action  
Device Endpoints (3)  
Not forcing (SIE controls driver)  
Force K (D+ HIGH, D– LOW)  
Force J (D+ LOW, D– HIGH)  
Force SE0 (D+ LOW, D– LOW)  
Force SE0 (D− LOW, D+ LOW)  
Force D− LOW, D+ HiZ  
The USB controller communicates with the host using  
dedicated FIFOs, one per endpoint. Each endpoint FIFO is  
implemented as 8 bytes of dedicated SRAM. There are three  
endpoints defined for Device “A” that are labeled “EPA0,”  
“EPA1,” and EPA2.”  
All USB devices are required to have an endpoint number 0  
(EPA0) that is used to initialize and control the USB device.  
End Point 0 provides access to the device configuration infor-  
mation and allows generic USB status and control accesses.  
End Point 0 is bidirectional as the USB controller can both  
receive and transmit data.  
Force D− HiZ, D+ LOW  
Force D− HiZ, D+ HiZ  
The endpoint mode registers are cleared during reset. The  
EPA0 endpoint mode register uses the format shown in Table  
19.  
USB Device  
USB Device Address A includes three endpoints: EPA0, EPA1,  
and EPA2. End Point 0 (EPA0) allows the USB host to  
recognize, set up, and control the device. In particular, EPA0  
is used to receive and transmit control (including set-up)  
packets.  
Bits[7:5] in the endpoint 0 mode registers (EPA0) are “sticky”  
status bits that are set by the SIE to report the type of token  
that was most recently received. The sticky bits must be  
cleared by firmware as part of the USB processing.  
The endpoint mode registers for EPA1 and EPA2 do not use  
USB Ports  
bits [7:5] as shown in Table 20.  
The USB Controller provides one USB device address with  
three endpoints. The USB Device Address Register contents  
Table 18.USB Device Address Register  
Addr:0x10  
USB Device Address Register  
Device  
Address  
Enable  
Device  
Address  
Bit 6  
Device  
Address  
Bit 5  
Device  
Address  
Bit 4  
Device  
Address  
Bit 3  
Device  
Address  
Bit 2  
Device  
Address  
Bit 1  
Device  
Address  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 19.USB Device EPA0, Mode Register  
Addr:0x12  
USB Device EPA0, Mode Register  
Endpoint 0  
Set-up  
Received  
Endpoint 0  
In  
Received  
Endpoint 0  
Out  
Received  
Acknowledge  
Mode  
Bit 3  
Mode  
Bit 2  
Mode  
Bit 1  
Mode  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 20.USB Device Endpoint Mode Register  
Addr: 0x14, 0x16 USB Device Endpoint Mode Register  
Reserved  
Reserved  
Reserved  
Acknowledge  
Mode  
Bit 3  
Mode  
Bit 2  
Mode  
Bit 1  
Mode  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
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The ‘Acknowledge’ bit is set whenever the SIE engages in a  
transaction that completes with an ‘ACK’ packet.  
While the ‘set-up’ bit is set, the CPU cannot write to the DMA  
buffers at memory locations 0xE0 through 0xE7 and 0xF8  
through 0xFF. This prevents an incoming set-up transaction  
from conflicting with a previous In data buffer filling operation  
by firmware.  
The ‘set-up’ PID status (bit[7]) is forced HIGH from the start of  
the data packet phase of the set-up transaction, until the start  
of the ACK packet returned by the SIE. The CPU is prevented  
from clearing this bit during this interval, and subsequently  
until the CPU first does an IORD to this endpoint 0 mode  
register.  
The mode bits (bits [3:0]) in an Endpoint Mode Register control  
how the endpoint responds to USB bus traffic. The mode bit  
encoding is shown in Section .  
Bits[6:0] of the endpoint 0 mode register are locked from CPU  
IOWR operations only if the SIE has updated one of these bits,  
which the SIE does only at the end of a packet transaction (set-  
up... Data... ACK, or Out... Data... ACK, or In... Data... ACK).  
The CPU can unlock these bits by doing a subsequent I/O read  
of this register.  
The format of the endpoint Device counter registers is shown  
in Table 21.  
Bits 0 to 3 indicate the number of data bytes to be transmitted  
during an IN packet, valid values are 0 to 8 inclusive. Data  
Valid bit 6 is used for OUT and set-up tokens only. Data 0/1  
Toggle bit 7 selects the DATA packet’s toggle state: 0 for  
DATA0, 1 for DATA1.  
Firmware must do an IORD after an IOWR to an endpoint 0  
register to verify that the contents have changed and that the  
SIE has not updated these values.  
Table 21.USB Device Counter Registers  
Addr: 0x11, 0x13, 0x15  
USB Device Counter Registers  
Data 0/1  
Toggle  
Data Valid  
Reserved  
R/W  
Reserved  
Byte count  
Bit 3  
Byte count  
Bit 2  
Byte count  
Bit 1  
Byte count  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
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upper 4 bits into a temporary register. When the firmware  
reads the upper 4 bits of the timer, it is actually reading the  
count stored in the temporary register. The effect of this logic  
is to ensure a stable 12-bit timer value can be read, even when  
the two reads are separated in time.  
12-bit Free-running Timer  
The 12-bit timer provides two interrupts (128 µs and 1.024 ms)  
and allows the firmware to directly time events that are up to  
4 ms in duration. The lower 8 bits of the timer can be read  
directly by the firmware. Reading the lower 8 bits latches the  
Timer (LSB)  
Table 22.Timer Register  
Addr: 0x24  
Timer Register (LSB)  
Timer  
Bit 7  
Timer  
Bit 6  
Timer  
Bit 5  
Timer  
Bit 4  
Timer  
Bit 3  
Timer  
Bit 2  
Timer  
Bit 1  
Timer  
Bit 0  
R
R
R
R
R
R
R
R
Timer (MSB)  
Table 23.Timer Register  
Addr: 0x25  
Timer Register (MSB)  
Reserved  
Reserved  
Reserved  
Reserved  
Timer  
Bit 11  
Timer  
Bit 10  
Timer  
Bit 9  
Timer  
Bit 8  
R
R
R
R
1.024-ms interrupt  
128-µs interrupt  
11  
L3  
10  
L2  
9
8
7
6
5
4
3
2
1
0
1-MHz clock  
L1  
L0  
D3 D2  
D1 D0  
D7 D6  
D5 D4  
D3 D2  
D1 D0  
To Timer Register  
8
Figure 6. Timer Block Diagram  
Processor Status and Control Register  
Table 24.Processor Status and Control Register  
Addr: 0xFF  
Processor Status and Control Register  
POR Default: 0x0101  
WDC Reset: 0x41  
7
6
5
4
3
2
1
0
IRQ  
Pending  
Watch Dog  
Reset  
USB Bus  
Reset  
Power-on  
Reset  
Suspend,Wait  
for Interrupt  
Interrupt  
Mask  
Single Step  
Run  
R
R/W  
R/W  
R/W  
R/W  
R
R/W  
R/W  
The “Run” (bit 0) is manipulated by the HALT instruction. When  
Halt is executed, the processor clears the run bit and halts at  
the end of the current instruction. The processor remains  
halted until a reset (Power On or Watch Dog). Notice, when  
writing to the processor status and control register, the run bit  
should always be written as a “1.”  
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The “Single Step” (bit 1) is provided to support a hardware  
debugger. When single step is set, the processor will execute  
one instruction and halt (clear the run bit). This bit must be  
cleared for normal operation.  
During Power-on Reset, the Processor Status and Control  
Register is set to 00010001, which indicates a Power-on Reset  
(bit 4 set) has occurred and no interrupts are pending (bit 7  
clear) yet.  
The “Interrupt Mask” (bit 2) shows whether interrupts are  
enabled or disabled. The firmware has no direct control over  
this bit as writing a zero or one to this bit position will have no  
effect on interrupts. Instructions DI, EI, and RETI manipulate  
the internal hardware that controls the state of the interrupt  
mask bit in the Processor Status and Control Register.  
During a Watch Dog Reset, the Processor Status and Control  
Register is set to 01000001, which indicates a Watch Dog  
Reset (bit 6 set) has occurred and no interrupts are pending  
(bit 7 clear) yet.  
Interrupts  
Writing a “1” to “Suspend, Wait for Interrupts” (bit 3) will halt  
the processor and cause the microcontroller to enter the  
“suspend” mode that significantly reduces power  
consumption. A pending interrupt or bus activity will cause the  
device to come out of suspend. After coming out of suspend,  
the device will resume firmware execution at the instruction  
following the IOWR which put the part into suspend. An IOWR  
that attempts to put the part into suspend will be ignored if  
either bus activity or an interrupt is pending.  
All interrupts are maskable by the Global Interrupt Enable  
Register and the USB End Point Interrupt Enable Register.  
Writing a “1” to a bit position enables the interrupt associated  
with that bit position. During a reset, the contents the Global  
Interrupt Enable Register and USB End Point Interrupt Enable  
Register are cleared, effectively disabling all interrupts.  
Pending interrupt requests are recognized during the last clock  
cycle of the current instruction. When servicing an interrupt,  
the hardware will first disable all interrupts by clearing the  
Interrupt Enable bit in the Processor Status and Control  
Register. Next, the interrupt latch of the current interrupt is  
cleared. This is followed by a CALL instruction to the ROM  
address associated with the interrupt being serviced (i.e., the  
Interrupt Vector). The instruction in the interrupt table is  
typically a JMP instruction to the address of the Interrupt  
Service Routine (ISR). The user can re-enable interrupts in the  
interrupt service routine by executing an EI instruction. Inter-  
rupts can be nested to a level limited only by the available  
stack space.  
The “Power-on Reset” (bit 4) is only set to “1” during a power  
on reset. The firmware can check bits 4 and 6 in the reset  
handler to determine whether a reset was caused by a Power  
On condition or a Watch Dog Timeout. PORS is used to  
determine suspend start-up timer value of 128 µs or 96 ms.  
The “USB Bus Reset” (bit 5) will occur when a USB bus reset  
is received. The USB Bus Reset is a singled-ended zero (SE0)  
that lasts more than 8 microseconds. An SE0 is defined as the  
condition in which both the D+ line and the D– line are LOW  
at the same time. When the SIE detects this condition, the  
USB Bus Reset bit is set in the Processor Status and Control  
register and an USB Bus Reset interrupt is generated. Please  
note this is an interrupt to the microcontroller and does not  
actually reset the processor.  
The Program Counter value as well as the Carry and Zero  
flags (CF, ZF) are automatically stored onto the Program Stack  
by the CALL instruction as part of the interrupt acknowledge  
process. The user firmware is responsible for insuring that the  
processor state is preserved and restored during an interrupt.  
The PUSH A instruction should be used as the first command  
in the ISR to save the accumulator value and the POP A  
instruction should be used just before the RETI instruction to  
restore the accumulator value. The program counter CF and  
ZF are restored and interrupts are enabled when the RETI  
instruction is executed.  
The “Watch Dog Reset” (bit 6) is set during a reset initiated by  
the Watch Dog Timer. This indicates the Watch Dog Timer  
went for more than 8 ms between watch dog clears.  
The “IRQ Pending” (bit 7) indicates one or more of the inter-  
rupts has been recognized as active. The interrupt  
acknowledge sequence should clear this bit until the next  
interrupt is detected.  
Table 25.Global Interrupt Enable Register  
Addr: 0x20  
Global Interrupt Enable Register  
7
6
5
4
3
2
1
0
Reserved  
Reserved  
GPIO  
Interrupt  
Enable  
DAC  
Interrupt  
Enable  
Reserved  
1.024-ms  
Interrupt  
Enable  
128-µsec  
Interrupt  
Enable  
USB Bus RST  
Interrupt  
Enable  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 26.USB End Point Interrupt Enable Register  
Addr: 0x21 USB End Point Interrupt Enable Register  
7
6
5
4
3
2
1
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
EPA2  
Interrupt  
Enable  
EPA1  
Interrupt  
Enable  
EPA0  
Interrupt  
Enable  
R/W  
R/W  
R/W  
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Interrupt Vectors  
0x0000—which corresponds to the first entry in the Interrupt  
Vector Table. Because the JMP instruction is 2 bytes long, the  
interrupt vectors occupy 2 bytes.  
The Interrupt Vectors supported by the USB Controller are  
listed in Table 27. Although Reset is not an interrupt, per se,  
the first instruction executed after a reset is at PROM address  
Table 27.Interrupt Vector Assignments  
Interrupt Vector Number  
ROM Address  
0x0000  
Function  
Execution after Reset begins here  
USB Bus Reset interrupt  
128-µs timer interrupt  
1.024-ms timer interrupt  
USB Address A Endpoint 0 interrupt  
USB Address A Endpoint 1 interrupt  
USB Address A Endpoint 2 interrupt  
Reserved  
not applicable  
1
2
0x0002  
0x0004  
0x0006  
0x0008  
0x000A  
0x000C  
0x000E  
0x0010  
0x0012  
0x0014  
0x0016  
0x0018  
3
4
5
6
7
8
Reserved  
9
Reserved  
10  
11  
12  
DAC interrupt  
GPIO interrupt  
Reserved  
Interrupt Latency  
DAC Interrupt  
Interrupt latency can be calculated from the following  
equation:  
Each DAC I/O pin can generate an interrupt, if enabled.The  
interrupt polarity for each DAC I/O pin is programmable. A  
positive polarity is a rising edge input while a negative polarity  
is a falling edge input. All of the DAC pins share a single  
interrupt vector, which means the firmware will need to read  
the DAC port to determine which pin or pins caused an  
interrupt.  
Interrupt Latency =(Number of clock cycles remaining in the  
current instruction)  
+ (10 clock cycles for the CALL instruction)  
+ (5 clock cycles for the JMP instruction)  
For example, if a 5 clock cycle instruction such as JC is being  
executed when an interrupt occurs, the first instruction of the  
Interrupt Service Routine will execute a min. of 16 clocks  
(1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is  
issued. Remember that the interrupt latches are sampled at  
the rising edge of the last clock cycle in the current instruction.  
Please note that if one DAC pin triggered an interrupt, no other  
DAC pins can cause a DAC interrupt until that pin has returned  
to its inactive (non-trigger) state or the corresponding interrupt  
enable bit is cleared. The USB Controller does not assign  
interrupt priority to different DAC pins and the DAC Interrupt  
Enable Register is not cleared during the interrupt  
acknowledge process.  
USB Bus Reset Interrupt  
The USB Bus Reset interrupt is asserted when a USB bus  
reset condition is detected. A USB bus reset is indicated by a  
single ended zero (SE0) on the upstream port for more than 8  
microseconds.  
GPIO Interrupt  
Each of the 32 GPIO pins can generate an interrupt, if enabled.  
The interrupt polarity can be programmed for each GPIO port  
as part of the GPIO configuration. All of the GPIO pins share  
a single interrupt vector, which means the firmware will need  
to read the GPIO ports with enabled interrupts to determine  
which pin or pins caused an interrupt.  
Timer Interrupt  
There are two timer interrupts: the 128-µs interrupt and the  
1.024-ms interrupt. The user should disable both timer inter-  
rupts before going into the suspend mode to avoid possible  
conflicts between servicing the interrupts first or the suspend  
request first.  
Please note that if one port pin triggered an interrupt, no other  
port pins can cause a GPIO interrupt until that port pin has  
returned to its inactive (non-trigger) state or its corresponding  
port interrupt enable bit is cleared. The USB Controller does  
not assign interrupt priority to different port pins and the Port  
Interrupt Enable Registers are not cleared during the interrupt  
acknowledge process.  
USB Endpoint Interrupts  
There are three USB endpoint interrupts, one per endpoint.  
The USB endpoints interrupt after the either the USB host or  
the USB controller sends a packet to the USB.  
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Truth Tables  
Table 28.USB Register Mode Encoding  
Mode  
Encoding  
0000  
Setup  
ignore  
accept  
In  
Out  
Comments  
Disable  
Nak In/Out  
ignore  
NAK  
ignore Ignore all USB traffic to this endpoint  
NAK  
Forced from Set-up on Control endpoint, from modes other  
than 0000  
0001  
0010  
0011  
0100  
Status Out Only  
Stall In/Out  
accept  
accept  
accept  
ignore  
stall  
stall  
check For Control endpoints  
stall For Control endpoints  
Ignore In/Out  
Isochronous Out  
ignore  
ignore  
ignore For Control endpoints  
always Available to low speed devices, future USB spec  
enhancements  
0101  
0110  
Status In Only  
Isochronous In  
accept  
ignore  
TX 0  
stall  
For Control Endpoints  
TX cnt  
ignore Available to low speed devices, future USB spec  
enhancements  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Nak Out  
ignore  
ignore  
accept  
accept  
ignore  
ignore  
accept  
accept  
ignore  
ignore  
TX 0  
NAK  
ACK  
NAK  
ACK  
An ACK from mode 1001 --> 1000  
Ack Out  
This mode is changed by SIE on issuance of ACK --> 1000  
An ACK from mode 1011 --> 1010  
Nak Out - Status In  
Ack Out - Status In  
Nak In  
TX 0  
This mode is changed by SIE on issuance of ACK --> 1010  
NAK  
ignore An ACK from mode 1101 --> 1100  
Ack In  
TX cnt  
NAK  
ignore This mode is changed by SIE on issuance of ACK --> 1100  
check An ACK from mode 1111 --> 1110 NAck In - Status Out  
Check This mode is changed by SIE on issuance of ACK -->1110  
Nak In - Status Out  
Ack In - Status Out  
TX cnt  
The ‘In’ column represents the SIE’s response to the token  
type.  
A Control endpoint has three extra status bits for PID (Setup,  
In and Out), but must be placed in the correct mode to function  
as such. Also a non-Control endpoint can be made to act as a  
Control endpoint if it is placed in a non appropriate mode.  
A disabled endpoint will remain such until firmware changes it,  
and all endpoints reset to disabled.  
A ‘check’ on an Out token during a Status transaction checks  
to see that the Out is of zero length and has a Data Toggle  
(DTOG) of 1.  
Any Setup packet to an enabled and accepting endpoint will  
be changed by the SIE to 0001 (NAKing). Any mode which  
indicates the acceptance of a Setup will acknowledge it.  
Most modes that control transactions involving an ending ACK  
will be changed by the SIE to a corresponding mode which  
NAKs follow on packets.  
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Figure 7. Decode table forTable 29: “Details of Modes for Differing Traffic Conditions”  
Properties of incoming packet  
Encoding  
Status bits  
What the SIE does to Mode bits  
PID Status bits Interrupt?  
End Point  
Mode  
End Point  
Mode  
3
Set-  
up  
Re-  
sponse  
In  
t
2
1
0
Token  
Setup  
In  
count  
buffer  
dval  
DTOG  
DVAL  
COUNT  
In  
Out  
ACK  
3
2
1
0
Out  
The validity of the received data  
The quality status of the DMA buffer  
Acknowledge phase completed  
The number of received bytes  
TX0: transmit 0-length packet  
Legend:  
UC: unchanged  
x: don’t care  
TX: transmit  
RX: receive  
available for Control endpoint only  
The response of the SIE can be summarized as follows:  
The Setup PID status is updated at the beginning of the Data  
packet phase.  
1. the SIE will only respond to valid transactions, and will ig-  
nore non-valid ones;  
The entire EndPoint 0 mode and the Count register are locked  
to CPU writes at the end of any transaction in which an ACK  
is transferred. These registers are only unlocked upon a CPU  
read of these registers, and only if that read happens after the  
transaction completes. This represents about a 1-µs window  
to which to the CPU is locked from register writes to these USB  
registers. Normally the firmware does a register read at the  
beginning of the ISR to unlock and get the mode register infor-  
mation. The interlock on the Mode and Count registers  
ensures that the firmware recognizes the changes that the SIE  
might have made during the previous transaction.  
2. the SIE will generate IRQ when a valid transaction is  
completed or when the DMA buffer is corrupted  
3. an incoming Data packet is valid if the count is <= 10 (CRC  
inclusive) and passes all error checking;  
4. a Setup will be ignored by all non-Control endpoints (in  
appropriate modes);  
5. an In will be ignored by an Out configured endpoint and vice  
versa.  
The In and Out PID status is updated at the end of a trans-  
action.  
Document #: 38-08027 Rev. *B  
Page 22 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Table 29.Details of Modes for Differing Traffic Conditions  
End Point Mode  
PID  
Set End Point Mode  
3
2
1
0
token  
count buffer  
dval  
DTOG  
DVAL  
COUNT Setup In  
Out  
ACK  
3
2
1
0
response int  
Setup Packet (if accepting)  
See Table 28 Setup  
See Table 28 Setup  
See Table 28 Setup  
Disabled  
<= 10  
> 10  
x
data  
junk  
junk  
valid  
updates  
1
updates  
1
1
1
UC  
UC  
UC  
UC  
UC  
UC  
1
0
0
0
1
ACK  
yes  
yes  
yes  
x
updates updates updates  
UC  
UC  
NoChange  
NoChange  
ignore  
ignore  
invalid  
updates  
UC  
0
updates  
UC  
0
0
0
0
x
x
UC  
x
UC  
UC  
UC  
UC  
UC  
NoChange  
ignore  
no  
Nak In/Out  
0
0
0
0
0
0
1
1
Out  
In  
x
x
UC  
UC  
x
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
UC  
UC  
NoChange  
NoChange  
NAK  
NAK  
yes  
yes  
UC  
Ignore In/Out  
0
0
1
1
0
0
0
0
Out  
In  
x
x
UC  
UC  
x
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
NoChange  
NoChange  
ignore  
ignore  
no  
no  
Stall In/Out  
0
0
0
0
1
1
1
1
Out  
In  
x
x
UC  
UC  
x
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
UC  
UC  
NoChange  
NoChange  
Stall  
Stall  
yes  
yes  
UC  
Control Write  
Normal Out/premature status In  
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
Out  
Out  
Out  
In  
<= 10  
data  
junk  
junk  
UC  
valid  
updates  
1
updates  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
1
1
1
0
1
0
ACK  
ignore  
ignore  
TX 0  
yes  
yes  
yes  
yes  
> 10  
x
invalid  
x
updates updates updates  
UC  
UC  
1
NoChange  
NoChange  
NoChange  
x
x
updates  
UC  
0
updates  
UC  
1
UC  
UC  
NAK Out/premature status In  
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Out  
Out  
Out  
In  
<= 10  
UC  
UC  
UC  
UC  
valid  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
UC  
UC  
UC  
1
NoChange  
NoChange  
NoChange  
NoChange  
NAK  
ignore  
ignore  
TX 0  
yes  
no  
> 10  
x
invalid  
x
UC  
UC  
UC  
x
x
no  
yes  
Status In/extra Out  
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Out  
Out  
Out  
In  
<= 10  
UC  
UC  
UC  
UC  
valid  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
UC  
UC  
UC  
1
0
0
1
1
Stall  
ignore  
ignore  
TX 0  
yes  
no  
> 10  
x
invalid  
x
UC  
UC  
UC  
NoChange  
NoChange  
NoChange  
x
x
no  
yes  
Control Read  
Normal In/premature status Out  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Out  
Out  
Out  
Out  
Out  
In  
2
2
UC  
UC  
UC  
UC  
UC  
UC  
valid  
valid  
valid  
x
1
0
1
1
updates  
updates  
updates  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
1
1
NoChange  
ACK  
Stall  
yes  
yes  
yes  
no  
UC  
UC  
UC  
UC  
1
0
0
0
0
1
1
1
1
!=2  
> 10  
x
updates  
UC  
1
1
Stall  
UC  
UC  
UC  
UC  
UC  
UC  
NoChange  
NoChange  
ignore  
ignore  
invalid  
x
UC  
UC  
no  
x
UC  
UC  
1
1
1
0
ACK (back) yes  
Nak In/premature status Out  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Out  
Out  
Out  
Out  
Out  
In  
2
2
UC  
UC  
UC  
UC  
UC  
UC  
valid  
valid  
valid  
x
1
0
1
1
updates  
updates  
updates  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
1
1
NoChange  
ACK  
Stall  
yes  
yes  
yes  
no  
UC  
UC  
UC  
UC  
UC  
0
0
0
0
1
1
1
1
!=2  
> 10  
x
updates  
UC  
1
1
Stall  
UC  
UC  
UC  
UC  
UC  
UC  
NoChange  
NoChange  
NoChange  
ignore  
ignore  
NAK  
invalid  
x
UC  
UC  
no  
x
UC  
UC  
yes  
Status Out/extra In  
0
0
0
0
1
1
0
0
Out  
Out  
2
2
UC  
UC  
valid  
valid  
1
0
1
1
updates  
updates  
UC  
UC  
UC  
UC  
1
1
1
NoChange  
ACK  
Stall  
yes  
yes  
UC  
0
0
1
1
Document #: 38-08027 Rev. *B  
Page 23 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Table 29.Details of Modes for Differing Traffic Conditions (continued)  
End Point Mode PID  
Set End Point Mode  
3
2
1
0
token  
Out  
Out  
Out  
In  
count buffer  
dval  
valid  
DTOG  
updates  
UC  
DVAL  
1
COUNT Setup In  
Out  
1
ACK  
UC  
3
2
1
0
response int  
0
0
1
0
!=2  
> 10  
x
UC  
UC  
UC  
UC  
updates  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
0
0
1
1
Stall  
ignore  
ignore  
Stall  
yes  
no  
0
0
0
0
0
0
1
1
1
0
0
0
x
invalid  
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC UC UC UC  
UC UC UC UC  
UC  
UC  
UC  
no  
x
UC  
UC  
UC  
0
1
0
1
1
0
yes  
Out endpoint  
Normal Out/erroneous In  
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Out  
Out  
Out  
In  
<= 10  
data  
junk  
junk  
UC  
valid  
updates  
1
updates  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
1
1
0
0
ACK  
yes  
yes  
yes  
no  
> 10  
x
invalid  
x
updates updates updates  
UC  
UC  
UC  
NoChange  
NoChange  
NoChange  
ignore  
ignore  
ignore  
x
x
updates  
UC  
0
updates  
UC  
1
UC  
UC  
NAK Out/erroneous In  
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Out  
Out  
Out  
In  
<= 10  
UC  
UC  
UC  
UC  
valid  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
UC  
UC  
UC  
UC  
NoChange  
NoChange  
NoChange  
NoChange  
NAK  
yes  
no  
no  
no  
> 10  
x
invalid  
x
UC  
UC  
UC  
ignore  
ignore  
ignore  
x
x
Isochronous endpoint (Out)  
0
0
1
1
0
0
1
1
Out  
In  
x
x
updates updates updates updates updates  
UC  
UC  
UC  
UC  
1
1
NoChange  
NoChange  
RX  
yes  
no  
UC  
x
UC  
UC  
UC  
UC  
UC  
ignore  
In endpoint  
Normal In/erroneous Out  
1
1
1
1
0
0
1
1
Out  
In  
x
x
UC  
UC  
x
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
UC  
UC  
UC  
1
NoChange  
ignore  
no  
1
1
0
0
ACK (back) yes  
NAK In/erroneous Out  
1
1
1
1
0
0
0
0
Out  
In  
x
x
UC  
UC  
x
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
UC  
UC  
UC  
UC  
NoChange  
NoChange  
ignore  
NAK  
no  
yes  
Isochronous endpoint (In)  
0
0
1
1
1
1
1
1
Out  
In  
x
x
UC  
UC  
x
x
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
UC  
1
UC  
UC  
UC  
UC  
NoChange  
NoChange  
ignore  
TX  
no  
yes  
Document #: 38-08027 Rev. *B  
Page 24 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Absolute Maximum Ratings  
Storage Temperature ..........................................................................................................................................–65°C to +150°C  
Ambient Temperature with Power Applied...............................................................................................................–0°C to +70°C  
Supply Voltage on V relative to V ....................................................................................................................–0.5V to +7.0V  
CC  
SS  
DC Input Voltage........................................................................................................................................... –0.5V to +V +0.5V  
CC  
DC Voltage Applied to Outputs in High Z State............................................................................................ –0.5V to + V +0.5V  
CC  
Max. Output Current into Port 0,1,2,3 and DAC[1:0] Pins ................................................................................................... 60 mA  
Max. Output Current into DAC[7:2] Pins............................................................................................................................. 10 mA  
Power Dissipation ............................................................................................................................................................. 300 mW  
[3]  
Static Discharge Voltage ............................................................................................................................................... > 2000V  
Latch-up Current ........................................................................................................................................................... > 200 mA  
DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C  
Parameter  
Min.  
Max.  
Unit  
Conditions  
General  
V
Operating Voltage  
Operating Voltage  
4.0  
5.5  
5.25  
40  
V
V
Non USB activity (note 4)  
USB activity (note 5)  
CC (1)  
CC (2)  
CC1  
V
4.35  
I
I
I
V
V
Operating Supply Current  
= 4.35V  
mA  
mA  
µA  
V
V
= 5.5V  
CC  
CC  
CC  
15  
CC2  
Supply Current - Suspend Mode  
Programming Voltage (disabled)  
Resonator Start-up Interval  
Internal Timer #1 Interrupt Period  
Internal Timer #2 Interrupt Period  
Watch Dog Timer Period  
30  
Oscillator off, D– > Voh min  
V = 5.0V, ceramic resonator  
CC  
SB1  
V
T
–0.4  
128  
0.4  
256  
128  
PP  
µs  
start  
int1  
int2  
watch  
il  
t
t
t
I
I
µs  
1.024 1.024  
ms  
ms  
µA  
mA  
8.192 14.33  
Input Leakage Current  
1
Any pin  
Max I IO Sink Current  
60  
Cumulative across all ports (note 6)  
sm  
SS  
Power-On Reset  
t
V
Reset Slew  
0.001  
2.8  
200  
ms  
Linear ramp: 0 to 4.35V (notes 7,8)  
15k ± 5% ohms to Gnd (note 5)  
vccs  
CC  
USB Interface  
V
Static Output HIGH  
3.6  
0.3  
V
V
oh  
V
Static Output LOW  
ol  
V
V
V
Differential Input Sensitivity  
Differential Input Common Mode Range  
Single-Ended Receiver Threshold  
Transceiver Capacitance  
0.2  
0.8  
0.8  
V
|(D+)–(D–)|  
9-1  
di  
2.5  
2.0  
20  
V
cm  
se  
V
C
I
pF  
µA  
kΩ  
kΩ  
kΩ  
in  
Hi-Z State Data Line Leakage  
–10  
10  
0 V < V <3.3 V  
lo  
in  
R
Bus Pull-up Resistance (V option)  
7.35K  
7.65  
7.5 kΩ ± 2% to V  
pu  
CC  
CC  
R
Bus Pull-up Resistance (Ext. 3.3V option)  
Bus Pull-down Resistance  
1.425 1.575  
14.25 15.75  
1.5 kΩ ± 5% to 3.0–3.6V  
pu  
R
15 kΩ ± 5%  
pd  
General Purpose I/O Interface  
R
Pull-up Resistance  
4.9K  
45%  
9.1K  
65%  
Ohms  
up  
V
Input Threshold Voltage  
V
All ports, LOW to HIGH edge  
ith  
CC  
Notes:  
3. Qualified with JEDEC EIA/JESD22-A114-B test method.  
4. Functionality is guaranteed of the V range, except USB transmitter and DACs.  
CC (1)  
5. USB transmitter functionality is guaranteed over the V  
range, as well as DAC outputs.  
CC (2)  
6. Total current cumulative across all Port pins flowing to V is limited to minimize Ground-Drop noise effects.  
SS  
7. Port 3 bit 7 controls whether the parts goes into suspend after a POR event or waits 128 ms to begin running.  
8. POR will re-occur whenever V drops to approximately 2.5V.  
CC  
Document #: 38-08027 Rev. *B  
Page 25 of 32  
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CY7C63513C  
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DC Characteristics Fosc = 6 MHz; Operating Temperature = 0 to 70°C (continued)  
Parameter  
Input Hysteresis Voltage  
Min.  
6%  
7.2  
3.5  
1.4  
Max.  
12%  
16.5  
10.6  
7.5  
Unit  
Conditions  
V
V
All ports, HIGH to LOW edge  
Port 3, Vout = 1.0V (note 4)  
H
CC  
I
I
I
Sink Current  
Sink Current  
Source Current  
mA  
mA  
mA  
ol  
Port 0,1,2, Vout = 2.0V (note 4)  
Voh = 2.4V (all ports 0,1,2,3) (note 4)  
ol  
oh  
DAC Interface  
R
Pull-up Resistance  
8.0K  
0.1  
0.5  
1.6  
8
20.0K  
0.3  
1.5  
4.8  
24  
Ohms (note 14)  
up  
[15]  
[15]  
[15]  
[15]  
I
I
I
I
I
I
t
DAC[7:2] Sink Current (0)  
DAC[7:2] Sink Current (F)  
DAC[1:0] Sink Current (0)  
DAC[1:0] Sink Current (F)  
mA  
mA  
mA  
mA  
Vout = 2.0 VDC (note 5)  
sink0(0)  
sink0(F)  
sink1(0)  
sink1(F)  
range  
lin  
Vout = 2.0 DC (note 5)  
Vout = 2.0 VDC (note 5)  
Vout = 2.0 VDC (note 5)  
Vout = 2.0 VDC (notes 5,12)  
Any pin (note 10)  
Programmed Isink Ratio: max/min  
Differential Nonlinearity  
4
6
0.5  
0.8  
21  
lsb  
Current Sink Response Time  
Tracking Ratio DAC[1:0] to DAC[7:2]  
µs  
Full scale transition  
sink  
T
14  
Vout = 2.0V (note 11)  
ratio  
Switching Characteristics  
Parameter  
Clock  
Description  
Min.  
Max.  
Unit  
Conditions  
t
t
t
Input Clock Cycle Time  
Clock HIGH Time  
Clock LOW Time  
165.0  
168.3  
ns  
ns  
ns  
CYC  
CH  
0.45 t  
CYC  
0.45 t  
CL  
CYC  
USB Driver Characteristics  
[5, 9]  
t
t
Transition Rise Time  
75  
75  
ns  
ns  
ns  
ns  
%
V
CLoad = 50 pF  
r
5, 9]  
Transition Rise Time  
300  
CLoad = 600 pF  
r
[5, 9]  
t
Transition Fall Time  
CLoad = 50 pF  
f
[5, 9]  
t
t
Transition Fall Time  
300  
125  
2.0  
CLoad = 600 pF  
f
[5, 9]  
Rise/Fall Time Matching  
Output Signal Crossover Voltage  
80  
t /t  
rfm  
r f  
V
1.3  
Notes 5 and 9  
crs  
USB Data Timing  
t
t
t
t
t
t
t
t
t
Low Speed Data Rate  
1.4775  
–75  
1.5225  
75  
Mbs  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
ns  
Ave. Bit Rate (1.5 Mb/s ± 1.5%)  
drate  
djr1  
[13]  
Receiver Data Jitter Tolerance  
Receiver Data Jitter Tolerance  
Differential to EOP Transition Skew  
EOP Width at Receiver  
To Next Transition  
[13]  
–45  
45  
For Paired Transitions  
djr2  
–40  
100  
Note 6  
deop  
eopr1  
eopr2  
eopt  
udj1  
udj2  
[13]  
330  
Rejects as EOP  
[13]  
EOP Width at Receiver  
675  
Accepts as EOP  
Source EOP Width  
1.25  
–95  
1.50  
95  
Differential Driver Jitter  
To next transition, Figure 12  
Differential Driver Jitter  
–150  
150  
To paired transition, Figure 12  
Notes:  
9. Per Table 7-7 of revision 1.1 of USB specification, for C  
of 50–600 pF.  
LOAD  
10. Measured as largest step size vs. nominal according to measured full scale and zero programmed values.  
11. T = Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed.  
ratio  
12. Irange: Isinkn(15)/ Isinkn(0) for the same pin.  
13. Measured at crossover point of differential data signals.  
14. Limits total bus capacitance loading (C  
) to 400 pF per section 7.1.5 of revision 1.1 of USB specification.  
LOAD  
15. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused pins.  
Document #: 38-08027 Rev. *B  
Page 26 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
.
t
CYC  
t
CH  
CLOCK  
t
CL  
Figure 8. Clock Timing  
t
t
f
r
D+  
V
oh  
90%  
90%  
V
crs  
10%  
10%  
V
ol  
D−  
Figure 9. USB Data Signal Timing  
TPERIOD  
Differential  
Data Lines  
TJR  
TJR1  
TJR2  
Consecutive  
Transitions  
N * TPERIOD + TJR1  
Paired  
Transitions  
N * TPERIOD + TJR2  
Figure 10. Receiver Jitter Tolerance  
Document #: 38-08027 Rev. *B  
Page 27 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
TPERIOD  
Crossover Point  
Extended  
Crossover  
Point  
Differential  
Data Lines  
Diff. Data to  
SE0 Skew  
N * TPERIOD + TDEOP  
Source EOP Width: TEOPT  
Receiver EOP Width: TEOPR1, TEOPR2  
Figure 11. Differential to EOP Transition Skew and EOP Width  
TPERIOD  
Crossover  
Points  
Differential  
Data Lines  
Consecutive  
Transitions  
N * TPERIOD + TxJR1  
Paired  
Transitions  
N * TPERIOD + TxJR2  
Figure 12. Differential Data Jitter  
Ordering Information  
EPROM  
Size  
Package  
Name  
Operating  
Range  
Ordering Code  
CY7C63413C-PVXC  
CY7C63413C-PVXCT  
CY7C63413C-PXC  
CY7C63513C-PVXC  
CY7C63613C-SXC  
CY7C63413C-XC  
Package Type  
48-Lead Shrunk Small Outline Package  
48-Lead SSOP Lead-Free Tape-reel  
40-pin (600 mil) PDIP Lead-Free  
48-Lead SSOP Lead-Free  
8 KB  
8 KB  
8 KB  
8 KB  
8 KB  
8KB  
SP48  
SP48  
P2  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
SP48  
SZ24.3  
-
24-lead (300 mil) SOIC Lead-Free  
Die Lead-Free  
Document #: 38-08027 Rev. *B  
Page 28 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Die Pad Locations  
Table 30.DIe Pad Locations (in microns)  
Pad #  
1
Pin Name  
D+  
X
Y
Pad #  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Pin Name  
X
Y
1496.95  
467.40  
345.15  
242.15  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
98.00  
306.30  
442.15  
593.40  
696.40  
824.25  
949.65  
2995.00  
2995.00  
3023.60  
3023.60  
2661.25  
2558.25  
2455.25  
2352.25  
2249.25  
2146.25  
1134.25  
1031.25  
928.25  
825.25  
721.05  
618.05  
516.25  
413.25  
98.00  
V
1619.65  
1719.65  
1823.10  
1926.10  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
2066.30  
1858.00  
1718.30  
1618.50  
1513.50  
1301.90  
1160.50  
3023.60  
3023.60  
3023.60  
3023.60  
2657.35  
2554.35  
2451.35  
2348.35  
2245.35  
2142.35  
1130.35  
1027.35  
924.35  
821.35  
719.55  
616.55  
512.35  
409.35  
98.00  
CC  
2
D-  
V
SS  
3
Port3[7]  
Port3[5]  
Port3[3]  
Port3[1]  
Port2[7]  
Port2[5]  
Port2[3]  
Port2[1]  
Por1[7]  
Por1[5]  
Por1[3]  
Por1[1]  
DAC7  
Port3[6]  
Port3[4]  
Port3[2]  
Port3[0]  
Port2[6]  
Port2[4]  
Port2[2]  
Port2[0]  
Port1[6]  
Port1[4]  
Port1[2]  
Port1[0]  
DAC6  
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DAC5  
DAC4  
Port0[7]  
Port0[5]  
Port0[3]  
Port0[1]  
DAC3  
Port0[6]  
Port0[4]  
Port0[2]  
Port0[0]  
DAC2  
98.00  
98.00  
98.00  
98.00  
DAC1  
98.00  
DAC0  
98.00  
V
V
98.00  
XtalOut  
XtalIn  
98.00  
PP  
SS  
98.00  
98.00  
Document #: 38-08027 Rev. *B  
Page 29 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Package Diagrams  
48-Lead Shrunk Small Outline Package SP48  
51-85061-*C  
40-Lead (600-Mil) Molded DIP P2  
51-85019-*A  
Document #: 38-08027 Rev. *B  
Page 30 of 32  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Package Diagrams (continued)  
24-Lead (300-Mil) SOIC S24.3/SZ24.3  
NOTE :  
1. JEDEC STD REF MO-119  
PIN 1 ID  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT  
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE  
12  
1
MIN.  
3. DIMENSIONS IN INCHES  
MAX.  
0.291[7.391]  
0.300[7.620]  
4. PACKAGE WEIGHT 0.65gms  
*
0.394[10.007]  
0.419[10.642]  
PART #  
13  
24  
0.026[0.660]  
0.032[0.812]  
S24.3 STANDARD PKG.  
SZ24.3 LEAD FREE PKG.  
SEATING PLANE  
0.597[15.163]  
0.615[15.621]  
0.092[2.336]  
0.105[2.667]  
*
0.004[0.101]  
0.0091[0.231]  
0.0125[0.317]  
*
0.015[0.381]  
0.050[1.270]  
0.004[0.101]  
0.0118[0.299]  
0.050[1.270]  
TYP.  
0.013[0.330]  
0.019[0.482]  
51-85025-*C  
All products and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-08027 Rev. *B  
Page 31 of 32  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
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CY7C63413C  
CY7C63513C  
CY7C63613C  
Document History Page  
Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-speed High I/O, 1.5 -Mbps USB Controller  
Document Number: 38-08027  
Issue  
Date  
Orig. of  
Change  
REV.  
**  
ECN NO.  
116224  
Description of Change  
06/12/02  
DSG  
KKU  
Change from Spec number: 38-00754 to 38-08027  
*A  
237148  
SEE ECN  
Removed 24 pin package, CY7C63411/12, CY7C63511/12 and  
CY7C636XX parts  
Added Lead-Free part numbers to section 20.0  
Added USB Logo.  
*B  
418699  
See ECN  
TYJ  
Part numbers updated with MagnaChip offerings  
Document #: 38-08027 Rev. *B  
Page 32 of 32  
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