50
CY7C150
1Kx4 Static RAM
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Features
• Memory reset function
• 1024x4 staticRAM for control storein high-speed com-
puters
• CMOS for optimum speed/power
• High speed
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
— 10 ns (commercial)
— 12 ns (military)
• Low power
— 495 mW (commercial)
— 550 mW (military)
• Separate inputs and outputs
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D0−D3) is written into the memory location
specified on the address pins (A0 through A9).
• 5-voltpowersupply±10%toleranceinbothcommercial
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O0 through O3).
and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible inputs and outputs
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
RS
D D D D
0
1
2
3
DIP/SOIC
Top View
CS
OE
DATAINPUT
CONTROL
A
A
4
V
A
2
3
1
2
3
4
5
24
23
22
21
20
19
18
17
16
15
14
13
CC
WE
A
A
5
1
A
6
A
0
A
0
O
0
A
RS
CS
7
A
1
A
7C150
8
6
7
8
O
1
64x64
ARRAY
A
2
A
9
D
0
WE
OE
D
3
D
O
3
O
A
3
O
2
A
4
D
9
1
10
11
12
O
0
A
5
2
O
3
O
1
GND
2
COLCUMONLDUECMONDER
DECODER
C150-2
C150–1
A
6
A
7
A
8
A
9
Selection Guide
7C150−10 7C150−12 7C150−15 7C150−25 7C150−35
Maximum Access Time (ns)
Commercial
Military
10
12
12
15
15
25
25
35
90
Maximum Operating Current (mA)
Commercial
Military
90
90
90
90
100
100
100
100
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05024 Rev. **
Revised August 24, 2001
CY7C150
Switching Characteristics Over the Operating Range[2,5]
7C150−10
7C150−12
7C150−15
7C150−25
7C150−35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
10
2
12
2
15
2
25
2
35
2
ns
ns
ns
tAA
Address to Data Valid
10
8
12
10
15
12
25
15
35
20
tOHA
Output Hold from Address
Change
tACS
CS LOW to Data Valid
OE LOW to Data Valid
ns
ns
ns
ns
ns
ns
tLZCS
tHZCS
tDOE
0
0
0
0
0
0
0
0
0
0
6
6
8
8
11
10
20
15
25
20
tLZOE
tHZOE
WRITE CYCLE[8]
tWC Write Cycle Time
tSCS
tAW
6
8
9
20
25
10
6
12
8
15
11
13
2
25
15
20
5
35
20
30
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
10
2
tHA
2
tSA
2
2
2
5
5
tPWE
tSD
6
8
11
11
2
15
15
5
20
20
5
Data Set-Up to Write End
Data Hold from Write End
6
8
tHD
2
2
tLZWE
tHZWE
0
0
0
0
0
6
8
12
20
25
RESET CYCLE
tRRC Reset Cycle Time
tSAR
20
0
24
0
30
0
50
0
70
0
ns
ns
Address Valid to Beginning of
Reset
tSWER
tSCSR
Write Enable HIGH to Beginning
of Reset
0
0
0
0
0
0
0
0
0
0
ns
ns
Chip Select LOW to Beginning of
Reset
tPRS
Reset Pulse Width
10
0
12
0
15
0
20
0
30
0
ns
ns
tHCSR
Chip Select Hold After End of
Reset
tHWER
Write Enable Hold After End of
Reset
8
12
15
30
40
ns
tHAR
Address Hold After End of Reset
Reset HIGH to Output in Low Z[6]
10
0
12
0
15
0
30
0
40
0
ns
ns
ns
tLZRS
tHZRS
Reset LOW to Output in
6
8
12
20
25
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
7.
I
t
HZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
Document #: 38-05024 Rev. **
Page 3 of 11
CY7C150
Switching Waveforms
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C150-5
Read CycleNo. 2
t
RC
CE
t
ACS
OE
t
t
HZOE
t
DOE
HZCS
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCS
C150-6
Write CycleNo.1(WEControlled) [8]
t
WC
ADDRESS
CE
t
SCS
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C150-7
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CS and OE = VIL.
11. Address prior to or coincident with CS transition LOW.
Document #: 38-05024 Rev. **
Page 4 of 11
CY7C150
Switching Waveforms (continued)
Write Cycle No2. (CS Controlled) [8,12]
t
WC
ADDRESS
t
SA
t
SCS
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
DATA I/O
IN
t
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
C150-8
t
RRC
ADDRESS
WE
t
t
SAR
t
HAR
t
SWER
HWER
t
t
HCSR
CS
SCSR
t
PRS
RESET
t
t
LZRS
HZRS
DATA I/O
HIGH
IMPEDANCE
OUTPUT VALID ZERO
C150-9
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
Document #: 38-05024 Rev. **
Page 5 of 11
CY7C150
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs.AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs.OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs.SUPPLY VOLTAGE
60
50
40
30
20
1.4
1.2
1.2
1.0
0.8
I
I
CC
CC
1.0
0.8
0.6
V
CC
=5.0V
0.6
0.4
T =25°C
A
V
V
IN
=5.0V
=5.0V
CC
0.4
0.2
0.0
10
0
I
SB
0.2
0.0
I
SB
−55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs.AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs.SUPPLY VOLTAGE
150
125
1.6
1.4
1.4
1.3
1.2
100
75
V
CC
=5.0V
1.2
1.0
T =25°C
A
1.1
1.0
T =25°C
A
50
V
CC
=5.0V
0.8
25
0
0.9
0.8
0.6
−55
0.0
1.0
2.0
3.0
4.0
5.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
TYPICALPOWER–ONCURRENT
vs.SUPPLYVOLTAGE
TYPICAL ACCESS TIME CHANGE
vs.OUTPUT LOADING
NORMALIZED I vs.CYCLETIME
CC
3.0
2.5
2.0
1.5
30
1.1
1.0
0.9
0.8
V
=5.0V
CC
T =25°C
A
V
CC
=0.5V
20
1.0
0.5
0.0
10
0
V
=4.5V
CC
T =25°C
A
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE(V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05024 Rev. **
Page 6 of 11
CY7C150
Truth Table
Inputs
CS WE OE RS
Outputs
High Z
Mode
Not Selected
Reset
H
L
L
L
L
X
H
L
X
X
X
L
X
L
High Z
High Z
O0−O3
High Z
H
H
H
Write
H
X
Read
H
Output Disable
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C150−10PC
CY7C150−10SC
CY7C150−12PC
CY7C150−12SC
CY7C150−12DMB
CY7C150−15PC
CY7C150−15SC
CY7C150−15DMB
CY7C150−25PC
CY7C150−25SC
CY7C150−25DMB
CY7C150−35DMB
Name
P13A
S13
Package Type
10
24-Lead (300-Mil) Molded DIP Commercial
24-Lead Molded SOIC
12
15
25
35
P13A
S13
24-Lead (300-Mil) Molded DIP Commercial
24-Lead Molded SOIC
D14
24-Lead (300-Mil) CerDIP
Military
P13A
S13
24-Lead (300-Mil) Molded DIP Commercial
24-Lead Molded SOIC
D14
24-Lead (300-Mil) CerDIP
Military
P13A
S13
24-Lead (300-Mil) Molded DIP Commercial
24-Lead Molded SOIC
D14
24-Lead (300-Mil) CerDIP
24-Lead (300-Mil) CerDIP
Military
Military
D14
Document #: 38-05024 Rev. **
Page 7 of 11
CY7C150
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
READ CYCLE
DC Characteristics
tRC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Parameter
VOH
Subgroups
1, 2, 3
tAA
tOHA
VOL
VIH
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tACS
WRITE CYCLE
VIL Max.
IIX
tWC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSCS
IOZ
tAW
ICC
tHA
tSA
tPWE
tSD
tHD
RESET CYCLE
tRRC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSAR
tSWER
tSCSR
tPRS
tHCSR
tHWER
tHAR
Document #: 38-05024 Rev. **
Page 8 of 11
CY7C150
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9Config.A
24-Lead (300-Mil) Molded DIP P13/P13A
Document #: 38-05024 Rev. **
Page 9 of 11
CY7C150
Package Diagrams (continued)
24-Lead Molded SOIC S13
Document #: 38-05024 Rev. **
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C150
Document Title: Cy7C150 1K x4 Static RAM
Document Number: 38-05024
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106810
09/10/01
SZV
Change from Spec number: 38-00028 to 38-05024
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