Cypress CY7C1486V25 User Manual

CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
• Available speed grades are 250, 200, and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• 2.5V core power supply  
The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM  
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
• 2.5V/1.8V IO operation  
• Fast clock-to-output time  
(CE ), depth-expansion Chip Enables (CE and CE ), Burst  
1
2
3
— 3.0 ns (for 250-MHz device)  
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW ,  
X
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• Provide high-performance 3-1-1-1 access rate  
®
• User selectable burst counter supporting Intel  
®
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) is active. Subsequent burst  
addresses can be internally generated as controlled by the  
Advance pin (ADV).  
Pentium interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self timed writes  
• Asynchronous output enable  
• Single cycle chip deselect  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle. This part supports Byte  
Table” on page 10 for further details). Write cycles can be one  
to two or four bytes wide, as controlled by the byte write control  
inputs. When it is active LOW, GW causes all bytes to be  
written.  
• CY7C1480V25, CY7C1482V25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and  
non-Pb-free 165-ball FBGA package. CY7C1486V25  
available in Pb-free and non-Pb-free 209-ball FBGA  
package  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode option  
The CY7C1480V25/CY7C1482V25/CY7C1486V25 operates  
from a +2.5V core power supply while all outputs may operate  
with either a +2.5 or +1.8V supply. All inputs and outputs are  
JEDEC-standard JESD8-5-compatible.  
Selection Guide  
250 MHz  
3.0  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
450  
450  
400  
mA  
mA  
120  
120  
120  
Note  
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05282 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 23, 2007  
 
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Logic Block Diagram – CY7C1486V25 (1M x 72)  
ADDRESS  
REGISTER  
A0, A1,A  
A[1:0]  
MODE  
Q1  
Q0  
ADV  
CLK  
BINARY  
COUNTER  
CLR  
ADSC  
ADSP  
DQ  
H
,
DQPH  
DQ  
H
,
DQPH  
BW  
BW  
H
G
WRITE DRIVER  
WRITE DRIVER  
DQ  
G
,
DQPG  
DQ  
F
,
DQPF  
WRITE DRIVER  
WRITE DRIVER  
DQ  
F
,
DQPF  
DQ  
F
,
DQPF  
BW  
BW  
BW  
BW  
F
E
WRITE DRIVER  
WRITE DRIVER  
DQ  
E
,
DQPE  
DQ  
E
,
DQPE  
WRITE DRIVER  
WRITE DRIVER  
MEMORY  
ARRAY  
DQ  
D
,
DQPD  
DQ  
D
,
DQPD  
D
WRITE DRIVER  
WRITE DRIVER  
DQ  
C
,
DQPC  
DQ  
C
,
DQPC  
C
WRITE DRIVER  
WRITE DRIVER  
OUTPUT  
BUFFERS  
OUTPUT  
REGISTERS  
SENSE  
AMPS  
DQs  
DQP  
DQP  
DQP  
DQP  
DQP  
DQP  
DQP  
DQP  
A
B
C
D
E
E
DQ  
B
,
DQPB  
DQ  
B
,
DQPB  
WRITE DRIVER  
BW  
BW  
B
WRITE DRIVER  
DQ  
A
,
DQPA  
DQ  
A
,
DQPA  
F
WRITE DRIVER  
A
WRITE DRIVER  
G
H
BWE  
INPUT  
GW  
CE1  
CE2  
CE3  
OE  
REGISTERS  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
SLEEP  
CONTROL  
ZZ  
Document #: 38-05282 Rev. *H  
Page 3 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Pin Configurations  
100-Pin TQFP Pinout  
DQPC  
1
DQPB  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
VSS  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
NC  
VDDQ  
VSSQ  
NC  
A
NC  
NC  
VDDQ  
VSSQ  
NC  
DQPA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
VSS  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQC  
2
DQc  
VDDQ  
VSSQ  
DQC  
3
4
5
6
DQC  
7
NC  
DQC  
8
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
NC  
VDD  
NC  
VSS  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQPB  
NC  
DQC  
9
10  
11  
9
VSSQ  
VDDQ  
DQC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
12  
DQC  
13  
NC  
14  
VDD  
15  
NC  
VDD  
ZZ  
CY7C1482V25  
(4M x 18)  
CY7C1480V25  
(2M x 36)  
NC  
16  
VDD  
ZZ  
VSS  
17  
DQD  
18  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
DQPA  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
NC  
DQD  
19  
20  
21  
VDDQ  
VSSQ  
DQD  
22  
DQD  
23  
DQD  
24  
DQD  
25  
26  
27  
NC  
VSSQ  
VDDQ  
DQD  
DQD  
29  
VSSQ  
VDDQ  
NC  
NC  
NC  
VSSQ  
VDDQ  
NC  
NC  
NC  
28  
DQPD  
30  
Document #: 38-05282 Rev. *H  
Page 4 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Pin Configurations (continued)  
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout  
CY7C1480V25 (2M x 36)  
1
2
3
4
5
6
7
8
9
10  
A
11  
NC  
NC/288M  
NC/144M  
DQPC  
A
B
C
D
CE1  
BWC  
BWD  
VSS  
VDD  
BWB  
BWA  
VSS  
VSS  
CE  
A
BWE  
GW  
VSS  
ADSC  
OE  
ADV  
ADSP  
VDDQ  
VDDQ  
3
A
CE2  
VDDQ  
VDDQ  
CLK  
VSS  
VSS  
A
NC/576M  
DQPB  
DQB  
NC  
VSS  
NC/1G  
DQB  
DQC  
DQC  
VSS  
VDD  
DQC  
DQC  
DQC  
DQC  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQB  
DQB  
DQB  
NC  
DQB  
E
F
DQC  
DQC  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQB  
DQB  
ZZ  
G
H
J
DQD  
DQD  
DQD  
DQD  
DQD  
DQD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
DQA  
DQA  
DQA  
K
L
DQD  
DQPD  
NC  
DQD  
NC  
A
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
A
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
A
M
N
P
TDI  
A1  
TDO  
A0  
MODE  
A
A
A
TMS  
TCK  
A
A
A
A
R
CY7C1482V25 (4M x 18)  
1
2
A
3
4
5
NC  
6
7
8
9
10  
A
11  
A
NC/288M  
NC/144M  
NC  
A
B
C
D
BWB  
NC  
CE  
CE1  
CE2  
BWE  
GW  
VSS  
VSS  
ADSC  
OE  
ADV  
ADSP  
VDDQ  
VDDQ  
3
A
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
A
NC/576M  
DQPA  
DQA  
NC  
VDDQ  
VDDQ  
VSS  
VDD  
VSS  
NC/1G  
NC  
NC  
DQB  
VDD  
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQA  
DQA  
DQA  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
NC  
NC  
NC  
K
L
NC  
NC  
DQB  
DQPB  
NC  
NC  
NC  
A
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
A
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
NC  
NC  
A
M
N
P
TDI  
A1  
TDO  
MODE  
A
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05282 Rev. *H  
Page 5 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Pin Configurations (continued)  
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout  
CY7C1486V25 (1M × 72)  
1
2
3
A
4
5
6
7
8
9
10  
11  
DQG  
DQG  
DQG  
A
B
C
D
E
F
DQG  
DQG  
DQB  
DQB  
DQB  
CE  
ADSC  
BWE  
ADSP  
ADV  
A
CE  
A
DQB  
DQB  
2
3
NC/288M  
NC/144M  
BWS  
BWS  
BWS  
B
BWS  
F
G
C
DQG  
DQG  
NC/576M  
GW  
BWS  
NC  
BWS  
CE  
BWS  
A
BWS  
DQB  
DQB  
E
D
1
H
DQG  
V
NC/1G OE  
V
NC  
V
SS  
DQB  
SS  
DQPG DQPC  
V
V
V
V
V
V
DDQ  
DDQ  
DDQ  
SS  
DDQ  
DD  
DD  
DD  
DQPF DQPB  
DQC  
DQC  
V
V
V
DQF  
DQF  
V
V
NC  
NC  
NC  
NC  
V
V
SS  
SS  
SS  
SS  
DD  
SS  
G
H
J
DQC  
DQC  
V
DQC  
V
V
DDQ  
V
V
V
DD  
DDQ  
DQF  
DQF  
DDQ  
DDQ  
V
V
V
V
V
V
V
DQC  
DQC  
NC  
DQF  
SS  
SS  
SS  
SS  
SS  
SS  
DQ  
F
DQC  
NC  
V
V
V
V
DDQ  
V
DDQ  
DD  
DD  
DDQ  
DDQ  
DQF  
NC  
DQF  
NC  
K
L
CLK  
V
V
V
NC  
V
SS  
SS  
SS  
NC  
NC  
DQH  
DQH  
DQH  
V
V
V
NC  
NC  
V
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
DQA  
DQA  
DQ  
A
DDQ  
M
N
P
R
T
V
V
V
V
V
V
V
DQH  
DQH  
DQH  
V
V
SS  
SS  
SS  
SS  
SS  
DQA  
DQA  
DQA  
V
V
V
DDQ  
DQH  
DQH  
DQPD  
DQD  
DQD  
V
V
V
V
V
NC  
ZZ  
V
DD  
DD  
DDQ  
SS  
DDQ  
DDQ  
DQA  
DQA  
DQPA  
DQE  
DQE  
V
V
V
V
V
V
SS  
SS  
SS  
SS  
SS  
DQPH  
DQD  
DQD  
DQD  
DQD  
V
V
DDQ  
SS  
DD  
DD  
DDQ  
DDQ  
SS  
DDQ  
DD  
DQPE  
DQE  
DQE  
DQE  
DQE  
NC  
V
NC  
A
NC  
NC  
A
MODE  
A
U
V
W
A
A
A
A
A
A
A1  
A
DQD  
DQD  
A
A
A
DQE  
DQE  
TDI  
TDO  
TCK  
A
A0  
A
TMS  
Document #: 38-05282 Rev. *H  
Page 6 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Pin Definitions  
Pin Name  
I/O  
Description  
Address Inputs used to select one of the address locations. Sampled at the rising  
A , A , A  
Input-  
0
1
Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled  
1
2
3
active. A1: A0 are fed to the two-bit counter.  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the  
Synchronous SRAM. Sampled on the rising edge of CLK.  
Input-  
BW ,BW ,BW ,  
A
B
C
BW , BW , BW ,  
D
E
F
BW , BW  
G
H
GW  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,  
Synchronous a global write is conducted (ALL bytes are written, regardless of the values on BW and  
X
BWE).  
BWE  
CLK  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal  
Synchronous must be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock Input. Captures all synchronous inputs to the device. Also increments the burst  
counter when ADV is asserted LOW during a burst operation.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in  
1
2
3
Synchronous conjunction with CE and CE to select/deselect the device. ADSP is ignored if CE is  
2
3
1
HIGH. CE is sampled only when a new external address is loaded.  
1
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in  
Synchronous conjunction with CE and CE to select/deselect the device. CE is sampled only when a  
1
3
2
new external address is loaded.  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in  
Synchronous conjunction with CE and CE to select/deselect the device. CE is sampled only when a  
Input-  
1
2
3
new external address is loaded.  
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the IO pins.  
Asynchronous When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,  
and act as input data pins. OE is masked during the first clock of a read cycle when  
emerging from a deselected state.  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted, it automatically increments the address in a burst cycle.  
ADSP  
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.  
Synchronous When asserted LOW, addresses presented to the device are captured in the address  
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both  
asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH.  
1
ADSC  
ZZ  
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.  
Synchronous When asserted LOW, addresses presented to the device are captured in the address  
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both  
asserted, only ADSP is recognized.  
Input-  
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a  
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this  
pin has to be LOW or left floating. ZZ pin has an internal pull down.  
I/O-  
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is  
DQs, DQPs  
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
memory location specified by the addresses presented during the previous clock rise of  
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,  
the pins behave as outputs. When HIGH, DQs and DQP are placed in a tri-state condition.  
X
V
V
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
Ground  
Ground for the core of the device.  
Ground for the I/O circuitry.  
SS  
I/O Ground  
SSQ  
I/O Power Supply Power supply for the I/O circuitry.  
DDQ  
Note  
2. Applicable for TQFP package. For BGA package V serves as ground for the core and the IO circuitry.  
SS  
Document #: 38-05282 Rev. *H  
Page 7 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Pin Definitions (continued)  
Pin Name  
I/O  
Description  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V  
MODE  
Input Static  
DD  
or left floating selects interleaved burst sequence. This is a strap pin and must remain static  
during device operation. Mode pin has an internal pull up.  
TDO  
TDI  
JTAG Serial  
Output  
Synchronous packages.  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the  
JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP  
JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature  
Synchronous is not used, this pin can be disconnected or connected to V . This pin is not available on  
DD  
TQFP packages.  
TMS  
JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature  
Synchronous is not used, this pin can be disconnected or connected to V . This pin is not available on  
DD  
TQFP packages.  
TCK  
NC  
JTAG Clock  
-
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be  
connected to V . This pin is not available on TQFP packages.  
SS  
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address  
expansion pins and are not internally connected to the die.  
corresponding data is allowed to propagate to the input of the  
Output Registers. At the rising edge of the next clock the data  
Functional Overview  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
Maximum access delay from the clock rise (t ) is 3.0 ns  
(250 MHz device).  
is allowed to propagate through the output register and onto  
the data bus within 3.0 ns (250-MHz device) if OE is active  
LOW. The only exception occurs when the SRAM is emerging  
from a deselected state to a selected state, its outputs are  
always tri-stated during the first cycle of the access. After the  
first cycle of the access, the outputs are controlled by the OE  
signal. Consecutive single read cycles are supported. After the  
SRAM is deselected at clock rise by the chip select and either  
ADSP or ADSC signals, its output will tri-state immediately.  
CO  
The CY7C1480V25/CY7C1482V25/CY7C1486V25 supports  
secondary cache in systems using either a linear or inter-  
leaved burst sequence. The interleaved burst order supports  
Pentium and i486processors. The linear burst sequence is  
suited for processors that use a linear burst sequence. The  
burst order is user selectable, and is determined by sampling  
the MODE input. Accesses can be initiated with either the  
Processor Address Strobe (ADSP) or the Controller Address  
Strobe (ADSC). Address advancement through the burst  
sequence is controlled by the ADV input. A two-bit on-chip  
wraparound burst counter captures the first address in a burst  
sequence and automatically increments the address for the  
rest of the burst access.  
Single Write Accesses Initiated by ADSP  
This access is initiated when both of the following conditions  
are satisfied at clock rise: (1) ADSP is asserted LOW, and  
(2) CE , CE , CE are all asserted active. The address  
1
2
3
presented to A is loaded into the address register and the  
address advancement logic while being delivered to the  
memory array. The write signals (GW, BWE, and BW ) and  
X
ADV inputs are ignored during this first cycle.  
ADSP-triggered write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQs inputs is written into the corre-  
sponding address location in the memory array. If GW is HIGH,  
Byte write operations are qualified with the Byte Write Enable  
(BWE) and Byte Write Select (BW ) inputs. A Global Write  
X
Enable (GW) overrides all byte write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed write circuitry.  
then the write operation is controlled by the BWE and BW  
X
signals.  
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides  
Byte Write capability that is described in the “Truth Table for  
Read/Write” on page 11. Asserting the Byte Write Enable input  
asynchronous Output Enable (OE) provide easy bank  
selection and output tri-state control. ADSP is ignored if CE  
1
is HIGH.  
(BWE) with the selected Byte Write (BW ) input, will selec-  
X
Single Read Accesses  
tively write to only the desired bytes. Bytes not selected during  
a byte write operation remain unaltered. A synchronous  
self-timed write mechanism has been provided to simplify the  
write operations.  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
CE , CE , CE are all asserted active, and (3) the write signals  
1
2
3
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE  
Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a  
common IO device, the Output Enable (OE) must be  
deasserted HIGH before presenting data to the DQs inputs.  
Doing so tri-states the output drivers. As a safety precaution,  
1
is HIGH. The address presented to the address inputs (A) is  
stored into the address advancement logic and the Address  
Register while being presented to the memory array. The  
Document #: 38-05282 Rev. *H  
Page 8 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
DQs are automatically tri-stated whenever a write cycle is  
detected, regardless of the state of OE.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
the “sleep” mode. CE , CE , CE , ADSP, and ADSC must  
Single Write Accesses Initiated by ADSC  
ADSC Write accesses are initiated when the following condi-  
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
deasserted HIGH, (3) CE , CE , CE are all asserted active,  
1
2
3
and (4) the appropriate combination of the write inputs (GW,  
BWE, and BW ) are asserted active to conduct a write to the  
X
1
2
3
desired byte(s). ADSC-triggered write accesses need a single  
clock cycle to complete. The address presented to A is loaded  
into the address register and the address advancement logic  
while being delivered to the memory array. The ADV input is  
ignored during this cycle. If a global write is conducted, the  
data presented to the DQs is written into the corresponding  
address location in the memory core. If a byte write is  
conducted, only the selected bytes are written. Bytes not  
selected during a byte write operation remain unaltered. A  
synchronous self-timed write mechanism has been provided  
to simplify the write operations.  
remain inactive for the duration of t  
returns LOW.  
after the ZZ input  
ZZREC  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
)
First  
Address  
A1: A0  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a  
common IO device, the Output Enable (OE) must be  
deasserted HIGH before presenting data to the DQs inputs.  
Doing so tri-states the output drivers. As a safety precaution,  
DQs are automatically tri-stated whenever a write cycle is  
detected, regardless of the state of OE.  
Linear Burst Address Table  
(MODE = GND)  
Burst Sequences  
First  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides  
a two-bit wraparound counter, fed by A1: A0, that implements  
either an interleaved or linear burst sequence. The interleaved  
burst sequence is designed specifically to support Intel  
Pentium applications. The linear burst sequence is designed  
to support processors that follow a linear burst sequence. The  
burst sequence is user selectable through the MODE input.  
Address  
A1: A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
Asserting ADV LOW at clock rise automatically increments the  
burst counter to the next address in the burst sequence. Both  
Read and Write burst operations are supported.  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep Mode Standby Current  
Device Operation to ZZ  
Test Conditions  
ZZ > V – 0.2V  
Min.  
Max.  
120  
Unit  
mA  
ns  
I
t
t
t
t
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ Recovery Time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to Sleep Current  
ZZ Inactive to Exit Sleep Current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Document #: 38-05282 Rev. *H  
Page 9 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Truth Table  
The truth table for CY7C1480V25, CY7C1482V25, and CY7C1486V25 follows.  
Operation  
Add. Used CE  
CE  
X
L
CE ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
3
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Sleep Mode, Power Down  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Write Cycle, Begin Burst  
None  
None  
H
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
None  
L
X
L
L
None  
L
H
H
X
L
None  
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None  
X
L
X
X
X
L
X
Tri-State  
Q
External  
External  
External  
External  
External  
Next  
L-H  
L
L
L
H
X
L
L-H Tri-State  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H  
L-H  
D
Q
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State  
L-H  
L-H Tri-State  
L-H  
L-H Tri-State  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next  
L
H
L
Next  
L
Q
Next  
L
H
X
X
L
Next  
L
L-H  
L-H  
L-H  
D
D
Q
Next  
L
L
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State  
L-H  
L-H Tri-State  
Q
H
X
X
L-H  
L-H  
D
D
L
Notes  
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.  
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks  
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a  
don't care for the remainder of the write cycle  
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is  
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 38-05282 Rev. *H  
Page 10 of 32  
           
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Truth Table for Read/Write  
The read/write truth table for the CY7C1480V25 follows.  
[5]  
Function  
GW  
BWE  
BW  
BW  
BW  
BW  
A
D
C
B
Read  
Read  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
L
X
H
H
H
H
L
X
H
H
L
X
H
L
Write Byte A – (DQ and DQP )  
A
A
Write Byte B – (DQ and DQP )  
H
L
B
B
Write Bytes B, A  
Write Byte C – (DQ and DQP )  
L
H
H
L
H
L
C
C
Write Bytes C, A  
Write Bytes C, B  
Write Bytes C, B, A  
L
L
H
L
L
L
Write Byte D – (DQ and DQP )  
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A  
Write Bytes D, B  
Write Bytes D, B, A  
Write Bytes D, C  
L
L
H
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
L
L
L
H
L
L
L
L
Write All Bytes  
X
X
X
X
Truth Table for Read/Write  
The read/write truth table for the CY7C1482V25 follows.  
[5]  
Function  
GW  
BWE  
BW  
BW  
A
B
Read  
Read  
H
H
H
H
H
H
L
H
L
L
L
L
L
X
X
H
H
L
X
H
L
Write Byte A – (DQ and DQP )  
A
A
Write Byte B – (DQ and DQP )  
H
L
B
B
Write Bytes B, A  
Write All Bytes  
Write All Bytes  
L
L
L
X
X
Truth Table for Read/Write  
The read/write truth table for the CY7C1486V25 follows.  
[8]  
Function  
GW  
BWE  
BW  
X
Read  
H
H
H
H
L
H
L
L
L
X
X
Read  
All BW = H  
Write Byte x – (DQx and DQPx)  
Write All Bytes  
L
All BW = L  
X
Write All Bytes  
Note  
8. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can  
be enabled at the same time for any given write.  
Document #: 38-05282 Rev. *H  
Page 11 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Test Mode Select (TMS)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TMS input gives commands to the TAP controller and is  
sampled on the rising edge of TCK. You can leave this ball  
unconnected if the TAP is not used. The ball is pulled up inter-  
nally, resulting in a logic HIGH level.  
The CY7C1480V25/CY7C1482V25/CY7C1486V25 incorpo-  
rates a serial boundary scan test access port (TAP). This port  
operates in accordance with IEEE Standard 1149.1-1990 but  
does not have the set of functions required for full 1149.1  
compliance. These functions from the IEEE specification are  
excluded because their inclusion places an added delay in the  
critical speed path of the SRAM. Note that the TAP controller  
functions in a manner that does not conflict with the operation  
of other devices using 1149.1 fully compliant TAPs. The TAP  
operates using JEDEC-standard 2.5V or 1.8V I/O logic levels.  
Test Data-In (TDI)  
The TDI ball serially inputs information into the registers and  
can be connected to the input of any of the registers. The  
register between TDI and TDO is chosen by the instruction  
that is loaded into the TAP instruction register. For information  
on loading the instruction register, see the TAP Controller  
State Diagram. TDI is internally pulled up and can be uncon-  
nected if the TAP is unused in an application. TDI is connected  
to the most significant bit (MSB) of any register. (See TAP  
The CY7C1480V25/CY7C1482V25/CY7C1486V25 contains  
a TAP controller, instruction register, boundary scan register,  
bypass register, and ID register.  
Disabling the JTAG Feature  
Test Data-Out (TDO)  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See TAP Controller State Diagram.)  
(V ) to prevent device clocking. TDI and TMS are internally  
SS  
pulled up and may be unconnected. They may alternatively be  
connected to V through a pull up resistor. TDO must be left  
DD  
unconnected. At power up, the device comes up in a reset  
state, which does not interfere with the operation of the device.  
TAP Controller Block Diagram  
TAP Controller State Diagram  
0
TEST-LOGIC  
1
RESET  
0
Bypass Register  
2
1
0
0
0
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
Selection  
Circuitry  
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
0
0
TDI  
TDO  
1
1
.
.
.
2
1
CAPTURE-DR  
CAPTURE-IR  
0
0
x
.
.
.
.
.
2
1
SHIFT-DR  
0
SHIFT-IR  
0
Boundary Scan Register  
1
1
1
1
EXIT1-DR  
EXIT1-IR  
0
0
PAUSE-DR  
0
PAUSE-IR  
1
0
TCK  
TAP CONTROLLER  
TM S  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
Performing a TAP Reset  
UPDATE-DR  
UPDATE-IR  
Perform a RESET by forcing TMS HIGH (V ) for five rising  
DD  
1
0
1
0
edges of TCK. This RESET does not affect the operation of  
the SRAM and may be performed while the SRAM is  
operating.  
At power up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
TAP Registers  
Test Access Port (TAP)  
Registers are connected between the TDI and TDO balls and  
enable data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Document #: 38-05282 Rev. *H  
Page 12 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Instruction Register  
SAMPLE/PRELOAD; rather, it performs a capture of the IO  
ring when these instructions are executed.  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the “TAP Controller Block  
Diagram” on page 12. At power up, the instruction register is  
loaded with the IDCODE instruction. It is also loaded with the  
IDCODE instruction if the controller is placed in a reset state,  
as described in the previous section.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction after it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
enable fault isolation of the board-level serial test data path.  
EXTEST  
EXTEST is a mandatory 1149.1 instruction that is to be  
executed whenever the instruction register is loaded with all  
0s. EXTEST is not implemented in this SRAM TAP controller,  
and therefore this device is not compliant to 1149.1. The TAP  
controller does recognize an all-0 instruction.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This enables data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
When an EXTEST instruction is loaded into the instruction  
register, the SRAM responds as if a SAMPLE/PRELOAD  
instruction has been loaded. There is one difference between  
the two instructions. Unlike the SAMPLE/PRELOAD  
instruction, EXTEST places the SRAM outputs in a High-Z  
state.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM. The x36 configuration has a  
IDCODE  
73-bit-long register, and the x18 configuration has  
54-bit-long register.  
a
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and  
enables the IDCODE to be shifted out of the device when the  
TAP controller enters the Shift-DR state.  
The boundary scan register is loaded with the contents of the  
RAM IO ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller moves to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used  
to capture the contents of the IO ring.  
The IDCODE instruction is loaded into the instruction register  
at power up or whenever the TAP controller is in a test logic  
reset state.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in “Identification Register Defini-  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The  
PRELOAD portion of this instruction is not implemented, so  
the device TAP controller is not fully 1149.1 compliant.  
When the SAMPLE/PRELOAD instruction is loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and bidirectional balls  
is captured in the boundary scan register.  
TAP Instruction Set  
Overview  
Be aware that the TAP controller clock can only operate at a  
frequency up to 10 MHz, while the SRAM clock operates more  
than an order of magnitude faster. Because there is a large  
difference in the clock frequencies, it is possible that during the  
Capture-DR state, an input or output may undergo a transition.  
The TAP may then try to capture a signal while in transition  
(metastable state). This does not harm the device, but there is  
no guarantee as to the value that may be captured.  
Repeatable results may not be possible.  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in “Identification  
Codes” on page 16. Three of these instructions are listed as  
RESERVED and must not be used. The other five instructions  
are described in detail below.  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller’s capture setup plus  
The TAP controller cannot be used to load address data or  
control signals into the SRAM and cannot preload the IO  
buffers. The SRAM does not implement the 1149.1 commands  
EXTEST or INTEST or the PRELOAD portion of  
hold time (t plus t ).  
CS  
CH  
Document #: 38-05282 Rev. *H  
Page 13 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
The SRAM clock input might not be captured correctly if there  
is no way in a design to stop (or slow) the clock during a  
SAMPLE/PRELOAD instruction. If this is an issue, it is still  
possible to capture all other signals and simply ignore the  
value of the CLK captured in the boundary scan register.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO balls.  
Reserved  
Note that because the PRELOAD part of the command is not  
implemented, putting the TAP to the Update-DR state while  
performing a SAMPLE/PRELOAD instruction has the same  
effect as the Pause-DR command.  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min  
Max  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
10  
ns  
ns  
TDOV  
TDOX  
TCK Clock LOW to TDO Invalid  
0
Setup Times  
t
t
t
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes  
9.  
10. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.  
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CH  
CS  
R
F
Document #: 38-05282 Rev. *H  
Page 14 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
2.5V TAP AC Test Conditions  
1.8V TAP AC Test Conditions  
Input pulse levels ................................................ V to 2.5V  
Input pulse levels..................................... 0.2V to V  
– 0.2  
SS  
DDQ  
Input rise and fall time..................................................... 1 ns  
Input timing reference levels.........................................1.25V  
Output reference levels.................................................1.25V  
Test load termination supply voltage.............................1.25V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels........................................... 0.9V  
Output reference levels .................................................. 0.9V  
Test load termination supply voltage .............................. 0.9V  
2.5V TAP AC Output Load Equivalent  
1.8V TAP AC Output Load Equivalent  
1.25V  
0.9V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
ZO= 50Ω  
20pF  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
(0°C < T < +70°C; V = 2.5V ±0.125V unless otherwise noted)  
A
DD  
Parameter  
Description  
Test Conditions  
Min  
1.7  
2.1  
1.6  
Max  
Unit  
V
V
V
Output HIGH Voltage  
Output HIGH Voltage  
I
I
= –1.0 mA  
V
V
V
V
V
V
V
V
V
V
= 2.5V  
= 2.5V  
= 1.8V  
= 2.5V  
= 2.5V  
= 1.8V  
= 2.5V  
= 1.8V  
= 2.5V  
= 1.8V  
OH1  
OH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
= –100 µA  
V
OH2  
OH  
V
V
V
Output LOW Voltage  
Output LOW Voltage  
I
I
= 1.0 mA  
0.4  
0.2  
0.2  
V
OL1  
OL  
OL  
= 100 µA  
V
OL2  
V
V
V
I
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
1.7  
1.26  
–0.3  
–0.3  
–5  
V
V
+ 0.3  
V
IH  
DD  
DD  
+ 0.3  
V
0.7  
V
IL  
0.36  
5
V
GND V V  
DDQ  
µA  
X
I
Identification Register Definitions  
CY7C1480V25  
Instruction Field  
CY7C1482V25  
(4M x 18)  
CY7C1486V25  
(1M x72)  
Description  
(2M x36)  
Revision Number (31:29)  
Device Depth (28:24)  
000  
000  
000  
Describes the version number  
Reserved for internal use  
01011  
000000  
01011  
000000  
01011  
000000  
Architecture/Memory  
Type(23:18)  
Defines memory type and  
architecture  
Bus Width/Density(17:12)  
100100  
010100  
110100  
Defines width and density  
Cypress JEDEC ID Code  
(11:1)  
00000110100  
00000110100  
00000110100  
Enables unique identification  
of SRAM vendor  
ID Register Presence  
Indicator (0)  
1
1
1
Indicates the presence of an  
ID register  
Note  
11. All voltages referenced to V (GND).  
SS  
Document #: 38-05282 Rev. *H  
Page 15 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Scan Register Sizes  
Register Name  
Bit Size (x36)  
Bit Size (x18)  
Bit Size (x72)  
Instruction  
3
1
3
1
3
1
Bypass  
ID  
32  
73  
-
32  
54  
-
32  
-
Boundary Scan Order – 165FBGA  
Boundary Scan Order – 209BGA  
112  
Identification Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the IO ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
010  
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Boundary Scan Exit Order (2M x 36)  
Bit #  
1
165-Ball ID  
C1  
Bit #  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
165-Ball ID  
R3  
Bit #  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
165-Ball ID  
L10  
K11  
J11  
Bit #  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
165-Ball ID  
B8  
A7  
B7  
B6  
A6  
B5  
A5  
A4  
B4  
B3  
A3  
A2  
B2  
2
D1  
P2  
3
E1  
R4  
4
D2  
P6  
K10  
J10  
5
E2  
R6  
6
F1  
N6  
H11  
G11  
F11  
7
G1  
F2  
P11  
R8  
8
9
G2  
J1  
P3  
E11  
D10  
D11  
C11  
G10  
F10  
E10  
A10  
B10  
A9  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
P4  
K1  
P8  
L1  
P9  
J2  
P10  
R9  
M1  
N1  
R10  
R11  
N11  
M11  
L11  
M10  
K2  
L2  
M2  
R1  
B9  
R2  
A8  
Document #: 38-05282 Rev. *H  
Page 16 of 32  
 
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Boundary Scan Exit Order (4M x 18)  
Bit #  
1
165-Ball ID  
D2  
Bit #  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
165-Ball ID  
R8  
Bit #  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
165-Ball ID  
C11  
A11  
A10  
B10  
A9  
2
E2  
P3  
3
F2  
P4  
4
G2  
P8  
5
J1  
P9  
6
K1  
P10  
R9  
B9  
7
L1  
A8  
8
M1  
N1  
R10  
R11  
M10  
L10  
K10  
J10  
H11  
G11  
F11  
E11  
D11  
B8  
9
A7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
R1  
B7  
R2  
B6  
R3  
A6  
P2  
B5  
R4  
A4  
P6  
B3  
R6  
A3  
N6  
A2  
P11  
B2  
Document #: 38-05282 Rev. *H  
Page 17 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Boundary Scan Exit Order (1M x 72)  
Bit #  
1
209-Ball ID  
A1  
Bit #  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
209-Ball ID  
T1  
Bit #  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
209-Ball ID  
V10  
U11  
U10  
T11  
Bit #  
85  
209-Ball ID  
C11  
C10  
B11  
B10  
A11  
A10  
A9  
2
A2  
T2  
86  
3
B1  
U1  
87  
4
B2  
U2  
88  
5
C1  
C2  
D1  
D2  
E1  
V1  
T10  
R11  
R10  
P11  
P10  
N11  
N10  
M11  
M10  
L11  
89  
6
V2  
90  
7
W1  
W2  
T6  
91  
8
92  
U8  
9
93  
A7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
E2  
V3  
94  
A5  
F1  
V4  
95  
A6  
F2  
U4  
96  
D6  
G1  
G2  
H1  
H2  
J1  
W5  
V6  
97  
B6  
98  
D7  
W6  
U3  
L10  
99  
K3  
P6  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
A8  
U9  
J11  
B4  
J2  
V5  
J10  
B3  
L1  
U5  
H11  
H10  
G11  
G10  
F11  
C3  
L2  
U6  
C4  
M1  
M2  
N1  
N2  
P1  
W7  
V7  
C8  
C9  
U7  
B9  
V8  
F10  
E10  
E11  
D11  
D10  
B8  
V9  
A4  
P2  
W11  
W10  
V11  
C6  
R2  
R1  
B7  
A3  
Document #: 38-05282 Rev. *H  
Page 18 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
Exceeding the maximum ratings may impair the useful life of  
the device. These user guidelines are not tested.  
Static Discharge Voltage........................................... >2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch Up Current .................................................... >200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.3V to +3.6V  
DD  
Ambient  
Range  
V
V
DDQ  
DD  
Supply Voltage on V  
Relative to GND ......0.3V to +V  
Temperature  
DDQ  
DD  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
Commercial 0°C to +70°C  
2.5V –5%/+5%  
1.7V to  
+ 0.5V  
V
DDQ  
DD  
Industrial  
–40°C to +85°C  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
2.375  
2.375  
1.7  
Max  
2.625  
Unit  
V
V
V
DD  
V
V
V
V
V
I
for 2.5V IO  
for 1.8V IO  
V
DD  
DDQ  
1.9  
V
Output HIGH Voltage  
Output LOW Voltage  
for 2.5V IO, I = –1.0 mA  
2.0  
V
OH  
OL  
IH  
OH  
for 1.8V IO, I = –100 µA  
1.6  
V
OH  
for 2.5V IO, I = 1.0 mA  
0.4  
0.2  
V
OL  
for 1.8V IO, I = 100 µA  
V
OL  
Input HIGH Voltage  
for 2.5V IO  
for 1.8V IO  
for 2.5V IO  
for 1.8V IO  
1.7  
1.26  
–0.3  
–0.3  
–5  
V
V
+ 0.3V  
+ 0.3V  
0.7  
V
DD  
DD  
V
Input LOW Voltage  
V
IL  
0.36  
5
V
Input Leakage Current GND V V  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4.0-ns cycle, 250 MHz  
5.0-ns cycle, 200 MHz  
6.0-ns cycle, 167 MHz  
4.0-ns cycle, 250 MHz  
5.0-ns cycle, 200 MHz  
6.0-ns cycle, 167 MHz  
All speeds  
450  
450  
400  
200  
200  
200  
120  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
CYC  
Current  
= 1/t  
MAX  
I
Automatic CE  
Power Down  
Current—TTL Inputs  
V = Max, Device Deselected,  
DD  
SB1  
V
V or V V  
IN  
IH  
IN  
IL  
f = f  
= 1/t  
MAX CYC  
I
I
Automatic CE  
Power Down  
Current—CMOS Inputs f = 0  
V = Max, Device Deselected,  
DD  
SB2  
V
0.3V or V > V – 0.3V,  
IN  
IN  
DDQ  
Automatic CE  
Power Down  
Current—CMOS Inputs f = f  
V
V
= Max, Device Deselected, or 4.0-ns cycle, 250 MHz  
200  
200  
200  
135  
mA  
mA  
mA  
mA  
SB3  
DD  
0.3V or V > V  
– 0.3V  
IN  
IN  
DDQ  
5.0-ns cycle, 200 MHz  
6.0-ns cycle, 167 MHz  
All speeds  
= 1/t  
MAX  
CYC  
I
Automatic CE  
V = Max, Device Deselected,  
DD  
SB4  
Power Down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN  
IH IN IL  
Notes  
12. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
13. Power up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05282 Rev. *H  
Page 19 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Capacitance[14]  
100 TQFP 165 FBGA 209 FBGA  
Parameter  
Description  
Test Conditions  
Unit  
Package  
Package  
Package  
C
C
C
C
C
Address Input Capacitance  
Data Input Capacitance  
Control Input Capacitance  
Clock Input Capacitance  
Input/Output Capacitance  
T = 25°C, f = 1 MHz,  
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF  
pF  
pF  
pF  
pF  
ADDRESS  
DATA  
CTRL  
CLK  
A
V
= 2.5V  
= 2.5V  
DD  
V
DDQ  
I/O  
Thermal Resistance[14]  
100 TQFP  
Max.  
165 FBGA 209 FBGA  
Parameter  
Description  
Test Conditions  
Unit  
Max.  
Max.  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow  
standard test methods and  
procedures for measuring  
thermal impedance, per  
EIA/JESD51.  
24.63  
16.3  
15.2  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
2.28  
2.1  
1.7  
°C/W  
JC  
AC Test Loads and Waveforms  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
GND  
5 pF  
R = 1583Ω  
1 ns  
1 ns  
V = 1.25V  
L
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
1.8V I/O Test Load  
R = 14KΩ  
1.8V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ-0.2  
0.2  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 14KΩ  
1 ns  
1 ns  
V = 0.9V  
L
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Note  
14. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05282 Rev. *H  
Page 20 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Switching Characteristics Over the Operating Range  
250 MHz  
200 MHz  
167 MHz  
Unit  
Parameter  
Description  
Min. Max. Min. Max. Min. Max.  
t
V
(Typical) to the first access  
1
1
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
4.0  
2.0  
2.0  
5.0  
2.0  
2.0  
6.0  
2.4  
2.4  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
3.0  
3.0  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
1.3  
1.3  
1.3  
1.3  
1.5  
1.5  
DOH  
CLZ  
Clock to Low-Z  
Clock to High-Z  
3.0  
3.0  
3.0  
3.0  
3.4  
3.4  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
OE LOW to Output Low-Z  
0
0
0
OE HIGH to Output High-Z  
3.0  
3.0  
3.4  
Setup Times  
t
t
t
t
t
t
Address Setup Before CLK Rise  
ADSC, ADSP Setup Before CLK Rise  
ADV Setup Before CLK Rise  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ADS  
ADVS  
WES  
DS  
GW, BWE, BW Setup Before CLK Rise  
X
Data Input Setup Before CLK Rise  
Chip Enable Setup Before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
ADSP, ADSC Hold After CLK Rise  
ADV Hold After CLK Rise  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ADH  
ADVH  
WEH  
DH  
GW, BWE, BW Hold After CLK Rise  
X
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
CEH  
Notes  
15. Timing reference level is 1.25V when V  
= 2.5V and is 0.9V when V  
= 1.8V.  
DDQ  
DDQ  
16. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted.  
17. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation  
POWER  
DD  
can be initiated.  
18. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from  
CHZ CLZ OELZ  
OEHZ  
steady-state voltage.  
19. At any possible voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
OEHZ  
OELZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z before Low-Z under the same system conditions.  
20. This parameter is sampled and not 100% tested.  
Document #: 38-05282 Rev. *H  
Page 21 of 32  
           
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Switching Waveforms  
Read Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BWx  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
t
CHZ  
OELZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2  
+
1)  
Q(A2  
+
2)  
Q(A2  
+
3)  
Q(A2)  
Q(A2  
+
1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note  
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05282 Rev. *H  
Page 22 of 32  
 
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Switching Waveforms (continued)  
Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
ADDRESS  
BWE,  
t
t
AH  
AS  
A1  
A2  
A3  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BW  
X
t
t
WEH  
WES  
GW  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2  
+
1)  
D(A2  
+
1)  
D(A2  
+
2)  
D(A2  
+
3)  
D(A3)  
D(A3  
+
1)  
D(A3  
+
2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note  
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.  
X
Document #: 38-05282 Rev. *H  
Page 23 of 32  
 
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Switching Waveforms (continued)  
Read/Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
BWE, BW  
t
t
WEH  
WES  
X
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes  
23. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.  
24. GW is HIGH.  
Document #: 38-05282 Rev. *H  
Page 24 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Switching Waveforms (continued)  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes  
25. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.  
26. DQs are in high-Z when exiting ZZ sleep mode.  
Document #: 38-05282 Rev. *H  
Page 25 of 32  
   
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Part and Package Type  
Ordering Code  
167 CY7C1480V25-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
CY7C1482V25-167AXC  
Commercial  
CY7C1480V25-167BZC  
CY7C1482V25-167BZC  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1480V25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
CY7C1482V25-167BZXC  
CY7C1486V25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1486V25-167BGXC  
CY7C1480V25-167AXI  
CY7C1482V25-167AXI  
CY7C1480V25-167BZI  
CY7C1482V25-167BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
lndustrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1480V25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
CY7C1482V25-167BZXI  
CY7C1486V25-167BGI  
CY7C1486V25-167BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
200 CY7C1480V25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
CY7C1482V25-200AXC  
Commercial  
CY7C1480V25-200BZC  
CY7C1482V25-200BZC  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1480V25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
CY7C1482V25-200BZXC  
CY7C1486V25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1486V25-200BGXC  
CY7C1480V25-200AXI  
CY7C1482V25-200AXI  
CY7C1480V25-200BZI  
CY7C1482V25-200BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
lndustrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1480V25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
CY7C1482V25-200BZXI  
CY7C1486V25-200BGI  
CY7C1486V25-200BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
Document #: 38-05282 Rev. *H  
Page 26 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Part and Package Type  
Ordering Code  
250 CY7C1480V25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1482V25-250AXC  
Commercial  
CY7C1480V25-250BZC  
CY7C1482V25-250BZC  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1480V25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1482V25-250BZXC  
CY7C1486V25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1486V25-250BGXC  
CY7C1480V25-250AXI  
CY7C1482V25-250AXI  
CY7C1480V25-250BZI  
CY7C1482V25-250BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1480V25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1482V25-250BZXI  
CY7C1486V25-250BGI  
CY7C1486V25-250BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
Document #: 38-05282 Rev. *H  
Page 27 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Package Diagrams  
Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
1.00 REF.  
51-85050-*B  
DETAIL  
A
Document #: 38-05282 Rev. *H  
Page 28 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Package Diagrams (continued)  
Figure 2. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165  
PIN 1 CORNER  
BOTTOM VIEW  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
1
Ø0.25 M C A B  
Ø0.45 0.05(165X)  
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00  
5.00  
10.00  
B
15.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85165-*A  
Document #: 38-05282 Rev. *H  
Page 29 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Package Diagrams (continued)  
Figure 3. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167  
51-85167-**  
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names  
mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05282 Rev. *H  
Page 30 of 32  
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the  
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to  
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Document History Page  
Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM  
Document Number: 38-05282  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
**  
114670  
118281  
08/06/02  
01/21/03  
PKS  
New Data Sheet  
*A  
HGK  
Changed t from 2.4 to 2.6 ns for 250 MHz  
CO  
Updated features on page 1 for package offering  
Removed 300 MHz offering  
Updated Ordering Information  
Changed Advanced Information to Preliminary  
*B  
233368 See ECN  
NJY  
Changed timing diagrams  
Changed logic block diagrams  
Modified Functional Description  
Modified “Functional Overview” section  
Added boundary scan order for all packages  
Included thermal numbers and capacitance values for all packages  
Included IDD and ISB values  
Removed 250-MHz speed grade offering and included 225 MHz speed bin  
Changed package outline for 165FBGA package and 209-ball BGA package  
Removed 119-BGA package offering  
*C  
*D  
299452 See ECN  
SYT  
Removed 225-MHz offering and included 250-MHz speed bin  
Changed t  
from 4.4 ns to 4.0 ns for 250-MHz Speed Bin  
CYC  
Changed Θ from 16.8 to 24.63 °C/W and Θ from 3.3 to 2.28 °C/W for 100  
JA  
JC  
TQFP Package on Page # 20  
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA  
Packages  
Added comment of ‘Lead-free BG packages availability’ below the Ordering  
Information  
323039 See ECN  
PCI  
Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection  
Guide  
Address expansion pins/balls in the pinouts for all packages are modified as  
per JEDEC standard  
Added Address Expansion pins in the Pin Definitions Table  
Added Truth Table and Note# 7 for CY7C1486V25 on page# 11  
Modified V , V Test Conditions  
OL  
OH  
Added Industrial temperature range  
Removed comment of ‘Lead-free BG packages availability’ below the  
Ordering Information  
Updated Ordering Information Table  
*E  
416193 See ECN  
NXR  
Converted from Preliminary to Final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed the description of I from Input Load Current to Input Leakage  
X
Current on page# 19  
Changed the I current values of MODE on page # 19 from -5 µA and 30 µA  
X
to -30 µA and 5 µA  
Changed the I current values of ZZ on page # 19 from -30 µA and 5 µA  
X
to -5 µA and 30 µA  
Changed V < V to V < V on page # 19  
IH  
DD  
IH  
DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Updated the Ordering Information Table  
*F  
470723 See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP  
TH TL  
TDOV  
AC Switching Characteristics table  
Updated the Ordering Information table  
Document #: 38-05282 Rev. *H  
Page 31 of 32  
CY7C1480V25  
CY7C1482V25  
CY7C1486V25  
Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM  
Document Number: 38-05282  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
*G  
486690 See ECN  
VKN  
Corrected the typo in the 209-Ball FBGA pinout.  
(Corrected the ball name H9 to V from V  
).  
SS  
SSQ  
*H  
1026720 See ECN VKN/KKVTMP Added footnote #2 related to V  
SSQ  
Document #: 38-05282 Rev. *H  
Page 32 of 32  

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