Cypress CY7C1471V33 User Manual

CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
72-Mbit (2M x 36/4M x 18/1M x 72)  
Flow-ThroughSRAMwithNoBLArchitecture  
Functional Description [1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates dead  
cycles between write and read cycles  
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are  
3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst  
SRAMs designed specifically to support unlimited true  
back-to-back read or write operations without the insertion of  
wait states. The CY7C1471V33, CY7C1473V33 and  
CY7C1475V33 are equipped with the advanced No Bus  
Latency (NoBL) logic required to enable consecutive read or  
write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of  
data through the SRAM, especially in systems that require  
frequent write-read transitions.  
• Supportsupto133MHzbusoperationswithzerowaitstates  
• Data is transferred on every clock  
• PincompatibleandfunctionallyequivalenttoZBTdevices  
• Internally self timed output buffer control to eliminate the  
need to use OE  
• Registered inputs for flow through operation  
• Byte Write capability  
• 3.3V/2.5V IO supply (V  
)
DDQ  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock  
cycle.Maximum access delay from the clock rise is 6.5 ns  
(133-MHz device).  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
• Synchronous self timed writes  
Write operations are controlled by two or four Byte Write Select  
• Asynchronous Output Enable (OE)  
(BW ) and a Write Enable (WE) input. All writes are conducted  
X
with on-chip synchronous self timed write circuitry.  
• CY7C1471V33, CY7C1473V33 available in  
JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and  
non-Pb-free 165-Ball FBGA package. CY7C1475V33  
available in Pb-free and non-Pb-free 209-Ball FBGA  
package  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
• Three Chip Enables (CE , CE , CE ) for simple depth  
1
2
3
expansion  
• Automatic power down feature available using ZZ mode or  
CE deselect  
• IEEE 1149.1 JTAG Boundary Scan compatible  
• Burst Capability — linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
6.5  
117 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
305  
275  
mA  
mA  
120  
120  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05288 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 04, 2007  
 
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Logic Block Diagram – CY7C1475V33 (1M x 72)  
ADDRESS  
REGISTER  
A0, A1,  
A
0
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
CLK  
CEN  
C
WRITE ADDRESS  
WRITE ADDRESS  
REGISTER  
1
REGISTER  
2
O
U
T
O
U
T
P
U
T
S
E
N
S
E
P
U
T
D
A
T
A
ADV/LD  
BW  
BW  
BW  
BW  
BW  
BW  
BW  
a
R
E
G
I
MEMORY  
ARRAY  
B
U
F
DQ s  
WRITE  
DRIVERS  
b
c
S
T
E
E
R
I
A
M
P
DQ Pa  
DQ Pb  
DQ Pc  
DQ Pd  
DQ Pe  
DQ Pf  
DQ Pg  
DQ Ph  
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
F
S
T
E
R
S
d
e
E
R
S
S
f
N
G
g
E
E
BW  
h
WE  
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
CE1  
CE2  
CE3  
READ LOGIC  
Sleep Control  
ZZ  
Document #: 38-05288 Rev. *J  
Page 3 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Pin Configurations  
100-Pin TQFP Pinout  
DQPC  
DQC  
DQC  
VDDQ  
VSS  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
1
DQPB  
DQB  
DQB  
VDDQ  
VSS  
2
3
4
5
DQC  
6
DQB  
BYTE C  
BYTE B  
DQB  
DQC  
DQC  
DQC  
VSS  
7
8
DQB  
DQB  
VSS  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
DQC  
DQC  
NC  
VDDQ  
DQB  
DQB  
VSS  
CY7C1471V33  
VDD  
NC  
NC  
VDD  
ZZ  
VSS  
DQD  
DQD  
VDDQ  
VSS  
DQA  
DQA  
VDDQ  
VSS  
DQD  
DQA  
DQD  
DQA  
BYTE D  
BYTE A  
DQA  
DQD  
DQD  
VSS  
DQA  
VSS  
VDDQ  
DQD  
DQD  
DQPD  
VDDQ  
DQA  
DQA  
DQPA  
Document #: 38-05288 Rev. *J  
Page 4 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Pin Configurations (continued)  
100-Pin TQFP Pinout  
NC  
1
NC  
2
NC  
3
VDDQ  
4
VSS  
5
NC  
6
NC  
7
DQB  
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A
NC  
NC  
VDDQ  
VSS  
NC  
DQPA  
DQA  
DQA  
VSS  
VDDQ  
DQA  
DQA  
VSS  
DQB  
9
VSS  
10  
VDDQ  
11  
DQB  
DQB  
NC  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
CY7C1473V33  
BYTE A  
NC  
VDD  
NC  
BYTE B  
VDD  
ZZ  
VSS  
DQB  
DQB  
VDDQ  
VSS  
DQB  
DQB  
DQPB  
NC  
DQA  
DQA  
VDDQ  
VSS  
DQA  
DQA  
NC  
NC  
VSS  
VDDQ  
NC  
VSS  
VDDQ  
NC  
NC  
NC  
NC  
NC  
Document #: 38-05288 Rev. *J  
Page 5 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Pin Configurations (continued)  
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout  
CY7C1471V33 (2M x 36)  
1
2
A
3
CE1  
4
BWC  
5
BWB  
6
CE  
7
8
9
A
10  
A
11  
NC  
NC/576M  
NC/1G  
DQPC  
DQC  
CEN  
WE  
VSS  
VSS  
ADV/LD  
A
B
C
D
3
A
CE2  
VDDQ  
VDDQ  
BWD  
VSS  
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
A
A
NC  
NC  
DQC  
VDDQ  
VDDQ  
NC  
DQPB  
DQB  
VDD  
DQB  
DQC  
DQC  
DQC  
NC  
DQC  
DQC  
DQC  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQB  
DQB  
DQB  
NC  
DQB  
DQB  
DQB  
ZZ  
E
F
G
H
J
DQD  
DQD  
DQD  
DQD  
DQD  
DQD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
DQA  
DQA  
DQA  
K
L
DQD  
DQPD  
DQD  
NC  
A
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
M
N
P
NC/144M  
TDI  
TDO  
NC/288M  
A0  
MODE  
A
A
A
TMS  
TCK  
A
A
A
A
R
CY7C1473V33 (4M x 18)  
1
NC/576M  
NC/1G  
NC  
2
A
3
CE1  
4
BWB  
5
NC  
6
CE  
7
8
9
A
10  
A
11  
A
CEN  
WE  
VSS  
VSS  
ADV/LD  
A
B
C
D
3
A
CE2  
VDDQ  
VDDQ  
NC  
VSS  
VDD  
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
A
A
NC  
NC  
DQB  
VDDQ  
VDDQ  
NC  
NC  
DQPA  
DQA  
NC  
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQA  
DQA  
DQA  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
NC  
NC  
NC  
K
L
NC  
NC  
DQB  
DQPB  
NC  
NC  
A
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
NC  
NC  
M
N
P
NC/144M  
TDI  
TDO  
NC/288M  
A0  
MODE  
A
A
A
TMS  
TCK  
A
A
A
A
R
Document #: 38-05288 Rev. *J  
Page 6 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Pin Configurations (continued)  
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout  
CY7C1475V33 (1M × 72)  
1
2
3
4
5
6
7
8
9
10  
11  
DQg  
DQg  
DQg  
DQg  
DQg  
DQg  
DQg  
DQg  
DQPc  
DQc  
DQc  
A
CE  
A
ADV/LD  
WE  
A
A
CE  
A
DQb  
DQb  
DQb  
DQb  
DQb  
DQb  
A
B
2
3
BWS  
BWS  
BWS  
NC  
BWS  
BWS  
NC  
BWS  
BWS  
c
g
b
e
f
BWS NC/576M CE  
NC  
NC  
C
D
h
d
1
a
V
NC/1G  
OE  
V
NC  
SS  
DQb  
SS  
DQb  
DQPb  
DQf  
E
F
DQPg  
DQc  
V
DDQ  
V
V
V
V
V
V
DD  
DDQ  
DDQ  
DDQ  
DD  
DD  
DQPf  
DQf  
V
V
V
V
V
NC  
NC  
NC  
NC  
CEN  
NC  
NC  
V
SS  
SS  
SS  
SS  
SS  
SS  
G
H
J
DQc  
DQc  
V
V
V
V
V
V
V
DD  
DDQ  
DDQ  
DQf  
DQf  
DD  
DDQ  
DQf  
DDQ  
V
V
V
V
V
V
V
DQc  
DQc  
NC  
SS  
SS  
SS  
SS  
SS  
SS  
DQf  
DQf  
NC  
V
DQc  
NC  
V
V
V
DDQ  
DD  
DD  
DDQ  
DDQ  
DDQ  
DQf  
NC  
K
L
CLK  
V
V
NC  
SS  
SS  
DD  
NC  
NC  
DQh  
DQh  
DQh  
V
V
V
V
DDQ  
V
V
DDQ  
DD  
DDQ  
DQa  
DQa  
DQa  
DDQ  
M
N
P
R
T
V
V
V
V
V
SS  
DQh  
DQh  
DQh  
V
V
SS  
SS  
SS  
SS  
SS  
DQa  
DQa  
DQa  
V
V
V
DQh  
DQh  
DQPd  
DQd  
DQd  
V
V
V
NC  
ZZ  
DD  
DD  
DDQ  
DDQ  
DDQ  
DDQ  
DQa  
DQa  
DQPa  
DQe  
DQe  
V
V
V
V
V
V
SS  
SS  
SS  
SS  
DD  
SS  
SS  
V
V
V
V
DQPh  
DQd  
DQd  
DQd  
DQd  
V
V
DDQ  
DD  
DDQ  
DDQ  
DDQ  
DD  
DQPe  
DQe  
DQe  
DQe  
DQe  
V
NC  
A
V
NC  
A
NC  
A
NC  
A
MODE  
A
SS  
SS  
U
V
W
NC/288M  
NC/144M  
A
A
A1  
A
DQd  
DQd  
A
A
A
A
DQe  
DQe  
TDI  
TDO  
TCK  
A0  
A
TMS  
Document #: 38-05288 Rev. *J  
Page 7 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Pin Definitions  
Name  
IO  
Description  
Address Inputs used to select one of the address locations. Sampled at the rising edge  
A , A , A  
Input-  
0
1
Synchronous of the CLK. A  
are fed to the two-bit burst counter.  
[1:0]  
BW , BW ,  
Input-  
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.  
A
B
BW , BW ,  
Synchronous Sampled on the rising edge of CLK.  
C
D
BW , BW ,  
E
F
BW , BW  
G
H
WE  
Input-  
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.  
Synchronous This signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input-  
Advance/Load Input. Advances the on-chip address counter or loads a new address.  
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When  
LOW, a new address can be loaded into the device for an access. After being deselected,  
ADV/LD should must driven LOW to load a new address.  
CLK  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with  
CEN. CLK is only recognized if CEN is active LOW.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction  
1
2
3
Synchronous with CE and CE to select or deselect the device.  
2
3
Input-  
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in  
Synchronous conjunction with CE and CE to select or deselect the device.  
1
3
Input-  
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select or deselect the device.  
1
2
OE  
Input-  
OutputEnable, Asynchronous Input, Active LOW. Combined with the synchronous logic  
Asynchronous block inside the device to control the direction of the IO pins. When LOW, the IO pins are  
enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as  
input data pins. OE is masked during the data portion of a write sequence, during the first  
clock when emerging from a deselected state, when the device is deselected.  
CEN  
ZZ  
Input-  
Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by  
Synchronous the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN  
does not deselect the device, use CEN to extend the previous cycle when required.  
Input-  
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”  
Asynchronous condition with data integrity preserved. During normal operation, this pin must be LOW or  
left floating. ZZ pin has an internal pull down.  
DQ  
IO-  
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
memory location specified by the addresses presented during the previous  
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is  
s
clock rise of the  
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the  
pins behave as outputs. When HIGH, DQ and DQP are placed in a tri-state condition.The  
s
X
outputs are automatically tri-stated during the data portion of a write sequence, during the  
first clock when emerging from a deselected state, and when the device is deselected,  
regardless of the state of OE.  
DQP  
IO-  
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ .During  
X
s
Synchronous write sequences, DQP is controlled by BW correspondingly.  
X
X
MODE  
Input Strap Pin Mode Input. Selects the burst order of the device.  
When tied to Gnd selects linear burst sequence. When tied to V or left floating selects  
DD  
interleaved burst sequence.  
V
V
V
Power Supply Power supply inputs to the core of the device.  
IO Power Supply Power supply for the IO circuitry.  
Ground Ground for the device.  
DD  
DDQ  
SS  
Document #: 38-05288 Rev. *J  
Page 8 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Pin Definitions (continued)  
Name  
IO  
Description  
TDO  
JTAG serial  
output  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the  
JTAG feature is not used, this pin must be left unconnected. This pin is not available on  
Synchronous TQFP packages.  
TDI  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature  
Synchronous is not used, this pin can be left floating or connected to V through a pull up resistor. This  
DD  
pin is not available on TQFP packages.  
TMS  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature  
Synchronous is not used, this pin can be disconnected or connected to V . This pin is not available on  
DD  
TQFP packages.  
TCK  
NC  
JTAG  
-Clock  
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be  
connected to V . This pin is not available on TQFP packages.  
SS  
-
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address  
expansion pins and are not internally connected to the die.  
the output buffers. The data is available within 6.5 ns  
(133-MHz device) provided OE is active LOW. After the first  
Functional Overview  
The CY7C1471V33, CY7C1473V33, and CY7C1475V33 are  
synchronous flow through burst SRAMs designed specifically  
to eliminate wait states during write-read transitions. All  
synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock signal is qualified with  
the Clock Enable input signal (CEN). If CEN is HIGH, the clock  
signal is not recognized and all internal states are maintained.  
All synchronous operations are qualified with CEN. Maximum  
clock of the read access, the output buffers are controlled by  
OE and the internal control logic. OE must be driven LOW to  
drive out the requested data. On the subsequent clock,  
another operation (read/write/deselect) can be initiated. When  
the SRAM is deselected at clock rise by one of the chip enable  
signals, output is be tri-stated immediately.  
Burst Read Accesses  
access delay from the clock rise (t  
device).  
) is 6.5 ns (133-MHz  
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have  
an on-chip burst counter that enables the user to supply a  
single address and conduct up to four reads without  
reasserting the address inputs. ADV/LD must be driven LOW  
to load a new address into the SRAM, as described in the  
Single Read Access section. The sequence of the burst  
counter is determined by the MODE input signal. A LOW input  
on MODE selects a linear burst mode, a HIGH selects an inter-  
leaved burst sequence. Both burst counters use A0 and A1 in  
the burst sequence, and wraps around when incremented  
sufficiently. A HIGH input on ADV/LD increments the internal  
burst counter regardless of the state of chip enable inputs or  
WE. WE is latched at the beginning of a burst cycle. Therefore,  
the type of access (read or write) is maintained throughout the  
burst sequence.  
CDV  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If (CEN)  
1
2
3
is active LOW and ADV/LD is asserted LOW, the address  
presented to the device is latched. The access can either be  
a read or write operation, depending on the status of the Write  
Enable (WE). Byte Write Select (BW ) can be used to conduct  
X
Byte Write operations.  
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self timed write  
circuitry.  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (reads, writes, and deselects) are pipelined.  
ADV/LD must be driven LOW after the device is deselected to  
load a new address for the next operation.  
Single Write Accesses  
Write accesses are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
Single Read Accesses  
and CE are ALL asserted active, and (3) WE is asserted  
3
A read access is initiated when these conditions are satisfied  
at clock rise:  
LOW. The address presented to the address bus is loaded into  
the Address Register. The Write signals are latched into the  
Control Logic block. The data lines are automatically tri-stated  
regardless of the state of the OE input signal. This allows the  
• CEN is asserted LOW  
• CE , CE , and CE are ALL asserted active  
1
2
3
external logic to present the data on DQs and DQP .  
X
• WE is deasserted HIGH  
• ADV/LD is asserted LOW.  
On the next clock rise the data presented to DQs and DQP  
X
(or a subset for Byte Write operations, see “Truth Table for  
Read/Write” on page 12 for details) inputs is latched into the  
device and the write is complete. Additional accesses  
(read/write/deselect) can be initiated on this cycle.  
The address presented to the address inputs is latched into  
the Address Register and presented to the memory array and  
control logic. The control logic determines that a read access  
is in progress and allows the requested data to propagate to  
Document #: 38-05288 Rev. *J  
Page 9 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
The data written during the write operation is controlled by  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
BW signals. The CY7C1471V33, CY7C1473V33, and  
X
)
CY7C1475V33 provides Byte Write capability that is described  
First  
Address  
A1: A0  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
with the selected BW input selectively writes to only the  
X
desired bytes. Bytes not selected during a Byte Write  
operation remain unaltered. A synchronous self timed write  
mechanism has been provided to simplify the write operations.  
Byte write capability is included to greatly simplify  
read/modify/write sequences, which can be reduced to simple  
byte write operations.  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Because  
the  
CY7C1471V33,  
CY7C1473V33,  
and  
CY7C1475V33 are common IO devices, data must not be  
driven into the device while the outputs are active. The Output  
Enable (OE) can be deasserted HIGH before presenting data  
Linear Burst Address Table  
(MODE = GND)  
to the DQs and DQP inputs. Doing so tri-states the output  
First  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
X
drivers. As a safety precaution, DQs and DQP are automati-  
Address  
A1: A0  
X
cally tri-stated during the data portion of a write cycle,  
regardless of the state of OE.  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
Burst Write Accesses  
The CY7C1471V33, CY7C1473V33, and CY7C1475V33  
have an on-chip burst counter that enables the user to supply  
a single address and conduct up to four write operations  
without reasserting the address inputs. ADV/LD must be  
driven LOW to load the initial address, as described in the  
Single Write Access section. When ADV/LD is driven HIGH on  
the subsequent clock rise, the Chip Enables (CE , CE , and  
1
2
CE ) and WE inputs are ignored and the burst counter is incre-  
3
mented. The correct BW inputs must be driven in each cycle  
X
of the burst write to write the correct bytes of data.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected before entering  
the “sleep” mode. CE , CE , and CE , must remain inactive  
1
2
3
for the duration of t  
after the ZZ input returns LOW.  
ZZREC  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
Test Conditions  
ZZ > V – 0.2V  
Min  
Max  
120  
Unit  
mA  
ns  
I
t
t
t
t
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Document #: 38-05288 Rev. *J  
Page 10 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Truth Table  
[2, 3, 4, 5, 6, 7, 8]  
The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.  
Address  
Operation  
Deselect Cycle  
CE CE  
ZZ ADV/LD  
WE  
BW  
X
OE  
CEN CLK  
DQ  
CE  
1
2
3
Used  
None  
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H  
L->H  
L->H  
L->H  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Deselect Cycle  
None  
Deselect Cycle  
None  
Continue Deselect Cycle  
None  
X
H
Read Cycle  
External  
L->H Data Out (Q)  
(Begin Burst)  
Read Cycle  
(Continue Burst)  
Next  
External  
Next  
X
L
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
H
L
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
L
L
L
L
L
L
L
L->H Data Out (Q)  
NOP/Dummy Read  
(Begin Burst)  
L->H  
L->H  
Tri-State  
Tri-State  
Dummy Read  
(Continue Burst)  
X
L
X
L
H
L
Write Cycle  
(Begin Burst)  
External  
Next  
L->H Data In (D)  
L->H Data In (D)  
Write Cycle  
(Continue Burst)  
X
L
X
L
H
L
X
L
L
NOP/Write Abort  
(Begin Burst)  
None  
H
H
L->H  
L->H  
Tri-State  
Tri-State  
Write Abort  
Next  
X
X
H
X
(Continue Burst)  
Ignore Clock Edge (Stall)  
Sleep Mode  
Current  
None  
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
X
L->H  
X
-
H
Tri-State  
Notes  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = L signifies at least one Byte Write Select is active, BW = Valid signifies that the desired Byte Write  
X
X
Selects are asserted, see “Truth Table for Read/Write” on page 12 for details.  
3. Write is defined by BW , and WE. See “Truth Table for Read/Write” on page 12.  
X
4. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.  
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
X
6. CEN = H, inserts wait states.  
7. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = tri-state when OE  
X
is inactive or when the device is deselected, and DQs and DQP = data when OE is active.  
X
Document #: 38-05288 Rev. *J  
Page 11 of 32  
               
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Truth Table for Read/Write  
The read-write truth table for CY7C1471V33 follows.  
Function  
WE  
H
L
BW  
BW  
X
BW  
X
BW  
X
A
B
C
D
Read  
X
H
L
Write No bytes written  
H
H
L
H
H
H
L
H
H
H
H
L
Write Byte A – (DQ and DQP )  
L
A
A
Write Byte B – (DQ and DQP )  
L
H
H
H
L
B
B
Write Byte C – (DQ and DQP )  
L
H
H
L
C
C
Write Byte D – (DQ and DQP )  
L
H
L
D
D
Write All Bytes  
L
L
Truth Table for Read/Write  
The read-write truth table for CY7C1473V33 follows.  
Function  
WE  
H
L
BW  
X
BW  
a
b
Read  
X
H
L
Write – No Bytes Written  
H
Write Byte a – (DQ and DQP )  
L
H
a
a
Write Byte b – (DQ and DQP )  
L
L
H
L
b
b
Write Both Bytes  
L
L
Truth Table for Read/Write  
The read-write truth table for CY7C1475V33 follows.  
Function  
WE  
H
BW  
X
x
Read  
Write – No Bytes Written  
Write Byte X (DQ and DQP  
L
H
L
L
x
x)  
Write All Bytes  
L
All BW = L  
Note  
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is based on which byte write is active.  
X
Document #: 38-05288 Rev. *J  
Page 12 of 32  
   
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Test Access Port (TAP)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
Test Clock (TCK)  
The CY7C1471V33, CY7C1473V33, and CY7C1475V33  
incorporate a serial boundary scan test access port (TAP).  
This port operates in accordance with IEEE Standard  
1149.1-1990 but does not have the set of functions required  
for full 1149.1 compliance. These functions from the IEEE  
specification are excluded because their inclusion places an  
added delay in the critical speed path of the SRAM. Note that  
the TAP controller functions in a manner that does not conflict  
with the operation of other devices using 1149.1 fully compliant  
TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V  
IO logic levels.  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Test MODE SELECT (TMS)  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
Test Data-In (TDI)  
The CY7C1471V33, CY7C1473V33, and CY7C1475V33  
contain a TAP controller, instruction register, boundary scan  
register, bypass register, and ID register.  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. For  
information about loading the instruction register, see the TAP  
Controller State Diagram. TDI is internally pulled up and can  
be unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) of any register.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V through a pull up resistor. TDO must be  
DD  
left unconnected. During power up, the device comes up in a  
reset state, which does not interfere with the operation of the  
device.  
Test Data-Out (TDO)  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See TAP Controller State Diagram.)  
TAP Controller State Diagram  
TEST-LOGIC  
1
RESET  
0
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
TAP Controller Block Diagram  
0
0
0
1
1
0
CAPTURE-DR  
CAPTURE-IR  
Bypass Register  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
2
1
0
0
0
Selection  
Circuitry  
Selection  
Circuitry  
1
1
Instruction Register  
31 30 29  
Identification Register  
TDI  
TDO  
1
1
EXIT1-DR  
EXIT1-IR  
.
.
.
2
1
0
0
PAUSE-DR  
0
PAUSE-IR  
1
0
x
.
.
.
.
.
2
1
1
Boundary Scan Register  
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
TCK  
TAP CONTROLLER  
1
0
1
0
TM S  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
Performing a TAP Reset  
A RESET is performed by forcing TMS HIGH (V ) for five  
DD  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
During power up, the TAP is reset internally to ensure that  
TDO comes up in a High-Z state.  
Document #: 38-05288 Rev. *J  
Page 13 of 32  
   
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
TAP Registers  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented.  
Registers are connected between the TDI and TDO balls and  
enable data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
The TAP controller cannot be used to load address data or  
control signals into the SRAM and cannot preload the IO  
buffers. The SRAM does not implement the 1149.1 commands  
EXTEST or INTEST or the PRELOAD portion of  
SAMPLE/PRELOAD; rather, it performs a capture of the IO  
ring when these instructions are executed.  
nstruction Register  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the “TAP Controller Block  
Diagram” on page 13. During power up, the instruction register  
is loaded with the IDCODE instruction. It is also loaded with  
the IDCODE instruction if the controller is placed in a reset  
state as described in the previous section.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction after it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
EXTEST  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary ‘01’ pattern to  
enable fault isolation of the board-level serial test data path.  
EXTEST is a mandatory 1149.1 instruction which is to be  
executed whenever the instruction register is loaded with all  
0s. EXTEST is not implemented in this SRAM TAP controller,  
and therefore this device is not compliant to 1149.1. The TAP  
controller does recognize an all-0 instruction.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
When an EXTEST instruction is loaded into the instruction  
register, the SRAM responds as if a SAMPLE/PRELOAD  
instruction has been loaded. There is one difference between  
the two instructions. Unlike the SAMPLE/PRELOAD  
instruction, EXTEST places the SRAM outputs in a High-Z  
state.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
IDCODE  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and  
enables the IDCODE to be shifted out of the device when the  
TAP controller enters the Shift-DR state.  
The boundary scan register is loaded with the contents of the  
RAM IO ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the IO ring.  
The IDCODE instruction is loaded into the instruction register  
during power up or whenever the TAP controller is in a test  
logic reset state.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in “Identification Register Defini-  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The  
PRELOAD portion of this instruction is not implemented, so  
the device TAP controller is not fully 1149.1 compliant.  
When the SAMPLE/PRELOAD instruction is loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and bidirectional balls  
is captured in the boundary scan register.  
TAP Instruction Set  
Overview  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
may undergo a transition. The TAP may then try to capture a  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in “Identification  
Codes” on page 18. Three of these instructions are listed as  
RESERVED and must not be used. The other five instructions  
are described in detail below.  
Document #: 38-05288 Rev. *J  
Page 14 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
signal while in transition (metastable state). This does not  
harm the device, but there is no guarantee as to the value that  
is captured. Repeatable results may not be possible.  
Note that since the PRELOAD part of the command is not  
implemented, putting the TAP to the Update-DR state while  
performing a SAMPLE/PRELOAD instruction has the same  
effect as the Pause-DR command.  
To guarantee that the boundary scan register captures the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller’s capture setup plus  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
hold time (t plus t ).  
CS  
CH  
The SRAM clock input might not be captured correctly if there  
is no way in a design to stop (or slow) the clock during a  
SAMPLE/PRELOAD instruction. If this is an issue, it is still  
possible to capture all other signals and simply ignore the  
value of the CLK captured in the boundary scan register.  
Reserved  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO balls.  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TM SS  
TDIS  
TM SH  
Test M ode Select  
(TM S)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
Document #: 38-05288 Rev. *J  
Page 15 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
TAP AC Switching Characteristics  
Over the Operating Range  
Parameter  
Clock  
Description  
Min  
Max  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
5
ns  
ns  
TDOV  
TDOX  
0
Setup Times  
t
t
t
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes  
10.t and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
11.Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05288 Rev. *J  
Page 16 of 32  
   
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ................................................ V to 3.3V  
Input pulse levels.................................................V to 2.5V  
SS  
SS  
Input rise and fall times................................................... 1 ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels......................................... 1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.25V  
1.5V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
20pF  
ZO= 50Ω  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
(0°C < T < +70°C; V = 3.3V ±0.165V unless otherwise noted)  
A
DD  
Parameter  
Description  
Test Conditions  
Min  
2.4  
2.0  
2.9  
2.1  
Max  
Unit  
V
V
V
V
V
V
V
Output HIGH Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
I
I
I
= –4.0 mA, V  
= –1.0 mA, V  
= –100 µA  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
V
V
V
V
V
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
V
OH2  
OL1  
OL2  
IH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
I
I
I
= 8.0 mA  
= 1.0 mA  
= 100 µA  
0.4  
0.4  
0.2  
0.2  
V
OL  
OL  
OL  
V
V
V
2.0  
1.7  
V
V
+ 0.3  
V
DD  
DD  
+ 0.3  
V
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
I
GND < V < V  
DDQ  
µA  
X
IN  
Note  
12. All voltages refer to V (GND).  
SS  
Document #: 38-05288 Rev. *J  
Page 17 of 32  
 
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Identification Register Definitions  
CY7C1471V33 CY7C1473V33 CY7C1475V33  
Instruction Field  
Description  
(2Mx36)  
(4Mx18)  
(1Mx72)  
Revision Number (31:29)  
000  
000  
000  
Describes the version number  
Device Depth (28:24)  
01011  
001001  
01011  
001001  
01011  
001001  
Reserved for internal use  
Architecture/Memory  
Type(23:18)  
Defines memory type and architecture  
Bus Width/Density(17:12)  
100100  
010100  
110100  
Defines width and density  
Cypress JEDEC ID Code (11:1)  
00000110100  
00000110100  
00000110100 EnablesuniqueidentificationofSRAM  
vendor  
ID Register Presence Indicator (0)  
1
1
1
Indicates the presence of an ID  
register  
Scan Register Sizes  
Register Name  
Bit Size (x36)  
Bit Size (x18)  
Bit Size (x72)  
Instruction  
3
1
3
1
3
1
Bypass  
ID  
32  
71  
-
32  
52  
-
32  
-
Boundary Scan Order – 165FBGA  
Boundary Scan Order – 209BGA  
110  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.  
IDCODE  
001 Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011 Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation. This instruction does not implement 1149.1 preload  
function and is therefore not 1149.1 compliant.  
RESERVED  
RESERVED  
BYPASS  
101 Do Not Use: This instruction is reserved for future use.  
110 Do Not Use: This instruction is reserved for future use.  
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Note  
13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.  
Document #: 38-05288 Rev. *J  
Page 18 of 32  
     
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Boundary Scan Exit Order (2M x 36)  
Bit #  
1
165-Ball ID  
C1  
Bit #  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
165-Ball ID  
R3  
Bit #  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
165-Ball ID  
J11  
Bit #  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
165-Ball ID  
B7  
B6  
A6  
B5  
A5  
A4  
B4  
B3  
A3  
A2  
B2  
2
D1  
P2  
K10  
J10  
3
E1  
R4  
4
D2  
P6  
H11  
G11  
F11  
E11  
D10  
D11  
C11  
G10  
F10  
E10  
A9  
5
E2  
R6  
6
F1  
R8  
7
G1  
F2  
P3  
8
P4  
9
G2  
J1  
P8  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
P9  
K1  
P10  
R9  
L1  
J2  
R10  
R11  
N11  
M11  
L11  
M10  
L10  
K11  
M1  
N1  
B9  
K2  
A10  
B10  
A8  
L2  
M2  
R1  
B8  
R2  
A7  
Boundary Scan Exit Order (4M x 18)  
Bit #  
1
165-Ball ID  
Bit #  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
165-Ball ID  
R4  
Bit #  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
165-Ball ID  
L10  
Bit #  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
165-Ball ID  
D2  
E2  
F2  
G2  
J1  
B10  
A8  
B8  
A7  
B7  
B6  
A6  
B5  
A4  
B3  
A3  
A2  
B2  
2
P6  
K10  
J10  
3
R6  
4
R8  
H11  
G11  
F11  
5
P3  
6
K1  
L1  
P4  
7
P8  
E11  
8
M1  
N1  
R1  
R2  
R3  
P2  
P9  
D11  
C11  
A11  
9
P10  
R9  
10  
11  
12  
13  
R10  
R11  
M10  
A9  
B9  
A10  
Document #: 38-05288 Rev. *J  
Page 19 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Boundary Scan Exit Order (1M x 72)  
Bit #  
1
209-Ball ID  
A1  
Bit #  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
209-Ball ID  
T1  
Bit #  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
209-Ball ID  
U10  
T11  
Bit #  
85  
209-Ball ID  
B11  
B10  
A11  
A10  
A7  
2
A2  
T2  
86  
3
B1  
U1  
T10  
R11  
R10  
P11  
P10  
N11  
N10  
M11  
M10  
L11  
87  
4
B2  
U2  
88  
5
C1  
C2  
D1  
D2  
E1  
V1  
89  
6
V2  
90  
A5  
7
W1  
W2  
T6  
91  
A9  
8
92  
U8  
9
93  
A6  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
E2  
V3  
94  
D6  
F1  
V4  
95  
K6  
F2  
U4  
96  
B6  
G1  
G2  
H1  
H2  
J1  
W5  
V6  
L10  
97  
K3  
P6  
98  
A8  
W6  
V5  
J11  
99  
B4  
J10  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
B3  
U5  
H11  
H10  
G11  
G10  
F11  
C3  
J2  
U6  
C4  
L1  
W7  
V7  
C8  
L2  
C9  
M1  
M2  
N1  
N2  
P1  
U7  
B9  
V8  
F10  
E10  
E11  
D11  
D10  
C11  
C10  
B8  
V9  
A4  
W11  
W10  
V11  
V10  
U11  
C6  
B7  
P2  
A3  
R2  
R1  
Document #: 38-05288 Rev. *J  
Page 20 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static Discharge Voltage........................................... >2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch Up Current .................................................... >200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Range  
V
V
DDQ  
DD  
Temperature  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
DD  
DDQ  
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
to V  
+ 0.5V  
DD  
Industrial  
–40°C to +85°C  
DDQ  
Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
3.135  
3.135  
2.375  
2.4  
Max  
Unit  
V
V
3.6  
DD  
V
V
V
V
V
I
For 3.3V IO  
For 2.5V IO  
For 3.3V IO, I = –4.0 mA  
V
V
DDQ  
DD  
2.625  
V
Output HIGH Voltage  
Output LOW Voltage  
V
OH  
OL  
IH  
OH  
For 2.5V IO, I = –1.0 mA  
2.0  
V
OH  
For 3.3V IO, I = 8.0 mA  
0.4  
0.4  
V
OL  
For 2.5V IO, I = 1.0 mA  
V
OL  
Input HIGH Voltage  
For 3.3V IO  
For 2.5V IO  
For 3.3V IO  
For 2.5V IO  
2.0  
1.7  
V
V
+ 0.3V  
V
DD  
DD  
+ 0.3V  
V
Input LOW Voltage  
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
Input Leakage Current GND V V  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DD,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
7.5 ns cycle, 133 MHz  
10 ns cycle, 117 MHz  
305  
275  
200  
200  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
MAX CYC  
Current  
I
I
I
I
Automatic CE  
Power Down  
Current—TTL Inputs  
V = Max, Device Deselected, 7.5 ns cycle, 133 MHz  
DD  
SB1  
V
V or V V  
IN  
IH IN IL  
10 ns cycle, 117 MHz  
f = f  
, inputs switching  
MAX  
Automatic CE  
Power Down  
Current—CMOS Inputs f = 0, inputs static  
V
V
= Max, Device Deselected, All speeds  
0.3V or V > V – 0.3V,  
120  
mA  
SB2  
SB3  
SB4  
DD  
IN  
IN  
DD  
Automatic CE  
Power Down  
Current—CMOS Inputs f = f  
V
V
=Max, DeviceDeselected, or 7.5 ns cycle, 133 MHz  
200  
200  
mA  
mA  
DD  
0.3V or V > V – 0.3V  
IN  
IN  
DDQ  
10 ns cycle, 117 MHz  
, inputs switching  
MAX  
Automatic CE  
Power Down  
Current—TTL Inputs  
V
V
= Max, Device Deselected, All Speeds  
165  
mA  
DD  
V – 0.3V or V  
,
IN  
DD  
IN 0.3V  
f = 0, inputs static  
Notes  
14. Overshoot: V (AC) < V +1.5V (pulse width less than t  
/2). Undershoot: V (AC) > –2V (pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
15. T  
: assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05288 Rev. *J  
Page 21 of 32  
   
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Capacitance  
Tested initially and after any design or process change that may affect these parameters.  
100 TQFP 165 FBGA  
209 BGA  
Unit  
Parameter  
Description  
Test Conditions  
Package  
Package  
Package  
C
C
C
C
C
Address Input Capacitance  
Data Input Capacitance  
Control Input Capacitance  
Clock Input Capacitance  
Input/Output Capacitance  
T = 25°C, f = 1 MHz,  
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF  
pF  
pF  
pF  
pF  
ADDRESS  
DATA  
CTRL  
CLK  
A
V
= 3.3V  
= 2.5V  
DD  
V
DDQ  
IO  
Thermal Resistance  
Tested initially and after any design or process change that may affect these parameters.  
100 TQFP 165 FBGA 209 FBGA  
Parameter  
Description  
Test Conditions  
Unit  
Max  
Max  
Max  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow  
standard test methods  
and procedures for  
measuring thermal  
impedance, according to  
EIA/JESD51.  
24.63  
16.3  
15.2  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
2.28  
2.1  
1.7  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V IO Test Load  
R = 317Ω  
3.3V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
90%  
10%  
Z = 50Ω  
0
10%  
L
GND  
5 pF  
R = 351Ω  
1 ns  
1 ns  
V = 1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
2.5V IO Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
1 ns  
1 ns  
V = 1.25V  
L
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Document #: 38-05288 Rev. *J  
Page 22 of 32  
 
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Switching Characteristics  
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when V  
= 3.3V and  
DDQ  
is 1.25V when V  
= 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 22 unless otherwise noted.  
DDQ  
133 MHz  
117 MHz  
Min Max  
Description  
Unit  
Parameter  
Min  
Max  
t
1
1
ms  
POWER  
Clock  
t
t
t
Clock Cycle Time  
7.5  
2.5  
2.5  
10  
3.0  
3.0  
ns  
ns  
ns  
CYC  
CH  
Clock HIGH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
6.5  
8.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CDV  
DOH  
CLZ  
2.5  
3.0  
2.5  
3.0  
[17, 18, 19]  
Clock to Low-Z  
Clock to High-Z  
3.8  
3.0  
4.5  
3.8  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
OE LOW to Output Low-Z  
OE HIGH to Output High-Z  
0
0
3.0  
4.0  
Setup Times  
t
t
t
t
t
t
Address Setup Before CLK Rise  
ADV/LD Setup Before CLK Rise  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ALS  
WES  
CENS  
DS  
WE, BW Setup Before CLK Rise  
X
CEN Setup Before CLK Rise  
Data Input Setup Before CLK Rise  
Chip Enable Setup Before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
ADV/LD Hold After CLK Rise  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ALH  
WEH  
CENH  
DH  
WE, BW Hold After CLK Rise  
X
CEN Hold After CLK Rise  
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
CEH  
Notes  
16. This part has an internal voltage regulator; t  
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation  
DD  
POWER  
can be initiated.  
17. t  
, t  
,t  
, and t  
are specified with AC test conditions shown in part (b) of“AC Test Loads and Waveforms” on page 22. Transition is measured ±200 mV  
CHZ CLZ OELZ  
OEHZ  
from steady-state voltage.  
18. At any supplied voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
OEHZ  
OELZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z before Low-Z under the same system conditions.  
19. This parameter is sampled and not 100% tested.  
Document #: 38-05288 Rev. *J  
Page 23 of 32  
       
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Switching Waveforms  
Figure 1 shows read-write timing waveform.  
Figure 1. Read/Write Timing  
t
1
2
3
4
5
6
7
8
9
10  
CYC  
t
CLK  
t
t
t
t
t
CENS  
CES  
CENH  
CEH  
CL  
CH  
CEN  
CE  
ADV/LD  
W E  
BW  
X
A1  
A2  
A4  
A3  
A5  
A6  
A7  
ADDRESS  
DQ  
t
CDV  
t
t
AS  
AH  
t
t
t
t
CHZ  
DOH  
OEV  
CLZ  
D(A1)  
t
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
D(A7)  
t
OEHZ  
t
DS  
DH  
t
DOH  
t
OELZ  
OE  
COM M AND  
W RITE  
D(A1)  
W RITE  
D(A2)  
BURST  
W RITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
W RITE  
D(A5)  
READ  
Q(A6)  
W RITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes  
For this waveform ZZ is tied LOW.  
20.  
21. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.  
1
2
3
1
2
3
22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.  
Document #: 38-05288 Rev. *J  
Page 24 of 32  
       
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Switching Waveforms (continued)  
Figure 2 shows NOP, STALL and DESELECT Cycles waveform.  
Figure 2. NOP, STALL and DESELECT Cycles  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BW [A:D]  
ADDRESS  
A1  
A2  
A3  
A4  
A5  
t
CHZ  
D(A1)  
Q(A2)  
Q(A3)  
D(A4)  
Q(A5)  
DQ  
t
DOH  
COMMAND  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
Note  
23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.  
Document #: 38-05288 Rev. *J  
Page 25 of 32  
   
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Switching Waveforms (continued)  
Figure 3 shows ZZ Mode timing waveform.  
Figure 3. ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes  
24. Device must be deselected when entering ZZ mode. See “Truth Table” on page 11 for all possible signal conditions to deselect the device.  
25. DQs are in high-Z when exiting ZZ sleep mode.  
Document #: 38-05288 Rev. *J  
Page 26 of 32  
     
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Part and Package Type  
Ordering Code  
133 CY7C1471V33-133AXC  
CY7C1473V33-133AXC  
CY7C1471V33-133BZC  
CY7C1473V33-133BZC  
CY7C1471V33-133BZXC  
CY7C1473V33-133BZXC  
CY7C1475V33-133BGC  
CY7C1475V33-133BGXC  
CY7C1471V33-133AXI  
CY7C1473V33-133AXI  
CY7C1471V33-133BZI  
CY7C1473V33-133BZI  
CY7C1471V33-133BZXI  
CY7C1473V33-133BZXI  
CY7C1475V33-133BGI  
CY7C1475V33-133BGXI  
117 CY7C1471V33-117AXC  
CY7C1473V33-117AXC  
CY7C1471V33-117BZC  
CY7C1473V33-117BZC  
CY7C1471V33-117BZXC  
CY7C1473V33-117BZXC  
CY7C1475V33-117BGC  
CY7C1475V33-117BGXC  
CY7C1471V33-117AXI  
CY7C1473V33-117AXI  
CY7C1471V33-117BZI  
CY7C1473V33-117BZI  
CY7C1471V33-117BZXI  
CY7C1473V33-117BZXI  
CY7C1475V33-117BGI  
CY7C1475V33-117BGXI  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
Commercial  
51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
lndustrial  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
Commercial  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
lndustrial  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free  
51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free  
Document #: 38-05288 Rev. *J  
Page 27 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Package Diagrams  
Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
1.00 REF.  
51-85050-*B  
DETAIL  
A
Document #: 38-05288 Rev. *J  
Page 28 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Package Diagrams (continued)  
Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165  
PIN 1 CORNER  
BOTTOM VIEW  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
1
Ø0.25 M C A B  
Ø0.45 0.05(165X)  
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00  
5.00  
10.00  
B
15.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85165-*A  
Document #: 38-05288 Rev. *J  
Page 29 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Package Diagrams (continued)  
Figure 6. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167  
51-85167-**  
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device  
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05288 Rev. *J  
Page 30 of 32  
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the  
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to  
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Document History Page  
Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM  
with NoBL™ Architecture  
Document Number: 38-05288  
Issue  
Date  
REV. ECN NO.  
Orig. of Change  
Description of Change  
**  
114675 08/06/02  
121521 02/07/03  
PKS  
CJM  
New Data Sheet  
*A  
Updated features for package offering  
Updated ordering information  
Changed Advanced Information to Preliminary  
*B  
223721 See ECN  
NJY  
Changed timing diagrams  
Changed logic block diagrams  
Modified Functional Description  
Modified “Functional Overview” section  
Added boundary scan order for all packages  
Included thermal numbers and capacitance values for all packages  
Removed 150-MHz speed grade offering  
Included ISB and IDD values  
Changed package outline for 165FBGA package and 209-Ball BGA package  
Removed 119-BGA package offering  
*C  
*D  
*E  
235012 See ECN  
243572 See ECN  
299511 See ECN  
RYQ  
NJY  
SYT  
Minor Change: The data sheets do not match on the spec system and  
external web  
Changed ball H2 from V to NC in the 165-Ball FBGA package in page 6  
DD  
Modified capacitance values on page 21  
Removed 117-MHz Speed Bin  
Changed Θ from 16.8 to 24.63 °C/W and Θ from 3.3 to 2.28 °C/W for 100  
JA  
JC  
TQFP Package on Page # 21  
Added Pb-free information for 100-Pin TQFP, 165 FBGA and 209 BGA  
Packages  
Added comment of ‘Pb-free BG packages availability’ below the Ordering  
Information  
*F  
320197 See ECN  
331513 See ECN  
PCI  
PCI  
Corrected part number typos in the logic block diagram on page# 2  
*G  
Address expansion pins/balls in the pinouts for all packages are modified as  
per JEDEC standard  
Added Address Expansion pins in the Pin Definitions Table  
Added Industrial Operating Range  
Modified V , V Test Conditions  
OL  
OH  
Updated Ordering Information Table  
*H  
416221 See ECN  
RXU  
Converted from Preliminary to Final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Removed 100MHz Speed bin & Added 117MHz Speed bin  
Changed the description of I from Input Load Current to Input Leakage  
X
Current on page# 19  
Changed the I current values of MODE on page # 19 from –5 µA and 30 µA  
X
to –30 µA and 5 µA  
Changed the I current values of ZZ on page # 19 from –30 µA and 5 µA  
X
to –5 µA and 30 µA  
Changed V < V to V < V on page # 19  
IH  
DD  
IH  
DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Updated the Ordering Information Table  
Document #: 38-05288 Rev. *J  
Page 31 of 32  
CY7C1471V33  
CY7C1473V33  
CY7C1475V33  
Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM  
with NoBL™ Architecture  
Document Number: 38-05288  
Issue  
Date  
REV. ECN NO.  
Orig. of Change  
Description of Change  
*I  
472335 See ECN  
VKN  
Corrected the typo in the pin configuration for 209-Ball FBGA pinout  
(Corrected the ball name for H9 to V from V  
).  
SS  
SSQ  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND.  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP AC  
TH TL  
TDOV  
Switching Characteristics table.  
Updated the Ordering Information table.  
*J  
1274732 See ECN  
VKN/AESA  
Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform  
Document #: 38-05288 Rev. *J  
Page 32 of 32  

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