Cypress CY7C1464AV33 User Manual

CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined SRAM with NoBL™ Architecture  
Functional Description  
Features  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
— Available speed grades are 250, 200 and 167 MHz  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are  
3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst  
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.  
They are designed to support unlimited true back-to-back  
Read/Write operations with no wait states. The  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33  
are  
equipped with the advanced (NoBL) logic required to enable  
consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
Write/Read  
transitions.  
The  
• 3.3V power supply  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin  
compatible and functionally equivalent to ZBT devices.  
• 3.3V/2.5V I/O power supply  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• CY7C1460AV33, CY7C1462AV33 available in  
JEDEC-standard lead-free 100-pin TQFP, lead-free and  
non-lead-free 165-ball FBGA package. CY7C1464AV33  
available in lead-free and non-lead-free 209-ball FBGA  
package  
Write operations are controlled by the Byte Write Selects  
(BW –BW  
for  
CY7C1464AV33,  
BW –BW  
for  
a
h
a
d
CY7C1460AV33 and BW –BW for CY7C1462AV33) and a  
Write Enable (WE) input. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
a
b
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram-CY7C1460AV33 (1M x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
BWa  
BWb  
BWc  
BWd  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
WRITE  
DRIVERS  
DQPa  
DQPb  
DQPc  
DQPd  
A
M
P
S
T
E
R
S
F
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05353 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 22, 2006  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Configurations  
100-pin TQFP Pinout  
DQPc  
DQc  
DQc  
1
2
3
4
5
6
7
8
NC  
NC  
NC  
DDQ  
1
2
3
4
5
6
7
8
A
NC  
NC  
78  
DQPb  
DQb  
DQb  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
80  
79  
V
V
DDQ  
V
V
V
NC  
DQPa  
DQa  
DQa  
DDQ  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DDQ  
SS  
V
V
V
SS  
SS  
SS  
DQc  
DQc  
NC  
NC  
DQb  
DQb  
DQb  
DQb  
DQb  
DQc  
DQc  
9
DQb  
9
V
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
SS  
SS  
V
V
DDQ  
DDQ  
V
V
DQa  
DQa  
V
NC  
DDQ  
DDQ  
DQc  
DQc  
NC  
DQb  
DQb  
DQb  
DQb  
NC  
V
SS  
CY7C1462AV33  
(2M × 18)  
CY7C1460AV33  
(1M × 36)  
SS  
V
V
DD  
NC  
DD  
NC  
NC  
V
V
ZZ  
DD  
DD  
V
V
SS  
SS  
ZZ  
DQa  
DQa  
DQd  
DQb  
DQa  
DQa  
DQd  
DQb  
DDQ  
V
V
DDQ  
V
V
V
DQa  
DQa  
NC  
NC  
V
V
DDQ  
DDQ  
V
V
SS  
V
SS  
SS  
SS  
DQd  
DQd  
DQd  
DQd  
DQa  
DQa  
DQb  
DQb  
DQa DQPb  
DQa  
NC  
V
SS  
V
V
SS  
SS  
SS  
V
V
DDQ  
DDQ  
V
DDQ  
DDQ  
DQd  
DQd  
DQPd  
DQa  
DQa  
DQPa  
NC  
NC  
NC  
NC  
NC  
NC  
Document #: 38-05353 Rev. *D  
Page 3 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Configurations (continued)  
165-ball FBGA (15 x 17 x 1.4 mm) Pinout  
CY7C1460AV33 (1M × 36)  
1
2
A
3
4
5
6
7
8
9
A
10  
A
11  
NC  
NC/576M  
NC/1G  
DQPc  
ADV/LD  
A
B
C
D
CE1  
BWc  
BWd  
VSS  
VDD  
BWb  
BWa  
VSS  
VSS  
CE  
CEN  
WE  
3
A
CE2  
VDDQ  
VDDQ  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
A
A
NC  
NC  
DQc  
VSS  
VSS  
VDDQ  
VDDQ  
NC  
DQb  
DQPb  
DQb  
DQc  
DQc  
DQc  
DQc  
NC  
DQc  
DQc  
DQc  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQb  
DQb  
DQb  
NC  
DQb  
DQb  
DQb  
ZZ  
E
F
G
H
J
DQd  
DQd  
DQd  
DQd  
DQd  
DQd  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
DQa  
DQa  
DQa  
K
L
DQd  
DQd  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQa  
NC  
A
DQa  
DQPa  
M
N
P
DQPd  
NC/144M NC/72M  
TDI  
TDO  
NC/288M  
A
MODE  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
CY7C1462AV33 (2M × 18)  
1
NC/576M  
NC/1G  
NC  
2
A
3
4
5
NC  
6
CE  
7
8
9
A
10  
A
11  
A
A
B
C
D
CE1  
BWb  
NC  
CEN  
ADV/LD  
3
NC  
A
CE2  
VDDQ  
VDDQ  
BWa  
VSS  
VSS  
CLK  
VSS  
VSS  
A
A
WE  
VSS  
VSS  
OE  
VSS  
VDD  
NC  
DQb  
VSS  
VDD  
VDDQ  
VDDQ  
NC  
NC  
DQPa  
DQa  
NC  
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQa  
DQa  
DQa  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQb  
DQb  
DQb  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQa  
DQa  
DQa  
NC  
NC  
NC  
K
L
NC  
NC  
DQb  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQa  
NC  
A
NC  
NC  
M
N
P
DQPb  
NC/144M NC/72M  
TDI  
TDO  
NC/288M  
A
MODE  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05353 Rev. *D  
Page 4 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Configurations (continued)  
209-ball FBGA (14 x 22 x 1.76 mm) Pinout  
CY7C1464AV33 (512K x 72)  
1
DQg  
DQg  
DQg  
2
3
4
5
6
7
8
9
10  
DQb  
11  
A
B
C
D
E
F
DQg  
DQg  
CE  
CE  
ADV/LD  
WE  
DQb  
DQb  
3
2
A
A
A
A
A
BWS  
DQb  
DQb  
NC  
BWS  
BWS  
f
BWS  
b
c
g
DQg  
DQg  
DQPc  
DQc  
DQc  
NC/576M  
NC  
NC  
BWS  
NC  
BWS  
CE  
BWS  
a
BWS  
DQb  
DQb  
DQPb  
DQf  
e
d
1
h
DQg  
V
NC/1G  
OE  
V
NC  
V
SS  
DQb  
SS  
DQPg  
DQc  
V
V
V
V
V
V
DD  
DDQ  
DDQ  
DDQ  
SS  
DDQ  
DD  
DD  
DQPf  
DQf  
V
V
V
V
V
NC  
NC  
NC  
NC  
CEN  
NC  
NC  
V
V
SS  
SS  
SS  
SS  
SS  
G
H
J
DQc  
DQc  
V
V
V
DDQ  
V
V
V
DD  
DDQ  
DQf  
DQf  
DD  
DDQ  
DQf  
DDQ  
V
V
V
V
V
V
SS  
V
DQc  
DQc  
NC  
SS  
SS  
SS  
SS  
SS  
DQf  
DQf  
NC  
DQc  
NC  
V
V
DDQ  
V
V
V
DDQ  
DD  
DD  
DDQ  
DDQ  
DQf  
NC  
K
L
CLK  
V
V
NC  
V
SS  
SS  
NC  
NC  
DQh  
DQh  
DQh  
V
V
V
V
DDQ  
DD  
DD  
SS  
DDQ  
DDQ  
DQa  
DQa  
DQa  
DDQ  
M
N
P
R
T
V
V
V
V
V
V
V
DQh  
DQh  
DQh  
V
V
SS  
SS  
SS  
SS  
SS  
DQa  
DQa  
DQa  
V
V
V
V
V
DDQ  
DQh  
DQh  
DQPd  
DQd  
DQd  
V
V
V
V
V
NC  
ZZ  
DD  
DD  
SS  
DDQ  
SS  
DDQ  
DDQ  
DQa  
DQa  
DQPa  
DQe  
DQe  
V
V
V
V
SS  
SS  
SS  
SS  
V
DQPh  
DQd  
DQd  
DQd  
DQd  
V
V
DDQ  
SS  
DD  
DD  
DDQ  
DDQ  
SS  
DDQ  
DD  
DQPe  
DQe  
DQe  
DQe  
DQe  
NC  
V
NC  
NC  
NC  
A
MODE  
A
U
V
W
NC/72M  
A
A
NC/288M  
NC/144M  
A
A
A1  
A
DQd  
DQd  
A
A
A
A
DQe  
DQe  
TDI  
TDO  
TCK  
A0  
A
TMS  
Pin Definitions  
Pin Name  
I/O Type  
Pin Description  
A0  
A1  
A
Input-  
Synchronous  
Address Inputs used to select one of the address locations. Sampled at the rising  
edge of the CLK.  
BW  
Input-  
Synchronous  
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.  
a
BW  
BW  
BW  
BW  
BW  
BW  
BW  
Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and  
b
c
d
e
f
a
a
a
b
b
DQP , BW controls DQ and DQP , BW controls DQ and DQP , BW controls DQ and  
b
c
c
c
d
d
d
e
e
DQP , BW controls DQ and DQP , BW controls DQ and DQP , BW controls DQ and  
e
f
f
f
g
g
g
h
h
DQP .  
h
g
h
WE  
Input-  
Synchronous  
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active  
LOW. This signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input-  
Synchronous  
Advance/Load Input used to advance the on-chip address counter or load a new  
address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced.  
When LOW, a new address can be loaded into the device for an access. After being  
deselected, ADV/LD should be driven LOW in order to load a new address.  
Document #: 38-05353 Rev. *D  
Page 5 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Pin Definitions (continued)  
Pin Name  
CLK  
I/O Type  
Pin Description  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with  
CEN. CLK is only recognized if CEN is active LOW.  
CE  
CE  
CE  
Input-  
Synchronous  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
1
2
3
with CE and CE to select/deselect the device.  
2
3
Input-  
Synchronous  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in  
conjunction with CE and CE to select/deselect the device.  
1
3
Input-  
Synchronous  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
with CE and CE to select/deselect the device.  
1
2
OE  
Input-  
Output Enable, active LOW. Combined with the synchronous logic block inside the device  
Asynchronous to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as  
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is  
masked during the data portion of a write sequence, during the first clock when emerging  
from a deselected state and when the device has been deselected.  
CEN  
Input-  
Synchronous  
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by  
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN  
does not deselect the device, CEN can be used to extend the previous cycle when required.  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
I/O-  
Synchronous  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is  
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
a
b
c
d
e
f
memory location specified by A during the previous clock rise of the read cycle. The  
X
direction of the pins is controlled by OE and the internal control logic. When OE is asserted  
LOW, the pins can behave as outputs. When HIGH, DQ –DQ are placed in a tri-state  
a
d
condition. The outputs are automatically tri-stated during the data portion of a write  
sequence, during the first clock when emerging from a deselected state, and when the  
device is deselected, regardless of the state of OE.  
g
h
DQP DQP  
I/O-  
Synchronous  
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ  
.
[31:0]  
a,  
b,  
d
DQP DQP  
During write sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is  
c,  
a
a
b
b
c
DQP DQP  
controlled by BW , and DQP is controlled by BW , DQP is controlled by BW , DQP is  
e,  
f
c
d
d
e
e
f
DQP DQP  
controlled by BW , DQP is controlled by BW , DQP is controlled by BW .  
g,  
h
f
g
g
h
h
MODE  
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst  
order. Pulled LOW selects the linear burst order. MODE should not change states during  
operation. When left floating MODE will default HIGH, to an interleaved burst order.  
TDO  
TDI  
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.  
Synchronous  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.  
Synchronous  
TMS  
TCK  
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of  
Synchronous  
TCK.  
JTAG-Clock  
Clock input to the JTAG circuitry.  
V
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
I/O Power Supply Power supply for the I/O circuitry.  
DDQ  
Ground  
N/A  
Ground for the device. Should be connected to ground of the system.  
SS  
NC  
No connects. This pin is not connected to the die.  
NC/72M  
N/A  
Not connected to the die. Can be tied to any voltage level.  
NC/144M  
NC/288M  
NC/576M  
NC/1G  
N/A  
N/A  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
Not connected to the die. Can be tied to any voltage level.  
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”  
N/A  
N/A  
ZZ  
Input-  
Asynchronous condition with data integrity preserved. During normal operation, this pin can be connected  
to V or left floating. ZZ pin has an internal pull-down.  
SS  
Document #: 38-05353 Rev. *D  
Page 6 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Functional Overview  
the internal burst counter regardless of the state of chip  
enables inputs or WE. WE is latched at the beginning of a burst  
cycle. Therefore, the type of access (Read or Write) is  
maintained throughout the burst sequence.  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are  
synchronous-pipelined Burst NoBL SRAMs designed specifi-  
cally to eliminate wait states during Write/Read transitions. All  
synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock signal is qualified with  
the Clock Enable input signal (CEN). If CEN is HIGH, the clock  
signal is not recognized and all internal states are maintained.  
All synchronous operations are qualified with CEN. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise  
Single Write Accesses  
Write access are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
and CE are ALL asserted active, and (3) the write signal WE  
3
is asserted LOW. The address presented to the address inputs  
is loaded into the Address Register. The write signals are  
latched into the Control Logic block.  
(t ) is 2.6 ns (250-MHz device).  
CO  
On the subsequent clock rise the data lines are automatically  
tri-stated regardless of the state of the OE input signal. This  
allows the external logic to present the data on DQ and DQP  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If Clock  
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,  
the address presented to the device will be latched. The  
access can either be a read or write operation, depending on  
(DQ  
DQ  
/DQP  
for  
for CY7C1460AV33 and DQ /DQP  
a,b  
CY7C1464AV33,  
a,b,c,d,e,f,g,h  
a,b,c,d,e,f,g,h  
/DQP  
a,b,c,d  
a,b,c,d  
a,b  
for CY7C1462AV33). In addition, the address for the subse-  
quent access (Read/Write/Deselect) is latched into the  
Address Register (provided the appropriate control signals are  
asserted).  
the status of the Write Enable (WE). BW can be used to  
[x]  
conduct byte write operations.  
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self-timed write  
circuitry.  
On the next clock rise the data presented to DQ and DQP  
(DQ  
/DQP  
for  
CY7C1464AV33,  
a,b,c,d,e,f,g,h  
a,b,c,d,e,f,g,h  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
DQ  
/DQP  
for CY7C1460AV33 & DQ /DQP for  
a,b,c,d  
a,b,c,d  
a,b  
a,b  
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW once the device has been  
deselected in order to load a new address for the next  
operation.  
CY7C1462AV33) (or a subset for byte write operations, see  
Write Cycle Description table for details) inputs is latched into  
the device and the write is complete.  
The data written during the Write operation is controlled by BW  
(BW  
for  
CY7C1464AV33,  
BW  
for  
a,b,c,d,e,f,g,h  
a,b,c,d  
Single Read Accesses  
CY7C1460AV33 and BW for CY7C1462AV33) signals. The  
a,b  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides  
byte write capability that is described in the Write Cycle  
Description table. Asserting the Write Enable input (WE) with  
the selected Byte Write Select (BW) input will selectively write  
to only the desired bytes. Bytes not selected during a byte  
A read access is initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
1
2
and CE are ALL asserted active, (3) the Write Enable input  
3
signal WE is deasserted HIGH, and (4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the Address Register and presented to the memory core  
and control logic. The control logic determines that a read  
access is in progress and allows the requested data to  
propagate to the input of the output register. At the rising edge  
of the next clock the requested data is allowed to propagate  
through the output register and onto the data bus within 2.6 ns  
(250-MHz device) provided OE is active LOW. After the first  
clock of the read access the output buffers are controlled by  
OE and the internal control logic. OE must be driven LOW in  
order for the device to drive out the requested data. During the  
second clock, a subsequent operation (Read/Write/Deselect)  
can be initiated. Deselecting the device is also pipelined.  
Therefore, when the SRAM is deselected at clock rise by one  
of the chip enable signals, its output will tri-state following the  
next clock rise.  
write operation will remain unaltered.  
A
synchronous  
self-timed write mechanism has been provided to simplify the  
write operations. Byte write capability has been included in  
order to greatly simplify Read/Modify/Write sequences, which  
can be reduced to simple byte write operations.  
Because  
the  
are  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33  
common I/O devices, data should not be driven into the device  
while the outputs are active. The Output Enable (OE) can be  
deasserted HIGH before presenting data to the DQ and DQP  
(DQ  
/DQP  
for  
for CY7C1460AV33 and DQ /DQP  
a,b  
CY7C1464AV33,  
a,b,c,d,e,f,g,h  
a,b,c,d,e,f,g,h  
DQ  
/DQP  
a,b,c,d  
a,b,c,d  
a,b  
for CY7C1462AV33) inputs. Doing so will tri-state the output  
drivers. As  
(DQ  
a
safety precaution, DQ and DQP  
for CY7C1464AV33,  
for CY7C1460AV33 and DQ /DQP  
a,b  
/DQP  
a,b,c,d,e,f,g,h  
a,b,c,d,e,f,g,h  
DQ  
/DQP  
a,b,c,d  
a,b,c,d  
a,b  
Burst Read Accesses  
for CY7C1462AV33) are automatically tri-stated during the  
data portion of a write cycle, regardless of the state of OE.  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have  
an on-chip burst counter that allows the user the ability to  
supply a single address and conduct up to four Reads without  
reasserting the address inputs. ADV/LD must be driven LOW  
in order to load a new address into the SRAM, as described in  
the Single Read Access section above. The sequence of the  
burst counter is determined by the MODE input signal. A LOW  
input on MODE selects a linear burst mode, a HIGH selects an  
interleaved burst sequence. Both burst counters use A0 and  
A1 in the burst sequence, and will wrap-around when incre-  
mented sufficiently. A HIGH input on ADV/LD will increment  
Burst Write Accesses  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has  
an on-chip burst counter that allows the user the ability to  
supply a single address and conduct up to four WRITE opera-  
tions without reasserting the address inputs. ADV/LD must be  
driven LOW in order to load the initial address, as described  
in the Single Write Access section above. When ADV/LD is  
driven HIGH on the subsequent clock rise, the chip enables  
(CE , CE , and CE ) and WE inputs are ignored and the burst  
1
2
3
Document #: 38-05353 Rev. *D  
Page 7 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
counter is incremented. The correct BW (BW  
for  
a,b,c,d,e,f,g,h  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
CY7C1464AV33, BW  
for CY7C1460AV33 and BW for  
a,b,c,d  
a,b  
)
CY7C1462AV33) inputs must be driven in each cycle of the  
burst write in order to write the correct bytes of data.  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
Sleep Mode  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Linear Burst Address Table (MODE = GND)  
the “sleep” mode. CE , CE , and CE , must remain inactive  
1
2
3
for the duration of t  
after the ZZ input returns LOW.  
ZZREC  
First  
Second  
Address  
Third  
Address  
Fourth  
Address  
Address  
A1,A0  
00  
A1,A0  
01  
A1,A0  
10  
A1,A0  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
Min.  
Max.  
100  
Unit  
mA  
ns  
I
t
t
t
t
ZZ > V 0.2V  
DD  
DDZZ  
ZZ > V 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Truth Table[1, 2, 3, 4, 5, 6, 7]  
Address  
Operation  
Deselect Cycle  
Continue  
Used  
None  
None  
CE  
H
X
ZZ  
L
L
ADV/LD WE  
BW  
X
X
OE  
X
X
CEN  
L
L
CLK  
L-H  
L-H  
DQ  
Tri-State  
Tri-State  
x
L
X
X
H
Deselect Cycle  
Read Cycle  
(Begin Burst)  
Read Cycle  
(Continue Burst)  
NOP/Dummy Read  
(Begin Burst)  
Dummy Read  
External  
Next  
L
X
L
L
L
L
L
L
H
L
H
X
H
X
X
X
X
X
L
L
L
L
L
L
L-H  
L-H  
L-H  
L-H  
Data Out (Q)  
Data Out (Q)  
Tri-State  
External  
Next  
H
H
X
H
Tri-State  
(Continue Burst)  
Notes:  
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =  
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.  
2. Write is defined by WE and BW . See Write Cycle Description table for details.  
X
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.  
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.  
5. CEN = H inserts wait states.  
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.  
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Tri-state when OE  
s
X
is inactive or when the device is deselected, and DQ =data when OE is active.  
s
Document #: 38-05353 Rev. *D  
Page 8 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Truth Table[1, 2, 3, 4, 5, 6, 7] (continued)  
Address  
Operation  
Write Cycle  
(Begin Burst)  
Write Cycle  
(Continue Burst)  
NOP/WRITE ABORT  
(Begin Burst)  
WRITE ABORT  
(Continue Burst)  
IGNORE CLOCK  
EDGE  
Used  
CE  
L
ZZ  
L
ADV/LD WE  
BW  
L
OE  
X
CEN  
L
CLK  
DQ  
Data In (D)  
x
External  
L
H
L
L
X
L
L-H  
L-H  
L-H  
L-H  
L-H  
Next  
None  
Next  
X
L
L
L
L
L
L
H
H
X
X
X
X
X
L
L
Data In (D)  
Tri-State  
Tri-State  
-
X
X
H
X
X
X
L
Current  
H
(Stall)  
SLEEP MODE  
None  
X
H
X
X
X
X
X
X
Tri-State  
Partial Write Cycle Description[1, 2, 3, 8]  
Function (CY7C1460AV33)  
Read  
WE  
H
L
BW  
X
H
H
H
H
H
H
H
H
L
BW  
X
H
H
H
H
L
BW  
X
H
H
L
BW  
a
d
c
b
X
H
L
Write – No bytes written  
Write Byte a – (DQ and DQP )  
L
a
a
Write Byte b – (DQ and DQP )  
L
H
L
b
b
Write Bytes b, a  
Write Byte c – (DQ and DQP )  
L
L
L
H
H
L
H
L
c
c
Write Bytes c, a  
Write Bytes c, b  
Write Bytes c, b, a  
L
L
L
LL  
L
H
L
L
L
Write Byte d – (DQ and DQP )  
L
H
H
H
H
L
H
H
L
H
L
d
d
Write Bytes d, a  
Write Bytes d, b  
Write Bytes d, b, a  
Write Bytes d, c  
Write Bytes d, c, a  
Write Bytes d, c, b  
Write All Bytes  
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
[2,8]  
Function (CY7C1462AV33)  
WE  
BW  
x
BW  
x
b
a
Read  
H
L
L
L
L
Write – No Bytes Written  
Write Byte a – (DQ and DQP )  
H
H
L
H
L
a
a
Write Byte b – (DQ and DQP )  
H
L
b
b
Write Both Bytes  
L
[2,8]  
Function (CY7C1464AV33)  
WE  
H
BW  
x
x
Read  
Write – No Bytes Written  
L
H
Write Byte X (DQ and DQP  
L
L
x
x)  
Write All Bytes  
L
All BW = L  
Note:  
8. Table only lists a partial listing of the byte write combinations. Any combination of BW  
is valid. Appropriate write will be done based on which byte write is active.  
[a:d]  
Document #: 38-05353 Rev. *D  
Page 9 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Test Data-In (TDI)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. TDI  
is internally pulled up and can be unconnected if the TAP is  
unused in an application. TDI is connected to the most signif-  
icant bit (MSB) of any register. (See Tap Controller Block  
Diagram.)  
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor-  
porates a serial boundary scan test access port (TAP). This  
part is fully compliant with 1149.1. The TAP operates using  
JEDEC-standard 3.3V or 2.5V I/O logic level.  
The  
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33  
contains a TAP controller, instruction register, boundary scan  
register, bypass register, and ID register.  
Disabling the JTAG Feature  
Test Data-Out (TDO)  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V through a pull-up resistor. TDO should be  
DD  
left unconnected. Upon power-up, the device will come up in  
a reset state which will not interfere with the operation of the  
device.  
TAP Controller Block Diagram  
0
TAP Controller State Diagram  
Bypass Register  
TEST-LOGIC  
1
2
1
0
0
0
RESET  
0
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
Selection  
Circuitry  
TDI  
TDO  
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
.
.
.
2
1
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
x
.
.
.
.
.
2
1
0
0
Boundary Scan Register  
SHIFT-DR  
0
SHIFT-IR  
0
1
1
1
1
EXIT1-DR  
EXIT1-IR  
TCK  
TMS  
TAP CONTROLLER  
0
0
PAUSE-DR  
0
PAUSE-IR  
0
1
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
Performing a TAP Reset  
A RESET is performed by forcing TMS HIGH (VDD) for five  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
UPDATE-DR  
UPDATE-IR  
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
TAP Registers  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
Test Access Port (TAP)  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Instruction Register  
Test MODE SELECT (TMS)  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
Document #: 38-05353 Rev. *D  
Page 10 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board-level serial test data path.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High-Z state until the next command is  
given during the “Update IR” state.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM. The length of the Boundary  
Scan Register for the SRAM in different packages is listed in  
the Scan Register Sizes table.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
will undergo a transition. The TAP may then try to capture a  
signal while in transition (metastable state). This will not harm  
the device, but there is no guarantee as to the value that will  
be captured. Repeatable results may not be possible.  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the I/O ring.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI, and the LSB is connected to TDO.  
hold times (t and t ). The SRAM clock input might not be  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK# captured in the  
boundary scan register.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO pins.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells  
prior to the selection of another boundary scan test operation.  
TAP Instruction Set  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
Overview  
Eight different instructions are possible with the three bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO pins. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
EXTEST  
The EXTEST instruction enables the preloaded data to be  
driven out through the system output pins. This instruction also  
selects the boundary scan register to be connected for serial  
access between the TDI and TDO in the shift-DR controller  
state.  
IDCODE  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
EXTEST OUTPUT BUS TRI-STATE  
IEEE Standard 1149.1 mandates that the TAP controller be  
able to put the output bus into a tri-state mode.  
The IDCODE instruction is loaded into the instruction register  
upon power-up or whenever the TAP controller is given a test  
logic reset state.  
The boundary scan register has a special bit located at bit #89  
(for 165-FBGA package) or bit #138 (for 209-FBGA package).  
Document #: 38-05353 Rev. *D  
Page 11 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
When this scan cell, called the “extest output bus tri-state,” is  
latched into the preload register during the “Update-DR” state  
in the TAP controller, it will directly control the state of the  
output (Q-bus) pins, when the EXTEST is entered as the  
current instruction. When HIGH, it will enable the output  
buffers to drive the output bus. When LOW, this bit will place  
the output bus into a High-Z condition.  
loaded into that shift-register cell will latch into the preload  
register. When the EXTEST instruction is entered, this bit will  
directly control the output Q-bus pins. Note that this bit is  
preset HIGH to enable the output when the device is  
powered-up, and also when the TAP controller is in the  
Test-Logic-Reset” state.  
Reserved  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that  
cell, during the “Shift-DR” state. During “Update-DR,” the value  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
[9, 10]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min.  
Max.  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Notes:  
9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05353 Rev. *D  
Page 12 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ................................................ V to 3.3V  
Input pulse levels ................................................V to 2.5V  
SS  
SS  
Input rise and fall times................................................... 1 ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels......................................... 1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.5V  
1.25V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
ZO= 50Ω  
20pF  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
[11]  
(0°C < TA < +70°C; V = 3.135V to 3.6V unless otherwise noted)  
DD  
Parameter  
Description  
Test Conditions  
Min.  
2.4  
2.0  
2.9  
2.1  
Max.  
Unit  
V
V
V
V
V
V
V
Output HIGH Voltage  
I
I
I
= –4.0 mA, V  
= –1.0 mA, V  
= –100 µA  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
V
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
V
V
V
V
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
V
OH2  
OL1  
OL2  
IH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
I
I
I
= 8.0 mA  
= 1.0 mA  
= 100 µA  
0.4  
0.4  
0.2  
0.2  
V
OL  
OL  
OL  
V
V
V
2.0  
1.7  
V
V
+ 0.3  
V
DD  
DD  
+ 0.3  
V
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
I
GND < V < V  
DDQ  
µA  
X
IN  
Identification Register Definitions  
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33  
Instruction Field  
(1M ×36)  
(2M ×18)  
(512K ×72)  
Description  
Revision Number (31:29)  
000  
000  
000  
Describes the version number.  
Reserved for Internal Use  
[12]  
Device Depth (28:24)  
01011  
001000  
01011  
001000  
01011  
Architecture/Memory Type(23:18)  
001000  
Defines memory type and archi-  
tecture  
Bus Width/Density(17:12)  
100111  
010111  
110111  
Defines width and density  
Cypress JEDEC ID Code (11:1)  
00000110100  
00000110100  
00000110100 Allows unique identification of  
SRAM vendor.  
ID Register Presence Indicator (0)  
1
1
1
Indicates the presence of an ID  
register.  
Notes:  
11. All voltages referenced to V (GND).  
SS  
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.  
Document #: 38-05353 Rev. *D  
Page 13 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Scan Register Sizes  
Register Name  
Bit Size (×36)  
Bit Size (×18)  
Bit Size (×72)  
Instruction  
3
1
3
1
3
1
Bypass  
ID  
32  
89  
-
32  
89  
-
32  
-
Boundary Scan Order (165-ball FBGA package)  
Boundary Scan Order (209-ball FBGA package)  
138  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High-Z state.  
IDCODE  
001  
010  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Document #: 38-05353 Rev. *D  
Page 14 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
165-ball FBGA Boundary Scan Order [13]  
CY7C1460AV33 (1M x 36), CY7C1462AV33 (2M x 18)  
Bit#  
1
ball ID  
N6  
Bit#  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
ball ID  
E11  
D11  
G10  
F10  
E10  
D10  
C11  
A11  
B11  
A10  
B10  
A9  
Bit#  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
ball ID  
A3  
A2  
B2  
C2  
B1  
A1  
C1  
D1  
E1  
F1  
Bit#  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
ball ID  
N1  
2
N7  
N2  
3
10N  
P11  
P8  
P1  
4
R1  
5
R2  
6
R8  
P3  
7
R9  
R3  
8
P9  
P2  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
R4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
P4  
G1  
D2  
E2  
F2  
N5  
P6  
B9  
R6  
C10  
A8  
Internal  
G2  
H1  
H3  
J1  
B8  
A7  
B7  
B6  
K1  
L1  
A6  
B5  
M1  
J2  
A5  
H10  
G11  
F11  
A4  
K2  
L2  
B4  
B3  
M2  
Note:  
13. Bit# 89 is preset HIGH.  
Document #: 38-05353 Rev. *D  
Page 15 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
209-ball BGA Boundary Scan Order [13, 14]  
CY7C14604V33 (512K x 72)  
Bit#  
1
Ball ID  
Bit#  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
ball ID  
6F  
Bit#  
71  
ball ID  
6H  
6C  
6B  
6A  
5A  
5B  
5C  
5D  
4D  
4C  
4A  
4B  
3C  
3B  
3A  
2A  
1A  
2B  
1B  
2C  
1C  
2D  
1D  
1E  
2E  
2F  
Bit#  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
ball ID  
3K  
W6  
V6  
2
8K  
72  
4K  
3
U6  
9K  
73  
6K  
4
W7  
V7  
10K  
11J  
10J  
11H  
10H  
11G  
10G  
11F  
10F  
10E  
11E  
11D  
10D  
11C  
10C  
11B  
10B  
11A  
10A  
9C  
74  
2K  
5
75  
2L  
6
U7  
76  
1L  
7
T7  
77  
2 Mbit  
1 Mbit  
2N  
8
V8  
78  
9
U8  
79  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
T8  
80  
1N  
V9  
81  
2P  
U9  
82  
1P  
P6  
83  
2R  
W11  
W10  
V11  
V10  
U11  
U10  
T11  
T10  
R11  
R10  
P11  
P10  
N11  
N10  
M11  
M10  
L11  
L10  
K11  
M6  
84  
1R  
85  
2T  
86  
1T  
87  
2U  
88  
1U  
89  
2V  
90  
1V  
91  
2W  
1W  
6T  
92  
93  
9B  
94  
3U  
9A  
95  
3V  
8D  
96  
4T  
8C  
97  
1F  
5T  
8B  
98  
1G  
2G  
2H  
1H  
2J  
4U  
8A  
99  
4V  
7D  
100  
101  
102  
103  
104  
105  
5W  
5V  
7C  
7B  
5U  
7A  
1J  
Internal  
L6  
6D  
1K  
6N  
J6  
6G  
Note:  
14. Bit# 138 is preset HIGH.  
Document #: 38-05353 Rev. *D  
Page 16 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current.................................................... > 200 mA  
Storage Temperature .................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Ambient  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
Range  
Temperature  
V
V
DDQ  
DD  
DD  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
Commercial 0°C to +70°C  
Industrial –40°C to +85°C  
3.3V  
–5%/+10%  
2.5V –5% to  
DDQ  
DD  
V
DD  
DC to Outputs in Tri-State................... –0.5V to V  
+ 0.5V  
DDQ  
DC Input Voltage....................................–0.5V to V + 0.5V  
DD  
[15, 16]  
Electrical Characteristics Over the Operating Range  
DC Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
3.6  
V
V
DD  
V
V
V
V
V
I
for 3.3V I/O  
for 2.5V I/O  
V
DD  
DDQ  
2.625  
V
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = 4.0 mA  
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = 1.0 mA  
2.0  
V
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
OL  
for 2.5V I/O, I = 1.0 mA  
V
OL  
[15]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
2.0  
1.7  
V
V
+ 0.3V  
+ 0.3V  
0.8  
V
DD  
DD  
V
[15]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
V
IL  
0.7  
V
Input Leakage Current GND V V  
except ZZ and MODE  
5
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
DD  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 167 MHz  
475  
425  
375  
225  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
CYC  
MAX  
I
I
I
I
Automatic CE  
Power-down  
Current—TTL Inputs  
Max. V , Device Deselected, All speed grades  
DD  
SB1  
SB2  
SB3  
SB4  
V
V or V V , f = f  
=
IN  
IH  
IN  
IL  
MAX  
1/t  
CYC  
Automatic CE  
Power-down  
Current—CMOS Inputs f = 0  
Max. V , Device Deselected, All speed grades  
120  
200  
135  
mA  
mA  
mA  
DD  
V
0.3V or V > V  
0.3V,  
IN  
IN  
DDQ  
Automatic CE  
Power-down  
Current—CMOS Inputs f = f  
Max. V , Device Deselected, All speed grades  
DD  
V
0.3V or V > V  
0.3V,  
IN  
IN  
CYC  
DDQ  
= 1/t  
MAX  
Automatic CE  
Max. V , Device Deselected, All speed grades  
DD  
Power-down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN  
IH  
IN  
IL  
Notes:  
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t  
/2).  
IH  
DD  
CYC  
IL  
CYC  
.
16. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
Power-up  
DD  
IH  
DD  
DDQ DD  
Document #: 38-05353 Rev. *D  
Page 17 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Capacitance[17]  
100 TQFP  
Max.  
165 FBGA  
209 FBGA  
Max.  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
pF  
C
C
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
6.5  
3
7
7
6
5
5
7
IN  
A
V
= 2.5V V  
= 2.5V  
DD  
DDQ  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
5.5  
pF  
Thermal Resistance[17]  
100 TQFP  
Package  
165 FBGA  
Package  
209 FBGA  
Package  
Parameters  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Testconditionsfollowstandard  
test methods and procedures  
for measuring thermal  
25.21  
20.8  
25.31  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
2.28  
3.2  
4.48  
°C/W  
JC  
impedance, per EIA/JESD51.  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
OUTPUT  
R = 317Ω  
3.3V  
OUTPUT  
R = 50Ω  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 351Ω  
1 ns  
1 ns  
INCLUDING  
V = 1.5V  
T
(a)  
JIG AND  
SCOPE  
(b)  
(c)  
2.5V I/O Test Load  
OUTPUT  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R =1538Ω  
1 ns  
INCLUDING  
JIG AND  
SCOPE  
1 ns  
V = 1.25V  
T
(a)  
(b)  
(c)  
Note:  
17. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05353 Rev. *D  
Page 18 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
[22, 23]  
Switching Characteristics Over the Operating Range  
–250  
Max.  
–200  
Max.  
–167  
Parameter  
Description  
Min.  
Min.  
Min.  
Max.  
Unit  
[18]  
t
V
(typical) to the first access read or write  
1
1
1
ms  
Power  
CC  
Clock  
t
Clock Cycle Time  
Maximum Operating Frequency  
Clock HIGH  
4.0  
5.0  
6.0  
ns  
MHz  
ns  
CYC  
F
250  
200  
167  
MAX  
t
t
1.5  
1.5  
2.0  
2.0  
2.4  
2.4  
CH  
CL  
Clock LOW  
ns  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
OE LOW to Output Valid  
2.6  
2.6  
3.2  
3.0  
3.4  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
EOV  
DOH  
CHZ  
CLZ  
Data Output Hold After CLK Rise  
1.0  
1.0  
0
1.5  
1.3  
0
1.5  
1.5  
0
[19, 20, 21]  
Clock to High-Z  
2.6  
2.6  
3.0  
3.0  
3.4  
3.4  
[19, 20, 21]  
Clock to Low-Z  
[19, 20, 21]  
OE  
HIGH to Output High-Z  
EOHZ  
EOLZ  
[19, 20, 21]  
OE LOW to Output Low-Z  
Set-up Times  
t
t
t
t
t
t
Address Set-up Before CLK Rise  
Data Input Set-up Before CLK Rise  
CEN Set-up Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
DS  
CENS  
WES  
ALS  
CES  
WE, BW Set-up Before CLK Rise  
x
ADV/LD Set-up Before CLK Rise  
Chip Select Set-up  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
Data Input Hold After CLK Rise  
CEN Hold After CLK Rise  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
DH  
CENH  
WEH  
ALH  
CEH  
WE, BW Hold After CLK Rise  
x
ADV/LD Hold after CLK Rise  
Chip Select Hold After CLK Rise  
Notes:  
18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be  
initiated.  
19. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ EOLZ  
EOHZ  
20. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
EOHZ  
EOLZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
21. This parameter is sampled and not 100% tested.  
22. Timing reference is 1.5V when V  
3.3V and is 1.25V when V  
2.5V.  
DDQ=  
DDQ=  
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05353 Rev. *D  
Page 19 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Switching Waveforms  
[24, 25, 26]  
Read/Write/Timing  
1
2
3
4
5
6
7
8
9
10  
t
CYC  
t
CLK  
t
t
t
CENS CENH  
CL  
CH  
CEN  
t
t
CES  
CEH  
CE  
ADV/LD  
WE  
BWx  
A1  
A2  
A4  
CO  
A3  
A5  
A6  
A7  
ADDRESS  
t
t
t
t
DS  
DH  
t
t
t
DOH  
OEV  
CLZ  
CHZ  
t
t
AS  
AH  
Data  
D(A1)  
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
In-Out (DQ)  
t
OEHZ  
t
DOH  
t
OELZ  
OE  
WRITE  
D(A1)  
WRITE  
D(A2)  
BURST  
WRITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
WRITE  
D(A5)  
READ  
Q(A6)  
WRITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes:  
24. For this waveform ZZ is tied low.  
25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.  
Document #: 38-05353 Rev. *D  
Page 20 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Switching Waveforms (continued)  
[24, 25, 27]  
NOP,STALL and DESELECT Cycles  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BWx  
A1  
A2  
A3  
A4  
A5  
ADDRESS  
t
CHZ  
D(A4)  
D(A1)  
Q(A2)  
Q(A3)  
Q(A5)  
Data  
In-Out (DQ)  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
[28, 29]  
ZZ Mode Timing  
CLK  
ZZ  
t
t
ZZ  
ZZREC  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.  
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.  
29. I/Os are in High-Z when exiting ZZ sleep mode.  
Document #: 38-05353 Rev. *D  
Page 21 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Part and Package Type  
167 CY7C1460AV33-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1462AV33-167AXC  
Commercial  
CY7C1460AV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1462AV33-167BZC  
CY7C1460AV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1462AV33-167BZXC  
CY7C1464AV33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1464AV33-167BGXC  
CY7C1460AV33-167AXI  
CY7C1462AV33-167AXI  
CY7C1460AV33-167BZI  
CY7C1462AV33-167BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
lndustrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1460AV33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1462AV33-167BZXI  
CY7C1464AV33-167BGI  
CY7C1464AV33-167BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
200 CY7C1460AV33-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1462AV33-200AXC  
Commercial  
CY7C1460AV33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1462AV33-200BZC  
CY7C1460AV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1462AV33-200BZXC  
CY7C1464AV33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1464AV33-200BGXC  
CY7C1460AV33-200AXI  
CY7C1462AV33-200AXI  
CY7C1460AV33-200BZI  
CY7C1462AV33-200BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
lndustrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1460AV33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1462AV33-200BZXI  
CY7C1464AV33-200BGI  
CY7C1464AV33-200BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
Document #: 38-05353 Rev. *D  
Page 22 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Part and Package Type  
250 CY7C1460AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1462AV33-250AXC  
Commercial  
CY7C1460AV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1462AV33-250BZC  
CY7C1460AV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1462AV33-250BZXC  
CY7C1464AV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1464AV33-250BGXC  
CY7C1460AV33-250AXI  
CY7C1462AV33-250AXI  
CY7C1460AV33-250BZI  
CY7C1462AV33-250BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1460AV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1462AV33-250BZXI  
CY7C1464AV33-250BGI  
CY7C1464AV33-250BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
Document #: 38-05353 Rev. *D  
Page 23 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Package Diagrams  
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
1.40 0.05  
14.00 0.10  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
0.25  
1. JEDEC STD REF MS-026  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Document #: 38-05353 Rev. *D  
Page 24 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Package Diagrams (continued)  
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)  
PIN 1 CORNER  
BOTTOM VIEW  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
Ø0.25 M C A B  
Ø0.45 0.05(165X)  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00  
5.00  
10.00  
B
15.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85165-*A  
Document #: 38-05353 Rev. *D  
Page 25 of 27  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Package Diagrams (continued)  
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)  
51-85167-**  
ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress  
Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.  
Document #: 38-05353 Rev. *D  
Page 26 of 27  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1460AV33  
CY7C1462AV33  
CY7C1464AV33  
Document History Page  
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM  
with NoBL™ Architecture  
Document Number: 38-05353  
Orig. of  
REV.  
ECN No. Issue Date Change  
Description of Change  
**  
254911  
See ECN  
SYT  
New Data sheet  
Part number changed from previous revision. New and old part number differ  
by the letter “A”  
*A  
303533  
See ECN  
SYT  
Changed H9 pin from V  
FBGA on Page # 5  
to V on the Pin Configuration table for 209  
SSQ SS  
Changed the test condition from V = Min to V = Max for V in the  
DD  
DD  
OL  
Electrical Characteristics table  
Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All  
Packages on the Thermal Resistance Table  
Changed I from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200  
DD  
and 167 MHz respectively  
Changed I  
from 190, 180 and 170 mA to 225 mA for 250, 200 and 167  
SB1  
MHz respectively  
Changed I  
Changed I  
from 80 mA to 100 mA for all frequencies  
from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 MHz  
SB2  
SB3  
respectively  
Changed I  
from 100 mA to 110 mA for all frequencies  
SB4  
Changed C , C  
and C to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP  
IN CLK  
I/O  
Package  
Changed t from 3.0 to 3.2 ns and t  
from 1.3 ns to 1.5 ns for 200 MHz  
CO  
DOH  
Speed Bin  
Added lead-free information for 100-pin TQFP and 165 FBGA and 209 BGA  
packages  
*B  
331778  
See ECN  
SYT  
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA  
Package as per JEDEC standards and updated the Pin Definitions accord-  
ingly  
Modified V  
Changed C , C  
V
test conditions  
and C to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA  
I/O  
OL, OH  
IN CLK  
Package  
Added Industrial Temperature Grade  
Changed I and I from 100 and 110 mA to 120 and 135 mA respectively  
SB2  
SB4  
Updated the Ordering Information by Shading and Unshading MPNs as per  
availability  
*C  
417509  
See ECN  
RXU  
Converted from Preliminary to Final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed I current value in MODE from –5 & 30 µA to –30 & 5 µA respec-  
X
tively and also Changed I current value in ZZ from –30 & 5 µA to –5 & 30  
X
µA respectively on page# 18  
Modified test condition from V < V to V < V  
IH  
DD  
IH  
DD  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Replaced Package Diagram of 51-85050 from *A to *B  
*D  
473229  
See ECN  
NXR  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP  
TH TL  
TDOV  
AC Switching Characteristics table  
Updated the Ordering Information table.  
Document #: 38-05353 Rev. *D  
Page 27 of 27  

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