Cypress CY7C1442AV33 User Manual

CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
36-Mbit (1M x 36/2M x 18/512K x 72)  
Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM  
integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
• Available speed grades are 250, 200 and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
• 2.5V/3.3V I/O power supply  
• Fast clock-to-output times  
(CE ), depth-expansion Chip Enables (CE and CE ), Burst  
1
2
3
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW  
X
— 2.6 ns (for 250-MHz device)  
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• Provide high-performance 3-1-1-1 access rate  
®
User-selectable burst counter supporting Intel  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
®
Pentium interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the byte write control inputs. GW when active  
• Single Cycle Chip Deselect  
• CY7C1440AV33, CY7C1442AV33 available in lead-free  
100-pin TQFP package, lead-free and non-lead-free  
165-ball FBGA package. CY7C1446AV33 available in  
lead-free and non-lead-free 209-ball FBGA package  
causes all bytes to be written.  
LOW  
The  
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
• Also available in lead-free packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
operates from a +3.3V core power supply while all outputs may  
operate with either a +2.5 or +3.3V supply. All inputs and  
outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
250 MHz  
2.6  
200 MHz  
3.2  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
475  
425  
375  
mA  
mA  
120  
120  
120  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05383 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 23, 2006  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Logic Block Diagram – CY7C1446AV33 (512K x 72)  
ADDRESS  
REGISTER  
A0, A1,A  
A[1:0]  
MODE  
Q1  
ADV  
CLK  
BINARY  
COUNTER  
CLR  
Q0  
ADSC  
ADSP  
DQH, DQPH  
WRITE DRIVER  
DQH, DQPH  
WRITE DRIVER  
BWH  
BWG  
BWF  
BWE  
BWD  
BWC  
DQG, DQPG  
WRITE DRIVER  
DQF, DQPF  
WRITE DRIVER  
DQF, DQPF  
WRITE DRIVER  
DQF, DQPF  
WRITE DRIVER  
DQE, DQPE  
WRITE DRIVER  
DQE, DQPE  
WRITE DRIVER  
MEMORY  
ARRAY  
DQD, DQPD  
WRITE DRIVER  
DQD, DQPD  
WRITE DRIVER  
DQC, DQPC  
WRITE DRIVER  
DQC, DQPC  
WRITE DRIVER  
OUTPUT  
BUFFERS  
OUTPUT  
REGISTERS  
SENSE  
AMPS  
DQs  
DQPA  
DQPB  
DQPC  
DQPD  
DQPE  
DQPF  
DQPG  
DQPH  
E
DQB, DQPB  
WRITE DRIVER  
DQB, DQPB  
WRITE DRIVER  
BWB  
DQA, DQPA  
WRITE DRIVER  
DQA, DQPA  
WRITE DRIVER  
BWA  
BWE  
INPUT  
REGISTERS  
GW  
CE1  
CE2  
CE3  
OE  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
SLEEP  
CONTROL  
ZZ  
Document #: 38-05383 Rev. *E  
Page 3 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Pin Configurations  
100-pin TQFP Pinout  
DQPC  
1
DQPB  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
VSS  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
NC  
VDDQ  
VSSQ  
NC  
A
NC  
NC  
VDDQ  
VSSQ  
NC  
DQPA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
VSS  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQC  
2
DQc  
VDDQ  
VSSQ  
DQC  
3
4
5
6
DQC  
7
NC  
DQC  
8
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
NC  
VDD  
NC  
VSS  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQPB  
NC  
DQC  
9
10  
11  
9
VSSQ  
VDDQ  
DQC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
12  
DQC  
13  
NC  
14  
VDD  
15  
NC  
VDD  
ZZ  
CY7C1442AV33  
(2M x 18)  
CY7C1440AV33  
(1M x 36)  
NC  
16  
VDD  
ZZ  
VSS  
17  
DQD  
18  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
DQPA  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
NC  
DQD  
19  
20  
21  
VDDQ  
VSSQ  
DQD  
22  
DQD  
23  
DQD  
24  
DQD  
25  
26  
27  
NC  
VSSQ  
VDDQ  
DQD  
DQD  
29  
VSSQ  
VDDQ  
NC  
NC  
NC  
VSSQ  
VDDQ  
NC  
NC  
NC  
28  
DQPD  
30  
Document #: 38-05383 Rev. *E  
Page 4 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Pin Configurations (continued)  
165-ball FBGA (15 x 17 x 1.4 mm) Pinout  
CY7C1440AV33 (1M x 36)  
1
2
3
4
5
6
7
8
9
10  
A
11  
NC  
NC/288M  
NC/144M  
DQPC  
A
B
C
D
CE1  
BWC  
BWD  
VSS  
VDD  
BWB  
BWA  
VSS  
VSS  
CE  
ADSC  
OE  
A
BWE  
GW  
VSS  
VSS  
ADV  
ADSP  
VDDQ  
VDDQ  
3
A
CE2  
VDDQ  
VDDQ  
CLK  
VSS  
VSS  
A
NC/576M  
DQPB  
DQB  
NC  
VSS  
VDD  
NC/1G  
DQB  
DQC  
DQC  
DQC  
DQC  
DQC  
NC  
DQC  
DQC  
DQC  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQB  
DQB  
DQB  
NC  
DQB  
DQB  
DQB  
ZZ  
E
F
G
H
J
DQD  
DQD  
DQD  
DQD  
DQD  
DQD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
DQA  
DQA  
DQA  
K
L
DQD  
DQPD  
NC  
DQD  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
A
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
A
M
N
P
NC/72M  
TDI  
A1  
TDO  
A0  
MODE  
A
A
A
TMS  
TCK  
A
A
A
A
R
CY7C1442AV33 (2M x 18)  
1
2
A
3
4
5
NC  
6
7
8
9
10  
A
11  
A
NC/288M  
NC/144M  
NC  
A
B
C
D
BWB  
NC  
CE  
CE1  
CE2  
BWE  
GW  
VSS  
VSS  
ADSC  
OE  
ADV  
ADSP  
VDDQ  
VDDQ  
3
A
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
A
NC/576M  
DQPA  
DQA  
NC  
VDDQ  
VDDQ  
VSS  
VDD  
VSS  
NC/1G  
NC  
NC  
DQB  
VDD  
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQA  
DQA  
DQA  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQB  
DQB  
DQB  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
NC  
NC  
NC  
K
L
NC  
NC  
DQB  
DQPB  
NC  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
A
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
NC  
NC  
A
M
N
P
NC/72M  
TDI  
A1  
TDO  
MODE  
A
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05383 Rev. *E  
Page 5 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Pin Configurations (continued)  
209-ball FBGA (14 x 22 x 1.76 mm) Pinout  
CY7C1446AV33 (512K × 72)  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
A
CE  
DQG  
DQG  
DQG  
DQG  
ADSC  
BW  
A
ADSP  
ADV  
A
CE  
2
DQB  
DQB  
DQB  
DQB  
DQB  
3
BWS  
NC/288M  
NC/144M  
BWS  
BWS  
F
BWS  
B
C
G
DQG  
DQG  
DQG  
DQG  
NC/576M  
GW  
BWS  
NC  
BWS  
CE  
BWS  
A
BWS  
E
DQB  
DQB  
D
1
H
V
NC/1G OE  
V
NC  
V
SS  
DQB  
SS  
DQPG DQPC  
V
V
V
V
V
V
DDQ  
DDQ  
DDQ  
SS  
DDQ  
DD  
DD  
DD  
DQPF DQPB  
DQC  
DQC  
V
V
V
DQF  
DQF  
V
V
NC  
NC  
NC  
NC  
V
V
SS  
SS  
SS  
SS  
DD  
SS  
G
H
J
DQC  
DQC  
V
DQC  
V
V
DDQ  
V
DD  
V
V
DDQ  
DQF  
DQF  
DDQ  
DDQ  
V
V
V
V
V
V
V
DQC  
DQC  
NC  
DQF  
DQF  
SS  
SS  
SS  
SS  
SS  
SS  
DQC  
NC  
V
V
V
DDQ  
V
V
DDQ  
DD  
DD  
DDQ  
DDQ  
DQF  
NC  
DQF  
NC  
K
L
CLK  
V
V
NC  
V
SS  
SS  
SS  
NC  
NC  
DQH  
DQH  
DQH  
V
V
V
NC  
NC  
NC  
ZZ  
V
V
V
DDQ  
DD  
SS  
DD  
DDQ  
DDQ  
DQA  
DQA  
DQA  
DDQ  
M
N
P
R
T
V
V
V
V
DQH  
DQH  
DQH  
V
V
SS  
SS  
SS  
SS  
SS  
DQA  
DQA  
DQA  
V
V
V
DDQ  
DQH  
DQH  
DQPD  
DQD  
DQD  
V
V
V
V
V
V
DD  
DD  
DDQ  
DDQ  
DDQ  
DQA  
DQA  
DQPA  
DQE  
DQE  
V
V
V
V
V
V
V
SS  
SS  
SS  
SS  
SS  
SS  
V
V
V
DQPH  
DQD  
DQD  
DQD  
DQD  
DDQ  
DD  
DD  
DDQ  
DDQ  
SS  
DDQ  
DD  
DQPE  
DQE  
DQE  
DQE  
DQE  
NC  
V
NC  
A
NC  
NC  
A
MODE  
A
SS  
U
V
W
A
A
A
NC/72M  
A
A
A1  
A
DQD  
DQD  
A
A
A
DQE  
DQE  
TDI  
TDO  
TCK  
A
A0  
A
TMS  
Pin Definitions  
Name  
I/O  
Description  
Address Inputs used to select one of the address locations. Sampled at the rising edge  
A , A , A  
Input-  
Synchronous  
0
1
[2]  
of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active.  
1
2
3
A1: A0 are fed to the two-bit counter.  
BW , BW ,  
Input-  
Synchronous  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the  
SRAM. Sampled on the rising edge of CLK.  
A
B
BW , BW ,  
C
D
BW , BW ,  
E
F
BW , BW  
G
H
GW  
Input-  
Synchronous  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,  
a global write is conducted (ALL bytes are written, regardless of the values on BW and  
X
BWE).  
BWE  
CLK  
Input-  
Synchronous  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal  
must be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment  
the burst counter when ADV is asserted LOW, during a burst operation.  
CE  
Input-  
Synchronous  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
1
with CE and CE to select/deselect the device. ADSP is ignored if CE is HIGH. CE is  
2
3
1
1
sampled only when a new external address is loaded.  
Document #: 38-05383 Rev. *E  
Page 6 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Pin Definitions (continued)  
Name  
I/O  
Description  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction  
with CE and CE to select/deselect the device. CE is sampled only when a new external  
CE  
Input-  
Synchronous  
2
3
1
3
2
address is loaded.  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
with CE and CE to select/deselect the device. Not available for AJ package version. Not  
CE  
Input-  
Synchronous  
1
2
connected for BGA. Where referenced, CE is assumed active throughout this document  
3
for BGA. CE is sampled only when a new external address is loaded.  
3
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.  
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,  
and act as input data pins. OE is masked during the first clock of a read cycle when emerging  
from a deselected state.  
ADV  
Input-  
Synchronous  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,  
it automatically increments the address in a burst cycle.  
ADSP  
Input-  
Synchronous  
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.  
When asserted LOW, addresses presented to the device are captured in the address  
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both  
asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH.  
1
ADSC  
Input-  
Synchronous  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.  
When asserted LOW, addresses presented to the device are captured in the address  
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both  
asserted, only ADSP is recognized.  
ZZ  
Input-  
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a  
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this  
pin has to be LOW or left floating. ZZ pin has an internal pull-down.  
I/O-  
Synchronous  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is  
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
DQs, DQP  
X
memory location specified by the addresses presented during the previous  
clock rise of the  
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the  
pins behave as outputs. When HIGH, DQs and DQP are placed in a tri-state condition.  
X
V
V
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
Ground  
Ground for the core of the device.  
SS  
I/O Ground  
Ground for the I/O circuitry.  
SSQ  
DDQ  
I/O Power Supply Power supply for the I/O circuitry.  
MODE  
TDO  
TDI  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V  
DD  
or left floating selects interleaved burst sequence. This is a strap pin and should remain  
static during device operation. Mode Pin has an internal pull-up.  
JTAG serial  
output  
Synchronous  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the  
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available  
on TQFP packages.  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature  
Synchronous  
is not being utilized, this pin can be disconnected or connected to V . This pin is not  
DD  
available on TQFP packages.  
TMS  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature  
Synchronous  
is not being utilized, this pin can be disconnected or connected to V . This pin is not  
DD  
available on TQFP packages.  
TCK  
NC  
JTAG-  
Clock  
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must  
be connected to V . This pin is not available on TQFP packages.  
SS  
No Connects. Not internally connected to the die  
NC/72M,  
NC/144M,  
NC/288M,  
NC/576M,  
NC/1G  
No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M  
and NC/1G are address expansion pins are not internally connected to the die.  
Document #: 38-05383 Rev. *E  
Page 7 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
then the Write operation is controlled by BWE and BW  
signals.  
Functional Overview  
X
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
The  
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
provides Byte Write capability that is described in the Write  
Cycle Descriptions table. Asserting the Byte Write Enable  
input (BWE) with the selected Byte Write (BW ) input, will  
selectively write to only the desired bytes. Bytes not selected  
during a Byte Write operation will remain unaltered. A  
synchronous self-timed Write mechanism has been provided  
to simplify the Write operations.  
Maximum access delay from the clock rise (t ) is 2.6ns  
CO  
X
(250-MHz device).  
The  
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
supports secondary cache in systems utilizing either a linear  
or interleaved burst sequence. The interleaved burst order  
supports Pentium and i486processors. The linear burst  
sequence is suited for processors that utilize a linear burst  
sequence. The burst order is user selectable, and is deter-  
mined by sampling the MODE input. Accesses can be initiated  
with either the Processor Address Strobe (ADSP) or the  
Controller Address Strobe (ADSC). Address advancement  
through the burst sequence is controlled by the ADV input. A  
two-bit on-chip wraparound burst counter captures the first  
address in a burst sequence and automatically increments the  
address for the rest of the burst access.  
Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
is a common I/O device, the Output Enable (OE) must be  
deasserted HIGH before presenting data to the DQs inputs.  
Doing so will tri-state the output drivers. As a safety  
precaution, DQs are automatically tri-stated whenever a Write  
cycle is detected, regardless of the state of OE.  
Single Write Accesses Initiated by ADSC  
ADSC Write accesses are initiated when the following condi-  
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
deserted HIGH, (3) CE , CE , CE are all asserted active, and  
(4) the appropriate combination of the Write inputs (GW, BWE,  
and BW ) are asserted active to conduct a Write to the desired  
byte(s). ADSC-triggered Write accesses require a single clock  
cycle to complete. The address presented to A is loaded into  
the address register and the address advancement logic while  
being delivered to the memory array. The ADV input is ignored  
during this cycle. If a global Write is conducted, the data  
presented to the DQs is written into the corresponding address  
location in the memory core. If a Byte Write is conducted, only  
the selected bytes are written. Bytes not selected during a  
Byte Write operation will remain unaltered. A synchronous  
self-timed Write mechanism has been provided to simplify the  
Write operations.  
Byte Write operations are qualified with the Byte Write Enable  
1
2
3
(BWE) and Byte Write Select (BW ) inputs. A Global Write  
X
Enable (GW) overrides all Byte Write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed Write circuitry.  
X
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. ADSP is ignored if CE  
1
is HIGH.  
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,  
(2) CE , CE , CE are all asserted active, and (3) the Write  
1
2
3
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if  
Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
is a common I/O device, the Output Enable (OE) must be  
deasserted HIGH before presenting data to the DQs inputs.  
Doing so will tri-state the output drivers. As a safety  
precaution, DQs are automatically tri-stated whenever a Write  
cycle is detected, regardless of the state of OE.  
CE is HIGH. The address presented to the address inputs (A)  
1
is stored into the address advancement logic and the Address  
Register while being presented to the memory array. The  
corresponding data is allowed to propagate to the input of the  
Output Registers. At the rising edge of the next clock the data  
is allowed to propagate through the output register and onto  
the data bus within 2.6 ns (250-MHz device) if OE is active  
LOW. The only exception occurs when the SRAM is emerging  
from a deselected state to a selected state, its outputs are  
always tri-stated during the first cycle of the access. After the  
first cycle of the access, the outputs are controlled by the OE  
signal. Consecutive single Read cycles are supported. Once  
the SRAM is deselected at clock rise by the chip select and  
either ADSP or ADSC signals, its output will tri-state immedi-  
ately.  
Burst Sequences  
The  
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33  
provides a two-bit wraparound counter, fed by A1: A0, that  
implements either an interleaved or linear burst sequence. The  
interleaved burst sequence is designed specifically to support  
Intel Pentium applications. The linear burst sequence is  
designed to support processors that follow a linear burst  
sequence. The burst sequence is user selectable through the  
MODE input. Asserting ADV LOW at clock rise will automati-  
cally increment the burst counter to the next address in the  
burst sequence. Both Read and Write burst operations are  
supported.  
Single Write Accesses Initiated by ADSP  
This access is initiated when both of the following conditions  
are satisfied at clock rise: (1) ADSP is asserted LOW, and  
Sleep Mode  
(2) CE , CE , CE are all asserted active. The address  
1
2
3
presented to A is loaded into the address register and the  
address advancement logic while being delivered to the  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
memory array. The Write signals (GW, BWE, and BW ) and  
X
ADV inputs are ignored during this first cycle.  
ADSP-triggered Write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQs inputs is written into the corre-  
sponding address location in the memory array. If GW is HIGH,  
the  
“sleep” mode. CE , CE , CE , ADSP, and ADSC must  
1
2
3
remain inactive for the duration of t  
returns LOW.  
after the ZZ input  
Page 8 of 31  
ZZREC  
Document #: 38-05383 Rev. *E  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
Linear Burst Address Table (MODE = GND)  
)
First  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
First  
Second  
Address  
A1: A0  
Third  
Address  
A1: A0  
Fourth  
Address  
A1: A0  
Address  
A1: A0  
Address  
A1: A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
ZZ > V – 0.2V  
Min.  
Max.  
100  
Unit  
mA  
ns  
I
t
t
t
t
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
ZZ Inactive to exit sleep current  
0
ns  
RZZI  
Truth Table [2, 3, 4, 5, 6, 7]  
Operation  
Add. Used CE  
CE  
X
L
CE ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
3
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Sleep Mode, Power Down  
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
WRITE Cycle, Begin Burst  
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
READ Cycle, Suspend Burst  
None  
None  
H
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
None  
L
X
L
L
None  
L
H
H
X
L
None  
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
L
None  
X
L
X
X
X
L
X
Tri-State  
Q
External  
External  
External  
External  
External  
Next  
L-H  
L
L
L
H
X
L
L-H Tri-State  
L
L
H
H
H
H
H
X
X
H
X
H
L-H  
L-H  
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State  
L-H  
L-H Tri-State  
L-H  
L-H Tri-State  
X
X
H
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
Q
Next  
L
H
L
Next  
L
Q
Next  
L
H
X
X
L
Next  
L
L-H  
L-H  
L-H  
D
D
Q
Next  
L
L
Current  
H
H
Notes:  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.  
4. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.  
OE  
OE  
5. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .  
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks  
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a  
don't care for the remainder of the write cycle.  
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is  
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 38-05383 Rev. *E  
Page 9 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
[2, 3, 4, 5, 6, 7]  
Truth Table (continued)  
Operation  
Add. Used CE  
CE  
X
CE ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
3
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
Current  
Current  
Current  
Current  
Current  
X
H
H
X
H
X
X
X
X
X
L
L
L
L
L
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State  
X
L-H  
Q
X
H
X
X
L-H Tri-State  
X
L-H  
L-H  
D
D
X
L
Truth Table for Read/Write[4,8,9]  
Function (CY7C1440AV33)  
GW  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE  
H
L
BW  
X
H
H
H
H
H
H
H
H
L
BW  
BW  
X
H
H
L
BW  
A
D
C
B
Read  
Read  
X
H
H
H
H
L
X
H
L
Write Byte A – (DQ and DQP )  
L
A
A
Write Byte B – (DQ and DQP )  
L
H
L
B
B
Write Bytes B, A  
Write Byte C – (DQ and DQP )  
L
L
L
H
H
L
H
L
C
C
Write Bytes C, A  
Write Bytes C, B  
Write Bytes C, B, A  
L
L
L
L
H
L
L
L
L
Write Byte D – (DQ and DQP )  
L
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A  
Write Bytes D, B  
Write Bytes D, B, A  
Write Bytes D, C  
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes  
X
X
X
X
X
Truth Table for Read/Write[4, 8, 9]  
Function (CY7C1442AV33)  
GW  
H
BWE  
BW  
X
BW  
A
B
Read  
Read  
H
L
L
L
L
L
X
X
H
L
H
H
H
L
Write Byte A – (DQ and DQP )  
H
A
A
Write Byte B – (DQ and DQP )  
H
H
L
B
B
Write Bytes B, A  
Write All Bytes  
Write All Bytes  
H
L
H
L
L
L
X
X
Notes:  
8. BW represents any byte write signal. To enable any byte write BW , a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled  
x
x
at the same time for any given write.  
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.  
X
Document #: 38-05383 Rev. *E  
Page 10 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Truth Table for Read/Write[4, 8, 9]  
Function (CY7C1446AV33)  
GW  
H
BWE  
BW  
X
Read  
Read  
H
L
L
L
X
X
H
All BW = H  
Write Byte x – (DQ and DQP )  
H
L
All BW = L  
X
x
x
Write All Bytes  
Write All Bytes  
H
L
Test Access Port (TAP)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
Test Clock (TCK)  
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incor-  
porates a serial boundary scan test access port (TAP). This  
part is fully compliant with IEEE Standard 1149.1. The TAP  
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 contains  
a TAP controller, instruction register, boundary scan register,  
bypass register, and ID register.  
Test MODE SELECT (TMS)  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
Test Data-In (TDI)  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. TDI  
is internally pulled up and can be unconnected if the TAP is  
unused in an application. TDI is connected to the most signif-  
icant bit (MSB) of any register. (See Tap Controller Block  
Diagram.)  
be connected to V through a pull-up resistor. TDO should be  
DD  
left unconnected. Upon power-up, the device will come up in  
a reset state which will not interfere with the operation of the  
device.  
TAP Controller State Diagram  
TEST-LOGIC  
1
RESET  
0
Test Data-Out (TDO)  
1
1
1
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
TAP Controller Block Diagram  
1
1
0
1
1
EXIT1-DR  
EXIT1-IR  
Bypass Register  
0
0
2
1
0
0
0
PAUSE-DR  
0
PAUSE-IR  
0
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
1
1
Selection  
Circuitry  
TDI  
TDO  
0
0
.
.
.
2
1
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
x
.
.
.
.
.
2
1
1
0
1
0
Boundary Scan Register  
TCK  
TMS  
The 0/1 next to each state represents the value of TMS at the  
rising edge of TCK.  
TAP CONTROLLER  
Document #: 38-05383 Rev. *E  
Page 11 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Performing a TAP Reset  
TAP Instruction Set  
A RESET is performed by forcing TMS HIGH (V ) for five  
DD  
Overview  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
Eight different instructions are possible with the three bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
At power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
TAP Registers  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
IDCODE  
Instruction Register  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
The IDCODE instruction is loaded into the instruction register  
upon power-up or whenever the TAP controller is given a test  
logic reset state.  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board-level serial test data path.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High-Z state until the next command is  
given during the “Update IR” state.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the in-  
struction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is cap-  
tured in the boundary scan register.  
(V ) when the BYPASS instruction is executed.  
SS  
Boundary Scan Register  
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is possi-  
ble that during the Capture-DR state, an input or output will  
undergo a transition. The TAP may then try to capture a signal  
while in transition (metastable state). This will not harm the  
device, but there is no guarantee as to the value that will be  
captured. Repeatable results may not be possible.  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the I/O ring.  
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI, and the LSB is connected to TDO.  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
hold times (t and t ). The SRAM clock input might not be  
Identification (ID) Register  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the bound-  
ary scan register between the TDI and TDO pins.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells pri-  
or to the selection of another boundary scan test operation.  
Document #: 38-05383 Rev. *E  
Page 12 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
The boundary scan register has a special bit located at, bit #89  
(for 165-FBGA package) or bit #138 (for 209-FBGA package).  
When this scan cell, called the “extest output bus tri-state”, is  
latched into the preload register during the “Update-DR” state  
in the TAP controller, it will directly control the state of the  
output (Q-bus) pins, when the EXTEST is entered as the  
current instruction. When HIGH, it will enable the output  
buffers to drive the output bus. When LOW, this bit will place  
the output bus into a High-Z condition.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO pins. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
This bit can be set by entering the SAMPLE/PRELOAD or  
EXTEST command, and then shifting the desired bit into that  
cell, during the “Shift-DR” state. During “Update-DR”, the value  
loaded into that shift-register cell will latch into the preload  
register. When the EXTEST instruction is entered, this bit will  
directly control the output Q-bus pins. Note that this bit is  
pre-set HIGH to enable the output when the device is  
powered-up, and also when the TAP controller is in the  
Test-Logic-Reset” state.  
EXTEST  
The EXTEST instruction enables the preloaded data to be  
driven out through the system output pins. This instruction also  
selects the boundary scan register to be connected for serial  
access between the TDI and TDO in the shift-DR controller  
state.  
EXTEST OUTPUT BUS TRI-STATE  
Reserved  
IEEE Standard 1149.1 mandates that the TAP controller be  
able to put the output bus into a tri-state mode.  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
Document #: 38-05383 Rev. *E  
Page 13 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
[10, 11]  
TAP AC Switching Characteristics Over the operating Range  
Parameter  
Clock  
Description  
Min.  
Max.  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ............................................... V to 3.3V  
Input pulse levels.................................................V to 2.5V  
SS  
SS  
Input rise and fall times...................... ..............................1ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels................... ......................1.25V  
Output reference levels .................. ..............................1.25V  
Test load termination supply voltage .................... ........1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.5V  
1.25V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
ZO= 50Ω  
20pF  
20pF  
Notes:  
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
Document #: 38-05383 Rev. *E  
Page 14 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
TAP DC Electrical Characteristics And Operating Conditions  
[12]  
(0°C < TA < +70°C; V = 3.135 to 3.6V unless otherwise noted)  
DD  
Parameter  
Description  
Test Conditions  
Min.  
2.4  
2.0  
2.9  
2.1  
Max.  
Unit  
V
V
V
V
V
V
V
Output HIGH Voltage  
I
I
I
= –4.0 mA, V  
= –1.0 mA, V  
= –100 µA  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
V
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
V
V
V
V
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
V
OH2  
OL1  
OL2  
IH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
I
I
I
= 8.0 mA  
= 1.0 mA  
= 100 µA  
0.4  
0.4  
0.2  
0.2  
V
OL  
OL  
OL  
V
V
V
2.0  
1.7  
V
V
+ 0.3  
V
DD  
DD  
+ 0.3  
V
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
I
GND < V < V  
DDQ  
µA  
X
IN  
Identification Register Definitions  
CY7C1440AV33 CY7C1442AV33 CY7C1446AV33  
Instruction Field  
(1M x 36)  
(2M x 18)  
(512K x 72)  
Description  
Revision Number (31:29)  
000  
000  
000  
Describes the version number.  
Reserved for Internal Use  
[13]  
Device Depth (28:24)  
01011  
01011  
01011  
Architecture/Memory Type(23:18)  
000000  
000000  
000000  
Defines memory type and  
architecture  
Bus Width/Density(17:12)  
100111  
010111  
110111  
Defines width and density  
Cypress JEDEC ID Code (11:1)  
00000110100  
00000110100  
00000110100 Allows unique identification of  
SRAM vendor.  
ID Register Presence Indicator (0)  
1
1
1
Indicates the presence of an ID  
register.  
Scan Register Sizes  
Register Name  
Bit Size (x36)  
Bit Size (x18)  
Bit Size (x72)  
Instruction  
Bypass  
ID  
3
1
3
1
3
1
32  
89  
32  
89  
32  
Boundary Scan Order (165-ball FBGA package)  
Boundary Scan Order (209-ball FBGA package)  
138  
Identification Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the I/O ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
RESERVED  
010  
011  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
Do Not Use: This instruction is reserved for future use.  
Notes:  
12. All voltages referenced to V (GND).  
SS  
13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.  
Document #: 38-05383 Rev. *E  
Page 15 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Identification Codes (continued)  
Instruction  
Code  
Description  
SAMPLE/PRELOAD  
100  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
165-ball FBGA Boundary Scan Order [14,15]  
CY7C1440AV33 (1M x 36), CY7C1442AV33 (2M x 18)  
Bit #  
1
ball ID  
Bit #  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
ball ID  
E11  
D11  
G10  
F10  
E10  
D10  
C11  
A11  
B11  
A10  
B10  
A9  
Bit #  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
ball ID  
A3  
A2  
B2  
C2  
B1  
A1  
C1  
D1  
E1  
F1  
Bit #  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
ball ID  
N1  
N6  
N7  
2
N2  
3
N10  
P11  
P8  
P1  
4
R1  
5
R2  
6
R8  
P3  
7
R9  
R3  
8
P9  
P2  
9
P10  
R10  
R11  
H11  
N11  
M11  
L11  
K11  
J11  
M10  
L10  
K10  
J10  
H9  
R4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
P4  
G1  
D2  
E2  
F2  
N5  
P6  
B9  
R6  
C10  
A8  
Internal  
G2  
H1  
H3  
J1  
B8  
A7  
B7  
B6  
K1  
L1  
A6  
M1  
J2  
B5  
A5  
A4  
B4  
B3  
H10  
G11  
F11  
K2  
L2  
M2  
Notes:  
14. Balls that are NC (No Connect) are preset LOW.  
15. Bit# 89 is preset HIGH.  
Document #: 38-05383 Rev. *E  
Page 16 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
[14, 16]  
209-ball FBGA Boundary Scan Order  
CY7C1446AV33 (512K x 72)  
Bit #  
1
ball ID  
Bit #  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
ball ID  
Bit #  
71  
ball ID  
Bit #  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
ball ID  
K3  
F6  
K8  
W6  
V6  
H6  
C6  
B6  
A6  
A5  
B5  
C5  
D5  
D4  
C4  
A4  
B4  
C3  
B3  
A3  
A2  
A1  
B2  
B1  
C2  
C1  
D2  
D1  
E1  
E2  
F2  
F1  
G1  
G2  
H2  
H1  
J2  
2
72  
K4  
3
U6  
K9  
73  
K6  
4
W7  
V7  
K10  
J11  
J10  
H11  
H10  
G11  
G10  
F11  
F10  
E10  
E11  
D11  
D10  
C11  
C10  
B11  
B10  
A11  
A10  
C9  
74  
K2  
5
75  
L2  
6
U7  
76  
L1  
7
T7  
77  
M2  
M1  
N2  
N1  
P2  
8
V8  
78  
9
U8  
79  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
T8  
80  
V9  
81  
U9  
82  
P1  
P6  
83  
R2  
R1  
T2  
W11  
W10  
V11  
V10  
U11  
U10  
T11  
T10  
R11  
R10  
P11  
P10  
N11  
N10  
M11  
M10  
L11  
L10  
K11  
M6  
84  
85  
86  
T1  
87  
U2  
U1  
V2  
88  
89  
90  
V1  
91  
W2  
W1  
T6  
92  
93  
B9  
94  
U3  
V3  
A9  
95  
D7  
96  
T4  
C8  
97  
T5  
B8  
98  
U4  
V4  
A8  
99  
D8  
100  
101  
102  
103  
104  
105  
5W  
5V  
C7  
B7  
5U  
Internal  
A7  
J1  
L6  
D6  
K1  
N6  
J6  
G6  
Note:  
16. Bit# 138 is preset HIGH.  
Document #: 38-05383 Rev. *E  
Page 17 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.3V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND ......0.3V to +V  
Range  
Temperature  
V
V
DDQ  
DDQ  
DD  
DD  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%  
+ 0.5V  
to V  
DDQ  
DD  
Industrial  
–40°C to +85°C  
[17, 18]  
Electrical Characteristics Over the Operating Range  
DC Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
V
3.6  
DD  
V
V
V
V
V
I
for 3.3V I/O  
for 2.5V I/O  
V
V
DDQ  
DD  
2.625  
V
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = 4.0 mA  
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = 1.0 mA  
2.0  
V
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
OL  
for 2.5V I/O, I = 1.0 mA  
V
OL  
[17]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
2.0  
1.7  
V
V
+ 0.3V  
V
DD  
DD  
+ 0.3V  
V
[17]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
Input Leakage Current GND V V  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
µA  
SS  
30  
5
µA  
DD  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 167 MHz  
All speeds  
475  
425  
375  
225  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
MAX CYC  
Current  
I
I
I
I
Automatic CE  
Power-down  
Current—TTL Inputs  
V = Max, Device Deselected,  
DD  
SB1  
SB2  
SB3  
SB4  
V
V or V V  
IN  
IH  
IN  
IL  
f = f  
= 1/t  
MAX CYC  
Automatic CE  
Power-down  
Current—CMOS Inputs f = 0  
V
V
= Max, Device Deselected,  
0.3V or V > V – 0.3V,  
All speeds  
120  
200  
135  
mA  
mA  
mA  
DD  
IN  
IN  
DDQ  
Automatic CE  
Power-down  
Current—CMOS Inputs f = f  
V = Max, Device Deselected, or All speeds  
DD  
V
0.3V or V > V  
– 0.3V  
IN  
IN  
DDQ  
= 1/t  
MAX  
CYC  
Automatic CE  
Power-down  
Current—TTL Inputs  
V
V
= Max, Device Deselected,  
All speeds  
DD  
V or V V , f = 0  
IN  
IH IN IL  
Notes:  
17. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
18. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
Power-up  
DD  
IH  
DD  
DDQ DD.  
Document #: 38-05383 Rev. *E  
Page 18 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Capacitance[19]  
100 TQFP  
Max.  
165 FBGA 209 FBGA  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max.  
Max.  
Unit  
pF  
C
T = 25°C, f = 1 MHz,  
6.5  
3
7
7
6
5
5
7
IN  
A
V
= 3.3V  
= 2.5V  
DD  
C
C
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
DDQ  
5.5  
pF  
Thermal Resistance[19]  
100 TQFP  
Package  
165 FBGA 209 FBGA  
Unit  
Parameter  
Description  
Test Conditions  
Package  
Package  
Θ
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard  
test methods and procedures  
for measuring thermal  
25.21  
20.8  
25.31  
°C/W  
JA  
Thermal Resistance  
(Junction to Case)  
2.28  
3.2  
4.48  
°C/W  
JC  
impedance, per EIA/JESD51.  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
90%  
10%  
Z = 50Ω  
0
10%  
R = 50Ω  
L
GND  
5 pF  
R = 351Ω  
INCLUDING  
JIG AND  
SCOPE  
1ns  
1ns  
V = 1.5V  
T
(a)  
(b)  
(c)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
INCLUDING  
JIG AND  
SCOPE  
1ns  
1ns  
V = 1.25V  
T
(a)  
(b)  
(c)  
Note:  
19. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05383 Rev. *E  
Page 19 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
[24, 25]  
Switching Characteristics Over the Operating Range  
–250  
–200  
–167  
Parameter  
Description  
Min.  
Max  
Min. Max. Min.  
Max  
Unit  
[20]  
t
V
(Typical) to the first Access  
1
1
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
4.0  
1.5  
1.5  
5
6
ns  
ns  
ns  
CYC  
CH  
2.0  
2.0  
2.4  
2.4  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
2.6  
3.2  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
1.0  
1.0  
1.5  
1.3  
1.5  
1.5  
DOH  
CLZ  
[21, 22, 23]  
Clock to Low-Z  
[21, 22, 23]  
Clock to High-Z  
2.6  
2.6  
3.0  
3.0  
3.4  
3.4  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[21, 22, 23]  
OE LOW to Output Low-Z  
0
0
0
[21, 22, 23]  
OE HIGH to Output High-Z  
2.6  
3.0  
3.4  
Set-up Times  
t
t
t
t
t
t
Address Set-up Before CLK Rise  
ADSC, ADSP Set-up Before CLK Rise  
ADV Set-up Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ADS  
ADVS  
WES  
DS  
GW, BWE, BW Set-up Before CLK Rise  
X
Data Input Set-up Before CLK Rise  
Chip Enable Set-up Before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
ADSP, ADSC Hold After CLK Rise  
ADV Hold After CLK Rise  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ADH  
ADVH  
WEH  
DH  
GW, BWE, BW Hold After CLK Rise  
X
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
CEH  
Notes:  
20. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation  
DD  
POWER  
can be initiated.  
21. t  
, t  
,t  
, and t  
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
22. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
OEHZ  
OELZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
23. This parameter is sampled and not 100% tested.  
24. Timing reference level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05383 Rev. *E  
Page 20 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Switching Waveforms  
[26]  
Read Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BWx  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
t
CHZ  
OELZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note:  
26. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05383 Rev. *E  
Page 21 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Switching Waveforms (continued)  
[26, 27]  
Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BWE,  
BWX  
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note:  
27.  
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.  
X
Document #: 38-05383 Rev. *E  
Page 22 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Switching Waveforms (continued)  
[26, 28, 29]  
Read/Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
t
t
WEH  
WES  
BWE,  
BWX  
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes:  
28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.  
29. GW is HIGH.  
Document #: 38-05383 Rev. *E  
Page 23 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Switching Waveforms (continued)  
[30, 31]  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.  
31. DQs are in high-Z when exiting ZZ sleep mode.  
Document #: 38-05383 Rev. *E  
Page 24 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Part and Package Type  
167 CY7C1440AV33-167AXC  
CY7C1442AV33-167AXC  
CY7C1440AV33-167BZC  
CY7C1442AV33-167BZC  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1440AV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1442AV33-167BZXC  
CY7C1446AV33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1446AV33-167BGXC  
CY7C1440AV33-167AXI  
CY7C1442AV33-167AXI  
CY7C1440AV33-167BZI  
CY7C1442AV33-167BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
lndustrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1440AV33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1442AV33-167BZXI  
CY7C1446AV33-167BGI  
CY7C1446AV33-167BGXI  
200 CY7C1440AV33-200AXC  
CY7C1442AV33-200AXC  
CY7C1440AV33-200BZC  
CY7C1442AV33-200BZC  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1440AV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1442AV33-200BZXC  
CY7C1446AV33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1446AV33-200BGXC  
CY7C1440AV33-200AXI  
CY7C1442AV33-200AXI  
CY7C1440AV33-200BZI  
CY7C1442AV33-200BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
lndustrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1440AV33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1442AV33-200BZXI  
CY7C1446AV33-200BGI  
CY7C1446AV33-200BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
Document #: 38-05383 Rev. *E  
Page 25 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Part and Package Type  
250 CY7C1440AV33-250AXC  
CY7C1442AV33-250AXC  
CY7C1440AV33-250BZC  
CY7C1442AV33-250BZC  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1440AV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1442AV33-250BZXC  
CY7C1446AV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
CY7C1446AV33-250BGXC  
CY7C1440AV33-250AXI  
CY7C1442AV33-250AXI  
CY7C1440AV33-250BZI  
CY7C1442AV33-250BZI  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Industrial  
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)  
CY7C1440AV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free  
CY7C1442AV33-250BZXI  
CY7C1446AV33-250BGI  
CY7C1446AV33-250BGXI  
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)  
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free  
Document #: 38-05383 Rev. *E  
Page 26 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Package Diagrams  
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
1.40 0.05  
14.00 0.10  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
0.25  
1. JEDEC STD REF MS-026  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Document #: 38-05383 Rev. *E  
Page 27 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Package Diagrams (continued)  
PIN 1 CORNER  
BOTTOM VIEW  
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
Ø0.25 M C A B  
Ø0.45 0.05(165X)  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00  
5.00  
10.00  
B
15.00 0.10  
0.15(4X)  
51-85165-*A  
SEATING PLANE  
C
Document #: 38-05383 Rev. *E  
Page 28 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Package Diagrams (continued)  
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)  
51-85167-**  
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM  
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05383 Rev. *E  
Page 29 of 31  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Document History Page  
Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync  
SRAM  
Document Number: 38-05383  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
124437  
254910  
03/04/03  
See ECN  
CJM  
SYT  
New data sheet  
*A  
Part number changed from previous revision. New and old part number differ  
by the letter “A”  
Modified Functional Block diagrams  
Modified switching waveforms  
Added Boundary scan information  
Added Footnote #14 (32-Bit Vendor ID Code changed)  
Added I , I and I values in the DC Electrical Characteristics  
DD  
X
SB  
Added t  
specifications in Switching Characteristics table  
POWER  
Removed 119 PBGA package  
Changed 165 FBGA package from BB165C (15 x 17 x 1.20 mm) to BB165  
(15 x 17 x 1.40 mm)  
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22  
x 1.76 mm)  
*B  
306335  
See ECN  
SYT  
Changed H9 pin from V  
FBGA on Page # 6  
to V on the Pin Configuration table for 209  
SSQ SS  
Changed t from 3.0 to 3.2 ns and t  
from 1.3 ns to 1.5 ns for 200 Mhz  
DOH  
CO  
speed bin on the Switching Characteristics table on Page # 19  
Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W respectively for  
TQFP Package on Pg # 19  
Replaced ΘJA and ΘJC from TBD to respective Values for 165 BGA and 209  
FBGA Packages on the Thermal Resistance Table  
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 FBGA  
Packages  
Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for  
frequencies of 250, 200 and 167 MHz respectively  
Changed ISB1 from 190, 180 and 170 mA to 225 mA for frequencies of 250,  
200 and 167 MHz respectively  
Changed ISB2 from 80 to 100 mA  
Changed ISB3 from 180, 170 and 160 mA to 200 mA for frequencies of 250,  
200 and 167 MHz respectively  
Changed ISB4 from 100 to 110 mA  
*C  
332173  
See ECN  
SYT  
Modified Address Expansion balls in the pinouts for 165 FBGA and 209  
FBGA Package as per JEDEC standards  
Modified V  
Changed C , C  
V
test conditions  
and C to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA  
I/O  
OL, OH  
IN CLK  
Package  
Changed I  
and I  
from 100 and 110 mA to 120 and 135 mA respectively  
SB4  
SB2  
Added Industrial Temperature Grade  
Included the missing 100 TQFP Package Diagram  
Updated the Ordering Information by Shading and Unshading MPNs as per  
availability  
*D  
417547  
See ECN  
RXU  
Converted from Preliminary to Final  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed I current value in MODE from –5 & 30 µA to –30 & 5 µA respec-  
X
tively and also Changed I current value in ZZ from –30 & 5 µA to –5 & 30  
X
µA respectively on page# 18  
Modified test condition in note# 8 from V < V to V < V  
IH  
DD  
IH  
DD  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Replaced Package Diagram of 51-85050 from *A to *B  
Updated the Ordering Information  
Document #: 38-05383 Rev. *E  
Page 30 of 31  
CY7C1440AV33  
CY7C1442AV33  
CY7C1446AV33  
Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync  
SRAM  
Document Number: 38-05383  
Orig. of  
REV.  
ECN NO. Issue Date Change  
Description of Change  
*E  
473650  
See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND.  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP  
TH TL  
TDOV  
AC Switching Characteristics table.  
Updated the Ordering Information table.  
Document #: 38-05383 Rev. *E  
Page 31 of 31  

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