Cypress CY7C141 User Manual

CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
1K x 8 Dual-Port Static RAM  
Features  
Functional Description  
True dual-ported memory cells, which allow simultaneous  
reads of the same memory location  
The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141  
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports  
are provided permitting independent access to any location in  
memory. The CY7C130/130A/ CY7C131/131A can be used as  
either a standalone 8-bit dual-port static RAM or as a master  
dual-port RAM in conjunction with the CY7C140/CY7C141 slave  
dual-port device in systems requiring 16-bit or greater word  
widths. It is the solution to applications requiring shared or  
buffered data, such as cache memory for DSP, bit-slice, or multi-  
processor designs.  
1K x 8 organization  
0.65 micron CMOS for optimum speed and power  
High speed access: 15 ns  
Low operating power: ICC = 110 mA (maximum)  
Fully asynchronous operation  
Each port has independent control pins; chip enable (CE), write  
enable (R/W), and output enable (OE). Two flags are provided  
on each port, BUSY and INT. BUSY signals that the port is trying  
to access the same location currently being accessed by the  
other port. INT is an interrupt flag indicating that data is placed  
in a unique location (3FF for the left port and 3FE for the right  
port). An automatic power down feature is controlled indepen-  
dently on each port by the chip enable (CE) pins.  
Automatic power down  
Master CY7C130/130A/CY7C131/131A easily expands data  
bus width to 16 or more bits using slave CY7C140/CY7C141  
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY  
input on CY7C140/CY7C141  
INT flag for port-to-port communication  
The CY7C130/130A and CY7C140 are available in 48-pin DIP.  
The CY7C131/131A and CY7C141 are available in 52-pin  
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free  
PQFP.  
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,  
52-pin TQFP  
Pb-free packages available  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
L
CE  
R
OE  
L
OE  
R
I/O  
I/O  
I/O  
I/O  
7L  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
0R  
0L  
[2]  
BUSY  
BUSY  
R
L
A
A
A
9L  
0L  
9R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
ARBITRATION  
LOGIC  
(7C130/7C131 ONLY)  
AND  
CE  
L
CE  
R
INTERRUPT LOGIC  
OE  
L
OE  
R
R/W  
R/W  
R
L
[3]  
L
INT  
INT  
R
Notes  
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.  
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.  
CY7C140/CY7C141 (Slave): BUSY is input.  
3. Open drain outputs: pull-up resistor required.  
Cypress Semiconductor Corporation  
Document #: 38-06002 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 09, 2008  
     
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Pin Definitions  
Left Port  
CEL  
Right Port  
Description  
CER  
Chip Enable  
Read/Write Enable  
Output Enable  
Address  
R/WL  
R/WR  
OER  
OEL  
A0L–A11/12L  
I/O0L–I/O15/17L  
INTL  
A0R–A11/12R  
I/O0R–I/O15/17R  
INTR  
Data Bus Input/Output  
Interrupt Flag  
Busy Flag  
BUSYL  
VCC  
BUSYR  
Power  
GND  
Ground  
Selection Guide  
7C130-30  
7C130-35  
7C131-35  
7C140-35  
7C141-35  
7C130-45  
7C131-45  
7C140-45  
7C141-45  
7C130-55  
7C131-55  
7C140-55  
7C141-55  
7C131-15[4]  
7C131A-15  
7C141-15  
7C130A-30  
7C131-30  
7C140-30  
7C141-30  
7C131-25[4]  
7C141-25  
Parameter  
Unit  
Maximum Access Time  
15  
25  
30  
35  
45  
55  
ns  
Maximum Operating  
Current  
Com’l/Ind  
Com’l/Ind  
190  
170  
170  
120  
120  
110  
mA  
Maximum Standby  
Current  
75  
65  
65  
45  
45  
35  
mA  
Shaded areas contain preliminary information.  
Note  
4. 15 and 25 ns version available only in PLCC/PQFP packages.  
Document #: 38-06002 Rev. *E  
Page 3 of 19  
   
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Maximum Ratings[5]  
DC Input Voltage ............................................–3.5V to +7.0V  
Output Current into Outputs (LOW)............................. 20 mA  
Exceeding maximum ratings may shorten the useful life of the  
device. User guidelines are not tested.  
Static Discharge Voltage........................................... >2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature ................................. –65°C to +150  
°C  
Latch Up Current .................................................... >200 mA  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Operating Range  
Supply Voltage to Ground Potential  
(Pin 48 to Pin 24)............................................–0.5V to +7.0V  
Range  
Commercial  
Industrial  
Ambient Temperature  
VCC  
0°C to +70°C  
–40°C to +85°C  
–55°C to +125°C  
5V ± 10%  
5V ± 10%  
5V ± 10%  
DC Voltage Applied to Outputs  
in High Z State................................................–0.5V to +7.0V  
Military[6]  
Electrical Characteristics Over the Operating Range[7]  
7C130-30[4]  
7C130-35,45 7C130-55  
7C131-35,45 7C131-55  
7C140-35,45 7C140-55  
7C141-35,45 7C141-55  
7C131-15[4] 7C130A-30  
7C131A-15 7C131-25,30  
Parameter  
Description  
Test Conditions  
Unit  
7C141-15  
7C140-30  
7C141-25,30  
Min Max Min Max Min Max Min Max  
VOH  
VOL  
Output HIGH Voltage VCC = Min, IOH = –4.0 mA  
Output LOW Voltage IOL = 4.0 mA  
IOL = 16.0 mA[8]  
2.4  
2.4  
2.2  
2.4  
2.4  
V
V
0.4  
0.5  
0.4  
0.5  
0.4  
0.5  
0.4  
0.5  
VIH  
VIL  
IIX  
Input HIGH Voltage  
2.2  
2.2  
2.2  
V
V
Input LOW Voltage  
0.8  
+5  
+5  
0.8  
+5  
+5  
0.8  
+5  
+5  
0.8  
+5  
+5  
Input Leakage Current GND < VI < VCC  
–5  
–5  
–5  
–5  
–5  
–5  
–5  
–5  
μA  
μA  
IOZ  
Output Leakage  
Current  
GND < VO < VCC  
Output Disabled  
,
IOS  
Output Short  
VCC = Max,  
–350  
190  
75  
–350  
170  
65  
–350  
120  
45  
–350 mA  
110 mA  
35 mA  
75 mA  
Circuit Current[9, 10]  
V
OUT = GND  
ICC  
VCC Operating  
Supply Current  
CE = VIL,  
Outputs Open, f = fMAX  
Com’l  
Com’l  
Com’l  
[11]  
ISB1  
ISB2  
Standby Current  
Both Ports, TTL Inputs f = fMAX  
CEL and CER > VIH,  
[11]  
Standby Current  
One Port,  
TTL Inputs  
CEL or CER > VIH,  
135  
115  
90  
Active Port Outputs Open  
[11]  
f = fMAX  
ISB3  
Standby Current  
Both Ports,  
CMOS Inputs  
Both Ports CEL and CER > Com’l  
VCC – 0.2V,  
VIN > VCC – 0.2V  
15  
15  
15  
85  
15 mA  
70 mA  
or VIN < 0.2V, f = 0  
ISB4  
Standby Current  
One Port,  
One Port CEL or  
Com’l  
125  
105  
CER > VCC – 0.2V,  
CMOS Inputs  
VIN > VCC – 0.2V  
or VIN < 0.2V,  
Active Port Outputs Open, f =  
fMAX  
Shaded areas contain preliminary information.  
Notes  
5. The voltage on any input or I/O pin cannot exceed the power pin during power up.  
6. is the “instant on” case temperature  
T
A
7. See the last page of this specification for Group A subgroup testing information.  
8. BUSY and INT pins only.  
9. Duration of the short circuit should not exceed 30 seconds.  
10. This parameter is guaranteed but not tested.  
11. At f = f  
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t and using AC Test Waveforms input levels of GND to 3V.  
MAX  
RC  
Document #: 38-06002 Rev. *E  
Page 4 of 19  
             
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Capacitance[10]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
Max  
15  
Unit  
pF  
CIN  
COUT  
10  
pF  
Figure 4. AC Test Loads and Waveforms  
5V  
R1 893Ω  
R1 893Ω  
5V  
5V  
OUTPUT  
OUTPUT  
281Ω  
BUSY  
R2  
347Ω  
R2  
347Ω  
OR  
INT  
30 pF  
5 pF  
30  
pF  
INCLUDING  
JIGAND  
INCLUDING  
JIGAND  
(a)  
(b)  
3.0V  
SCOPE  
SCOPE  
BUSY Output Load  
(CY7C130/CY7C131 ONLY)  
ALL INPUT PULSES  
90%  
Equivalent to:  
THÉVENIN EQUIVALENT  
90%  
10%  
10%  
250Ω  
GND  
OUTPUT  
1.40V  
5ns  
5ns  
Document #: 38-06002 Rev. *E  
Page 5 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Characteristics Over the Operating Range[7, 12]  
7C130-30  
7C130-25[4]  
7C131-25  
7C140-25  
7C141-25  
7C131-15[4]  
7C131A-15  
7C141-15  
7C130A-30  
7C131-30  
7C140-30  
7C141-30  
Parameter  
Description  
Unit  
Min  
15  
0
Max  
Min  
Max  
Min  
30  
0
Max  
Read Cycle  
tRC  
Read Cycle Time  
Address to Data Valid[13]  
25  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
15  
25  
30  
tOHA  
tACE  
Data Hold from Address Change  
CE LOW to Data Valid[13]  
OE LOW to Data Valid[13]  
OE LOW to Low Z[10, 14, 15]  
OE HIGH to High Z[10, 14, 15]  
CE LOW to Low Z[10, 14, 15]  
CE HIGH to High Z[10, 14, 15]  
CE LOW to Power Up[10]  
CE HIGH to Power Down[10]  
15  
10  
25  
15  
30  
20  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
3
3
0
3
5
0
3
5
0
10  
10  
15  
15  
15  
25  
15  
15  
25  
tPD  
Write Cycle[16]  
tWC  
Write Cycle Time  
15  
12  
12  
2
25  
20  
20  
2
30  
25  
25  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
CE LOW to Write End  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
R/W Pulse Width  
tAW  
tHA  
tSA  
0
0
0
tPWE  
tSD  
12  
10  
0
15  
15  
0
25  
15  
0
Data Setup to Write End  
Data Hold from Write End  
R/W LOW to High Z[15]  
tHD  
tHZWE  
tLZWE  
10  
15  
15  
0
0
0
Shaded areas contain preliminary information.  
Notes  
12. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified  
I
/I and 30 pF load capacitance.  
OL OH,  
13. AC Test Conditions use V = 1.6V and V = 1.4V.  
OH  
OL  
14. At any given temperature and voltage condition for any given device, t  
is less than t  
and t  
is less than t  
.
LZOE  
HZCE  
LZCE  
HZOE  
15. t  
, t  
, t  
, t  
, t  
and t  
are tested with C = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.  
LZCE LZWE HZOE LZOE HZCE  
HZWE  
L
16. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can  
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-06002 Rev. *E  
Page 6 of 19  
         
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Characteristics Over the Operating Range[7, 12] (continued)  
7C130-30  
7C130-25[4]  
7C131-25  
7C140-25  
7C141-25  
7C131-15[4]  
7C131A-15  
7C141-15  
7C130A-30  
7C131-30  
7C140-30  
7C141-30  
Parameter  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Busy/Interrupt Timing  
tBLA  
tBHA  
tBLC  
tBHC  
tPS  
BUSY LOW from Address Match  
BUSY HIGH from Address Mismatch[17]  
BUSY LOW from CE LOW  
BUSY HIGH from CE HIGH[17]  
Port Set Up for Priority  
15  
15  
15  
15  
20  
20  
20  
20  
20  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
5
0
5
0
5
0
tWB  
R/W LOW after BUSY LOW  
tWH  
R/W HIGH after BUSY HIGH  
BUSY HIGH to Valid Data  
13  
20  
30  
tBDD  
tDDD  
tWDD  
15  
25  
30  
Write Data Valid to Read Data Valid  
Write Pulse to Data Delay  
Note 19  
Note 19  
Interrupt Timing  
tWINS  
tEINS  
tINS  
R/W to INTERRUPT Set Time  
15  
15  
15  
15  
15  
15  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
ns  
ns  
ns  
ns  
ns  
ns  
CE to INTERRUPT Set Time  
Address to INTERRUPT Set Time  
OE to INTERRUPT Reset Time[17]  
CE to INTERRUPT Reset Time[17]  
Address to INTERRUPT Reset Time[17]  
tOINR  
tEINR  
tINR  
Shaded areas contain preliminary information.  
Notes  
17. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.  
18. CY7C140/CY7C141 only.  
19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:  
BUSY on Port B goes HIGH.  
Port B’s address is toggled.  
CE for Port B is toggled.  
R/W for Port B is toggled during valid read.  
Document #: 38-06002 Rev. *E  
Page 7 of 19  
     
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Characteristics Over the Operating Range[7,12]  
7C130-35  
7C131-35  
7C140-35  
7C141-35  
7C130-45  
7C130-55  
7C131-55  
7C140-55  
7C141-55  
7C131-45  
7C140-45  
7C141-45  
Parameter  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Read Cycle  
tRC  
Read Cycle Time  
Address to Data Valid[13]  
35  
0
45  
0
55  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
35  
45  
55  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
Data Hold from Address Change  
CE LOW to Data Valid[13]  
OE LOW to Data Valid[13]  
OE LOW to Low Z[10, 14, 15]  
OE HIGH to High Z[10, 14, 15]  
CE LOW to Low Z[10, 14, 15]  
CE HIGH to High Z[10, 14, 15]  
CE LOW to Power Up[10]  
CE HIGH to Power Down[10]  
35  
20  
45  
25  
55  
25  
3
5
0
3
5
0
3
5
0
20  
20  
35  
20  
20  
35  
25  
25  
35  
tPD  
Write Cycle[16]  
tWC Write Cycle Time  
tSCE  
tAW  
35  
30  
30  
2
45  
35  
35  
2
55  
40  
40  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
R/W Pulse Width  
tHA  
tSA  
0
0
0
tPWE  
tSD  
25  
15  
0
30  
20  
0
30  
20  
0
Data Setup to Write End  
Data Hold from Write End  
tHD  
tHZWE  
tLZWE  
20  
20  
25  
R/W HIGH to Low Z[15]  
0
0
0
Busy/Interrupt Timing  
tBLA BUSY LOW from Address Match  
20  
20  
20  
20  
25  
25  
25  
25  
30  
30  
30  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tBHA  
tBLC  
tBHC  
tPS  
BUSY HIGH from Address Mismatch[17]  
BUSY LOW from CE LOW  
BUSY HIGH from CE HIGH[17]  
Port Set Up for Priority  
5
0
5
0
5
0
tWB  
R/W LOW after BUSY LOW  
R/W HIGH after BUSY HIGH  
BUSY HIGH to Valid Data  
tWH  
30  
35  
35  
tBDD  
tDDD  
tWDD  
35  
45  
45  
Write Data Valid to Read Data Valid  
Write Pulse to Data Delay  
Note 19  
Note 19  
Note 19  
Note 19 ns  
Note 19 ns  
Interrupt Timing  
tWINS  
tEINS  
tINS  
R/W to INTERRUPT Set Time  
25  
25  
25  
25  
25  
25  
35  
35  
35  
35  
35  
35  
45  
45  
45  
45  
45  
45  
ns  
ns  
ns  
ns  
ns  
ns  
CE to INTERRUPT Set Time  
Address to INTERRUPT Set Time  
OE to INTERRUPT Reset Time[17]  
CE to INTERRUPT Reset Time[17]  
Address to INTERRUPT Reset Time[17]  
tOINR  
tEINR  
tINR  
Document #: 38-06002 Rev. *E  
Page 8 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Waveforms  
Figure 5. Read Cycle No. 1[20, 21]  
Either Port Address Access  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATAVALID  
DATA VALID  
Figure 6. Read Cycle No. 2[20, 22]  
Either Port CE/OE Access  
CE  
OE  
t
HZCE  
t
ACE  
t
HZOE  
t
DOE  
t
LZOE  
t
LZCE  
DATA VALID  
DATA OUT  
t
PU  
t
PD  
I
CC  
I
SB  
Figure 7. Read Cycle No. 3[21]  
Read with BUSY, Master: CY7C130 and CY7C131  
t
RC  
ADDRESS  
ADDRESS MATCH  
R
t
PWE  
R/W  
R
t
HD  
D
INR  
VALID  
ADDRESS MATCH  
ADDRESS  
L
t
PS  
t
BHA  
BUSY  
L
t
BLA  
t
BDD  
DOUT  
VALID  
L
t
DDD  
t
WDD  
Notes  
20. R/W is HIGH for read cycle.  
21. Device is continuously selected, CE = V and OE = V .  
IL  
IL  
22. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-06002 Rev. *E  
Page 9 of 19  
     
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Waveforms (continued)  
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[16, 23]  
Either Port  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
AW  
HA  
t
SA  
t
PWE  
R/W  
t
t
HD  
SD  
DATAIN  
OE  
DATA VALID  
t
HZOE  
HIGH IMPEDANCE  
D
OUT  
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[17, 24]  
t
WC  
ADDRESS  
CE  
t
t
HA  
SCE  
t
AW  
t
SA  
t
PWE  
R/W  
t
t
SD  
HD  
DATAIN  
DATA VALID  
t
LZWE  
t
HZWE  
HIGH IMPEDANCE  
DATAOUT  
Notes  
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t  
or t  
+ t to allow the data I/O pins to enter high impedance  
HZWE SD  
PWE  
and for data to be placed on the bus for the required t  
.
SD  
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.  
Document #: 38-06002 Rev. *E  
Page 10 of 19  
   
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Waveforms (continued)  
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)  
CEL Valid First:  
ADDRESS LR,  
ADDRESS MATCH  
CE  
L
t
PS  
CE  
R
t
t
BHC  
BLC  
BUSY  
R
CER Valid First:  
ADDRESSL,R  
ADDRESS MATCH  
CE  
R
t
PS  
CE  
L
t
t
BHC  
BLC  
BUSY  
L
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)  
Left Address Valid First:  
t
or t  
WC  
RC  
ADDRESS MATCH  
ADDRESS MISMATCH  
ADDRESS  
L
t
PS  
ADDRESS  
R
t
t
BHA  
BLA  
BUSY  
R
Right Address Valid First:  
t
or t  
WC  
RC  
ADDRESS MATCH  
ADDRESS MISMATCH  
ADDRESS  
R
t
PS  
ADDRESS  
L
t
t
BHA  
BLA  
BUSY  
L
Document #: 38-06002 Rev. *E  
Page 11 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Waveforms (continued)  
Figure 12. Busy Timing Diagram No. 3  
Write with BUSY (Slave:CY7C140/CY7C141)  
CE  
t
PWE  
R/W  
t
t
WH  
WB  
BUSY  
Document #: 38-06002 Rev. *E  
Page 12 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Switching Waveforms (continued)  
Figure 13. Interrupt Timing Diagrams  
Left Side Sets INTR  
t
WC  
ADDR  
WRITE 3FF  
L
t
t
HA  
INS  
CE  
L
t
EINS  
R/W  
L
t
SA  
t
WINS  
INT  
R
Right Side Clears INTR  
t
RC  
ADDR  
R
READ 3FF  
t
t
INT  
HA  
CE  
R
t
EINR  
R/W  
R
OE  
R
t
OINR  
INT  
R
Right Side Sets INTL  
t
WC  
ADDR  
R
WRITE 3FE  
t
t
HA  
INS  
CE  
R
t
EINS  
R/W  
R
t
SA  
t
WINS  
INT  
L
Left Side Clears INTL  
t
RC  
ADDR  
R
READ 3FE  
t
t
INR  
HA  
CE  
L
t
EINR  
R/W  
L
OE  
L
t
OINR  
INT  
L
Document #: 38-06002 Rev. *E  
Page 13 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Typical DC and AC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
120  
100  
80  
1.4  
1.2  
1.0  
0.8  
1.2  
1.0  
ICC  
ICC  
0.8  
0.6  
0.4  
60  
VCC = 5.0V  
TA = 25°C  
VCC = 5.0V  
VIN = 5.0V  
0.6  
0.4  
40  
ISB3  
0.2  
0.6  
20  
0
I SB3  
0.2  
0.0  
–55  
25  
125  
0
1.0  
2.0  
3.0  
4.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
1.1  
100  
80  
1.2  
1.0  
60  
TA = 25°C  
VCC = 5.0V  
1.0  
40  
0.8  
VCC = 5.0V  
20  
0
0.9  
0.8  
TA = 25°C  
0.6  
–55  
0.0  
1.0  
2.0  
3.0  
4.0  
25  
125  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
TYPICAL POWER-ON CURRENT  
vs. SUPPLY VOLTAGE  
TYPICAL ACCESS TIME CHANGE  
vs. OUTPUT LOADING  
NORMALIZED ICC vs. CYCLE TIME  
1.25  
30.0  
25.0  
3.0  
2.5  
VCC = 4.5V  
TA = 25°C  
VIN = 0.5V  
1.0  
2.0  
20.0  
15.0  
10.0  
1.5  
1.0  
0.75  
VCC = 4.5V  
TA = 25°C  
0.5  
0.0  
5.0  
0
0.50  
10  
20  
30  
40  
0
1.0  
2.0  
3.0  
4.0 5.0  
0
200 400 600 800 1000  
CAPACITANCE (pF)  
CYCLE FREQUENCY (MHz)  
SUPPLY VOLTAGE (V)  
Document #: 38-06002 Rev. *E  
Page 14 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Ordering Information  
Speed  
(ns)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
30  
CY7C130-30PC  
CY7C130A-30PI  
CY7C130-35PC  
CY7C130-35PI  
CY7C130-45PC  
CY7C130-45PI  
CY7C130-55PC  
CY7C130-55PI  
CY7C131-15JC  
CY7C131-15JXC  
CY7C131-15NC  
CY7C131-15JI  
CY7C131A-15JXI  
CY7C131-15NXI  
CY7C131-25JC  
CY7C131-25JXC  
CY7C131-25NC  
CY7C131-25NXC  
CY7C131-25JI  
CY7C131-25NI  
CY7C131-30JC  
CY7C131-30NC  
CY7C131-30JI  
CY7C131-35JC  
CY7C131-35NC  
CY7C131-35JI  
CY7C131-35NI  
CY7C131-45JC  
CY7C131-45NC  
CY7C131-45JI  
CY7C131-45NI  
CY7C131-55JC  
CY7C131-55JXC  
CY7C131-55NC  
CY7C131-55NXC  
CY7C131-55JI  
CY7C131-55JXI  
CY7C131-55NI  
CY7C131-55NXI  
CY7C140-30PC  
CY7C140-30PI  
P25  
P25  
P25  
P25  
P25  
P25  
P25  
P25  
J69  
J69  
N52  
J69  
J69  
N52  
J69  
J69  
N52  
N52  
J69  
N52  
J69  
N52  
J69  
J69  
N52  
J69  
N52  
J69  
N52  
J69  
N52  
J69  
J69  
N52  
N52  
J69  
J69  
N52  
N52  
P25  
P25  
48-Pin (600 Mil) Molded DIP  
48-Pin Pb-Free (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
52-Pin Plastic Leaded Chip Carrier  
Commercial  
Industrial  
35  
45  
55  
15  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
52-Pin Pb-Free Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Pb-Free Plastic Leaded Chip Carrier  
52-Pin Pb-Free Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Pb-Free Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
25  
Commercial  
52-Pin Pb-Free Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
30  
35  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Commercial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
Commercial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
45  
55  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Commercial  
Industrial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Pb-Free Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Commercial  
52-Pin Pb-Free Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Pb-Free Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
52-Pin Pb-Free Plastic Quad Flatpack  
48-Pin (600 Mil) Molded DIP  
30  
Commercial  
Industrial  
48-Pin (600 Mil) Molded DIP  
Document #: 38-06002 Rev. *E  
Page 15 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Ordering Information (continued)  
Speed  
Package  
Name  
Operating  
Range  
Ordering Code  
(ns)  
Package Type  
35  
45  
55  
15  
25  
CY7C140-35PC  
CY7C140-35PI  
CY7C140-45PC  
CY7C140-45PI  
CY7C140-55PC  
CY7C140-55PI  
CY7C141-15JC  
CY7C141-15NC  
CY7C141-25JC  
CY7C141-25JXC  
CY7C141-25NC  
CY7C141-25JI  
CY7C141-25NI  
CY7C141-30JC  
CY7C141-30NC  
CY7C141-30JI  
CY7C141-35JC  
CY7C141-35NC  
CY7C141-35JI  
CY7C141-35NI  
CY7C141-45JC  
CY7C141-45NC  
CY7C141-45JI  
CY7C141-45NI  
CY7C141-55JC  
CY7C141-55NC  
CY7C141-55JI  
CY7C141-55NI  
P25  
P25  
P25  
P25  
P25  
P25  
J69  
N52  
J69  
J69  
N52  
J69  
N52  
J69  
N52  
J69  
J69  
N52  
J69  
N52  
J69  
N52  
J69  
N52  
J69  
N52  
J69  
N52  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
48-Pin (600 Mil) Molded DIP  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Commercial  
52-Pin Pb-Free Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
30  
35  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Commercial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
Commercial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Industrial  
45  
55  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Commercial  
Industrial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Commercial  
Industrial  
52-Pin Plastic Leaded Chip Carrier  
52-Pin Plastic Quad Flatpack  
Document #: 38-06002 Rev. *E  
Page 16 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Package Diagrams  
Figure 14. 48-Pin (600 Mil) Sidebraze DIP D26  
MIL-STD-1835 D-14 Config. C  
51-80044 **  
Figure 15. 52-Pin Pb-Free Plastic Leaded Chip Carrier J69  
MIN.  
DIMENSIONS IN INCHES  
MAX.  
SEATING PLANE  
PIN #1 ID  
7
1
47  
8
46  
0.013  
0.021  
0.750  
0.756  
0.045  
0.055  
0.690  
0.730  
0.785  
0.795  
20  
34  
0.023  
0.033  
21  
33  
0.020 MIN.  
0.750  
0.756  
0.090  
0.130  
0.165  
0.200  
0.785  
0.795  
51-85004-*A  
Document #: 38-06002 Rev. *E  
Page 17 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Package Diagrams (continued)  
Figure 16. 48-Pin (600 Mil) Molded DIP P25  
51-85020-*B  
Figure 17. 52-Pin Pb-Free Plastic Quad Flatpack N52  
51-85042-**  
Document #: 38-06002 Rev. *E  
Page 18 of 19  
CY7C130, CY7C130A  
CY7C131, CY7C131A  
CY7C140, CY7C141  
Document History Page  
Document Title: CY7C130/CY7C130A/CY7C131/CY7C131A/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM  
Document Number: 38-06002  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
110169  
122255  
236751  
325936  
SZV  
RBI  
09/29/01  
12/26/02  
See ECN  
See ECN  
Change from Spec number: 38-00027 to 38-06002  
Power up requirements added to Maximum Ratings Information  
Removed cross information from features section  
*A  
*B  
*C  
YDT  
RUY  
Added pin definitions table, 52-pin PQFP package diagram and Pb-free  
information  
*D  
*E  
393153  
YIM  
See ECN  
12/17/08  
Added CY7C131-15JI to ordering information  
Added Pb-Free parts to ordering information:  
CY7C131-15JXI  
2623540 VKN/PYRS  
Added CY7C130A and CY7C131A parts  
Removed military information  
Updated ordering information table  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Clocks & Buffers  
Wireless  
Memories  
CAN 2.0b  
Image Sensors  
USB  
© Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-06002 Rev. *E  
Revised December 09, 2008  
Page 19 of 19  
All products and company names mentioned in this document may be the trademarks of their respective holders.  

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