CY7C1365C
9-Mbit (256K x 32) Flow-Through Sync SRAM
Features
Functional Description[1]
• 256K x 32 common I/O
The CY7C1365C is a 256K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
• 3.3V core power supply (V
)
DD
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
)
DDQ
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• Provide high-performance 2-1-1-1 access rate
®
• User-selectable burst counter supporting Intel
®
[2]
(CE ), depth-expansion Chip Enables (CE and CE ), Burst
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
1
2
3
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin
.
• Asynchronous output enable
The CY7C1365C allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
• Supports 3.3V I/O level
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• “ZZ” Sleep Mode option
Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1365C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
250
40
180
mA
mA
40
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. is not available on 2 Chip Enable TQFP package.
CE
3
Cypress Semiconductor Corporation
Document #: 38-05690 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
CY7C1365C
Pin Configurations
100-Pin TQFP Pinout (2 Chip Enable) (AJ version)
NC
1
NC
80
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB
DQB
3
4
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
5
6
7
8
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1365C
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE D
BYTE A
Document #: 38-05690 Rev. *E
Page 3 of 18
CY7C1365C
Pin Configurations (continued)
100-Pin TQFP Pinout (3 Chip Enable) (A version)
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
1
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
DQB
DQB
3
4
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
5
6
7
8
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1365C
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE D
BYTE A
Document #: 38-05690 Rev. *E
Page 4 of 18
CY7C1365C
Pin Descriptions
Name
TQFP
I/O
Description
Address Inputs used to select one of the 256K address
A0, A1, A 37,36,32,33,34,35,44,45,46,
47,48,49,50,81,82,99,100
Input-
Synchronous locations. Sampled at the rising edge of the CLK if ADSP or ADSC
is active LOW, and CE , CE , andCE are sampled active. A feed
92 (for 2 Chip Enable Version)
43 (for 3 Chip Enable Version)
1
2
3
[1:0]
the 2-bit counter.
BW BW 93,94,
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to
A,
B,
95,96
88
Synchronous conduct Byte Writes to the SRAM. Sampled on the rising edge of
CLK.
BW BW
C,
D
GW
Input-
Synchronous the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW and BWE).
Global Write Enable Input, active LOW. When asserted LOW on
[A:D]
BWE
CLK
87
89
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge
Synchronous of CLK. This signal must be asserted LOW to conduct a Byte Write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
Also used to increment the burst counter whenADV is asserted LOW,
during a burst operation.
CE
98
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
1
Synchronous CLK. Used in conjunction with CE and CE to select/deselect the
2
3
device. ADSP is ignored
a new external address is loaded.
CE is sampled only when
if CE is HIGH.
1
1
CE
CE
97
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
2
Synchronous CLK. Used in conjunction with CE and CE to select/deselect the
1
3
device. CE is sampled only when a new external address is loaded.
2
92 (for 3 Chip Enable Version)
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of
3
Synchronous CLK. Used in conjunction with CE and CE to select/deselect the
1
2
device. CE is assumed active throughout this document for BGA.
3
CE is sampled only when a new external address is loaded.
3
86
Input-
Output Enable, asynchronous input, active LOW. Controls the
OE
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a Read cycle when
emerging from a deselected state.
83
84
Input-
Advance Input signal, sampled on the rising edge of CLK. When
ADV
Synchronous asserted, it automatically increments the address in a burst cycle.
ADSP
Input- Address Strobe from Processor, sampled on the rising edge of
Synchronous CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A are also loaded
[1:0]
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when
CE is deasserted
1
HIGH.
85
Input-
Synchronous CLK, active LOW. When asserted LOW, addresses presented to the
device are captured in the address registers. A are also loaded
Address Strobe from Controller, sampled on the rising edge of
ADSC
[1:0]
into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized.
ZZ
64
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the
Asynchronous device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQs
52,53,56, 57,58,59, 62,63,68,
69,72,73,74,75,78,79,2,3,6,7, Synchronous data register that is triggered by the rising edge of CLK. As outputs,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip
8,9,12,13,18,19,22,23,24,25,
28,29
they deliver the data contained in the memory location specified by
the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs are
placed in a tri-state condition.
Document #: 38-05690 Rev. *E
Page 5 of 18
CY7C1365C
Pin Descriptions (continued)
Name
TQFP
15,41,65, 91
I/O
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
Description
V
V
V
DD
17,40,67,90
SS
4,11,20,27,54,61,70,77
I/O Power Power supply for the I/O circuitry.
Supply
DDQ
,
V
5,10,21,26,55,60,71,76
31
I/O Ground Ground for the I/O circuitry.
SSQ
MODE
NC
Input-
Static
Selects Burst Order. When tied to GND selects linear burst
sequence. When tied to V or left floating selects interleaved burst
DD
sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
1,30,51,80,14,16,38,39,42,66
43 (for 2 Chip Enable Version)
No Connects. Not Internally connected to the die.
Document #: 38-05690 Rev. *E
Page 6 of 18
CY7C1365C
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:D])
indicate a write access. ADSC is ignored if ADSP is active
LOW.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
) is 6.5 ns (133-MHz device).
CDV
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[D:A] will be
written into the specified address location. Byte writes are
allowed. During byte writes, BWA controls DQA, BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os
are tri-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE.
The CY7C1365C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize
a linear burst sequence. The burst order is user-selectable,
and is determined by sampling the MODE input. Accesses can
be initiated with either the Processor Address Strobe (ADSP)
or the Controller Address Strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automati-
cally increments the address for the rest of the burst access.
Burst Sequences
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
The CY7C1365C provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Three synchronous Chip Selects (CE , CE , CE ) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
1
2
3
1
Sleep Mode
Single Read Accesses
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE , CE , and CE are all
1
2
3
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
inactive for the duration of t
LOW.
after the ZZ input returns
ZZREC
available at the data outputs a maximum to t
after clock
CDV
rise. ADSP is ignored if CE is HIGH.
1
Interleaved Burst Address Table
(MODE = Floating or VDD
Single Write Accesses Initiated by ADSP
)
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , CE are all asserted
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
1
2
3
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:D]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device.Byte writes are allowed.
During byte writes, BWA controls DQA and BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os
are tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Second
Third
Fourth
Address
Address
Address
Address
A ,A
A ,A
A ,A
A ,A
1
0
1
0
1
0
1
0
00
01
10
11
Single Write Accesses Initiated by ADSC
01
10
11
10
11
00
11
00
01
00
01
10
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
Document #: 38-05690 Rev. *E
Page 7 of 18
CY7C1365C
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > V – 0.2V
Min.
Max.
Unit
mA
ns
I
t
t
t
t
50
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
CYC
ZZ recovery time
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current
This parameter is sampled
This parameter is sampled
2t
ns
0
ns
RZZI
Truth Table[3, 4, 5, 6, 7]
Address
Used
Cycle Description
CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK
DQ
1
3
2
Deselected Cycle,
Power-down
None
None
None
None
None
H
L
L
L
X
X
X
H
X
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H
L-H
L-H
L-H
L-H
Tri-State
Deselected Cycle,
Power-down
L
L
Tri-State
Tri-State
Tri-State
Tri-State
Deselected Cycle,
Power-down
X
L
L
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
Power-down
X
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
L
L
L
H
X
L
Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Tri-State
Next
L
Q
Next
L
H
X
X
L
Tri-State
Next
L
D
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State
Q
H
X
X
Tri-State
D
D
L
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals (BW , BW , BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: D]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05690 Rev. *E
Page 8 of 18
CY7C1365C
Truth Table for Read/Write[3, 4]
Function
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BW
X
H
H
H
H
H
H
H
H
L
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
D
C
B
Read
Read
X
H
L
Write Byte (A, DQP )
L
A
Write Byte (B, DQP )
L
H
L
B
Write Bytes (B, A, DQP , DQP )
L
L
A
B
Write Byte (C, DQP )
L
H
H
L
H
L
C
Write Bytes (C, A, DQP , DQP )
L
L
C
A
Write Bytes (C, B, DQP , DQP )
L
L
H
L
C
B
Write Bytes (C, B, A, DQP , DQP , DQP )
L
L
L
C
B
A
Write Byte (D, DQP )
L
H
H
H
H
L
H
H
L
H
L
D
Write Bytes (D, A, DQP , DQP )
L
L
D
A
Write Bytes (D, B, DQP , DQP )
L
L
H
L
D
A
Write Bytes (D, B, A, DQP , DQP , DQP )
L
L
L
D
B
A
Write Bytes (D, B, DQP , DQP )
L
L
H
H
L
H
L
D
B
Write Bytes (D, B, A, DQP , DQP , DQP )
L
L
L
D
C
A
Write Bytes (D, C, A, DQP , DQP , DQP )
L
L
L
H
L
D
B
A
Write All Bytes
Write All Bytes
L
L
L
L
X
X
X
X
X
Document #: 38-05690 Rev. *E
Page 9 of 18
CY7C1365C
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on V Relative to GND........ –0.5V to +4.6V
DD
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
V
DDQ
DD
Supply Voltage on V
Relative to GND ......–0.5V to +V
DD
DDQ
3.3V –
5%/+10%
2.5V–5%to
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
V
DD
+ 0.5V
DDQ
[8, 9]
Electrical Characteristics Over the Operating Range
CY7C1365C
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
Unit
V
V
3.6
3.6
V
V
DD
for 3.3V I/O
for 2.5V I/O
DDQ
2.625
V
V
V
V
V
I
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
for 3.3V I/O, I = –4.0 mA
V
OH
OL
IH
OH
for 2.5V I/O, I = –1.0 mA
2.0
V
OH
for 3.3V I/O, I = 8.0 mA
0.4
0.4
V
OL
for 2.5V I/O, I = 1.0 mA
V
OL
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
GND ≤ V ≤ V
2.0
1.7
V
V
+ 0.3V
V
DD
DD
+ 0.3V
V
[8]
Input LOW Voltage
–0.3
–0.3
−5
0.8
V
IL
0.7
5
V
Input Leakage Current
except ZZ and MODE
µA
X
I
DDQ
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
µA
µA
µA
mA
mA
mA
SS
DD
SS
DD
5
Input Current of ZZ
30
5
I
I
Output Leakage Current
GND ≤ V ≤ V , Output Disabled
DDQ
–5
OZ
I
V
Operating Supply Current V = Max., I = 0 mA,
OUT
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
250
180
110
DD
DD
DD
f = f
= 1/t
MAX
CYC
I
I
I
I
Automatic CE Power-Down
Current—TTL Inputs
Max. V , Device Deselected, All speeds
DD
SB1
V
≥ V or V ≤ V , f = f
IN
IH IN IL MAX,
inputs switching
Automatic CE Power-Down
Current—CMOS Inputs
Max. V , Device Deselected,
All speeds
All speeds
40
100
40
mA
mA
mA
SB2
SB3
SB4
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN
DD IN
f = 0, inputs static
Automatic CE Power-Down
Current—CMOS Inputs
Max. V , Device Deselected,
DD
V
f = f
≥V
– 0.3V or V ≤ 0.3V,
IN
DDQ IN
, inputs switching
MAX
Automatic CE Power-Down
Current—TTL Inputs
Max. V , Device Deselected, All speeds
DD
V
≥ V or V ≤ V , f = 0,
IN
IH IN IL
inputs static.
Notes:
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
9. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05690 Rev. *E
Page 10 of 18
CY7C1365C
Capacitance[10]
100 TQFP
Max.
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Unit
pF
C
C
C
5
5
5
IN
A
V
= 3.3V
= 2.5V
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
V
DDQ
pF
Thermal Resistance[10]
100 TQFP
Package
Parameter
Description
Test Conditions
Unit
Θ
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
29.41
°C/W
JA
Thermal Resistance
(Junction to Case)
6.13
°C/W
JC
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
INCLUDING
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
T
(a)
JIG AND
SCOPE
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Notes:
10. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05690 Rev. *E
Page 11 of 18
CY7C1365C
[11, 12]
Switching Characteristics Over the Operating Range
–133
–100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
[13]
t
V
(Typical) to the First Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
3.0
3.0
10
4.0
4.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
CDV
DOH
CLZ
2.0
0
2.0
0
[14, 15, 16]
Clock to Low-Z
[14, 15, 16]
Clock to High-Z
3.5
3.5
3.5
3.5
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
[14, 15, 16]
OE LOW to Output Low-Z
0
0
[14, 15, 16]
OE HIGH to Output High-Z
3.5
3.5
Set-up Times
t
t
t
t
t
t
Address Set-up before CLK Rise
ADSP, ADSC Set-up before CLK Rise
ADV Set-up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW
Set-up before CLK Rise
[A:D]
Data Input Set-up before CLK Rise
Chip Enable Set-up
CES
Hold Times
t
t
t
t
t
t
Address Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADSP, ADSC Hold after CLK Rise
ADH
WEH
ADVH
DH
,
,
GW BWE BW
Hold after CLK Rise
[A:D]
ADV Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CEH
Notes:
11. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
13. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
POWER
DD
can be initiated.
14. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
15. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05690 Rev. *E
Page 12 of 18
CY7C1365C
Timing Diagrams
[17]
Read Cycle Timing
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:D]
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
17. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05690 Rev. *E
Page 13 of 18
CY7C1365C
Timing Diagrams (continued)
[18, 19]
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst.
t
t
t
ADH
ADS
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst.
t
t
WEH
WES
BWE,
BW[A:D]
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst.
OE
t
t
DH
DS
Data in (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Notes:
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
Document #: 38-05690 Rev. *E
Page 14 of 18
CY7C1365C
Timing Diagrams (continued)
[17, 19, 20]
Read/Write Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW[A:D]
CE
t
t
WEH
WES
t
t
CEH
CES
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Note:
20.
GW is HIGH.
Document #: 38-05690 Rev. *E
Page 15 of 18
CY7C1365C
Timing Diagrams (continued)
[21, 22]
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
133
CY7C1365C-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
(3 Chip Enable)
CY7C1365C-133AJXC
CY7C1365C-133AXI
CY7C1365C-133AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Industrial
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100
CY7C1365C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
(3 Chip Enable)
CY7C1365C-100AJXC
CY7C1365C-100AXI
CY7C1365C-100AJXI
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Industrial
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05690 Rev. *E
Page 16 of 18
CY7C1365C
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
1.40 0.05
14.00 0.10
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
0.25
1. JEDEC STD REF MS-026
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05690 Rev. *E
Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1365C
Document History Page
Document Title: CY7C1365C 9-Mbit (256K x 32) Flow-Through Sync SRAM
Document Number: 38-05690
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
286269
320834
See ECN
See ECN
PCI
PCI
New data sheet
Added 133 MHz in the Ordering Information table
Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41 and
*A
JA
JC
6.13 °C/W respectively
Modified V test conditions
V
OL, OH
Corrected IDD, tCDV, tCH, tDOH and tCL for 100MHz to 180 mA, 8.5 ns, 4
ns, 2 ns and 4 ns respectively
Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics and truth
table on page# 6
Added Industrial operating range
Updated Ordering Information Table
*B
*C
377095
408725
See ECN
See ECN
PCI
Changed I
from 30 to 40 mA
SB2
Modified test condition in note# 9 from V < V to V < V
IH
DD
IH
DD
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed three state to tri-state
Converted from Preliminary to Final
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information
*D
*E
429278
501828
See ECN
See ECN
NXR
VKN
Added 2.5VI/O option
Updated Ordering Information Table
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Relative to GND
DDQ
Document #: 38-05690 Rev. *E
Page 18 of 18
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