CY7C1334H
2-Mbit (64K x 32) Pipelined SRAM with
NoBL™ Architecture
Features
Functional Description[1]
• Pin compatible and functionally equivalent to ZBT™
devices
The CY7C1334H is
a
3.3V/2.5V, 64K
x
32
synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1334H is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of the SRAM, especially
in systems that require frequent Write/Read transitions.
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed write
• Asynchronous output enable (OE)
Write operations are controlled by the four Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are
[A:D]
• Offered in Lead-Free JEDEC-standard 100-pin TQFP
package
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
U
T
E
N
S
U
T
ADV/LD
BWA
BWB
BWC
BWD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
WRITE
DRIVERS
A
M
P
S
T
E
R
S
F
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05678 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 6, 2006
CY7C1334H
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK. A are fed to the two-bit burst counter.
A0, A1, A
Input-
Synchronous
[1:0]
BW
WE
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
[A:D]
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a Write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE
CE
CE
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
1
2
3
with CE and CE to select/deselect the device.
2
3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE and CE to select/deselect the device.
1
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE and CE to select/deselect the device.
1
2
OE
Input-
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been deselected.
CEN
ZZ
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. During normal operation, this pin can be connected to
or left floating.
V
SS
DQs
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
during the clock rise of the read cycle. The direction of the pins is controlled
[16:0]
by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQ are placed in a tri-state condition. The outputs are automatically tri-stated
s
during the data portion of a write sequence, during the first clock when emerging from a
deselected state, and when the device is deselected, regardless of the state of OE.
MODE
Input
Strap pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V or left floating selects inter-
DD
leaved burst sequence.
V
V
Power Supply Power supply inputs to the core of the device.
DD
I/O Power
Supply
Power supply for the I/O circuitry.
DDQ
V
V
Ground
Ground for the device.
SS
I/O Ground
Ground for the I/O circuitry. Should be connected to the ground of the system
SSQ
NC
No Connects. Not internally connected to the die. 4M, 9M,18M, 72M, 144M, 288M, 576M and
1G are address expansion pins and are not internally connected to the die.
Document #: 38-05678 Rev. *B
Page 3 of 13
CY7C1334H
the state of Chip Enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The CY7C1334H is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
1
2
and CE are ALL asserted active, and (3) the write signal WE
3
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
access delay from the clock rise (t ) is 3.5 ns (166-MHz
device).
CO
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
Accesses can be initiated by asserting all three Chip Enables
(CE , CE , CE ) active at the rising edge of the clock. If Clock
DQP
. In addition, the address for the subsequent access
1
2
3
[A:D]
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW
conduct Byte Write operations.
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs (or a subset
for Byte Write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.
can be used to
[A:D]
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
The data written during the Write operation is controlled by
BW
signals. The CY7C1334H provides Byte Write
[A:D]
Three synchronous Chip Enables (CE , CE , CE ) and an
capability that is described in the Write Cycle Description table.
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
) input will selectively write to only the
[A:D]
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
1
2
Because the CY7C1334H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs. Doing so will tri-state the
output drivers. As a safety precaution, DQs are automatically
tri-stated during the data portion of a Write cycle, regardless of
the state of OE.
and CE are ALL asserted active, (3) the Write Enable input
3
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.
Burst Write Accesses
The CY7C1334H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE , CE , and CE ) and WE inputs are
1
2
3
ignored and the burst counter is incremented. The correct
BW inputs must be driven in each cycle of the burst write
[A:D]
in order to write the correct bytes of data.
Burst Read Accesses
The CY7C1334H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE , CE , and CE , must remain inactive
for the duration of t
1
2
3
after the ZZ input returns LOW.
ZZREC
Document #: 38-05678 Rev. *B
Page 4 of 13
CY7C1334H
Linear Burst Address Table (MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or VDD
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Deselect Cycle
Used
CE
H
X
L
ZZ ADV/LD WE
BW
X
OE
X
X
L
CEN
CLK
L-H
L-H
DQ
x
None
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
L
L
L
L
L
L
L
L
L
L
H
X
Tri-State
Tri-State
Continue Deselect Cycle
None
X
Read Cycle (Begin Burst)
External
Next
X
L-H Data Out (Q)
L-H Data Out (Q)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
X
L
H
L
X
L
External
Next
X
H
H
X
X
X
X
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Tri-State
Tri-State
Data In (D)
Data In (D)
Tri-State
Tri-State
-
X
L
H
L
X
External
Next
L
Write Cycle (Continue Burst)
X
L
H
L
X
L
L
NOP/WRITE ABORT (Begin Burst) None
H
H
X
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
Next
X
X
X
H
X
X
X
X
X
Current
None
Sleep MODE
X
Tri-State
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies
that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
, and WE. See Write Cycle Descriptions table.
[A:D]
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
OE is inactive or when the device is deselected, and DQs = data when OE is active.
= Tri-State when
[A:D]
Document #: 38-05678 Rev. *B
Page 5 of 13
CY7C1334H
Write Cycle Description[2, 3]
Function
WE
H
L
BW
X
H
H
H
H
H
H
H
H
L
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
D
C
B
Read
X
H
L
Write − No bytes written
Write Byte A − (DQ )
L
A
Write Byte B − (DQ )
L
H
L
B
Write Bytes A, B
L
L
Write Byte C − (DQ )
L
H
H
L
H
L
C
Write Bytes C,A
Write Bytes C, B
Write Bytes C, B, A
L
L
L
L
H
L
L
L
L
Write Byte D − (DQ )
L
H
H
H
H
L
H
H
L
H
L
D
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min.
Max.
Unit
I
t
t
t
t
ZZ > V − 0.2V
40
mA
ns
ns
ns
ns
DDZZ
DD
ZZ > V − 0.2V
2t
ZZS
DD
CYC
ZZ < 0.2V
2t
CYC
ZZREC
ZZI
ZZ Active to sleep current
ZZ inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
CYC
0
RZZI
Document #: 38-05678 Rev. *B
Page 6 of 13
CY7C1334H
DC Input Voltage....................................... −0.5V to V + 0.5V
Maximum Rating
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND.........−0.5V to +4.6V
DD
Ambient
Range Temperature (T )
Supply Voltage on V
Relative to GND .......−0.5V to +V
DD
V
V
DDQ
DDQ
A
DD
DC Voltage Applied to Outputs
in Tri-State ................................................−0.5V to V
Com’l
Ind’l
0°C to +70°C
3.3V - 5%/+10% 2.5V-5%to
+ 0.5V
V
DDQ
DD
–40°C to +85°C
[9, 10]
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
Unit
V
V
V
3.6
DD
for 3.3V I/O
for 2.5V I/O
V
V
DDQ
DD
2.625
V
V
V
V
V
I
Output HIGH Voltage
Output LOW Voltage
for 3.3V I/O, I = –4.0 mA
V
OH
OL
IH
OH
for 2.5V I/O, I = –1.0 mA
2.0
OH
for 3.3V I/O, I = 8.0 mA
0.4
0.4
V
V
OL
for 2.5V I/O, I = 1.0 mA
OL
[9]
Input HIGH Voltage
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
GND ≤ V ≤ V
2.0
1.7
V
V
+ 0.3V
DD
DD
+ 0.3V
0.8
[9]
Input LOW Voltage
–0.3
–0.3
–5
V
IL
0.7
Input Leakage Current
except ZZ and MODE
5
µA
X
I
DDQ
Input Current of MODE Input = V
Input = V
−30
−5
µA
µA
SS
DD
SS
DD
5
Input Current of ZZ
Input = V
Input = V
µA
30
5
µA
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
−5
µA
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
240
225
100
90
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
MAX CYC
Current
I
Automatic CE
Power-Down
Current—TTL Inputs
V
= Max, Device
SB1
DD
Deselected,
V
≥ V or V ≤ V
IN
IH
IN
IL
f = f
= 1/t
MAX
CYC
I
I
Automatic CE
Power-Down
Current—CMOS Inputs
V
= Max, Device
All speeds
40
mA
SB2
SB3
DD
Deselected, V ≤ 0.3V or
IN
V
V
> V
– 0.3V, f = 0
IN
DDQ
Automatic CE
Power-Down
Current—CMOS Inputs
= Max, Device
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
85
75
mA
mA
DD
Deselected, or V ≤ 0.3V or
IN
– 0.3V
V
> V
IN
DDQ
f = f
= 1/t
CYC
MAX
I
Automatic CE
Power-Down
Current—TTL Inputs
V
= Max, Device
All Speeds
45
mA
SB4
DD
Deselected,
V ≥ V or V ≤ V , f = 0
IN
IH
IN
IL
Notes:
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
10. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD
Document #: 38-05678 Rev. *B
Page 7 of 13
CY7C1334H
Capacitance[11]
100 TQFP
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
C
5
5
5
IN
A
V
= 3.3V,
= 2.5V
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
V
DDQ
pF
Thermal Resistance[11]
100 TQFP
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance Test conditions follow standard test methods and
(Junction to Ambient) procedures for measuring thermal impedance, per
30.32
°C/W
JA
EIA/JESD51
Θ
Thermal Resistance
(Junction to Case)
6.85
°C/W
JC
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R =1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Notes:
11. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05678 Rev. *B
Page 8 of 13
CY7C1334H
[12, 13]
Switching Characteristics Over the Operating Range
166 MHz
133 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Unit
[14]
t
V
(typical) to the First Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
CO
1.5
0
1.5
0
DOH
CLZ
[15, 16, 17]
Clock to Low-Z
[15, 16, 17]
Clock to High-Z
3.5
3.5
4.0
4.0
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
[15, 16, 17]
OE LOW to Output Low-Z
0
0
[15, 16, 17]
OE HIGH to Output High-Z
3.5
4.0
Set-up Times
t
t
t
t
t
t
Address Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ALS
WES
CENS
DS
GW, BW
Set-up before CLK Rise
[A:D]
CEN Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold after CLK Rise
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ALH
WEH
CENH
DH
GW, BW
Hold after CLK Rise
[A:D]
CEN Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CEH
Notes:
12. Test conditions shown in (a), (b) and (c) of AC Test Loads.
13. Timing reference level is 1.5V when V = 3.3V and 1.25V when V
= 2.5V.
DDQ
DDQ
14. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V minimum initially before a Read or Write operation
POWER
DD
can be initiated.
15. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
16. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Tri-State prior to Low-Z under the same system conditions
17. This parameter is sampled and not 100% tested.
Document #: 38-05678 Rev. *B
Page 9 of 13
CY7C1334H
Switching Waveforms
[18, 19, 20]
Read/Write Timing
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW[A:D]
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
18.
19. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05678 Rev. *B
Page 10 of 13
CY7C1334H
Switching Waveforms (continued)
[18, 19, 21]
NOP, STALL, and Deselect Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
[22, 23]
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
23. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05678 Rev. *B
Page 11 of 13
CY7C1334H
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
CY7C1334H-166AXC
CY7C1334H-166AXI
CY7C1334H-133AXC
CY7C1334H-133AXI
Package Type
166
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
Industrial
133
Commercial
Industrial
Package Diagram
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05678 Rev. *B
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1334H
Document History Page
Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05678
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
347357
424820
See ECN
See ECN
PCI
New Data Sheet
*A
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
< V to V
< V
DDQ
DD
DDQ DD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
*B
459347
See ECN
NXR
Converted from Preliminary to Final
Included 2.5V I/O option
Updated the Ordering Information table.
Document #: 38-05678 Rev. *B
Page 13 of 13
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