Cypress CY7C1312AV18 User Manual

CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

18-Mb QDR™-II SRAM 2-Word Burst Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 333 MHz) @ 167MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x18, and x36 configurations

• Full data coherancy , providing most current data

• Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are

1.8V Synchronous Pipelined SRAMs, equipped with QDR-II

architecture. QDR-II architecture consists of two separate

ports to access the memory array. The Read port has

dedicated Data Outputs to support Read operations and the

Write Port has dedicated Data Inputs to support Write opera-

tions. QDR-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. The

Read address is latched on the rising edge of the K clock and

the Write address is latched on the rising edge of the K clock.

Accesses to the QDR-II Read and Write ports are completely

independent of one another. In order to maximize data

throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with two 8-bit words (CY7C1310AV18) or 18-bit

words (CY7C1312AV18) or 36-bit words (CY7C1314AV18)

that burst sequentially into or out of the device. Since data can

be transferred into and out of the device on every rising edge

of both input clocks (K and K and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball

(11x15 matrix)

• Variable drive HSTL output buffers

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Configurations

CY7C1310AV18 – 2M x 8

CY7C1312AV18 – 1M x 18

CY7C1314AV18 – 512K x 36

Logic Block Diagram (CY7C1310AV18)

D_[7:0]

Write

Reg

Write

Reg

Address

A_(19:0)

Address

A_(19:0)

RPS

Control

Logic

CLK

Gen.

DOFF

Read Data Reg.

V_REF

Reg.

WPS

Control

Logic

BWS_[1:0]

Q_[7:0]

Cypress Semiconductor Corporation

Document #: 38-05497 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised June 1, 2004

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Pin Configurations

CY7C1310AV18 (2M × 8) – 11 × 15 BGA

V_SS/36M

V_SS/72M

NC/144M

RPS

BWS₁

NC/288M

WPS

BWS₀

V_SS

V_DDQ

V_SS

V_DD

V_SS

VSS

V_DDQ

V_DD

V_SS

V_REF

V_DDQ

V_REF

DOFF

V_SS

TDO

TCK

TMS

TDI

CY7C1312AV18 (1M × 18) – 11 × 15 BGA

NC/288M

BWS₀

V_SS/72M

V_SS/144M NC/36M

WPS

RPS

BWS₁

D11

D10

Q10

V_SS

Q12

D13

V_REF

Q11

D12

Q13

V_DDQ

D14

Q14

D15

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

V_REF

V_DD

V_SS

V_DDQ

DOFF

Q15

D17

D16

Q16

Q17

V_SS

TDO

TCK

TMS

TDI

Document #: 38-05497 Rev. *A

Page 3 of 21

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Pin Configurations (continued)

CY7C1314AV18 (512k × 36) – 11 × 15 BGA

V_SS/288M NC/72M

NC/36M V_SS/144M

BWS₂

BWS₁

WPS

RPS

Q27

Q18

Q28

D20

D18

D19

Q19

D17

D16

Q16

Q17

BWS₃

BWS₀

D27

D28

Q29

Q30

D30

V_SS

D15

D29

Q21

D22

V_REF

Q31

D32

Q24

Q20

D21

Q22

V_DDQ

D23

Q23

D24

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

Q15

D14

Q14

D13

V_REF

V_DD

V_SS

Q13

VDDQ

D12

DOFF

D31

Q32

Q33

Q12

D11

Q11

D33

D34

Q35

Q34

D26

D35

D25

Q25

Q26

V_SS

D10

Q10

TDO

TCK

TMS

TDI

Pin Definitions

Pin Name

I/O

Input-

Pin Description

Data input signals, sampled on the rising edge of K and K clocks during valid write

[x:0]

Synchronous

operations.

CY7C1310AV18 - D

CY7C1312AV18 - D

CY7C1314AV18 - D

[7:0]

[17:0]

[35:0]

WPS

Input-

Synchronous

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When

asserted active, a write operation is initiated. Deasserting will deselect the Write port.

Deselecting the Write port will cause D

to be ignored.

[x:0]

BWS , BWS ,

Input-

Synchronous

Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and

K clocks during write operations. Used to select which byte is written into the device

during the current portion of the write operations. Bytes not written remain unaltered.

BWS , BWS

CY7C1310AV18 − BWS controls D

and BWS controls D

[3:0]

[8:0]

[7:4]

CY7C1312AV18 − BWS controls D

and BWS controls D

[17:9].

, BWS controls D

CY7C1314AV18 − BWS controls D

, BWS controls D

[17:9]

[26:18]

and BWS controls D

[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte

Write Select will cause the corresponding byte of data to be ignored and not written into

the device.

Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K (read address) and K (write

address) clocks during active read and write operations. These address inputs are multi-

plexed for both Read and Write operations. Internally, the device is organized as 2M x 8

(2 arrays each of 1M x 8) for CY7C1310AV18, 1M x 18 (2 arrays each of 512K x 18) for

CY7C1312AV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314AV18.

Therefore, only 20 address inputs are needed to access the entire memory array of

CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for

CY7C1314AV18. These inputs are ignored when the appropriate port is deselected.

Document #: 38-05497 Rev. *A

Page 4 of 21

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Pin Definitions (continued)

Pin Name

I/O

Pin Description

Outputs-

Synchronous

Data Output signals. These pins drive out the requested data during a Read operation.

Valid data is driven out on the rising edge of both the C and C clocks during Read

operations or K and K when in single clock mode. When the Read port is deselected,

[x:0]

are automatically tri-stated.

[x:0]

CY7C1310AV18 − Q

CY7C1312AV18 − Q

CY7C1314AV18 − Q

[7:0]

[17:0]

[35:0]

RPS

Input-

Synchronous

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).

When active, a Read operation is initiated. Deasserting will cause the Read port to be

deselected. When deselected, the pending access is allowed to complete and the output

drivers are automatically tri-stated following the next rising edge of the C clock. Each

read access consists of a burst of two sequential transfers.

Input-Clock

Positive Output Clock Input. C is used in conjunction with C to clock out the Read data

from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

Negative Output Clock Input. C is used in conjunction with C to clock out the Read data

from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

to the device and to drive out data through Q

when in single clock mode. All accesses

[x:0]

are initiated on the rising edge of K.

Input-Clock

Echo Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented

to the device and to drive out data through Q when in single clock mode.

[x:0]

CQ is referenced with respect to C. This is a free running clock and is synchronized

to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC timing table.

Echo Clock

Input

CQ is referenced with respect to C. This is a free running clock and is synchronized

to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC timing table.

Output Impedance Matching Input. This input is used to tune the device outputs to the

system data bus impedance. CQ,CQ and Q

output impedance are set to 0.2 x RQ,

[x:0]

where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be

connected directly to V , which enables the minimum impedance mode. This pin cannot

be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off – Active LOW. Connecting this pin to ground will turn off the DLL inside

the device. The timings in the DLL turned off operation will be different from those listed

in this data sheet. More details on this operation can be found in the application note,

“DLL Operation in the QDR-II.”

TDO

TCK

TDI

Output

Input

N/A

TDO for JTAG.

TCK pin for JTAG.

TDI pin for JTAG.

TMS

TMS pin for JTAG.

Not connected to the die. Can be tied to any voltage level.

NC/36M

N/A

Address expansion for 36M. This is not connected to the die and so can be tied to any

voltage level.

NC/72M

N/A

Address expansion for 72M. This is not connected to the die and so can be tied to any

voltage level.

/72M

Input

Address expansion for 72M. This must be tied LOW on the 18M devices.

Address expansion for 144M. This must be tied LOW on the 18M devices.

Address expansion for 288M. This must be tied LOW on the 18M devices.

SS/

/144M

288M

Document #: 38-05497 Rev. *A

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Pin Definitions (continued)

Pin Name

I/O

Pin Description

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs

and Outputs as well as AC measurement points.

REF

Power Supply

Ground

Power supply inputs to the core of the device.

Ground for the device.

Power Supply

Power supply inputs for the outputs of the device.

DDQ

devices without the insertion of wait states in a depth

expanded memory.

Introduction

Functional Overview

Write Operations

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are

synchronous pipelined Burst SRAMs equipped with both a

Read port and a Write port. The Read port is dedicated to

Read operations and the Write port is dedicated to Write

operations. Data flows into the SRAM through the Write port

and out through the Read Port. These devices multiplex the

address inputs in order to minimize the number of address pins

required. By having separate Read and Write ports, the QDR-II

completely eliminates the need to “turn-around” the data bus

and avoids any possible data contention, thereby simplifying

system design. Each access consists of two 8-bit data

transfers in the case of CY7C1310AV18, two 18-bit data

transfers in the case of CY7C1312AV18 and two 36-bit data

transfers in the case of CY7C1314AV18, in one clock cycles.

Write operations are initiated by asserting WPS active at the

rising edge of the Positive Input Clock (K). On the same K

clock rise, the data presented to D

into the lower 18-bit Write Data register provided BWS

is latched and stored

[17:0]

are

[1:0]

both asserted active. On the subsequent rising edge of the

Negative Input Clock (K), the address is latched and the infor-

mation presented to D

is stored into the Write Data

are both asserted active. The 36

[17:0]

[1:0]

bits of data are then written into the memory array at the

specified location. When deselected, the write port will ignore

all inputs after the pending Write operations have been

completed.

Byte Write Operations

Accesses for both ports are initiated on the rising edge of the

positive Input Clock (K). All synchronous input timings are

referenced from the rising edge of the input clocks (K and K)

and all output timings are referenced to the rising edge of

output clocks (C and C or K and K when in single clock mode).

Byte Write operations are supported by the CY7C1312AV18.

A write operation is initiated as described in the Write

Operation section above. The bytes that are written are deter-

mined by BWS and BWS which are sampled with each 18-bit

data word. Asserting the appropriate Byte Write Select input

during the data portion of a write will allow the data being

presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion

of a write will allow the data stored in the device for that byte

to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

All synchronous data inputs (D

) inputs pass through input

[x:0]

registers controlled by the input clocks (K and K). All

synchronous data outputs (Q ) outputs pass through output

[x:0]

registers controlled by the rising edge of the output clocks (C

and C or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS

) inputs pass

[x:0]

through input registers controlled by the rising edge of the

input clocks (K and K).

Single Clock Mode

The CY7C1312AV18 can be used with a single clock that

controls both the input and output registers. In this mode, the

device will recognize only a single pair of input clocks (K and

K) that control both the input and output registers. This

operation is identical to the operation if the device had zero

skew between the K/K and C/C clocks. All timing parameters

remain the same in this mode. To use this mode of operation,

the user must tie C and C HIGH at power on. This function is

a strap option and not alterable during device operation.

CY7C1312AV18 is described in the following sections. The

same basic descriptions apply to CY7C1310AV18 and

CY7C1314AV18.

Read Operations

The CY7C1312AV18 is organized internally as two arrays of

512Kx18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the Positive Input Clock (K).

The address is latched on the rising edge of the K Clock. The

address presented to Address inputs is stored in the Read

address register. Following the next K clock rise the corre-

sponding lowest order 18-bit word of data is driven onto the

Concurrent Transactions

The Read and Write ports on the CY7C1312AV18 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user

can Read or Write to any location, regardless of the trans-

action on the other port. Also, reads and writes can be started

in the same clock cycle. If the ports access the same location

at the same time, the SRAM will deliver the most recent infor-

mation associated with the specified address location. This

includes forwarding data from a Write cycle that was initiated

on the previous K clock rise.

using C as the output timing reference. On the subse-

[17:0]

quent rising edge of C, the next 18-bit data word is driven onto

the Q . The requested data will be valid 0.45 ns from the

[17:0]

rising edge of the output clock (C and C or K and K when in

single clock mode).

Synchronous internal circuitry will automatically tri-state the

outputs following the next rising edge of the Output Clocks

(C/C). This will allow for a seamless transition between

Document #: 38-05497 Rev. *A

Page 6 of 21

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Depth Expansion

Echo Clocks

The CY7C1312AV18 has a Port Select input for each port.

This allows for easy depth expansion. Both Port Selects are

sampled on the rising edge of the Positive Input Clock only (K).

Each port select input can deselect the specified port.

Deselecting a port will not affect the other port. All pending

transactions (Read and Write) will be completed prior to the

device being deselected.

Echo clocks are provided on the QDR-II to simplify data

capture on high-speed systems. Two echo clocks are

generated by the QDR-II. CQ is referenced with respect to C

and CQ is referenced with respect to C. These are

free-running clocks and are synchronized to the output

clock(C/C) of the QDR-II. In the single clock mode, CQ is

generated with respect to K and CQ is generated with respect

to K. The timings for the echo clocks are shown in the AC

Timing table.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ

DLL

pin on the SRAM and V to allow the SRAM to adjust its

output driver impedance. The value of RQ must be 5x the

value of the intended line impedance driven by the SRAM. The

allowable range of RQ to guarantee impedance matching with

a tolerance of ±15% is between 175Ω and 350Ω, with

These chips utilize a Delay Lock Loop (DLL) that is designed

to function between 80 MHz and the specified maximum clock

frequency. The DLL may be disabled by applying ground to the

DOFF pin. The DLL can also be reset by slowing the cycle time

= 1.5V.The output impedance is adjusted every 1024

of input clocks K and K to greater than 30 ns.

DDQ

cycles upon powerup to account for drifts in supply voltage and

temperature.

Application Example^[1]

R = 250ohms

SRAM #4

R = 250ohms

SRAM #1

CQ/CQ#

R W

CQ/CQ#

DATA IN

DATA OUT

Address

RPS#

BUS

MASTER

(CPU

ASIC)

WPS#

BWS#

CLKIN/CLKIN#

Source K

Source K#

Delayed K

Delayed K#

R = 50ohms

Vt = Vddq/2

Truth Table^{[ 2, 3, 4, 5, 6, 7]}

Operation

RPS WPS

D(A + 0)at K(t) ↑

D(A + 1) at K(t) ↑

Write Cycle:

L-H

Load address on the rising edge of K clock; input write data

on K and K rising edges.

Read Cycle:

L-H

Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑

Load address on the rising edge of K clock; wait one and a

half cycle; read data on C and C rising edges.

NOP: No Operation

L-H

D=X

Q=High-Z

D=X

Q=High-Z

Standby: Clock Stopped

Stopped

Previous State

Notes:

1. The above application shows 4 QDRII being used.

^{2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,}↑represents rising edge.

3. Device will power-up deselected and the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

charging symmetrically.

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS , BWS , BWS , and BWS can be altered on different portions of a

write cycle, as long as the set-up and hold requirements are achieved.

Document #: 38-05497 Rev. *A

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

[2, 8]

Write Cycle Descriptions (CY7C1310AV18 and CY7C1312AV18)

BWS BWS

Comments

L-H

–

During the Data portion of a Write sequence :

CY7C1310AV18 − both nibbles (D

) are written into the device,

[7:0]

CY7C1312AV18 − both bytes (D

) are written into the device.

[17:0]

–

L-H

–

L-H During the Data portion of a Write sequence :

CY7C1310AV18 − both nibbles (D

) are written into the device,

) are written into the device.

[7:0]

CY7C1312AV18 − both bytes (D

[17:0]

–

During the Data portion of a Write sequence :

CY7C1310AV18 − only the lower nibble (D

) is written into the device. D

will remain unaltered,

will remain unaltered.

[3:0]

[7:4]

CY7C1312AV18 − only the lower byte (D

) is written into the device. D

[8:0]

[17:9]

L-H During the Data portion of a Write sequence :

CY7C1310AV18 − only the lower nibble (D

) is written into the device. D

will remain unaltered,

will remain unaltered.

[3:0]

[7:4]

CY7C1312AV18 − only the lower byte (D

[8:0]

[17:9]

L-H

–

During the Data portion of a Write sequence :

CY7C1310AV18 − only the upper nibble (D

) is written into the device. D

will remain unaltered,

will remain unaltered.

[7:4]

[3:0]

CY7C1312AV18 − only the upper byte (D

[17:9]

[8:0]

L-H During the Data portion of a Write sequence :

CY7C1310AV18 − only the upper nibble (D

) is written into the device. D

will remain unaltered,

will remain unaltered.

[7:4]

[3:0]

CY7C1312AV18 − only the upper byte (D

[17:9]

[8:0]

L-H

–

No data is written into the devices during this portion of a write operation.

L-H No data is written into the devices during this portion of a write operation.

[2, 8]

Write Cycle Descriptions (CY7C1314AV18)

BWS BWS BWS BWS

Comments

L-H

During the Data portion of a Write sequence, all four bytes (D

the device.

) are written into

[35:0]

L-H

L-H During the Data portion of a Write sequence, all four bytes (D

the device.

During the Data portion of a Write sequence, only the lower byte (D

) is written

[8:0]

into the device. D

will remain unaltered.

[35:9]

L-H During the Data portion of a Write sequence, only the lower byte (D

into the device. D will remain unaltered.

) is written

[35:9]

L-H

During the Data portion of a Write sequence, only the byte (D

) is written into

[17:9]

the device. D

and D

will remain unaltered.

[8:0]

[35:18]

L-H During the Data portion of a Write sequence, only the byte (D

the device. D and D will remain unaltered.

) is written into

[17:9]

[8:0]

[35:18]

L-H

During the Data portion of a Write sequence, only the byte (D

) is written into

[26:18]

[35:27]

the device. D

and D

will remain unaltered.

[17:0]

[35:27]

L-H During the Data portion of a Write sequence, only the byte (D

the device. D and D will remain unaltered.

[17:0]

[35:27]

L-H

During the Data portion of a Write sequence, only the byte (D

the device. D will remain unaltered.

[26:0]

L-H During the Data portion of a Write sequence, only the byte (D

the device. D will remain unaltered.

[26:0]

L-H

No data is written into the device during this portion of a write operation.

L-H No data is written into the device during this portion of a write operation.

Document #: 38-05497 Rev. *A

Page 8 of 21

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CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

(Above which useful life may be impaired.)

Storage Temperature .................................–65°C to +150°C

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V Relative to GND........ –0.5V to +2.9V

Ambient

[14]

DDQ

Range Temperature(T )

DC Voltage Applied to Outputs

in High-Z State .................................... –0.5V to V

+ 0.5V

DDQ

Com’l

0°C to +70°C

1.8 ± 0.1 V

1.4V to V

[12]

DC Input Voltage ............................ –0.5V to V

DDQ

[9,14]

DC Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

1.7

Typ.

Max.

Unit

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

Output LOW Voltage

1.8

1.5

1.9

1.4

DDQ

[10]

[11]

/2 –0.12

/2 – 0.12

– 0.2

/2 + 0.12

V /2 + 0.12

DDQ

= −0.1 mA, Nominal Impedance

DDQ

OH(LOW)

DDQ

= 0.1 mA, Nominal Impedance

0.2

V +0.3

DDQ

OL(LOW)

[12]

Input HIGH Voltage

+ 0.1

REF

[12, 13]

Input LOW Voltage

Clock Input Voltage

Input Load Current

–0.3

– 0.1

+ 0.3

REF

–0.3

−5

DDQ

GND ≤ V ≤ V

µA

DDQ

Output Leakage Current GND ≤ V ≤ V

Output Disabled

−5

DDQ,

[15]

Input Reference Voltage

Typical Value = 0.75V

0.68

0.75

0.95

700

800

450

470

REF

Operating Supply

= Max., I

= 0 mA, 133 MHz

167 MHz

OUT

= 1/t

CYC

f = f

MAX

Automatic

Power-down Current

Max. V , Both Ports

133 MHz

167 MHz

SB1

Deselected, V ≥ V or

= 1/t

≤ V f = f

Inputs Static

MAX CYC,

AC Electrical Characteristics Over the Operating Range

Parameter

Description

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Test Conditions

Min.

Typ.

Max.

Unit

+ 0.2

–

REF

–

– 0.2

REF

Notes:

9. All Voltage referenced to Ground.

10. Output are impedance controlled. Ioh=-(Vddq/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

11. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

12. Overshoot: V^IH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5V (Pulse width less than tCYC/2).

13. This spec is for all inputs except C and C clocks. For C and C clocks, VIL(Max.) = V – 0.2V.

REF

14. Power-up: Assumes a linear ramp from 0v to V^DD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD

15. V (Min.) = 0.68V or 0.46V , whichever is larger, V (Max.) = 0.95V or 0.54V , whichever is smaller.

REF

DDQ

REF

DDQ

Document #: 38-05497 Rev. *A

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PRELIMINARY

[16,17]

Switching Characteristics Over the Operating Range

Cypress Consortium

Parameter Parameter

167 MHz

133 MHz

Description

K Clock and C Clock Cycle Time

Min.

Max.

7.9

–

Min.

7.5

Max. Unit

6.0

2.4

2.7

8.4

–

CYC

KHKH

KHKL

KLKH

KHKH

Input Clock (K/K and C/C) HIGH

Input Clock (K/K and C/C) LOW

3.0

–

3.0

–

K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising

edge to rising edge)

–

3.38

–

KHKH

K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0

2.8

0.0

3.55

KHCH

Set-up Times

Address Set-up to K Clock Rise

0.5

–

0.5

–

Control Set-up to Clock (K, K) Rise (RPS, WPS)

Double Data Rate Control Set-up to Clock (K, K) Rise

SCDDR

(BWS , BWS , BWS , BWS )

D Set-up to Clock (K and K) Rise

[X:0]

0.5

–

0.5

–

Hold Times

Address Hold after Clock (K and K) Rise

0.5

–

0.5

–

Control Hold after Clock (K and K) Rise (RPS, WPS)

Double Data Rate Control Hold after Clock (K and K) Rise

HCDDR

(BWS , BWS , BWS , BWS )

D Hold after Clock (K and K) Rise

[X:0]

0.5

–

0.5

–

Output Times

C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid

–

0.50

–

0.50

–

CHQV

CHQX

Data Output Hold after Output C/C Clock Rise (Active to

Active)

–0.50

DOH

C/C Clock Rise to Echo Clock Valid

Echo Clock Hold after C/C Clock Rise

Echo Clock High to Data Valid

–

–0.50

–

0.50

–

0.50

–

CCQO

CQOH

CQD

CHCQV

CHCQX

CQHQV

CQHQX

CHZ

–0.50

–

0.40

–

0.40

–

Echo Clock High to Data Invalid

–0.40

–

–0.40

–

CQDOH

CHZ

[18,19]

Clock (C and C) Rise to High-Z (Active to High-Z)

0.50

–

0.50

–

[18,19]

Clock (C and C) Rise to Low-Z

–0.50

CLZ

DLL Timing

Clock Phase Jitter

–

0.20

–

0.20

KC Var

KC lock

KC Var

KC lock

DLL Lock Time (K, C)

1024

cycl

K Static to DLL Reset

KC Reset

Thermal Resistance^[20]

Parameter

Description

Test Conditions

165 FBGAPackage

Unit

Thermal Resistance Test conditions follow standard test methods and

(Junction to Ambient) procedures for measuring thermal impedence, per

16.7

°C/W

EIA / JESD51.

Thermal Resistance

(Junction to Case)

2.5

°C/W

Notes:

16. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequncy,

it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.

17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V

= 1.5V, input

DDQ

pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC test loads.

OL OH

18. t

, t

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CHZ CLZ

19. At any given voltage and temperature t

is less than t

and t

less than t

CHZ

CLZ

CHZ

Document #: 38-05497 Rev. *A

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Capacitance^[20]

Parameter

Description

Input Capacitance

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

= 1.8V

Clock Input Capacitance

Output Capacitance

CLK

= 1.5V

DDQ

AC Test Loads and Waveforms

V_REF= 0.75V

0.75V

V_REF

OUTPUT

Device

0.75V

R = 50Ω

OUTPUT

[12]

ALL INPUT PULSES

Z = 50Ω

1.25V

Device

R = 50Ω

0.75V

Under

Test

0.25V

5 pF

Slew Rate = 2V / ns

Under

Test

V_REF= 0.75V

(a)

RQ =

250Ω

RQ =

250Ω

INCLUDING

JIG AND

SCOPE

(b)

Note:

20. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05497 Rev. *A

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Switching Waveforms^[21,22,23]

Read/Write/Deselect Sequence

READ

WRITE

READ

WRITE

READ

WRITE

NOP

WRITE

NOP

CYC

KHKH

RPS

WPS

SA HA

D11

SA HA

D30

D10

D31

D50

D51

D60

Q20

D61

Q21

Q00

Q01

Q40

Q41

CHZ

CLZ

CQD

DOH

KHCH

KHKH

CYC

KHCH

CCQO

CQOH

CCQO

CQOH

DON’T CARE

UNDEFINED

Notes:

21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

22. Output are disabled (High-Z) one clock cycle after a NOP.

23. In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.,

Document #: 38-05497 Rev. *A

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TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant

with IEEE Standard #1149.1-1900. The TAP operates using

JEDEC standard 1.8V I/O logic levels.

When the TAP controller is in the Capture IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board level serial test path.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

Bypass Register

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

be connected to V

through a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

(V ) when the BYPASS instruction is executed.

Test Access Port–Test Clock

Boundary Scan Register

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices.

Test Mode Select

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see Instruction codes). The

output changes on the falling edge of TCK. TDO is connected

to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP Reset

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

A Reset is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

Instruction Register

Three-bit instructions can be serially loaded into the instruction

Document #: 38-05497 Rev. *A

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PRELIMINARY

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required - that is, while data

captured is shifted out, the preloaded data can be shifted in.

SAMPLE Z

BYPASS

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

SAMPLE/PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction.

When the SAMPLE / PRELOAD instructions are loaded into

the instruction register and the TAP controller is in the Cap-

ture-DR state, a snapshot of data on the inputs and output pins

is captured in the boundary scan register.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47.

When this scan cell, called the "extest output bus tristate", is

latched into the preload register during the "Update-DR" state

in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t and t ). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE / PRELOAD instruction. If

this is an issue, it is still possible to capture all other signals

and simply ignore the value of the CK and CK# captured in the

boundary scan register.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the "Shift-DR" state. During "Update-DR", the

value loaded into that shift-register cell will latch into the

preload register. When the EXTEST instruction is entered, this

bit will directly control the output Q-bus pins. Note that this bit

is pre-set HIGH to enable the output when the device is

powered-up, and also when the TAP controller is in the

"Test-Logic-Reset" state.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05497 Rev. *A

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TAP Controller State Diagram^[24]

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

CAPTURE-IR

SHIFT-DR

SHIFT-IR

EXIT1-DR

EXIT1-IR

PAUSE-DR

PAUSE-IR

EXIT2-DR

EXIT2-IR

UPDATE-DR

UPDATE-IR

Note:

24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document #: 38-05497 Rev. *A

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TAP Controller Block Diagram

Bypass Register

Selection

Circuitry

Selection

Circuitry

TDO

TDI

Instruction Register

31 30

Identification Register

106

Boundary Scan Register

TCK

TMS

TAP Controller

[9,12,25]

TAP Electrical Characteristics Over the Operating Range

Parameter

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Test Conditions

= −2.0 mA

Min.

1.4

Max.

Unit

OH1

OH2

OL1

OL2

= −100 µA

= 2.0 mA

= 100 µA

1.6

0.4

0.2

0.65V

+ 0.3

Input LOW Voltage

–0.3

−5

0.35V

Input and OutputLoad Current

GND ≤ V ≤ V

µA

Note:

25. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

Document #: 38-05497 Rev. *A

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[26, 27]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

100

TCYC

MHz

TCK Clock LOW

Set-up Times

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

TAP Timing and Test Conditions^[27]

0.9V

50Ω

ALL INPUT PULSES

0.9V

TDO

1.8V

Z = 50

Ω

C = 20 pF

GND

t_TL

t_TH

(a)

Test Clock

TCK

t_TCYC

t_TMSS

t_TMSH

Test Mode Select

TMS

t_TDIS

t_TDIH

Test Data-In

TDI

Test Data-Out

TDO

t_TDOV

t_TDOX

26. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

27. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.

Document #: 38-05497 Rev. *A

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PRELIMINARY

Identification Register Definitions

CY7C1310AV18

CY7C1312AV18

1M x 18

CY7C1314AV18

512K x 36

000

Instruction Field

2M x 8

Description

Revision Number (31:29)

000

Version number.

Cypress Device ID (28:12) 11010011010000101 11010011010010101 11010011010100101 Defines the type of SRAM.

Cypress JEDEC ID (11:1)

00000110100

Allows unique identification of

SRAM vendor.

ID Register Presence (0)

Indicates the presence of an

ID register.

Scan Register Sizes

Instruction

Bit Size

Bypass

107

Boundary Scan

Instruction Codes

Instruction

EXTEST

Code

Description

Captures the Input/Output ring contents.

000

001

IDCODE

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the Input/Output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Boundary Scan Order

Boundary Scan Order (continued)

Bit #

Bump ID

Bit #

Bump ID

11L

11M

10L

11K

10K

11P

10P

10N

10J

11J

11H

10G

10M

11N

Document #: 38-05497 Rev. *A

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Boundary Scan Order (continued)

Bit #

Bump ID

Bit #

Bump ID

11F

11G

10F

11E

10E

10D

10C

11D

11B

11C

10B

11A

Internal

100

101

102

103

104

105

106

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Ordering Information

Speed

Package

Operating

Range

(MHz)

Ordering Code

Name

Package Type

13 x 15 x 1.4 mm FBGA

167

CY7C1310AV18-167BZC

CY7C1312AV18-167BZC

CY7C1314AV18-167BZC

CY7C1310AV18-133BZC

CY7C1312AV18-133BZC

CY7C1314AV18-133BZC

BB165D

Commercial

133

BB165D

13 x 15 x 1.4 mm FBGA

Commercial

Package Diagram

165 FBGA 13 x 15 x 1.40 mm BB165D

51-85180-**

QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and

Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05497 Rev. *A

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Document History Page

Document Title: CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 18-Mb QDR™-II SRAM 2-Word Burst Architecture

Document Number: 38-05497

Orig. of

REV.

ECN No. Issue Date Change

Description of Change

208405

230396

see ECN

DIM

VBL

New Data Sheet

Upload datasheet to the internet

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