CY62138EV30
MoBL®
®
2-Mbit (256K x 8) MoBL Static RAM
Features
• Very high speed: 45 ns
The CY62138EV30 is a high-performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
— Wide voltage range: 2.20V – 3.60V
• Pin-compatible with CY62138CV30
• Ultra-low standby power
®
This is ideal for providing More Battery Life™ (MoBL ) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra-low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
pins (I/O through I/O ) is then written into the location
0
7
specified on the address pins (A through A ).
0
18
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Offered in Pb-free 36-ball BGA package
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
Data in Drivers
A0
A1
1
2
A
A23
A4
A
A5
3
4
5
256K x 8
ARRAY
A6
A87
A9
A10
A11
6
7
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
OE
Note:
Cypress Semiconductor Corporation
Document #: 38-05577 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 14, 2006
CY62138EV30
MoBL®
DC Input Voltage
......................–0.3V to V
+ 0.3V
Maximum Ratings
CC(MAX)
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Ambient
Temperature
Product
Range
V
CC
Supply Voltage to Ground
CY62138EV30LL
Industrial –40°Cto+85°C 2.2V to
3.6V
Potential........................................ –0.3V to V
+ 0.3V
+ 0.3V
CC(MAX)
......................... –0.3V to V
CC(MAX)
DC Voltage Applied to Outputs
in High-Z State
Electrical Characteristics Over the Operating Range
CY62138EV30-45
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
Output HIGH Voltage
I
= –0.1
V
= 2.20V
2.0
V
OH
OH
CC
mA
I
= –1.0
V
= 2.70V
2.4
V
OH
CC
mA
V
V
V
I
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
I
I
= 0.1 mA V = 2.20V
0.4
0.4
V
V
OL
IH
IL
OL
OL
CC
= 2.1 mA V = 2.70V
CC
V
V
V
V
= 2.2V to 2.7V
= 2.7V to 3.6V
= 2.2V to 2.7V
= 2.7V to 3.6V
1.8
2.2
V
V
+ 0.3V
V
CC
CC
CC
CC
CC
CC
+ 0.3V
0.6
V
–0.3
–0.3
–1
V
0.8
V
Input Leakage
Current
GND < V < V
CC
+1
µA
IX
I
I
I
Output Leakage
Current
GND < V < V
CC
Output Disabled
,
–1
+1
20
µA
OZ
O
V
Operating
f = f
=
V
= V
CCmax
= 0 mA
15
mA
CC
CC
MAX
CC
Supply Current
1/t
I
RC
OUT
CMOS levels
f = 1 MHz
2
1
2.5
7
mA
I
Automatic CE
Power-down
Current — CMOS
Inputs
CE > V – 0.2V, V > V – 0.2V,
µA
SB1
CC
IN
CC
V
< 0.2V), f = f
(Address and
IN
MAX
Data Only), f = 0 (OE, and WE),
= 3.60V
V
CC
I
Automatic CE
Power-down
Current — CMOS
Inputs
CE > V – 0.2V,
1
7
µA
SB2
CC
V
> V – 0.2V or V < 0.2V,
IN
CC IN
f = 0, V = 3.60V
CC
[7]
Capacitance for all packages
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
10
Unit
C
C
Input Capacitance
Output Capacitance
pF
pF
IN
A
V
= V
CC
CC(typ.)
10
OUT
Notes:
4. V
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
= V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a 100 µs ramp time from 0 to V (min.) and 200 µs wait time after V stabilization.
CC
CC
Document #: 38-05577 Rev. *A
Page 3 of 9
CY62138EV30
MoBL®
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
Θ
Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, four-layer
(Junction to Ambient) printed circuit board
72
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
8.86
°C/W
JC
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
OUTPUT
VCC
90%
10%
10%
R2
30 pF
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
Unit
Ω
R1
R2
Ω
R
Ω
TH
TH
V
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min. Typ.
Max. Unit
V
I
V
for Data Retention
1
V
DR
CC
Data Retention Current
V
V
= 1V, CE > V − 0.2V,
0.8
3
µA
CCDR
CC
CC
> V − 0.2V or V < 0.2V
IN
CC
IN
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
R
t
RC
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
1.5V
V
V
CC
VCC (min.)
DR
t
t
R
CDR
CE
Notes:
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full Device AC operation requires linear V ramp from V to V > 100 µs or stable at V > 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05577 Rev. *A
Page 4 of 9
CY62138EV30
MoBL®
Switching Characteristics (Over the Operating Range)
45 ns
Parameter
Read Cycle
Description
Min.
45
Max.
Unit
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
Address to Data Valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
45
AA
Data Hold from Address Change
CE LOW to Data Valid
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
OE LOW to Data Valid
OE LOW to Low Z
5
10
0
OE HIGH to High Z
18
18
45
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-up
CE HIGH to Power-up
PD
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
SCE
AW
HA
0
SA
35
25
0
PWE
SD
Data Set-up to Write End
Data Hold from Write End
HD
WE LOW to High Z
18
HZWE
LZWE
WE HIGH to Low Z
10
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2,
CC(typ)
input pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ)
OL OH
10. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
11. t
, t
, and t
transitions are measured when the output enter a high-impedance state.
HZOE HZCE
HZWE
12. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
Document #: 38-05577 Rev. *A
Page 5 of 9
CY62138EV30
MoBL®
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
ICC
ISB
50%
50%
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATAIN
DATA I/O
VALID
t
HZOE
Notes:
15. Address valid prior to or coincident with CE transition LOW.
16. Data I/O is high impedance if OE = V
.
IH
17. During this period, the I/Os are in output state and input signals should not be applied.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.
Document #: 38-05577 Rev. *A
Page 6 of 9
CY62138EV30
MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
HA
t
SA
t
AW
t
PWE
WE
OE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
t
IN
t
LZWE
HZWE
Truth Table
CE
H
L
WE
OE
X
Inputs/Outputs
Mode
Power
X
H
H
L
High Z
Deselect/Power-down
Read
Standby (I
)
SB
L
Data Out (I/O –I/O )
Active (I
Active (I
Active (I
)
)
)
0
7
CC
CC
CC
L
H
High Z
Data in (I/O –I/O )
Output Disabled
Write
L
X
0
7
Document #: 38-05577 Rev. *A
Page 7 of 9
CY62138EV30
MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62138EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free)
Industrial
Package Diagrams
36-ball VFBGA (6 x 8 x 1 mm) (51-85149)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05(36X)
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
51-85149-*C
C
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05577 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62138EV30
MoBL®
Document History Page
®
Document Title: CY62138EV30 2-Mbit (256K x 8) MoBL Static RAM
Document Number: 38-05577
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
237432
427817
Description of Change
See ECN
See ECN
AJU
New data sheet
*A
NXR
Removed 35 ns Speed Bin
Removed “L” version
Removed 32-pin TSOPII package from product Offering.
Changed ball C3 from DNU to NC.
Removed the redundant footnote on DNU.
Moved Product Portfolio from Page # 3 to Page #2.
Changed I (Max) value from 2 mA to 2.5 mA and I (Typ) value from
CC
CC
1.5 mA to 2 mA at f = 1 MHz
Changed I (Typ) value from 12 mA to 15 mA at f = f =1/t
CC
max
RC
Changed I
2.5 µA to 7 µA.
and I
Typ. values from 0.7 µA to 1 µA and Max. values from
SB1
SB2
Changed V stabilization time in footnote #7 from 100 µs to 200 µs
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
CC
Changed V from 1.5V to 1V on Page# 4.
DR
Changed I
from 1 µA to 3 µA in the Data Retention Characteristics table
CCDR
on Page # 4.
Corected t in Data Retention Characteristics from 100 µs to t ns
R
RC
Changed t
Changed t
Changed t
Changed t
, t
, t
, t
, t
from 6 ns to 10 ns
from 15 ns to 18 ns
OHA LZCE LZWE
HZOE HZCE HZWE
from 3 ns to 5 ns
and t from 40 ns to 35 ns
LZOE
SCE
AW
Changed t from 20 ns to 25 ns
SD
Changed t
from 25 ns to 35 ns
PWE
Updated the Ordering Information table and replaced Package Name
column with Package Diagram.
Document #: 38-05577 Rev. *A
Page 9 of 9
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