STK17T88
32K x 8 AutoStore™ nvSRAM with
Real Time Clock
Features
Description
■ nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watchdog Timer, Clock Alarm, Power
Monitor)
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
Quantum Trap storage element included with each memory cell.
■ Capacitor or Battery Backup for RTC
■ 25, 45 ns Read Access and R/W Cycle Time
■ Unlimited Read/Write Endurance
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
■ Automatic Nonvolatile STORE on Power Loss
■ Nonvolatile STORE Under Hardware or Software Control
■ Automatic RECALL to SRAM on Power Up
■ Unlimited RECALL Cycles
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
■ 200K STORE Cycles
■ 20-Year Nonvolatile Data Retention
■ Single 3V +20%, -10% Power Supply
■ Commercial and Industrial Temperatures
■ 48-pin 300-mil SSOP Package (RoHS-Compliant)
Logic Block Diagram
VCC
VCAP
Quantum Trap
512 X 512
VRTCbat
VRTCcap
POWER
CONTROL
A5
A6
A7
A8
STORE
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
A9
HSB
A11
A12
A13
A14
512 X 512
SOFTWARE
DETECT
A13 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
X1
X2
COLUMN DEC
RTC
INT
A0 A1 A2 A3 A4 A10
A14 – A0
MUX
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52040 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised March 17, 2009
STK17T88
Absolute Maximum Ratings
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to VSS...........–0.5V to (V + 0.5V)
CC
Voltage on DQ0-7 or HSB......................–0.5V to (V + 0.5V)
CC
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature................................... –55°C to 140°C
Storage Temperature.................................... –65°C to 150°C
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15 mA
RF (SSOP-48) Package Thermal Characteristics
θ 6.2 C/W; θ 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]
jc
ja
DC Characteristics
(V = 2.7V-3.6V)
CC
Commercial
Industrial
Symbol
Parameter
Average V Current
Units
Notes
Min
Max
Min
Max
I
65
50
70
55
mA
mA
t
t
= 25 ns
= 45 ns
CC
CC
AVAV
AVAV
1
Dependent on output loading and cycle rate.
Values obtained without output loads.
I
I
Average V Current
during STORE
3
3
mA All Inputs Don’t Care, V = max
CC
CC
CC
2
3
Average current for duration of STORE
cycle (t
)
STORE
Average V Current
10
10
mA W ≥ (V – 0.2V)
CC
CC
= 200ns
CC
at t
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle rate.
Values obtained without output loads.
AVAV
3V, 25°C, Typical
I
I
Average V
Current during
AutoStore™ Cycle
3
3
3
3
mA All Inputs Don’t Care
CC
CAP
4
Average current for duration of STORE cycle
(t
)
STORE
V
Standby Current
mA E ≥ (V -0.2V)
CC
SB
CC
(Standby, Stable
CMOS Levels)
All Others V ≤ 0.2V or ≥ (V -0.2V)
IN CC
Standby current level after nonvolatile cycle
complete
I
I
Input Leakage
Current
±1
±1
µA
V
= max
CC
ILK
V
= V to V
IN
SS
CC
Off-State Output
Leakage Current
±1
±1
µA
V
V = max
CC
OLK
V
= V to V , E or G ≥ V
IN
SS
CC
IH
V
V
Input Logic “1”
Voltage
2.0
V
+ 0.5
2.0
V + 0.5
CC
All Inputs
IH
CC
Input Logic “0”
Voltage
V
–0.5
0.8
V
–0.5
SS
0.8
V
All Inputs
IL
SS
Note:The HSB pin has I
=-10uA for V of 2.4V, this parameter is characterized but not tested.
OH
OUT
Note:The INT is open-drain and does not source or sink high current when interrupt Register bit D3 is below.
Document Number: 001-52040 Rev. *A
Page 3 of 22
STK17T88
DC Characteristics (continued)
(V = 2.7V-3.6V)
CC
Commercial
Industrial
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
V
Output Logic “1”
Voltage
2.4
2.4
V
I
I
=– 2 mA
= 4 mA
OH
OUT
OUT
V
T
Output Logic “0”
Voltage
0.4
70
0.4
85
V
°C
V
OL
Operating Temper-
ature
0
–40
A
V
Operating Voltage
2.7
17
3.6
57
2.7
17
3.6
57
3.0V +20%, -10%
CC
V
Storage Capacitance
µF Between V
pin and V , 5V rated.
CAP
CAP
SS
NV
Nonvolatile STORE
operations
200
200
K
C
DATA
Data Retention
20
20
Years At 55°C
R
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times ...................................................≤ 5ns
Input and Output Timing Reference Levels .................... 1.5V
Capacitance
[2]
Symbol
Parameter
Input Capacitance
Output Capacitance
Max
7
Units
Conditions
C
C
pF
pF
∆V = 0 to 3V
IN
7
∆V = 0 to 3V
OUT
Figure 2. AC Output Loading
Figure 3. AC Output Loading for Tristate Specs (T , t
,
HZ LZ
t
, t
, t
, t
)
WLQZ WHQZ GLQX GHQZ
Note
2. These parameters are guaranteed but not tested.
Document Number: 001-52040 Rev. *A
Page 4 of 22
STK17T88
RTC DC Characteristics
Commercial
Industrial
Symbol
Parameter
Units
Notes
Min
Max
300
3.3
Min
Max
350
3.3
IBAK
RTC Backup Current
—
—
nA
V
From either VRTCcap or VRTCbat
VRTCbat
RTC Battery Pin
Voltage
1.8
1.8
Typical = 3.0 Volts during normal operation
VRTCcap
tOSCS
RTC Capacitor Pin
Voltage
1.2
—
2.7
10
5
1.2
—
2.7
10
5
V
Typical = 2.4 Volts during normal operation
RTCOscillatortimeto
start
sec
sec
At Minimum Temperature from Power up or
Enable
—
—
At 25°C from Power up or Enable
Figure 4. RTC Component Configuration
X1
X2
Recommended Values
Y1
= 32.768 KHz
= 10M Ohm
RF
C1
= 0 (install cap footprint,
but leave unloaded)
C2 = 56 pF ± 10% (do not vary from this value)
Document Number: 001-52040 Rev. *A
Page 5 of 22
STK17T88
SRAM READ Cycles #1 and #2
Symbols
NO.
STK17T88-25
STK17T88-45
Parameter
Units
#1
#2
Alt.
tACS
Min
Max
Min
Max
1
2
3
4
5
6
tELQV
Chip Enable Access Time
Read Cycle Time
25
45
ns
ns
ns
ns
ns
ns
tAVAV
tELEH
tRC
tAA
tOE
tOH
tLZ
25
45
tAVQV
tAVQV
tGLQV
tAXQX
tELQX
Address Access Time
25
12
45
20
Output Enable to Data Valid
Output Hold after Address Change
[4]
tAXQX
3
3
3
3
Address Change or Chip Enable to
Output Active
7
tEHQZ
tHZ
Address Change or Chip Disable to
Output Inactive
10
15
ns
8
9
tGLQX
tOLZ
tOHZ
tPA
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
0
0
ns
ns
ns
ns
tGHQZ
10
25
15
45
10
11
tELICCL
tEHICCH
tPS
Figure 5. SRAM READ Cycle #1: Address Controlled
AVAV
t
ADDRESS
AVQV
t
t
AXQX
DQ (DATA OUT)
DATA VALID
Figure 6. SRAM READ Cycle #2: E and G Controlled
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ± 200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles.
Document Number: 001-52040 Rev. *A
Page 6 of 22
STK17T88
SRAM WRITE Cycles #1 and #2
Symbols
NO.
STK17T88-25
STK17T88-45
Parameter
Units
#1
#2
Alt.
tWC
Min
25
20
20
10
0
Max
Min
45
30
30
15
0
Max
12 tAVAV
tAVAV
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 tWLWH
14 tELWH
15 tDVWH
16 tWHDX
17 tAVWH
18 tAVWL
19 tWHAX
20 tWLQZ
21 tWHQX
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWP
tCW
tDW
tDH
tAW
tAS
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
20
0
30
0
tWR
tWZ
tOW
0
0
10
15
3
3
Figure 7. SRAM WRITE Cycle #1: W Controlled
AVAV
t
ADDRESS
ELWH
t
WHAX
t
E
AVWH
t
AVWL
t
WLWH
t
W
DVWH
WHDX
t
t
DATA IN
DATA IN
DATA VALID
WLQZ
t
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
Figure 8. SRAM WRITE Cycle #2: E Controlled
AVAV
t
ADDRESS
E
AVEL
ELEH
t
t
t
EHAX
AVEH
t
WLEH
t
W
DVEH
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Notes
7. If W is low when E goes low, the outputs remain in the high-impedance state.
8. E or W must be ≥ V during address transitions.
IH
Document Number: 001-52040 Rev. *A
Page 7 of 22
STK17T88
AutoStore/Power Up RECALL
Symbols
NO.
STK17T88
Parameter
Units
Notes
Standard
Alternate
Min
Max
40
22 tHRECALL
Power up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
ms
ms
V
23 tSTORE
24 VSWITCH
25 VCCRISE
tHLHZ
12.5
2.65
150
µS
Figure 9. AutoStore Power Up RECALL
NOTE: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
Notes
9.
t
starts from the time V rises above V
CC SWITCH
HRECALL
10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
11. Industrial Grade Devices require 15 ms Max.
Document Number: 001-52040 Rev. *A
Page 8 of 22
STK17T88
Software-Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed. [12, 13]
Symbols
E Cont Alternate
STK17T88-35
STK17T88-45
NO.
Parameter
Units
Notes
Min
25
0
Max
Min
45
0
Max
26 tAVAV
27 tAVEL
28 tELEH
29 tEHAX
30 tRECALL
tRC
tAS
tCW
STORE / RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
ms
20
1
30
1
Address Hold Time
RECALL Duration
100
100
Notes
12. The software sequence is clocked on the falling edge of E controlled READs
13. The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.
Document Number: 001-52040 Rev. *A
Page 9 of 22
STK17T88
Hardware STORE Cycle
Symbols
NO.
STK17T88
Parameter
Units
Notes
Standard Alternate
Min
1
Max
31 tDELAY
32 tHLHX
tHLQZ
Hardware STORE to SRAM Disabled
Hardware STORE Pulse Width
70
µs
14
15
ns
Figure 11. Hardware STORE Cycle
Soft Sequence Commands
Symbols
NO.
Parameter
STK17T88
Units
Notes
Standard
Min
Max
33 tSS
Soft Sequence Processing Time
70
µs
Figure 12. Soft Sequence Command
Notes
14. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete
15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command
Document Number: 001-52040 Rev. *A
Page 10 of 22
STK17T88
MODE Selection
E
W
G
A
-A
Mode
I/O
Power
Notes
14
0
H
L
L
L
X
H
L
X
L
X
L
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
X
X
Active
H
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
0x0FC0
Nonvolatile Store
Output High Z
ICC2
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Nonvolatile Recall
Notes
17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
18. While there are 15 addresses on the STK17T88, only the lower 13 are used to control software modes.
19. I/O state depends on the state of G. The I/O table shown assumes G low.
Document Number: 001-52040 Rev. *A
Page 11 of 22
STK17T88
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
nvSRAM Operation
The STK17T88 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are the SRAM
memory cell and a nonvolatile QuantumTrap™ cell. The SRAM
memory cell operates like a standard fast static RAM. Data in the
SRAM can be transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture allows all cells to be stored
and recalled in parallel. During the STORE and RECALL opera-
tions SRAM READ and WRITE operations are inhibited. The
STK17T88 supports unlimited read and writes like a typical
SRAM. In addition, it provides unlimited RECALL operations
from the nonvolatile cells and up to 200K STORE operations.
AutoStore operation, a unique feature of Cypress QuanumTrap
technology that is a standard feature on the STK17T88.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 5 shows the proper connection of the storage capacitor
pin is driven to 5V by a charge pump internal to the chip. A pull
up should be placed on W to hold it inactive during power up.
SRAM READ
The STK17T88 performs a READ cycle whenever E and G are
low while W and HSB are high. The address specified on pins
A0-14 determine which of the 32,768 data bytes are accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAVQV (READ cycle #1). If the READ is
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB signal can be monitored by the system to detect
an AutoStore cycle is in progress.
initiated by E and G, the outputs are valid at tELQV or at tGLQV
,
whichever is later (READ cycle #2). The data outputs repeatedly
respond to address changes within the tAVQV access time
without the need for transitions on any control input pins, and
remain valid until another address change or until E or G is
brought high, or W and HSB is brought low.
Hardware STORE (HSB) Operation
The STK17T88 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin is
driven low, the STK17T88 conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
WRITE to the SRAM took place since the last STORE or
RECALL cycle. The HSB pin has a very resistive pull up and is
internally driven low to indicate a busy condition while the
STORE (initiated by any means) is in progress. This pin should
be externally pulled up if it is used to drive other inputs.
Figure 13. AutoStore Mode
VCC
VCAP
VCC
W
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low, the
STK17T88 continues to allow SRAM operations for tDELAY
.
During tDELAY, multiple SRAM READ operations may take place.
If a WRITE is in progress when HSB is pulled low, it is allowed a
time, tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until HSB returns
high.
SRAM WRITE
During any STORE operation, regardless of how it was initiated,
the STK17T88 will continue to drive the HSB pin low, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the STK17T88 will remain disabled until the
HSB pin returns high.
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 are written into memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an E
controlled WRITE.
If HSB is not used, it should be left unconnected.
Hardware Recall (POWER UP)
It is recommended that G be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If G is
left low, internal circuitry turns off the output buffers tWLQZ after
W goes low.
During power up or after any low-power condition
(VCC<VSWITCH), an internal RECALL request will be latched.
When VCC once again exceeds the sense voltage of VSWITCH, a
RECALL cycle is automatically initiated and takes tHRECALL to
complete.
AutoStore Operation
The STK17T88 stores data to nvSRAM using one of three
storage operations. These three operations are Hardware Store
Document Number: 001-52040 Rev. *A
Page 12 of 22
STK17T88
If the STK17T88 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK17T88
software STORE cycle is initiated by executing sequential E
controlled READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data is erased
and then the new data is programmed into the nonvolatile
elements. Once a STORE cycle is initiated, further memory
inputs and outputs are disabled until the cycle is completed.
Noise Considerations
The STK17T88 is a high-speed memory and so must have a
high-frequency bypass capacitor of 0.1 µF connected between
both VCC pins and VSS ground plane with no plane break to chip
VSS. Use leads and traces that are as short as possible. As with
all high-speed CMOS ICs, careful routing of power, ground, and
signals reduce circuit noise.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
Preventing AutoStore
Because of the use of nvSRAM to store critical RTC data, the
AutoStore function can not be disabled on the STK17T88.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
Once the sixth address in the sequence has been entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles be used in
the sequence. After the tSTORE cycle time has been fulfilled, the
SRAM is again activated for READ and WRITE operation.
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, etc. should always program a unique NV
pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or
more random bytes) as part of the final system manufacturing
test to ensure these system routines work consistently.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a man-
ner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ
operations must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state (autostore enabled, etc.). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, etc.).
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is trans-
ferred into the SRAM cells. After the tRECALL cycle time, the
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
■ The OSCEN bit in the Calibration register at 0x7FF8 should be
set to 1 to preserve battery life when the system is in storage
■ The VCAP value specified in this datasheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max VCAP value because the
nvSRAM internal algorithm calculates VCAP charge time based
on this max Vcap value. Customers that want to use a larger
VCAP value to make sure there is extra store charge and store
time should discuss their Vcap size selection with Cypress to
understand any impact on the VCAPvoltage level at the end of
a tRECALL period.
Data Protection
The STK17T88 protects data from corruption during low-voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low-voltage condition is detected when
VCC<VSWITCH
.
Document Number: 001-52040 Rev. *A
Page 13 of 22
STK17T88
A capacitor has the obvious advantage of being more reliable
and not containing hazardous materials. The capacitor is
recharged every time the power is turned on so that the real time
clock continues to have the same backup time over years of
operation
Real Time Clock
The clock registers maintain time up to 9,999 years in
one-second increments. The user can set the time to any
calendar time and the clock automatically keeps track of days of
the week and month, leap years, and century transitions. There
are eight registers dedicated to the clock functions which are
used to set time with a write cycle and to read time during a read
cycle. These registers contain the Time of Day in BCD format.
Bits defined as “0” are currently not used and are reserved for
future use by Cypress.
If you select a battery power source, connect the battery to the
VRTCbat pin and leave the VRTCcap pin unconnected. A 3V lithium
is recommended for this application. The battery capacity should
be chosen for the total anticipated cumulative down-time
required over the life of the system.
The real time clock is designed with a diode internally connected
to the VRTCbat pin. This prevents the battery from ever being
charged by the circuit.
Reading the Clock
The user should halt internal updates to the real time clock
registers before reading clock data to prevent reading of data in
transition. Stopping the internal register updates does not affect
clock accuracy.
Stopping and Starting the RTC Oscillator
The OSCEN bit in Calibration register at 0x7FF8 enables RTC
oscillator operation. This bit is nonvolatile and shipped to
customers in the “enabled” state (set to 0). OSCEN should be set
to a 1 to preserve battery life while the system is in storage. This
turns off the oscillator circuit extending the battery life. If the
OSCEN bit goes from disabled to enabled, it typically takes 5
seconds (10 seconds max) for the oscillator to start.
Write a “1” to the read bit “R” (in the Flags register at 0x7FF0) to
capture the current time in holding registers. Clock updates do
not restart until a “0” is written to the read bit. The RTC registers
can now be read while the internal clock continues to run.
Within 20ms after a “0” is written to the read bit, all real time clock
registers are simultaneously updated.
The STK17T88 has the ability to detect oscillator failure due to
loss of backup power. The failure is recorded by the OSCF
(Oscillator Failed bit) of the Flags register (at address 0x7FF0).
When the device is powered on (VCC goes above VSWITCH) the
OSCEN bit is checked for “enabled” status. If the OSCEN bit is
enabled and the oscillator is not active within 5 ms, the OSCF bit
is set. The user should check for this condition and then write a
0 to clear the flag. When the OSCF flag bit, the real time clock
registers are reset to the “Base Time” (see the section Setting
registers.
Setting the Clock
Set the write bit “W” (in the Flags register at 0x7FF0) to a “1”
enable the time to be set. The correct day, date and time can then
be written into the real time clock registers in 24-hour BCD
format. The time written is referred to as the “Base Time.” This
value is stored in nonvolatile registers and used in calculation of
the current time. Reset the write bit to “0” to transfer the time to
the actual clock counters, The clock starts counting at the new
base time.
The value of OSCF should be reset to 0 when the real time clock
registers are written for the first time. This initializes the state of
this bit since it may have become set when the system was first
powered on.
Backup Power
The RTC is intended to keep time even when system power is
lost. When primary power, VCC, drops below VSWITCH, the real
time clock switches to the backup power supply connected to
either the VRTCcap or VRTCbat pin.
To reset OSCF, set the write bit “W” (in the Flags register at
0x7FF0) to a “1” to enable writes to the Flags register. Write a “0”
to the OSCF bit and then reset the write bit to “0” to disable
writes.
The clock oscillator uses a maximum of 300 nanoamps at 2 volts
to maximize the backup time available from the backup source.
You can power the real time clock with either a capacitor or a
battery. Factors to be considered when choosing a backup
power source include the expected duration of power outages
and the cost and reliability trade-off of using a battery versus a
capacitor.
Calibrating The Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 KHz. Clock accuracy depends on the quality
of the crystal specified (usually 35 ppm at 25 C). This error could
equate to 1.53 minutes gain or loss per month. The STK17T88
employs a calibration circuit that can improve the accuracy to
+1/-2 ppm at 25 C. The calibration circuit adds or subtracts
counts from the oscillator divider circuit.
If you select a capacitor power source, connect the capacitor to
the VRTCcap pin and leave the VRTCbat pin unconnected.
Capacitor backup time values based on maximum current specs
are shown below. Nominal times are approximately 3 times
longer.
The number of time pulses added or subtracted depends upon
the value loaded into the five calibration bits found in Calibration
register (at 0x7FF8). Adding counts speeds the clock up;
subtracting counts slows the clock down. The Calibration bits
occupy the five lower order bits of the register. These bits can be
set to represent any value between 0 and 31 in binary form. Bit
D5 is a Sign bit, where a “1” indicates positive calibration and a
“0” indicates negative calibration. Calibration occurs during a 64
minute period. The first 62 minutes in the cycle may, once per
Capacitor Value
0.1 F
Backup Time
72 hours
14 days
0.47 F
1.0 F
30 days
Document Number: 001-52040 Rev. *A
Page 14 of 22
STK17T88
minute, have one second either shortened by 128 or lengthened
by 256 oscillator cycles.
The watchdog timer is a free-running-down counter that uses the
32Hz clock (31.25 ms) derived from the crystal oscillator. The
watchdog timer function does not operate unless the oscillator is
running.
If a binary “1” is loaded into the register, only the first 2 minutes
of the 64 minute cycle is modified; if a binary 6 is loaded, the first
12 are affected, and so on. Therefore each calibration step has
the effect of adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is +4.068 or
-2.034 ppm of adjustment per calibration step in the Calibration
register.
The watchdog counter is loaded with a starting value from the
load register and then counts down to zero, setting the watchdog
flag (WDF) and generating an interrupt if the watchdog interrupt
is enabled. The watchdog flag bit is reset when the Flags register
is read. The operating software would normally reload the
counter by setting the watchdog strobe bit (WDS) to 1 within the
timing interval programmed into the load register.
The calibration register value is determined during system test
by setting the CAL bit in the Flags register (at 0x7FF0) to 1. This
causes the INT pin to toggle at a nominal 512 Hz. This frequency
can be measured with a frequency counter. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
would indicate a +20 ppm error, requiring a -10 (001010) to be
loaded into the Calibration register. Note that setting or changing
the calibration register does not affect the frequency test output
frequency.
To use the watchdog timer to reset the processor on timeout, the
INT is tied to processor master reset and Interrupt register is
programmed to 24h to enable interrupts to pulse the reset pin on
timeout.
To load the watchdog timer, set a new value into the load register
by writing a “0” to the watchdog write bit (WDW) of the watchdog
register (at 0x7FF7). Then load a new value into the load register.
Once the new value is loaded, the watchdog write bit is then set
to 1 to disable watchdog writes. The watchdog strobe bit (WDS)
is set to 1 to load this value into the watchdog timer. Note: Setting
the load register to zero disables the watchdog timer function.
To set or clear CAL, set the write bit “W” (in the Flags register at
0x7FF0) to a “1” to enable writes to the Flags register. Write a
value to CAL and then reset the write bit to “0” to disable writes.
The default Calibration register value from the factory is 00h. The
user calibration value loaded is retained during a power loss.
The system software should initialize the watchdog load register
on power up to the desired value since the register is not nonvol-
atile.
Alarm
Power Monitor
The alarm function compares a user-programmed alarm
time/date (stored in registers 0x7FF1-5) with the real time clock
time-of-day/date values. When a match occurs, the alarm flag
(AF) is set and an interrupt is generated if the alarm interrupt is
enabled. The alarm flag is automatically reset when the Flags
register is read.
The STK17T88 provides a power monitor function. The power
monitor is based on an internal band-gap reference circuit that
compares the VCC voltage to VSWITCH
.
When the power supply drops below VSWITCH, the real time clock
circuit is switched to the backup supply (battery or capacitor).
Each of the alarm registers has a match bit as its MSB. Setting
the match bit to a 1 disables this alarm register from the alarm
comparison. When the match bit is 0, the alarm register is
compared with the equivalent real time clock register. Using the
match bits, an alarm can occur as specifically as one particular
second on one day of the month or as frequently as once per
minute.
When operating from the backup source, no data may be read
or written and the clock functions are not available to the user.
The clock continues to operate in the background. Updated clock
data is available to the user tHRECALL delay after VCC has been
restored to the device.
When the power is lost, the PF flag in the Flags register is set to
indicate the power failure and an interrupt is generated if the
power fail interrupt is enabled (interrupt register=20h). The INT
line would normally be tied to the processor master reset input
to perform power-off reset.
Note The product requires the match bit for seconds (0x7FF2,
bit D7) be set to 0 for proper operation of the Alarm Flag and
Interrupt.
The alarm value should be initialized on power up by software
since the alarm registers are not nonvolatile.
Interrupts
To set or clear the Alarm registers, set the write bit “W” (in the
Flags register at 0x7FF0) to a “1” to enable writes to the Alarm
registers. Write an alarmvalue to the alarm registers and then
reset the write bit to “0” to disable writes.
The STK17T88 has a Flags register, Interrupt register, and
interrupt logic that can interrupt the microcontroller or general a
power up master reset signal. There are three potential interrupt
sources: the watchdog timer, the power monitor, and the clock
alarm. Each can be individually enabled to drive the INT pin by
setting the appropriate bit in the Interrupt register. In addition,
each has an associated flag bit in the Flags register that the host
processor can read to determine the interrupt source. Two bits in
the interrupt register determine the operation of the INT pin
driver.
Watchdog Timer
The watchdog timer is designed to interrupt or reset the
processor should its program get hung in a loop and not respond
in a timely manner. The software must reload the watchdog timer
before it counts down to zero to prevent this interrupt or reset.
Document Number: 001-52040 Rev. *A
Page 15 of 22
STK17T88
Figure 15 is a functional diagram of the interrupt logic.
High/Low (H/L). When set to a 1, the INT pin is active high and
the driver mode is push-pull. The INT pin can drive high only
when VCC>VSWITCH. When set to a 0, the INT pin is active low
and the drive mode is open-drain. The active low (open drain)
output is maintained even when power is lost.
Figure 15. Interrupt Block Diagram
WDF
Watchdog
Timer
WIE
Pulse/Level (P/L). When set to a 1, the INT pin is driven for
approximately 200 ms when the interrupt occurs. The pulse is
reset when the Flags register is read. When P/L is set to a 0, the
INT pin is driven high or low (determined by H/L) until the Flags
register is read.
VCC
PF
P/L
Power
Pin
Driver
INT
Monitor
PFE
H/L
VINT
VSS
AF
The Interrupt register is loaded with the default value 00h at the
factory. The user should configure the Interrupt register to the
value desired for their desired mode of operation. Once
configured, the value is retained during power failures.
Clock
Alarm
AIE
Interrupt Register
Flags Register
Watchdog Interrupt Enable (WIE). When set to 1, the watchdog
timer drives the INT pin when a watchdog time-out occurs. When
WIE is set to 0, the watchdog time-out only sets the WDF flag bit.
The Flags register has three flag bits: WDF, AF, and PF. These
flags are set by the watchdog time-out, alarm match, or power
fail monitor respectively. The processor can either poll this
register or enable the interrupts to be informed when a flag is set.
The flags are automatically reset once the register is read.
Alarm Interrupt Enable (AIE). When set to 1, the INT pin is driven
when an alarm match occurs. When set to 0, the alarm match
only sets the AF flag bit.
The Flags register is automatically loaded with the value 00h on
power up (with the exception of the OSCF bit).
Power Fail Interrupt Enable (PFE). When set to 1, the INT pin is
driven by a power fail signal from the power monitor. When set
to 0, only the PF flag is set.
Document Number: 001-52040 Rev. *A
Page 16 of 22
STK17T88
RTC Register Map
BCD Format Data
Register
D7
Function / Range
D6
D5
D4
D3
D2
D1
D0
0x7FFF
0x7FFE
10s Years
0
Years
Months
Years: 00-99
Months: 01-12
0
0
10s
Months
0x7FFD
0x7FFC
0x7FFB
0x7FFA
0x7FF9
0x7FF8
0
0
0
0
0
0
0
0
10s Day of Month
Day of Month
Day of Week
Hours
Minutes
Seconds
Day of Month: 01-31
Day of week: 01-07
Hours: 00-23
Minutes: 00-59
Seconds: 00-59
Calibration values*
0
0
0
10s Hours
10s Minutes
10s Seconds
OSCEN
[0]
0
Cal
Sign
Calibration [00000]
0x7FF7
0x7FF6
WDS
WDW
WDT
Watchdog*
Interrupts*
WIE[0]
AIE[0] PFE[0]
0
H/L [1]
P/L [0]
0
0
0x7FF5
0x7FF4
0x7FF3
0x7FF2
0x7FF1
0x7FF0
M
M
M
M
0
0
10s Alarm Date
10s Alarm Hours
Alarm Day
Alarm, Day of Month: 01-31
Alarm, hours: 00-23
Alarm, minutes: 00-59
Alarm, seconds: 00-59
Centuries: 00-99
Alarm Hours
Alarm Minutes
Alarm Seconds
Centuries
10 Alarm Minutes
10 Alarm Seconds
10s Centuries
AF PF
WDF
OSCF
0
CAL[0]
W[0]
R[0]
Flags*
*A binary value, not a BCD value.
0 - Not implemented, reserved for future use.
Default Settings of nonvolatile Calibration and Interrupt registers from factory
Calibration Register=00h
Interrupt Register=00h
The User should configure to the desired value at startup or during operation and the value is then retained during a power failure.
[ ] designates values shipped from the factory. See Stopping and Starting the RTC Oscillator on page 14.
Document Number: 001-52040 Rev. *A
Page 17 of 22
STK17T88
Register Map Detail
Real Time Clock – Years
D4 D3
0x7FFF
D7
D6
D5
D2
D1
D0
10s Years
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble
contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99.
Real Time Clock – Months
0x7FFE
0x7FFD
0x7FFC
0x7FFB
D7
0
D6
0
D5
0
D4
D3
D2
D1
Months
D0
10s
Month
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12.
Real Time Clock – Date
D7
0
D6
0
D5
D4
D3
D2
D1
D0
10s Day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from
0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31.
Leap years are automatically adjusted for.
Real Time Clock – Day
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
0
0
Day of week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that
counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not
integrated with the date.
Real Time Clock – Hours
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates
from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the
register is 0-23.
Real Time Clock – Minutes
0x7FFA
0x7FF9
D7
0
D6
D5
D4
D3
D2
D1
Minutes
D0
10s Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59.
Real Time Clock – Seconds
D7
0
D6
D5
D4
D3
D2
D1
Seconds
D0
10s Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59.
Calibration
0x7FF8
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
0
Calibratio
n Sign
Calibration
OSCEN
Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator is enabled.
Disabling the oscillator saves battery/capacitor power during storage.
Calibration Sign
Calibration
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
These five bits control the calibration of the clock.
Watchdog Timer
0x7FF7
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automat-
ically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.
Document Number: 001-52040 Rev. *A
Page 18 of 22
STK17T88
Register Map Detail (continued)
WDW
Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0).
This allows the user to strobe the watchdog without disturbing the time-out value. Setting this bit to 0 allows
bits 5-0 to be written.
WDT
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It
represents a multiplier of the 32 Hz count (31.25 ms). The range or time-out values is 31.25 ms (a setting
of 1) to 2 seconds (setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits
can be written only if the WDW bit was cleared to 0 on a previous cycle.
Interrupt
0x7FF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
ABE
H/L
P/L
0
0
WIE
AIE
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the
INT pin and sets the WDF flag. When set to 0, the watchdog time-out only sets the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and sets the AF flag. When set
to 0, the alarm match only sets the AF flag.
PFIE
Power-Fail Enable. When set to 1, a power failure drives the INT pin and sets the PF flag. When set to 0,
a power failure only sets the PF flag.
0
Reserved for Future Use
H/L
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain,
active low.
P/L
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for
approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the
Flags register is read.
Alarm – Day
0x7FF5
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Date
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes
the match circuit to ignore the date value.
Alarm – Hours
0x7FF4
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Hours
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the hours value.
Alarm – Minutes
0x7FF3
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Minutes
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the minutes value.
Alarm – Seconds
0x7FF2
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Seconds
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the seconds value.
0x7FF1
Real Time Clock – Centuries
10s Centuries
Centuries
Contains the BCD value of Centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper centuries digit and operates from 0 to 9. The range for the register is 0-99
centuries.
Document Number: 001-52040 Rev. *A
Page 19 of 22
STK17T88
Register Map Detail (continued)
Flags
0x7FF0
D7
D6
AF
D5
PF
D4
OSCF
D3
0
D2
CAL
D1
W
D0
R
WDF
WDF
AF
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without
being reset by the user. It is cleared to 0 when the Flags register is read or on power up
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm
registers with the match bits = 0. It is cleared when the Flags register is read or on power up
PF
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold VSWITCH. It
is cleared to 0 when the Flags register is read or on power up.
OSCF
Oscillator Fail Flag. Set to 1 on power up only if the oscillator is enabled and not running in the first 5ms
of operation. This indicates that the RTC backup power failed and the clock value is no longer valid. The
user must reset this bit to 0 to clear this condition.
CAL
W
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0, the INT
pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
Write Time. Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to the
RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit
to 0 disables writes to the registers and causes the contents of the real time clock registers to be transferred
to the timekeeping counters if the time has changed (a new base time is loaded). The bit defaults to 0 on
power up.
R
Read Time. Setting the R bit to 1 captures the current time in holding registers so that clock updates are
not during the reading process. Set the R bit to 0 to enable the holding register to resume clock updates.
The bit defaults to 0 on power up.
Commercial and Industrial Ordering Information
STK17T88 - R F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Temperature Range:
C - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Speed:
25 - 25 ns
45 - 45 ns
Lead Finish
F = 100% Sn (Matte Tin) RoHS Compliant
Package:
R = Plastic 48-pin 330 mil SSOP
Ordering Codes
Ordering Code
STK17T88-RF25
Description
Access Times (ns)
Temperature
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
25
45
25
45
25
45
25
45
Commercial
STK17T88-RF45
Commercial
Commercial
Commercial
Industrial
STK17T88-RF25TR
STK17T88-RF45TR
STK17T88-RF25I
STK17T88-RF45I
STK17T88-RF25ITR
STK17T88-RF45ITR
Industrial
Industrial
Industrial
Document Number: 001-52040 Rev. *A
Page 20 of 22
STK17T88
Document History Page
Document Title: STK17T88 32K x 8 AutoStore™ nvSRAM with Real-Time Clock
Document Number: 001- 52040
Orig. of
Rev
ECN No.
Submission Date
Description of change
Change
GVCH/PYRS
GVCH
**
2668660
2675319
03/04/2009
03/17/2009
New data sheet
*A
Corrected typo on page 1 in ‘Description’
section: changed 256KB to 256Kb.
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application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52040 Rev. *A
Revised March 17, 2009
Page 22 of 22
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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