Analog Devices ADuC812 User Manual
®
MicroConverter , Multichannel  
a
12-Bit ADC with Embedded FLASH MCU  
ADuC812  
FEATURES  
APPLICATIONS  
ANALOG I/O  
Intelligent Sensors Calibration and Conditioning  
Battery Powered Systems (Portable PCs, Instruments,  
Monitors)  
8-Channel, High Accuracy 12-Bit ADC  
On-Chip, 100 ppm/؇C Voltage Reference  
High-Speed 200 kSPS  
Transient Capture Systems  
DMA Controller for High-Speed ADC-to-RAM Capture  
Two 12-Bit Voltage Output DACs  
On-Chip Temperature Sensor Function  
MEMORY  
8K Bytes On-Chip Flash/EE Program Memory  
640 Bytes On-Chip Flash/EE Data Memory  
256 Bytes On-Chip Data RAM  
16M Bytes External Data Address Space  
64K Bytes External Program Address Space  
8051-COMPATIBLE CORE  
12 MHz Nominal Operation (16 MHz Max)  
Three 16-Bit Timer/Counters  
High Current Drive Capability—Port 3  
Nine Interrupt Sources, Two Priority Levels  
POWER  
Specified for 3 V and 5 V Operation  
Normal, Idle, and Power-Down Modes  
ON-CHIP PERIPHERALS  
DAS and Communications Systems  
Control Loop Monitors (Optical Networks/Base Stations)  
GENERAL DESCRIPTION  
The ADuC812 is a fully integrated 12-bit data acquisition system  
incorporating a high performance self calibrating multichannel  
ADC, dual DAC and programmable 8-bit MCU (8051 instruc-  
tion set compatible) on a single chip.  
The programmable 8051-compatible core is supported by 8K  
bytes Flash/EE program memory, 640 bytes Flash/EE data  
memory and 256 bytes data SRAM on-chip.  
Additional MCU support functions include Watchdog Timer,  
Power Supply Monitor and ADC DMA functions. 32 Pro-  
grammable I/O lines, I2C-compatible, SPI and Standard UART  
Serial Port I/O are provided for multiprocessor interfaces and  
I/O expansion.  
Normal, idle, and power-down operating modes for both the  
MCU core and analog converters allow for flexible power man-  
agement schemes suited to low power applications. The part is  
specified for 3 V and 5 V operation over the industrial tem-  
perature range and is available in a 52-lead, plastic quad  
flatpack package.  
UART Serial I/O  
2-Wire (I2C®-Compatible) and SPI® Serial I/O  
Watchdog Timer  
Power Supply Monitor  
FUNCTIONAL BLOCK DIAGRAM  
P0.0–P0.7  
P1.0–P1.7  
P2.0–P2.7  
P3.0–P3.7  
DAC0  
BUF  
BUF  
DAC0  
ADC  
CONTROL  
AND  
CALIBRATION  
LOGIC  
12-BIT  
AIN0 (P1.0)–AIN7 (P1.7)  
DAC  
SUCCESSIVE  
AIN  
MUX  
T/H  
CONTROL  
APPROXIMATION  
ADC  
DAC1  
DAC1  
T0 (P3.4)  
T1 (P3.5)  
MICROCONTROLLER  
T2 (P1.0)  
T2EX (P1.1)  
8051 BASED  
MICROCONTROLLER CORE  
POWER SUPPLY  
MONITOR  
3 ꢀ 16-BIT  
TIMER/COUNTERS  
2.5V  
REF  
TEMP  
SENSOR  
WATCHDOG  
TIMER  
2-WIRE  
SPI  
8K ꢀ 8 PROGRAM  
INT0 (P3.2)  
INT1 (P3.3)  
ALE  
SERIAL I/O  
FLASH EEPROM  
640 ꢀ 8 USER  
FLASH EEPROM  
UART  
OSC  
MUX  
V
BUF  
REF  
PSEN  
256 ꢀ 8 USER  
EA  
RAM  
ADuC812  
C
REF  
RESET  
XTAL1 XTAL2 RxD TxD  
(P3.0) (P3.1)  
SCLOCK  
MISO  
(P3.3)  
AV  
AGND DV  
DGND  
MOSI/  
SDATA  
DD  
DD  
MicroConverter is a registered trademark of Analog Devices, Inc.  
I2C is a registered trademark of Philips Corporation.  
SPI is a registered trademark of Motorola Inc.  
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2001  
ADuC812  
SPECIFICATIONS1, 2  
(AVDD = DVDD = 3.0 V or 5.0 V ؎10%, REFIN/REFOUT = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz,  
fSAMPLE = 200 kHz, DAC VOUT Load to AGND; RL = 2 k⍀, CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.)  
ADuC812BS  
Parameter  
VDD = 5 V  
VDD = 3 V  
Unit  
Test Conditions/Comments  
ADC CHANNEL SPECIFICATIONS  
DC ACCURACY3, 4  
Resolution  
Integral Nonlinearity  
12  
1/2  
1.5  
1.5  
1
12  
1/2  
Bits  
LSB typ  
LSB max  
LSB typ  
LSB typ  
fSAMPLE = 100 kHz  
fSAMPLE = 100 kHz  
fSAMPLE = 200 kHz  
fSAMPLE = 100 kHz. Guaranteed No  
Missing Codes at 5 V  
1.5  
1
Differential Nonlinearity  
CALIBRATED ENDPOINT ERRORS5, 6  
Offset Error  
5
1
LSB max  
LSB typ  
LSB typ  
LSB max  
LSB typ  
LSB typ  
2
1
Offset Error Match  
Gain Error  
1
6
1
1.5  
2
1.5  
Gain Error Match  
USER SYSTEM CALIBRATION7  
Offset Calibration Range  
Gain Calibration Range  
5
2.5  
5
2.5  
% of VREF typ  
% of VREF typ  
DYNAMIC PERFORMANCE  
fIN = 10 kHz Sine Wave  
f
SAMPLE = 100 kHz  
Signal-to-Noise Ratio (SNR)8  
Total Harmonic Distortion (THD)  
Peak Harmonic or Spurious Noise  
70  
–78  
–78  
70  
–78  
–78  
dB typ  
dB typ  
dB typ  
ANALOG INPUT  
Input Voltage Ranges  
Leakage Current  
0 to VREF  
10  
1
0 to VREF  
Volts  
µA max  
µA typ  
pF max  
1
20  
Input Capacitance9  
20  
TEMPERATURE SENSOR10  
Voltage Output at 25°C  
Voltage TC  
600  
–3.0  
600  
–3.0  
mV typ  
mV/°C typ  
Can vary significantly (> 20%)  
from device to device  
DAC CHANNEL SPECIFICATIONS  
DC ACCURACY11  
Resolution  
12  
3
12  
3
1
Bits  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
LSB typ  
LSB typ  
mV max  
mV typ  
mV max  
mV typ  
% typ  
0.5  
60  
25  
30  
10  
0.5  
Guaranteed 12-Bit Monotonic  
% of Full-Scale on DAC1  
25  
Full-Scale Error  
10  
0.5  
Full-Scale Mismatch  
ANALOG OUTPUTS  
Voltage Range_0  
Voltage Range_1  
Resistive Load  
Capacitive Load  
Output Impedance  
ISINK  
0 to VREF  
0 to VDD  
10  
100  
0.5  
0 to VREF  
0 to VDD  
10  
100  
0.5  
V typ  
V typ  
kΩtyp  
pF typ  
Ωtyp  
50  
50  
µA typ  
–3–  
REV. B  
ADuC812–SPECIFICATIONS1, 2  
(continued)  
ADuC812BS  
Parameter  
VDD = 5 V  
VDD = 3 V  
Unit  
Test Conditions/Comments  
DAC AC CHARACTERISTICS  
Voltage Output Settling Time  
15  
10  
15  
10  
µs typ  
Full-Scale Settling Time to  
Within 1/2 LSB of Final Value  
1 LSB Change at Major Carry  
Digital-to-Analog Glitch Energy  
nV sec typ  
REFERENCE INPUT/OUTPUT  
REFIN Input Voltage Range9  
Input Impedance  
2.3/VDD  
150  
2.5 2.5%  
2.3/VDD  
150  
V min/max  
kΩ typ  
V min/max  
V typ  
REFOUT Output Voltage  
Initial Tolerance @ 25°C  
2.5  
2.5  
REFOUT Tempco  
100  
100  
ppm/°C typ  
FLASH/EE MEMORY PERFORMANCE  
CHARACTERISTICS12, 13  
Endurance  
10,000  
50,000  
10  
Cycles min  
Cycles typ  
Years min  
50,000  
64  
Data Retention  
WATCHDOG TIMER  
CHARACTERISTICS  
Oscillator Frequency  
64  
kHz typ  
POWER SUPPLY MONITOR  
CHARACTERISTICS  
Power Supply Trip Point Accuracy  
2.5  
% of Selected  
Nominal Trip  
Point Voltage  
max  
1.0  
1.0  
% of Selected  
Nominal Trip  
Point Voltage  
typ  
DIGITAL INPUTS  
Input High Voltage (VINH  
XTAL1 Input High Voltage (VINH) Only  
Input Low Voltage (VINL  
)
2.4  
4
0.8  
10  
1
V min  
V min  
V max  
µA max  
µA typ  
)
Input Leakage Current (Port 0, EA)  
VIN = 0 V or VDD  
VIN = 0 V or VDD  
1
Logic 1 Input Current  
(All Digital Inputs)  
10  
1
–80  
µA max  
µA typ  
µA max  
µA typ  
µA max  
µA typ  
pF typ  
VIN = VDD  
VIN = VDD  
1
Logic 0 Input Current (Port 1, 2, 3)  
–40  
–40  
VIL = 450 mV  
Logic 1-0 Transition Current (Port 1, 2, 3) –700  
–400  
Input Capacitance  
V
V
IL = 2 V  
IL = 2 V  
–400  
10  
10  
–4–  
REV. B  
ADuC812  
ADuC812BS  
Parameter  
VDD = 5 V  
VDD = 3 V  
Unit  
Test Conditions/Comments  
DIGITAL OUTPUTS  
Output High Voltage (VOH  
)
2.4  
4.0  
V min  
V typ  
VDD = 4.5 V to 5.5 V  
ISOURCE = 80 µA  
VDD = 2.7 V to 3.3 V  
2.6  
ISOURCE = 20 µA  
Output Low Voltage (VOL  
)
ALE, PSEN, Ports 0 and 2  
0.4  
0.2  
0.4  
0.2  
V max  
V typ  
V max  
V typ  
ISINK = 1.6 mA  
ISINK = 1.6 mA  
ISINK = 8 mA  
0.2  
0.2  
Port 3  
I
SINK = 8 mA  
Floating State Leakage Current  
Floating State Output Capacitance  
10  
5
10  
µA max  
µA typ  
pF typ  
5
10  
POWER REQUIREMENTS14, 15, 16  
IDD Normal Mode17  
43  
32  
26  
8
25  
18  
15  
7
mA max  
mA typ  
mA typ  
mA typ  
mA max  
mA typ  
mA typ  
mA typ  
µA max  
µA typ  
MCLKIN = 16 MHz  
MCLKIN = 16 MHz  
MCLKIN = 12 MHz  
MCLKIN = 1 MHz  
MCLKIN = 16 MHz  
MCLKIN = 16 MHz  
MCLKIN = 12 MHz  
MCLKIN = 1 MHz  
16  
12  
3
IDD Idle Mode  
17  
6
2
50  
5
IDD Power-Down Mode18  
50  
5
NOTES  
1Specifications apply after calibration.  
2Temperature range –40°C to +85°C.  
3Linearity is guaranteed during normal MicroConverter Core operation.  
4Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.  
5Measured in production at VDD = 5 V after Software Calibration Routine at 25°C only.  
6User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.  
7The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.  
8SNR calculation includes distortion and noise components.  
9Specification is not production tested, but is supported by characterization data at initial product release.  
10The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result.  
11DAC linearity is calculated using:  
reduced code range of 48 to 4095, 0 to VREF range  
reduced code range of 48 to 3995, 0 to VDD range  
DAC output load = 10 kΩ and 50 pF.  
12Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance).  
13Endurance Cycling is evaluated under the following conditions:  
Mode  
= Byte Programming, Page Erase Cycling  
Cycle Pattern  
Erase Time  
Program Time  
= 00Hex to FFHex  
= 20 ms  
= 100 µs  
14  
I
at other MCLKIN frequencies is typically given by:  
DD  
Normal Mode (VDD = 5 V):  
Normal Mode (VDD = 3 V):  
Idle Mode (VDD = 5 V):  
Idle Mode (VDD = 3 V):  
IDD = (1.6 nAs × MCLKIN) + 6 mA  
IDD = (0.8 nAs × MCLKIN) + 3 mA  
IDD = (0.75 nAs × MCLKIN) + 6 mA  
IDD = (0.25 nAs × MCLKIN) + 3 mA  
Where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA.  
15  
16  
I
I
Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.  
is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.  
DD  
DD  
17Analog IDD = 2 mA (typ) in normal operation (internal VREF, ADC and DAC peripherals powered on).  
18EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.  
Typical specifications are not production tested, but are supported by characterization data at initial product release.  
Specifications subject to change without notice.  
Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information.  
–5–  
REV. B  
ADuC812  
ABSOLUTE MAXIMUM RATINGS*  
(TA = 25°C unless otherwise noted)  
PIN CONFIGURATION  
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V  
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V  
DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V  
Digital Input Voltage to DGND . . . . . –0.3 V, DVDD + 0.3 V  
Digital Output Voltage to DGND . . . . –0.3 V, DVDD + 0.3 V  
52 51 50 49 48 47 46 45 44 43 42 41 40  
1
2
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
P1.0/ADC0/T2  
P1.1/ADC1/T2EX  
P1.2/ADC2  
P2.7/A15/A23  
P2.6/A14/A22  
P2.5/A13/A21  
P2.4/A12/A20  
DGND  
PIN 1  
IDENTIFIER  
V
REF to AGND . . . . . . . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V  
3
Analog Inputs to AGND . . . . . . . . . . . –0.3 V, AVDD + 0.3 V  
Operating Temperature Range Industrial (B Version)  
4
P1.3/ADC3  
5
AV  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C  
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
6
DV  
DD  
AGND  
ADuC812  
TOP VIEW  
(Not to Scale)  
7
XTAL2  
C
V
REF  
8
XTAL1  
REF  
9
DAC0  
DAC1  
P2.3/A11/A19  
P2.2/A10/A18  
P2.1/A9/A17  
P2.0/A8/A16  
SDATA/MOSI  
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W  
10  
11  
12  
13  
Lead Temperature, Soldering  
P1.4/ADC4  
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C  
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C  
P1.5/ADC5/SS  
P1.6/ADC6  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those listed in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
14 15 16 17 18 19 20 21 22 23 24 25 26  
ORDERING GUIDE  
Package  
Temperature  
Range  
Package  
Option  
Model  
Description  
ADuC812BS  
Eval-ADuC812QS  
–40°C to +85°C  
52-Lead Plastic Quad Flatpack  
QuickStart Development System  
S-52  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection. Although  
the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on  
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are  
recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
–6–  
REV. B  
ADuC812  
PIN FUNCTION DESCRIPTIONS  
Mnemonic  
Type Function  
DVDD  
AVDD  
CREF  
VREF  
P
P
I
I/O  
Digital Positive Supply Voltage, 3 V or 5 V Nominal  
Analog Positive Supply Voltage, 3 V or 5 V Nominal  
Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND.  
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the  
reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this  
appears at the pin. This pin can be overdriven by an external reference.  
AGND  
P1.0–P1.7  
G
I
Analog Ground. Ground Reference point for the analog circuitry.  
Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure  
any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share  
the following functionality.  
ADC0–ADC7  
T2  
I
I
Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.  
Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to  
a 1 to 0 transition of the T2 input.  
T2EX  
I
Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for  
Counter 2.  
SS  
I
Slave Select Input for the SPI Interface  
SDATA  
SCLOCK  
MOSI  
MISO  
DAC0  
DAC1  
RESET  
I/O  
I/O  
I/O  
I/O  
O
User Selectable, I2C-Compatible or SPI Data Input/Output Pin  
Serial Clock Pin for I2C-Compatible or SPI Serial Interface Clock  
SPI Master Output/Slave Input Data I/O Pin for SPI Interface  
SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface  
Voltage Output from DAC0  
O
I
Voltage Output from DAC1  
Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the  
device. External power-on reset (POR) circuity must be implemented to drive the RESET pin as described  
in the Power-On Reset Operation section of this data sheet.  
P3.0–P3.7  
I/O  
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are  
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3  
pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also  
contain various secondary functions which are described below.  
RxD  
TxD  
INT0  
I/O  
O
I
Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port  
Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port  
Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two  
priority levels. This pin can also be used as a gate control input to Timer 0.  
INT1  
I
Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two  
priority levels. This pin can also be used as a gate control input to Timer 1.  
T0  
T1  
CONVST  
I
I
I
Timer/Counter 0 Input  
Timer/Counter 1 Input  
Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled.  
A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.  
WR  
O
O
O
I
G
I/O  
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.  
Read Control Signal, Logic Output. Enables the external data memory to Port 0.  
Output of the Inverting Oscillator Amplifier  
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.  
Digital Ground. Ground reference point for the digital circuitry.  
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are  
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2  
pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits  
the high order address bytes during fetches from external program memory and middle and high order  
address bytes during accesses to the external 24-bit external data memory space.  
RD  
XTAL2  
XTAL1  
DGND  
P2.0–P2.7  
(A8–A15)  
(A16–A23)  
REV. B  
–7–  
ADuC812  
PIN FUNCTION DESCRIPTION (continued)  
Mnemonic  
Type Function  
PSEN  
O
Program Store Enable, Logic Output. This output is a control signal that enables the external program  
memory to the bus during external fetch operations. It is active every six oscillator periods except during  
external data memory accesses. This pin remains high during internal program execution. PSEN can also be  
used to enable serial download mode when pulled low through a resistor on power-up or RESET.  
ALE  
O
I
Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit  
address space accesses) of the address into external memory during normal operation. It is activated every  
six oscillator periods except during an external data memory access.  
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from  
internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch  
all instructions from external program memory.  
EA  
P0.7–P0.0  
(A0–A7)  
I/O  
Port 0 is an 8-Bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them float and in  
that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data  
bus during accesses to external program or data memory. In this application it uses strong internal pull-ups  
when emitting 1s.  
The ratio is dependent upon the number of quantization levels  
TERMINOLOGY  
in the digitization process; the more levels, the smaller the quan-  
tization noise. The theoretical signal to (noise +distortion) ratio  
for an ideal N-bit converter with a sine wave input is given by:  
ADC SPECIFICATIONS  
Integral Nonlinearity  
This is the maximum deviation of any code from a straight line  
passing through the endpoints of the ADC transfer function.  
The endpoints of the transfer function are zero scale, a point  
1/2 LSB below the first code transition and full scale, a point  
1/2 LSB above the last code transition.  
Signal to (Noise + Distortion) = (6.02N + 1.76) dB  
Thus for a 12-bit converter, this is 74 dB.  
Total Harmonic Distortion  
Total Harmonic Distortion is the ratio of the rms sum of the  
harmonics to the fundamental.  
Differential Nonlinearity  
This is the difference between the measured and the ideal 1 LSB  
change between any two adjacent codes in the ADC.  
DAC SPECIFICATIONS  
Relative Accuracy  
Relative accuracy or endpoint linearity is a measure of the  
maximum deviation from a straight line passing through the  
endpoints of the DAC transfer function. It is measured after  
adjusting for zero error and full-scale error.  
Offset Error  
This is the deviation of the first code transition (0000 . . . 000)  
to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.  
Full-Scale Error  
This is the deviation of the last code transition from the ideal  
AIN voltage (Full Scale – 1.5 LSB) after the offset error has  
been adjusted out.  
Voltage Output Settling Time  
This is the amount of time it takes for the output to settle to a  
specified level for a full-scale input change.  
Signal to (Noise + Distortion) Ratio  
This is the measured ratio of signal to (noise + distortion) at the  
output of the A/D converter. The signal is the rms amplitude of  
the fundamental. Noise is the rms sum of all nonfundamental  
signals up to half the sampling frequency (fS/2), excluding dc.  
Digital-to-Analog Glitch Impulse  
This is the amount of charge injected into the analog output  
when the inputs change state. It is specified as the area of the  
glitch in nV sec.  
–8–  
REV. B  
ADuC812  
ARCHITECTURE, MAIN FEATURES  
7FH  
2FH  
The ADuC812 is a highly integrated true 12-bit data acquisition  
system. At its core, the ADuC812 incorporates a high- perfor-  
mance 8-bit (8052-Compatible) MCU with on-chip  
reprogrammable nonvolatile Flash program memory control-  
ling a multichannel (8-input channels), 12-bit ADC.  
BANKS  
SELECTED  
VIA  
BIT-ADDRESSABLE SPACE  
(BIT ADDRESSES 0FH–7FH)  
The chip incorporates all secondary functions to fully support  
the programmable data acquisition core. These secondary  
functions include User Flash Memory, Watchdog Timer  
(WDT), Power Supply Monitor (PSM) and various industry-  
standard parallel and serial interfaces.  
20H  
18H  
10H  
08H  
00H  
BITS IN PSW  
1FH  
17H  
0FH  
07H  
11  
10  
4 BANKS OF 8 REGISTERS  
R0–R7  
01  
00  
PROGRAM MEMORY SPACE  
READ ONLY  
RESET VALUE OF  
STACK POINTER  
FFFFH  
EXTERNAL  
PROGRAM  
MEMORY  
SPACE  
Figure 2. Lower 128 Bytes of Internal RAM  
MEMORY ORGANIZATION  
As with all 8052-compatible devices, the ADuC812 has separate  
address spaces for Program and Data memory as shown in Fig-  
ure 1. Also as shown in Figure 1, an additional 640 Bytes of  
User Data Flash EEPROM are available to the user. The User  
Data Flash Memory area is accessed indirectly via a group of  
control registers mapped in the Special Function Register (SFR)  
area in the Data Memory Space.  
2000H  
1FFFH  
EA = 1  
EA = 0  
EXTERNAL  
PROGRAM  
MEMORY  
SPACE  
INTERNAL  
8K BYTE  
FLASH/EE  
PROGRAM  
MEMORY  
The SFR space is mapped in the upper 128 bytes of internal data  
memory space. The SFR area is accessed by direct addressing  
only and provides an interface between the CPU and all on-chip  
peripherals. A block diagram showing the programming model  
of the ADuC812 via the SFR area is shown in Figure 3.  
0000H  
DATA MEMORY SPACE  
READ/WRITE  
FFFFFFH  
9FH  
(PAGE 159)  
640 BYTES  
FLASH/EE DATA  
MEMORY  
8K BYTE  
ELECTRICALLY  
640-BYTE  
REPROGRAMMABLE  
ELECTRICALLY  
ACCESSED  
INDIRECTLY  
VIA SFR  
NONVOLATILE  
REPROGRAMMABLE  
FLASH/EE PROGRAM  
NONVOLATILE  
CONTROL REGISTERS  
MEMORY  
FLASH/EE DATA  
MEMORY  
00H  
(PAGE 0)  
128-BYTE  
AUTO-CALIBRATING  
EXTERNAL  
DATA  
SPECIAL  
8051  
8-CHANNEL  
INTERNAL  
DATA MEMORY  
SPACE  
FUNCTION  
COMPATIBLE  
HIGH SPEED  
12-BIT ADC  
MEMORY  
SPACE  
REGISTER  
CORE  
AREA  
(24-BIT  
ADDRESS  
SPACE)  
FFH  
SPECIAL  
FUNCTION  
REGISTERS  
ACCESSIBLE  
BY DIRECT  
ADDRESSING  
ONLY  
FFH  
ACCESSIBLE  
OTHER ON-CHIP  
PERIPHERALS  
TEMPERATURE  
SENSOR  
BY  
INDIRECT  
ADDRESSING  
ONLY  
UPPER  
128  
2 ꢀ 12-BIT DACs  
SERIAL I/O  
PARALLEL I/O  
WDT  
80H  
80H  
7FH  
ACCESSIBLE  
BY  
LOWER  
128  
DIRECT  
PSM  
AND  
INDIRECT  
ADDRESSING  
00H  
000000H  
Figure 3. Programming Model  
Figure 1. Program and Data Memory Maps  
The lower 128 bytes of internal data memory are mapped as  
shown in Figure 2. The lowest 32 bytes are grouped into four  
banks of eight registers addressed as R0 through R7. The next  
16 bytes (128 bits) above the register banks form a block of  
bit addressable memory space at bit addresses 00H through 7FH.  
REV. B  
–9–  
ADuC812  
OVERVIEW OF MCU-RELATED SFRs  
Power Control SFR  
Accumulator SFR  
The Power Control (PCON) register contains bits for power-  
saving options and general-purpose status flags as shown in  
Table II.  
ACC is the Accumulator register and is used for math opera-  
tions including addition, subtraction, integer multiplication and  
division, and Boolean bit manipulations. The mnemonics for  
accumulator-specific instructions refer to the Accumulator as A.  
SFR Address  
87H  
00H  
No  
Power ON Default Value  
Bit Addressable  
B SFR  
The B register is used with the ACC for multiplication and  
division operations. For other instructions it can be treated as a  
general-purpose scratchpad register.  
SMOD ALEOFF GF1  
GF0  
PD  
IDL  
Stack Pointer SFR  
The SP register is the stack pointer and is used to hold an inter-  
nal RAM address that is called the “top of the stack.” The SP  
register is incremented before data is stored during PUSH and  
CALL executions. While the Stack may reside anywhere in  
on-chip RAM, the SP register is initialized to 07H after a reset.  
This causes the stack to begin at location 08H.  
Table II. PCON SFR Bit Designations  
Bit  
Name  
Description  
7
6
5
4
3
2
1
0
SMOD  
———  
———  
ALEOFF  
GF1  
Double UART Baud Rate  
Reserved  
Reserved  
Disable ALE Output  
General-Purpose Flag Bit  
General-Purpose Flag Bit  
Power-Down Mode Enable  
Idle Mode Enable  
Data Pointer  
The Data Pointer is made up of three 8-bit registers, named  
DPP (page byte), DPH (high byte) and DPL (low byte). These  
are used to provide memory addresses for internal and external  
code access and external data access. It may be manipulated as a  
16-bit register (DPTR = DPH, DPL), although INC DPTR  
instructions will automatically carry over to DPP, or as three  
independent 8-bit registers (DPP, DPH, DPL).  
GF0  
PD  
IDL  
Program Status Word SFR  
The PSW register is the Program Status Word which contains  
several bits reflecting the current status of the CPU as detailed  
in Table I.  
SFR Address  
Power ON Default Value  
Bit Addressable  
D0H  
00H  
Yes  
CY  
AC  
F0  
RS1  
RS0  
OV  
F1  
P
Table I. PSW SFR Bit Designations  
Bit  
Name  
CY  
AC  
F0  
RS1  
RS0  
Description  
7
6
5
4
3
Carry Flag  
Auxiliary Carry Flag  
General-Purpose Flag  
Register Bank Select Bits  
RS1  
RS0  
Selected Bank  
0
0
1
1
0
1
0
1
0
1
2
3
2
1
0
OV  
F1  
P
Overflow Flag  
General-Purpose Flag  
Parity Bit  
–10–  
REV. B  
ADuC812  
SPECIAL FUNCTION REGISTERS  
All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR)  
area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other on-  
chip peripherals.  
Figure 4 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the figure  
below (NOT USED). Unoccupied locations in the SFR address space are not implemented i.e., no register exists at this location. If  
an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on chip testing are shown lighter shaded  
below (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted  
by '1' in the figure below, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H.  
SPICON1  
DAC0L  
DAC0H  
DAC1L  
DAC1H  
DACCON  
ISPI  
FFH  
WCOL  
SPE  
FDH  
SPIM  
FCH  
CPOL CPHA SPR1  
SPR0  
RESERVED NOT USED  
BITS  
0
0
0
0
0
0
0
FEH  
0
0
0
0
0
0
0
0
0
FBH  
0
FAH  
0
F9H  
0
F8H  
0
F8H  
00H F9H 00H FAH 00H FBH 00H FCH 00H FDH 04H  
ADCOFSL3 ADCOFSH3 ADCGAINL3 ADCGAINH3 ADCCON3  
B1  
SPIDAT  
RESERVED  
BITS  
BITS  
F7H  
MDO  
F6H  
0
0
0
F5H  
MCO  
F4H  
MDI  
F3H  
0
F2H  
0
F1H  
0
F0H  
0
0
0
0
0
F0H 00H F1H 00H F2H 20H F3H 00H F4H 00H F5H 00H  
I2CCON1  
F7H 00H  
ADCCON1  
MDE  
EEH  
I2CM I2CRS I2CTX  
I2CI  
E8H  
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED  
EFH  
EDH  
ECH  
EBH  
0
0
0
0
EAH  
E9H  
0
0
0
0
0
0
0
0
0
EFH 20H  
E8H 00H  
ACC1  
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
BITS  
E7H  
E6H  
E5H  
E4H  
E3H  
E2H  
E1H  
E0H  
E0H  
00H  
ADCCON21 ADCDATAL ADCDATAH  
PSMCON  
DFH DEH  
ADCI  
DFH  
DMA CCONV SCONV CS3  
CS2  
DAH  
CS1  
D9H  
CS0  
D8H  
RESERVED RESERVED RESERVED RESERVED  
DEH  
0
0
0
DDH  
0
DCH  
0
DBH  
D8H 00H D9H 00H DAH 00H  
PSW1  
D0H 00H  
T2CON1  
C8H 00H  
WDCON1  
C0H 00H  
IP1  
DMAL  
D2H 00H D3H 00H D4H 00H  
RCAP2L RCAP2H TL2  
DMAH  
DMAP  
CY  
D7H  
AC  
D6H  
F0  
D5H  
RS1  
D4H  
RS0  
D3H  
OV  
D2H  
FI  
D1H  
P
D0H  
RESERVED  
RESERVED  
RESERVED RESERVED RESERVED  
0
0
TH2  
TF2  
CFH  
EXF2  
CEH  
RCLK TCLK EXEN2  
CDH  
TR2  
CAH  
CNT2 CAP2  
C9H  
RESERVED RESERVED  
0
CCH  
0
CBH  
0
0
C8H  
0
CAH 00H CBH 00H CCH 00H CDH 00H  
ETIM3  
EDARL  
C6H 00H  
EDATA3  
PRE2  
C7H  
PRE1  
PRE0  
C5H  
WDR1 WDR2 WDS  
WDE  
C0H  
NOT USED  
ECON  
NOT USED  
NOT USED  
RESERVED  
RESERVED  
EDATA4  
0
C6H  
0
0
C4H  
0
0
C3H  
0
C2H  
0
C1H  
0
0
0
0
C4H C9H  
EDATA1  
ETIM1  
ETIM2  
EDATA2  
PSI  
BFH  
PADC  
PT2  
BDH  
PS  
BCH  
PT1  
BBH  
PX1  
BAH  
PT0  
B9H  
PX0  
B8H  
0
1
0
1
0
1
0
1
BEH  
0
0
1
0
1
0
1
0
1
0
0
B8H 00H B9H 00H BAH 52H BBH 04H BCH 00H BDH 00H BEH 00H BFH 00H  
P31  
RD  
B7H  
WR  
B6H  
T1  
B5H  
T0  
B4H  
INT1  
B3H  
INT0  
B2H  
TxD  
B1H  
RxD  
B0H  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
B0H FFH  
IE1  
IE2  
EA  
AFH  
EADC  
ET2  
ADH  
ES  
ACH  
ET1  
ABH  
EX1  
AAH  
ET0  
A9H  
EX0  
A8H  
NOT USED  
NOT USED  
NOT USED  
AEH  
0
1
0
1
0
1
A8H 00H A9H 00H  
P21  
NOT USED  
NOT USED  
I2CDAT  
NOT USED  
I2CADD  
NOT USED  
A7H  
A6H  
A5H  
A4H  
A3H  
A2H  
A1H  
A0H  
A0H FFH  
SCON1  
SBUF  
SM0  
9FH  
SM1  
9EH  
SM2  
9DH  
REN  
9CH  
TB8  
9BH  
RB8  
9AH  
TI  
99H  
RI  
98H  
NOT USED  
98H 00H 99H 00H 9AH 00H 9BH 55H  
P11, 2  
T2EX  
91H  
T2  
90H  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
TH0  
NOT USED  
TH1  
NOT USED  
97H  
96H  
95H  
94H  
93H  
92H  
90H FFH  
TCON1  
TMOD  
TL0  
TL1  
TF1  
8FH  
TR1  
8EH  
TF0  
8DH  
TR0  
8CH  
IE1  
8BH  
IT1  
8AH  
IE0  
89H  
IT0  
88H  
NOT USED  
88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H  
P01  
SP  
DPL  
DPH  
DPP  
PCON  
RESERVED RESERVED  
87H  
86H  
85H  
84H  
83H  
82H  
81H  
80H  
80H FFH 81H 07H 82H 00H 83H 00H 84H 00H  
87H 00H  
SFR MAP KEY:  
THESE BITS ARE CONTAINED IN THIS BYTE.  
TCON  
MNEMONIC  
IT0  
88H  
MNEMONIC  
SFR ADDRESS  
IE0  
89H  
0
0
DEFAULT VALUE  
88H 00H  
DEFAULT VALUE  
SFR ADDRESS  
SFR NOTES:  
1
2
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.  
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE  
PORT PINS, WRITE A '0' TO THE CORRESPONDING PORT 1 SFR BIT.  
3
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.  
Figure 4. Special Function Register Locations and Reset Values  
REV. B  
–11–  
ADuC812  
ADC CIRCUIT INFORMATION  
ADC Transfer Function  
General Overview  
The analog input range for the ADC is 0 V to VREF. For this  
range, the designed code transitions occur midway between  
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,  
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight  
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when  
VREF = 2.5 V. The ideal input/output transfer characteristic for  
the 0 to VREF range is shown in Figure 5.  
The ADC conversion block incorporates a fast, 8-channel,  
12-bit, single supply A/D converter. This block provides the  
user with multichannel mux, track/hold, on-chip reference,  
calibration features and A/D converter. All components in this  
block are easily configured via a 3-register SFR interface.  
The A/D converter consists of a conventional successive-  
approximation converter based around a capacitor DAC. The  
converter accepts an analog input range of 0 to +VREF. A high  
precision, low drift and factory calibrated 2.5 V reference is  
provided on-chip. The internal reference may be overdriven via  
the external VREF pin. This external reference can be in the  
OUTPUT  
CODE  
111...111  
111...110  
111...101  
range 2.3 V to AVDD  
.
111...100  
FS  
1LSB =  
Single step or continuous conversion modes can be initiated in  
software or alternatively by applying a convert signal to the an  
external pin. Timer 2 can also be configured to generate a repeti-  
tive trigger for ADC conversions. The ADC may be configured  
to operate in a DMA Mode whereby the ADC block continu-  
ously converts and captures samples to an external RAM space  
without any interaction from the MCU core. This automatic  
capture facility can extend through a 16 MByte external Data  
Memory space.  
4096  
000...011  
000...010  
000...001  
000...000  
0V 1LSB  
+FS  
–1LSB  
VOLTAGE INPUT  
Figure 5. ADC Transfer Function  
The ADuC812 is shipped with factory programmed calibration  
coefficients which are automatically downloaded to the ADC on  
power-up ensuring optimum ADC performance. The ADC core  
contains internal Offset and Gain calibration registers. A  
software calibration routine is provided to allow the user to  
overwrite the factory programmed calibration coefficients if  
required, thus minimizing the impact of endpoint errors in the  
user’s target system.  
Typical Operation  
Once configured via the ADCCON 1-3 SFRs (shown on the  
following page) the ADC will convert the analog input and provide  
an ADC 12-bit result word in the ADCDATAH/L SFRs. The top  
4 bits of the ADCDATAH SFR will be written with the channel  
selection bits so as to identify the channel result. The format of the  
ADC 12 bit result word is shown in Figure 6.  
A voltage output from an On-Chip bandgap reference propor-  
tional to absolute temperature can also be routed through the  
front end ADC multiplexor (effectively a 9th ADC channel  
input) facilitating a temperature sensor implementation.  
ADCDATAH SFR  
CH–ID  
TOP 4 BITS  
HIGH 4 BITS OF  
ADC RESULT WORD  
ADCDATAL SFR  
LOW 8 BITS OF THE  
ADC RESULT WORD  
Figure 6. ADC Result Format  
–12–  
REV. B  
ADuC812  
ADCCON1 – (ADC Control SFR #1)  
The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as  
detailed below.  
SFR Address:  
EFH  
SFR Power-On Default Value: 20H  
MD1  
MD0  
CK1  
CK0  
AQ1  
AQ0  
T2C  
EXC  
Table III. ADCCON1 SFR Bit Designations  
Bit  
Name  
Description  
ADCCON1.7 MD1  
ADCCON1.6 MD0  
The mode bits (MD1, MD0) select the active operating mode of the ADC  
as follows:  
MD1 MD0 Active Mode  
0
0
1
1
0
1
0
1
ADC powered down.  
ADC normal mode  
ADC powered down if not executing a conversion cycle.  
ADC standby if not executing a conversion cycle.  
Note: In powered down mode the ADC VREF circuits are maintained on, whereas in power-down mode all  
ADC peripherals are powered down thus minimizing current consumption.  
ADCCON1.5 CK1  
ADCCON1.4 CK0  
The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the  
ADC clock. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected  
as follows:  
CK1 CK0 MCLK Divider  
0
0
1
1
0
1
0
1
1
2
4
8
ADCCON1.3 AQ1  
ADCCON1.2 AQ0  
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track/hold amplifier  
to acquire the input signal and are selected as follows:  
AQ1 AQ0 #ADC Clks  
0
0
1
1
0
1
0
1
1
2
4
8
ADCCON1.1 T2C  
ADCCON1.0 EXC  
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 over flow bit be used as  
the ADC convert start trigger input.  
The external trigger enable bit (EXC) is set by the user to allow the external Pin 23 (CONVST) to be  
used as the active low convert start input. This input should be an active low pulse (minimum pulse  
width >100 ns) at the required sample rate.  
REV. B  
–13–  
ADuC812  
ADCCON2 – (ADC Control SFR #2)  
The ADCCON2 register controls ADC channel selection and conversion modes as detailed below.  
SFR Address:  
SFR Power On Default Value:  
D8H  
00H  
ADCI  
DMA  
CCONV  
SCONV  
CS3  
CS2  
CS1  
CS0  
Table IV. ADCCON2 SFR Bit Designations  
L
ocation  
Name  
Description  
ADCCON2.7 ADCI  
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the  
end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt  
Service Routine.  
ADCCON2.6 DMA  
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode opera-  
tion. A more detailed description of this mode is given in the ADC DMA Mode section.  
ADCCON2.5 CCONV  
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of  
conversion.  
In this mode the ADC starts converting based on the timing and channel configuration already set up in  
the ADCCON SFRs, the ADC automatically starts another conversion once a previous conversion  
has completed.  
ADCCON2.4 SCONV  
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is  
automatically reset to “0” on completion of the single conversion cycle.  
ADCCON2.3 CS3  
ADCCON2.2 CS2  
ADCCON2.1 CS1  
ADCCON2.0 CS0  
The channel selection bits (CS3-0) allow the user to program the ADC channel selection under  
software control. When a conversion is initiated the channel converted will be that pointed to by  
these channel selection bits. In DMA mode the channel selection is derived from the channel ID  
written to the external memory.  
CS3 CS2 CS1 CS0 CH#  
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Temp Sensor  
DMA STOP  
All other combinations reserved  
ADCCON3 – (ADC Control SFR #3)  
The ADCCON3 register gives user software an indication of ADC busy status.  
SFR Address:  
SFR Power On Default Value:  
F5H  
00H  
BUSY  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
RSVD  
Table V. ADCCON3 SFR Bit Designations  
Bit  
Location  
Bit  
Status  
Description  
ADCCON3.7 BUSY  
The ADC busy status bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or  
calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.  
ADCCON3.6 RSVD  
ADCCON3.5 RSVD  
ADCCON3.4 RSVD  
ADCCON3.3 RSVD  
ADCCON3.2 RSVD  
ADCCON3.1 RSVD  
ADCCON3.0 RSVD  
ADCCON3.0–3.6 are reserved (RSVD) for internal use. These bits will read as zero and should only  
be written as zero by user software.  
–14–  
REV. B  
ADuC812  
Driving the A/D Converter  
ADuC812  
The ADC incorporates a successive approximation (SAR) archi-  
tecture involving a charge-sampled input stage. Figure 7 shows  
the equivalent circuit of the analog input section. Each ADC  
conversion is divided into two distinct phases as defined by the  
position of the switches in Figure 7. During the sampling phase  
(with SW1 and SW2 in the “track” position) a charge propor-  
tional to the voltage on the analog input is developed across the  
input sampling capacitor. During the conversion phase (with  
both switches in the “hold” position) the capacitor DAC is  
adjusted via internal SAR logic until the voltage on node A is  
zero indicating that the sampled charge on the input capacitor is  
balanced out by the charge being output by the capacitor DAC.  
The digital value finally contained in the SAR is then latched  
out as the result of the ADC conversion. Control of the SAR,  
and timing of acquisition and sampling modes, is handled  
automatically by built-in ADC control logic. Acquisition and  
conversion times are also fully configurable under user control.  
51⍀  
1
AIN0  
0.01␮F  
Figure 8. Buffering Analog Inputs  
does so by providing a capacitive bank from which the 2 pF sam-  
pling capacitor can draw its charge. Since the 0.01 µF capacitor  
in Figure 8 is more than 4096 times the size of the 2 pF sam-  
pling capacitor, its voltage will not change by more than one  
count (1/4096) of the 12-bit transfer function when the 2 pF  
charge from a previous channel is dumped onto it. A larger  
capacitor can be used if desired, but not a larger resistor (for  
reasons described below).  
The Schottky diodes in Figure 8 may be necessary to limit the  
voltage applied to the analog input pin as per the data sheet  
absolute maximum ratings. They are not necessary if the op  
amp is powered from the same supply as the ADuC812 since  
in that case the op amp is unable to generate voltages above  
VDD or below ground. An op amp of some kind is necessary  
unless the signal source is very low impedance to begin with.  
DC leakage currents at the ADuC812’s analog inputs can  
cause measurable dc errors with external source impedances  
as little as 100 Ω or so. To ensure accurate ADC operation, keep  
the total source impedance at each analog input less than 61 Ω.  
The table below illustrates examples of how source impedance  
can affect dc accuracy.  
AIN0  
TEMPERATURE  
SENSOR  
ADuC812  
AIN7  
200⍀  
TRACK  
SW1  
2pF  
Source  
Impedance  
61 Ω  
Error from 1 µA  
Leakage Current  
61 µV = 0.1 LSB  
610 µV = 1 LSB  
Error from 10 µA  
Leakage Current  
610 µV = 1 LSB  
6.1 mV = 10 LSB  
CAPACITOR  
DAC  
HOLD  
NODE A  
SW2  
610 Ω  
Although Figure 8 shows the op amp operating at a gain of 1,  
you can of course configure it for any gain needed. Also, you  
can just as easily use an instrumentation amplifier in its place to  
condition differential signals. Use any modern amplifier that is  
capable of delivering the signal (0 to VREF) with minimal satura-  
tion. Some single-supply rail-to-rail op amps that are useful for  
this purpose include, but are certainly not limited to, the ones  
given in Table VI. Check Analog Devices literature (CD ROM  
data book, etc.) for details on these and other op amps and  
instrumentation amps.  
TRACK  
HOLD  
COMPARATOR  
AGND  
Figure 7. Internal ADC Structure  
Note that whenever a new input channel is selected, a residual  
charge from the 2 pF sampling capacitor places a transient on  
the newly selected input. The signal source must be capable of  
recovering from this transient before the sampling switches click  
into “hold” mode. Delays can be inserted in software (between  
channel selection and conversion request) to account for input  
stage settling, but a hardware solution will alleviate this burden  
from the software design task and will ultimately result in a  
cleaner system implementation. One hardware solution would  
be to choose a very fast settling op amp to drive each analog  
input. Such an op amp would need to fully settle from a small  
signal transient in less than 300 ns in order to guarantee adequate  
settling under all software configurations. A better solution, recom-  
mended for use with any amplifier, is shown in Figure 8.  
Table VI. Some Single-Supply Op Amps  
Op Amp Model  
Characteristics  
OP181/OP281/OP481  
OP191/OP291/OP491  
OP196/OP296/OP496  
OP183/OP283  
OP162/OP262/OP462  
AD820/AD822/AD824  
AD823  
Micropower  
I/O Good up to VDD, Low Cost  
I/O to VDD, Micropower, Low Cost  
High Gain-Bandwidth Product  
High GBP, Micro Package  
FET Input, Low Cost  
FET Input, High GBP  
Though at first glance the circuit in Figure 8 may look like a  
simple antialiasing filter, it actually serves no such purpose since  
its corner frequency is well above the Nyquist frequency, even at  
a 200 kHz sample rate. Though the R/C does helps to reject some  
incoming high-frequency noise, its primary function is to ensure  
that the transient demands of the ADC input stage are met. It  
Keep in mind that the ADC’s transfer function is 0 to VREF, and  
any signal range lost to amplifier saturation near ground will  
impact dynamic range. Though the op amps in Table VI are  
capable of delivering output signals very closely approaching  
REV. B  
–15–  
ADuC812  
ground, no amplifier can deliver signals all the way to ground when  
powered by a single supply. Therefore, if a negative supply is  
available, you might consider using it to power the front-end  
amplifiers. If you do, however, be sure to include the Schottky  
diodes shown in Figure 8 (or at least the lower of the two  
diodes) to protect the analog input from undervoltage conditions.  
To summarize this section, use the circuit of Figure 8 to drive  
the analog input pins of the ADuC812.  
ADuC812  
V
DD  
2.5V  
51⍀  
BANDGAP  
REFERENCE  
EXTERNAL  
VOLTAGE  
REFERENCE  
BUFFER  
V
C
REF  
8
7
0.1␮F  
Voltage Reference Connections  
REF  
The on-chip 2.5 V bandgap voltage reference can be used as the  
reference source for the ADC and DACs. In order to ensure  
the accuracy of the voltage reference you must decouple both  
the VREF pin and the CREF pin to ground with 0.1 µF ceramic  
chip capacitors as shown in Figure 9.  
0.1␮F  
Figure 10. Using an External Voltage Reference  
Configuring the ADC  
The three SFRs (ADCCON1, ADCCON2, ADCCON3) con-  
figure the ADC. In nearly all cases, an acquisition time of 1 ADC  
clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide plenty  
of time for the ADuC812 to acquire its signal before switching  
the internal track and hold amplifier in to hold mode. The  
only exception would be a high source impedance analog  
input, but these should be buffered first anyway since source  
impedances of greater than 610 Ω can cause dc errors as well.  
ADuC812  
2.5V  
51⍀  
BUFFER  
BANDGAP  
REFERENCE  
BUFFER  
V
REF  
8
0.1␮F  
The ADuC812’s successive approximation ADC is driven by a  
divided down version of the master clock. To ensure adequate  
ADC operation, this ADC clock must be between 400 kHz and  
4 MHz, and optimum performance is obtained with ADC clock  
between 400 kHz and 3 MHz. Frequencies within this range can  
easily be achieved with master clock frequencies from 400 kHz to  
well above 16 MHz with the four ADC clock divide ratios to  
choose from. For example, with a 12 MHz master clock, set the  
ADC clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz)  
by setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1,  
ADCCON1.4 = 0).  
C
REF  
7
0.1␮F  
Figure 9. Decoupling VREF and CREF  
The internal voltage reference can also be tapped directly from  
the VREF pin, if desired, to drive external circuitry. However, a  
buffer must be used in this case to ensure that no current is  
drawn from the VREF pin itself. The voltage on the CREF pin is  
that of an internal node within the buffer block, and its voltage  
is critical to ADC and DAC accuracy. Do not connect anything  
to this pin except the capacitor, and be sure to keep trace-  
lengths short on the CREF capacitor, decoupling the node  
straight to the underlying ground plane.  
The total ADC conversion time is 15 ADC clocks, plus 1 ADC  
clock for synchronization, plus the selected acquisition time (1,  
2, 3, or 4 ADC clocks). For the example above, with a 1 clock  
acquisition time, total conversion time is 17 ADC clocks (or  
5.67 µs for a 3 MHz ADC clock).  
The ADuC812 powers up with its internal voltage reference in  
the “off” state. The voltage reference turns on automatically  
whenever the ADC or either DAC gets enabled in software.  
Once enabled, the voltage reference requires approximately  
65 ms to power up and settle to its specified value. Be sure that  
your software allows this time to elapse before initiating any  
conversions. If an external voltage reference is preferred, simply  
connect it to the VREF pin as shown in Figure 10 to overdrive  
the internal reference.  
In continuous conversion mode, a new conversion begins each  
time the previous one finishes. The sample rate is then simply  
the inverse of the total conversion time described above. In the  
example above, the continuous conversion mode sample rate  
would be 176.5 kHz.  
ADC DMA Mode  
The on-chip ADC has been designed to run at a maximum  
conversion speed of 5 µs (200 kHz sampling rate). When con-  
verting at this rate the ADuC812 micro has 5 µs to read the  
ADC result and store the result in memory for further post  
processing all within 5 µs otherwise the next ADC sample could  
be lost. In an interrupt driven routine the micro would also have  
to jump to the ADC Interrupt Service routine which will also  
increase the time required to store the ADC results. In applica-  
tions where the ADuC812 cannot sustain the interrupt rate, an  
ADC DMA mode is provided.  
To ensure accurate ADC operation, the voltage applied to VREF  
must be between 2.3 V and AVDD. In situations where analog  
input signals are proportional to the power supply (such as some  
strain-gage applications) it can be desirable to connect the VREF  
pin directly to AVDD. In such a configuration you must also  
connect the CREF pin directly to AVDD to circumvent internal  
buffer headroom limitations. This allows the ADC input trans-  
fer function to accurately span the full range 0 to AVDD  
.
Operation of the ADC or DACs with a reference voltage below  
2.3 V, however, may incur loss of accuracy eventually resulting  
in missing codes or nonmonotonicity. For that reason, do not  
use a reference voltage less than 2.3 V.  
To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be  
set. This allows the ADC results to be written directly to a  
16 MByte external static memory SRAM (mapped into data  
memory space) without any interaction from the ADuC812  
–16–  
REV. B  
ADuC812  
core. This mode allows the ADuC812 to capture a contiguous  
sample stream at full ADC update rates (200 kHz).  
STOP COMMAND  
1
0
0
1
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
0
00000AH  
NO CONVERSION  
RESULT WRITTEN HERE  
A typical DMA Mode configuration example.  
CONVERSION RESULT  
FOR ADC CH#3  
To set the ADuC812 into DMA mode a number of steps must  
be followed.  
CONVERSION RESULT  
FOR TEMP SENSOR  
0
1. The ADC must be powered down. This is done by ensuring  
MD1 and MD0 are both set to 0 in ADCCON1.  
CONVERSION RESULT  
FOR ADC CH#5  
0
2. The DMA Address pointer must be set to the start address of  
where the ADC Results are to be written. This is done by  
writing to the DMA mode Address Pointers DMAL, DMAH,  
and DMAP. DMAL must be written to first, followed by  
DMAH and then by DMAP.  
CONVERSION RESULT  
FOR ADC CH#2  
000000H  
1
Figure 12. Typical External Memory Configuration Post  
ADC DMA Operation  
The DMA logic operates from the ADC clock and uses  
pipe-lining to perform the ADC conversions and access the  
external memory at the same time. The time it takes to perform  
one ADC conversion is called a DMA cycle. The actions per-  
formed by the logic during a typical DMA cycle are shown in  
the following diagram.  
3. The external memory must be preconfigured. This consists  
of writing the required ADC channel IDs into the top four  
bits of every second memory location in the external SRAM  
starting at the first address specified by the DMA address  
pointer. As the ADC DMA mode operates independent from  
the ADuC812 core it is necessary to provide it with a stop  
command. This is done by duplicating the last channel ID to  
be converted followed by “1111” into the next channel selec-  
tion field. A typical preconfiguration of external memory is  
as follows.  
CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE  
WRITE ADC RESULT  
CONVERTED DURING  
PREVIOUS DMA CYCLE  
READ CHANNEL ID  
TO BE CONVERTED DURING  
NEXT DMA CYCLE  
STOP COMMAND  
1
0
0
1
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
0
00000AH  
DMA CYCLE  
REPEAT LAST CHANNEL  
FOR A VALID STOP  
CONDITION  
Figure 13. DMA Cycle  
From the previous diagram, it can bee seen that during one DMA  
cycle the following actions are performed by the DMA logic.  
CONVERT ADC CH#3  
CONVERT TEMP SENSOR  
CONVERT ADC CH#5  
0
1. An ADC conversion is performed on the channel whose ID  
was read during the previous cycle.  
0
2. The 12-bit result and the channel ID of the conversion per-  
formed in the previous cycle is written to the external memory.  
000000H  
1
CONVERT ADC CH#2  
Figure 11. Typical DMA External Memory Preconfiguration  
3. The ID of the next channel to be converted is read from  
external memory.  
4. The DMA is initiated by writing to the ADC SFRs in the  
following sequence.  
For the previous example the complete flow of events is shown  
in Figure 13. Because the DMA logic uses pipe-lining, it takes  
three cycles before the first correct result is written out.  
a. ADCCON2 is written to enable the DMA mode. i.e.,  
MOV ADCCON2, #40H; DMA Mode enabled  
b. ADCCON1 is written to configure the conversion time  
and power up of the ADC. It can also enable Timer 2  
driven conversions or External Triggered conversions if  
required.  
Micro Operation during ADC DMA Mode  
During ADC DMA mode the MicroConverter core is free to  
continue code execution, including general housekeeping and  
communication tasks. However, it should be noted that MCU  
core accesses to Ports 0 and 2 (which of course are being used  
by the DMA controller) are gated “OFF” during ADC DMA  
mode of operation. This means that even though the instruction  
that accesses the external Ports 0 or 2 will appear to execute, no  
data will be seen at these external Ports as a result.  
c. ADC conversions are initiated. This is done by starting  
single/continuous conversions, starting Timer 2 running  
for Timer 2 conversions or by receiving an external trigger.  
When the DMA conversions are completed, the ADC interrupt  
bit ADCI is set by hardware and the external SRAM contains  
the new ADC conversion results as shown below. It should be  
noted that no result is written to the last two memory locations.  
The MicroConverter core can be configured with an interrupt to  
be triggered by the DMA controller when it had finished filling  
the requested block of RAM with ADC results, allowing the  
service routine for this interrupt to post process data without  
any real-time timing constraints.  
When the DMA mode logic is active it takes the responsibility of  
storing the ADC results away from both the user and ADuC812  
core logic. As it writes the results of the ADC conversions to  
external memory, it takes over the external memory interface  
from the core. Thus, any core instructions which access the external  
memory while DMA mode is enabled will not get access to it. The  
core will execute the instructions and they will take the same time  
to execute but they will not gain access to the external memory.  
The Offset and Gain Calibration Coefficients  
The ADuC812 has two ADC calibration coefficients, one for offset  
calibration and one for gain calibration. Both the offset and gain  
calibration coefficients are 14-bit words, located in the Special  
Function Register (SFR) area. The offset calibration coefficient  
is divided into ADCOFSH (6 bits) and ADCOFSL (8 bits) and  
REV. B  
–17–  
ADuC812  
the gain calibration coefficient is divided into ADCGAINH (6 bits)  
and ADCGAINL (8 bits).The offset calibration coefficient compen-  
sates for dc offset errors in both the ADC and the input signal.  
EPROM  
TECHNOLOGY  
EEPROM  
TECHNOLOGY  
IN-CIRCUIT  
REPROGRAMMABLE  
SPACE EFFICIENT/  
DENSITY  
Increasing the offset coefficient compensates for positive offset,  
and effectively pushes the ADC Transfer Function DOWN.  
Decreasing the offset coefficient compensates for negative offset,  
and effectively pushes the ADC Transfer Function UP. The  
maximum offset that can be compensated is typically 5% of  
FLASH/EE MEMORY  
TECHNOLOGY  
Figure 14. Flash Memory Development  
V
REF, which equates to typically 125 mV with a 2.5 V reference.  
update program code space in-circuit without the need to  
replace one-time programmable (OTP) devices at remote  
operating nodes.  
Similarly, the gain calibration coefficient compensates for dc  
gain errors in both the ADC and the input signal.  
Increasing the gain coefficient compensates for a smaller analog  
input signal range and scales the ADC Transfer Function UP,  
effectively increasing the slope of the transfer function. Decreas-  
ing the gain coefficient, compensates for a larger analog input  
signal range and scales the ADC Transfer Function DOWN,  
effectively decreasing the slope of the transfer function. The  
maximum analog input signal range for which the gain coeffi-  
cient can compensate is 1.025 × VREF and the minimum input  
range is 0.975 × VREF which equates to typically 2.5% of the  
reference voltage.  
Flash/EE Memory and the ADuC812  
The ADuC812 provides two arrays of Flash/EE memory for  
user applications. 8K bytes of Flash/EE Program space are  
provided on-chip to facilitate code execution without any  
external discrete ROM device requirements. The program  
memory can be programmed using conventional third party  
memory programmers. This array can also be programmed  
in-circuit, using the serial download mode provided.  
A 640-Byte Flash/EE Data Memory space is also provided on-chip.  
This may be used by the user as a general purpose nonvolatile  
scratchpad area. User access to this area is via a group of six  
SFRs.  
Calibration  
Each ADuC812 is calibrated in the factory prior to shipping and  
the offset and gain calibration coefficients are stored in a hidden  
area of FLASH/EE memory. Each time the ADuC812 powers  
up, an internal power-on configuration routine, copies these  
coefficients into the offset and gain calibration registers in  
the SFR area.  
ADuC812 Flash/EE Memory Reliability  
The Flash/EE Program and Data Memory arrays on the ADuC812  
are fully qualified for two key Flash/EE memory characteristics,  
namely Flash/EE Memory Cycling Endurance and Flash/EE  
Memory Data Retention.  
The MicroConverter ADC accuracy may vary from system to  
system due to board layout, grounding, clock speed, etc. To get  
the best ADC accuracy in your system, you should perform  
the software calibration routine described in the technical  
note uC005 available from the MicroConverter home page  
(www.analog.com/microconverter).  
Endurance quantifies the ability of the Flash/EE memory to be  
cycled through many Program, Read, and Erase cycles. In real  
terms, a single endurance cycle is composed of four independent,  
sequential events. These events are defined as:  
a. Initial Page Erase Sequence  
b. Read/Verify Sequence  
c. Byte Program Sequence  
d. Second Read/Verify Sequence  
A single Flash/EE  
Memory  
Endurance Cycle  
NONVOLATILE FLASH MEMORY  
Flash Memory Overview  
The ADuC812 incorporates Flash memory technology on-chip  
to provide the user with a nonvolatile, in-circuit reprogram-  
mable, code and data memory space.  
In reliability qualification, every byte in both the program and  
data Flash/EE memory is cycled from 00 hex to FFhex until a  
first fail is recorded signifying the endurance limit of the on-chip  
Flash/EE memory.  
Flash/EE memory is a relatively recent type of nonvolatile memory  
technology and is based on a single transistor cell architecture.  
As indicated in the specification pages of this data sheet, the  
ADuC812 Flash/EE Memory Endurance qualification has been  
carried out in accordance with JEDEC Specification A117 over  
the industrial temperature range of –40°C, +25°C, and +85°C.  
The results allow the specification of a minimum endurance figure  
over supply and temperature of 10,000 cycles, with an endurance  
figure of 50,000 cycles being typical of operation at 25°C.  
This technology is basically an outgrowth of EPROM technol-  
ogy and was developed through the late 1980s. Flash/EE memory  
takes the flexible in-circuit reprogrammable features of  
EEPROM and combines them with the space efficient/density  
features of EPROM (see Figure 14).  
Because Flash/EE technology is based on a single transistor cell  
architecture, a Flash memory array, like EPROM, can be imple-  
mented to achieve the space efficiencies or memory densities  
required by a given design.  
Retention quantifies the ability of the Flash/EE memory to retain  
its programmed data over time. Again, the ADuC812 has been  
qualified in accordance with the formal JEDEC Retention Life-  
time Specification (A117) at a specific junction temperature  
(TJ = 55°C). As part of this qualification procedure, the Flash/EE  
memory is cycled to its specified endurance limit described  
above, before data retention is characterized. This means  
that the Flash/EE memory is guaranteed to retain its data for  
its full specified retention lifetime every time the Flash/EE  
memory is reprogrammed.  
Like EEPROM, Flash memory can be programmed in-system at  
a byte level, although it must first be erased; the erase being  
performed in page blocks. Thus, Flash memory is often and  
more correctly referred to as Flash/EE memory.  
Overall, Flash/EE memory represents a step closer towards  
the ideal memory device that includes nonvolatility, in-circuit  
programmability, high density and low cost. Incorporated in  
the ADuC812, Flash/EE memory technology allows the user to  
–18–  
REV. B  
ADuC812  
Using the Flash/EE Program Memory  
Using the Flash/EE Data Memory  
This 8K Byte Flash/EE Program Memory array is mapped  
into the lower 8K bytes of the 64K bytes program space addres-  
sable by the ADuC812 and will be used to hold user code in  
typical applications.  
The user Flash/EE data memory array consists of 640 bytes that  
are configured into 160 (Page 00H to Page 9FH), 4-byte pages  
as shown in Figure 16.  
9FH  
BYTE 1  
BYTE 2  
BYTE 3  
BYTE 4  
The program memory array can be programmed in one of two  
modes, namely:  
Serial Downloading (In-Circuit Programming)  
As part of its embedded download/debug kernel, the ADuC812  
facilitates serial code download via the standard UART serial port.  
Serial download mode is automatically entered on power-up if  
the external pin, PSEN, is pulled low through an external resis-  
tor as shown in Figure 15. Once in this mode, the user can  
download code to the program memory array while the device is  
sited in its target application hardware. A PC serial download  
executable is provided as part of the ADuC812 QuickStart  
development system.  
00H  
BYTE 1  
BYTE 2  
BYTE 3  
BYTE 4  
Figure 16. User Flash/EE Memory Configuration  
As with other ADuC812 user-peripherals circuits, the inter-  
face to this memory space is via a group of registers mapped  
in the SFR space. A group of four data registers (EDATA1-4)  
are used to hold the 4-byte page being accessed. EADRL is used  
to hold the 8-bit address of the page being accessed. Finally,  
ECON is an 8-bit control register that may be written with  
one of five Flash/EE memory access commands to trigger various  
read, write, erase and verify functions. These register can be  
summarized as follows:  
The Serial Download protocol is detailed in a MicroConverter  
Applications Note uC004 available from the ADI MicroConverter  
Website at www.analog.com/micronverter.  
ECON:  
SFR Address: B9H  
Function:  
Controls access to 640 Bytes  
Flash/EE Data Space.  
00H  
Default:  
EADRL:  
SFR Address: C6H  
Function:  
Holds the Flash/EE Data  
Page Address. 0 through 9F Hex  
00H  
Default:  
EDATA 1–4:  
SFR Address: BCH to BFH respectively  
Function:  
Holds Flash/EE Data  
memory page write or page  
read data bytes.  
PULL PSEN LOW DURING RESET TO  
CONFIGURE THE ADuC812 FOR  
SERIAL DOWNLOAD MODE  
ADuC812  
Default :  
EDATA1–4 –> 00H  
PSEN  
1k⍀  
A block diagram of the SFR registered interface to the Data  
Flash/EE Memory array is shown in Figure 17.  
Figure 15. Flash/EE Memory Serial Download Mode  
Programming  
FUNCTION:  
HOLDS THE 8-BIT PAGE  
ADDRESS POINTER  
FUNCTION:  
HOLDS THE 4-BYTE  
PAGE WORD  
Parallel Programming  
9FH  
BYTE 2  
BYTE 4  
BYTE 3  
BYTE 1  
The parallel programming mode is fully compatible with  
conventional third party Flash or EEPROM device programmers.  
In this mode Ports P0, P1 and P2 operate as the external data  
and address bus interface, ALE operates as the Write Enable  
strobe and Port P3 is used as a general configuration port that  
configures the device for various program and erase operations  
during parallel programming.  
EADRL  
EDATA1 (BYTE 1)  
EDATA2 (BYTE 2)  
EDATA3 (BYTE 3)  
EDATA4 (BYTE 4)  
00H  
BYTE 1 BYTE 2 BYTE 3 BYTE 4  
ECON COMMAND  
INTERPRETER LOGIC  
The high voltage (12 V) supply required for Flash programming  
is generated using on-chip charge pumps to supply the high  
voltage program lines.  
FUNCTION:  
INTERPRETS THE FLASH  
COMMAND WORD  
FUNCTION:  
HOLDS COMMAND WORD  
ECON  
The complete parallel programming specification is available  
on the MicroConverter home page at www.analog.com/  
microconverter.  
Figure 17. User Flash/EE Memory Control and  
Configuration  
REV. B  
–19–  
ADuC812  
ECON—Flash/EE Memory Control SFR  
Using the Flash/EE Memory Interface  
This SFR acts as a command interpreter and may be written  
with one of five command modes to enable various read, pro-  
gram and erase cycles as detailed in Table VII:  
As with all Flash/EE memory architectures, the array can be pro-  
grammed in system at a byte level, although it must be erased  
first, the erasure being performed in page blocks (4-byte pages  
in this case).  
Table VII. ECON–Flash/EE Memory Control Register  
Command Modes  
A typical access to the Flash/EE array will involve setting up the  
page address to be accessed in the EADRL SFR, configuring the  
EDATA1-4 with data to be programmed to the array (the  
EDATA SFRs will not be written for read accesses) and finally  
writing the ECON command word which initiates one of the six  
modes shown in Table VII. It should be noted that a given  
mode of operation is initiated as soon as the command word is  
written to the ECON SFR. The core microcontroller operation  
on the ADuC812 is idled until the requested Program/Read or  
Erase mode is completed.  
Command Byte Command Mode  
01H  
READ COMMAND  
Results in four bytes being read into  
EDATA 1–4 from memory page address  
contained in EADRL.  
02H  
PROGRAM COMMAND  
Results in four bytes (EDATA 1–4) being  
written to memory page address in EADRL.  
This write command assumes the designated  
“write” page has been pre-erased.  
RESERVED FOR INTERNAL USE  
03H should not be written to the  
ECON SFR.  
In practice, this means that even though the Flash/EE memory  
mode of operation is typically initiated with a two-machine cycle  
MOV instruction (to write to the ECON SFR), the next instruction  
will not be executed until the Flash/EE operation is complete  
(250 µs or 20 ms later). This means that the core will not respond  
to Interrupt requests until the Flash/EE operation is complete,  
although the core peripheral functions like Counter/Timers will  
continue to count and time as configured throughout this pseudo-  
idle period.  
03H  
04H  
VERIFY COMMAND  
Allows the user to verify if data in EDATA  
1–4 is contained in page address designated  
by EADRL.  
Erase-All  
A subsequent read of the ECON SFR will  
result in a “zero” being read if the verifi-  
cation is valid, a nonzero value will be  
read to indicate an invalid verification.  
ERASE COMMAND  
Results in an erase of the 4-byte page  
designated in EADRL.  
Although the 640-byte User Flash/EE array is shipped from the  
factory pre-erased, i.e., Byte locations set to FFH, it is nonethe-  
less good programming practice to include an erase-all routine  
as part of any configuration/setup code running on the ADuC812.  
An “ERASE-ALL” command consists of writing “06H” to the  
ECON SFR, which initiates an erase of all 640 byte locations in  
the Flash/EE array. This command coded in 8051 assembly  
would appear as:  
05H  
06H  
ERASE-ALL COMMAND  
Results in erase of the full Flash/EE data  
memory 160-page (640 bytes) array.  
MOV ECON, #06H  
; Erase all Command  
; 20 ms Duration  
07H to FFH  
RESERVED COMMANDS  
Commands reserved for future use.  
Program a Byte  
In general terms, a byte in the Flash/EE array can only be pro-  
grammed if it has previously been erased. To be more specific, a  
byte can only be programmed if it already holds the value FFH.  
Because of the Flash/EE architecture, this erasure must happen  
at a page level; therefore, a minimum of four bytes (1 page) will  
be erased when an erase command is initiated. A more specific  
example of the Program-Byte process is shown below. In this  
example the user writes F3H into the second byte on Page  
03H of the Flash/EE Data Memory space while preserving the  
other three bytes already in this page. As the user is only required  
to modify one of the page bytes, the full page must be first read so  
that this page can then be erased without the existing data being  
lost. This example, coded in 8051 assembly, would appear as:  
Flash/EE Memory Timing  
The typical program/erase times for the Flash/EE Data  
Memory are:  
Erase Full Array (640 Bytes) – 20 ms  
Erase Single Page (4 Bytes) – 20 ms  
Program Page (4 Bytes)  
– 250 µs  
Read Page (4 Bytes)  
– Within Single Instruction Cycle  
Flash/EE erase and program timing is derived from the master  
clock. When using a master clock frequency of 11.0592 MHz it  
is not necessary to write to the ETIM registers at all. However,  
when operating at other master clock frequencies (fCLK), you  
must change the values of ETIM1 and ETIM2 to avoid degrad-  
ing data Flash/EE endurance and retention. ETIM1 and ETIM2  
form a 16-bit word, ETIM2 being the high byte and ETIM1 the  
low byte. The value of this 16-bit word must be set as follows to  
ensure optimum data Flash/EE endurance and retention.  
MOV EADRL, #03H  
MOV ECON, #01H  
; Set Page Address Pointer  
; Read Page  
MOV EDATA2, #0F3H ; Write New Byte  
MOV ECON, #05H  
MOV ECON, #02H  
; Erase Page  
; Write Page (Program  
Flash/EE)  
ETIM2, ETIM1 = 100 µs × fCLK  
ETIM3 should always remain at its default value of 201 dec/C9 hex.  
–20–  
REV. B  
ADuC812  
USER INTERFACE TO OTHER ON-CHIP ADuC812  
PERIPHERALS  
The following section gives a brief overview of the various  
peripherals also available on-chip. A summary of the SFRs used to  
control and configure these peripherals is also given.  
Each can operate in 12-bit or 8-bit mode. Both DACs share a  
control register, DACCON, and four data registers, DAC1H/L,  
DAC0H/L. It should be noted that in 12-bit asynchronous mode,  
the DAC voltage output will be updated as soon as the DACL  
data SFR has been written; therefore, the DAC data registers  
should be updated as DACH first, followed by DACL.  
DAC  
The ADuC812 incorporates two 12-bit, voltage output DACs  
on-chip. Each has a rail-to-rail voltage output buffer capable  
of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to  
DACCON  
SFR Address  
Power-On Default Value  
Bit Addressable  
DAC Control Register  
FDH  
04H  
No  
VREF (the internal bandgap 2.5 V reference) and 0 V to AVDD  
.
MODE  
RNG1  
RNG0  
CLR1  
CLR0  
SYNC  
PD1  
PD0  
Table VIII. DACCON SFR Bit Designations  
Bit  
Name  
Description  
7
MODE  
RNG1  
RNG0  
CLR1  
CLR0  
SYNC  
The DAC MODE bit sets the overriding operating mode for both DACs.  
Set to “1” = 8-Bit Mode (Write 8 Bits to DACxL SFR).  
Set to “0”= 12-Bit Mode.  
6
5
4
3
2
DAC1 Range Select Bit.  
Set to “1” = DAC1 Range 0–VDD  
.
Set to “0” = DAC1 Range 0–VREF  
.
DAC0 Range Select Bit.  
Set to “1” = DAC0 Range 0–VDD.  
Set to “0” = DAC0 Range 0–VREF.  
DAC1 Clear Bit.  
Set to “0” = DAC1 Output Forced to 0 V.  
Set to “1” = DAC1 Output Normal.  
DAC0 Clear Bit.  
Set to “0” = DAC1 Output Forced to 0 V.  
Set to “1” = DAC1 Output Normal.  
DAC0/1 Update Synchronization Bit.  
When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can  
simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both  
DACs will then update simultaneously when the SYNC bit is set to “1.”  
DAC1 Power-Down Bit.  
Set to “1” = Power-On DAC1.  
Set to “0” = Power-Off DAC1.  
1
0
PD1  
PD0  
DAC0 Power-Down Bit.  
Set to “1” = Power-On DAC0.  
Set to “0” = Power-Off DAC0.  
DACxH/L  
DAC Data Registers  
Function  
SFR Address  
DAC Data Registers, written by user to update the DAC output.  
DAC0L (DAC0 Data Low Byte) –>F9H; DAC1L (DAC1 Data Low Byte)->FBH  
DAC0H (DAC0 Data High Byte)–>FAH; DAC1H(DAC1 Data High Byte)->FCH  
Power-On Default Value  
Bit Addressable  
00H  
No  
–>All four Registers  
–>All four Registers  
The 12-bit DAC data should be written into DACxH/L right-justified such that DACL contains the lower eight bits, and the lower  
nibble of DACH contains the upper four bits.  
REV. B  
–21–  
ADuC812  
V
Using the D/A Converter  
DD  
The on-chip D/A converter architecture consists of a resistor  
string DAC followed by an output buffer amplifier, the func-  
tional equivalent of which is illustrated in Figure 18. Details of  
the actual DAC architecture can be found in U.S. Patent Num-  
ber 5969657 (www.uspto.gov). Features of this architecture  
include inherent guaranteed monotonicity and excellent differ-  
ential linearity.  
V
– 50mV  
DD  
V
– 100mV  
DD  
AV  
DD  
ADuC812  
100mV  
50mV  
0mV  
R
V
REF  
OUTPUT  
BUFFER  
R
R
000 HEX  
FFF HEX  
8
Figure 19. Endpoint Nonlinearities Due to Amplifier  
Saturation  
HIGH-Z  
DISABLE  
R
R
The endpoint nonlinearities conceptually illustrated in Figure 19  
get worse as a function of output loading. Most of the ADuC812’s  
data sheet specifications assume a 10 kΩ resistive load to ground  
at the DAC output. As the output is forced to source or sink  
more current, the nonlinear regions at the top or bottom  
(respectively) of Figure 19 become larger. With larger current  
demands, this can significantly limit output voltage swing.  
Figure 20 and Figure 21 illustrate this behavior. It should be noted  
that the upper trace in each of these figures is only valid for an  
output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC  
loading will not cause high-side voltage drops as long as the  
reference voltage remains below the upper trace in the correspond-  
ing figure. For example, if AVDD = 3 V and VREF = 2.5 V, the  
high-side voltage will not be affected by loads less than 5 mA.  
But somewhere around 7 mA the upper curve in Figure 21 drops  
below 2.5 V (VREF) indicating that at these higher currents the  
(FROM MCU)  
Figure 18. Resistor String DAC Functional Equivalent  
As illustrated in Figure 18, the reference source for each DAC is  
user selectable in software. It can be either AVDD or VREF. In  
0-to-AVDD mode, the DAC output transfer function spans from  
0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the  
DAC output transfer function spans from 0 V to the internal  
V
REF or if an external reference is applied the voltage at the VREF  
pin. The DAC output buffer amplifier features a true rail-to-rail  
output stage implementation. This means that, unloaded, each  
output is capable of swinging to within less than 100 mV of both  
AVDD and ground. Moreover, the DAC’s linearity specification  
(when driving a 10 kΩ resistive load to ground) is guaranteed  
through the full transfer function except codes 0 to 48, and, in  
0-to-AVDD mode only, codes 3995 to 4095. Linearity degrada-  
tion near ground and VDD is caused by saturation of the output  
amplifier, and a general representation of its effects (neglecting  
offset and gain error) is illustrated in Figure 19. The dotted line  
in Figure 19 indicates the ideal transfer function, and the solid  
line represents what the transfer function might look like with  
endpoint nonlinearities due to saturation of the output amplifier.  
Note that Figure 19 represents a transfer function in 0-to-VDD  
mode only. In 0-to-VREF mode (with VREF < VDD) the lower  
nonlinearity would be similar, but the upper portion of the  
transfer function would follow the “ideal” line right to the end  
(VREF in this case, not VDD), showing no signs of endpoint lin-  
earity errors.  
output will not be capable of reaching VREF  
.
5
DAC LOADED WITH 0FFF HEX  
4
3
2
1
DAC LOADED WITH 0000 HEX  
0
0
5
10  
15  
SOURCE/SINK CURRENT – mA  
Figure 20. Source and Sink Current Capability with  
VREF = VDD = 5 V  
–22–  
REV. B  
ADuC812  
the DAC outputs will remain at ground potential whenever the  
DAC is disabled. However, each DAC output will still spike  
briefly when you first apply power to the chip, and again when  
each DAC is first enabled in software. Typical scope shots of  
these spikes are given in Figure 23 and Figure 24 respectively.  
3
2
1
0
200␮s/DIV  
AV – 2V/DIV  
DD  
0
5
10  
15  
SOURCE/SINK CURRENT – mA  
Figure 21. Source and Sink Current Capability with  
VREF = VDD = 3 V  
DAC OUT – 500mv/DIV  
To drive significant loads with the DAC outputs, external buff-  
ering may be required, as illustrated in Figure 22.  
Figure 23. DAC Output Spike at Chip Power-Up  
5␮s/DIV, 1V/DIV  
ADuC812  
9
10  
Figure 22. Buffering the DAC Outputs  
The DAC output buffer also features a high-impedance disable  
function. In the chip’s default power-on state, both DACs are  
disabled, and their outputs are in a high-impedance state (or  
“three-state”) where they remain inactive until enabled in software.  
This means that if a zero output is desired during power-up or  
power-down transient conditions, then a pull-down resistor must  
be added to each DAC output. Assuming this resistor is in place,  
Figure 24. DAC Output Spike at DAC Enable  
REV. B  
–23–  
ADuC812  
WATCHDOG TIMER  
The watchdog timer itself is a 16-bit counter. The watchdog  
timeout interval can be adjusted via the PRE2–0 bits in  
WDCON. Full Control and Status of the watchdog timer  
function can be controlled via the watchdog timer control  
SFR (WDCON).  
The purpose of the watchdog timer is to generate a device reset  
within a reasonable amount of time if the ADuC812 enters  
an erroneous state, possibly due to a programming error.  
The Watchdog function can be disabled by clearing the WDE  
(Watchdog Enable) bit in the Watchdog Control (WDCON)  
SFR. When enabled, the watchdog circuit will generate a system  
reset if the user program fails to set the watchdog timer refresh  
bits (WDR1, WDR2) within a predetermined amount of time  
(see PRE2–0 bits in WDCON).  
WDCON  
Watchdog Timer Control Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
C0H  
00H  
Yes  
PRE2  
PRE1  
PRE0  
—
WDR1  
WDR2  
WDS  
WDE  
Table IX. WDCON SFR Bit Designations  
Bit  
Name  
Description  
7
6
5
PRE2  
PRE1  
PRE0  
Watchdog Timer Prescale Bits.  
PRE2  
PRE1  
PRE0  
Timeout Period (ms)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16  
32  
64  
128  
256  
512  
1024  
2048  
4
3
2
1
—
Not Used.  
WDR1  
WDR2  
WDS  
Watchdog timer refresh bits, set sequentially to refresh the watchdog.  
Watchdog Status Bit.  
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.  
Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.  
Watchdog Enable Bit.  
1
WDE  
Set by user to enable the watchdog and clear its counters.  
Example  
To set up the watchdog timer for a timeout period  
of 2048 ms the following code would be used.  
MOV  
WDCON,#0E0h ;2.048 second  
;timeout period  
SETB WDE  
;enable watchdog timer  
In order to prevent the watchdog timer timing out the timer  
refresh bits need to be set before 2.048 seconds has elapsed.  
SETB WDR1  
SETB WDR2  
;refresh watchdog timer..  
; ..bits must be set in this  
;order  
–24–  
REV. B  
ADuC812  
POWER SUPPLY MONITOR  
the core using the PSMI bit in the PSMCON SFR. This bit will  
not be cleared until the failing power supply has returned  
above the trip point for at least 256 ms. This is to ensure that  
the power supply has fully settled before the bit is cleared. This  
monitor function allows the user to save working registers to avoid  
possible data loss due to the low supply condition, and also ensures  
that normal code execution will not resume until a safe supply  
level has been well established. The supply monitor is also  
protected against spurious glitches triggering the interrupt circuit.  
As its name suggests, the Power Supply Monitor, once enabled,  
monitors both supplies (AVDD and DVDD) on the ADuC812. It  
will indicate when either power supply drops below one of five  
user-selectable voltage trip points from 2.63 V to 4.63 V. For  
correct operation of the Power Supply Monitor function, AVDD  
must be equal to or greater than 2.7 V. The Power Supply  
Monitor function is controlled via the PSMCON SFR. If  
enabled via the IE2 SFR, the Power Supply Monitor will interrupt  
PSMCON  
Power Supply Monitor  
Control Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
DFH  
DCH  
No  
—
CMP  
PSMI  
TP2  
TP1  
TP0  
PSF  
PSMEN  
Table X. PSMCON SFR Bit Designations  
Bit  
Name  
Description  
7
6
—
CMP  
Not Used.  
AVDD and DVDD Comparator Bit.  
This is a read-only bit and directly reflects the state of the AVDD and DVDD comparators.  
Read “1” indicates that both AVDD and DVDD supply are above its selected trip point.  
Read “0” indicates that either AVDD or DVDD supply are below its selected trip point.  
Power Supply Monitor Interrupt Bit.  
5
PSMI  
This bit will be set high by the MicroConverter if CMP is low, indicating low analog  
or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD  
and/or CMP return (and remain) high, a 256 ms counter is started. When this counter  
times out, the PSMI interrupt is cleared. PSMI can also be written by the user. How  
ever, if either comparator output is low, it is not possible for the user to clear PSMI.  
VDD Trip Point Selection Bits.  
4
3
2
TP2  
TP1  
TP0  
These bits select the AVDD and DVDD trip-point voltage as follows:  
TP2  
TP1  
TP0  
Selected DVDD Trip Point (V)  
0
0
0
0
0
0
1
1
0
0
1
0
1
0
4.63  
4.37  
3.08  
2.93  
2.63  
1
1
0
PSF  
AVDD/DVDD fault indicator  
Read “1” indicates that the AVDD supply caused the fault condition.  
Read “0” indicates that the DVDD supply caused the fault condition.  
Power Supply Monitor Enable Bit.  
PSMEN  
Set to “1” by the user to enable the Power Supply Monitor Circuit.  
Cleared to “0” by the user to disable the Power Supply Monitor Circuit.  
Example  
ORG  
0043h  
;PSM ISR  
To configure the PSM for a trippoint of 4.37 V, the following  
code would be used  
CHECK:MOV  
A,PSMCON  
;PSMCON.5 is the  
;PSM interrupt  
;bit..  
;..it is cleared  
;only when Vdd  
;has remained  
;above the trip  
;point for 256ms  
;or more.  
MOV  
PSMCON,#005h  
;enable PSM with  
;4.37V threshold  
;enable interrupts  
;enable PSM  
JB  
ACC.5,CHECK  
SETB  
MOV  
EA  
IE2,#002h  
;interrupt  
If the supply voltage falls below this level, the PC would vector  
to the ISR.  
RETI  
; return only when "all's well"  
REV. B  
–25–  
ADuC812  
SERIAL PERIPHERAL INTERFACE  
SCLOCK pin is configured as an output in master mode and as  
an input in slave mode. In master mode the bit-rate, polarity  
and phase of the clock are controlled by the CPOL, CPHA,  
SPR0 and SPR1 bits in the SPICON SFR (see Table XII).  
In slave mode the SPICON register will have to be configured  
with the phase and polarity (CPHA and CPOL) of the expected  
input clock. In both master and slave mode the data is transmitted  
on one edge of the SCLOCK signal and sampled on the other. It  
is important therefore that the CPHA and CPOL are configured the  
same for the master and slave devices.  
The ADuC812 integrates a complete hardware Serial Peripheral  
Interface (SPI) on-chip. SPI is an industry standard synchronous  
serial interface that allows eight bits of data to be synchronously  
transmitted and received simultaneously, i.e., full duplex.  
It should be noted that the SPI pins are shared with the I2C  
interface and therefore the user can only enable one or the other  
interface at any given time (see SPE in SPICON below).  
The SPI Port can be configured for Master or Slave operation and  
typically consists of four pins, namely:  
MISO (Master In, Slave Out Data I/O Pin), Pin #19  
The MISO (master in slave out) pin is configured as an input line  
in master mode and an output line in slave mode. The MISO  
line on the master (data in) should be connected to the MISO  
line in the slave device (data out). The data is transferred as  
byte wide (8-bit) serial data, MSB first.  
SS (Slave Select Input Pin), Pin #12  
The Slave Select (SS) input pin is shared with the ADC5 input.  
In order to configure this pin as a digital input the bit must be  
cleared, e.g., CLR P1.5.  
This line is active low. Data is only received or transmitted in  
slave mode when the SS pin is low, allowing the ADuC812 to  
be used in single master, multislave SPI configurations. If  
CPHA = 1 then the SS input may be permanently pulled low.  
With CPHA = 0 then the SS input must be driven low before  
the first bit in a byte wide transmission or reception and return  
high again after the last bit in that byte wide transmission or  
reception. In SPI Slave Mode, the logic level on the external SS  
pin (Pin #13), can be read via the SPR0 bit in the SPICON SFR.  
MOSI (Master Out, Slave In Pin), Pin #27  
The MOSI (master out slave in) pin is configured as an output line  
in master mode and an input line in slave mode. The MOSI  
line on the master (data out) should be connected to the MOSI  
line in the slave device (data in). The data is transferred as byte  
wide (8-bit) serial data, MSB first.  
SCLOCK (Serial Clock I/O Pin), Pin #26  
The master serial clock (SCLOCK) is used to synchronize  
the data being transmitted and received through the MOSI  
and MISO data lines. A single data bit is transmitted and  
received in each SCLOCK period. Therefore, a byte is  
transmitted/received after eight SCLOCK periods. The  
The following SFR registers are used to control the SPI interface.  
SPICON  
SPI Control Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
F8H  
OOH  
Yes  
ISPI  
WCOL  
SPE  
SPIM  
CPOL  
CPHA  
SPR1  
SPR0  
Table XI. SPICON SFR Bit Designations  
Bit  
Name  
Description  
7
ISPI  
SPI Interrupt Bit.  
Set by MicroConverter at the end of each SPI transfer.  
Cleared directly by user code or indirectly by reading the SPIDAT SFR  
Write Collision Error Bit.  
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.  
Cleared by user code.  
SPI Interface Enable Bit.  
6
5
4
3
2
WCOL  
SPE  
Set by user to enable the SPI interface.  
Cleared by user to enable the I2C interface.  
SPI Master/Slave Mode Select Bit.  
SPIM  
CPOL  
CPHA  
Set by user to enable Master Mode operation (SCLOCK is an output).  
Cleared by user to enable Slave Mode operation (SCLOCK is an input).  
Clock Polarity Select Bit.  
Set by user if SCLOCK idles high.  
Cleared by user if SCLOCK idles low.  
Clock Phase Select Bit.  
Set by user if leading SCLOCK edge is to transmit data.  
Cleared by user if trailing SCLOCK edge is to transmit data.  
–26–  
REV. B  
ADuC812  
Table XII. SPICON SFR Bit Designations (continued)  
Description  
Bit  
Name  
1
0
SPR1  
SPR0  
SPI Bit-Rate Select Bits.  
These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:  
SPR1  
SPR0  
Selected Bit Rate  
fOSC/4  
f
fOSC/32  
fosc/64  
0
0
1
1
0
1
0
1
OSC/8  
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin #12)  
can be read via the SPR0 bit.  
NOTE  
The CPOL and CPHA bits should both contain the same values for master and slave devices.  
SPIDAT  
SPI Data Register  
Function  
The SPIDAT SFR is written by the  
user to transmit data over the SPI  
interface or read by user code to  
read data just received by the SPI  
interface.  
F7H  
SFR Address  
Power-On Default Value  
Bit Addressable  
00H  
No  
SPI Interface—Master Mode  
Using the SPI Interface  
In master mode, the SCLOCK pin is always an output and gener-  
ates a burst of eight clocks whenever user code writes to the  
SPIDAT register. The SCLOCK bit rate is determined by  
SPR0 and SPR1 in SPICON. It should also be noted that the  
SS pin is not used in master mode. If the ADuC812 needs to  
assert the SS pin on an external slave device, a Port digital output  
pin should be used.  
Depending on the configuration of the bits in the SPICON SFR  
shown in Table XII, the ADuC812 SPI interface will transmit  
or receive data in a number of possible modes. Figure 26 shows  
all possible ADuC812 SPI configurations and the timing rela-  
tionships and synchronization between the signals involved.  
Also shown in this figure is the SPI interrupt bit (ISPI) and how  
it is triggered at the end of each byte-wide communication.  
In master mode a byte transmission or reception is initiated  
by a write to SPIDAT. Eight clock periods are generated via the  
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.  
With each SCLOCK period a data bit is also sampled via MISO.  
After eight clocks, the transmitted byte will have been completely  
transmitted and the input byte will be waiting in the input shift  
register. The ISPI flag will be set automatically and an interrupt  
will occur if enabled. The value in the shift register will be latched  
into SPIDAT.  
SCLOCK  
(CPOL = 1)  
SCLOCK  
(CPOL = 0)  
SS  
SAMPLE INPUT  
DATA OUTPUT  
?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB  
SPI Interface—Slave Mode  
In slave mode the SCLOCK is an input. The SS pin must  
also be driven low externally during the byte communication.  
ISPI FLAG  
SAMPLE INPUT  
Transmission is also initiated by a write to SPIDAT. In slave  
mode, a data bit is transmitted via MISO and a data bit is received  
via MOSI through each input SCLOCK period. After eight clocks,  
the transmitted byte will have been completely transmitted and the  
input byte will be waiting in the input shift register. The ISPI flag  
will be set automatically and an interrupt will occur if enabled.  
The value in the shift register will be latched into SPIDAT only  
when the transmission/reception of a byte has been completed.  
The end of transmission occurs after the eighth clock has been  
received if CPHA = 1, or when SS returns high if CPHA = 0.  
DATA OUTPUT  
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB  
?
ISPI FLAG  
Figure 25. SPI Timing, All Modes  
REV. B  
–27–  
ADuC812  
I2C-COMPATIBLE INTERFACE  
previously). An Application Note describing the operation of this  
interface as implemented is available from the MicroConverter  
Website at www.analog.com/microconverter. This interface  
can be configured as a Software Master or Hardware Slave,  
and uses two pins in the interface.  
The ADuC812 supports a 2-wire serial interface mode which is  
I2C compatible. The I2C-compatible interface shares its pins with  
the on-chip SPI interface and therefore the user can only enable  
one or the other interface at any given time (see SPE in SPICON  
SDATA (Pin 27)  
SCLOCK (Pin 26)  
Serial data I/O Pin  
Serial Clock  
Three SFRs are used to control the I2C-compatible interface.  
These are described below:  
I2CCON:  
SFR Address  
Power-On Default Value  
Bit Addressable  
I2C Control Register  
E8H  
00H  
Yes  
MDO  
MDE  
MCO  
MDI  
I2CM  
I2CRS  
I2CTX  
I2CI  
Table XIII. I2CCON SFR Bit Designations  
Bit  
Name  
Description  
7
MDO  
MDE  
MCO  
MDI  
I2C Software Master Data Output Bit (MASTER MODE ONLY).  
This data bit is used to implement a master I2C transmitter interface in software. Data written to this  
bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set.  
I2C Software Master Data Output Enable Bit (MASTER MODE ONLY).  
Set by user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin  
as an input (Rx).  
6
5
4
3
2
1
0
I2C Software Master Clock Output Bit (MASTER MODE ONLY).  
This data bit is used to implement a master I2C transmitter interface in software. Data written to  
this bit will be outputted on the SCLOCK pin.  
I2C Software Master Data Input Bit (MASTER MODE ONLY).  
This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA  
pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) = “0.”  
I2C Master/Slave Mode Bit.  
I2CM  
I2CRS  
I2CTX  
I2CI  
Set by user to enable I2C software master mode.  
Cleared by user to enable I2C hardware slave mode.  
I2C Reset Bit (SLAVE MODE ONLY).  
Set by user to reset the I2C interface.  
Cleared by user code for normal I2C operation.  
I2C Direction Transfer Bit (SLAVE MODE ONLY).  
Set by the MicroConverter if the interface is transmitting.  
Cleared by the MicroConverter if the interface is receiving.  
I2C Interrupt Bit (SLAVE MODE ONLY).  
Set by the MicroConverter after a byte has been transmitted or received.  
Cleared by User Software.  
I2C Address Register  
Holds the I2C peripheral address  
for the part. It may be overwritten  
by user code. Technical Note µC001  
at www.analog.com/microconverter  
describes the format of the I2C  
standard 7-bit address in detail.  
9BH  
I2CDAT  
Function  
I2C Data Register  
I2CADD  
Function  
The I2CDAT SFR is written by  
the user to transmit data over  
the I2C interface or read by user  
code to read data just received by  
the I2C interface. User software  
should only access I2CDAT once  
per interrupt cycle.  
SFR Address  
Power-On Default Value  
Bit Addressable  
55H  
No  
SFR Address  
Power-On Default Value  
Bit Addressable  
9AH  
00H  
No  
–28–  
REV. B  
ADuC812  
8051-COMPATIBLE ON-CHIP PERIPHERALS  
Port 3 is a bidirectional port with internal pull-ups directly  
controlled via the P3 SFR (SFR address = B0 hex). Port 3 pins  
that have 1s written to them are pulled high by the internal pull-  
ups and in that state they can be used as inputs. As inputs, Port  
3 pins being pulled externally low will source current because of  
the internal pull-ups. Port 3 pins also have various secondary  
functions described in Table XV.  
This section gives a brief overview of the various secondary  
peripheral circuits that are also available to the user on-chip.  
These remaining functions are fully 8051-compatible and are  
controlled via standard 8051 SFR bit definitions.  
Parallel I/O Ports 0–3  
The ADuC812 uses four input/output ports to exchange data with  
external devices. In addition to performing general-purpose I/O,  
some ports are capable of external memory operations; others are  
multiplexed with an alternate function for the peripheral features  
on the device. In general, when a peripheral is enabled, that pin  
may not be used as a general purpose I/O pin.  
Table XV. Port 3, Alternate Pin Functions  
Pin  
Alternate Function  
P3.0  
RXD (UART Input Pin)  
(or Serial Data I/O in Mode 0)  
TXD (UART Output Pin)  
Port 0 is an 8-bit open drain bidirectional I/O port that is directly  
controlled via the P0 SFR (SFR address = 80 hex). Port 0 pins  
that have 1s written to them via the Port 0 SFR will be configured  
as open drain and will therefore float. In that state, Port 0 pins  
can be used as high impedance inputs. An external pull-up  
resistor will be required on Port 0 outputs to force a valid logic  
high level externally. Port 0 is also the multiplexed low-order  
address and data bus during accesses to external program or data  
memory. In this application it uses strong internal pull-ups when  
emitting 1s.  
P3.1  
(or Serial Clock Output in Mode 0)  
INT0 (External Interrupt 0)  
INT1 (External Interrupt 1)  
T0 (Timer/Counter 0 External Input)  
T1 (Timer/Counter 1 External Input)  
WR (External Data Memory Write Strobe)  
RD (External Data Memory Read Strobe)  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
The alternate functions of P1.0, P1.1, P1.5 and Port 3 pins can  
only be activated if the corresponding bit latch in the P1 and  
P3 SFRs contains a 1. Otherwise, the port pin is stuck at 0.  
Port 1 is also an 8-bit port directly controlled via the P1 SFR  
(SFR address = 90 hex). Port 1 ia an input only port. Port 1  
digital output capability is not supported on this device. Port 1  
pins can be configured as digital inputs or analog inputs.  
Timers/Counters  
The ADuC812 has three 16-bit Timer/Counters: Timer 0,  
Timer 1, and Timer 2. The Timer/Counter hardware has been  
included on-chip to relieve the processor core of the overhead  
inherent in implementing timer/counter functionality in soft-  
ware. Each Timer/Counter consists of two 8-bit registers THx and  
TLx (x = 0, 1 and 2). All three can be configured to operate  
either as timers or event counters.  
By (power-on) default these pins are configured as Analog Inputs,  
i.e., “1” written in the corresponding Port 1 register bit. To  
configure any of these pins as digital inputs, the user should  
write a “0” to these port bits to configure the corresponding pin  
as a high impedance digital input.  
These pins also have various secondary functions described in  
Table XIV.  
In “Timer” function, the TLx register is incremented every  
machine cycle. Thus one can think of it as counting machine  
cycles. Since a machine cycle consists of 12 core clock periods,  
the maximum count rate is 1/12 of the core clock frequency.  
Table XIV. Port 1, Alternate Pin Functions  
Pin  
Alternate Function  
In “Counter” function, the TLx register is incremented by a 1-to-0  
transition at its corresponding external input pin, T0, T1, or T2.  
In this function, the external input is sampled during S5P2 of  
every machine cycle. When the samples show a high in one cycle  
and a low in the next cycle, the count is incremented. The new  
count value appears in the register during S3P1 of the cycle follow-  
ing the one in which the transition was detected. Since it takes two  
machine cycles (24 core clock periods) to recognize a 1-to-0 transi-  
tion, the maximum count rate is 1/24 of the core clock frequency.  
There are no restrictions on the duty cycle of the external  
input signal, but to ensure that a given level is sampled at  
least once before it changes, it must be held for a minimum of  
one full machine cycle.  
P1.0  
P1.1  
P1.5  
T2 (Timer/Counter 2 External Input)  
T2EX (Timer/Counter 2 Capture/Reload Trigger)  
SS (Slave Select for the SPI interface)  
Port 2 is a bidirectional port with internal pull-up resistors directly  
controlled via the P2 SFR (SFR address = A0 hex). Port 2 pins  
that have 1s written to them are pulled high by the internal pull-up  
resistors and, in that state, they can be used as inputs. As inputs,  
Port 2 pins being pulled externally low will source current because  
of the internal pull-up resistors. Port 2 emits the high order  
address bytes during fetches from external program memory  
and middle and high order address bytes during accesses to the  
24-bit external data memory space.  
REV. B  
–29–  
ADuC812  
User configuration and control of all Timer operating modes is  
achieved via three SFRs, namely:  
TMOD  
Timer/Counter 0 and 1 Mode  
Register  
89H  
SFR Address  
Power-On Default Value 00H  
Bit Addressable  
TMOD, TCON:  
Control and configuration for  
Timers 0 and 1.  
No  
T2CON:  
Control and configuration for  
Timer 2.  
Gate  
C/T  
M1  
M0  
Gate  
C/T  
M1  
M0  
Table XVI. TMOD SFR Bit Designations  
Bit  
Name  
Description  
7
Gate  
Timer 1 Gating Control.  
Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set.  
Cleared by software to enable timer 1 whenever TR1 control bit is set.  
Timer 1 Timer or Counter Select Bit.  
6
C/T  
Set by software to select counter operation (input from T1 pin).  
Cleared by software to select timer operation (input from internal system clock).  
Timer 1 Mode Select Bit 1 (Used with M0 Bit).  
5
4
M1  
M0  
Timer 1 Mode Select Bit 0.  
M1  
0
0
M0  
0
1
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.  
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.  
8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be  
reloaded into TL1 each time it overflows.  
1
0
1
1
Timer/Counter 1 Stopped.  
3
2
Gate  
C/T  
Timer 0 Gating Control.  
Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set.  
Cleared by software to enable Timer 0 whenever TR0 control bit is set.  
Timer 0 Timer or Counter Select Bit.  
Set by software to select counter operation (input from T0 pin).  
Cleared by software to select timer operation (input from internal system clock).  
Timer 0 Mode Select Bit 1.  
1
0
M1  
M0  
Timer 0 Mode Select Bit 0.  
M1  
0
0
M0  
0
1
TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler.  
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no  
prescaler  
1
1
0
1
8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to  
be reloaded into TL0 each time it overflows.  
TL0 is an 8-bit timer/counter controlled by the standard timer 0 control  
bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.  
–30–  
REV. B  
ADuC812  
TCON: Timer/Counter 0 and 1 Control Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
88H  
00H  
Yes  
TF1  
TR1  
TF0  
TR0  
IE11  
IT11  
IE01  
IT01  
NOTE  
1These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.  
Table XVII. TCON SFR Bit Designations  
Bit  
Name  
Description  
7
TF1  
Timer 1 Overflow Flag.  
Set by hardware on a timer/counter 1 overflow.  
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.  
Timer 1 Run Control Bit.  
Set by user to turn on timer/counter 1.  
Cleared by user to turn off timer/counter 1.  
Timer 0 Overflow Flag.  
Set by hardware on a timer/counter 0 overflow.  
Cleared by hardware when the PC vectors to the interrupt service routine.  
Timer 0 Run Control Bit.  
6
5
4
3
TR1  
TF0  
TR0  
IE1  
Set by user to turn on timer/counter 0.  
Cleared by user to turn off timer/counter 0.  
External Interrupt 1 (INT1) Flag.  
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1,  
depending on bit IT1 state.  
Cleared by hardware when the when the PC vectors to the interrupt service routine only if the  
interrupt was transition-activated. If level-activated, the external requesting source controls the  
request flag, rather than the on-chip hardware.  
2
1
IT1  
IE0  
External Interrupt 1 (IE1) Trigger Type.  
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).  
Cleared by software to specify level-sensitive detection (i.e., zero level).  
External Interrupt 0 (INT0) Flag.  
Set by hardware by a falling edge or zero level being applied to external interrupt pin  INT0,  
depending on bit IT0 state.  
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt  
was transition-activated. If level-activated, the external requesting source controls the request  
flag, rather than the on-chip hardware.  
0
IT0  
External Interrupt 0 (IE0) Trigger Type.  
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).  
Cleared by software to specify level-sensitive detection (i.e., zero level).  
Timer/Counter 0 and 1 Data Registers  
Each timer consists of two 8-bit registers. These can be used as  
independent registers or combined to be a single 16-bit register  
depending on the timer mode configuration.  
TH0 and TL0  
Timer 0 high byte and low byte.  
SFR Address = 8CH, 8AH respectively.  
TH1 and TL1  
Timer 1 high byte and low byte.  
SFR Address = 8DH, 8BH respectively.  
REV. B  
–31–  
ADuC812  
TIMER/COUNTER 0 AND 1 OPERATING MODES  
Mode 2 (8-Bit Timer/Counter with Auto Reload)  
The following paragraphs describe the operating modes for timer/  
counters 0 and 1. Unless otherwise noted, it should be assumed  
that these modes of operation are the same for timer 0 as for timer 1.  
Mode 2 configures the timer register as an 8-bit counter (TL0)  
with automatic reload, as shown in Figure 28. Overflow from TL0  
not only sets TF0, but also reloads TL0 with the contents of TH0,  
which is preset by software. The reload leaves TH0 unchanged.  
Mode 0 (13-Bit Timer/Counter)  
Mode 0 configures an 8-bit timer/counter with a divide-by-32  
prescaler. Figure 26 shows mode 0 operation.  
CORE  
،12  
CLK  
C/T = 0  
INTERRUPT  
CORE  
،12  
TL0  
TF0  
CLK  
(8 BITS)  
C/T = 0  
C/T = 1  
INTERRUPT  
TL0  
TH0  
P3.4/T0  
TF0  
(5 BITS) (8 BITS)  
CONTROL  
TR0  
C/T = 1  
P3.4/T0  
CONTROL  
RELOAD  
GATE  
P3.2/INT0  
TR0  
TH0  
(8 BITS)  
GATE  
Figure 28. Timer/Counter 0, Mode 2  
P3.2/INT0  
Mode 3 (Two 8-Bit Timer/Counters)  
Figure 26. Timer/Counter 0, Mode 0  
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in  
Mode 3 simply holds its count. The effect is the same as setting  
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two  
separate counters. This configuration is shown in Figure 29. TL0  
uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TF0.  
TH0 is locked into a timer function (counting machine cycles)  
and takes over the use of TR1 and TF1 from timer 1. Thus, TH0  
now controls the “Timer 1” interrupt. Mode 3 is provided for  
applications requiring an extra 8-bit timer or counter.  
In this mode, the timer register is configured as a 13-bit register.  
As the count rolls over from all 1s to all 0s, it sets the timer overflow  
flag TF0. The overflow flag, TF0, can then be used to request an  
interrupt. The counted input is enabled to the timer when TR0 = 1  
and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer  
to be controlled by external input INT0, to facilitate pulsewidth  
measurements. TR0 is a control bit in the special function regis-  
ter TCON; Gate is in TMOD. The 13-bit register consists of all  
eight bits of TH0 and the lower five bits of TL0. The upper three  
bits of TL0 are indeterminate and should be ignored. Setting the  
run flag (TR0) does not clear the registers.  
When timer 0 is in Mode 3, timer 1 can be turned on and off by  
switching it out of, and into, its own Mode 3, or can still be used by  
the serial interface as a Baud Rate Generator. In fact, it can be used,  
in any application not requiring an interrupt from timer 1 itself.  
Mode 1 (16-Bit Timer/Counter)  
Mode 1 is the same as Mode 0, except that the timer register is  
running with all 16 bits. Mode 1 is shown in Figure 27.  
CORE  
CLK  
CORE  
CLK/12  
،12  
C/T = 0  
C/T = 1  
INTERRUPT  
CORE  
CLK  
TL0  
،12  
TF0  
(8 BITS)  
C/T = 0  
INTERRUPT  
TL0  
TH0  
TF0  
P3.4/T0  
(8 BITS) (8 BITS)  
CONTROL  
TR0  
C/T = 1  
P3.4/T0  
CONTROL  
GATE  
TR0  
P3.2/INT0  
INTERRUPT  
GATE  
CORE  
CLK/12  
TH0  
(8 BITS)  
TF1  
P3.2/INT0  
CONTROL  
Figure 27. Timer/Counter 0, Mode 1  
TR1  
Figure 29. Timer/Counter 0, Mode 3  
–32–  
REV. B  
ADuC812  
T2CON  
Timer/Counter 2 Control Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
C8H  
00H  
Yes  
TF2  
EXF2  
RCLK  
TCLK  
EXEN2  
TR2  
CNT2  
CAP2  
Table XVIII. T2CON SFR Bit Designations  
Bit  
Name  
Description  
7
TF2  
Timer 2 Overflow Flag.  
Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1.  
Cleared by user software.  
Timer 2 External Flag.  
Set by hardware when either a capture or reload is caused by a negative transition on T2EX and  
EXEN2 = 1.  
Cleared by user software.  
Receive Clock Enable Bit.  
Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port  
Modes 1 and 3.  
Cleared by user to enable timer 1 overflow to be used for the receive clock.  
Transmit Clock Enable Bit.  
Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial  
port Modes 1 and 3.  
Cleared by user to enable timer 1 overflow to be used for the transmit clock.  
Timer 2 External Enable Flag.  
6
5
4
3
EXF2  
RCLK  
TCLK  
EXEN2  
Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if  
Timer 2 is not being used to clock the serial port.  
Cleared by user for Timer 2 to ignore events at T2EX.  
Timer 2 Start/Stop Control Bit.  
Set by user to start timer 2.  
Cleared by user to stop timer 2.  
2
1
0
TR2  
CNT2  
CAP2  
Timer 2 Timer or Counter Function Select Bit.  
Set by user to select counter function (input from external T2 pin).  
Cleared by user to select timer function (input from on-chip core clock).  
Timer 2 Capture/Reload Select Bit.  
Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1.  
Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX  
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is  
forced to autoreload on Timer 2 overflow.  
Timer/Counter 2 Data Registers  
Timer/Counter 2 also has two pairs of 8-bit data registers  
associated with it. These are used as both timer data registers  
and timer capture/reload registers.  
TH2 and TL2  
Timer 2, data high byte and low byte.  
SFR Address = CDH, CCH respectively.  
RCAP2H and RCAP2L  
Timer 2, Capture/Reload byte and low byte.  
SFR Address = CBH, CAH respectively.  
REV. B  
–33–  
ADuC812  
Timer/Counter Operation Modes  
16-Bit Capture Mode  
The following paragraphs describe the operating modes for timer/  
counter 2. The operating modes are selected by bits in the T2CON  
SFR as shown in Table XIX.  
In the “Capture” mode, there are again two options, which are  
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2  
is a 16-bit timer or counter which, upon overflowing, sets bit TF2,  
the Timer 2 overflow bit, which can be used to generate an inter-  
rupt. If EXEN2 = 1, then Timer 2 still performs the above, but  
a l-to-0 transition on external input T2EX causes the current value  
in the Timer 2 registers, TL2 and TH2, to be captured into regis-  
ters RCAP2L and RCAP2H, respectively. In addition, the  
transition at T2EX causes bit EXF2 in T2CON to be set, and  
EXF2, like TF2, can generate an interrupt. The Capture Mode  
is illustrated in Figure 31.  
Table XIX. TIMECON SFR Bit Designations  
RCLK (or) TCLK  
CAP2  
TR2  
MODE  
0
0
1
X
0
1
X
X
1
1
1
0
16-Bit Autoreload  
16-Bit Capture  
Baud Rate  
OFF  
The baud rate generator mode is selected by RCLK = 1 and/or  
TCLK = 1.  
16-Bit Autoreload Mode  
In “Autoreload” mode, there are two options, which are selected  
by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2  
rolls over it not only sets TF2 but also causes the Timer 2 registers  
to be reloaded with the 16-bit value in registers RCAP2L and  
RCAP2H, which are preset by software. If EXEN2 = 1, then  
Timer 2 still performs the above, but with the added feature that  
a 1-to-0 transition at external input T2EX will also trigger the  
16-bit reload and set EXF2. The Autoreload mode is illustrated  
in Figure 30 below.  
In either case if Timer 2 is being used to generate the baud rate,  
the TF2 interrupt flag will not occur. Hence Timer 2 interrupts  
will not occur so they do not have to be disabled. In this mode  
the EXF2 flag, however, can still cause interrupts and this can  
be used as a third external interrupt.  
Baud rate generation will be described as part of the UART  
serial port operation in the following pages.  
CORE  
12  
CLK  
C/T2 = 0  
C/T2 = 1  
TL2  
(8-BITS)  
TH2  
(8-BITS)  
T2  
PIN  
CONTROL  
TR2  
RELOAD  
TRANSITION  
DETECTOR  
RCAP2L  
RCAP2H  
TF2  
TIMER  
INTERRUPT  
T2EX  
PIN  
EXF2  
CONTROL  
EXEN2  
Figure 30. Timer/Counter 2, 16-Bit Autoreload Mode  
CORE  
CLK  
12  
C/T2 = 0  
TL2  
(8-BITS)  
TH2  
(8-BITS)  
TF2  
C/T2 = 1  
T2  
PIN  
CONTROL  
TR2  
TIMER  
INTERRUPT  
CAPTURE  
TRANSITION  
DETECTOR  
RCAP2L  
RCAP2H  
T2EX  
PIN  
EXF2  
CONTROL  
EXEN2  
Figure 31. Timer/Counter 2, 16-Bit Capture Mode  
–34–  
REV. B  
ADuC812  
TXD(P3.1) while the SFR interface to the UART is comprised  
of SBUF and SCON, as described below.  
UART SERIAL INTERFACE  
The serial port is full duplex, meaning it can transmit and receive  
simultaneously. It is also receive-buffered, meaning it can com-  
mence reception of a second byte before a previously received byte  
has been read from the receive register. However, if the first  
byte still has not been read by the time reception of the second  
byte is complete, the first byte will be lost. The physical inter-  
face to the serial data network is via Pins RXD(P3.0) and  
SBUF  
The serial port receive and transmit registers are both accessed  
through the SBUF SFR (SFR address = 99 hex). Writing to  
SBUF loads the transmit register and reading SBUF accesses a  
physically separate receive register.  
SCON  
UART Serial Port Control  
Register  
98H  
SFR Address  
Power-On Default Value  
Bit Addressable  
00H  
Yes  
SM0  
SM1  
SM2  
REN  
TB8  
RB8  
TI  
RI  
Table XX. SCON SFR Bit Designations  
Bit  
Name  
Description  
7
6
SM0  
SM1  
UART Serial Mode Select Bits.  
These bits select the Serial Port operating mode as follows:  
SM0  
SM1  
Selected Operating Mode  
0
0
1
0
1
0
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)  
Mode 1: 8-bit UART, variable baud rate  
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or  
(Core_Clk/32)  
1
1
Mode 3: 9-bit UART, variable baud rate  
5
4
SM2  
REN  
Multiprocessor Communication Enable Bit.  
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.  
In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is  
cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is  
set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will  
be set as soon as the byte of data has been received.  
Serial Port Receive Enable Bit.  
Set by user software to enable serial port reception.  
Cleared by user software to disable serial port reception.  
Serial Port Transmit (Bit 9).  
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.  
Serial port Receiver Bit 9.  
3
2
TB8  
RB8  
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is  
latched into RB8.  
1
0
TI  
RI  
Serial Port Transmit Interrupt Flag.  
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in  
Modes 1, 2, and 3. TI must be cleared by user software.  
Serial Port Receive Interrupt Flag.  
Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in  
Modes 1, 2, and 3. RI must be cleared by software.  
REV. B  
–35–  
ADuC812  
Mode 0: 8-Bit Shift Register Mode  
Mode 2: 9-Bit UART with Fixed Baud Rate  
Mode 0 is selected by clearing both the SM0 and SM1 bits in the  
SFR SCON. Serial data enters and exits through RXD. TXD  
outputs the shift clock. Eight data bits are transmitted or received.  
Transmission is initiated by any instruction that writes to SBUF.  
The data is shifted out of the RXD line. The eight bits are  
transmitted with the least-significant bit (LSB) first, as shown  
in Figure 32.  
Mode 2 is selected by setting SM0 and clearing SM1. In this  
mode the UART operates in 9-bit mode with a fixed baud rate.  
The baud rate is fixed at Core_Clk/64 by default, although by  
setting the SMOD bit in PCON, the frequency can be doubled to  
Core_Clk/32. Eleven bits are transmitted or received, a start  
bit (0), eight data bits, a programmable ninth bit and a stop bit  
(1). The ninth bit is most often used as a parity bit, although it  
can be used for anything, including a ninth data bit if required.  
MACHINE  
CYCLE 1  
MACHINE MACHINE  
CYCLE 2 CYCLE 7  
MACHINE  
CYCLE 8  
To transmit, the eight data bits must be written into SBUF. The  
ninth bit must be written to TB8 in SCON. When transmission is  
initiated the eight data bits (from SBUF) are loaded onto the  
transmit shift register (LSB first). The contents of TB8 are loaded  
into the ninth bit position of the transmit shift register. The trans-  
mission will start at the next valid baud rate clock. The TI flag  
is set as soon as the stop bit appears on TXD.  
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4  
S4 S5 S6 S1 S2 S3 S4 S5 S6  
CORE  
CLK  
ALE  
RXD  
(DATA OUT)  
DATA BIT 0  
DATA BIT 1  
DATA BIT 6  
DATA BIT 7  
TXD  
(SHIFT  
Reception for Mode 2 is similar to that of Mode 1. The eight  
data bytes are input at RXD (LSB first) and loaded onto the  
receive shift register. When all eight bits have been clocked in,  
the following events occur:  
CLOCK)  
Figure 32. UART Serial Port Transmission, Mode 0  
Reception is initiated when the receive enable bit (REN) is 1 and  
the receive interrupt bit (RI) is 0. When RI is cleared the data is  
clocked into the RXD line and the clock pulses are output from  
the TXD line.  
The eight bits in the receive shift register are latched into SBUF.  
The ninth data bit is latched into RB8 in SCON.  
The Receiver interrupt flag (RI) is set.  
Mode 1: 8-Bit UART, Variable Baud Rate  
This will be the case if, and only if, the following conditions are  
met at the time the final shift pulse is generated:  
Mode 1 is selected by clearing SM0 and setting SM1. Each  
data byte (LSB first) is preceded by a start bit (0) and followed by  
a stop bit (1). Therefore 10 bits are transmitted on TXD or  
received on RXD. The baud rate is set by the Timer 1 or Timer 2  
overflow rate, or a combination of the two (one for transmission  
and the other for reception).  
RI = 0, and  
Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.  
If either of these conditions is not met, the received frame is  
irretrievably lost, and RI is not set.  
Transmission is initiated by writing to SBUF. The “write to  
SBUF” signal also loads a 1 (stop bit) into the ninth bit position  
of the transmit shift register. The data is output bit by bit  
until the stop bit appears on TXD and the transmit interrupt  
flag (TI) is automatically set as shown in Figure 33.  
Mode 3: 9-Bit UART with Variable Baud Rate  
Mode 3 is selected by setting both SM0 and SM1. In this mode  
the 8051 UART serial port operates in 9-bit mode with a variable  
baud rate determined by either Timer 1 or Timer 2. The opera-  
tion of the 9-bit UART is the same as for Mode 2 but the baud  
rate can be varied as for Mode 1.  
STOP BIT  
START  
BIT  
In all four modes, transmission is initiated by any instruction that  
uses SBUF as a destination register. Reception is initiated in Mode 0  
by the condition RI = 0 and REN = 1. Reception is initiated in  
the other modes by the incoming start bit if REN = 1.  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
TXD  
TI  
(SCON.1)  
SET INTERRUPT  
I.E., READY FOR MORE DATA  
UART Serial Port Baud Rate Generation  
Mode 0 Baud Rate Generation  
The baud rate in Mode 0 is fixed:  
Figure 33. UART Serial Port Transmission, Mode 0  
Reception is initiated when a 1-to-0 transition is detected on  
RXD. Assuming a valid start bit was detected, character reception  
continues. The start bit is skipped and the eight data bits are  
clocked into the serial port shift register. When all eight bits have  
been clocked in, the following events occur: The eight bits in the  
receive shift register are latched into SBUF The ninth bit (Stop  
bit) is clocked into RB8 in SCON. The Receiver interrupt flag  
(RI) is set if, and only if, the following conditions are met at the  
time the final shift pulse is generated: RI = 0, and Either  
SM2 = 0, or SM2 = 1 and the received stop bit = 1.  
Mode 0 Baud Rate = (Core Clock Frequency/12)  
Mode 2 Baud Rate Generation  
The baud rate in Mode 2 depends on the value of the SMOD bit  
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core  
clock. If SMOD = 1, the baud rate is 1/32 of the core clock:  
Mode 2 Baud Rate = (2SMOD/64) × (Core Clock Frequency)  
Mode 1 and 3 Baud Rate Generation  
The baud rates in Modes 1 and 3 are determined by the overflow  
rate in Timer 1 or Timer 2, or both (one for transmit and the  
other for receive).  
If either of these conditions is not met, the received frame is  
irretrievably lost, and RI is not set.  
–36–  
REV. B  
ADuC812  
Timer 1 Generated Baud Rates  
Modes 1 and 3 Baud Rate = (1/16) × (Timer 2 Overflow Rate)  
When Timer 1 is used as the baud rate generator, the baud rates  
in Modes 1 and 3 are determined by the Timer 1 overflow rate and  
the value of SMOD as follows:  
Therefore, when Timer 2 is used to generate baud rates, the timer  
increments every two clock cycles and not every core machine  
cycle as before. Hence, it increments six times faster than Timer  
1, and therefore baud rates six times faster are possible. Because  
Timer 2 has 16-bit autoreload capability, very low baud rates  
are still possible.  
Modes 1 and 3 Baud Rate =  
(2SMOD/32) × (Timer 1 Overflow Rate)  
The Timer 1 interrupt should be disabled in this application. The  
Timer itself can be configured for either timer or counter opera-  
tion, and in any of its three running modes. In the most typical  
application, it is configured for timer operation, in the Autoreload  
mode (high nibble of TMOD = 0010 Binary). In that case, the baud  
rate is given by the formula:  
Timer 2 is selected as the baud rate generator by setting the TCLK  
and/or RCLK in T2CON. The baud rates for transmit and receive  
can be simultaneously different. Setting RCLK and/or TCLK puts  
Timer 2 into its baud rate generator mode as shown in Figure 34.  
In this case, the baud rate is given by the formula:  
Modes 1 and 3 Baud Rate =  
Modes 1 and 3 Baud Rate -  
(Core Clk)/(32 × [65536 – (RCAP2H, RCAP2L)])  
(2SMOD/32) × (Core Clock/(12 × [256-TH1]))  
Table XXI shows some commonly-used baud rates and how they  
might be calculated from a core clock frequency of 11.0592 MHz  
and 12 MHz. Generally speaking, a 5% error is tolerable  
using asynchronous (start/stop) communications.  
Table XXII shows some commonly used baud rates and how they  
might be calculated from a core clock frequency of 11.0592 MHz  
and 12 MHz.  
Table XXII. Commonly Used Baud Rates, Timer 2  
Table XXI. Commonly-Used Baud Rates, Timer 1  
Ideal  
Baud  
Core  
CLK  
RCAP2H RCAP2L  
Actual  
Baud  
%
Error  
Ideal  
Baud CLK  
Core  
SMOD TH1-Reload Actual  
%
Error  
Value  
Value  
Value  
Value  
Baud  
19200 12  
–1 (FFh)  
–1 (FFh)  
–1 (FFh)  
–2 (FEh)  
–1 (FFh)  
–1 (FFh)  
–1 (FFh)  
–2 (FFh)  
–20 (ECh) 19661  
–41 (D7h) 9591  
–164 (5Ch) 2398  
–72 (B8h) 1199  
–18 (EEh) 19200  
–36 (DCh) 9600  
–144(70h) 2400  
–32 (E0h) 1200  
2.4  
0.1  
0.1  
0.1  
0
0
0
0
9600 12  
19200 11.0592  
9600  
2400  
1
–7 (F9h)  
–3 (FDh)  
–3 (FDh)  
–12(F4h)  
8929  
19200  
9600  
2400  
7
0
0
0
9600  
2400  
1200  
12  
12  
12  
1
0
0
11.0592  
11.0592  
19200 11.0592  
9600  
2400  
1200  
11.0592  
11.0592  
11.0592  
Timer 2 Generated Baud Rates  
Baud rates can also be generated using Timer 2. Using Timer 2  
is similar to using Timer 1 in that the timer must overflow 16 times  
before a bit is transmitted/received. Because Timer 2 has a 16-bit  
Autoreload mode a wider range of baud rates is possible using  
Timer 2.  
TIMER 1  
OVERFLOW  
2
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12.  
0
1
SMOD  
CONTROL  
CORE  
CLK  
2
TIMER 2  
C/T2 = 0  
C/T2 = 1  
OVERFLOW  
1
1
0
0
TL2  
(8-BITS)  
TH2  
(8-BITS)  
RCLK  
T2  
PIN  
RX  
CLOCK  
16  
TR2  
TCLK  
16  
RELOAD  
TX  
CLOCK  
RCAP2L  
RCAP2H  
NOTE: AVAILABILITY OF ADDITIONAL  
EXTERNAL INTERRUPT  
EXF  
2
TIMER 2  
INTERRUPT  
T2EX  
PIN  
CONTROL  
TRANSITION  
DETECTOR  
EXEN2  
Figure 34. Timer 2, UART Baud Rates  
–37–  
REV. B  
ADuC812  
INTERRUPT SYSTEM  
The ADuC812 provides a total of nine interrupt sources with  
two priority levels. The control and configuration of the interrupt  
system is carried out through three Interrupt-related SFRs.  
IE:  
IP:  
Interrupt Enable Register.  
Interrupt Priority Register.  
IE2:  
Secondary Interrupt Enable Register.  
IE:  
Interrupt Enable Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
A8H  
00H  
Yes  
EA  
EADC  
ET2  
ES  
ET1  
EX1  
ET0  
EX0  
Table XXIII. IE SFR Bit Designations  
Description  
Bit  
Name  
7
6
5
4
3
2
1
0
EA  
Written by User to Enable “1” or Disable “0” All Interrupt Sources  
Written by User to Enable “1” or Disable “0” ADC Interrupt  
Written by User to Enable “1” or Disable “0” Timer 2 Interrupt  
Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt  
Written by User to Enable “1” or Disable “0” Timer 1 Interrupt  
Written by User to Enable “1” or Disable “0” External Interrupt 1  
Written by User to Enable “1” or Disable “0” Timer 0 Interrupt  
Written by User to Enable “1” or Disable “0” External Interrupt 0  
EADC  
ET2  
ES  
ET1  
EX1  
ET0  
EX0  
IP:  
Interrupt Priority Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
B8H  
00H  
Yes  
PSI  
PADC  
PT2  
PS  
PT1  
PX1  
PT0  
PX0  
Table XXIV. IP SFR Bit Designations  
Description  
Written by User to Select SPI/I2C Priority (“1” = High; “0” = Low)  
Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low)  
Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low)  
Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low)  
Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low)  
Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low)  
Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low)  
Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low)  
Bit  
Name  
7
6
5
4
3
2
1
0
PSI  
PADC  
PT2  
PS  
PT1  
PX1  
PT0  
PX0  
–38–  
REV. B  
ADuC812  
IE2:  
Secondary Interrupt Enable Register  
SFR Address  
Power-On Default Value  
Bit Addressable  
A9H  
00H  
No  
—
—
—
—
—
—
EPSMI  
ESI  
Table XXV. IE2 SFR Bit Designations  
Bit  
Name  
Description  
7
6
5
4
3
2
1
0
—
—
—
—
—
—
EPSMI  
ESI  
Reserved for Future Use.  
Reserved for Future Use.  
Reserved for Future Use.  
Reserved for Future Use.  
Reserved for Future Use.  
Reserved for Future Use.  
Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt.  
Written by User to Enable “1” or Disable “0” SPI/I2C Serial Port Interrupt.  
Interrupt Priority  
Interrupt Vectors  
The Interrupt Enable registers are written by the user to enable  
individual interrupt sources, while the Interrupt Priority registers  
allow the user to select one of two priority levels for each interrupt.  
An interrupt of a high priority may interrupt the service routine  
of a low priority interrupt, and if two interrupts of different priority  
occur at the same time, the higher level interrupt will be serviced  
first. An interrupt cannot be interrupted by another interrupt of  
the same priority level. If two interrupts of the same priority level  
occur simultaneously, a polling sequence is observed as shown  
in Table XXVI.  
When an interrupt occurs the program counter is pushed onto  
the stack and the corresponding interrupt vector address is  
loaded into the program counter. The interrupt Vector Addresses  
are shown in the Table XXVII.  
Table XXVII. Interrupt Vector Addresses  
Source  
Vector Address  
IE0  
TF0  
IE1  
TF1  
RI + TI  
TF2 + EXF2  
ADCI  
I2CI + ISPI  
PSMI  
0003 Hex  
000B Hex  
0013 Hex  
001B Hex  
0023 Hex  
002B Hex  
0033 Hex  
003B Hex  
0043 Hex  
Table XXVI. Priority within an Interrupt Level  
Source  
Priority  
Description  
PSMI  
IE0  
1 (Highest)  
2
Power Supply Monitor Interrupt  
External Interrupt 0  
ADCI  
3
ADC Interrupt  
TF0  
IE1  
4
5
Timer/Counter 0 Interrupt  
External Interrupt 1  
TF1  
6
7
8
Timer/Counter 1 Interrupt  
I2CI + ISPI  
RI + TI  
TF2 + EXF2  
I2C/SPI Interrupt  
Serial Interrupt  
Timer/Counter 2 Interrupt  
9 (Lowest)  
REV. B  
–39–  
ADuC812  
ADuC812 HARDWARE DESIGN CONSIDERATIONS  
This section outlines some of the key hardware design consider-  
ations that must be addressed when integrating the ADuC812  
into any hardware system.  
Note that a second very important function of the EA pin is  
described in the Single Pin Emulation Mode section of this  
data sheet.  
External program memory (if used) must be connected to the  
ADuC812 as illustrated in Figure 37. Note that 16 I/O lines  
(Ports 0 and 2) are dedicated to bus functions during external  
program memory fetches. Port 0 (P0) serves as a multiplexed  
address/data bus. It emits the low byte of the program counter  
(PCL) as an address, and then goes into a float state awaiting  
the arrival of the code byte from the program memory. During the  
time that the low byte of the program counter is valid on P0, the  
signal ALE (Address Latch Enable) clocks this byte into an  
address latch. Meanwhile, Port 2 (P2) emits the high byte of the  
program counter (PCH), then PSEN strobes the EPROM and  
the code byte is read into the ADuC812.  
Clock Oscillator  
The clock source for the ADuC812 can come either from an  
external source or from the internal clock oscillator. To use the  
internal clock oscillator connect a parallel resonant crystal  
between Pins 32 and 33, and connect a capacitor from each pin  
to ground as shown below.  
ADuC812  
XTAL1  
TO INTERNAL  
TIMING CIRCUITS  
ADuC812  
EPROM  
XTAL2  
D0–D7  
(INSTRUCTION)  
P0  
Figure 35. External Parallel Resonant Crystal Connections  
A0–A7  
LATCH  
ALE  
ADuC812  
XTAL1  
EXTERNAL  
A8–A15  
P2  
CLOCK  
SOURCE  
OE  
PSEN  
TO INTERNAL  
TIMING CIRCUITS  
XTAL2  
Figure 37. External Program Memory Interface  
Figure 36. Connecting an External Clock Source  
Note that program memory addresses are always 16 bits wide, even  
in cases where the actual amount of program memory used is less  
than 64K bytes. External program execution sacrifices two of the  
8-bit ports (P0 and P2) to the function of addressing the program  
memory. While executing from external program memory, Ports  
0 and 2 can be used simultaneously for read/write access to exter-  
nal data memory, but not for general-purpose I/O.  
Whether using the internal oscillator or an external clock source,  
the ADuC812’s specified operational clock speed range is 300 kHz  
to 16 MHz. The core itself is static, and will function all the way  
down to dc. But at clock speeds slower that 400 kHz the ADC  
will no longer function correctly. Therefore to ensure specified  
operation, use a clock frequency of at least 400 kHz and no  
more than 16 MHz.  
Though both external program memory and external data memory  
are accessed by some of the same pins, the two are completely  
independent of each other from a software point of view. For  
example, the chip can read/write external data memory while  
executing from external program memory.  
External Memory Interface  
In addition to its internal program and data memories, the  
ADuC812 can access up to 64K bytes of external program  
memory (ROM/PROM/etc.) and up to 16M bytes of external  
data memory (SRAM).  
Figure 38 shows a hardware configuration for accessing up to  
64K bytes of external RAM. This interface is standard to any  
8051-compatible MCU.  
To select from which code space (internal or external program  
memory) to begin executing instructions, tie the EA (external  
access) pin high or low, respectively. When EA is high (pulled up  
to VDD), user program execution will start at address 0 of the  
internal 8K bytes Flash/EE code space. When EA is low (tied to  
ground) user program execution will start at address 0 of the  
external code space. In either case, addresses above 1FFF hex  
(8K) are mapped to the external space.  
ADuC812  
SRAM  
D0–D7  
(DATA)  
P0  
LATCH  
A0–A7  
ALE  
P2  
A8–A15  
OE  
RD  
WE  
WR  
Figure 38. External Data Memory Interface (64 K Address  
Space)  
–40–  
REV. B  
ADuC812  
If access to more than 64K bytes of RAM is desired, a feature  
unique to the ADuC812 allows addressing up to 16M bytes  
of external RAM simply by adding an additional latch as illustrated  
in Figure 39.  
The best way to implement an external POR function to meet the  
above requirements involves the use of a dedicated POR chip, such  
as the ADM809/ADM810 SOT-23 packaged PORs from Analog  
Devices. Recommended connection diagrams for both active-high  
ADM810 and active-low ADM809 PORs are shown in Figure  
41 and Figure 42, respectively.  
ADuC812  
SRAM  
D0–D7  
(DATA)  
P0  
ADuC812  
POWER SUPPLY  
20  
LATCH  
LATCH  
A0–A7  
34 DV  
DD  
ALE  
P2  
48  
A8–A15  
POR  
(ACTIVE HIGH)  
15  
RESET  
A16–A23  
Figure 41. External Active High POR Circuit  
OE  
RD  
Some active-low POR chips, such as the ADM809 can be used with  
a manual push-button as an additional reset source as illustrated  
by the dashed line connection in Figure 42.  
WE  
WR  
Figure 39. External Data Memory Interface (16 M Bytes  
Address Space)  
ADuC812  
POWER SUPPLY  
20  
In either implementation, Port 0 (P0) serves as a multiplexed  
address/data bus. It emits the low byte of the data pointer (DPL) as  
an address, which is latched by a pulse of ALE prior to data being  
placed on the bus by the ADuC812 (write operation) or the  
SRAM (read operation). Port 2 (P2) provides the data pointer  
page byte (DPP) to be latched by ALE, followed by the data  
pointer high byte (DPH). If no latch is connected to P2, DPP is  
ignored by the SRAM, and the 8051 standard of 64K byte external  
data memory access is maintained.  
1k⍀  
34 DV  
48  
DD  
POR  
(ACTIVE LOW)  
15  
RESET  
OPTIONAL  
MANUAL  
RESET  
PUSH-BUTTON  
Detailed timing diagrams of external program and data memory  
read and write access can be found in the timing specification  
sections of this data sheet.  
Figure 42. External Active Low POR Circuit  
Power Supplies  
The ADuC812’s operational power supply voltage range is 2.7 V  
to 5.25 V. Although the guaranteed data sheet specifications are  
given only for power supplies within 2.7 V to 3.6 V or 10% of  
the nominal 5 V level, the chip will function equally well at any  
power supply level between 2.7 V and 5.5 V.  
Power-On Reset Operation  
External POR (power-on reset) circuitry must be implemented to  
drive the RESET pin of the ADuC812. The circuit must hold  
the RESET pin asserted (high) whenever the power supply  
(DVDD) is below 2.5 V. Furthermore, VDD must remain above  
2.5 V for at least 10 ms before the RESET signal is deasserted  
(low) by which time the power supply must have reached at least  
a 2.7 V level. The external POR circuit must be operational  
down to 1.2 V or less. The timing diagram of Figure 40 illus-  
trates this functionality under three separate events: power-up,  
brownout, and power-down. Notice that when RESET is asserted  
(high) it tracks the voltage on DVDD. These recommendations  
must be adhered to through the manufacturing flow of your  
ADuC812-based system as well as during its normal power-on  
operation. Failure to adhere to these recommendations can  
result in permanent damage to device functionality.  
Separate analog and digital power supply pins (AVDD and DVDD  
respectively) allow AVDD to be kept relatively free of noisy digital  
signals often present on the system DVDD line. However, though  
you can power AVDD and DVDD from two separate supplies if  
desired, you must ensure that they remain within 0.3 V of one  
another at all times in order to avoid damaging the chip (as per the  
Absolute Maximum Ratings section of this data sheet). Therefore  
it is recommended that unless AVDD and DVDD are connected  
directly together, you connect back-to-back Schottky diodes  
between them as shown in Figure 43.  
DIGITAL SUPPLY  
ANALOG SUPPLY  
10␮F  
10␮F  
+
+
–
2.5V MIN  
–
ADuC812  
DV  
DD  
10ms  
MIN  
10ms  
MIN  
1.2V MAX  
1.2V MAX  
20  
5
AV  
DD  
34 DV  
48  
DD  
0.1␮F  
0.1␮F  
21  
RESET  
6
AGND  
35 DGND  
47  
Figure 40. External POR Timing  
Figure 43. External Dual-Supply Connections  
REV. B  
–41–  
ADuC812  
As an alternative to providing two separate power supplies, the  
user can help keep AVDD quiet by placing a small series resistor  
and/or ferrite bead between it and DVDD, and then decoupling  
AVDD separately to ground. An example of this configuration is  
shown in Figure 44. With this configuration other analog cir-  
cuitry (such as op amps, voltage reference, etc.) can be powered  
from the AVDD supply line as well. Thne user will still want to  
include back-to-back Schottky diodes between AVDD and DVDD  
in order to protect from power-up and power-down transient  
conditions that could separate the two supply voltages momentarily.  
Table XXVIII. Typical IDD of Core and Peripherals  
VDD = 5 V VDD = 3 V  
Core:  
(Normal Mode) (1.6 nAs × MCLK) + (0.8 nAs × MCLK) +  
6 mA 3 mA  
Core:  
(Idle Mode)  
(0.75 nAs × MCLK) + (0.25 nAs × MCLK) +  
5 mA  
3 mA  
ADC:  
DAC (Each):  
Voltage Ref:  
1.3 mA  
250 µA  
200 µA  
1.0 mA  
200 µA  
150 µA  
DIGITAL SUPPLY  
10␮F  
1.6V  
ADuC812  
Since operating DVDD current is primarily a function of clock  
speed, the expressions for “CORE” supply current in Table  
XXVIII are given as functions of MCLK, the oscillator frequency.  
Plug in a value for MCLK in hertz to determine the current con-  
sumed by the core at that oscillator frequency. Since the ADC  
and DACs can be enabled or disabled in software, add only the  
currents from the peripherals you expect to use. The internal  
voltage reference is automatically enabled whenever either the  
ADC or at least one DAC is enabled. And again, do not forget  
to include current sourced by I/O pins, serial port pins, DAC  
outputs, etc., plus the additional current drawn during Flash/EE  
erase and program cycles.  
10␮F  
BEAD  
+
–
20  
AV  
5
DD  
34 DV  
48  
DD  
0.1␮F  
0.1␮F  
21  
35  
DGND  
6
AGND  
47  
Figure 44. External Single-Supply Connections  
Notice that in both Figure 43 and Figure 44, a large value (10 µF)  
reservoir capacitor sits on DVDD and a separate 10 µF capacitor  
sits on AVDD. Also, local small-value (0.1 µF) capacitors are  
located at each VDD pin of the chip. As per standard design prac-  
tice, be sure to include all of these capacitors, and ensure the  
smaller capacitors are close to each AVDD pin with trace lengths as  
short as possible. Connect the ground terminal of each of these  
capacitors directly to the underlying ground plane. Finally, it  
should also be noted that, at all times, the analog and digital  
ground pins on the ADuC812 must be referenced to the same  
system ground reference point.  
A software switch allows the chip to be switched from normal  
mode into idle mode, and also into full power-down mode. Below  
are brief descriptions of power-down and idle modes.  
In idle mode, the oscillator continues to run, but is gated off to  
the core only. The on-chip peripherals continue to receive the  
clock, and remain functional. Port pins and DAC output pins  
retain their states in this mode. The chip will recover from idle  
mode upon receiving any enabled interrupt, or on receiving a  
hardware reset.  
In full power-down mode, the on-chip oscillator stops, and all  
on-chip peripherals are shut down. Port pins retain their logic  
levels in this mode, but the DAC output goes to a high-impedance  
state (three-state). The chip will only recover from power-down  
mode upon receiving a hardware reset or when power is cycled.  
During full power-down mode, the ADuC812 consumes a total  
of approximately 5 µA.  
Power Consumption  
The currents consumed by the various sections of the  
ADuC812 are shown in Table XXVIII. The “CORE” values  
given represent the current drawn by DVDD, while the rest  
(“ADC,” “DAC,” “voltage ref”) are pulled by the AVDD pin  
and can be disabled in software when not in use. The other  
on-chip peripherals (watchdog timer, power supply monitor,  
etc.) consume negligible current and are therefore lumped in  
with the “CORE” operating current here. Of course, the user  
must add any currents sourced by the parallel and serial I/O  
pins, and that sourced by the DAC, in order to determine the  
total current needed at the ADuC812’s supply pins. Also,  
current drawn from the DVDD supply will increase by  
approximately 10 mA during Flash/EE erase and program cycles.  
–42–  
REV. B  
ADuC812  
Grounding and Board Layout Recommendations  
As with all high resolution data converters, special attention must  
be paid to grounding and PC board layout of ADuC812-based  
designs in order to achieve optimum performance from the ADCs  
and DAC.  
In all of these scenarios, and in more complicated real-life appli-  
cations, keep in mind the flow of current from the supplies and  
back to ground. Make sure the return paths for all currents are  
as close as possible to the paths the currents took to reach their  
destinations. For example, do not power components on the  
analog side of Figure 45b with DVDD since that would force  
return currents from DVDD to flow through AGND. Also, try to  
avoid digital currents flowing under analog circuitry, which could  
happen if the user placed a noisy digital chip on the left half  
of the board in Figure 45c. Whenever possible, avoid large  
discontinuities in the ground plane(s) (such as are formed by a  
long trace on the same layer), since they force return signals to  
travel a longer path. And of course, make all connections to the  
ground plane directly, with little or no trace separating the pin  
from its via to ground.  
Although the ADuC812 has separate pins for analog and digital  
ground (AGND and DGND), the user must not tie these to two  
separate ground planes unless the two ground planes are con-  
nected together very close to the ADuC812, as illustrated in the  
simplified example of Figure 45a. In systems where digital and  
analog ground planes are connected together somewhere else  
(at the system’s power supply for example), they cannot be con-  
nected again near the ADuC812 since a ground loop would result.  
In these cases, tie the ADuC812’s AGND and DGND pins all  
to the analog ground plane, as illustrated in Figure 45b. In systems  
with only one ground plane, ensure that the digital and analog  
components are physically separated onto separate halves of the  
board such that digital return currents do not flow near analog  
circuitry and vice versa. The ADuC812 can then be placed between  
the digital and analog sections, as illustrated in Figure 45c.  
If the user plans to connect fast logic signals (rise/fall time < 5 ns)  
to any of the ADuC812’s digital inputs, add a series resistor to  
each relevant line to keep rise and fall times longer than 5 ns at  
the ADuC812 input pins. A value of 100 Ω or 200 Ω is usually  
sufficient to prevent high-speed signals from coupling capacitively  
into the ADuC812 and affecting the accuracy of ADC conversions.  
PLACE ANALOG  
COMPONENTS HERE  
PLACE DIGITAL  
COMPONENTS HERE  
A
AGND  
DGND  
PLACE ANALOG  
COMPONENTS  
HERE  
PLACE DIGITAL  
COMPONENTS  
HERE  
B
AGND  
DGND  
PLACE DIGITAL  
COMPONENTS  
HERE  
C
PLACE ANALOG  
COMPONENTS  
HERE  
GND  
Figure 45. System Grounding Schemes  
REV. B  
–43–  
ADuC812  
DOWNLOAD/DEBUG  
ENABLE JUMPER  
(NORMALLY OPEN)  
DV  
DV  
DD  
DD  
1k⍀  
1k⍀  
2-PIN HEADER FOR  
EMULATION ACCESS  
(NORMALLY OPEN)  
49  
52 51 50  
ADC0  
48 47 46 45 44  
43  
42 41 40  
51⍀  
39  
ANALOG INPUT  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
AV  
DV  
DD  
DD  
AV  
DD  
DGND  
DV  
DD  
AGND  
ADuC812  
C
REF  
XTAL2  
XTAL1  
V
OUTPUT  
11.0592MHz  
REF  
V
REF  
DAC0  
DAC1  
DAC OUTPUT  
DVDD  
ADM810  
GND  
NOT CONNECTED IN THIS EXAMPLE  
V
RST  
DV  
DD  
CC  
ADM202  
DV  
DD  
9-PIN D-SUB  
FEMALE  
C1+  
V+  
V
CC  
GND  
1
2
3
4
5
6
7
8
9
C1–  
T1OUT  
C2+  
C2–  
V–  
R1IN  
R1OUT  
T1IN  
T2OUT  
R2IN  
T2IN  
R2OUT  
Figure 46. Typical System Configuration  
OTHER HARDWARE CONSIDERATIONS  
the PSEN pin, as shown in Figure 46. To get the ADuC812  
into download mode, simply connect this jumper and power-  
cycle the device (or manually reset the device, if a manual reset  
button is available) and it will be ready to receive a new program  
serially. With the jumper removed, the device will come up in  
normal mode (and run the program) whenever power is cycled  
or RESET is toggled.  
To facilitate in-circuit programming, plus in-circuit debug and  
emulation options, users will want to implement some simple  
connection points in their hardware that will allow easy access to  
download, debug, and emulation modes.  
In-Circuit Serial Download Access  
Nearly all ADuC812 designs will want to take advantage of the  
in-circuit reprogrammability of the chip. This is accomplished by a  
connection to the ADuC812’s UART, which requires an external  
RS-232 chip for level translation if downloading code from a PC.  
Basic configuration of an RS-232 connection is illustrated in  
Figure 46 with a simple ADM202-based circuit. If users would  
rather not design an RS-232 chip onto a board, refer to the applica-  
tion note “uC006–A 4-Wire UART-to-PC Interface”* for a  
simple (and zero-cost-per-board) method of gaining in-circuit  
serial download access to the ADuC812.  
Note that PSEN is normally an output (as described in the  
External Memory Interface section) and it is sampled as an  
input only on the falling edge of RESET (i.e., at power-up or  
upon an external manual reset). Note also that if any external  
circuitry unintentionally pulls PSEN low during power-up or  
reset events, it could cause the chip to enter download mode and  
therefore fail to begin user code execution as it should. To pre-  
vent this, ensure that no external signals are capable of pulling  
the PSEN pin low, except for the external PSEN jumper itself.  
In addition to the basic UART connections, users will also need  
a way to trigger the chip into download mode. This is accom-  
plished via a 1 kΩ pull-down resistor that can be jumpered onto  
Embedded Serial Port Debugger  
From a hardware perspective, entry to serial port debug mode is  
identical to the serial download entry sequence described above.  
In fact, both serial download and serial port debug modes can be  
thought of as essentially one mode of operation used in two  
different ways.  
*Application Note uC006 is available at www.analog.com/microconverter  
–44–  
REV. B  
ADuC812  
Note that the serial port debugger is fully contained on the  
ADuC812 device, (unlike “ROM monitor” type debuggers) and  
therefore no external memory is needed to enable in-system  
debug sessions.  
Single-Pin Emulation Mode  
Also built into the ADuC812 is a dedicated controller for  
single-pin in-circuit emulation (ICE) using standard production  
ADuC812 devices. In this mode, emulation access is gained by  
connection to a single pin, the EA pin. Normally, this pin is hard-  
wired either high or low to select execution from internal or  
external program memory space, as described earlier. To enable  
single-pin emulation mode, however, users will need to pull the  
EA pin high through a 1 kΩ resistor as shown in Figure 46. The  
emulator will then connect to the 2-pin header also shown in  
Figure 46. To be compatible with the standard connector that  
comes with the single-pin emulator available from Accutron Limited  
(www.accutron.com), use a 2-pin 0.1-inch pitch “Friction Lock”  
header from Molex (www.molex.com) such as their part number  
22-27-2021. Be sure to observe the polarity of this header. As  
represented in Figure 46, when the Friction Lock tab is at the  
right, the ground pin should be the lower of the two pins (when  
viewed from the top).  
Figure 47. Components of the QuickStart Development  
System  
Enhanced-Hooks Emulation Mode  
ADuC812 also supports enhanced-hooks emulation mode. An  
enhanced-hooks-based emulator is available from Metalink  
Corporation (www.metaice.com). No special hardware support  
for these emulators needs to be designed onto the board since  
these are “pod-style” emulators where users must replace the  
chip on their board with a header device that the emulator pod  
plugs into. The only hardware concern is then one of determin-  
ing if adequate space is available for the emulator pod to fit into  
the system enclosure.  
Typical System Configuration  
Figure 48. Typical Debug Session  
A typical ADuC812 configuration is shown in Figure 46. It sum-  
marizes some of the hardware considerations discussed in the  
previous paragraphs.  
Download—In-Circuit Serial Downloader  
The Serial Downloader is a Windows application that allows the  
user to serially download an assembled program (Intel Hex format  
file) to the on-chip program FLASH memory via the serial  
COM1 port on a standard PC. An Application Note (uC004)  
detailing this serial download protocol is available from  
www.analog.com/microconverter.  
QUICKSTART DEVELOPMENT SYSTEM  
The QuickStart Development System is a full featured, low cost  
development tool suite supporting the ADuC812. The system  
consists of the following PC-based (Windows-compatible) hard-  
ware and software development tools.  
DeBug—In-Circuit Debugger  
The Debugger is a Windows application that allows the user to  
debug code execution on silicon using the MicroConverter UART  
serial port. The debugger provides access to all on-chip periph-  
erals during a typical debug session as well as single-step and  
break-point code execution control.  
Hardware:  
ADuC812 Evaluation Board, Plug-In  
Power Supply and Serial Port Cable  
Code Development:  
Code Functionality:  
8051 Assembler  
Windows Based Simulator  
ADSIM—Windows Simulator  
In-Circuit Code Download: Serial Downloader  
The Simulator is a Windows application that fully simulates all  
the MicroConverter functionality including ADC and DAC  
peripherals. The simulator provides an easy-to-use, intuitive, inter-  
face to the MicroConverter functionality and integrates many  
standard debug features; including multiple breakpoints, single  
stepping; and code execution trace capability. This tool can be  
used both as a tutorial guide to the part as well as an efficient way  
to prove code functionality before moving to a hardware platform.  
In-Circuit Debugger:  
Miscellaneous Other:  
Serial Port Debugger  
CD-ROM Documentation and  
Two Additional Prototype Devices  
Figure 47 shows the typical components of a QuickStart  
Development System. A brief description of some of the software  
tools components in the QuickStart Development System is  
given below.  
The QuickStart development tool-suite software is freely  
available at the Analog Devices MicroConverter Website  
www.analog.com/microconverter.  
REV. B  
–45–  
ADuC812  
TIMING SPECIFICATIONS1, 2, 3  
(AVDD = DVDD = 3.0 V or 5.0 V ؎ 10%. All specifications TA = TMIN to TMAX unless otherwise noted.)  
12 MHz  
Typ  
Variable Clock  
Parameter  
Min  
Max  
Min  
Typ  
Max  
Unit  
Figure  
CLOCK INPUT (External Clock Driven XTAL1)  
tCK  
XTAL1 Period  
83.33  
62.5  
20  
20  
1000  
ns  
ns  
ns  
ns  
ns  
µs  
50  
50  
50  
50  
50  
tCKL  
tCKH  
tCKR  
tCKF  
XTAL1 Width Low  
XTAL1 Width High  
XTAL1 Rise Time  
XTAL1 Fall Time  
ADuC812 Machine Cycle Time  
20  
20  
20  
20  
20  
20  
4
tCYC  
1
12tCK  
NOTES  
1AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1 and VIL max for  
a Logic 0.  
2For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the  
loaded VOH/VOL level occurs.  
3CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted.  
4ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12.  
tCKR  
tCKH  
tCKL  
tCKF  
tCK  
Figure 49. XTAL 1 Input  
DV – 0.5V  
DD  
V
– 0.1V  
V
V
– 0.1V  
LOAD  
LOAD  
0.2V + 0.9V  
TEST POINTS  
TIMING  
REFERENCE  
POINTS  
CC  
V
V
LOAD  
LOAD  
0.2V – 0.1V  
CC  
– 0.1V  
V
+ 0.1V  
LOAD  
LOAD  
0.45V  
Figure 50. Timing Waveform Characteristics  
–46–  
REV. B  
ADuC812  
12 MHz  
Max  
Variable Clock  
Min Max  
Parameter  
Min  
Unit  
Figure  
EXTERNAL PROGRAM MEMORY  
tLHLL  
tAVLL  
tLLAX  
tLLIV  
tLLPL  
tPLPH  
tPLIV  
tPXIX  
tPXIZ  
tAVIV  
tPLAZ  
tPHAX  
ALE Pulsewidth  
127  
43  
53  
2tCK – 40  
tCK – 40  
tCK – 30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
52  
52  
52  
52  
52  
52  
52  
52  
52  
52  
52  
52  
Address Valid to ALE Low  
Address Hold after ALE Low  
ALE Low to Valid Instruction In  
ALE Low to PSEN Low  
234  
145  
4tCK – 100  
3tCK – 105  
53  
205  
tCK – 30  
3tCK – 45  
PSEN Pulsewidth  
PSEN Low to Valid Instruction In  
Input Instruction Hold after PSEN  
Input Instruction Float after PSEN  
Address to Valid Instruction In  
PSEN Low to Address Float  
Address Hold after PSEN High  
0
0
0
0
59  
312  
25  
tCK – 25  
5tCK – 105  
25  
MCLK  
tLHLL  
ALE (O)  
tAVLL  
tLLPL  
tPLPH  
tLLIV  
tPLIV  
PSEN (O)  
tPXIZ  
tPLAZ  
tLLAX  
tPXIX  
INSTRUCTION  
(IN)  
PORT 0 (I/O)  
PORT 2 (O)  
PCL (OUT)  
tAVIV  
tPHAX  
PCH  
Figure 51. External Program Memory Read Cycle  
REV. B  
–47–  
ADuC812  
12 MHz  
Min  
Variable Clock  
Parameter  
Max  
Min  
Max  
Unit  
Figure  
EXTERNAL DATA MEMORY READ CYCLE  
tRLRH  
tAVLL  
tLLAX  
tRLDV  
tRHDX  
tRHDZ  
tLLDV  
tAVDV  
tLLWL  
tAVWL  
tRLAZ  
tWHLH  
RD Pulsewidth  
400  
43  
48  
6tCK – 100  
tCK – 40  
tCK – 35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
53  
53  
53  
53  
53  
53  
53  
53  
53  
53  
53  
53  
Address Valid after ALE Low  
Address Hold after ALE Low  
RD Low to Valid Data In  
Data and Address Hold after RD  
Data Float after RD  
ALE Low to Valid Data In  
Address to Valid Data In  
ALE Low to RD or WR Low  
Address Valid to RD or WR Low  
RD Low to Address Float  
RD or WR High to ALE High  
252  
5tCK – 165  
0
0
97  
2tCK –70  
517  
585  
300  
8tCK – 150  
9tCK – 165  
3tCK + 50  
200  
203  
3tCK – 50  
4tCK – 130  
0
123  
0
43  
tCK – 40  
6tCK – 100  
MCLK  
ALE (O)  
tWHLH  
PSEN (O)  
tLLDV  
tLLWL  
tRLRH  
RD (O)  
tAVWL  
tRLDV  
tRHDZ  
tLLAX  
tRHDX  
tAVLL  
tRLAZ  
A0–A7 (OUT)  
DATA (IN)  
PORT 0 (I/O)  
PORT 2 (O)  
tAVDV  
A16–A23  
A8–A15  
Figure 52. External Data Memory Read Cycle  
–48–  
REV. B  
ADuC812  
12 MHz  
Min  
Variable Clock  
Parameter  
Max  
Min  
Max  
Unit  
Figure  
EXTERNAL DATA MEMORY WRITE CYCLE  
tWLWH  
tAVLL  
tLLAX  
tLLWL  
tAVWL  
tQVWX  
tQVWH  
tWHQX  
tWHLH  
WR Pulsewidth  
400  
43  
48  
200  
203  
33  
433  
33  
6tCK – 100  
tCK – 40  
tCK – 35  
3tCK – 50  
4tCK – 130  
tCK – 50  
7tCK – 150  
tCK – 50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
54  
54  
54  
54  
54  
54  
54  
54  
54  
Address Valid after ALE Low  
Address Hold after ALE Low  
ALE Low to RD or WR Low  
Address Valid to RD or WR Low  
Data Valid to WR Transition  
Data Setup Before WR  
300  
123  
3tCK + 50  
6tCK – 100  
Data and Address Hold after WR  
RD or WR High to ALE High  
43  
tCK – 40  
MCLK  
ALE (O)  
tWHLH  
PSEN (O)  
tLLWL  
tWLWH  
WR (O)  
tAVWL  
tLLAX  
tQVWX  
tWHQX  
tAVLL  
tQVWH  
DATA  
A0–A7  
A16–A23  
A8–A15  
PORT 2 (O)  
Figure 53. External Data Memory Write Cycle  
REV. B  
–49–  
ADuC812  
12 MHz  
Min Typ Max  
Variable Clock  
Typ  
Parameter  
Min  
Max  
Unit  
Figure  
UART TIMING (Shift Register Mode)  
tXLXL  
tQVXH  
tDVXH  
tXHDX  
tXHQX  
Serial Port Clock Cycle Time  
Output Data Setup to Clock  
Input Data Setup to Clock  
Input Data Hold after Clock  
Output Data Hold after Clock  
1.0  
12tCK  
µs  
ns  
ns  
ns  
ns  
55  
55  
55  
55  
55  
700  
300  
0
10tCK – 133  
2tCK + 133  
0
50  
2tCK – 117  
ALE (O)  
tXLXL  
TxD  
6
7
0
1
(OUTPUT CLOCK)  
SET RI  
OR  
SET TI  
tQVXH  
tXHQX  
RxD  
(OUTPUT DATA)  
LSB  
MSB  
BIT6  
BIT1  
tDVXH  
tXHDX  
RxD  
(INPUT DATA)  
MSB  
BIT6  
BIT1  
LSB  
Figure 54. UART Timing in Shift Register Mode  
–50–  
REV. B  
ADuC812  
Parameter  
Min  
Max  
Unit  
Figure  
I2C-COMPATIBLE INTERFACE TIMING  
tL  
tH  
SCLOCK Low Pulsewidth  
4.7  
4.0  
0.6  
100  
0
0.6  
0.6  
µs  
µs  
µs  
ns  
µs  
µs  
µs  
56  
56  
56  
56  
56  
56  
56  
SCLOCK High Pulsewidth  
Start Condition Hold Time  
Data Setup Time  
tSHD  
tDSU  
tDHD  
tRSU  
tPSU  
tBUF  
Data Hold Time  
0.9  
Setup Time for Repeated Start  
Stop Condition Setup Time  
Bus Free Time between a STOP  
Condition and a START Condition  
Rise Time of Both SCLOCK and SDATA  
Fall Time of Both SCLOCK and SDATA  
Pulsewidth of Spike Suppressed  
1.3  
µs  
ns  
ns  
ns  
56  
56  
56  
56  
tR  
tF  
tSUP  
300  
300  
50  
1
NOTE  
1Input filtering on both the SCLOCK and SDATA inputs suppress noise spikes which are less than 50 ns.  
tBUF  
tSUP  
tR  
SDATA (I/O)  
MSB  
LSB  
ACK  
MSB  
tDSU  
tDSU  
tSHD  
tDHD  
tDHD  
tRSU  
tR  
tH  
tPSU  
SCLK (I)  
1
2-7  
8
9
1
PS  
S(R)  
tF  
tSUP  
tL  
STOP  
START  
REPEATED  
START  
CONDITION CONDITION  
Figure 55. I2C-Compatible Interface Timing  
REV. B  
–51–  
ADuC812  
Parameter  
Min  
Typ  
Max  
Unit  
Figure  
SPI MASTER MODE TIMING (CPHA = 1)  
tSL  
tSH  
SCLOCK Low Pulsewidth  
SCLOCK High Pulsewidth  
Data Output Valid after SCLOCK Edge  
Data Input Setup Time before SCLOCK Edge  
Data Input Hold Time after SCLOCK Edge  
Data Output Fall Time  
Data Output Rise Time  
SCLOCK Rise Time  
SCLOCK Fall Time  
330  
330  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
57  
57  
57  
57  
57  
57  
57  
57  
57  
tDAV  
tDSU  
tDHD  
tDF  
tDR  
tSR  
50  
100  
100  
10  
10  
10  
10  
25  
25  
25  
25  
tSF  
SCLOCK  
(CPOL=0)  
tSL  
tSH  
tSR  
tSF  
SCLOCK  
(CPOL=1)  
tDAV  
tDF  
tDR  
LSB  
MSB  
BIT 6 – 1  
MOSI  
MISO  
LSB IN  
MSB IN  
BIT 6 – 1  
tDHD  
tDSU  
Figure 56. SPI Master Mode Timing (CPHA = 1)  
–52–  
REV. B  
ADuC812  
Parameter  
Min  
Typ  
Max  
Unit  
Figure  
SPI MASTER MODE TIMING (CPHA = 0)  
tSL  
tSH  
tDAV  
tDOSU  
tDSU  
tDHD  
tDF  
tDR  
tSR  
tSF  
SCLOCK Low Pulsewidth  
SCLOCK High Pulsewidth  
Data Output Valid after SCLOCK Edge  
Data Output Setup before SCLOCK Edge  
Data Input Setup Time before SCLOCK Edge  
Data Input Hold Time after SCLOCK Edge  
Data Output Fall Time  
Data Output Rise Time  
SCLOCK Rise Time  
SCLOCK Fall Time  
330  
330  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
58  
58  
58  
58  
58  
58  
58  
58  
58  
58  
50  
150  
100  
100  
10  
10  
10  
10  
25  
25  
25  
25  
SCLOCK  
(CPOL=0)  
tSL  
tSH  
tSF  
tSR  
SCLOCK  
(CPOL=1)  
tDAV  
tDF  
tDOSU  
tDR  
MSB  
BIT 6 – 1  
LSB  
MOSI  
MISO  
BIT 6 – 1  
MSB IN  
LSB IN  
tDSU tDHD  
Figure 57. SPI Master Mode Timing (CPHA = 0)  
REV. B  
–53–  
ADuC812  
Parameter  
Min  
Typ  
Max  
Unit  
Figure  
SPI SLAVE MODE TIMING (CPHA = 1)  
tSS  
tSL  
tSH  
tDAV  
tDSU  
tDHD  
tDF  
tDR  
tSR  
SS to SCLOCK Edge  
SCLOCK Low Pulsewidth  
SCLOCK High Pulsewidth  
Data Output Valid after SCLOCK Edge  
Data Input Setup Time before SCLOCK Edge  
Data Input Hold Time after SCLOCK Edge  
Data Output Fall Time  
Data Output Rise Time  
SCLOCK Rise Time  
SCLOCK Fall Time  
SS High after SCLOCK Edge  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
59  
59  
59  
59  
59  
59  
59  
59  
59  
59  
59  
330  
330  
50  
100  
100  
10  
10  
10  
10  
25  
25  
25  
25  
tSF  
tSFS  
0
SS  
tSFS  
tSS  
SCLOCK  
(CPOL=0)  
tSL  
tSH  
tSF  
tSR  
SCLOCK  
(CPOL=1)  
tDAV  
tDR  
tDF  
MISO  
MOSI  
LSB  
MSB  
BIT 6 – 1  
LSB IN  
MSB IN  
BIT 6 – 1  
tDSU  
tDHD  
Figure 58. SPI Slave Mode Timing (CPHA = 1)  
–54–  
REV. B  
ADuC812  
Parameter  
Min  
Typ  
Max  
Unit  
Figure  
SPI SLAVE MODE TIMING (CPHA = 0)  
tSS  
tSL  
tSH  
tDAV  
tDSU  
tDHD  
tDF  
tDR  
tSR  
SS to SCLOCK Edge  
SCLOCK Low Pulsewidth  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
330  
330  
SCLOCK High Pulsewidth  
Data Output Valid after SCLOCK Edge  
Data Input Setup Time before SCLOCK Edge  
Data Input Hold Time after SCLOCK Edge  
Data Output Fall Time  
Data Output Rise Time  
SCLOCK Rise Time  
SCLOCK Fall Time  
Data Output Valid after SS Edge  
SS High after SCLOCK Edge  
50  
100  
100  
10  
10  
10  
10  
25  
25  
25  
25  
20  
tSF  
tDOSS  
tSFS  
SS  
tSFS  
tSS  
SCLOCK  
(CPOL=0)  
tSH  
tSL  
tSR  
tSF  
SCLOCK  
(CPOL=1)  
tDAV  
tDOSS  
tDF  
tDR  
MSB  
BIT 6 – 1  
LSB  
MISO  
MOSI  
BIT 6 – 1  
MSB IN  
LSB IN  
tDSU tDHD  
Figure 59. SPI Slave Mode Timing (CPHA = 0)  
REV. B  
–55–  
ADuC812  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
52-Lead Plastic Quad Flatpack  
(S-52)  
0.094 (2.39)  
0.084 (2.13)  
0.557 (14.15)  
0.537 (13.65)  
SQ  
0.037 (0.95)  
0.026 (0.65)  
52  
40  
1
39  
PIN 1  
SEATING  
PLANE  
0.398 (10.11)  
0.390 (9.91)  
TOP VIEW  
SQ  
(PINS DOWN)  
0.012 (0.30)  
0.006 (0.15)  
13  
27  
14  
26  
0.008 (0.20)  
0.006 (0.15)  
0.014 (0.35)  
0.010 (0.25)  
0.025 (0.65)  
BSC  
0.082 (2.09)  
0.078 (1.97)  
Revision History  
Location  
Page  
Data Sheet changed from REV. A to REV. B.  
Entire Data Sheet has been revised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All  
–56–  
REV. B  

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