Agilent Technologies FS2010 User Manual

FuturePlus Systems Corporation  
FS2010 Users Manual  
For use with Agilent Logic Analyzers  
Revision – 1.1  
Copyright 2005 FuturePlus® Systems Corporation  
FuturePlus is a trademark of FuturePlus Systems Corporation  
Use of EyeFinder/Eyescan .............................................................................27  
Transaction Viewer.................................................................................. 28  
General Information................................................................................ 29  
Characteristics................................................................................................29  
State/Timing Adapter Probe Interface Compatibility ...............................................29  
Card Edge Extender Connector ................................................................................29  
Standards Supported.................................................................................................29  
Power Requirements.................................................................................................29  
Logic Analyzer Required..........................................................................................29  
Number of Probes Used............................................................................................29  
Minimum Clock Period (State).................................................................................29  
Etch length................................................................................................................30  
Operations.................................................................................................................30  
Environmental Temperature .....................................................................................30  
Altitude .....................................................................................................................30  
Humidity...................................................................................................................30  
Testing and Troubleshooting ....................................................................................30  
Servicing...................................................................................................................30  
Signal Connections.........................................................................................30  
The State/Timing Adapter Probe interface pinout....................................................30  
J2 Signal Connector ................................................................................ 31  
J3 Signal Connections ............................................................................. 33  
J4 Signal Connections ............................................................................. 35  
3
How to reach us  
For Technical Support:  
FuturePlus Systems Corporation  
36 Olde English Road  
Bedford NH 03110  
TEL: 603-471-2734  
FAX: 603-471-2738  
For Sales and Marketing Support:  
FuturePlus Systems Corporation  
TEL: 719-278-3540  
FAX: 719-278-9586  
FuturePlus Systems has technical sales representatives in several  
major countries. For an up to date listing please see  
Agilent Technologies is also an authorized reseller of many  
FuturePlus products. Contact any Agilent Technologies sales office  
for details.  
4
Product Warranty  
This FuturePlus Systems product has a warranty against defects in material and  
workmanship for a period of 1 year from the date of shipment. During the  
warranty period, FuturePlus Systems will, at its option, either replace or repair  
products proven to be defective. For warranty service or repair, this product must  
be returned to the factory.  
Due to the complex nature of the FS2010 and the wide variety of customer  
target implementations, the FS2010 has a 30 day acceptance period by the  
customer from the date of receipt. If the customer does not contact  
FuturePlus Systems within 30 days of the receipt of the product it will be said that  
the product has been accepted by the customer. If the customer is not satisfied  
with the FS2010 they may return the FS2010 within 30 days for a refund.  
For products returned to FuturePlus Systems for warranty service, the Buyer  
shall prepay shipping charges to FuturePlus Systems and FuturePlus Systems  
shall pay shipping charges to return the product to the Buyer. However, the  
Buyer shall pay all shipping charges, duties, and taxes for products returned to  
FuturePlus Systems from another country.  
FuturePlus Systems warrants that its software and hardware designated by  
FuturePlus Systems for use with an instrument will execute its programming  
instructions when properly installed on that instrument. FuturePlus Systems does  
not warrant that the operation of the hardware or software will be uninterrupted or  
error-free.  
The foregoing warranty shall not apply to defects resulting from improper or  
inadequate maintenance by the Buyer, Buyer-supplied software or interfacing,  
unauthorized modification or misuse, operation outside of the environmental  
specifications for the product, or improper site preparation or maintenance. NO  
OTHER WARRANTY IS EXPRESSED OR IMPLIED. FUTUREPLUS SYSTEMS  
SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF  
Limitation of  
Warranty  
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  
THE REMEDIES PROVIDED HEREIN ARE BUYER’S SOLE AND EXCLUSIVE  
REMEDIES. FUTUREPLUS SYSTEMS SHALL NOT BE LIABLE FOR ANY  
DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL  
DAMAGES, WHETHER BASED ON CONTRACT, TORT, OR ANY OTHER  
LEGAL THEORY.  
Exclusive Remedies  
Assistance  
Product maintenance agreements and other customer assistance agreements  
are available for FuturePlus Systems products. For assistance, contact  
Technical Support.  
5
Introduction  
The FS2010 is a 32/64 bit, 0 to 133Mhz PCI-X State and Timing adapter probe  
for use with Agilent logic analyzers. This card has a universal card edge  
connector and a 3.3v extender card connector. The FS2010 PCI-X State/Timing  
adapter probe and extender card performs three functions.  
The first is to act as an extender card, physically extending a module up  
approximately 1.5 inches from the motherboard connector.  
The second is to provide a complete timing analysis interface between any  
PCI-X add-in slot and Agilent Logic Analyzers.  
The third is to provide a complete state analysis interface and software  
decode of the PCI-X traffic between any PCI-X add-in slot and Agilent Logic  
Analyzers.  
The State/Timing Adapter Probe interface is a passive bus monitor which does  
not assert any signals on the PCI-X bus. Because the FS2010 interface does  
not actively buffer the PCI-X bus signals, negligible skew is introduced.  
The configuration software on the diskette sets up the format menu of the logic  
analyzer for compatibility with your PCI-X bus.  
This manual is organized to help you quickly find the information you need.  
How to Use This  
Manual  
Analyzing the PCI-X Local Bus chapter introduces you to the FS2010 and  
lists the minimum equipment required and accessories supplied for PCI-X  
bus analysis.  
The State Analysis chapter explains how to configure the FS2010 to  
perform state analysis on your PCI-X bus.  
The Timing Analysis chapter explains how to configure the FS2010 to  
perform timing analysis on your PCI-X bus.  
The General Information chapter provides information on the operating  
characteristics, the test point and cable header pinout and the mechanical  
drawing for the FS2010 module.  
6
Analyzing the PCI-X  
Local Bus  
This chapter introduces you to the FS2010 and lists the minimum  
equipment required and accessories supplied for PCI-X Local Bus  
analysis. This chapter also contains information that is common to both  
state and timing analysis.  
The FS2010 product consists of the following accessories:  
Accessories  
Supplied  
The FS2010 probe.  
1 Diskette containing the configuration files and the FS2010 PCI-X  
decoder for 167xx analyzer.  
A CD containing the setup file to install the configuration files and  
protocol decoder on the 1680/90/900 analyzer or to use as an offline  
viewer.  
This operating manual on CD, Quick Start sheet, and SW  
Entitlement certificates for the software.  
The minimum equipment required for analysis of a PCI-X Local Bus  
consists of the following equipment:  
Minimum Equipment  
Required  
Agilent 16700 analysis frame with the 16715 analyzer card or better.  
Revision 2.80.00 or better of the Agilent Logic analysis frame  
software.  
1680/90/900 Logic analyzer or PC containing Agilent 1680/90/900  
OS version 3.00.00 or better.  
The FS2010 Product  
A PCI-X target bus  
The type of logic analyzer card used will determine the correct type of  
termination adapter needed. For analyzer cards that use the 40 pin  
header, 1671x, 1674x, 16750/1/2, 1691x you will need the E5385A  
Additional  
Equipment Required  
(FuturePlus number is FS1015) termination adapter cables.  
For  
analyzer cards that use the 90 pin header, 16753/4/5/6, 1695x you will  
need the E5378A (FuturePlus number is FS1014) termination adapter.  
A total of 3 adapter cables are required for 64 bit data width capture.  
7
This operating manual uses the same signal notation as the PCI-X  
LOCAL BUS SPECIFICATION - REVISION 1.0 That is, a # symbol at the  
end of a signal name indicates that the signal’s active state occurs when  
it is at a low voltage. The absence of a # symbol indicates that the signal  
is active at a high voltage.  
Signal Naming  
Conventions  
When connecting the logic analyzer cards to the FS2010 it is necessary  
to know which logic analyzer card in which slot has been configured as  
the Master and which one has been configured as the Expander. Refer  
to the SYSTEM view of your 1670x or 1690x mainframe to determine  
how the cards have been configured.  
Determining which  
logic analyzer card is  
the Master  
8
Configuration Files  
167xx Analyzer 169xx Analyzer File name for  
State/Timing Analysis  
Description  
16715/6/7/9 or  
1674X or  
16750/1/2  
1680/90,  
16750/1/2,  
1691x  
CP210_1  
*2 card state  
analysis  
16715/6/7/9 or  
1674X or  
16750/1/2  
1680/90,  
16750/1/2,  
1691x  
CP210_2  
CP210_3  
*2 card timing  
16715/6/7/9 or  
1674X or  
16750/1/2  
1680/90,  
16750/1/2,  
1691x  
1 card eyefinder  
config  
16753/4/5/6  
16753/4/5/6,  
1691x  
CP210_4  
1 card eyescan  
config  
*For 32 bit analysis load the timing or state configuration file into a single  
logic analyzer card. If you are using a 16910 card then only one card is  
required for 64 bit analysis.  
9
The following explains how to connect the logic analyzer to the FS2010  
for either state or timing analysis:  
Connecting the  
167xx Agilent logic  
analyzer to the  
FS2010  
1. Connect the logic analyzer PODs 3 adapter cables, either the  
E5378A or E5385A depending on the logic analyzer cards used.  
2. Plug the Adapter cables into the probe as shown in the table  
below.  
167XX/1655X  
PCI-X Analysis Probe  
connector  
Comment  
Master POD 1  
Master POD 2  
Master POD 3  
Master POD 4  
Expander POD 1  
Expander POD 2  
J2 odd  
J2 even  
J3 odd  
J3 even  
J4 odd  
J4 odd  
J CLK  
optional 64 bit  
optional 64 bit  
The card edge connector of the FS2010 module can accommodate one  
64 or 32 bit 3.3V PCI-X add-in card. To install simply align the module  
with the connector and gently push the module in until it is seated in the  
connector. There is sufficient clearance for the add-in card front plate.  
The FS2010/PCI-X add-in card combination can then be installed in any  
slot of the PCI-X Local bus.  
How to install a PCI-X  
add-in card into the  
FS2010  
When removing the PCI-X add-in card from the card edge extender  
connector grasp the FS2010 with one hand and the PCI-X add-in card  
with the other. Gently rock the PCI-X add-in card until it is free from the  
connector.  
The nature of an extender card is that it extends the etch length of the  
bus. Due to the sensitivity of some PCI-X designs, extending the etch  
length can interfere with the PCI-X add-in card operation. Operation of  
the PCI-X add-in card when installed in the card edge extender  
connector is not guaranteed.  
System operation with  
the PCI-X add-in card  
10  
To install the FS2010 software, insert the diskette labeled 16700/702  
Installation disk for the FS2010 into the Agilent 16700 diskette drive.  
From the SYSTEM ADMINISTRATION TOOLS select INSTALL under  
SOFTWARE. From the SOFTWARE INSTALL screen select the  
FLEXIBLE DISK and APPLY. Once the title appears select it and then  
select INSTALL.  
Setting up the 167xx  
Analyzer  
This procedure does not need to be repeated. It only needs to be  
done the first time the PCI-X Analysis Probe is used.  
When this has completed, load the appropriate configuration file from the  
/configs/FuturePlus/FS2010 directory. Refer to the table on the following  
pages for a list of analyzers and corresponding configuration files.  
The FS2010 product is a licensed product, which is locked to a single  
Agilent 1670x frame. Complete instructions for licensing this software  
are detailed on the Entitlement Certificate that is enclosed with this  
product.  
167xx  
Licensing  
The licensing area for the 1670x mainframe is found under System  
Administration. Once you are at the licensing area choose the  
Processor/Bus Solutions tab, in here you will find the PCIX inverse  
assembler listed. Type your password in the space provided to enable  
the use of the inverse assembler. A demo period is provided by typing  
the word demo into the password space next to the product name.  
The following picture shows the licensing area after pressing the  
licensing button on the previous screen. This is where you would enter  
the password you will receive after following the instructions on the SW  
License Entitlement Certificate.  
11  
The 1680/90/900 Analyzer is a PC based application that requires a PC  
running Windows OS with the Agilent logic analyzer software installed or  
a 16900 frame.  
Setting up the  
1680/90/900 Analyzer  
Before installing the protocol decoder for the PCI-X protocol on a PC you  
must install the Agilent logic analyzer software. Once the Agilent logic  
analyzer software is installed, you can install the FS2010 protocol  
decoder by placing the CD-ROM disk into the CD-ROM drive of the  
target computer or Analyzer and executing the .exe setup program that  
is contained on the disk. The .exe setup file can be executed from within  
the File Explorer PC Utility. You must navigate to the .exe file on the CD-  
ROM disk and then double click the .exe file name from within the File  
Explorer navigation panel.  
The installation procedure does not need to be repeated. It only  
needs to be done the first time the Analysis Probe Adapter is used.  
The PCI Inverse Assembler is a licensed product that is locked to a  
single hard drive. The licensing process is performed by Agilent. There  
are instructions on this process on the 16900 SW Entitlement certificate  
provided with this product.  
1680/90/900  
Licensing  
Loading 1680/90/900  
configuration files  
When the software has been licensed you should be ready to load a  
configuration file. You can access the configuration files by clicking on  
the folder that was placed on the desktop. When you click on the folder  
it should open up to display all the configuration files to choose from. If  
you put your mouse cursor on the name of the file a description will  
appear telling you what the setup consists of, once you choose the  
configuration file that is appropriate for your configuration the 16900  
operating system should execute. The protocol decoder automatically  
loads when the configuration file is loaded. If the decoder does not load,  
you may load it by selecting tools from the menu bar at the top of the  
screen and select the decoder from the list.  
For a diagram on logic analyzer cable attachment to the probe click the  
properties button on the General Purpose Probe icon from the overview  
tab. When you click the Properties button another window will open  
showing what pods are attached to each cable. If you select one of the  
entries from the list in the window another window will open up showing  
the signal name on each pin of the connector the cables are attached to.  
Connecting the  
1680/90/9xx Agilent  
logic analyzer to the  
FS2010  
Refer to the table on page 9 for a list of analyzers and corresponding  
configuration files.  
12  
Data that is saved on a 167xx analyzer in fast binary format, or 16900  
analyzer data saved as a *.ala file, can be imported into the 1680/90/900  
environment for analysis. You can do offline analysis on a PC if you  
have the 1680/90/900 operating system installed on the PC, if you need  
this software please contact Agilent.  
Offline Analysis  
Offline analysis allows a user to be able to analyze a trace offline at a PC  
so it frees up the analyzer for another person to use the analyzer to  
capture data.  
If you have already used the license that was included with your package  
on a 1680/90/900 analyzer and would like to have the offline analysis  
feature on a PC you may buy additional licenses, please contact  
FuturePlus sales department.  
In order to view decoded data offline, after installing the 1680/90/900  
operating system on a PC, you must install the FuturePlus software.  
Please follow the installation instructions for “Setting up 1680/90/900  
analyzer”. Once the FuturePlus software has been installed and  
licensed follow these steps to import the data and view it.  
From the desktop, double click on the Agilent logic analyzer icon. When  
the application comes up there will be a series of questions, answer the  
first question asking which startup option to use, select Continue Offline.  
On the analyzer type question, select Cancel. When the application  
comes all the way up you should have a blank screen with a menu bar  
and tool bar at the top.  
For data from a 1680/90/900 analyzer, open the .ala file using the File,  
Open menu selections and browse to the desired .ala file.  
For data from a 16700, choose File -> Import from the menu bar, after  
selecting import select “yes” when it asks if the system is ready to import  
16700 data.  
13  
After clicking “next” you must browse for the fast binary data file you  
want to import. Once you have located the file and clicked start import,  
the data should appear in the listing.  
After the data has been imported you must load the protocol decoder  
before you will see any decoding. To load the decoder select Tools from  
the menu bar, when the drop down menu appears select Inverse  
Assembler, then choose the name of the decoder for your particular  
product. The figure below is a general picture; please choose the  
appropriate decoder for the trace you are working with.  
14  
After the decoder has loaded, select Preferences if required, from the  
overview screen and set the preferences to their correct value in order to  
decode the trace properly. This is a general requirement, some  
decoders do not have preferences, and if this is the case then no  
preference setting is necessary.  
15  
The FS2010 diskette sets up the format menu as shown in the following  
table. This format is the same for both Timing and State Analysis.  
The Format Menu  
Label  
Clk Inputs Pod 6 Pod 5 Pod 4  
Pod 3  
Pod 2  
Pod 1  
10:3  
ADDR  
11,10,9,8,6,5,4,3  
11,10,9,6,5,4,3,2  
8,7,6,5,3,2,1,0  
ADDR_B  
STAT  
15:0  
15:0  
15:0  
15:0  
K,J,M,L,K  
J
14,13,7,2,1  
12,1,0  
11,2,1  
CLK  
AD_HI  
AD_LO  
FRAME#  
IRDY#  
11,10,9,8,6,5,4,3  
14  
11,10,9,6,5,4,3,2  
8,7,6,5,3,2,1,0  
10:3  
2
TRDY#  
STOP#  
DEVSEL#  
C/B3_0  
C/B7_4  
ACK64#  
REQ64#  
PAR  
M
13  
1
1
L,K  
K,J  
7
1
12  
0
2
12  
PAR_64  
REQ#  
0
GNT#  
10  
11  
SERR#  
PERR#  
RST#  
13  
14  
PCIXCAP  
INTD_A#  
IDSEL  
0
15,14  
4
15,14  
LOCK#  
M66EN  
PME#  
15  
8
9
CYCLE  
TERM CODE  
M,L,K  
M
14,13,7  
13  
12  
2,1  
1
16  
Loading the configuration file will automatically load the PCI-X  
Transaction Decode software onto the workspace. If this does not  
happen then check to make sure that the PCI-X decode software was  
properly installed  
The PCI-X  
Transaction Decode  
Software  
17  
FS2010 Software and  
Timing mode  
The FS2010 Decoder should NOT be run when the logic analyzer is  
configured in timing mode. This will cause the system to hang.  
The ADDR and DATA variables in the FORMAT menu are assigned to  
the AD[31:0] signals on the PCI-X bus. The ADDR_B is the AD[63:32]  
signals on the PCI-X bus.  
The ADDR, ADDR_B and  
DATA variables  
18  
The CYCLE variable is made up of the following signals: TRDY#,  
FRAME#, IRDY#, C/BE(3:0), DEVSEL# , and STOP#. This variable has  
27 symbols defined that can be used to help make triggering, timing  
analysis and pattern filtering easier. The following lists the bit pattern  
and the corresponding symbol.  
The CYCLE variable  
Symbol  
C/BE(3:0 FRAME# IRDY# DEVSEL# TRDY# STOP#  
)
INTACK  
0000  
0
1
1
1
1
SPECIAL CYCLE  
I/O READ  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
001X  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
XXXX  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
X
X
0
0
X
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
1
0
0
1
1
I/O WRITE  
RESERVED  
RESERVED1  
MEM RD DWORD  
MEM WRITE  
MEM RD BL  
MEM WR BL  
CONF READ  
CONF WRITE  
SPLIT COMPLETION  
DAC  
MEM RD BLOCK  
MEM WR BLOCK  
IO XACTION  
ADDR CYCLE  
DATA XFER  
IDLE  
RETRY  
DISC NXT ADB  
DECODE  
SINGLE DATA DISCON  
TARGET ABORT  
TARGET RESPONSE (WAIT)  
WAIT  
19  
The TERM CODE variable is made up of DEVSEL#, TRDY#, and  
STOP#. The following lists the bit pattern and the corresponding symbol.  
Symbol  
DEVSEL# TRDY#  
STOP#  
MASTER ABORT  
SPLIT RESPONSE  
TARGET ABORT  
SINGLE DATA DISC  
RETRY  
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
0
0
DISC NXT ADB  
The hardware layout of the FS2010 made it impossible for the signals to  
be connected to the logic analyzer in a logical order. Therefore, bit re-  
ordering is done in the configuration file to make the data easier to view.  
The bit re-ordering function can be found in the FORMAT menu.  
Bit Re-ordering  
Below is a list of labels that have been re-ordered  
ADDR  
ADDR_B  
STAT  
AD_HI  
AD_LO  
C/B3_0  
CYCLE  
TERM CODE  
20  
State Analysis  
This chapter explains how to configure the FS2010 to perform state  
analysis on the PCI-X Local Bus. The configuration software sets up the  
format specification menu of the logic analyzer for compatibility with the  
PCI-X Local Bus. The next chapter explains how to configure the  
FS2010 to perform timing analysis.  
The FS2010 State/Timing Adapter Probe interface does not require that  
a PCI-X add-in card be installed in the FS2010 card edge extender  
connector.  
Load the logic analyzer configuration file and configure the workspace  
for PCI-X analysis.  
Configure the trigger menu to acquire PCI-X data. Select RUN and, as  
soon as there is activity on the bus, the logic analyzer will begin to  
acquire data. The analyzer will continue to acquire data and will display  
the data when the analyzer memory is full; the trigger specification is  
TRUE or when you select STOP.  
Acquiring Data  
The logic analyzer will flash “Slow or Missing Clock” if it does not see the  
PCI-X signal CLK toggling.  
The logic analyzer will flash “Waiting in level 1” if the trigger specification  
has not been met.  
If you are analyzing a 32 bit bus, load the configuration file for a 64 bit  
bus into a single analyzer card, the upper 64 bit labels will be truncated,  
but will work fine.  
21  
Configuring the  
Workspace for PCI-X  
Analysis  
For full analysis, the PCI-X workspace should appear as below.  
167xx screenshot  
169xx screenshot showing overview  
22  
The State Listing  
Display  
Captured data is as shown in the following figure. The below figure  
displays the PCI-X transactor decode on a 167xx frame.  
23  
The above figure shows the listing from the 169xx frame.  
24  
The FS2010 generates one output column that is sub-divided into the  
following sub-columns.  
Name  
Base  
TEXT  
Description  
CMD  
Wait  
The command type displayed in HEX  
The type of wait state  
ADDR_H  
TEXT  
HEX  
The address as it appears during a 64 bit  
address transfer (as defined by a DAC)  
ADDR_L  
The address as it appears on the lower AD  
lines (AD[31:0]). This HEX value is  
incremented during burst transactions  
Data_H  
TEXT  
TEXT  
TEXT  
HEX  
The upper 32 bit AD lines representing data  
The lower 32 bit AD lines representing data  
Termination type  
Data_L  
Termination  
CBE_H  
Data byte enables for the upper 32 bit AD  
lines (AD[63:32]).  
CBE_L  
HEX  
Data byte enables for the lower 32 bit AD  
lines (AD[31:0]).  
The FS2010 Decode Software will perform the following functions:  
Functionality of the  
FS2010 Transaction  
Decode Software  
Decode all PCI-X command and cycle types  
Decode Attribute and Split Address fields for easy reading  
Color code the data and attribute to match the transaction type  
(command). The colors used by the software are as follows:  
Memory: Green  
Split Completions are colored according to the original request  
command ID.  
I/O transactions: Yellow  
Configuration transactions: Blue  
Interrupt Acknowledge, Special Cycle transactions and the DAC  
cycle: Purple  
Idle: White  
Wait cycles: colored in accordance with the rest of the  
transaction  
Match the Request to the Response by printing the corresponding  
address aligned with the data on a Split Response. In addition the  
original command will be printed with the Split Response to indicate  
what command was originally requested  
25  
Timing Analysis  
Since the FS2010 interface does not buffer the PCI-X bus, it introduces  
negligible skew to the PCI-X Local Bus signals.  
Load the logic analyzer configuration file.  
If the FS2010 software is installed, load the logic analyzer  
configuration file for timing from the logic/configs/FuturePlus/FS2010  
directory on the 167xx analyzer. If using the 1680/90/900 double  
click the folder that was placed on the desktop during installation and  
choose the appropriate configuration file.  
Touch RUN and, as soon as there is activity on the bus, the logic  
analyzer will begin to acquire data. The analyzer will continue to acquire  
data and will display the data when the analyzer memory is full, the  
trigger specification is TRUE or when you touch STOP.  
Acquiring Data  
The logic analyzer will flash “Waiting in level 1” if the trigger specification  
has not been met.  
If you are analyzing a 32 bit bus, load the configuration file for a 64 bit  
bus into a single analyzer card, the upper 64 bit labels will be truncated,  
but will work fine.  
26  
Captured data is displayed as shown in the following figure.  
The Waveform  
Display  
Use of Eye Finder can greatly enhance your timing analysis by helping  
find the data valid window of every signal on the bus with respect to the  
clock. You can compare the results of Eye Finder to your simulation and  
the PCI-X specification to see if your system operates within expected  
Use of  
EyeFinder/Eyescan  
setup and hold margins. Eye Finder can be found in the setup and hold  
area of your logic analysis card FORMAT menu. The configuration file  
for Eyefinder, CP201_3 , has clock qualifiers defined to insure that data  
is valid during measurements.  
EyeScan features are available with 16753/4/5/6 cards that provide  
information about signal voltage as well timing windows  
Transaction Viewer  
The FS2010 Protocol Decoder version 2.0 or higher is enabled to work  
with the FuturePlus Systems Transaction Viewer. The Transaction  
Viewer is a powerful tool that allows the user to view PCI-X data  
captured with the FS2010 in a graphical environment that presents the  
information by Transaction as opposed to State. This tool is fully  
integrated with State Listing on the 16900 and allows marker and trigger  
settings to be shared between the Protocol Decoder and the Transaction  
Viewer.  
The Transaction Viewer itself is a separate application that needs to be  
downloaded from the FuturePlus Systems website:  
www.futureplus.com. The user manual for the Transaction Viewer is also  
separate and can be found either on the FuturePlus Systems  
Documentation CD on the FuturePlus Systems website.  
28  
General Information  
This chapter provides additional reference information including the  
characteristics and signal connections for the FS2010 module.  
The following operating characteristics are not specifications, but are  
typical operating characteristics for the FS2010 module.  
Characteristics  
32 or 64 bit PCI-X Local bus universal connector pinout. All PCI-X local  
bus ground pins of the universal board pinout are connected to the  
ground plane of the FS2010 module.  
State/Timing Adapter  
Probe Interface  
Compatibility  
Card Edge Extender  
Connector  
The FS2010 extender card connector is a 3.3V, 64 bit connector that  
accepts either 3.3V or universal 32 or 64 bit long or short card form  
factor. All of the signals from the PCI-X bus are routed to the card edge  
extender connector.  
Standards Supported  
Power Requirements  
The PCI-X Local Bus Specification Revision 1.0  
The FS2010 State/Timing Adapter Probe logic contains no active  
components. The PCI-X add-in card installed in the FS2010 can draw  
power from the +/-12V, 3.3V and the 5V pins of the target as if it were  
installed without the FS2010.  
Logic Analyzer Required  
Agilent 16715/6/7/9, 1674X, or 16750/1/2, 16953/4/5/6 installed in the  
16700A or 16700B mainframe. Agilent 1680/90/900, 16953/4/5/6, 1691x,  
1695x logic analyzers.  
The State/Timing Adapter Probe interface uses 4 cable headers for 32  
bit analysis and 6 for 64 bit analysis.  
Number of Probes Used  
Minimum Clock Period  
(State)  
0 to 133Mhz  
29  
Due to the FS2010 being an interposer all signals are extended 1.2 in. in  
length, consisting of 57 ohm single-ended impedance etch.  
Etch length  
Operations  
All PCI-X Local Bus operations are supported by the hardware and the  
inverse assembler.  
Environmental  
Temperature  
Operating:0 to 55 degrees C (+32 to +131 degrees F)  
Non operating:-40 to +75 degrees C (-40 to +167 degrees F)  
Operating: 4,6000m (15,000 ft)  
Altitude  
Non operating: 15,3000m (50,000 ft)  
Up to 90% non-condensing. Avoid sudden, extreme temperature  
changes which would cause condensation on the FS2010 module.  
Humidity  
There are no automatic performance tests or adjustments for the  
FS2010 module. If a failure is suspected in the FS2010 module contact  
the factory or your FuturePlus Systems authorized distributor.  
Testing and  
Troubleshooting  
The repair strategy for the FS2010 is module replacement. However, if  
parts of the FS2010 module are damaged or lost contact the factory for a  
list of replacement parts.  
Servicing  
The FS2010 contains 3 Samtec connectors which the adapter cables  
connect to. Each adapter cable contains 2 connectors to connect to the  
Agilent logic analyzer.  
Signal Connections  
The FS2010 module monitors signals for both state and timing analysis.  
The following tables list the PCI-X Local Bus signals on the 6 cables.  
The State/Timing  
Adapter Probe interface  
pinout  
30  
J2 Signal Connector  
Signal  
Name/Logical  
Signal name  
Signal  
name/Logical  
Signal Name  
Logic Analyzer  
channel number  
SAMTEC  
Pin number  
SAMTEC  
Pin number  
Logic Analyzer  
channel number  
Ground  
NC  
1
2
Ground  
NC  
3
4
Ground  
Odd D0  
Ground  
Odd D1  
Ground  
Odd D2  
Ground  
Odd D3  
Ground  
Odd D4  
Ground  
Odd D5  
Ground  
Odd D6  
Ground  
Odd D7  
Ground  
Odd D8  
Ground  
Odd D9  
Ground  
Odd D10  
Ground  
Odd 11  
Ground  
Odd D12  
5
6
Ground  
Even D0  
Ground  
Even D1  
Ground  
Even D2  
Ground  
Even D3  
Ground  
Even D4  
Ground  
Even D5  
Ground  
Even D6  
Ground  
Even D7  
Ground  
Even D8  
Ground  
Even D9  
Ground  
Even D10  
Ground  
Even D11  
Ground  
Even D12  
PCIXCAP  
DEVSEL#  
IRDY#  
AD17  
7
8
AD16  
AD18  
AD20  
AD22  
IDSEL  
AD24  
AD26  
AD28  
AD30  
PME#  
GNT#  
RESET#  
NC  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
AD19  
AD21  
AD23  
AD25  
AD27  
AD29  
AD31  
REQ#  
NC  
31  
Signal  
Name/Logical  
Signal name  
Signal  
name/Logical  
Signal Name  
Logic Analyzer  
channel number  
SAMTEC  
Pin number  
SAMTEC  
Pin number  
Logic Analyzer  
channel number  
Ground  
Odd D13  
Ground  
Odd D14  
Ground  
Odd D15  
Ground  
NC  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
Ground  
Even D13  
Ground  
Even D14  
Ground  
Even D15  
Ground  
NC  
NC  
NC  
INTD#  
INTB#  
INTC#  
INTA#  
Ground  
NC  
Ground  
NC  
Ground  
Ground  
Odd D16P/Odd  
CLKN  
Even DP16P/Even  
CLKN  
CLK  
79  
81  
83  
80  
82  
84  
C/BE3#  
Ground  
Ground  
Ground  
Odd DP16N/Odd  
CLKN  
Even DP16N/Even  
CLKN  
Ground  
Ground  
Odd External Ref  
Ground  
NC  
85  
87  
89  
91  
93  
95  
97  
99  
86  
88  
90  
92  
94  
96  
98  
100  
Ground  
Even External Ref  
Ground  
NC  
Ground  
Ground  
+5V  
Ground  
Ground  
+5V  
+5V  
+5V  
+5V  
+5V  
+5V  
32  
J3 Signal Connections  
Signal  
Name/Logical  
Signal name  
Signal  
name/Logical  
Signal Name  
Logic Analyzer  
channel number  
SAMTEC  
Pin number  
SAMTEC  
Pin number  
Logic Analyzer  
channel number  
Ground  
NC  
1
2
Ground  
NC  
3
4
Ground  
Odd D0  
Ground  
Odd D1  
Ground  
Odd D2  
Ground  
Odd D3  
Ground  
Odd D4  
Ground  
Odd D5  
Ground  
Odd D6  
Ground  
Odd D7  
Ground  
Odd D8  
Ground  
Odd D9  
Ground  
Odd D10  
Ground  
Odd 11  
Ground  
Odd D12  
5
6
Ground  
Even D0  
Ground  
Even D1  
Ground  
Even D2  
Ground  
Even D3  
Ground  
Even D4  
Ground  
Even D5  
Ground  
Even D6  
Ground  
Even D7  
Ground  
Even D8  
Ground  
Even D9  
Ground  
Even D10  
Ground  
Even D11  
Ground  
Even D12  
C/BE4#  
ACK64#  
AD1  
7
8
PAR64  
C/BE5#  
REQ64#  
AD0  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
AD3  
AD5  
AD2  
AD7  
AD4  
AD8  
AD6  
NC  
C/BE0#  
AD9  
M66EN  
AD10  
AD12  
AD14  
C/BE1#  
AD11  
AD13  
AD15  
PAR  
33  
Signal  
Name/Logical  
Signal name  
Signal  
name/Logical  
Signal Name  
Logic Analyzer  
channel number  
SAMTEC  
Pin number  
SAMTEC  
Pin number  
Logic Analyzer  
channel number  
Ground  
Odd D13  
Ground  
Odd D14  
Ground  
Odd D15  
Ground  
NC  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
Ground  
Even D13  
Ground  
Even D14  
Ground  
Even D15  
Ground  
NC  
SERR#  
PERR#  
LOCK#  
STOP#  
FRAME#  
NC  
Ground  
NC  
Ground  
NC  
Ground  
Ground  
Odd D16P/Odd  
CLKN  
Even DP16P/Even  
CLKN  
C/BE2#  
Ground  
79  
81  
83  
80  
82  
84  
TRDY#  
Ground  
Ground  
Ground  
Odd DP16N/Odd  
CLKN  
Even DP16N/Even  
CLKN  
Ground  
Odd External Ref  
Ground  
NC  
85  
87  
89  
91  
93  
95  
97  
99  
86  
88  
90  
92  
94  
96  
98  
100  
Ground  
Even External Ref  
Ground  
NC  
Ground  
Ground  
+5V  
Ground  
Ground  
+5V  
+5V  
+5V  
+5V  
+5V  
+5V  
34  
J4 Signal Connections  
Signal  
Name/Logical  
Signal name  
Signal  
name/Logical  
Signal Name  
Logic Analyzer  
channel number  
SAMTEC  
Pin number  
SAMTEC  
Pin number  
Logic Analyzer  
channel number  
Ground  
NC  
1
2
Ground  
NC  
3
4
Ground  
Odd D0  
Ground  
Odd D1  
Ground  
Odd D2  
Ground  
Odd D3  
Ground  
Odd D4  
Ground  
Odd D5  
Ground  
Odd D6  
Ground  
Odd D7  
Ground  
Odd D8  
Ground  
Odd D9  
Ground  
Odd D10  
Ground  
Odd 11  
Ground  
Odd D12  
5
6
Ground  
Even D0  
Ground  
Even D1  
Ground  
Even D2  
Ground  
Even D3  
Ground  
Even D4  
Ground  
Even D5  
Ground  
Even D6  
Ground  
Even D7  
Ground  
Even D8  
Ground  
Even D9  
Ground  
Even D10  
Ground  
Even D11  
Ground  
Even D12  
AD33  
AD35  
AD37  
AD39  
AD41  
AD43  
AD45  
AD47  
C/BE4#  
AD51  
AD53  
AD55  
AD57  
7
8
AD32  
AD34  
AD36  
AD38  
AD40  
AD42  
AD44  
AD46  
C/BE5#  
AD50  
AD52  
AD54  
AD56  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
35  
Signal  
Name/Logical  
Signal name  
Signal  
name/Logical  
Signal Name  
Logic Analyzer  
channel number  
SAMTEC  
Pin number  
SAMTEC  
Pin number  
Logic Analyzer  
channel number  
Ground  
Odd D13  
Ground  
Odd D14  
Ground  
Odd D15  
Ground  
NC  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
Ground  
Even D13  
Ground  
Even D14  
Ground  
Even D15  
Ground  
NC  
AD59  
AD61  
AD63  
AD58  
AD60  
AD62  
Ground  
NC  
Ground  
NC  
Ground  
Ground  
Odd D16P/Odd  
CLKN  
Even DP16P/Even  
CLKN  
C/BE6#  
Ground  
79  
81  
83  
80  
82  
84  
C/BE7#  
Ground  
Ground  
Ground  
Odd DP16N/Odd  
CLKN  
Even DP16N/Even  
CLKN  
Ground  
Odd External Ref  
Ground  
NC  
85  
87  
89  
91  
93  
95  
97  
99  
86  
88  
90  
92  
94  
96  
98  
100  
Ground  
Even External Ref  
Ground  
NC  
Ground  
Ground  
+5V  
Ground  
Ground  
+5V  
+5V  
+5V  
+5V  
+5V  
+5V  
36  

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