ADC MLN7400 User Manual

Cost Effective  
Network Processor  
for TCP/IP  
with ARM7TDMI™  
MLN7400  
Evaluation Board Manual  
Version 0.20  
December 31, 2003  
MCS Logic Inc.  
Copyright © 2003 MCS LOGIC Limited. All rights reserved  
EVB7400  
EVB7400  
User’s Manual V.0.10  
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Copyright © 2004 MCS LOGIC Limited. All rights reserved  
EVB7400  
Table of Contents  
User’s Manual V.0.10  
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Copyright © 2004 MCS LOGIC Limited. All rights reserved  
EVB7400  
Chapter 1 Introduction  
EVB7400 is a MLN7400 evaluation board and MCS-uClinux training kit that is suitable for code development and exploration of MN7400  
with MCS-uClinux. It includes much of the hardware and software required completing your application development. It supports various  
function related with network, communication such as IIC, SPI, UART, 10/100 Ethernet, multimedia module such as sound DAC, storage  
media such as NAND FLASH memory module. Using the JTAG interface, you can debug the EVB7400 directly.  
1.1 System Requirements  
-. Host computer : IBM compatible PC  
-. EVB7400 (Evaluation Board for MLN7400)  
-. DC 5V Power  
JTAG  
X-Tal/Osc  
PLL  
UART0~4  
ARM7TDMI  
IIC Serial  
EEPROM  
&RTC  
4 Console  
UARTs  
4KBytes  
Cache  
SPI Serial  
EEPROM  
1 high-  
speed  
UART  
Ethernet  
PHY  
(AC101L)  
10/100  
Ethernet DMA  
MAC  
DAC(CS4340)  
MIC IN  
I2C  
SPI  
Boot ROM  
(ROM Bank0)  
2ch GDMA  
GPIOs  
User Flash  
KEY  
4 channel  
ADC  
(ROM Bank1)  
MATRIX  
Peripheral  
Bridge  
Memory  
Controller  
SRAM  
(ROM Bank2)  
4 Timers  
NAND Flash  
WDT  
PCMCIA  
Socket  
(ROM Bank3)  
Status  
LEDs  
DAC I/F  
Interrupt  
Controller  
Eextenal  
Interrupt Key  
SDRAM  
[Figure 1 ] EVB7400 BLOCK DIAGRAM  
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EVB7400  
ADDRESS  
MLN7400 MAP  
EVB7400  
0x000_0000 ~ 0x0FF_FFFF  
0x100_0000 ~ 0x1FF_FFFF  
0x200_0000 ~ 0x2FF_FFFF  
0x300_0000 ~ 0x3FF_FFFF  
0x400_0000 ~ 0x5FF_FFFF  
ROM/Flash bank 0 (16Mbytes)  
ROM/Flash bank 1 (16Mbytes)  
ROM/Flash bank 2 (16Mbytes)  
ROM/Flash bank 3 (16Mbytes)  
Cacheable SDRAM area (32Mbytes)  
FLASH(512KB)  
SRAM(128KB)  
FLASH(2MB)  
PCMCIA Card  
SDRAM 64Mbits(8Mbytes)  
0x600_0000 ~ 0x600_5FFF  
(Cacheable)  
0x800_0000 ~ 0xEFF_FFFF  
(Non-Cacheable)  
0xF00_0000 ~ 0xFFF_FFFF  
SFR Registers  
[Figure 2 ] MEMORY MAP  
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EVB7400  
1.2 Board Components  
The arrangement of major components on the board is shown in Figure 3. The major components include:  
[Figure 3 ] BLOCK DIAGRAM (TOP VIEW)  
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EVB7400  
A Flash ROM  
There is a socket(U9) which accept 512Kbyte size of 8 bit Flash Memory(AT29C010 ~ 40). This is for diaganostic program(includes all  
pheriperal device driver and TCP/IP protocol stack) and BIOS(MCS-uClinux Boot loader) program.  
User Flash memory(Selectable Boot ROM)  
A mounted 48 TSOP type flash(AM29LV160BB), U8, is mounted for saving MCS-uClinux image. It has 2Mbytes(1M x 16bits)size. If you  
want to use this for boot ROM, SW2 should be set to to X16 and U9 should be removed. (The default setting is X8)  
SDRAM  
SDRAM size is 8Mbytes ( 4M x 16bits)  
SRAM  
There is a SRAM at ROM Bank1. SRAM SIZE is 64K x 16 bits.  
NAND Flash  
A mounted NAND Flash ROM is provided for saving user data.  
To use NAND flash, you should install and uninstall some 0 ohm register at bottom of board. Please refer to chapter 2 and Schemetic.  
EEPROM(AT24C256, AT25040)  
There are two EEPROM(U3, U4). One is an IIC Serial EEPROM(U3) and the other is a SPI serial EEPROM(U4).  
The size of EEPROM(U3) is 32Kbytes, and the size of EEPROM(U4) is 4Kbytes.  
RTC & Thermometer  
There is a DS1629(U5) for RTC and thermometer check. The RTC clock is supplied by the crystal(32.768KHz)  
Serial Port  
There are 5 9-pin female Serial ports for serial data communiation. One is for console between the host PC and EVB7400 and others for  
converter(Serial to Ethernet, Serial to wireless and so on). And there is one 9-pin mail Serial ports for High Speed UART.  
Ethernet Interface  
There are RJ45 connector and Ethernet Phy for network.(AC101L, 10/100 BASE-T)  
AUDIO IN/OUT  
There is a stereo DAC(CS4340) for AUDIO out. And MIC and AMP is connected to ADIN3(ADC channel3) for AUDIO In.  
Reset Button  
There is a button for system reset.  
Power On/Off Switch  
There is a swithch for power on/off.  
LED Indicatorst  
Seven LEDs are supplied on the EVB7400. Each LED shows power status, user programmable status, ethernet link and activity.  
PCMCIA Socket  
There is a PCMCIA Socket(J2). To use it, you should set ROM BANK3 as PCMCIA mode.  
JTAG Port  
One 20-pin JTAG port(J3) is supplied to connect with JTAG based Emulator.  
Expansion Connectors  
Seven connectors(JP2~JP8) are supplied for system expansion. They contain board data bus, adddress bus, external memory bank  
control, IIC, SPI, and MII signals.  
Key Matrix  
There are 12 key buttons. They can be used ADC application.  
Five buttons(SW4, SW7, SW10, SW13, SW15) are connected to ADIN0(ADC channel 0).  
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EVB7400  
Four buttons(SW5, SW8, SW11, SW14) are connected to ADIN1(ADC channel 1).  
Three buttons(SW5, SW8, SW11, SW14) are connected to ADIN2(ADC channel 2).  
External Interrrupt Key  
There are two button to use external interrupts. Each button(S1,S2) is connected to External interrupt0 and 2.  
External Timer0 Clock  
Timer0 can be supplied by the external clock(ocsillator)  
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EVB7400  
Chapter 2 Board Configuration  
The EVB7400 is set with default configuration. You can use the board with the defualt settings direclty. However, you can also change  
the settings according to your nedds.  
2.1 Endian Selection (SW1)  
Status  
Description  
BIG  
BIG Endian  
LITTLE  
BIG  
Little Endian  
LITTLE  
2.2 Boot ROM and ROM Bank0 length Selection (SW2)  
Status  
Description  
X8  
ROM BANK0 Size is 8 bits.  
ROM BANK0 : AT29C040 512 X 8bits Flash  
ROM BANK2 : AM29LV160BB 1M X 16bits Flash  
X16  
X8  
ROM BANK 0 size is 16 bits.  
ROM BANK0 : AM29LV160BB 1M X 16 bits Flash  
*Note : AT29C040(U9) should be removed  
X16  
2.3 NAND FLASH  
You can use NAND Flash through GPIO of MLN7400. To use NAND Flash you shoud install 0 ohm registance.  
Refer to schementic page4.  
Install Register reference  
R12, R13, R14, R15, R16,  
R17, R18, R19, R20, R21,  
R22, R23, R24, R25, R26  
Unintall Register Reference  
R39, R40, R41,R42, R43,  
R44, R54,R55,R56  
*Note: To use NAND Flash, you can’t use SPI Interface, Console UART3 and High Speed UART(UART4)  
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EVB7400  
2.4 GPIO Setting  
<128-TQFP/ 144 -LQFP Common I/O>  
<144 -LQFP Extended I/O>  
Setting  
Setting  
PIN  
Shared  
Initial Board Setting  
Value PIN  
Shared  
Initial  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
Board Setting  
Value  
GP00 CUTXD1  
GP01 CURXD1  
GP02 CUTXD2  
GP03 CURXD2  
GP04 CUTXD3  
GP05 CURXD3  
GP06 CUTXD4  
GP07 CURXD4  
GP08 nBE[0]  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
S,0  
S,I  
S,O  
UART1  
S, O  
S, O  
S, O  
S, O  
S, O  
S, O  
S, O  
S, O  
S, O  
S, O  
S, O  
N, O  
N, O  
S, I  
GP27  
EXT_TCLK0  
EXT_TCLK1  
EXT_TCLK2  
HUARTnDCD4  
HUARTnCTS4  
Ext Timer0 Clk  
LED 2  
S, I  
UART1  
GP28  
GP29  
GP30  
GP31  
N, O  
N, O  
N, I  
UART2  
LED 3  
UART2  
NFIO0  
UART3/NFWEN  
UART3/NFWRN  
UART4/NFALEN  
UART4/NFCLEN  
SRAM(nBE0)  
SRAM(nBE1)  
Timer0 TOUT0  
SPI SS#  
NFIO1  
N, I  
GP32(0) HUARTnRTS4  
GP33(1) HUARTnDSR4  
GP34(2) HUARTnDTR4  
GP35(3) EXINT2  
GP36(4) EXINT3  
GP37(5) TOUT[2]  
GP38(6) TOUT[3]  
GP39(7) DLRCK  
NFIO2  
N, I  
NFIO3  
N, I  
NFIO4  
N, I  
Ext Int2 Test  
NFIO5  
S, I  
GP09 nBE[1]  
N, I  
GP10 TOUT[0]  
GP11 TOUT[1]  
GP12 TX_ERR  
GP13 NTRST  
GP14 ECSN2  
NFIO6  
N, I  
NFIO7  
N, I  
LED 0  
DLRCK  
DBCK  
S, O  
S, O  
S, O  
S, O  
JTAG(nTRST)  
SRAM(ECSN2)  
PCMCIA(CE1#)  
SPI MISO/NFCEN  
SPI MOSI/NFRDN  
SPI Clock/NFRBN  
Ext Int0 Test  
PCMCIA IRQ  
LED 1  
GP40(8) DBCK  
S, O  
S, O  
S, I  
GP41(9) DMCK  
DMCK  
GP15 ECSN3/CE1# S,O  
GP42(10) DDATA  
DDATA  
GP16 SPIMISO  
GP17 SPIMOSI  
GP18 SPICLK  
GP19 EXINT0  
GP20 EXINT1  
GP21 EXT_UCLK  
N,I  
N,I  
N,I  
N,I  
N,I  
N,I  
S, O  
S, O  
S, I  
S : Special  
N : Noraml  
S, I  
I
: Input  
N, O  
O : Output  
GP22 REG#/DLRCK N,I  
PCMCIA REG#/DLRCK S, O  
PCMCIA CE2#/DBCK S, O  
GP23 CE2#/DBCK  
S,O  
GP24 IORD#/DMCK N,I  
GP25 IOWR#/DDATA N,I  
PCMCIA IORD#DMCK S, O  
PCMCIA IOWR#/DDATA S, O  
1) GP22 ~GP25  
7400P  
PCMCIA  
DAC  
GP26 ENWAIT  
N,I  
PCMCIA ENWAIT  
S, O  
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EVB7400  
Chapter 3 Setup EVB7400 Environments  
3.1 Ethernet 10/100 BASE-T Connector  
Same connector and pin for both 10Base-T and 100 Base-Tx  
< At the network interface card/hubs >  
< At the cables >  
RJ45 female connetor at the network interface cards and hubs  
RJ45 male connector at the cable  
Pin  
1
2
3
4
5
6
7
8
Name  
TX+  
TX-  
RX+  
N/C  
N/C  
RX-  
N/C  
N/C  
Descriptions  
Tranmit Data+  
Tranmit Data-  
Receive Data+  
Not Connected  
Not Connected  
Receive Data-  
Not Connected  
Not Connected  
NOTE : TX & RX are swapped on hub  
3.2 Connection Method for UTP Cable  
RJ45 pins on EVB7400 is defined to Adapter side. So, you straight connect EVB7400 to hub through UTP cable. In this case, between  
the EVB7400 and the Hub, the pin numbers correspond to each other.  
Between the EVB7400 and the NIC which is on the Host PC, you have to connect each other through UTP cable which is crossover  
patch cord.  
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EVB7400  
[Figure 4 ] UTP CABLE CONNECTION  
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EVB7400  
Chapter 4 Connection Configurations for Debug Console  
4.1  
Configuration the Hyper Terminal  
To configure the Hyper Terminal, which is a Windows utility program for serial communications, refer to following steps:  
1. Run the Hyper Terminal program  
-. Window 95/98/2000/XP start tool bar -> Program -> Accessories -> Hyper Terminal Group  
-> Double click Hyperterm.exe -> Enter a connection name -> Select a icon -> Click OK.  
2. Select COM Port to communicate with EVB7400 board.  
-. Choose COM1 or COM2 as the serial communication port and click OK.  
3. Set the serial port properties  
-. Bits per second: 57600 bps  
-. Data Bits : 8 bits  
-. Stop Bits : 1  
-. Flow control : None  
4. Select the Properties from the File menu  
[Figure 5 ] PROPERTIES SETTING PAGE  
5. Choose Setting Page.  
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EVB7400  
[Figure 6 ] CHOOSE SETTING PAGE  
6. Re-connect Hyper Terminal to run at new properties  
Disconnect : Call -> Disconnect  
Connect: Call -> Call  
7. Power-On Reset or push the reset button on EVB7400 board  
Now, the diagnostic program menu is showed on the Hyper Terminal  
4.2  
Downloading Binary Image and Flash Write  
4.2.1 Downloading Binary Image  
You can download a binary image file through the serial cable to target without an emulator.  
1. Type “ f ” to download user program to EVM7400 on Diagnostic program main menu.  
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EVB7400  
2. Type “8” at Flash Program Menu and type address to download.  
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EVB7400  
3. select the Send File from the Transfer menu  
File Name : Select the file name, which you want too download.  
Protocol : Select the Xmodem or 1K Xmodem.  
4. Click Ok.  
Then, the file that you selected will be downloaded.  
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EVB7400  
4.2.2 Flash Write  
You can write downloaded binary image at User flash memory(AM29LV160BB, U8).  
Type “2” to write an executable binary file at User Flash memory.  
Then, you can execute your image by changing Boot Rom selection switch(SW2) to X16(default is X8).  
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EVB7400  
Chapter 5 Opennice32 Installation  
5.1 OPENice32  
The OPENice32 can also be connected with the EVB7400 as a debugging system for software applications development. OPENice32 is  
a JTAG-based, nonintrusive, debugging system for ARM-based controllers or processors. JTAG provides the interface between a  
debugger and the ARM-based controller development board.  
To use the OPENice32, the following additional equipment are required:  
- OPENice32  
- 14-way ribbon cable  
- 9-pin RS232 cable or parallel cable  
- 5 V DC (Max. 3A) power supply  
5.2 Connecting EVB7400 and PC  
The OPENice32 should be connected to the EVB7400's JTAG Port (J3) via a 20-way cable, and to the host PC via a 9-pin RS232 serial  
or parallel cable.  
To power on the OPENice32, DC 5 V power supply is  
required.  
EVB7400  
[Figure 7 ] CONNECTING WITH OPENICE32  
5.3 Powering up the Board and OPENice32  
We recommend that you power on the EVB7400 before the OPENice32 is powered on. In this way, the system initialization and memory  
configuration for EVB7400 performed by the Boot Code can be completed first.  
Otherwise, it may cause the failure of code download via JTAG.  
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EVB7400  
Chapter 6 EVB7400 1.0 Schemetic and BOM  
6.1 EVB7400 BOM  
No. PART NO  
GEOMETRY  
COUNT  
DESCRIPTION  
REFERENCE  
Vendor  
1
2
3
4
5
6
7
8
MLN7400  
144LQFP  
128TQFP  
8 SOIC  
8 SOIC  
8 SOIC  
44TSOP  
54TSOP  
48TSOP  
32DIP  
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
Microprocessor  
Microprocessor  
EEPROM(IIC)  
EEPROM(SPI)  
RTC  
SRAM  
SDRAM  
Flash  
Flash  
U1  
U2  
U3  
U4  
U5  
U6  
U7  
U8  
MCS Logic  
MCS Logic  
Atmel  
Atmel  
Dallas  
Samsung  
Samsung  
AMD  
Atmel  
Altima  
MLN7400P  
AT24C256  
AT25040  
DS1629  
K6R1016V1D  
K4S641632  
AM29LV160BB  
AT29C040A  
AC101L  
H1102  
MAX3232  
74LVC14  
74LV08  
AMS1086  
MAX4468EKA  
CS4340  
K9F2808-YCB0  
Xtal_osc 10MHz  
9
U9  
U10  
U11  
U12, U13, U14  
U15  
U16  
U17  
U18  
U20  
U21  
X2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
48 TQFP  
PHY  
Transformer  
RS232  
PULSE  
MAXIM  
16 SOIC  
Regulator  
AMP  
Stereo DAC  
NAND Flash  
Xtal-Oscillator  
(System CLK)  
semtech  
MAXIM  
CRYSTAL  
Samsung  
8pin SOT23  
16 SOIC  
48 TSOP  
Half  
20  
21  
22  
Xtal_osc 25MHz  
Crystal 32.768KHz  
Crystal 10MHz  
Half  
1
1
Xtal-Oscillator  
(PHY CLK)  
Crystal(RTC)  
Y2  
Y1  
X1  
DIP(cylinder  
type)  
DIP(ATS Holder 1  
type)  
Crystal  
(System CLK)  
23  
24  
25  
26  
Xtal_oxc 1MHz  
Battery  
Battery Connector  
PushButton SW  
Half  
CR2032  
1
1
1
15  
Test CLK  
3V coin Battery  
X3  
BT1  
Reset, ExtInt  
S1,S2,S3,SW4,SW5,  
SW6,SW7,SW8,SW9,SW10,SW11,  
SW12,SW13,SW14,  
SW15  
27  
28  
29  
30  
31  
32  
DPDT SW  
Power Toggle SW  
1N4004  
1N4148  
LED  
3
1
2
1
5
1
SW1,SW2,SW16  
SW3  
D1,D2  
3pin DIP  
DIP  
SMD  
A12AP  
Diode  
Diode  
NKK  
JST  
D3  
D4,D5,D6,D7,D8  
PCMCIA 68Pin Con  
ICM-C68H-S112- J2  
400N1  
33  
34  
35  
36  
37  
RJ-45  
1
1
1
1
1
J1  
HEADER 10X2  
POWER JACK  
MIC IN JACK  
AUDIO OUT JACK  
JTAG  
DC5V PWR  
J3  
J4  
J5  
J6  
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EVB7400  
38  
39  
40  
DB9 FEMAIL  
DB9 MAIL  
HEADER 13X2  
5
1
4
UART0~4  
P1,P2,P3,P4,P5  
P6  
JP3,JP4,JP6,JP8  
HUART Option  
DATA, MII,  
ADDRESS,  
MEMORY  
41  
42  
43  
44  
HEADER 24X2  
HEADER 4X2  
HEADER 6X2  
HEADER 1  
1
1
1
7
GPIO heaser  
IIC & SPI  
HUART header  
Test Pin  
JP7  
JP2  
JP5  
JP1,TP1,TP2,TP3,TP4  
TP5, TP6  
45  
46  
Beads(100Mhz)  
0
2012  
0603(1608)  
1
68  
L
R
L1  
R8,R9,R10,R11,R12,  
R13,R14,R15,R16,R17,  
R18,R19,R20,R21,R22,  
R23,R24,R25,R26,R27,  
R28,R29,R30,R31,R32,  
R33,R34,R35,R36,R37,  
R38,R39,R40,R41,R42,  
R43,R44,R45,R46,R47,  
R48,R49,R50,R51,R52,  
R53,R54,R55,R56,R57,  
R58,R59,R60,R61,R62,  
R63,R72,R73,R74,R77,  
R80,R176,R177,R180,R181,  
R200,R201,R202  
47  
48  
0
33  
1206(3216)  
0603(1608)  
4
12  
R
R
R204,R205,R206,R207  
R2,R3,R5,R65,R85  
R86,R87,R88,R95,R96  
R97,R107  
59  
50  
51  
52  
53  
54  
55  
56  
57  
58  
49.9  
75  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
4
5
1
3
5
3
2
4
1
10  
R
R
R
R
R
R
R
R
R
R
R89,R90,R91,R92  
R84,R103,R104,R105,R106  
R178  
R155,R,156,R157  
R144,145,R146,R147,R151  
R158,R159,R160  
R93 R94  
R161,R162,R172,R174  
R163  
R4,R7,R79,R82,R83  
R152, R153,R154,R164,R168  
R66,R67,R69,R70  
R179  
100  
270  
330  
390  
500  
560  
820  
1K  
59  
60  
61  
62  
2K  
3K  
2.2K  
4.7K  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
4
1
1
50  
R
R
R
R
R167  
R6,R64,R68,R71,R75,  
R76,R78,R81,R98,R99,  
R100,R101,R108,R109,R110,R111,  
R112,R113,R114,R115,R116,R117,  
R118,R119,R120,R121,R122,R123,  
R124,R125,R126,R127,R128,R129,  
R130,R131,R132,R133,R134,R135,  
R136,R137,R138,R139,R140,R141,  
R142,R143,R150,R166  
63  
64  
10K  
20K  
0603(1608)  
0603(1608)  
5
1
R
R
R102,R148,R149,R173,R175  
R171  
User’s Manual V.0.10  
22/36  
Copyright © 2004 MCS LOGIC Limited. All rights reserved  
EVB7400  
65  
66  
67  
68  
100K  
1M  
0.01uF_2kV  
0.01uF  
0603(1608)  
0603(1608)  
DIP  
3
1
1
9
R
R
R165,R169,R170  
R1  
C56  
C47,C57,C58,C59,C60,  
C61,C62,C83,C87  
C1,C2,C3,C4,C5,  
0603(1608)  
C
C
69  
0.1uF  
0603(1608)  
65  
C6,C7,C8,C9,C10,  
C11,C12,C15,C17,C18,  
C19,C20,C21,C22,C23,  
C24,C25,C26,C27,C28,  
C29,C32,C33,C34,C35,  
C36,C37,C38,C39,C40,  
C41,C42,C43,C44,C45,  
C46,C48,C50,C52,C63,  
C64,C65,C66,C79,C80,  
C81,C82,C85,C89,C92,  
C93,C94,C96,C97,C183,  
C184,C185,C186C187,C188  
C51,C53,C54,C55,C90,  
C91  
70  
1uF  
0603(1608)  
6
C
71  
72  
73  
74  
75  
76  
20pF  
22pF  
27pF  
47pF  
100pF  
330pF  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
0603(1608)  
2
2
1
1
1
12  
C
C
C
C
C
C
C13,C14  
C30,C31  
C49  
C88  
C95  
C67,C68,C69,C70,C71,  
C72,C73,C74,C75,C76,  
C77,C78  
77  
78  
820pF  
1uF  
0603(1608)  
SMD A(3216) 17  
1
C
T/C  
C16  
TC11,TC12,TC13,TC14,TC15TC16,  
TC17,TC18,TC19,TC20TC21,TC22,  
TC37,TC38,TC39  
TC41, TC42  
79  
80  
81  
2.2uF  
3.3uF  
10uF  
SMD A(3216)  
SMD A(3216)  
SMD B(3528)  
2
2
8
T/C  
T/C  
T/C  
TC9,TC10  
TC35,TC36  
TC3,TC6,TC7,TC25,TC26,  
TC28,TC29,TC34  
TC8  
TC1,TC2,TC4,TC5,TC23,  
TC24  
82  
83  
22uF  
47uF  
SMD B(3528)  
SMD C(6032)  
1
6
T/C  
T/C  
84  
100uF  
SMD D(7343)  
3
T/C  
TC27,TC31,TC33  
User’s Manual V.0.10  
23/36  
Copyright © 2004 MCS LOGIC Limited. All rights reserved  
EVB7400  
6.2 EVB7400 Schematic  
User’s Manual V.0.10  
24/36  
Copyright © 2004 MCS LOGIC Limited. All rights reserved  
 
1
2
3
4
5
6
7
A
A
B
B
MLN7400 Evaluation Board  
C
C
D
D
E
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
MCS LOGIC  
REV.  
E
MLN7400EV  
UPDATE  
SHEET  
1 / 14  
2003.11.18  
REMARK  
BLOCK DIAGRAM  
4
5
1
2
3
6
1
2
3
4
5
6
7
SYSTEM CLOCK  
VCC_33  
OPTIONAL  
R1  
1M  
TDO  
TEST  
TDI  
TCK  
TMS  
R4  
1K  
VCC_33  
X1  
R2  
33  
R3  
33  
1
2
X2  
C184  
0.1uF  
XI  
XO  
1
2
4
VCC  
OUT  
SYSCLK  
R5 33  
NC  
GROUND  
A
A
10MHz  
C13  
C14  
3
XI  
GND  
10MHZ  
C1  
C2  
C3  
C4  
C5  
C6  
TC1  
MDIO  
20pF  
20pF  
NRESET  
MDC  
MII_RXD3  
MII_RXD2  
MII_RXD1  
MII_RXD0  
MII_RXDV  
MII_RXCLK  
MII_RXERR  
GROUND  
VCC_33A  
GROUND  
ADIN0  
47uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
VCC_33  
ADIN1  
ADIN2  
ADIN3  
GROUND  
GROUND  
GROUND  
VCC_33  
AGND  
C7  
C8  
C9  
C10  
C11  
C12  
TC2  
U1  
B
B
47uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
DATA(15:0)  
7
6
5
4
3
2
1
1
2
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
D07  
TX_CLK  
TX_EN  
MII_TXCLK  
MII_TXEN  
MII_TXD0  
MII_TXD1  
MII_TXD2  
MII_TXD3  
D06  
GROUND  
VCC_33  
VCC_33A  
3
D05  
TX_D0  
4
R207  
R204  
0_3216  
D04  
TX_D1  
5
D03  
TX_D2  
6
0_3216  
H1  
D02  
TX_D3  
1
L1  
BEADS_100MHz  
7
D01  
GP38_TOUT3  
GP37_TOUT2  
RX_COL  
GP38_TOUT3  
GP37_TOUT2  
8
VDD33_00  
FHOLE3.5  
9
AGND  
GND33_00  
MII_COL  
MII_CRS  
GROUND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
GP27_EXT_TCLK0  
RX_CRS  
GP27_EXTTCLK0  
GP28_EXTTCLK1  
98  
GP28_EXT_TCLK1  
GP36_EXINT3  
GP35_EXINT2  
SDA  
GP36_EXINT3  
GP35_EXINT2  
SDA  
0
97  
R206  
R205  
0_3216  
0_3216  
D00  
8
96  
D08  
9
95  
D09  
SCL  
SCL  
C
10  
11  
12  
13  
14  
15  
FGND  
94  
D10  
GND33_05  
C
93  
D11  
VDD33_05  
92  
D12  
GP26_ENWAIT  
GP25_IOWR*  
GP24_IORD*  
GP23_CE2*  
GP22_REG*  
GP21_EXT_UCLK  
GP20_EXINT1  
GP19_EXINT0  
GP18_SPICLK  
GP17_SPIMOSI  
GP16_SPIMISO  
GP15_ECSN3  
GP14_ECSN2  
GP13_NTRST  
GP12_TX_ERR  
GP11_TOUT1  
GP10_TOUT0  
GND33_04  
GP26_ENWAIT  
GP25_IOWR*  
GP24_IORD*  
GP23_CE2*  
GROUND  
FGND  
91  
MLN7400_144LQFP  
D13  
90  
D14  
GROUND  
89  
D15  
88  
SDCLK  
CKE  
SDCLK  
SDCKE  
GP22_REG*  
87  
GP21_EXTUCLK  
GP20_EXINT1  
GP19_EXINT0  
GP18_SPICLK  
GP17_SPIMOSI  
GP16_SPIMISO  
GP15_ECSN3  
GP14_ECSN2  
GP13_NTRST  
GP12_TXERR  
GP11_TOUT1  
GP10_TOUT0  
3
2
86  
AD03  
85  
AD02  
ADDR(20:0)  
84  
VDD33_01  
GND33_01  
GP29_EXT_TCLK2  
83  
Endian Setting  
82  
GP29_EXTTCLK2  
81  
GP30_HUARTNDCD4  
GP30_HUARTNDCD4  
VCC_33  
1
0
4
5
6
7
8
9
80  
AD01  
AD00  
AD04  
AD05  
AD06  
AD07  
AD08  
AD09  
79  
78  
C16  
820pF  
77  
BIG  
LITTLE  
FILTER  
SW1  
1
R6  
R7  
4.7K  
1K  
76  
2
75  
ADDR(19)  
3
4
6
D
D
74  
VDD33_04  
73  
GP09_NBE1  
GP09_NBE1  
GROUND  
5
GROUND  
SW_DPDT  
MLN7400_144LQFP  
E
GP08_NBE0  
GP07_CURXD4  
GP06_CUTXD4  
GP05_CURXD3  
GP04_CUTXD3  
GP03_CURXD2  
GP02_CUTXD2  
GP01_CURXD1  
GP00_CUTXD1  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
GROUND  
MCS LOGIC  
REV.  
MLN7400EV  
E
UPDATE  
SHEET  
2/14  
2003.11.18  
10 11 12 13 14  
15 16  
17 18 19 20  
REMARK  
Main CPU MLN7400  
4
5
1
2
3
6
1
2
3
4
5
6
7
VCC_33A  
A
A
VCC_33  
AGND  
U2  
DATA(15:0)  
7
6
5
4
3
2
1
1
2
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
D07  
TX_CLK  
TX_EN  
MII_TXCLK  
MII_TXEN  
MII_TXD0  
MII_TXD1  
MII_TXD2  
MII_TXD3  
MII_COL  
MII_CRS  
SDA  
B
D06  
D05  
D04  
D03  
D02  
D01  
B
3
TX_D0  
4
TX_D1  
5
TX_D2  
6
TX_D3  
VCC_33  
7
RX_COL  
8
VDD33_00  
GND33_00  
D00  
RX_CRS  
9
SDA  
0
8
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
SCL  
SCL  
D08  
GND33_05  
VDD33_05  
9
D09  
10  
11  
12  
13  
14  
15  
D10  
GP26_ENWAIT  
GP25_IOWR*  
GP24_IORD*  
GP23_CE2*  
GP22_REG*  
GP21_EXT_UCLK  
GP20_EXIT1  
GP19_EXIT_0  
GP18_SPICLK  
GP17_SPIMOSI  
GP16_SPIMISO  
GP15_ECSN3  
GP14_ECSN2  
GP13_NTRST  
GP12_TX_ERR  
GP11_TOUT(1)  
GP10_TOUT(0)  
GND33_04  
VDD33_04  
GP26_ENWAIT  
GP25_IOWR*  
GP24_IORD*  
GP23_CE2*  
D11  
D12  
MLN7400P_128TQFP  
D13  
D14  
GP22_REG*  
D15  
GP21_EXTUCLK  
GP20_EXINT1  
GP19_EXINT0  
GP18_SPICLK  
GP17_SPIMOSI  
GP16_SPIMISO  
GP15_ECSN3  
GP14_ECSN2  
GP13_NTRST  
GP12_TXERR  
GP11_TOUT1  
GP10_TOUT0  
SDCLK  
CKE  
SDCLK  
SDCKE  
C
3
2
C
AD03  
AD02  
VDD33_01  
GND3_01  
AD01  
AD00  
AD04  
AD05  
AD06  
AD07  
AD08  
AD09  
GROUND  
1
0
4
5
6
7
8
9
GP09_NBE(1)  
GP09_NBE1  
MLN7400P_128TQFP  
D
D
GROUND  
E
ADDR(20:0)  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
GP07_CURXD4  
MCS LOGIC  
GP06_CUTXD4  
GP05_CURXD3  
GP04_CUTXD3  
GP03_CURXD2  
GP02_CUTXD2  
GP01_CURXD1  
GP00_CUTXD1  
REV.  
MLN7400EV  
E
UPDATE  
SHEET  
3/14  
2003.11.18  
REMARK  
Main CPU MLN7400P 128TQFP  
4
5
1
2
3
6
1
2
3
4
5
6
7
OPTIONAL  
Do not install  
Install to use  
NAND Flash  
Only use when CPU is  
MLN7400P and need to use  
DAC  
A
A
R8  
R9  
0
0
0
0
R12  
R13  
R14  
R15  
R16  
R17  
R18  
R19  
0
0
0
0
0
0
0
0
GP25_IOWR*  
GP24_IORD*  
GP23_CE2*  
GP22_REG*  
DDATA  
DMCK  
DBCK  
GP38_TOUT3  
GP37_TOUT2  
NFIO7  
NFIO6  
NFIO5  
NFIO4  
NFIO3  
NFIO2  
NFIO1  
NFIO0  
MLN7400P  
DAC I/F  
R10  
R11  
NAND  
FLASH  
I/F  
GP36_EXINT3  
DLRCK  
GP34_HUARTNDTR4  
GP33_HUARTNDSR4  
GP32_HUARTNRTS4  
GP31_HUARTNCTS4  
GP30_HUARTNDCD4  
R27  
R28  
R29  
R30  
0
0
0
0
GP42_DDATA  
GP41_DMCK  
GP40_DBCK  
GP39_DLRCK  
DDATA  
DMCK  
DBCK  
DAC I/F  
DLRCK  
B
R20  
R21  
R22  
R23  
R24  
R25  
R26  
0
0
0
0
0
0
0
GP18_SPICLK  
GP17_SPIMOSI  
GP16_SPIMISO  
GP07_CURXD4  
GP06_CUTXD4  
GP05_CURXD3  
GP04_CUTXD3  
NFRBN  
NFRDN  
NFCEN  
NFCLEN  
NFALEN  
NFWRN  
NFWEN  
B
R31  
R32  
R33  
R34  
R35  
R36  
R37  
R200  
0
0
0
0
0
0
0
0
GP26_ENWAIT  
GP25_IOWR*  
GP24_IORD*  
GP22_REG*  
GP20_EXINT1  
GP23_CE2*  
PCMCIA_WAIT*  
PCMCIA_IOWR*  
PCMCIA_IORD*  
PCMCIA_REG*  
PCMCIA_IRQ*  
PCMCIA  
I/F  
PCMCIA_CE2*  
GP15_ECSN3  
GP37_TOUT2  
PCMCIA_CE1*  
PCMCIA_RESET_GP37  
JP1  
TOUT0_TEST  
R39  
R40  
R41  
R42  
R43  
R44  
R45  
R46  
R47  
R48  
0
0
0
0
0
0
0
0
0
0
R38  
0
1
GP32_HUARTNRTS4  
GP31_HUARTNCTS4  
GP07_CURXD4  
GP06_CUTXD4  
GP05_CURXD3  
GP04_CUTXD3  
GP03_CURXD2  
GP02_CUTXD2  
GP01_CURXD1  
GP00_CUTXD1  
HUARTNRTS4  
HUARTNCTS4  
CURXD4  
GP10_TOUT0  
C
JUMP  
C
VCC_33  
CUTXD4  
CURXD3  
CUART  
I/F  
CUTXD3  
CURXD2  
CUTXD2  
CURXD1  
CUTXD1  
R49  
0
GP13_NTRST  
NTRST  
R50  
R51  
R52  
R53  
0
0
0
0
GP12_TXERR  
GP21_EXTUCLK  
GP28_EXTTCLK1  
GP29_EXTTCLK2  
LED0*  
LED1*  
LED2*  
LED3*  
LED  
I/F  
VCC_33  
D
D
VCC_33  
X3  
1
4
3
VCC  
OUT  
NC  
EXT_TCLK0  
C185  
R65  
33  
R61  
0
2
GP27_EXTTCLK0  
GND  
1MHZ  
R54  
R55  
R56  
R57  
0
0
0
0
GP18_SPICLK  
GP17_SPIMOSI  
GP16_SPIMISO  
GP11_TOUT1  
SPI_CLK  
SPI_MOSI  
SPI_MISO  
SPI_SS*  
SPI  
I/F  
0.1uF  
TIMER 0  
EXTERNAL CLOCK  
E
GROUND GROUND  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
MCS LOGIC  
R62  
R63  
0
0
REV.  
GP35_EXINT2  
GP19_EXINT0  
EXTINT2  
EXTINT0  
R58  
R59  
R60  
0
0
0
GP14_ECSN2  
GP09_NBE1  
GP08_NBE0  
NECS2  
SRAM  
I/F  
MLN7400EV  
E
NBE1_UB  
NBE0_LB  
UPDATE  
SHEET  
4/14  
2003.11.18  
GPIO  
REMARK  
4
5
1
2
3
6
1
2
3
4
5
6
7
A
A
IIC EEPROM  
SPI EEPROM  
VCC_33  
VCC_33  
VCC_33  
VCC_33  
U4  
U3  
1
2
3
4
8
7
6
5
*CS  
VCC  
*HOLD  
SCK  
SPI_SS*  
VCC_33  
1
2
3
4
8
7
6
5
A0  
VCC  
WP  
C187  
SO  
SPI_MISO  
A1  
C186  
0.1uF  
0.1uF  
*WP  
GND  
SPI_CLK  
A2  
SCL  
SDA  
SCL  
SDA  
SI  
SPI_MOSI  
GND  
GROUND  
AT25040  
B
S524A40X10  
B
GROUND  
GROUND  
GROUND  
GROUND  
External Interrupt Test  
VCC_33  
VCC_33  
RTC  
R68  
4.7K  
EXTINT0  
C
VCC_33  
C
S1  
1
2
TACT_SW  
TC41  
1uF  
U5  
D1  
2
EXTINT 0  
SDA  
SCL  
1
2
3
4
8
1
SDA  
VDD  
OSC  
X1  
7
6
5
SCL  
1N4004  
ALRM  
GND  
X2  
DS1629  
Y1  
GROUND  
GROUND  
D2  
1N4004  
R71  
4.7K  
EXTINT2  
GROUND  
3
XTAL_32_768KHZ_H49S  
S2  
1
2
D
D
TACT_SW  
GROUND  
TC42  
1uF  
EXTINT 2  
GROUND  
GROUND  
E
GROUND  
GROUND  
GROUND  
GROUND  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
MCS LOGIC  
REV.  
MLN7400EV  
E
UPDATE  
SHEET  
5/14  
2003.11/18  
REMARK  
EEPROM & RTC  
4
5
1
2
3
6
1
2
3
4
5
6
7
VCC_33  
A
A
ADDR(14:0)  
DATA(15:0)  
0
1
0
23  
24  
25  
26  
29  
30  
31  
32  
33  
34  
22  
35  
36  
20  
21  
2
A0  
DQ0  
DQ1  
ADDR(15:0)  
DATA(15:0)  
1
U6  
4
A1  
0
1
0
2
2
1
7
5
A0  
I_O1  
I_O2  
A2  
DQ2  
1
3
3
2
3
8
7
A1  
A3  
DQ3  
2
2
4
4
9
8
A2  
I_O3  
A4  
DQ4  
3
3
5
5
4
10  
13  
14  
15  
16  
29  
30  
31  
32  
35  
36  
37  
38  
10  
11  
13  
42  
44  
45  
47  
48  
50  
51  
53  
A3  
I_O4  
A5  
DQ5  
4
4
6
6
5
A4  
I_O5  
A6  
DQ6  
5
5
7
7
18  
19  
20  
21  
24  
25  
26  
27  
42  
43  
44  
A5  
I_O6  
A7  
DQ7  
6
6
8
8
VCC_33  
A6  
I_O7  
A8  
DQ8  
7
7
VCC_33  
9
9
A7  
I_O8  
A9  
DQ9  
8
8
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
15  
A8  
I_O9  
A10  
A11  
A12  
A13  
A14  
U7  
4MX16_SDRAM  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
9
9
A9  
I_O10  
I_O11  
I_O12  
I_O13  
I_O14  
I_O15  
I_O16  
10  
11  
12  
13  
14  
15  
10  
11  
12  
13  
14  
15  
0
R72  
A10  
A11  
A12  
A13  
A14  
A15  
B
38  
37  
CLK  
CKE  
SDCLK  
SDCKE  
B
VCC_33  
22  
23  
28  
NC1  
NC2  
NC3  
6
17  
41  
CS*  
WE*  
OE*  
NECS1  
NEWE  
NEOE  
19  
18  
17  
16  
15  
39  
40  
CS*  
NC  
SDCSN  
SDRASN  
SDCASN  
SDWEN  
RAS*  
CAS*  
WE*  
11  
33  
VCC1  
VCC2  
GROUND  
0
0
R73  
R74  
39  
40  
LB*  
DQML  
DQMH  
NBE0_LB  
NBE1_UB  
ADDR(15)  
ADDR(16)  
GROUND  
12  
34  
UB*  
VSS1  
VSS2  
K6R1016V1D_SRAM  
GROUND  
BANK2  
SDRAM BANK  
FLASH  
GROUND  
C
C
VCC_33  
AMD Flash  
BANK  
VCC_33  
ADDR(18:0)  
VCC_33  
U9  
0
1
12  
11  
10  
9
A0  
BOSIZE : 8 Bit  
BOSIZE : 16Bit  
Selection  
A1  
2
32  
A2  
VDD  
ADDR(20:0)  
3
U8  
A3  
4
0
1
8
25  
24  
23  
22  
21  
20  
19  
18  
8
A4  
A0  
5
7
A5  
A1  
DATA(15:0)  
6
2
6
A6  
A2  
7
0
1
2
3
4
5
6
7
3
5
13  
14  
15  
17  
18  
19  
20  
21  
A7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
A3  
X8  
SW2  
2
8
4
VCC_33  
1
27  
26  
23  
25  
4
A8  
A4  
NECS2  
NECS0  
9
5
A9  
A5  
DATA(15:0)  
NCS_AMD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
6
3
4
6
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A6  
7
0
29  
31  
33  
35  
38  
40  
42  
44  
30  
32  
34  
36  
39  
41  
43  
45  
A7  
D0  
D1  
8
1
A8  
9
2
R75  
R79  
4.7K  
1K  
5
28  
29  
3
7
A9  
D2  
ADDR(20)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
3
6
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
RY_BY#  
D3  
4
D
D
5
D4  
SW_DPDT  
5
2
4
X16  
D5  
6
30  
1
3
D6  
7
2
D7  
8
1
D8  
GROUND  
9
22  
24  
31  
16  
48  
17  
16  
9
CE*  
OE*  
WE*  
GND  
D9  
NECS0  
NEOE  
NEWE  
10  
11  
12  
13  
14  
15  
D10  
D11  
D12  
D13  
D14  
D15  
VCC_33  
0
AT29C040A  
R77  
R78  
10  
15  
47  
4.7K  
GROUND  
BYTE_VCCQ  
14  
26  
28  
11  
*WP  
*CE  
*OE  
*WE  
BANK0  
E
NCS_AMD  
NEOE  
NEWE  
DESIGN  
CUSTOMER  
MCS LOGIC  
0
R80  
12  
*RST  
NRESET  
CHECK-1  
CHECK-2  
DATE  
REV.  
AM29LV160BB  
MLN7400EN  
E
BANK1  
UPDATE  
SHEET  
6/14  
2003.11.18  
GROUND  
REMARK  
MEMORY  
4
5
1
2
3
6
1
2
3
4
5
6
7
A
A
VCC_33  
VCC_33  
VCC_33  
Y2  
VCC_25  
4
3
1
2
NC_VDD  
X2_OUT  
X1_OE  
NC_GND  
XTAL_OSC_25MHZ  
GROUND  
GROUND  
GROUND  
GROUND  
NRESET  
MDIO  
MDC  
B
VCC_25  
VCC_25  
B
R85  
33  
33  
33  
33  
PHYADCO3  
PHYADCO2  
PHYADCO1  
PHYADCO0  
MII_RXD3  
MII_RXD2  
MII_RXD1  
MII_RXD0  
R86  
R87  
R88  
GROUND  
VCC_25  
VCC_25  
GROUND  
U10  
VCC_25  
VCC_25  
U11  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
J1  
VCC1  
VCC25OUT  
TXP  
GROUND  
GROUND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
9
GND1  
TXDP  
TDC  
TXDN  
NC1  
TXP  
TCMT  
TXN  
R95  
R96  
R97  
33  
33  
33  
3
10  
11  
12  
LED_LNK  
LED_SPD  
RXDV_CRSDV  
RMII_MODEL_RXC  
ISOLATE_RXER  
GND2  
TXN  
MII_RXDV  
MII_RXCLK  
MII_RXERR  
4
GND6  
VCCPLL  
RBIAD  
GND5  
GND4  
SD_FXEN  
RXP  
5
NC3  
6
NC2  
NC4  
7
AC101L  
13  
14  
VCC2  
RDP  
RDC  
RDN  
RXP  
8
TXER  
RCMT  
RXN  
C
9
TXC  
C
10  
11  
12  
TXEN  
H1102  
RJ45  
TXD0  
RXN  
TXD1  
VCC4  
FGND  
R103  
R104  
R105  
R106  
75  
75  
75  
75  
GROUND  
33  
GROUND  
GROUND  
R107  
MII_TXCLK  
MII_TXEN  
MII_TXD0  
MII_TXD1  
C56  
VCC_25  
0.01uF_2KV  
GROUNDGROUND  
VCC_25  
R108  
R109  
4.7K  
4.7K  
MII_TXD2  
MII_TXD3  
MII_COL  
MII_CRS  
GROUND  
VCCPLL  
FGND  
PHYADCO4  
PHYADCO3  
PHYADCO2  
PHYADCO1  
PHYADCO0  
R110  
R111  
R112  
R113  
R114  
4.7K  
4.7K  
4.7K  
4.7K  
4.7K  
Place close to  
pin32 0f AC101L  
D
D
VCC_25  
GROUND  
R117  
4.7K  
4.7K  
4.7K  
4.7K  
GROUNDGROUND  
R118  
R119  
R120  
GROUND  
GROUND  
VCC_25  
E
DESIGN  
CUSTOMER  
MCS LOGIC  
CHECK-1  
CHECK-2  
DATE  
REV.  
MLN7400EV  
E
Place close to  
pins 0f AC101L  
UPDATE  
SHEET  
7/14  
GROUND  
2003.11.18  
REMARK  
AC101L ETHERNET PHY  
4
5
1
2
3
6
1
2
3
4
5
6
7
P1  
UART0  
1
6
2
7
3
8
4
9
5
VCC_33  
A
A
U12  
1uF  
TC12  
1
16  
C1+  
VCC  
2
1
3
11  
12  
10  
9
2
TC11  
1uF  
DB9_FEMALE  
C1-  
T1I  
V+  
T1O  
R1I  
T2O  
R2I  
V-  
1
2
14  
13  
7
CUTXD0  
CURXD0  
CUTXD1  
CURXD1  
R1O  
T2I  
GROUND  
P2  
8
UART1  
R2O  
C2+  
1uF  
TC13  
4
6
1uF  
TC14  
1
6
2
7
3
8
4
9
5
2
1
2
1
5
15  
C2-  
GND  
MAX3232  
GROUND  
B
B
DB9_FEMALE  
GROUND  
GROUND  
P3  
UART2  
1
6
2
7
3
8
4
9
5
VCC_33  
U13  
C1+  
1uF  
TC16  
1
16  
VCC  
2
1
3
11  
12  
10  
9
2
TC15  
1uF  
DB9_FEMALE  
C1-  
T1I  
V+  
T1O  
R1I  
T2O  
R2I  
V-  
1
2
14  
13  
7
CUTXD2  
CURXD2  
CUTXD3  
CURXD3  
C
R1O  
T2I  
C
GROUND  
P4  
8
UART3  
R2O  
C2+  
1uF  
TC17  
4
6
1uF  
TC18  
1
6
2
7
3
8
4
9
5
2
1
2
1
5
1
5
C2-  
GND  
MAX3232  
GROUND  
DB9_FEMALE  
GROUND  
GROUND  
P5  
UART4  
1
6
2
7
3
8
4
9
5
D
D
VCC_33  
U14  
1uF  
TC20  
1
16  
C1+  
VCC  
2
1
3
11  
12  
10  
9
2
TC19  
1uF  
DB9_FEMALE  
C1-  
T1I  
V+  
T1O  
R1I  
T2O  
R2I  
V-  
1
2
14  
13  
7
CUTXD4  
CURXD4  
R1O  
T2I  
GROUND  
E
HUARTNRTS4  
HUARTNCTS4  
P6  
8
HUART  
OPTION  
R2O  
C2+  
1uF  
TC21  
4
6
1uF  
TC22  
1
6
2
7
3
8
4
9
5
DESIGN  
CUSTOMER  
2
1
2
1
MCS LOGIC  
CHECK-1  
CHECK-2  
DATE  
5
15  
REV.  
C2-  
GND  
MAX3232  
MLN7400EV  
E
GROUND  
UPDATE  
SHEET  
8/14  
2003.11.18  
RS232  
DB9_MALE  
GROUND  
REMARK  
GROUND  
4
5
1
2
3
6
1
2
3
4
5
6
7
VCC_33  
ADDR(11:0)  
A
A
J2  
0
29  
28  
27  
26  
25  
24  
23  
22  
12  
11  
8
17  
51  
52  
18  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
VCC0  
VCC1  
VPP2  
VPP1  
1
2
3
4
5
6
7
8
9
10  
11  
DATA(15:0)  
10  
21  
13  
14  
20  
19  
46  
47  
48  
49  
50  
53  
54  
55  
56  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
0
30  
31  
32  
2
D0  
1
D1  
B
2
B
D2  
3
D3  
4
3
D4  
5
4
D5  
6
VCC_33  
5
D6  
7
6
D7  
8
64  
65  
66  
37  
38  
39  
40  
41  
D8  
9
D9  
10  
11  
12  
13  
14  
15  
D10  
D11  
D12  
D13  
D14  
D15  
R201  
R202  
0
0
PCMCIA_RESET_GP37  
58  
C
RESET  
PCMCIA_RESET  
C
7
CE1*  
CE2*  
PCMCIA_CE1*  
PCMCIA_CE2*  
42  
9
15  
44  
45  
OE*  
NEOE  
NEWE  
WE*_PGM*  
IORO*  
GROUND  
PCMCIA_IORD*  
PCMCIA_IOWR*  
IOWR*  
61  
REG*  
PCMCIA_REG*  
VCC_33  
67  
36  
CD2*  
CD1*  
59  
16  
WAIT*  
PCMCIA_WAIT*  
PCMCIA_IRQ*  
RDY*_IREQ*  
D
D
57  
43  
VS2*  
VS1*  
62  
63  
BVD2*_SPKR  
68  
35  
34  
1
BVD1*_STSCHG  
GND0  
GND1  
GND2  
GND3  
60  
33  
INPACK*  
WP*_IOIS16*  
E
PCMCIA_68PIN_CONN  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
MCS LOGIC  
GROUND  
GROUND  
REV.  
BANK3  
MLN7400EV  
E
UPDATE  
SHEET  
9/14  
2003.11.18  
REMARK  
GROUND  
PCMCIA INTERFACE  
4
5
1
2
3
6
1
2
3
4
5
6
7
RESET SYSTEM  
GPIO LED  
VCC_33  
VCC_33  
VCC_33  
VCC_33  
VCC_33  
VCC_33  
VCC_33  
VCC_33  
A
A
RESET  
D3  
1N4148  
U15  
U15  
74LVC14  
2
74LVC14  
4
1
3
NRESET  
GROUND GROUND  
TC25  
10uF  
VCC_33  
14 Pin : VCC_33  
7 Pin : Ground  
S3  
1
2
VCC_33  
B
SW_RESET  
B
14 U16  
1
2
3
NTRST  
LED0*  
LED1*  
LED2*  
LED3*  
GROUND  
7
74LV08  
14 Pin : VCC_33  
7 Pin : Ground  
GROUND  
JTAG CONNECTOR  
TC26  
10uF  
POWER LED  
C
VCC_33  
C
J3  
VCC_33  
2
1
3
NTRST_JTAG  
4
6
5
TDI  
GROUND  
8
7
TMS  
TCK  
10  
12  
14  
16  
18  
20  
9
U15  
11  
13  
15  
17  
19  
74LVC14  
6
TDO  
5
NRESET  
NRESET  
PCMCIA_RESET  
HEADER2X10  
D
D
GROUND  
VCC_5IN  
VCC_5  
VCC_33  
GROUND  
SW3  
1
J4  
2
U17  
1
2
3
A1 B1  
3
A2 B2  
A3 B3  
3
2
4
E
IN  
OUT  
TAB  
SW_TOGGLE  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
PWR_JACK  
MCS LOGIC  
TC27  
100uF_16V  
TC33  
100uF_16V  
TC28  
10uF  
TC29  
10uF  
TC31  
100uF  
AMS1086  
REV.  
MLN7400EV  
E
UPDATE  
SHEET  
10/14  
2003.11.18  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
GROUND  
REMARK  
POWER&RESET  
4
5
1
2
3
6
1
2
3
4
5
6
7
DATA(15:0)  
VCC_33  
VCC_33  
JP2  
A
A
1
3
5
7
2
4
6
8
SPI_CLK  
SPI_MOSI  
SPI_MISO  
SPI_SS*  
SDA  
SCL  
VCC_33  
JP3  
HEADER2X4  
25  
23  
21  
19  
17  
15  
13  
11  
9
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
14  
15  
13  
11  
9
GROUND  
12  
10  
8
IIC & SPI  
HEADER  
JP5  
6
7
1
2
4
4
5
3
GP06_CUTXD4  
GP07_CURXD4  
GP31_HUARTNCTS4  
2
3
7
5
6
GP32_HUARTNRTS4  
GP33_HUARTNDSR4  
GP34_HUARTNDTR4  
0
1
5
6
7
8
GP30_HUARTNDCD4  
VCC_33  
3
4
9
10  
12  
1
2
11  
HEADER2X6  
HEADER2X13  
B
B
GROUND  
GROUND  
GROUND  
GROUND  
JP4  
DATA  
HEADER  
HIGH SPEED  
UART  
HEADER  
25  
23  
21  
19  
17  
15  
13  
11  
9
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
MII_CRS  
MDC  
MDIO  
MII_COL  
MII_RXERR  
MII_RXCLK  
MII_RXDV  
MII_RXD3  
MII_RXD2  
MII_RXD1  
MII_RXD0  
MII_TXCLK  
MII_TXEN  
MII_TXD3  
MII_TXD2  
MII_TXD1  
MII_TXD0  
ADDR(20:0)  
7
JP6  
5
6
20  
18  
16  
14  
12  
10  
8
25  
23  
21  
19  
17  
15  
13  
11  
9
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
3
4
19  
17  
15  
13  
11  
9
1
2
VCC_33  
HEADER2X13  
C
GROUND  
GROUND  
C
6
7
4
5
MII I/F  
HEADER  
TP1  
TP_040  
TP2  
TP_040  
TP3  
TP_040  
TP4  
TP_040  
2
3
7
0
1
5
6
3
4
TP5  
TP_040  
TP6  
TP_040  
1
2
VCC_33  
HEADER2X13  
GROUND  
GROUND  
GROUND  
ADDRESS  
HEADER  
JP7  
47  
45  
43  
41  
39  
37  
35  
33  
31  
29  
27  
25  
23  
21  
19  
17  
15  
13  
11  
9
48  
46  
44  
42  
40  
38  
36  
34  
32  
30  
28  
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
GP42_DDATA  
GP40_DBCK  
GP41_DMCK  
VCC_33  
GP38_TOUT3  
GP39_DLRCK  
GP37_TOUT2  
GP36_EXINT3  
GP34_HUARTNDTR4  
GP32_HUARTNRTS4  
GP30_HUARTNDCD4  
GP28_EXTTCLK1  
GP26_ENWAIT  
GP24_IORD*  
GP35_EXINT2  
GP33_HUARTNDSR4  
GP31_HUARTNCTS4  
GP29_EXTTCLK2  
GP27_EXTTCLK0  
GP25_IOWR*  
D
D
JP8  
25  
23  
21  
19  
17  
15  
13  
11  
9
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
GP22_REG*  
GP23_CE2*  
GP20_EXINT1  
GP18_SPICLK  
GP16_SPIMISO  
GP14_ECSN2  
GP21_EXTUCLK  
GP19_EXINT0  
GP17_SPIMOSI  
GP15_ECSN3  
GP13_NTRST  
GP11_TOUT1  
GP15_ECSN3  
GP14_ECSN2  
GP09_NBE1  
GP08_NBE0  
NEOE  
SDCASN  
SDRASN  
SDWEN  
SDCSN  
GP12_TXERR  
GP10_TOUT0  
E
GP08_NBE0  
GP09_NBE1  
NEWE  
NECS1  
GP06_CUTXD4  
GP04_CUTXD3  
GP02_CUTXD2  
GP00_CUTXD1  
GP07_CURXD4  
GP05_CURXD3  
GP03_CURXD2  
GP01_CURXD1  
7
7
SDCKE  
SDCLK  
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
5
6
5
6
NECS0  
MCS LOGIC  
3
4
3
4
1
2
1
2
REV.  
HEADER24x2  
GP1~  
ODD  
GPIO  
HEADER2X13  
GP0~  
EVEN  
GPIO  
MLN7400EV  
E
GROUND  
GROUND  
GROUND  
GROUND  
UPDATE  
SHEET  
GPIO  
HEADER  
MEMORY  
HEADER  
11/14  
2003.11.18  
REMARK  
Test Header Pin  
4
5
1
2
3
6
1
2
3
4
5
6
7
VCC_33A  
VCC_33A  
VCC_33A  
A
A
R152  
1K  
R153  
1K  
R154  
1K  
ADIN0  
ADIN1  
ADIN2  
SW4  
SW5  
SW6  
1
2
1
2
1
2
TACT_SW  
PLAY  
TACT_SW  
PGM  
TACT_SW  
EQ  
SW7  
2
SW8  
2
SW9  
2
1
1
1
1
1
1
1
1
TACT_SW  
STOP  
TACT_SW  
MENU  
TACT_SW  
VOL_UP  
B
B
SW10  
2
SW11  
2
SW12  
2
1
TACT_SW  
SKIP+  
TACT_SW  
ESP  
TACT_SW  
VOL_DN  
AGND  
VCC_33A  
SW13  
2
SW14  
2
TACT_SW  
SKIP-  
TACT_SW  
ENTER  
C188  
0.1uF  
C
C
AGND  
VCC_33A  
VCC_33A  
AGND  
SW15  
2
U18  
TACT_SW  
MODE  
MUTE  
Enable  
1
2
3
4
8
7
6
GND  
OUT  
VCC  
R167  
2.2K  
ADIN3  
SHDN  
R166  
R168  
4.7K  
1K  
SW16  
2
1
3
4
6
INP  
J5  
INN  
SHDN  
5
AGND  
MBIAS  
NC  
MUTE  
Disable  
MAX4468EKA_SOP8  
5
3
2
1
AGND  
SW_DPDT  
AGND  
MUTE  
SW  
D
D
R170  
C88  
100K  
AGND  
0.1uF  
MICIN  
47pF  
C89  
R171  
20K  
MIC  
JACK  
E
DESIGN  
CHECK-1  
CHECK-2  
DATE  
CUSTOMER  
MCS LOGIC  
AGND  
REV.  
MLN7400EV  
E
UPDATE  
SHEET  
12/14  
2003.11.18  
REMARK  
KEY MATRIX & MIC IN  
4
5
1
2
3
6
1
2
3
4
5
6
7
TC35  
1
3.3uF  
R172  
560  
A
A
2
J6  
AGND  
R174  
B
B
AOUTR  
AOUTL  
TC36  
1
3.3uF  
560  
3
2
1
2
VCC_33A  
C
LINE_OUT_JACK  
C
AGND  
U20  
AGND  
R177  
0
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
RST*  
SDATA  
SCLK  
LRCK  
MCLK  
DIF1  
MUTEC  
AOUTL  
VA  
NRESET  
DDATA  
DBCK  
AGND  
AOUTR  
REF_GND  
VQ  
DLRCK  
DMCK  
D
D
DIF0  
DEM0  
FILT+  
CS4340  
E
DESIGN  
CUSTOMER  
MCS LOGIC  
CHECK-1  
CHECK-2  
DATE  
REV.  
E
MLN7400EV  
AGND  
AGND  
AGND  
AGND  
AGND  
UPDATE  
SHEET  
13/14  
2003.11.18  
REMARK  
DAC  
4
5
1
2
3
6
1
2
3
4
5
6
7
A
A
VCC_33  
NAND_Flash  
U21  
1
2
48  
NC1  
NC15  
NC16  
NC17  
NC18  
IO7  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
NC2  
3
NC3  
4
B
NC4  
B
5
NC5  
NFIO7  
NFIO6  
NFIO5  
NFIO4  
6
GND1  
R_BN  
REN  
CEN  
NC6  
IO6  
NFPIN6  
7
IO5  
NFRBN  
VCC_33  
8
IO4  
NFRDN  
NFCEN  
VCC_33  
9
NC19  
NC20  
NC21  
VCC2  
VSS2  
NC22  
NC23  
NC24  
IO3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
NC7  
NFPIN38  
VCC1  
VSS1  
NC8  
C
C
NC9  
CLE  
NFCLEN  
NFALEN  
NFWRN  
NFWEN  
NFIO3  
NFIO2  
NFIO1  
NFIO0  
ALE  
GROUND  
WEN  
WPN  
NC10  
NC11  
NC12  
NC13  
NC14  
IO2  
IO1  
IO0  
NC25  
NC26  
NC27  
NC28  
R180  
R181  
0
0
NFPIN6  
GROUND GROUND  
GROUND GROUND  
D
D
K9F2808_YCB0  
NFPIN38  
E
DESIGN  
CHECK-1  
CHECK-2  
CUSTOMER  
GROUND  
MCS LOGIC  
REV.  
E
MLN7400  
DATE  
UPDATE  
SHEET  
14/14  
2003.11.18  
REMARK  
NAND FLASH  
4
5
1
2
3
6

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