Hitachi Travelstar HTS543212L9A300 User Manual
5K320 SATA OEM Specification  
Hitachi Global Storage Technologies  
Hard Disk Drive Specification  
Hitachi Travelstar 5K320  
2.5 inch SATA hard disk drive  
Models:  
HTS543232L9A300, HTS543232L9SA00  
HTS543225L9A300, HTS543225L9SA00  
HTS543216L9A300, HTS543216L9SA00  
HTS543212L9A300, HTS543212L9SA00  
HTS543280L9A300, HTS543280L9SA00  
Revision 1.5  
9 Apr., 2010  
1
 
5K320 SATA OEM Specification  
Table of Contents  
GENERAL.................................................................................................................................................9  
1 INTRODUCTION .......................................................................................................................................9  
1.1  
1.2  
1.3  
1.4  
Abbreviations.............................................................................................................................9  
References................................................................................................................................12  
General caution .......................................................................................................................12  
Drive handling precautions ....................................................................................................12  
2 OUTLINE OF THE DRIVE.........................................................................................................................13  
PART 1 FUNCTIONAL SPECIFICATION ...........................................................................................14  
3 FIXED DISK SUBSYSTEM DESCRIPTION ..................................................................................................15  
3.1  
3.2  
Control Electronics..................................................................................................................15  
Head disk assembly data ........................................................................................................15  
4 FIXED DISK CHARACTERISTICS..............................................................................................................16  
4.1  
4.2  
4.3  
4.4  
Formatted capacity by model number....................................................................................16  
Data sheet................................................................................................................................17  
Cylinder allocation ..................................................................................................................17  
Performance characteristics ...................................................................................................18  
5 DATA INTEGRITY ...................................................................................................................................22  
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
5.7  
5.8  
Data loss on power off .............................................................................................................22  
Write Cache .............................................................................................................................22  
Equipment status ....................................................................................................................22  
WRITE safety...........................................................................................................................22  
Data buffer test........................................................................................................................23  
Error recovery..........................................................................................................................23  
Automatic reallocation............................................................................................................23  
ECC ..........................................................................................................................................24  
6 SPECIFICATION .....................................................................................................................................25  
6.1  
6.2  
6.3  
6.4  
6.5  
6.6  
6.7  
6.8  
6.9  
Environment............................................................................................................................25  
DC power requirements ..........................................................................................................27  
Reliability.................................................................................................................................29  
Mechanical specifications........................................................................................................32  
Vibration and shock.................................................................................................................34  
Acoustics...................................................................................................................................36  
Identification labels.................................................................................................................37  
Electromagnetic compatibility................................................................................................37  
Safety........................................................................................................................................38  
6.10 Packaging.................................................................................................................................38  
6.11 Substance restriction requirements.......................................................................................38  
7 ELECTRICAL INTERFACE SPECIFICATIONS ............................................................................................39  
7.1  
7.2  
7.3  
Cabling .....................................................................................................................................39  
Interface connector..................................................................................................................39  
Signal definitions.....................................................................................................................40  
PART 2 INTERFACE SPECIFICATION...............................................................................................44  
8 GENERAL ..............................................................................................................................................45  
8.1  
8.2  
Introduction .............................................................................................................................45  
Terminology .............................................................................................................................45  
9 DEVIATIONS FROM STANDARD ..............................................................................................................46  
10 PHYSICAL INTERFACE.........................................................................................................................46  
11 REGISTERS ..........................................................................................................................................46  
11.1 Register naming convention ...................................................................................................47  
11.2 Command register...................................................................................................................47  
11.3 Device Control Register...........................................................................................................47  
11.4 Device Register ........................................................................................................................48  
11.5 Error Register..........................................................................................................................48  
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5K320 SATA OEM Specification  
11.6 Features Register ....................................................................................................................48  
11.7 LBA High Register ..................................................................................................................49  
11.8 LBA Low Register....................................................................................................................49  
11.9 LBA Mid Register....................................................................................................................49  
11.10 Sector Count Register..........................................................................................................49  
11.11 Status Register.....................................................................................................................49  
12 GENERAL OPERATION DESCRIPTIONS ................................................................................................51  
12.1 Reset Response ........................................................................................................................51  
12.2 Diagnostic and Reset considerations......................................................................................52  
12.3 Power-off considerations .........................................................................................................53  
12.4 Sector Addressing Mode..........................................................................................................54  
12.5 Power Management Feature ..................................................................................................54  
12.6 Advanced Power Management (Adaptive Battery Life Extender 3) Feature......................56  
12.7 Interface Power Management Mode (Slumber and Partial).................................................57  
12.8 S.M.A.R.T. Function................................................................................................................57  
12.9 Security Mode Feature Set .....................................................................................................58  
12.10 Protected Area Function......................................................................................................64  
12.11 Seek Overlap ........................................................................................................................67  
12.12 Write Cache Function..........................................................................................................67  
12.13 Reassign Function................................................................................................................67  
12.14 48-bit Address Feature Set..................................................................................................68  
12.15 Software Setting Preservation Feature Set .......................................................................69  
12.16 Native Command Queuing..................................................................................................70  
12.17 SMART Command Transport (SCT)...................................................................................70  
13 COMMAND PROTOCOL.........................................................................................................................72  
13.1 Data In Commands .................................................................................................................72  
13.2 Data Out Commands...............................................................................................................72  
13.3 Non-Data Commands..............................................................................................................73  
13.4 DMA Data Transfer Commands.............................................................................................74  
13.5 First-parity DMA Commands.................................................................................................74  
14 COMMAND DESCRIPTIONS ..................................................................................................................75  
14.1 Check Power Mode (E5h/98h).................................................................................................79  
14.2 Device Configuration Overlay (B1h) ......................................................................................80  
14.3 Download Microcode (92h)......................................................................................................84  
14.4 Execute Device Diagnostic (90h) ............................................................................................86  
14.5 Flush Cache (E7h)...................................................................................................................87  
14.6 Flush Cache Ext (EAh)............................................................................................................88  
14.7 Format Track (50h: Vendor Specific) .....................................................................................89  
14.8 Format Unit (F7h: Vendor Specific).......................................................................................90  
14.9 Identify Device (ECh)..............................................................................................................91  
14.10 Idle (E3h/97h).....................................................................................................................103  
14.11 Idle Immediate (E1h/95h) .................................................................................................104  
14.12 Initialize Device Parameters (91h)...................................................................................105  
14.13 Read Buffer (E4h) ..............................................................................................................106  
14.14 Read DMA(C8h/C9h) .........................................................................................................107  
14.15 Read DMA Ext (25h)..........................................................................................................108  
14.16 Read FPDMA Queued (60h)..............................................................................................109  
14.17 Read Log Ext(2Fh).............................................................................................................110  
14.18 Read Multiple (C4h)...........................................................................................................118  
14.19 Read Multiple Ext (29h) ....................................................................................................119  
14.20 Read Native Max Address (F8h).......................................................................................120  
14.21 Read Native Max Address Ext (27h) ................................................................................121  
14.22 Read Sector(s) (20h/21h)....................................................................................................122  
14.23 Read Sector(s) Ext (24h)....................................................................................................123  
14.24 Read Verify Sector(s) (40h/41h) ........................................................................................124  
14.25 Read Verify Sector(s) Ext (42h).........................................................................................125  
14.26 Recalibrate (1xh)................................................................................................................126  
14.27 Security Disable Password (F6h)......................................................................................127  
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5K320 SATA OEM Specification  
14.28 Security Erase Prepare (F3h) ...........................................................................................128  
14.29 Security Erase Unit (F4h) .................................................................................................129  
14.30 Security Freeze Lock (F5h) ...............................................................................................131  
14.31 Security Set Password (F1h).............................................................................................132  
14.32 Security Unlock (F2h)........................................................................................................134  
14.33 Seek (7xh)...........................................................................................................................135  
14.34 Sense Condition (F0h : vendor specific)............................................................................136  
14.35 Set Features (EFh).............................................................................................................137  
14.36 Set Max Address (F9h) ......................................................................................................139  
14.37 Set Max Address Ext (37h)................................................................................................141  
14.38 Set Multiple (C6h)..............................................................................................................143  
14.39 Sleep (E6h/99h)..................................................................................................................144  
14.40 S.M.A.R.T Function Set (B0h) ..........................................................................................145  
14.41 Standby (E2h/96h) .............................................................................................................160  
14.42 Standby Immediate (E0h/94h)..........................................................................................161  
14.43 Write Buffer (E8h) .............................................................................................................162  
14.44 Write DMA (CAh/CBh)......................................................................................................163  
14.45 Write DMA Ext (35h).........................................................................................................164  
14.46 Write DMA FUA Ext (3Dh)...............................................................................................165  
14.47 Write FPDMA Queued (61h).............................................................................................166  
14.48 Write Log Ext (3Fh)...........................................................................................................167  
14.49 Write Multiple (C5h)..........................................................................................................168  
14.50 Write Multiple Ext (39h) ...................................................................................................169  
14.51 Write Multiple FUA Ext (CEh).........................................................................................170  
14.52 Write Sector(s) (30h/31h)...................................................................................................171  
14.53 Write Sector(s) Ext (34h)...................................................................................................172  
14.54 Write Uncorrectable Ext (45h)..........................................................................................173  
15 TIMINGS ............................................................................................................................................175  
List of Figures  
Figure 1. Limits of temperature and humidity  
Figure 2. Mounting hole locations  
Figure 3. Interface connector pin assignments  
Figure 4. Parameter descriptions  
Figure 5 Initial Setting  
25  
32  
39  
42  
60  
61  
62  
66  
67  
147  
Figure 6 Usual Operation  
Figure 7 Password Lost  
Figure 8 Set Max security mode transition  
Figure 9 Seek overlap  
Figure 10 Selective self-test test span example  
List of Tables  
Table 1. Formatted capacity by model number.  
Table 2. Data sheet  
16  
17  
17  
18  
19  
19  
19  
19  
20  
21  
21  
25  
26  
27  
Table 3. Cylinder allocation  
Table 4. Performance characteristics  
Table 5. Mechanical positioning performance  
Table 6. Full stroke seek time  
Table 7. Single track seek time  
Table 8. Latency time  
Table 9. Drive ready time  
Table 10. Operating mode  
Table 11. Drive ready time  
Table 12. Environmental condition  
Table 13. Magnetic flux density limits  
Table 14. DC Power requirements  
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5K320 SATA OEM Specification  
Table 15. Power consumption efficiency  
Table 16. Physical dimensions and weight  
Table 17. Random vibration PSD profile breakpoints (operating)  
Table 18. Swept sine vibration  
Table 19. Random Vibration PSD Profile Breakpoints (nonoperating)  
Table 20. Operating shock  
Table 21. Nonoperating shock  
Table 22. Weighted sound power  
Table 23. Interface connector pins and I/O signals  
Table 24 Register naming convention and correspondence  
Table 25 Device Control Register  
Table 26 Device Register  
Table 27 Error Register  
Table 28 Status Register  
Table 29 Reset Response Table  
Table 30 Default Register Values  
Table 31 Diagnostic Codes  
Table 32 Reset error register values  
Table 33 Device’s behavior by ATA commands  
Table 34 Power conditions  
28  
32  
34  
34  
35  
35  
35  
36  
40  
47  
47  
48  
48  
49  
51  
52  
52  
52  
53  
55  
63  
64  
66  
70  
71  
75  
76  
77  
79  
80  
80  
82  
83  
84  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
101  
Table 35 Command table for device lock operation  
Table 36 Command table for device lock operation - continued  
Table 37 Set Max Set Password data content  
Table 38 Preserved Software Setting  
Table 39 SCT Action Code Supported  
Table 40 Command set  
Table 41 Command Set - continued  
Table 42 Command Set (Subcommand)  
Table 43 Check Power Mode Command (E5h/98h)  
Table 44 Device Configuration Overlay Command (B1h)  
Table 45 Device Configuration Overlay Features register values  
Table 46 Device Configuration Overlay Data structure  
Table 47 DCO error information definition  
Table 48 Download Command (92h)  
Table 49 Execute Device Diagnostic Command (90h)  
Table 50 Flush Cache Command (E7h)  
Table 51 Flush Cache EXT Command (EAh)  
Table 52 Format Track Command (50h)  
Table 53 Format Unit Command (F7h)  
Table 54 Identify Device Command (ECh)  
Table 55 Identify device information  
Table 56 Identify device information --- Continued ---  
Table 57 Identify device information --- Continued ---  
Table 58 Identify device information --- Continued ---  
Table 59 Identify device information --- Continued ---  
Table 60 Identify device information --- Continued ---  
Table 61 Identify device information --- Continued ---  
Table 62 Identify device information --- Continued ---  
Table 63 Identify device information --- Continued ---  
Table 64 Number of cylinders/heads/sectors by models for HTS5432XXL9SA00 / HTS5432XXL9A300 102  
Table 65 Idle Command (E3h/97h)  
103  
104  
105  
106  
107  
108  
109  
110  
110  
111  
112  
Table 66 Idle Immediate Command (E1h/95h)  
Table 67 Initialize Device Parameters Command (91h)  
Table 68 Read Buffer Command (E4h)  
Table 69 Read DMA Command (C8h/C9h)  
Table 70 Read DMA Ext Command (25h)  
Table 71 Read FPDMA Queued Command (60h)  
Table 72 Read Log Ext Command (2Fh)  
Table 73 Log address definition  
Table 74 General purpose Log Directory  
Table 75 Extended comprehensive SMART error Log  
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5K320 SATA OEM Specification  
Table 76 Extended Error log data structure  
Table 77 Command data structure  
Table 78 Error data structure  
Table 79 Extended Self-test log data structure  
Table 80 Extended Self-test log descriptor entry  
Table 81 Command Error information  
112  
113  
113  
114  
115  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
127  
128  
129  
129  
131  
132  
132  
134  
134  
135  
136  
137  
139  
141  
143  
144  
145  
148  
150  
151  
152  
154  
155  
155  
156  
156  
157  
157  
158  
159  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
Table 82 Phy Event Counter Identifier  
Table 83 Phy Event Counter information  
Table 84 Read Multiple Command (C4h)  
Table 85 Read Multiple Ext Command (29h)  
Table 86 Read Native Max Address Command (F8h)  
Table 87 Read Native Max Address Ext Command (29h)  
Table 88 Read Sector(s) Command (20h/21h)  
Table 89 Read Sector(s) Ext Command (24h)  
Table 90 Read Verify Sector(s) Command (40h/41h)  
Table 91 Read Verify Sector(s) Ext Command (42h)  
Table 92 Recalibrate Command (1xh)  
Table 93 Security Disable Password Command (F6h)  
Table 94 Password Information for Security Disable Password command  
Table 95 Security Erase Prepare Command (F3h)  
Table 96 Security Erase Unit Command (F4h)  
Table 97 Erase Unit Information  
Table 98 Security Freeze Lock Command (F5h)  
Table 99 Security Set Password Command (F1h)  
Table 100 Security Set Password Information  
Table 101 Security Unlock Command (F2h)  
Table 102 Security Unlock Information  
Table 103 Seek Command (7xh)  
Table 104 Sense Condition Command (F0h)  
Table 105 Set Features Command (EFh)  
Table 106 Set Max Address Command (F9h)  
Table 107 Set Max Address Ext Command (37h)  
Table 108 Set Multiple Command (C6h)  
Table 109 Sleep Command (E6h/99h)  
Table 110 S.M.A.R.T. Function Set Command (B0h)  
Table 111 Log sector addresses  
Table 112 Device Attribute Data Structure  
Table 113 Individual Attribute Data Structure  
Table 114 Status Flag Definitions  
Table 115 Device Attribute Thresholds Data Structure  
Table 116 Individual Threshold Data Structure  
Table 117 SMART Log Directory  
Table 118 S.M.A.R.T. error log sector  
Table 119 Error log data structure  
Table 120 Command data structure  
Table 121 Error data structure  
Table 122 Self-test log data structure  
Table 123 Selective self-test log data structure  
Table 124 S.M.A.R.T. Error Codes  
Table 125 Standby Command (E2h/96h)  
Table 126 Standby Immediate Command (E0h/94h)  
Table 127 Write Buffer Command (E8h)  
Table 128 Write DMA Command (CAh/CBh)  
Table 129 Write DMA Ext Command (35h)  
Table 130 Write DMA FUA Ext Command (3Dh)  
Table 131 Write FPDMA Queued Command (61h)  
Table 132 Write Log Ext Command  
Table 133 Write Multiple Command (C5h)  
Table 134 Write Multiple Ext Command (39h)  
Table 135 Write Multiple FUA Ext Command (CEh)  
Table 136 Write Sector(s) Command (30h/31h)  
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5K320 SATA OEM Specification  
Table 137 Write Sector(s) Ext Command (34h)  
Table 138 Write Uncorrectable Ext Command (45h)  
Table 139 Timeout Values  
172  
173  
175  
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5K320 SATA OEM Specification  
General  
1 Introduction  
This document describes the specifications of the HITACHI Travelstar 5K320, a 2.5-inch hard disk  
drive with Serial ATA interface:  
Drive  
name  
Model Number  
Max data  
transfer rate  
(Gbps)  
Capacity  
(GB)  
Height (mm)  
Rotation  
speed (rpm)  
HTS543232L9A300  
HTS543232L9SA00  
HTS543225L9A300  
HTS543225L9SA00  
HTS543216L9A300  
HTS543216L9SA00  
HTS543212L9A300  
HTS543212L9SA00  
HTS543280L9A300  
HTS543280L9SA00  
3.0  
Travelstar  
5K320-320  
320  
250  
160  
120  
80  
9.5  
9.5  
9.5  
9.5  
9.5  
5400  
5400  
5400  
5400  
5400  
1.5  
3.0  
1.5  
3.0  
1.5  
3.0  
1.5  
3.0  
1.5  
Travelstar  
5K320-250  
Travelstar  
5K320-160  
Travelstar  
5K320-120  
Travelstar  
5K320-80  
1.1 Abbreviations  
Abbreviation  
32 KB  
64 KB  
“
Meaning  
32 x 1024 bytes  
64 x 1024 bytes  
inch  
A
amp  
AC  
alternating current  
Advanced Technology  
AT  
ATA  
Bels  
BIOS  
°C  
Advanced Technology Attachment  
unit of sound power  
Basic Input/Output System  
degrees Celsius  
CSA  
C-UL  
Cyl  
Canadian Standards Association  
Canadian-Underwriters Laboratory  
cylinder  
DC  
direct current  
DFT  
DMA  
ECC  
Drive Fitness Test  
Direct Memory Access  
error correction code  
9
     
5K320 SATA OEM Specification  
EEC  
EMC  
ERP  
Esd  
European Economic Community  
electromagnetic compatibility  
Error Recovery Procedure  
electrostatic discharge  
Federal Communications Commission  
field replacement unit  
gravity, a unit of force  
1 000 000 000 bits  
1 000 000 000 bytes  
ground  
FCC  
FRU  
G
Gb  
GB  
GND  
h
hexadecimal  
HDD  
Hz  
hard disk drive  
hertz  
I
Input  
ILS  
integrated lead suspension  
impedance  
imped  
I/O  
Input/Output  
ISO  
International Standards Organization  
1,000 bytes  
KB  
Kbit/mm  
Kbit/sq-mm  
KHz  
LBA  
Lw  
1,000 bits per mm  
1000 bits per square mm  
kilohertz  
logical block addressing  
unit of A-weighted sound power  
meter  
m
max. or Max.  
MB  
maximum  
1,000,000 bytes  
Mbps  
Mb/sec  
MB/sec  
MHz  
MLC  
mm  
1,000,000 Bit per second  
1,000,000 Bit per second  
1,000,000 bytes per second  
megahertz  
Machine Level Control  
millimeter  
ms  
millisecond  
us,  
s
microsecond  
Nm  
Newton meter  
No. or #  
oct/min  
O
number  
oscillations per minute  
Output  
10  
5K320 SATA OEM Specification  
OD  
Open Drain Programmed Input/Output  
Program I/O  
PIO  
POH  
Pop.  
P/N  
power on hours  
population  
part number  
p-p  
peak-to-peak  
PSD  
RES  
RFI  
power spectral density  
radiated electromagnetic susceptibility  
radio frequency interference  
relative humidity  
RH  
% RH  
RMS  
RPM  
RST  
R/W  
sec  
per cent relative humidity  
root mean square  
revolutions per minute  
reset  
read/write  
second  
Sect/Trk  
SELV  
S.M.A.R.T  
Trk.  
TTL  
UL  
sectors per track  
secondary low voltage  
Self-monitoring, analysis, and reporting technology  
track  
transistor-transistor logic  
Underwriters Laboratory  
volt  
V
VDE  
W
Verband Deutscher Electrotechniker  
watt  
3-state  
transistor-transistor tristate logic  
11  
5K320 SATA OEM Specification  
1.2 References  
Serial ATA International Organization : Serial ATA Revision 2.6  
1.3 General caution  
Do not apply force to the top cover (See figure below).  
Do not cover the breathing hole on the top cover (See figure below).  
Do not touch the interface connector pins or the surface of the printed circuit board.  
The drive can be damaged by shock or ESD (Electric Static Discharge). Any damages incurred to  
the drive after removing it from the shipping package and the ESD protective bag are the  
responsibility of the user  
1.4 Drive handling precautions  
Do not press on the drive cover during handling.  
12  
     
5K320 SATA OEM Specification  
2 Outline of the drive  
2.5-inch, 9.5-mm Height  
Perpendicular Recording  
Formatted capacities of 320GB, 250GB, 160GB,120GB and 80GB(512 bytes/sector)  
SATA Interface conforming to Serial ATA International Organization: Serial ATA Revision  
2.6(15-February-2007)  
Integrated controller  
No-ID recording format  
Coding : 100/102 2bit parity (199/200 RC Modulation Encoding)  
Multi zone recording  
Enhanced ECC  
10 bit 40 symbol non Interleaved Read Solomon code  
Non interleave On-The –Fly correction  
Included 2 symbol system ECC  
Segmented Buffer with write cache  
8192 KB - Upper 1078KB is used for firmware  
Fast data transfer rate  
HTS5432xxL9A3xx model : up to 3.0Gbit/s  
HTS5432xxL9SAxx model : up to 1.5Gbit/s  
Media data transfer rate (max):  
775 Mb/s  
Average seek time: 12 ms for read  
Closed-loop actuator servo (Embedded Sector Servo)  
Rotary voice coil motor actuator  
Load/Unload mechanism  
Mechanical latch  
0.55 Watts at idle state  
Power on to ready  
3.5 sec  
Operating shock  
3920 m/sec2 (400 G)/2ms  
1960 m/sec2 (200G)/1ms  
Non operating shock  
9800 m/sec2 (1000 G)/1ms  
Bulk Encryption optional (HTS5432xxL9SAxx model only)  
13  
 
5K320 SATA OEM Specification  
Part 1 Functional Specification  
14  
 
5K320 SATA OEM Specification  
3 Fixed disk subsystem description  
3.1 Control Electronics  
The control electronics works with the following functions:  
SATA Interface Protocol  
Embedded Sector Servo  
No-ID (TM) formatting  
Multizone recording  
Code: 100/102 bit parity (199/200 RC Modulation Encoding)  
System ECC  
Enhanced Adaptive Battery Life Extender  
3.2 Head disk assembly data  
The following technologies are used in the drive:  
Femto Slider  
Perpendicular recording disk and write head  
TMR head  
Integrated lead suspension (ILS)  
Load/unload mechanism  
Mechanical latch  
15  
     
5K320 SATA OEM Specification  
4 Fixed disk characteristics  
4.1 Formatted capacity by model number  
HTS543232L9A300  
HTS543232L9SA00  
HTS543225L9A300  
HTS543225L9SA00  
Description  
Physical Layout  
Bytes per Sector  
Number of Heads  
Number of Disks  
Logical Layout  
512  
4
2
512  
4 / 3  
2
Number of Heads  
Number of Sectors/  
Track  
16  
63  
16  
63  
Number of  
16,383  
16,383  
Cylinders  
Number of Sectors  
Total Logical Data  
Bytes  
625,142,448  
320,072,933,376  
488,397,168  
250,059,350,016  
HTS543216L9A300  
HTS543216L9SA00 HTS543212L9SA00 HTS543280L9SA00  
HTS543212L9A300  
HTS543280L9A300  
Description  
Physical Layout  
Bytes per Sector  
Number of Heads  
Number of Disks  
Logical Layout  
512  
2
1
512  
2
1
512  
1
1
Number of Heads  
Number of Sectors/  
Track  
16  
63  
16  
63  
16  
63  
Number of  
16,383  
16,383  
16,383  
Cylinders  
Number of Sectors  
Total Logical Data  
Bytes  
312,581,808  
160,041,885,696  
234,441,648  
120,034,123,776  
156,301,488  
80,026,361,856  
Table 1. Formatted capacity by model number.  
16  
     
5K320 SATA OEM Specification  
4.2 Data sheet  
320  
GB  
5400  
729  
250  
GB  
5400  
775  
160  
GB  
5400  
729  
120  
80  
GB  
5400  
729  
GB  
5400  
674  
Rotational Speed (RPM)  
Data transfer rates (buffer to/from  
media) (Mbps)  
Data transfer rates (Gbit/sec)  
1.5/  
3.0  
1.5/  
3.0  
1.5/  
3.0  
1.5/  
3.0  
1.5/  
3.0  
Recording density (Kbit/mm) (Max)  
(KBPI) (Max)  
Track density (Ktrack/mm)(Max)  
(KTPI)(Max)  
1154  
216  
1207  
216  
1154  
216  
1066  
182  
1154  
216  
Areal density (Kbit/sq-mm.- Max)  
(Gbit/sq-inch - Max)  
Number of zones  
250  
24  
261  
24  
250  
24  
194  
24  
250  
24  
Table 2. Data sheet  
4.3 Cylinder allocation  
Data format is allocated by each head characteristics. Typical format is described below.  
160GB/p Mid BIP-Mid TPI format  
Zone  
Cylinder  
No. of  
Sectors/Trk  
1512  
1476  
1440  
1404  
1377  
1350  
1323  
1269  
1242  
1224  
1188  
1134  
1116  
1080  
1044  
1026  
999  
0
1
2
3
4
5
6
7
8
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8187  
12103  
19045  
26076  
29903  
35866  
40672  
49750  
55624  
59273  
66126  
72979  
76717  
85439  
88910  
92381  
96831  
103239  
111160  
115432  
122374  
127625  
136258  
138305  
8188  
12104  
19046  
26077  
29904  
35867  
40673  
49751  
55625  
59274  
66127  
72980  
76718  
85440  
88911  
92382  
96832  
103240  
111161  
115433  
122375  
127626  
136259  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
972  
918  
891  
864  
810  
756  
729  
Table 3. Cylinder allocation  
17  
       
5K320 SATA OEM Specification  
4.4 Performance characteristics  
Drive performance is characterized by the following parameters:  
Command Overhead  
Mechanical Positioning  
 Seek Time  
 Latency  
Data Transfer Speed  
Buffering Operation (Look ahead/Write Cache)  
Note: All the above parameters contribute to drive performance. There are other parameters which  
contribute to the performance of the actual system. This specification defines the essential characteristics  
of the drive. This specification does not include the system throughput as this is dependent upon the  
system and the application.  
The following table gives a typical value for each parameter.  
Function  
Average Random Seek Time - Read (ms)  
Average Random Seek Time - Write (ms)  
Rotational Speed (RPM)  
12  
13  
5400  
3.5  
Power-on-to-ready (sec)  
Command overhead (ms)  
1.0  
Disk-buffer data transfer (Mb/s) (max)  
Buffer-host data transfer (Gbit/s) (max)  
Table 4. Performance characteristics  
775  
1.5 / 3.0  
4.4.1  
Command overhead  
Command overhead time is defined as the interval from the time that a drive receives a command to the  
time that the actuator starts its motion.  
18  
   
5K320 SATA OEM Specification  
4.4.2  
Mechanical positioning  
4.4.2.1 Average seek time (including settling)  
Command Type  
Read  
Typical (ms)  
Max. (ms)  
12  
13  
14  
15  
Write  
Table 5. Mechanical positioning performance  
Typical and Max. are defined throughout the performance specification as follows:  
Typical  
Max.  
Average of the drive population tested at nominal environmental and voltage conditions.  
Maximum value measured on any one drive over the full range of the environmental and  
voltage conditions. (See section 6.1, "Environment" and section 6.2, "DC power  
requirements" )  
The seek time is measured from the start of motion of the actuator to the start of a reliable read or write  
operation. A reliable read or write operation implies that error correction/recovery is not employed to  
correct arrival problems. The Average Seek Time is measured as the weighted average of all possible  
seek combinations.  
max.  
(max. + 1 – n)(Tnin + Tnout)  
n=1  
Weighted Average = ––––––––––––––––––––––––––––  
(max. + 1)(max)  
Where: max.  
= maximum seek length  
n = seek length (1-to-max.)  
Tnin  
Tnout  
= inward measured seek time for an n-track seek  
= outward measured seek time for an n-track seek  
4.4.2.2 Full stroke seek  
Command Type  
Typical (ms)  
Max. (ms)  
25.0  
Read  
Write  
20.0  
21.0  
26.0  
Table 6. Full stroke seek time  
Full stroke seek time in milliseconds is the average time of 1000 full stroke seeks.  
4.4.2.3 Single track seek time (without command overhead, including  
settling)  
Command Type  
Typical (ms)  
Maximum (ms)  
Read  
Write  
1.0  
1.1  
2.0  
2.2  
Table 7. Single track seek time  
Single track seek is measured as the average of one (1) single track seek from every track in both  
directions (inward and outward).  
4.4.2.4 Average latency  
Rotational Speed  
(RPM)  
Time for one revolution  
Average Latency  
(ms)  
(ms)  
5400  
11.1  
5.5  
Table 8. Latency time  
19  
       
5K320 SATA OEM Specification  
4.4.2.5 Drive ready time  
Condition  
Power On To Ready  
Table 9. Drive ready time  
Typical (sec)  
3.5  
Max. (sec)  
9.5  
Ready  
The condition in which the drive is able to perform a media access command  
(for example—read, write) immediately.  
Power On To Ready This includes the time required for the internal self diagnostics.  
20  
 
5K320 SATA OEM Specification  
4.4.3  
Operating modes  
Operating mode Description  
Start up time period from spindle stop or power down.  
Spin-Up  
Seek  
Seek operation mode  
Write operation mode  
Read operation mode  
Write  
Read  
The device is capable of responding immediately to media access requests. All  
Performance idle electronic components remain powered and the full frequency servo remains  
operational.  
The device is capable of responding immediately to media access requests. Some  
circuitry—including servo system and R/W electronics—is in power saving mode.  
Active idle  
The head is parked near the mid-diameter the disk without servoing.  
A device in Active idle mode may take longer to complete the execution of a  
command because it must activate that circuitry.  
The head is unloaded onto the ramp position. The spindle motor is rotating at full  
speed.  
Low power idle  
Standby  
The device interface is capable of accepting commands. The spindle motor is  
stopped. All circuitry but the host interface is in power saving mode.  
The execution of commands is delayed until the spindle becomes ready.  
The device requires a soft reset or a hard reset to be activated. All electronics,  
including spindle motor and host interface, are shut off.  
Sleep  
Table 10. Operating mode  
4.4.3.1 Mode transition time  
From  
To  
Transition  
Time (typ)  
2.5  
Transition Time  
(max.)  
9.5  
Standby  
Idle  
Table 11. Drive ready time  
4.4.3.2 Operating mode at power on  
The device goes into Idle mode after power on or hard reset as an initial state..  
4.4.3.3 Adaptive power save control  
The transient timing from Performance Idle mode to Active Idle mode and Active Idle mode to Low Power  
Idle mode is controlled adaptively according to the access pattern of the host system. The transient  
timing from Low Power Idle mode to Standby mode is also controlled adaptively, if it is allowed by Set  
Features Enable Advanced Power Management subcommand.  
21  
   
5K320 SATA OEM Specification  
5 Data integrity  
5.1 Data loss on power off  
Data loss will not be caused by a power off during any operation except the write operation.  
A power off during a write operation causes the loss of any received or resident data that has not  
been written onto the disk media.  
A power off during a write operation might make a maximum of one sector of data unreadable. This  
state can be recovered by a rewrite operation.  
5.2 Write Cache  
When the write cache is enabled, the write command may complete before the actual disk write operation  
finishes. This means that a power off, even after the write command completion, could cause the loss of  
data that the drive has received but not yet written onto the disk.  
In order to prevent this data loss, confirm the completion of the actual write operation prior to the power  
off by issuing a  
Soft reset  
Hard reset  
Flush Cache command  
Standby command  
Standby Immediate command  
Sleep command  
Confirm the command’s completion.  
5.3 Equipment status  
The equipment status is available to the host system any time the drive is not ready to read, write, or seek.  
This status normally exists at the power-on time and will be maintained until the following conditions are  
satisfied:  
The access recalibration/tuning is complete.  
The spindle speed meets the requirements for reliable operation.  
The self-check of the drive is complete.  
The appropriate error status is made available to the host system if any of the following conditions occur  
after the drive has become ready:  
 The spindle speed lies outside the requirements for reliable operation.  
 The occurrence of a Write Fault condition.  
5.4 WRITE safety  
The drive ensures that the data is written into the disk media properly. The following conditions are  
monitored during a write operation. When one of these conditions exceeds the criteria, the write operation  
is terminated and the automatic retry sequence is invoked.  
Head off track  
External shock  
Low supply voltage  
Spindle speed out of tolerance  
Head open/short  
22  
         
5K320 SATA OEM Specification  
5.5 Data buffer test  
The data buffer is tested at power on reset and when a drive self-test is requested by the host. The test  
consists of a write/read '00'x and 'ff'x pattern on all buffers.  
5.6 Error recovery  
Errors occurring on the drive are handled by the error recovery procedure.  
Errors that are uncorrectable after application of the error recovery procedure are reported to the host  
system as nonrecoverable errors.  
5.7 Automatic reallocation  
The sectors that show some errors may be reallocated automatically when specific conditions are met.  
The drive does not report any auto reallocation to the host system. The conditions for auto reallocation  
are described below.  
5.7.1  
Nonrecovered write errors  
When a write operation cannot be completed after the Error Recovery Procedure (ERP) is fully carried out,  
the sectors are reallocated to the spare location. An error is reported to the host system only when the  
write cache is disabled and the auto reallocation has failed.  
5.7.2  
Nonrecoverable read error  
When a read operation fails after ERP is fully carried out, a hard error is reported to the host system. This  
location is registered internally as a candidate for the reallocation. When a registered location is specified  
as a target of a write operation, a sequence of media verification is performed automatically. When the  
result of this verification meets the required criteria, this sector is reallocated.  
5.7.3  
Recovered read errors  
When a read operation for a sector fails and is recovered at the specific ERP step, the sector is  
reallocated automatically. A media verification sequence may be run prior to the reallocation according to  
the predefined conditions.  
23  
     
5K320 SATA OEM Specification  
5.8 ECC  
The 10 bit symbol non interleaved ECC processor provides user data verification and correction  
capability. The first 6 symbol of ECC are 4 check symbols for user data and the 2 symbol system ECC.  
The other 34 symbols are Read Solomon ECC. Hardware logic corrects up to 16 symbols(20 bytes)  
errors on-the-fly.  
2 symbol System ECC is generated when HDC receives user data from HOST, and can correct up to 1  
symbol(10bit) errors on-the-fly when one transfers to HOST.  
24  
 
5K320 SATA OEM Specification  
6 Specification  
6.1 Environment  
6.1.1  
Temperature and humidity  
Operating conditions  
5 to 55°C (See note below)  
Temperature  
Relative humidity  
8 to 90% noncondensing  
29.4°C noncondensing  
20°C/hour  
Maximum wet bulb temperature  
Maximum temperature gradient  
Altitude  
–300 to 3048 m (10,000 ft)  
Nonoperating conditions  
Temperature  
–40 to 65°C  
Relative humidity  
5 to 95% noncondensing  
40°C noncondensing  
20°C/hour  
Maximum wet bulb temperature  
Maximum temperature gradient  
Altitude  
–300 to 12,192 m (40,000 ft)  
Table 12. Environmental condition  
The system is responsible for providing sufficient air movement to maintain surface temperatures below  
60°C at the center of top cover and below 63°C at the center of the drive circuit board assembly.  
The maximum storage period in the shipping package is one year.  
Specification (Environment)  
100  
41'C/95%  
90  
31'C/90%  
WetBulb 40'C  
80  
70  
WetBulb29.4'C  
60  
Non Operating  
50  
Operating  
40  
65'C/23%  
30  
20  
55'C/15%  
10  
0
-45  
-35  
-25  
-15  
-5  
5
15  
25  
35  
45  
55  
65  
Temperature (degC)  
Figure 1. Limits of temperature and humidity  
6.1.2  
Corrosion test  
The hard disk drive must be functional and show no signs of corrosion after being exposed to a  
temperature humidity stress of 50°C/90%RH (relative humidity) for one week followed by a temperature  
and humidity drop to 25'C/40%RH in 2 hours.  
25  
       
5K320 SATA OEM Specification  
6.1.3  
Radiation noise  
The disk drive shall work without degradation of the soft error rate under the following magnetic flux  
density limits at the enclosure surface.  
Frequency (KHz)  
DC  
Limits (uT RMS)  
1500 0-p  
0 < Frequency =< 60  
60 < Frequency =<100  
100 < Frequency =< 200  
200 < Frequency =< 400  
Table 13. Magnetic flux density limits  
500 RMS  
250 RMS  
100 RMS  
50 RMS  
6.1.4  
Conductive noise  
The disk drive shall work without soft error degradation in the frequency range from DC to 20 Mhz  
injected through any two of the mounting screw holes of the drive when an AC current of up to 45 mA  
(p-p) is applied through a 50-ohm resistor connected to any two mounting screw holes.  
26  
 
5K320 SATA OEM Specification  
6.2 DC power requirements  
Connection to the product should be made in a safety extra low voltage (SELV) circuits. The voltage  
specifications are applied at the power connector of the drive.  
Item  
Nominal supply  
Supply voltage  
Power supply ripple (0–20  
MHz)1  
Requirements  
+5 Volt dc  
–0.3 Volt to 6.0 Volt  
100 mV p-p max.  
Tolerance 2  
±5%  
Supply rise time  
1–100 ms  
Watts (RMS Typical) 7  
Performance Idle average 3  
Active Idle average  
1.7  
0.8  
0.55  
1.8  
Low Power Idle average  
Read average 4  
Write average  
1.8  
2.2  
Seek average 5  
Standby  
0.2  
0.1  
5.0  
Sleep  
6
Startup (maximum peak)  
Average from power on to  
ready  
3.8  
Table 14. DC Power requirements  
Footnotes:  
1.  
2.  
The maximum fixed disk ripple is measured at the 5 volt input of the drive.  
The disk drive shall not incur damage for an over voltage condition of +25% (maximum  
duration of 20 ms) on the 5 volt nominal supply.  
3.  
4.  
The idle current is specified at an inner track.  
The read/write current is specified based on three operations of 63 sector read/write per  
100 ms.  
5.  
6.  
7.  
The seek average current is specified based on three operations per 100 ms.  
The worst case operating current includes motor surge.  
“Typical” mean average of the drive population tested at nominal environmental and  
voltage conditions.  
27  
   
5K320 SATA OEM Specification  
6.2.1  
Power consumption efficiency  
Capacity  
320GB 250GB 160GB 120GB 80GB  
0.0017 0.0022 0.0034 0.0046 0.0069  
Power Consumption Efficiency  
(Watts/GB)  
Table 15. Power consumption efficiency  
Note: Power consumption efficiency is calculated as Power Consumption of Low Power Idle Watt/  
Capacity (GB).  
28  
 
5K320 SATA OEM Specification  
6.3 Reliability  
6.3.1  
Data reliability  
 Probability of not recovering data is 1 in 1014 bits read  
 ECC implementation  
On-the-fly correction performed as a part of read channel function recovers up to 16 symbols of error in 1  
sector (1 symbol is 10 bits).  
6.3.2  
Failure prediction (S.M.A.R.T.)  
The drive supports Self-monitoring, analysis and reporting technology (S.M.A.R.T.) function. The details  
are described in section 11.8, "S.M.A.R.T. Function" and in Section 13.32, "S.M.A.R.T. Function Set  
(B0h)"  
6.3.3  
Cable noise interference  
To avoid any degradation of performance throughput or error when the interface cable is routed on top or  
comes in contact with the HDA assembly, the drive must be grounded electrically to the system frame by  
four screws. The common mode noise or voltage level difference between the system frame and power  
cable ground or AT interface cable ground should be in the allowable level specified in the power  
requirement section.  
6.3.4  
Service life and usage condition  
The drive is designed to be used under the following conditions:  
The drive should be operated within specifications of shock, vibration, temperature, humidity, altitude,  
and magnetic field.  
The drive should be protected from ESD.  
The breathing hole in the top cover of the drive should not be covered.  
Force should not be applied to the cover of the drive.  
The specified power requirements of the drive should be satisfied.  
The drive frame should be grounded electrically to the system through four screws.  
The drive should be mounted with the recommended screw depth and torque.  
The interface physical and electrical requirements of the drive should satisfy Serial ATA Revision 2.6.  
 The power-off sequence of the drive should comply with the 6.3.6.2,"Required power-off  
sequence.”  
Service life of the drive is approximately 5 years or 20,000 power on hours, whichever comes first, under  
the following assumptions:  
Less than 333 power on hours per month.  
Seeking/Writing/Reading operation is less than 20% of power on hours.  
This does not represent any warranty or warranty period. Applicable warranty and warranty period are  
covered by the purchase agreement.  
29  
 
5K320 SATA OEM Specification  
6.3.5  
Preventive maintenance  
Load/unload  
None.  
6.3.6  
The product supports a minimum of 600,000 normal load/unloads.  
Load/unload is a functional mechanism of the hard disk drive. It is controlled by the drive micro code.  
Specifically, unloading of the heads is invoked by the following commands:  
Standby  
Standby immediate  
Sleep  
Load/unload is also invoked as one of the idle modes of the drive.  
The specified start/stop life of the product assumes that load/unload is operated normally, not in  
emergency mode.  
6.3.6.1 Emergency unload  
When hard disk drive power is interrupted while the heads are still loaded the micro code cannot operate  
and the normal 5-volt power is unavailable to unload the heads. In this case, normal unload is not  
possible. The heads are unloaded by routing the back EMF of the spinning motor to the voice coil. The  
actuator velocity is greater than the normal case and the unload process is inherently less controllable  
without a normal seek current profile.  
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently  
uncontrolled, it is more mechanically stressful than a normal unload.  
The drive supports a minimum of 20,000 emergency unloads.  
6.3.6.2 Required Power-Off Sequence  
The required host system sequence for removing power from the drive is as follows:  
Step 1: Issue one of the following commands.  
Standby  
Standby immediate  
Sleep  
Note: Do not use the Flush Cache command for the power off sequence because this command  
does not invoke Unload.  
Step 2: Wait until the Command Complete status is returned.  
In a typical case 500 ms are required for the command to finish completion; however, the host system  
time out value needs to be 30 seconds considering error recovery time.  
Step 3: Terminate power to HDD.  
This power-down sequence should be followed for entry into any system power-down state, system  
suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited  
to rare scenarios, such as battery removal during operation.  
6.3.6.3 Power switch design considerations  
In systems that use the Travelstar 5K320 consideration should be given to the design of the system  
power switch.  
Hitachi recommends that the switch operate under control of the host system, as opposed to being  
hardwired. The same recommendation is made for cover-close switches. When a hardwired switch is  
30  
5K320 SATA OEM Specification  
turned off, emergency unload occurs, as well as the problems cited in section 5.1, "Data loss by power  
off" and section 5.2, “Write Cache”.  
6.3.6.4 Test considerations  
Start/stop testing is classically performed to verify head/disk durability. The heads do not land on the disk,  
so this type of test should be viewed as a test of the load/unload function.  
Start/Stop testing should be done by commands through the interface, not by power cycling the drive.  
Simple power cycling of the drive invokes the emergency unload mechanism and subjects the HDD to  
nontypical mechanical stress.  
Power cycling testing may be required to test the boot-up function of the system. In this case HItachi  
recommends that the power-off portion of the cycle contain the sequence specified in section 6.3.6.2,  
"Required Power-Off Sequence”. If this is not done, the emergency unload function is invoked and  
nontypical stress results.  
31  
5K320 SATA OEM Specification  
6.4 Mechanical specifications  
6.4.1  
Physical dimensions and weight  
The following figure lists the dimensions for the drive.  
Model  
Height (mm)  
9.5±0.2  
9.5±0.2  
Width (mm)  
69.85±0.25  
69.85±0.25  
Length (mm)  
100.2±0.25  
100.2±0.25  
Weight (gram)  
102 Max  
95 Max  
320GB, 250GB models  
160GB, 120GB, 80GB models  
Table 16. Physical dimensions and weight  
6.4.2  
Mounting hole locations  
The mounting hole locations and size of the drive are shown below.  
Figure 2. Mounting hole locations  
32  
     
5K320 SATA OEM Specification  
6.4.3  
Connector description  
Connector specifications are included in section 7.2, "Interface connector" .  
6.4.4  
Mounting orientation  
The drive will operate in all axes (six directions) and will stay within the specified error rates when tilted ±5  
degrees from these positions.  
Performance and error rate will stay within specification limits if the drive is operated in the other  
permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation will  
be able to run vertically and vice versa.  
The recommended mounting screw torque is 0.3±0.05 Nm.  
The recommended mounting screw depth is 3.0±0.3 mm for bottom and 3.5±0.5 mm for horizontal  
mounting.  
The user is responsible for using the appropriate screws or equivalent mounting hardware to mount  
the drive securely enough to prevent excessive motion or vibration of the drive at seek operation or  
spindle rotation.  
6.4.5  
Load/unload mechanism  
The head load/unload mechanism is provided to protect the disk data during shipping, movement, or  
storage. Upon power down, a head unload mechanism secures the heads at the unload position. See  
section 6.5.4, "Nonoperating shock" for additional details.  
33  
5K320 SATA OEM Specification  
6.5 Vibration and shock  
All vibration and shock measurements in this section are for drives without mounting attachments for  
systems. The input level shall be applied to the normal drive mounting points.  
Vibration tests and shock tests are to be conducted by mounting the drive to a table using the bottom four  
mounting holes.  
6.5.1  
Operating vibration  
The drive will operate without a hard error while being subjected to the following vibration levels.  
6.5.1.1 Random vibration  
The test consists of 30 minutes of random vibration using the power spectral density (PSD) levels below.  
The vibration test level is 6.57 m/sec2 RMS (Root Mean Square) (0.67 G RMS).  
Random vibration PSD profile Breakpoint  
Hz  
5
m x 10n (m2/sec4)/Hz  
1.9 x E–3  
17  
1.1 x E–1  
45  
1.1 x E–1  
48  
7.7 x E–1  
62  
7.7 x E–1  
65  
9.6 x E–2  
150  
200  
500  
9.6 x E–2  
4.8 x E–2  
4.8 x E–2  
Table 17. Random vibration PSD profile breakpoints (operating)  
6.5.1.2 Swept sine vibration  
Swept sine vibration (zero to peak 5 to  
500 to 5 Hz sine wave)  
Sweep rate (oct/min)  
1.0  
9.8 m/sec2 (1 G) (5-500 Hz)  
Table 18. Swept sine vibration  
34  
     
5K320 SATA OEM Specification  
6.5.2  
Nonoperating vibration  
The disk drive withstands the following vibration levels without any loss or permanent damage.  
6.5.2.1 Random vibration  
The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration  
of 15 minutes per axis. The PSD levels for the test simulating the shipping and relocation environment is  
shown below.  
Hz  
2.5  
(m2/sec4)/Hz  
0.096  
5
2.88  
40  
1.73  
500  
1.73  
Table 19. Random Vibration PSD Profile Breakpoints (nonoperating)  
Note: Overall RMS level of vibration is 29.50 m/sec2 (3.01 G).  
6.5.2.2 Swept sine vibration  
49 m/sec2 (5 G) (zero-to-peak), 10 to 500 to 10 Hz sine wave  
0.5 oct/min sweep rate  
25.4 mm (peak-to-peak) displacement, 5 to 10 to 5 Hz  
6.5.3  
Operating shock  
The hard disk drive meets the criteria in the table below while operating under these conditions:  
The shock test consists of 10 shock inputs in each axis and direction for a total of 60.  
There must be a minimum delay of 3 seconds between shock pulses.  
The disk drive will operate without a hard error while subjected to the following half-sine shock pulse.  
Duration of 1 ms  
Duration of 2 ms  
1960 m/sec2 (200 G)  
3920 m/sec2 (400 G)  
Table 20. Operating shock  
The input level shall be applied to the normal disk drive subsystem mounting points used to secure the  
drive in a normal system.  
6.5.4  
Nonoperating shock  
The drive withstands the following half-sine shock pulse without any data loss or permanent damage.  
Duration of 1 ms  
Duration of 11 ms  
9800 m/sec2 (1000 G)  
1470 m/sec2 (150 G)  
Table 21. Nonoperating shock  
The shocks are applied for each direction of the drive for three mutually perpendicular axes, one axis at a  
time. Input levels are measured on a base plate where the drive is attached with four screws.  
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5K320 SATA OEM Specification  
6.6 Acoustics  
6.6.1  
Sound power level  
The criteria of A-weighted sound power level are described below.  
Measurements are to be taken in accordance with ISO 7779. The mean of the sample of 40 drives is to  
be less than the typical value. Each drive is to be less than the maximum value. The drives are to meet  
this requirement in both board down orientations.  
A-weighted Sound Power  
Typical (Bels)  
Maximum (Bels)  
Idle  
2.4  
2.6  
2.7  
2.9  
Operating  
Table 22. Weighted sound power  
The background power levels of the acoustic test chamber for each octave band are to be recorded.  
Sound power tests are to be conducted with the drive supported by spacers so that the lower surface of  
the drive be located 25±3 mm above from the chamber floor. No sound absorbing material shall be used.  
The acoustical characteristics of the disk drive are measured under the following conditions:  
Mode definitions  
Idle mode: Power on, disks spinning, track following, unit ready to receive and respond to control line  
commands.  
Operating mode: Continuous random cylinder selection and seek operation of the actuator with a  
dwell time at each cylinder. The seek rate for the drive can be calculated as shown below.  
Ns = 0.4/(Tt + T1)  
where:  
Ns = average seek rate in seeks/s  
Tt = published seek time from one random track to another without including rotational  
latency  
T1= equivalent time in seconds for the drive to rotate by half a revolution  
6.6.2  
Discrete tone penalty  
Discrete tone penalties are added to the A-weighted sound power (Lw) with the following formula only  
when determining compliance.  
Lwt(spec) = Lw = 0.1Pt + 0.3 < 4.0 (Bels)  
where  
Lw = A-weighted sound power level  
Pt = Value of desecrate tone penalty = dLt – 6.0(dBA)  
dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band.  
36  
   
5K320 SATA OEM Specification  
6.7 Identification labels  
The following labels are affixed to every drive:  
A label which is placed on the top of the head disk assembly containing the statement "Made by  
Hitachi" or equivalent, part number  
A bar code label which is placed on the disk drive based on user request. The location on the disk  
drive is to be designated in the drawing provided by the user.  
Labels containing the vendor's name, disk drive model number, serial number, place of manufacture,  
and UL/CSA logos.  
6.8 Electromagnetic compatibility  
When installed in a suitable enclosure and exercised with a random accessing routine at maximum data  
rate, the drive meets the following worldwide electromagnetic compatibility (EMC) requirements:  
・ United States Federal Communications Commission (FCC) Rules and Regulations (Class B),  
Part 15. RFI Suppression German National Requirements  
・ RFI Japan VCCI, Requirements of HITACHI products  
・ EU EMC Directive, Technical Requirements and Conformity Assessment Procedures  
6.8.1  
CE Mark  
The product is certified for compliance with EC directive 89/336/EEC. The EC marking for the certification  
appears on the drive.  
6.8.2  
C-Tick Mark  
The product complies with the Australian EMC standard "Limits and methods of measurement of radio  
disturbance characteristics of information technology equipment, AS/NZS 3548:1995 Class B."  
6.8.3  
BSMI Mark  
The product complies with the Taiwan EMC standard “Limits and methods of measurement of radio  
disturbance characteristics of information technology equipment, CNS 13438 (C6357)”  
6.8.4  
MIC Mark  
The product complies with the Korea EMC standard. The regulation for certification of information and  
communication equipment is based on “Telecommunications Basic Act” and “Radio Waves Act” Korea  
EMC requirment are based technically on CISPR22:1993-12 measurement standards and limits. MIC  
standards are likewise based on IEC standards.  
37  
   
5K320 SATA OEM Specification  
6.9 Safety  
6.9.1  
UL and CSA approval  
All models of the Travelstar 5K320 are qualified per UL60950-1:2003  
6.9.2  
IEC compliance  
All models of the Travelstar 5K320 comply with IEC 60950-1:2001.  
6.9.3  
German Safety Mark  
All models of the Travelstar 5K320 are approved by TUV on Test Requirement: EN 60950-1:2001, but the  
GS mark has not been obtained.  
6.9.4  
Flammability  
The printed circuit boards used in this product are made of material with a UL recognized  
flammability rating of V-1 or better. The flammability rating is marked or etched on the board. All  
other parts not considered electrical components are made of material with a UL recognized  
flammability rating of V-1 or better except minor mechanical parts.  
6.9.5  
Secondary circuit protection  
This product utilizes printed circuit wiring that must be protected against the possibility of  
sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection  
Against Combustion). Adequate secondary over current protection is the responsibility of the using  
system.  
The user must protect the drive from its electrical short circuit problem. A 10 amp limit is required  
for safety purpose.  
6.10 Packaging  
Drives are packed in ESD protective bags and shipped in appropriate containers.  
6.11 Substance restriction requirements  
The product complies with the Directive 2002/95/EC of the European Parliament on the restrictions  
of the use of the certain hazardous substances in electrical and electronic equipment (RoHS).  
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5K320 SATA OEM Specification  
7 Electrical interface specifications  
7.1 Cabling  
The maximum cable length from the host system to the hard disk drive plus circuit pattern length in the  
host system shall not exceed 1 meter.  
7.2 Interface connector  
The figure below shows the physical pin location.  
Figure 3. Interface connector pin assignments  
All pins are in a single row, with a 127 mm(.050”) pitch.  
The comments on the mating sequence in Table in the section 7.3 apply to the case of back-plane  
blind-mate connector only. In this case, the mating sequences are:(1)the ground pins P4 and P12;(2)  
the pre-charge power pins and the other ground pins; and (3) the signal pins and the rest of the  
power pins.  
There are three power pins for each voltage. One pin from each voltage is used for pre-charge in the  
backplane blind-mate situation.  
If a device uses 3.3V, then all V33 pins must be terminated. Otherwise, it is optional to terminate any  
of the V33 pins  
If a device uses 5.0V, then all V5 pins must be terminated. Otherwise, it is optional to terminate any  
of the V5 pins  
If a device uses 12.0V, then all V12 pins must be terminated. Otherwise, it is optional to terminate  
any of the V12 pins.  
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5K320 SATA OEM Specification  
7.3 Signal definitions  
The pin assignments of interface signals are listed as follows:  
No.  
S1  
S2  
S3  
Plug Connector pin definition  
2nd mate  
Signal  
Gnd  
I/O  
GND  
A+  
Differential signal A from Phy  
RX+  
RX-  
Input  
Input  
A-  
Signal  
S4  
S5  
Gnd  
B-  
2nd mate  
Differential signal B from Phy  
Gnd  
TX-  
Output  
Output  
S6  
S7  
B+  
TX+  
Gnd  
Gnd  
2nd mate  
Key and spacing separate signal and power  
segments  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
P8  
P9  
V33  
V33  
V33  
Gnd  
Gnd  
Gnd  
V5  
3.3V power  
3.3V  
3.3V  
3.3V  
Gnd  
Gnd  
Gnd  
5V  
3.3V power  
3.3V power, pre-charge, 2nd Mate  
1st mate  
2nd mate  
2nd mate  
5V power,pre-charge,2nd Mate  
5V power  
V5  
5V  
Power  
V5  
5V power  
2nd mate  
5V  
Gnd  
P10 Gnd  
DAS/DSS  
P11  
Device Activity Signal / Disable Staggered  
Note 1  
Spinup1  
P12 Gnd  
P13 V12  
P14 V12  
P15 V12  
1st mate  
Gnd  
V12  
V12  
V12  
12V power,pre-chage,2nd mate  
12V power  
12V power  
Table 23. Interface connector pins and I/O signals  
Note 1;  
Pin P11 is used by the drive to provide the host with an activity indication and by the host to  
indicate whether staggered spinup should be used.  
The signal the drive provides for activity indication is a low-voltage low-current driver.  
If pin P11 is asserted low the drive shall disable staggered spin-up and immediately initiate  
spin-up. If pin P11 is not connected in the host (floating), the drive shall enable staggered spin-up.  
7.3.1  
TX+ / TX-  
These signal are the outbound high-speed differential signals that are connected to the serial ATA  
cable  
7.3.2  
RX+ / RX-  
These signals are the inbound high-speed differential signals that are connected to the serial ATA  
cable.  
The following standard shall be referenced about signal specifications.  
Serial ATA: High Speed Serialized AT Attachment Revision 1.0a 7-January -2003  
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5K320 SATA OEM Specification  
41  
5K320 SATA OEM Specification  
7.3.3  
Out of band signaling  
Figure 4 shows the timing of COMRESET, COMINIT and COMWAKE.  
t1  
t2  
COMRESET/COMINIT  
COMWAKE  
t3  
t4  
PARAMETER  
Nominal (ns)  
DESCRIPTION  
T1  
T2  
T3  
T4  
ALINE primitives  
Spacing  
106.7  
320  
ALIGN primitives  
Psacing  
106.7  
106.7  
Figure 4. Parameter descriptions  
42  
 
5K320 SATA OEM Specification  
43  
5K320 SATA OEM Specification  
Part 2 Interface Specification  
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5K320 SATA OEM Specification  
8 General  
8.1 Introduction  
This specification describes the host interface of HTS5432XXL9SA00 / HTS5432XXL9A300.  
The interface conforms to following Working Document of Information technology with certain  
limitations described in the chapter 9 “Deviations from Standard” on Page 45..  
Serial ATA International Organization : Serial ATA Revision 2.6 dated on 15 February 2007  
AT Attachment 8 – ATA/ATAPI Command Set (ATA8-ACS) Revision 3f dated on 11 December 2006  
HTS5432XXL9SA00 / HTS5432XXL9A300 support following functions as Vendor Specific Function.  
Format Unit Function  
SENSE CONDITION command  
8.2 Terminology  
Device  
Host  
INTRQ  
Device indicates HTS5432XXL9SA00 / HTS5432XXL9A300  
Host indicates the system that the device is attached to.  
Interrupt request (Device or Host)  
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5K320 SATA OEM Specification  
9 Deviations from Standard  
The device conforms to the referenced specifications, with deviations described below.  
The interface conforms to the Working Document of Information Technology, AT Attachment 8 –  
ATA/ATAPI Command Set (ATA/ATAPI8-ACS) Revision 3f dated 11 Dec. 2006, with deviation as  
follows:  
S.M.A.R.T. Return Status S.M.A.R.T. RETURN STATUS subcommand does not check advisory attributes.  
That is, the device will not report threshold exceeded condition unless pre-failure  
attributes exceed their corresponding thresholds. For example, Power-On Hours  
Attribute never results in negative reliability status.  
Check Power Mode  
Check Power Mode command returns FFh to Sector Count Register when the device  
is in Idle mode. This command does not support 80h as the return value.  
10 Physical Interface  
Physical Interface is described in Functional Specification part.  
11 Registers  
In Serial ATA, the host adapter contains a set of registers that shadow the contents of the traditional  
device registers, referred to as the Shadow Register Block. Shadow Register Block registers are  
interface registers used for delivering commands to the device or posting status from the device.  
About details, please refer to the Serial ATA Specification.  
In the following cases, the host adapter sets the BSY bit in its shadow Status Register and transmits  
a FIS to the device containing the new contents.  
Command register is written in the Shadow Register Block  
Device Control register is written in the Shadow Register Block with a change of state of the  
SRST bit  
COMRESET is requested  
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5K320 SATA OEM Specification  
11.1 Register naming convention  
This specification uses the same naming conventions for the Command Block Registers as the  
ATA8-ACS standard. However, the register naming convention is different from that uses in the  
Serial ATA 2.6 specification. The following table defines the corresponding of the register names  
used in this specification with those used in the Serial ATA 2.6 specification.  
Register name in this  
specification when  
writing registers  
Register name in this  
specification when  
reading registers  
Serial ATA register  
name  
Features  
Feature current  
Feature previous  
Sector count current  
Sector count previous  
LBA low current  
LBA low previous  
LBA mid current  
LBA mid previous  
LBA high current  
LBA high previous  
Device  
Features (exp)  
Sector count  
Sector count (exp)  
LBA low  
Sector count HOB=0  
Sector count HOB=1  
LBA low HOB=0  
LBA low HOB=1  
LBA mid HOB=0  
LBA mid HOB=1  
LBA mid HOB=0  
LBA mid HOB=1  
Device  
LBA low (exp)  
LBA mid  
LBA mid (exp)  
LBA high  
LBA high (exp)  
Device  
Command  
Control  
Command  
N/A  
Device Control  
N/A  
N/A  
Status  
Status  
Error  
N/A  
Error  
Table 24 Register naming convention and correspondence  
11.2 Command register  
This register contains the command code being sent to the device. Command execution begins  
immediately after this register is written. The command set is shown in “Table 40 Command set” on  
page 75.  
All other registers required for the command must be set up before writing the Command Register.  
11.3 Device Control Register  
Device Control Register  
7
-
6
-
5
-
4
-
3
1
2
1
0
0
SRST  
-IEN  
Table 25 Device Control Register  
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5K320 SATA OEM Specification  
Bit Definitions  
SRST (RST)  
Software Reset. The device is held reset when RST=1. Setting RST=0 reenables the device.  
The host must set RST=1 and wait for at least 5 microseconds before setting RST=0, to  
ensure that the device recognizes the reset.  
-IEN  
Interrupt Enable. When IEN=0, and the device is selected, device interrupts to the host will  
be enabled. When IEN=1, or the device is not selected, device interrupts to the host will be  
disabled.  
11.4 Device Register  
Device Register  
7
-
6
L
5
-
4
0
3
2
1
0
HS3  
HS2  
HS1  
HS0  
Table 26 Device Register  
This register contains the device and head numbers.  
Bit Definitions  
L
Binary encoded address mode select. When L=0, addressing is by CHS mode. When L=1,  
addressing is by LBA mode.  
HS3,HS2,HS1,HS0 The HS3 through HS0 contain bits 24-27 of the LBA. At command completion, these bits are  
updated to reflect the current LBA bits 24-27.  
11.5 Error Register  
Error Register  
7
6
5
0
4
3
0
2
1
0
CRC  
UNC  
IDNF  
ABRT  
TK0NF  
AMNF  
Table 27 Error Register  
This register contains status from the last command executed by the device, or a diagnostic code.  
At the completion of any command except Execute Device Diagnostic, the contents of this register  
are valid always even if ERR=0 in the Status Register.  
Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register  
contains a diagnostic code. See “Table 31 Diagnostic Codes” on Page 52 for the definition.  
Bit Definitions  
ICRCE (CRC)  
Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus during a  
Ultra-DMA transfer.  
UNC  
Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been  
encountered.  
IDNF (IDN)  
ABRT (ABT)  
ID Not Found. IDN=1 indicates the requested sector’s ID field could not be found.  
Aborted Command. ABT=1 indicates the requested command has been aborted due to a  
device status error or an invalid parameter in an output register.  
Track 0 Not Found. T0N=1 indicates track 0 was not found during a Recalibrate command.  
Address Mark Not Found. AMN=1 indicates the data address mark has not been found after  
finding the correct ID field for the requested sector.  
TK0NF (T0N)  
AMNF (AMN)  
This bit is obsolete.  
11.6 Features Register  
This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function  
Set command and Format Unit command.  
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5K320 SATA OEM Specification  
11.7 LBA High Register  
This register contains Bits 16-23. At the end of the command, this register is updated to reflect the  
current LBA Bits 16-23.  
When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits  
16-23, and the “previous content” contains Bits 40-47. The 48-bit Address feature set is described in  
“12.14 48-bit Address Feature Set”.  
11.8 LBA Low Register  
This register contains Bits 0-7. At the end of the command, this register is updated to reflect the  
current LBA Bits 0-7.  
When 48-bit commands are used, the “most recently written” content contains LBA Bits 0-7, and the  
“previous content” contains Bits 24-31.  
11.9 LBA Mid Register  
This register contains Bits 8-15. At the end of the command, this register is updated to reflect the  
current LBA Bits 8-15.  
When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits  
8-15, and the “previous content” contains Bits 32-39.  
11.10 Sector Count Register  
This register contains the number of sectors of data requested to be transferred on a read or write  
operation between the host and the device. If the value in the register is set to 0, a count of 256  
sectors (in 28-bit addressing) or 65,536 sectors (in 48-bit addressing) is specified.  
If the register is zero at command completion, the command was successful. If not successfully  
completed, the register contains the number of sectors which need to be transferred in order to  
complete the request.  
The contents of the register are defined otherwise on some commands. These definitions are given in  
the command descriptions.  
11.11 Status Register  
Status Register  
7
6
5
4
3
2
1
0
BSY  
DRDY  
DF  
DSC  
DRQ  
CORR  
IDX  
ERR  
Table 28 Status Register  
This register contains the device status. The contents of this register are updated whenever an error  
occurs and at the completion of each command.  
If the host reads this register when an interrupt is pending, it is considered to be the interrupt  
acknowledge. Any pending interrupt is cleared whenever this register is read.  
If BSY=1, no other bits in the register are valid.  
Bit Definitions  
BSY  
Busy. BSY=1 whenever the device is accessing the registers. The host should not read or  
write any registers when BSY=1. If the host reads any register when BSY=1, the contents of  
the Status Register will be returned.  
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5K320 SATA OEM Specification  
DRDY (RDY)  
Device Ready. RDY=1 indicates that the device is capable of responding to a command.  
RDY will be set to 0 during power on until the device is ready to accept a command.  
Device Fault. DF=1 indicates that the device has detected a write fault condition. DF is set to  
0 after the Status Register is read by the host.  
DF  
DSC  
Device Seek Complete. DSC=1 indicates that a seek has completed and the device head is  
settled over a track. DSC is set to 0 by the device just before a seek begins. When an error  
occurs, this bit is not changed until the Status Register is read by the host, at which time the  
bit again indicates the current seek complete status.  
When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in  
spite of not spinning up.  
DRQ  
Data Request. DRQ=1 indicates that the device is ready to transfer a word or byte of data  
between the host and the device. The host should not write the Command register when  
DRQ=1.  
CORR (COR)  
IDX  
Corrected Data. Always 0.  
Index. Always 0  
ERR  
ERR=1 indicates that an error occurred during execution of the previous command. The  
Error Register should be read to determine the error type. The device sets ERR=0 when the  
next command is received from the host.  
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5K320 SATA OEM Specification  
12 General Operation Descriptions  
12.1 Reset Response  
There are three types of reset in ATA as follows:  
Power On Reset (POR)  
COMRESET  
The device executes a series of electrical circuitry diagnostics, spins up the HDA,  
tests speed and other mechanical parametric, and sets default values.  
COMRESET is issued in Serial ATA bus.  
The device resets the interface circuitry as well as Soft Reset.  
SRST bit in the Device Control Register is set, then is reset.  
The device resets the interface circuitry according to the Set Features requirement.  
Soft Reset (Software Reset)  
The actions of each reset are shown in “Table 29 Reset Response Table” on Page 51  
POR  
COMRESET  
Soft Reset  
Aborting Host interface  
Aborting Device operation  
Initialization of hardware  
Internal diagnostic  
-
-
o
(*1)  
x
o
(*1)  
x
O
O
x
x
Starting spindle motor  
Initialization of registers (*2)  
Reverting programmed parameters to default  
- Number of CHS (set by Initialize Device Parameter)  
- Multiple mode  
(*5)  
O
x
x
o
o
O
(*6)  
(*3)  
- Write cache  
- Read look-ahead  
- ECC bytes  
- Volatile max address  
Power mode  
(*5)  
o
(*4)  
o
(*4)  
x
Reset Standby timer value  
O ---- execute  
X ---- not execute  
Note.  
(*1) Execute after the data in write cache has been written.  
(*2) Default value on POR is shown in “Table 30 Default Register Values” on Page 52.  
(*3) The Set Features command with Feature register = CCh enables the device to  
revert these parameters to the power on defaults.  
(*4) In the case of sleep mode, the device goes to standby mode. In other case,  
the device does not change current mode.  
(*5) According to the initial power mode selection.  
(*6) See 12.15 Software Setting Preservation Feature Set.  
Table 29 Reset Response Table  
12.1.1 Register Initialization  
After power on, COMRESET, or software reset, the register values are initialized as shown in the following table.  
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5K320 SATA OEM Specification  
Register  
Default Value  
Error  
Diagnostic Code  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
01h  
01h  
00h  
00h  
00h  
50h  
50h  
Status  
Alternate Status  
Table 30 Default Register Values  
The meaning of the Error Register diagnostic codes resulting from power on, COMRESET or the  
Execute Device Diagnostic command are shown in the following table.  
Code  
Description  
01h  
No error Detected  
02h  
Formatter device error  
Sector buffer error  
03h  
04h  
05h  
Ecc circuitry error  
Controller microprocessor error  
Table 31 Diagnostic Codes  
12.2 Diagnostic and Reset considerations  
The Set Max password, the Set Max security mode and the Set Max unlock counter don’t retain over  
a Power On Reset but persist over a COMRESET or Soft Reset.  
For each Reset and Execute Device Diagnostic, the Diagnostic is done as follows:  
Execute Device Diagnostic  
In all the above cases: Power on, COMRESET, Soft reset, and the EXECUTE DEVICE  
DIAGNOSTIC command the Error register is shown in the following table.  
Device 0 Passed  
Error Register  
01h  
0xh  
Yes  
No  
Where x indicates the appropriate Diagnostic Code for the Power on, COMRESET, Soft reset, or Device  
Diagnostic error.  
Table 32 Reset error register values  
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5K320 SATA OEM Specification  
12.3 Power-off considerations  
12.3.1 Load/Unload  
Load/Unload is a functional mechanism of the HDD. It is controlled by the drive microcode.  
Specifically, unloading of the heads is invoked by the commands:  
Command  
Standby  
Response  
UL -> Comp.  
UL -> Comp.  
UL -> Comp.  
Standby immediate  
Sleep  
“UL” means “unload”.  
“Comp” means “complete”.  
Table 33 Device’s behavior by ATA commands  
Load/unload is also invoked as one of the idle modes of the drive.  
The specified start/stop life of the product assumes that load/unload is operated normally, NOT in  
emergency mode.  
12.3.2 Emergency unload  
When HDD power is interrupted while the heads are still loaded, the microcode cannot operate and  
the normal 5V power is unavailable to unload the heads. In this case, normal unload is not possible,  
so the heads are unloaded by routing the back-EMF of the spinning motor to the voice coil. The  
actuator velocity is greater than the normal case, and the unload process is inherently less  
controllable without a normal seek current profile.  
Emergency unload is intended to be invoked in rare situations. Because this operation is inherently  
uncontrolled, it is more mechanically stressful than a normal unload.  
A single emergency unload operation is more stressful than 100 normal unloads. Use of emergency  
unload reduces the start/stop life of the HDD at a rate at least 100X faster than that of normal  
unload, and may damage the HDD.  
12.3.3 Required power-off sequence  
Problems can occur on most HDDs when power is removed at an arbitrary time. Examples:  
Data loss from the write buffer.  
If the drive is writing a sector, a partially-written sector with an incorrect ECC block results. The sector  
contents are destroyed and reading that sector results in a hard error.  
Heads possibly land in the data zone instead of landing zone, depending on the design of the HDD.  
You may then turn off the HDD in the following order:  
1. Issue Standby Immediate or sleep command.  
2. Wait until COMMAND COMPLETE STATUS is returned. (It may take up to 350 ms in typical case)  
3. Terminate power to HDD.  
This power-down sequence should be followed for entry into any system power-down state, or system  
suspend state, or system hibernation state. In a robustly designed system, emergency unload is  
limited to rare scenarios such as battery removal during operation.  
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5K320 SATA OEM Specification  
12.4 Sector Addressing Mode  
All addressing of data sectors recorded on the device’s media is by a logical sector address. The  
logical CHS address for HTS5432XXL9SA00 / HTS5432XXL9A300 is different from the actual  
physical CHS location of the data sector on the disk media.  
HTS5432XXL9SA00 / HTS5432XXL9A300 support both Logical CHS Addressing Mode and LBA  
Addressing Mode as the sector addressing mode.  
The host system may select either the currently selected CHS translation addressing or LBA  
addressing on a command-by-command basis by using the L bit in the DEVICE register. So a host  
system must set the L bit to 1 if the host uses LBA Addressing mode.  
12.4.1 Logical CHS Addressing Mode  
The logical CHS addressing is made up of three fields: the cylinder number, the head number and  
the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS  
translation mode but can not exceed 255(0FFh). Heads are numbered from 0 to the maximum value  
allowed by the current CHS translation mode but can not exceed 15(0Fh). Cylinders are numbered  
from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed  
65535(0FFFFh).  
When the host selects a CHS translation mode using the INITIALIZE DEVICE PARAMETERS  
command, the host requests the number of sectors per logical track and the number of heads per  
logical cylinder. The device then computes the number of logical cylinders available in requested  
mode.  
The default CHS translation mode is described in the Identify Device Information. The current CHS  
translation mode also is described in the Identify Device Information.  
12.4.2 LBA Addressing Mode  
Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0)  
being the same sector as the first logical CHS addressed sector ( cylinder 0, head 0, sector 1).  
Irrespective of the logical CHS translation mode currently in effect, the LBA address of a given  
logical sector does not change. The following is always true:  
LBA = ( (cylinder * heads_per_cylinder + heads)  
* sectors_per_track ) + sector - 1  
where heads_per_cylinder and sectors_per_track are the current translation mode values.  
On LBA addressing mode, the LBA value is set to the following register.  
Device <--- LBA bits 27-24  
LBA High <--- LBA bits 23-16  
LBA Mid <--- LBA bits 15- 8  
LBA Low <--- LBA bits 7- 0  
12.5 Power Management Feature  
The power management feature set permits a host to modify the behavior in a manner which  
reduces the power required to operate. The power management feature set provides a set of  
commands and a timer that enables a device to implement low power consumption modes.  
HTS5432XXL9SA00 / HTS5432XXL9A300 implement the following set of functions.  
1. A Standby timer  
2. Idle command  
3. Idle Immediate command  
4. Sleep command  
5. Standby command  
6. Standby Immediate command  
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5K320 SATA OEM Specification  
12.5.1 Power Mode  
Sleep Mode  
The lowest power consumption when the device is powered on occurs in Sleep Mode.  
When in sleep mode, the device requires a reset to be activated.  
The device interface is capable of accepting commands, but as the media may not  
immediately accessible, there is a delay while waiting for the spindle to reach  
operating speed.  
Standby Mode  
Idle Mode  
Active Mode  
Refer to the section of Adaptive Battery Life Extender Feature.  
The device is in execution of a command or accessing the disk media with read  
look-ahead function or write cache function.  
12.5.2 Power Management Commands  
The Check Power Mode command allows a host to determine if a device is currently in, going to or  
leaving standby mode.  
The Idle and Idle Immediate commands move a device to idle mode immediately from the active or  
standby modes. The idle command also sets the standby timer count and starts the standby timer.  
The sleep command moves a device to sleep mode. The device’s interface becomes inactive at the  
completion of the sleep command. A reset is required to move a device out of sleep mode. When a  
device exits sleep mode it will enter standby mode.  
The Standby and Standby Immediate commands move a device to standby mode immediately from  
the active or idle modes. The standby command also sets the standby timer count.  
12.5.3 Standby/Sleep command completion timing  
1. Confirm the completion of writing cached data in the buffer to media  
2. Unload heads on the ramp  
3. Set DRDY bit and DSC bit in Status Register  
4. Activate the spindle break to stop the spindle motor  
5. Wait until spindle motor is stopped  
6. Perform post process  
12.5.4 Status  
In the active, idle and standby modes, the device shall have RDY bit of the status register set. If BSY  
bit is not set, device shall be ready to accept any command.  
In sleep mode, the device’s interface is not active. A host shall not attempt to read the device’s status  
or issue commands to the device.  
12.5.5 Interface Capability for Power Modes  
Each power mode affects the physical interface as defined in the following table:  
Mode  
BSY  
RDY  
Interface active  
Media  
Active  
Active  
Idle  
x
0
0
x
x
1
1
x
Yes  
Yes  
Yes  
No  
Active  
Standby  
Sleep  
Inactive  
Inactive  
Table 34 Power conditions  
Ready(RDY) is not a power condition. A device may post ready at the interface even though the  
media may not be accessible.  
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5K320 SATA OEM Specification  
12.5.6 Initial Power Mode at Power On  
After power on the device goes to IDLE mode or STANDBY mode depending on the setting of the  
Power Up in Standby Feature set  
12.6 Advanced Power Management (Adaptive  
Battery Life Extender 3) Feature  
This feature provides power saving without performance degradation. The Adaptive Battery Life  
Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the  
device by monitoring access patterns of the host.  
This technology has three idle modes; Performance Idle mode, Active Idle mode, and Low Power Idle  
mode.  
This feature allows the host to select an advanced power management level. The advanced power  
management level is a scale from the lowest power consumption setting of 01h to the maximum  
performance level of FEh. Device performance may increase with increasing advanced power  
management levels. Device power consumption may increase with increasing advanced power  
management levels. The advanced power management levels contain discrete bands, described in the  
section of Set Feature command in detail.  
This feature set uses the following functions:  
A SET FEATURES subcommand to enable Advanced Power Management  
A SET FEATURES subcommand to disable Advanced Power Management  
The Advanced Power Management feature is independent of the Standby timer setting. If both  
Advanced Power Management level and the Standby timer are set, the device will go to the Standby  
state when the timer times out or the device’s Advanced Power Management algorithm indicates  
that it is time to enter the Standby state.  
The IDENTIFY DEVICE response word 83, bit 3 indicates that Advanced Power Management  
feature is supported if set. Word 86, bit 3 indicates that Advanced Power Management is enabled if  
set.  
Word 91, bits 7-0 contain the current Advanced Power Management level if Advanced Power  
Management is enabled.  
12.6.1 Performance Idle mode  
This mode is usually entered immediately after Active mode command processing is complete,  
instead of conventional idle mode. In Performance Idle mode, all electronic components remain  
powered and full frequency servo remains operational. This provides instantaneous response to the  
next command. The duration of this mode is intelligently managed as described below.  
12.6.2 Active Idle mode  
In this mode, power consumption is 45-55% less than that of Performance Idle mode. Additional  
electronics are powered off, and the head is parked near the mid-diameter of the disk without  
servoing. Recovery time to Active mode is about 20ms.  
12.6.3 Low Power Idle mode  
Power consumption is 60%-65% less than that of Performance Idle mode. The heads are unloaded on  
the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about  
300ms.  
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5K320 SATA OEM Specification  
12.6.4 Transition Time  
The transition time is dynamically managed by users recent access pattern, instead of fixed times.  
The ABLE-3 algorithm monitors the interval between commands instead of the command frequency  
of ABLE-2. The algorithm supposes that next command will come with the same command interval  
distribution as the previous access pattern. The algorithm calculates the expected average saving  
energy and response delay for next command in several transition time case based on this  
assumption. And it selects the most effective transition time with the condition that the calculated  
response delay is shorter than the value calculated from the specified level by Set Feature Enable  
Advanced Power Management command.  
The optimal time to enter Active Idle mode is variable depending on the users recent behavior. It is  
not possible to achieve the same level of Power savings with a fixed entry time into Active Idle  
because every users data and access pattern is different. The optimum entry time changes over time.  
The same algorithm works for entering into Low Power Idle mode and Standby mode, which  
consumes less power but need more recovery time switching from this mode to Active mode.  
12.7 Interface Power Management Mode  
(Slumber and Partial)  
Interface Power Management Mode is supported by both Device-initiated interface power  
management and Host-initiated interface power management. Please refer to the Serial ATA  
Specification about Power Management Mode.  
12.8 S.M.A.R.T. Function  
The intent of Self-monitoring, analysis and reporting technology (S.M.A.R.T) is to protect user data  
and prevent unscheduled system downtime that may be caused by predictable degradation and/or  
fault of the device. By monitoring and storing critical performance and calibration parameters,  
S.M.A.R.T devices employ sophisticated data analysis algorithms to predict the likelihood of  
near-term degradation or fault condition. By alerting the host system of a negative reliability status  
condition, the host system can warn the user of the impending risk of a data loss and advise the user  
of appropriate action.  
Since S.M.A.R.T. utilizes the internal device microprocessor and other device resources, there may  
be some small overhead associated with its operation. However, special care has been taken in the  
design of the S.M.A.R.T. algorithms to minimize the impact to host system performance. Actual  
impact of S.M.A.R.T. overhead is dependent on the specific device design and the usage patterns of  
the host system. To further ensure minimal impact to the user, S.M.A.R.T. capable devices are  
shipped from the device manufacturer’s factory with the S.M.A.R.T. feature disabled. S.M.A.R.T.  
capable devices can be enabled by the system OEMs at time of system integration or in the field by  
aftermarket products.  
12.8.1 Attributes  
Attributes are the specific performance or calibration parameters that are used in analyzing the  
status of the device. Attributes are selected by the device manufacturer based on that attribute’s  
ability to contribute to the prediction of degrading or faulty conditions for that particular device. The  
specific set of attributes being used and the identity of these attributes is vendor specific and  
proprietary.  
12.8.2 Attribute values  
Attribute values are used to represent the relative reliability of individual performance or  
calibration attributes. Higher attribute values indicate that the analysis algorithms being used by  
- 57 -  
   
5K320 SATA OEM Specification  
the device are predicting a lower probability of a degrading or fault condition existing. Accordingly,  
lower attribute values indicate that the analysis algorithms being used by the device are predicting a  
higher probability of a degrading or fault condition existing. There is no implied linear reliability  
relationship corresponding to the numerical relationship between different attribute values for any  
particular attribute.  
12.8.3 Attribute thresholds  
Each attribute value has a corresponding attribute threshold limit which is used for direct  
comparison to the attribute value to indicate the existence of a degrading or faulty condition. The  
numerical value of the attribute thresholds are determined by the device manufacturer through  
design and reliability testing and analysis. Each attribute threshold represents the lowest limit to  
which its corresponding attribute value can be equal while still retaining a positive reliability status.  
Attribute thresholds are set at the device manufacturer’s factory and cannot be changed in the field.  
The valid range for attribute thresholds is from 1 through 253 decimal.  
12.8.4 Threshold exceeded condition  
If one or more attribute values are less than or equal to their corresponding attribute thresholds,  
then the device reliability status is negative, indicating an impending degrading or faulty condition.  
12.8.5 S.M.A.R.T. commands  
The S.M.A.R.T. commands provide access to attribute values, attribute thresholds and other logging  
and reporting information.  
12.8.6 S.M.A.R.T operation with power management modes  
The device saves attribute values automatically on every head unload timing except the emergency  
unload, even if the attribute auto save feature is not enabled. The head unload is done not only by  
Standby, Standby Immediate, or Sleep command, but also by the automatic power saving functions  
like ABLE-3 or Standby timer. So basically it is not necessary for a host system to enable the  
attribute auto save feature, when it utilizes the power management. If the attribute auto save  
feature is enabled, attribute values will be saved after 30minutes passed since the last saving,  
besides above condition.  
12.9 Security Mode Feature Set  
Security Mode Feature Set is a powerful security feature. With a device lock password, a user can  
prevent unauthorized access to hard disk device even if the device is removed from the computer.  
New commands are supported for this feature as below.  
Security Set Password  
Security Unlock  
Security Erase Prepare  
Security Erase Unit  
Security Freeze Lock  
Security Disable Password  
(‘F1’h)  
(‘F2’h)  
(‘F3’h)  
(‘F4’h)  
(‘F5’h)  
(‘F6’h)  
12.9.1 Security mode  
Following security modes are provided.  
Device Locked mode  
The device disables media access commands after power on. Media access  
commands are enabled by either a security unlock command or a security  
erase unit command.  
Device Unlocked mode  
The device enables all commands. If a password is not set this mode is  
- 58 -  
 
5K320 SATA OEM Specification  
entered after power on, otherwise it is entered by a security unlock or a  
security erase unit command.  
Device Frozen mode  
The device enables all commands except those which can update the device  
lock function, set/change password. The device enters this mode via a  
Security Freeze Lock command. It cannot quit this mode until power off.  
12.9.2 Security Level  
Following security levels are provided.  
High level security  
When the device lock function is enabled and the User Password is  
forgotten the device can be unlocked via a Master Password.  
When the device lock function is enabled and the User Password is  
forgotten then only the Master Password with a Security Erase Unit  
command can unlock the device. Then user data is erased.  
Maximum level security  
12.9.3 Password  
This function can have 2 types of passwords as described below.  
Master Password  
When the Master Password is set, the device does NOT enable the Device  
Lock Function, and the device can NOT be locked with the Master  
Password, but the Master Password can be used for unlocking the device  
locked.  
User Password  
The User Password should be given or changed by a system user. When the  
User Password is set, the device enables the Device Lock Function, and  
then the device is locked on next power on reset. If Software Setting  
Preservation is disabled, the device is locked on COMRESET as well.  
The system manufacturer/dealer who intends to enable the device lock function for the end users,  
must set the master password even if only single level password protection is required. Otherwise, if  
the User Password is forgotten then no one can unlock the device which is locked with the User  
Password.  
12.9.4 Master Password Revision Code  
This Master Password Revision Code is set by Security Set Password command with the master  
password. And this revision code field is returned in the Identify Device command word 92. The valid  
revision codes are 0001h to FFFEh. The default value of Master Password Revision Code is FFFEh.  
Value 0000h and FFFFh is reserved.  
12.9.5 Operation example  
12.9.5.1 Master Password setting  
The system manufacturer/dealer can set a initial Master Password using the Security Set Password  
command, without enabling the Device Lock Function.  
12.9.5.2 User Password setting  
When a User Password is set, the device will automatically enter lock mode the next time the device  
is powered on.  
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5K320 SATA OEM Specification  
Figure 5 Initial Setting  
Operation from POR after User Password is set  
When Device Lock Function is enabled, the device rejects media access command until a Security  
Unlock command is successfully completed.  
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5K320 SATA OEM Specification  
(*1) refer to Table 35 Command table for device lock operation on Page 63 and Table 36 Command table for  
device lock operation - continued on Page 64.  
Figure 6 Usual Operation  
User Password Lost  
If the User Password is forgotten and High level security is set, the system user can’t access any  
data. However the device can be unlocked using the Master Password.  
If a system user forgets the User Password and Maximum security level is set, data access is  
impossible. However the device can be unlocked using the Security Erase Unit command to unlock  
the device and erase all user data with the Master Password.  
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5K320 SATA OEM Specification  
Figure 7 Password Lost  
Attempt limit for SECURITY UNLOCK command  
The SECURITY UNLOCK command has an attempt limit. The purpose of this attempt limit is to  
prevent that someone attempts to unlock the drive by using various passwords many times.  
The device counts the password mismatch. If the password does not match, the device counts it up  
without distinguishing the Master password and the User password. If the count reaches 5, EXPIRE  
bit(bit 4) of Word 128 in Identify Device information is set, and then SECURITY ERASE UNIT  
command and SECURITY UNLOCK command are aborted until a power off. The count and EXPIRE  
bit are cleared after a power on reset.  
12.9.6 Command Table  
This table shows the device’s response to commands when the Security Mode Feature Set (Device  
lock function) is enabled.  
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5K320 SATA OEM Specification  
Command  
Device Device Device  
Locked Unlock Frozen  
Mode  
o
x
o
x
x
x
o
x
x
x
x
o
o
o
o
o
o
x
x
x
o
x
x
o
o
x
x
x
x
o
x
o
o
x
x
o
o
o
o
Mode  
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Mode  
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
x
o
x
o
x
x
o
o
o
Check Power Mode  
Device Configuration RESTORE  
Device Configuration FREEZE LOCK  
Device Configuration IDENTIFY  
Device Configuration SET  
Download Microcode  
Execute Device Diagnostic  
Flush Cache  
Flush Cache Ext  
Format Track  
Format Unit  
Identify Device  
Idle  
Idle Immediate  
Idle Immediate with Unload option  
Initialize Device Parameters  
Read Buffer  
Read DMA  
Read DMA Ext  
Read FPDMA Queued  
Read Log Ext  
Read Multiple  
Read Multiple Ext  
Read Native Max Address  
Read Native Max Address Ext  
Read Sector(s)  
Read Sector(s) Ext  
Read Verify Sector(s)  
Read Verify Sector(s) Ext  
Recalibrate  
Security Disable Password  
Security Erase Prepare  
Security Erase Unit  
Security Freeze Lock  
Security Set Password  
Security Unlock  
Seek  
Sense Condition  
Set Features  
Table 35 Command table for device lock operation  
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5K320 SATA OEM Specification  
Command  
Device Device Device  
Locked Unlock Frozen  
Mode  
Mode  
Mode  
Set Max Address  
Set Max Address Ext  
Set Max Freeze Lock  
Set Max Lock  
x
o
o
x
o
o
o
o
o
o
o
o
Set Max Set Password  
Set Max Unlock  
o
o
o
o
o
o
Set Multiple Mode  
Sleep  
o
o
o
o
o
o
S.M.A.R.T. Disable Operations  
o
o
o
S.M.A.R.T. Enable/Disable Automatic Offline  
S.M.A.R.T. Enable/Disable Attribute Autosave  
S.M.A.R.T. Enable Operations  
S.M.A.R.T. Execute Off-line Immediate  
S.M.A.R.T. Read Attribute Values  
S.M.A.R.T. Read Attribute Thresholds  
S.M.A.R.T. Read Log Sector  
S.M.A.R.T. Write Log Sector  
S.M.A.R.T. Return Status  
S.M.A.R.T. Save Attribute Values  
Standby  
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Standby Immediate  
o
o
o
Write Buffer  
o
o
o
Write DMA  
x
o
o
Write DMA Ext  
x
o
o
Write DMA FUA Ext  
x
o
o
Write FPDMA Queued  
x
o
o
Write Log Ext  
x
o
o
Write Multiple  
x
o
o
Write Multiple Ext  
x
o
o
Write Multiple FUA Ext  
Write Sector(s)  
x
o
o
x
o
o
Write Sector(s) Ext  
x
o
o
Write Uncorrectable Ext  
Table 36 Command table for device lock operation - continued  
x
o
o
12.10 Protected Area Function  
Protected Area Function is to provide the ‘protected area’ which can not be accessed via conventional  
method. This ‘protected area’ is used to contain critical system data such as BIOS or system  
management information. The contents of entire system main memory may also be dumped into  
‘protected area’ to resume after system power off.  
The LBA/CYL changed by following command affects the Identify Device Information.  
Two commands are defined for this function.  
Read Native Max Address  
Set Max Address  
(‘F8’h)  
(‘F9’h)  
Four security extension commands are implemented as sub-functions of the Set Max Address.  
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5K320 SATA OEM Specification  
Set Max Set Password  
Set Max Lock  
Set Max Freeze Lock  
Set Max Unlock  
12.10.1 Example for operation (In LBA mode)  
Assumptions :  
For better understanding, the following example uses actual values for LBA, size, etc. Since it is just  
an example, these values could be different.  
Device characteristics  
Capacity (native)  
Max LBA (native)  
:
:
:
:
:
:
536,870,912 byte (536MB)  
1,048,575 (0FFFFFh)  
8,388,608 byte  
16,384 (004000h)  
528,482,304 byte (528MB)  
1,032,192 (0FC000h)  
Required size for protected area  
Required blocks for protected area  
Customer usable device size  
Customer usable sector count  
LBA range for protected area  
Shipping HDDs from HDD manufacturer  
: 0FC000h to 0FFFFFh  
When the HDDs are shipped from HDD manufacturer, the device has been tested to have a  
capacity of 536MB,flagging the media defects not to be visible by system.  
1. Preparing HDDs at system manufacturer  
Special utility software is required to define the size of protected area and store the data into it.  
The sequence is :  
Issue Read Native Max Address command to get the real device max of LBA/CYL. Returned value shows  
that native device Max LBA is 0FFFFFh regardless to the current setting.  
Make entire device be accessible including the protected area by setting device Max LBA as 0FFFFFh via  
Set Max Address command. The option could be either nonvolatile or volatile.  
Test the sectors for protected area (LBA >= 0FC000h) if required.  
Write information data such as BIOS code within the protected area.  
Change maximum LBA using Set Max Address command to 0FBFFFh with nonvolatile option.  
From this point, the protected area cannot be accessed until next Set Max Address command is issued.  
Any BIOSes, device drivers, or application software access the HDD as if that is the 528MB device  
because the device acts exactly same as real 528MB device does.  
2. Conventional usage without system software support  
Since the HDD works as 528MB device, there is no special care to use this device for normal use.  
3. Advanced usage using protected area  
The data in the protected area is accessed by following.  
Issue Read Native Max Address command to get the real device max LBA/CYL. Returned value  
shows that native device Max LBA is 0FFFFFh regardless of the current setting.  
Make entire device be accessible including the protected area by setting device Max LBA as  
0FFFFFh via Set Max Address command with volatile option. By using this option, unexpected  
power removal or reset will not make the protected area remained accessible.  
Read information data from protected area.  
Issue POR to inhibit any access to the protected area.  
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5K320 SATA OEM Specification  
12.10.2 Set Max security extension commands  
The Set Max Set Password command allows the host to define the password to be used during the  
current power on cycle. This password is not related to the password used for the Security Mode  
Feature set. When the password is set the device is in the Set Max Unlocked mode.  
This command requests a transfer of a single sector of data from the host. The table shown below  
defines the content of this sector of information. The password is retained by the device until the  
next power cycle. When the device accepts this command the device is in Set Max Unlocked mode.  
Word  
Content  
Reserved  
0
1-16  
Password (32 bytes)  
Reserved  
17-255  
Table 37 Set Max Set Password data content  
The Set Max Lock command allows the host to disable the Set Max commands (except Set Max  
Unlock and Set Max Freeze Lock) until the next power cycle or the issuance and acceptance of the  
Set Max Unlock command. When this command is accepted the device is in the Set Max Locked  
mode.  
The Set Max Unlock command changes the device from the Set Max Locked mode to the Set Max  
Unlocked mode.  
This command requests a transfer of a single sector of data from the host. The Table shown above  
defines the content of this sector of information. The password supplied in the sector of data  
transferred is compared with the stored Set Max password. If the password compare fails, then the  
device returns command aborted and decrements the unlock counter. On the acceptance of the Set  
Max Lock command, this counter is set to a value of five and is decremented for each password  
mismatch when Set Max Unlock is issued and the device is locked. When this counter reaches zero,  
then the Set Max Unlock command returns command aborted until a power cycle.  
The Set Max Freeze Lock command allows the host to disable the SET Max commands (including Set  
Max Unlock) until the next power cycle. When this command is accepted the device is in the Set Max  
Frozen mode.  
The password, the Set Max security mode and the unlock counter don’t persist over a power cycle but  
does persist over a COMRESET or software reset.  
Note that If this command is immediately preceded by a Read Native Max Address command  
regardless of Feature register value, it shall be interpreted as a Set Max Address command.  
Figure 8 Set Max security mode transition  
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5K320 SATA OEM Specification  
12.11 Seek Overlap  
HTS5432XXL9SA00 / HTS5432XXL9A300 provide accurate seek time measurement method. The  
seek command is usually used to measure the device seek time by accumulating execution time for a  
number of seek commands. With typical implementation of the seek command, this measurement  
must including the device and host command overhead. To eliminate this overhead,  
HTS5432XXL9SA00 / HTS5432XXL9A300 overlap the seek command as described below.  
The first seek command completes before the actual seek operation is over. Then device can receive  
the next seek command from the host but actual seek operation for the next seek command starts  
right after the actual seek operation for the first seek command is completed. In other words, the  
execution of two seek commands overlaps excluding the actual seek operation.  
With this overlap, total elapsed time for a number of seek commands is the total accumulated time  
for the actual seek operation plus one pre and post overhead. When the number of seeks is large, just  
this one overhead can be ignored.  
Figure 9 Seek overlap  
12.12 Write Cache Function  
Write cache is a performance enhancement whereby the device reports completion of the write  
command (Write Sector(s) and Write Multiple) to the host as soon as the device has received all of  
the data into its buffer. The device assumes responsibility to write the data subsequently onto the  
disk.  
While writing data after completed acknowledgment of a write command, soft reset or COMRESET does  
not affect its operation. But power off terminates writing operation immediately and unwritten data are to  
be lost.  
Flush cache, Soft reset, Standby, Standby Immediate and Sleep are executed after the completion of  
writing to disk media on enabling write cache function. So the host system can confirm the completion of  
write cache operation by issuing flush cache command, Soft reset, Standby command, Standby Immediate  
command or Sleep command, and then, by confirming its completion.  
12.13 Reassign Function  
The reassign Function is used with read commands and write commands. The sectors of data for  
reassignment are prepared as the spare data sector. The one entry can register 256 consecutive  
sectors maximally.  
This reassignment information is registered internally, and the information is available right after  
completing the reassign function. Also the information is used on the next power on reset.  
If the number of the spare sector reaches 0 sector, the reassign function will be disabled  
automatically.  
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5K320 SATA OEM Specification  
The spare tracks for reassignment are located at regular intervals from Cylinder 0. As a result of  
reassignment, the physical location of logically sequenced sectors will be dispersed.  
12.13.1 Auto Reassign Function  
The sectors that show some errors may be reallocated automatically when specific conditions are met.  
The spare tracks for reallocation are located at regular intervals from Cylinder 0. The conditions for  
auto-reallocation are described below.  
Non recovered write errors  
When a write operation can not be completed after the Error Recovery Procedure(ERP) is fully  
carried out, the sector(s) are reallocated to the spare location. An error is reported to the host system  
only when the write cache is disabled and the auto reallocation fails.  
If the number of available spare sectors reaches 16 sectors, the write cache function will be disabled  
automatically.  
Non recovered read errors  
When a read operation fails after defined ERP is fully carried out, a hard error is reported to the  
host system. This location is registered internally as a candidate for the reallocation. When a  
registered location is specified as a target of a write operation, a sequence of media verification is  
performed automatically. When the result of this verification meets the criteria, this sector is  
reallocated.  
Recovered read errors  
When a read operation for a sector failed once then recovered at the specific ERP step, this sector of  
data is reallocated automatically. A media verification sequence may be run prior to the relocation  
according to the pre-defined conditions.  
12.14 48-bit Address Feature Set  
The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This  
allows device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that  
may be transferred by a single command are increased by increasing the allowable sector count to 16  
bits.  
Commands unique to the 48-bit Address feature set are:  
Flush Cache Ext  
Read DMA Ext  
Read Multiple Ext  
Read Native Max Address Ext  
Read Sector(s) Ext  
Read Verify Sector(s) Ext  
Set Max Address Ext  
Write DMA Ext  
Write Multiple Ext  
Write Sector(s) Ext  
The 48-bit Address feature set operates in LBA addressing only. Devices also implement commands  
using 28-bit addressing, and 28-bit and 48-bit commands may be intermixed.  
Support of the 48-bit Address feature set is indicated in the Identify Device response bit 10 word 83.  
In addition, the maximum user LBA address accessible by 48-bit addressable commands is contained  
in Identify Device response words 100 through 103.  
When the 48-bit Address feature set is implemented, the native maximum address is the value  
returned by a Read Native Max Address Ext command. If the native maximum address is equal to or  
less than 268,435,455, a Read Native Max Address shall return the native maximum address. If the  
native maximum address is greater than 268,435,455, a Read Native Max Address shall return a  
value of 268,435,455.  
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5K320 SATA OEM Specification  
12.15 Software Setting Preservation Feature Set  
When a device is enumerated, software will configure the device using Set Features and other  
commands. These software settings are often preserved across software reset but not necessarily  
across hardware reset. In Parallel ATA, only commanded hardware resets can occur, thus legacy  
software only reprograms settings that are cleared for the particular type of reset it has issued. In  
Serial ATA, COMRESET is equivalent to hard reset and a non-commanded COMRESET may occur  
if there is an asynchronous loss of signal. Since COMRESET is equivalent to hardware reset, in the  
case of an asynchronous loss of signal some software settings may be lost without legacy software  
knowledge. In order to avoid losing important software settings without legacy driver knowledge,  
the software settings preservation ensures that the value of important software settings is  
maintained across a COMRESET. Software settings preservation may be enabled or disabled using  
Set Features with a subcommand code of 06h. Software settings preservation is enabled by default.  
12.15.1 Preserved software settings  
If Software setting preservation is enabled, the following settings are preserved across COMRESET.  
Otherwise settings are cleared across COMRESET.  
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5K320 SATA OEM Specification  
Setting  
Contents  
Initialize device parameters  
Track length  
Number of head  
Number of cylinder  
Capacity  
Power Management Feature Set Standby  
Timer  
Time to fall into standby mode  
Security mode state  
Security freeze lock  
Security unlock  
Set max address  
Set feature  
Capacity  
Write Cache Enable/Disable  
Set Transfer Mode  
Advanced Power Management  
Enable/Disable  
Read Look-Ahead  
Reverting to Defaults  
Block size  
Set multiple mode  
Table 38 Preserved Software Setting  
12.16 Native Command Queuing  
Native Command Queuing feature (Read / Write FPDMA Queued commands) is supported. Please  
refer to the Serial ATA II Specification about Native Command Queuing.  
The host shall not issue a legacy ATA command while a native queued command is outstanding.  
Upon receiving a legacy ATA command while a native queued command is outstanding, the device  
aborts the command and halts command processing of outstanding native queued commands.  
12.17 SMART Command Transport (SCT)  
SMART Command Transport (SCT) feature set is supported. The SMART Read Log and SMART  
Write Log commands or Read Log Ext and Write Log Ext commands are used to issue a command in  
this feature sets. Log page E0h is used to issue commands and return status. Log page E1h is  
used to transport data. Please refer to the section 8 SCT Command Transport in ATA8-ACS  
specification for more detail.  
The following Action codes are supported.  
Action code  
Description  
0002h  
Write Same command  
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5K320 SATA OEM Specification  
0003h  
0004h  
Error Recovery Control command  
Feature Control command  
Feature  
Write Cache  
code 0001h  
Feature  
code 0003h  
Time Interval for temperature  
logging  
0005h  
SCT Data Table command  
Table 39 SCT Action Code Supported  
- 71 -  
 
5K320 SATA OEM Specification  
13 Command Protocol  
The commands are grouped into different classes according to the protocols followed for command  
execution. The command classes with their associated protocols are defined below.  
Please refer to Serial ATA Revision 2.6 (Section 11. device command layer protocol) about each  
protocol.  
For all commands, the host must first check if BSY=1, and should proceed no further unless and  
until BSY=0. For all commands, the host must also wait for RDY=1 before proceeding.  
A device must maintain either BSY=1 or DRQ=1 at all times until the command is completed. The  
INTRQ signal is used by the device to signal most, but not all, times when the BSY bit is changed  
from 1 to 0 during command execution.  
A command shall only be interrupted with a COMRESET or software reset. The result of writing to  
the Command register while BSY=1 or DRQ=1 is unpredictable and may result in data corruption. A  
command should only be interrupted by a reset at times when the host thinks there may be a  
problem, such as a device that is no longer responding.  
Interrupts are cleared when the host reads the Status Register, issues a reset, or writes to the  
Command Register.  
“Table 139 Timeout Values” on Page 175 shows the device timeout values.  
13.1 Data In Commands  
These commands are:  
Device Configuration Identify  
Identify Device  
Read Buffer  
Read Log Ext  
Read Multiple  
Read Multiple Ext  
Read Sector(s)  
Read Sector(s) Ext  
S.M.A.R.T. Read Attribute Values  
S.M.A.R.T. Read Attribute Thresholds  
S.M.A.R.T. Read log sector  
Execution includes the transfer of one or more 512 byte (>512 bytes on Read Long) sectors of data  
from the device to the host.  
Note that the status data for a sector of data is available in the Status Register before the sector is  
transferred to the host.  
If the device detects an invalid parameter, then it will abort the command by setting BSY=0, ERR=1,  
ABT=1.  
If an error occurs, the device will set BSY=0, ERR=1, and DRQ=1. The device will then store the  
error status in the Error Register. The registers will contain the location of the sector in error. The  
erroneous location will be reported with CHS mode or LBA mode, the mode is decided by mode select  
bit (bit 6) of Device register on issuing the command.  
13.2 Data Out Commands  
These commands are:  
Device Configuration Set  
Download Microcode  
Format Track  
Security Disable Password  
Security Erase Unit  
72  
     
5K320 SATA OEM Specification  
Security Set Password  
Security Unlock  
Set Max Set Password  
Set Max Unlock  
S.M.A.R.T Write Log Sector  
Write Buffer  
Write Log Ext  
Write Multiple  
Write Multiple Ext  
Write Sector(s)  
Write Sector(s) Ext  
Execution includes the transfer of one or more 512 byte (>512 bytes on Write Long) sectors of data  
from the host to the device.  
If the device detects an invalid parameter, then it will abort the command by setting BSY=0, ERR=1,  
ABT=1.  
If an uncorrectable error occurs, the device will set BSY=0 and ERR=1, store the error status in the  
Error Register. The registers will contain the location of the sector in error. The errored location will  
be reported with CHS mode or LBA mode. The mode is decided by mode select bit (bit 6) of Device  
register on issuing the command.  
13.3 Non-Data Commands  
These commands are:  
Check Power Mode  
Device Configuration Freeze Lock  
Device Configuration Restore  
Execute Device Diagnostic  
Flush Cache  
Flush Cache Ext  
Format Unit  
Idle  
Idle Immediate  
Idle Immediate with Unload option  
Initialize Device Parameters  
Read Native Max Address  
Read Native Max Address Ext  
Read Verify Sector(s)  
Read Verify Sector(s) Ext  
Recalibrate  
Security Erase Prepare  
Security Freeze Lock  
Seek  
Sense Condition  
Set Features  
Set Max Address  
Set Max Address Ext  
Set Max Lock  
Set Max Freeze Lock  
Set Multiple Mode  
Sleep  
S.M.A.R.T. Disable Operations  
S.M.A.R.T. Enable/Disable Attribute Autosave  
S.M.A.R.T. Enable/Disable Automatic Off-line  
S.M.A.R.T. Enable Operations  
S.M.A.R.T. Execute Off-line Immediate  
S.M.A.R.T. Return Status  
S.M.A.R.T. Save Attribute Values  
Standby  
Standby Immediate  
73  
 
5K320 SATA OEM Specification  
Write Uncorrectable Ext  
Execution of these commands involves no data transfer.  
13.4 DMA Data Transfer Commands  
These commands are:  
Read DMA  
Read DMA Ext  
Write DMA  
Write DMA Ext  
Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands  
except that the host initializes the slave-DMA channel prior to issuing the command.  
The DMA protocol allows high performance multi-tasking operating systems to eliminate processor  
overhead associated with PIO transfers.  
Refer Functional Specification part for further details.  
13.5 First-parity DMA Commands  
These commands are:  
Read FPDMA Queued  
Write FPDMA Queued  
Execution of this class of commands includes command queuing and the transfer of one or more  
blocks of data between the device and the host. The protocol is described in the section 11.14  
“FPDMA Queued command protocol” of “Serial ATA revision 2.6”.  
74  
   
5K320 SATA OEM Specification  
14 Command Descriptions  
Protocol  
Command  
Code  
(Hex) 7 6 5 4 3 2 1 0  
3
3
3
3
1
2
2
3
3
3
2
3+  
1
3
3
3
3
3
3
1
4
4
4
5
1
1
1
3
3
1
1
1
3
3
3
3
2
3
2
3
2
2
3
3
3
Check Power Mode  
E5  
98  
B1  
B1  
B1  
B1  
92  
90  
E7  
EA  
50  
F7  
EC  
E3  
97  
E1  
95  
E1  
91  
E4  
C8  
C9  
25  
60  
2F  
C4  
29  
F8  
27  
20  
21  
24  
40  
41  
42  
1x  
F6  
F3  
F4  
F5  
F1  
F2  
7x  
F0  
EF  
1 1 1 0 0 1 0 1  
1 0 0 1 1 0 0 0  
1 0 1 0 0 0 0 1  
1 0 1 0 0 0 0 1  
1 0 1 0 0 0 0 1  
1 0 1 0 0 0 0 1  
1 0 0 1 0 0 1 0  
1 0 0 1 0 0 0 0  
1 1 1 0 0 1 1 1  
1 1 1 0 1 0 1 0  
0 1 0 1 0 0 0 0  
1 1 1 1 0 1 1 1  
1 1 1 0 1 1 0 0  
1 1 1 0 0 0 1 1  
1 0 0 1 0 1 1 1  
1 1 1 0 0 0 0 1  
1 0 0 1 0 1 0 1  
1 1 1 0 0 0 0 1  
1 0 0 1 0 0 0 1  
1 1 1 0 0 1 0 0  
1 1 0 0 1 0 0 0  
1 1 0 0 1 0 0 1  
0 0 1 0 0 1 0 1  
0 1 1 0 0 0 0 0  
0 0 1 0 1 1 1 1  
1 1 0 0 0 1 0 0  
0 0 1 0 1 0 0 1  
1 1 1 1 1 0 0 0  
0 0 1 0 0 1 1 1  
0 0 1 0 0 0 0 0  
0 0 1 0 0 0 0 1  
0 0 1 0 0 1 0 0  
0 1 0 0 0 0 0 0  
0 1 0 0 0 0 0 1  
0 1 0 0 0 0 1 0  
0 0 0 1 - - - -  
1 1 1 1 1 0 1 0  
1 1 1 1 0 0 1 1  
1 1 1 1 0 1 0 0  
1 1 1 1 0 1 0 1  
1 1 1 1 0 0 0 1  
1 1 1 1 0 0 1 0  
0 1 1 1 - - - -  
1 1 1 1 0 0 0 0  
1 1 1 0 1 1 1 1  
Check Power Mode*  
Device Configuration Restore  
Device Configuration Freeze Lock  
Device Configuration Identify  
Device Configuration Set  
Download Microcode  
Execute Device Diagnostic  
Flush Cache  
Flush Cache Ext  
Format Track  
Format Unit  
Identify Device  
Idle  
Idle*  
Idle Immediate  
Idle Immediate*  
Idle Immediate with Unload option  
Initialize Device Parameters  
Read Buffer  
Read DMA  
Read DMA  
Read DMA Ext  
Read FPDMA Queued  
Read Log Ext  
Read Multiple  
Read Multiple Ext  
Read Native Max Address  
Read Native Max Address Ext  
Read Sector(s)  
Read Sector(s)  
Read Sector(s) Ext  
Read Verify Sector(s)  
Read Verify Sector(s)  
Read Verify Sector(s) Ext  
Recalibrate  
Security Disable Password  
Security Erase Prepare  
Security Erase Unit  
Security Freeze Lock  
Security Set Password  
Security Unlock  
Seek  
Sense Condition  
Set Features  
Table 40 Command set  
75  
   
5K320 SATA OEM Specification  
Protocol  
Command  
Code  
(Hex) 7 6 5 4 3 2 1 0  
F9 1 1 1 1 1 0 0 1  
37 0 0 1 1 0 1 1 1  
F9 1 1 1 1 1 0 0 1  
F9 1 1 1 1 1 0 0 1  
F9 1 1 1 1 1 0 0 1  
F9 1 1 1 1 1 0 0 1  
C6 1 1 0 0 0 1 1 0  
E6 1 1 1 0 0 1 1 0  
99 1 0 0 1 1 0 0 1  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
B0 1 0 1 1 0 0 0 0  
E2 1 1 1 0 0 0 1 0  
96 1 0 0 1 0 1 1 0  
E0 1 1 1 0 0 0 0 0  
94 1 0 0 1 0 1 0 0  
E8 1 1 1 0 1 0 0 0  
CA 1 1 0 0 1 0 1 0  
CB 1 1 0 0 1 0 1 1  
35 0 0 1 1 0 1 0 1  
3D 0 0 1 1 1 1 0 1  
61 0 1 1 0 0 0 0 1  
3F 0 0 1 1 1 1 1 1  
C5 1 1 0 0 0 1 0 1  
39 0 0 1 1 1 0 0 1  
CE 1 1 0 0 1 1 1 0  
30 0 0 1 1 0 0 0 0  
31 0 0 1 1 0 0 0 1  
34 0 0 1 1 0 1 0 0  
45 0 1 0 0 0 1 0 1  
3
3
3
3
2
2
3
3
3
3
3
3
3
3
1
1
1
3
3
2
3
3
3
3
2
4
4
4
4
5
2
2
2
2
2
2
2
3
Set Max Address  
Set Max Address Ext  
Set Max Freeze Lock  
Set Max Lock  
Set Max Set Password  
Set Max Unlock  
Set Multiple Mode  
Sleep  
Sleep*  
S.M.A.R.T. Disable Operations  
S.M.A.R.T. Enable/Disable Attribute Auto save  
S.M.A.R.T. Enable/Disable Automatic Off-line  
S.M.A.R.T. Enable Operations  
S.M.A.R.T. Execute Off-line Immediate  
S.M.A.R.T. Read Attribute Values  
S.M.A.R.T. Read Attribute Thresholds  
S.M.A.R.T. Read Log Sector  
S.M.A.R.T. Return Status  
S.M.A.R.T. Save Attribute Values  
S.M.A.R.T. Write Log Sector  
Standby  
Standby*  
Standby Immediate  
Standby Immediate*  
Write Buffer  
Write DMA  
Write DMA  
Write DMA Ext  
Write DMA FUA Ext  
Write FPDMA Queued  
Write Log Ext  
Write Multiple  
Write Multiple Ext  
Write Multiple FUA Ext  
Write Sector(s)  
Write Sector(s)  
Write Sector(s) Ext  
Write Uncorrectable Ext  
Protocol : 1 : PIO data IN command  
2 : PIO data OUT command  
3 : Non data command  
4 : DMA command  
5 : First-parity DMA command  
+ : Vendor specific command  
Table 41 Command Set - continued  
Commands marked * are alternate command codes for previously defined commands.  
Command (Subcommand)  
Command code  
(Hex)  
Feature  
Register  
76  
 
5K320 SATA OEM Specification  
(Hex)  
(S.M.A.R.T Function)  
S.M.A.R.T. Read Attribute Values  
S.M.A.R.T. Read Attribute Thresholds  
S.M.A.R.T. Enable/Disable Attribute Autosave  
S.M.A.R.T. Save Attribute Values  
S.M.A.R.T. Execute Off-line Immediate  
S.M.A.R.T. Read Log Sector  
S.M.A.R.T. Write Log Sector  
S.M.A.R.T. Enable Operations  
S.M.A.R.T. Disable Operations  
S.M.A.R.T. Return Status  
B0  
B0  
B0  
B0  
B0  
B0  
B0  
B0  
B0  
B0  
B0  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D8  
D9  
DA  
DB  
S.M.A.R.T. Enable/Disable Automatic Off-line  
(Set Features)  
Enable Write Cache  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
EF  
02  
03  
05  
06  
07  
10  
55  
66  
82  
85  
86  
90  
AA  
CC  
Set Transfer Mode  
Enable Advanced Power Management feature  
Enable Power-Up in Standby feature  
Power-Up in Standby feature device Spin-Up  
Enable use of Serial ATA feature  
Disable read look-ahead feature  
Disable reverting to power on defaults  
Disable write cache  
Disable Advanced Power Management feature  
Disable Power-Up in Standby feature  
Disable use of Serial ATA feature  
Enable read look-ahead feature  
Enable reverting to power on defaults  
(Set Max security extension)  
Set Max Set Password  
F9  
F9  
F9  
F9  
01  
02  
03  
04  
Set Max Lock  
Set Max Unlock  
Set Max Freeze Lock  
(Device Configuration Overlay)  
Device Configuration Restore  
Device Configuration Freeze Lock  
Device Configuration Identify  
Device Configuration Set  
B1  
B1  
B1  
B1  
C0  
C1  
C2  
C3  
Table 42 Command Set (Subcommand)  
“Table 40 Command set” on Page 75 shows the commands that are supported by the device. “ Table  
42 Command Set (Subcommand)” on Page 77 shows the sub-commands that are supported by each  
command or feature.  
The following symbols are used in the command descriptions:  
Output Registers  
0
Indicates that the bit must be set to 0.  
1
Indicates that the bit must be set to 1.  
H
Head number. Indicates that the head number part of the Device Register is an output parameter and should  
be specified.  
L
R
LBA mode. Indicates the addressing mode. Zero specifies CHS mode and one does LBA addressing mode.  
Retry. Original meaning is already obsolete, there is no difference between 0 and 1. (Using 0 is  
recommended for future compatibility.)  
B
Option Bit. Indicates that the Option Bit of the Sector Count Register should be specified. (This bit is used by  
77  
 
5K320 SATA OEM Specification  
Set Max ADDRESS command)  
V
x
-
Valid. Indicates that the bit is part of an output parameter and should be specified.  
Indicates that the hex character is not used.  
Indicates that the bit is not used.  
Input Registers  
0
Indicates that the bit is always set to 0.  
1
Indicates that the bit is always set to 1.  
H
Head number. Indicates that the head number part of the Device Register is an input parameter and will be set  
by the device.  
V
N
Valid. Indicates that the bit is part of an input parameter and will be set to 0 or 1 by the device.  
Not recommendable condition for start up. Indicates that the condition of device is not recommendable for  
start up.  
-
Indicates that the bit is not part of an input parameter.  
The command descriptions show the contents of the Status and Error Registers after the device has  
completed processing the command.  
78  
5K320 SATA OEM Specification  
14.1 Check Power Mode (E5h/98h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 1 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
0
0
-
-
0
0
V
Table 43 Check Power Mode Command (E5h/98h)  
The Check Power Mode command will report whether the device is spun up and the media is  
available for immediate access.  
Input Parameters From The Device  
Sector Count  
The power mode code. The command returns FFh in the Sector Count Register if the spindle  
motor is at speed and the device is not in Standby or Sleep mode. Otherwise, the Sector Count  
Register will be set to 0.  
79  
   
5K320 SATA OEM Specification  
14.2 Device Configuration Overlay (B1h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
1 0 1 0 V V V V  
Error  
...See Below...  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
V V V V V V V V  
V V V V V V V V  
-
-
-
-
-
-
-
-
Command  
1 0 1 1 0 0 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
V
V
0
-
V
-
0
V
Table 44 Device Configuration Overlay Command (B1h)  
Individual Device Configuration Overlay feature set commands are identified by the value placed in  
the Features register. The table below shows these Features register values.  
Value  
C0h  
Command  
DEVICE CONFIGURATION RESTORE  
C1h  
DEVICE CONFIGURATION FREEZE LOCK  
DEVICE CONFIGURATION IDENTIFY  
DEVICE CONFIGURATION SET  
Reserved  
C2h  
C3h  
other  
Table 45 Device Configuration Overlay Features register values  
14.2.1 DEVICE CONFIGURATION RESTORE (subcommand  
C0h)  
The DEVICE CONFIGURATION RESTORE command discard any setting previously made by a  
DEVICE CONFIGURATION SET command and return the content of the IDENTIFY DEVICE  
command response to the original settings as indicated by the data returned from the execution of a  
DEVICE CONFIGURATION IDENTIFY command.  
14.2.2 DEVICE CONFIGURATION FREEZE LOCK  
(subcommand C1h)  
The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the  
Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION  
FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION  
FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION  
RESTORE commands are aborted by the device. The DEVICE CONFIGURATION FREEZE LOCK  
condition shall be cleared by a power-down. The DEVICE CONFIGURATION FREEZE LOCK  
condition shall not be cleared by COMRESET or software reset.  
80  
     
5K320 SATA OEM Specification  
14.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand  
C2h)  
The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure via PIO  
data-in transfer. The content of this data structure indicates the selectable commands, modes, and  
feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command  
has been issued reducing the capabilities, the response to an IDENTIFY DEVICE or IDENTIFY  
PACKET DEVICE command will reflect the reduced set of capabilities, while the DEVICE  
CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.  
The format of the Device Configuration Overlay data structure is shown on next page.  
14.2.4 DEVICE CONFIGURATION SET (subcommand C3h)  
The DEVICE CONFIGURATION SET command allows a device manufacturer or a personal  
computer system manufacturer to reduce the set of optional commands, modes, or feature sets  
supported by a device as indicated by a DEVICE CONFIGURATION IDENTIFY command. The  
DEVICE CONFIGURATION SET command transfers an overlay that modifies some of the bits set  
in words 63, 78, 79, 82, 83, 84, and 88 of the IDENTIFY DEVICE command response. When the bits  
in these words are cleared, the device no longer supports the indicated command, mode, or feature  
set. If a bit is set in the overlay transmitted by the device that is not set in the overlay received from  
a DEVICE CONFIGURATION IDENTIFY command, no action is taken for that bit.  
The format of the overlay transmitted by the device is described in the table at next page. The  
restrictions on changing these bits are described in the text following that table. If any of the bit  
modification restrictions described are violated or any setting is changed with DEVICE  
CONFIGURATION SET command, the device shall return command aborted. At that case, error  
reason code is returned to sector count register, invalid word location is returned to LBA High  
register, and invalid bit location is returned to LBA Mid register. The Definition of error information  
is shown on the next page.  
ERROR INFORMATION EXAMPLE 1:  
After establish a protected area with SET MAX address, if a user attempts to execute DC SET or DC  
RESTORE, device abort that command and return error reason code as below.  
LBA High  
LBA Mid  
Sector count  
: 03h  
: 00h  
: 06h  
= word 3 is invalid  
this register is not assigned in this case  
= Protected area is now established  
ERROR INFORMATION EXAMPLE 2:  
When device is enabled the Security feature set, if user attempts to disable that feature, device abort  
that command and return error reason code as below.  
LBA High  
LBA Mid  
Sector count  
: 07h  
: 08h  
: 04h  
= word 7 is invalid  
= bit 3 is invalid  
= now Security feature set is enabled  
81  
5K320 SATA OEM Specification  
Word  
Content  
0002h  
0
1
Data Structure revision  
Multiword DMA modes supported  
15-3 Reserved  
2 1 = Multiword DMA mode 2 and below are supported  
1 1 = Multiword DMA mode 1 and below are supported  
0 1 = Multiword DMA mode 0 is supported  
2
Ultra DMA modes supported  
15-6 Reserved  
5 1 = Ultra DMA mode 5 and below are supported  
4 1 = Ultra DMA mode 4 and below are supported  
3 1 = Ultra DMA mode 3 and below are supported  
2 1 = Ultra DMA mode 2 and below are supported  
1 1 = Ultra DMA mode 1 and below are supported  
0 1 = Ultra DMA mode 0 is supported  
3-6  
7
Maximum LBA address  
Command set/feature set supported  
15-9 Reserved  
8 1 = 48-bit Addressing feature set supported  
7 1 = Host Protected Area feature set supported  
6 Reserved  
5 Reserved  
4 1 = Power-Up in Standby feature set supported  
3 1 = Security feature set supported  
2 1 = SMART error log supported  
1 1 = SMART self-test supported  
0 1 = SMART feature set supported  
8
SATA feature  
15-5 Reserved  
4 1 = Software setting preservation supported  
3 Reserved  
2 1 = Interface power management supported  
1 1 = Non-zero buffer offset in DMA Setup FIS supported  
0 1 = Native command queuing supported  
9-254  
255  
Reserved  
Integrity word <Note .>  
15-8  
7-0  
Checksum  
Signature (A5h)  
Table 46 Device Configuration Overlay Data structure  
Note.  
Bits 7:0 of this word contain the value A5h. Bits 15:8 of this word contain the data structure  
checksum. The data structure checksum is the two’s complement of the sum of all byte in words 0  
through 254 and the byte consisting of bits 7:0 of word 255. Each byte is added with unsigned  
arithmetic, and overflow is ignored. The sum of all bytes is zero when the checksum is correct.  
82  
 
5K320 SATA OEM Specification  
LBA High  
LBA Mid  
invalid word location  
invalid bit location (bits (7:0))  
invalid bit location (bits (15:8))  
error reason code & description  
01h DCO feature is frozen  
LBA Low  
Sector count  
02h Device is now Security Locked mode  
03h Device’s feature is already modified with DCO  
04h User attempt to disable any feature enabled  
05h Device is now SET MAX Locked or Frozen mode  
06h Protected area is now established  
07h DCO is not supported  
08h Subcommand code is invalid  
FFh other reason  
Table 47 DCO error information definition  
83  
 
5K320 SATA OEM Specification  
14.3 Download Microcode (92h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 0 0 1 0 0 1 0  
Status  
...See Below...  
Error Register  
Status Register  
7
8
9
0
10  
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
0
0
0
V
0
0
0
1
0
1
-
0
0
V
Table 48 Download Command (92h)  
Output Parameters To The Device  
Feature  
Subcommand code.  
03h : Download and save microcode with offsets.  
07h : Download and save microcode.  
Other values are reserved.  
Sector Count  
LBA Low  
LBA High/Mid  
Lower byte of 16-bit sector count value to transfer from the host.  
Higher byte of 16-bit sector count value to transfer from the host.  
Buffer offset (only used for Feature = 03h)  
This command enables the host to alter the device's microcode. The data transferred using the  
DOWNLOAD MICROCODE commands is vendor specific.  
All transfers shall be an integer multiple of the sector size. The size of the data transfer is  
determined by the contents of the LBA Low and Sector Count registers. The LBA Low register is  
used to extend the Sector Count register to create a 16-bit sector count value. The LBA Low register  
is the most significant eight bits and the Sector Count register is the least significant eight bits.  
ABT will be set to 1 in the Error Register if the value in the Feature register is neither 03h nor 07h,  
or the device is in Security Locked mode. When the reload of new microcode is requested in the data  
sent by the host for this Download command, UNC error will be set to 1 in the Error Register if the  
device fails to reload new microcode.  
In reloading new microcode, when the spin-up of the device is disabled, the device spins down after  
reloading new microcode.  
A Features register value of 03h indicates that the microcode will be transferred in one or more  
Download Microcode commands using the offset transfer method. The buffer offset value is starting  
location in the microcode file, which varies in 512 byte increments. It is defined by the LBA High and  
LBA Mid registers. The LBA High register is the most significant eight bits and the LBA Mid  
register is the least significant eight bits of the buffer offset value.  
All microcode segments shall be sent to the device in sequence.  
The device will abort the DOWNLOAD MICROCODE command and discard all previously  
downloaded microcode, if the current buffer offset is not equal to the sum of the previous  
84  
   
5K320 SATA OEM Specification  
DOWNLOAD MICROCODE command buffer offset and the previous sector count. The first  
DOWNLOAD MICROCODE command shall have a buffer offset of zero.  
The new firmware becomes effective immediately after the transfer of the last data segment has  
completed.  
When the device detects the last download microcode command for the firmware download the device  
will perform any device required verification and save the complete set of downloaded microcode.  
If the device receives a command other than download microcode prior to the receipt of the last  
segment the new command is executed and all previously downloaded microcode is discarded.  
If a software or hardware Reset is issued to the device before all of the microcode segments have  
been transferred to the device the device shall abandon all of the microcode segments received and  
process the Reset.  
85  
5K320 SATA OEM Specification  
14.4 Execute Device Diagnostic (90h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 0 0 1 0 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
V
V
V
V
V
V
0
0
0
-
-
0
0
0
Table 49 Execute Device Diagnostic Command (90h)  
The Execute Device Diagnostic command performs the internal diagnostic tests implemented by the  
device. The results of the test are stored in the Error Register.  
The normal Error Register bit definitions do not apply to this command. Instead, the register  
contains a diagnostic code. See “Table 31 Diagnostic Codes” on Page 52 for the definition.  
86  
   
5K320 SATA OEM Specification  
14.5 Flush Cache (E7h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 1 1 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 50 Flush Cache Command (E7h)  
This command causes the device to complete writing data from its cache.  
The device returns a status, RDY=1 and DSC=1 (50h), after following sequence.  
Data in the write cache buffer is written to disk media.  
Return a successfully completion.  
87  
   
5K320 SATA OEM Specification  
14.6 Flush Cache Ext (EAh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
-
-
-
-
-
-
-
-
-
-
-
-
1
6
-
-
-
-
-
-
-
-
-
-
-
-
-
1
5
-
-
-
-
-
-
-
-
-
-
-
-
-
1
4
-
-
-
-
-
-
-
-
-
-
-
-
-
0
3
-
-
-
-
-
-
-
-
-
-
-
-
-
1
2
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
0
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
Current  
...See Below...  
Previous  
Sector Count Current  
Previous  
Sector Count HOB=0  
HOB=1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
LBA Low  
LBA Mid  
LBA High  
HOB=0  
HOB=1  
HOB=0  
HOB=1  
HOB=0  
HOB=1  
Device  
Device  
Status  
Command  
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
0
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 51 Flush Cache EXT Command (EAh)  
This command causes the device to complete writing data from its cache.  
The device returns good status after data in the write cache is written to disk media.  
88  
   
5K320 SATA OEM Specification  
14.7 Format Track (50h: Vendor Specific)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
0 1 0 1 0 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 52 Format Track Command (50h)  
The Format Track command formats a single logical track on the device. Each good sector of data on  
the track will be initialized to zero with write operation. At this time, whether the sector of data is  
initialized correctly is not verified with read operation. Any data previously stored on the track will  
be lost.  
Output Parameters To The Device  
LBA Low  
LBA High/Mid  
In LBA mode, this register specifies LBA address bits 0 - 7 to be formatted. (L=1)  
The cylinder number of the track to be formatted. (L=0)  
In LBA mode, this register specifies LBA address bits 8 - 15 (Mid), 16 - 23 (High) to be  
formatted. (L=1)  
H
The head number of the track to be formatted. (L=0)  
In LBA mode, this register specifies LBA address bits 24 - 27 to be formatted. (L=1)  
Input Parameters From The Device  
LBA Low  
LBA High/Mid  
H
In LBA mode, this register specifies current LBA address bits 0-7. (L=1)  
In LBA mode, this register specifies current LBA address bits 8 - 15 (Mid), 16 - 23 (High)  
In LBA mode, this register specifies current LBA address bits 24 - 27. (L=1)  
In LBA mode, this command formats a single logical track including the specified LBA.  
89  
   
5K320 SATA OEM Specification  
14.8 Format Unit (F7h: Vendor Specific)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
V V V V V V V V  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 1 1 1  
Status  
...See Below...  
Error Register  
Status Register  
7
8
9
0
10  
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 53 Format Unit Command (F7h)  
The Format Unit command initializes all user data sectors after merging reassigned sector location  
into the defect information of the device and clearing the reassign information. Both new reassign  
information and new defect information are available right after this command completion, and are  
also used on next power on reset. Both previous information are erased from the device by this  
command.  
Note that the Format Unit command initializes from LBA 0 to Native MAX LBA. Host MAX LBA set  
by Initialize Drive Parameter or Set MAX ADDRESS command is ignored. So the protected area by  
Set MAX ADDRESS commands is also initialized.  
The security erase prepare command should be completed immediately prior to the Format Unit  
command. If the device receives a Format Unit command without a prior Security Erase Prepare  
command the device aborts the Format Unit command.  
If Feature register is NOT 11h, the device returns Abort error to the host.  
This command does not request to data transfer.  
Output Parameters To The Device  
Feature  
Destination code for this command  
11H Merge reassigned location into the defect information  
The execution time of this command is shown below.  
HTS543232L9SA00 / HTS543232L9A300  
HTS543225L9SA00 / HTS543225L9A300  
HTS543216L9SA00 / HTS543216L9A300  
HTS543212L9SA00 / HTS543212L9A300  
HTS543280L9SA00 / HTS543280L9A300  
125 min  
100 min  
65 min  
50 min  
35 min  
90  
   
5K320 SATA OEM Specification  
14.9 Identify Device (ECh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 1 1 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 54 Identify Device Command (ECh)  
The Identify Device command requests the device to transfer configuration information to the host.  
The device will transfer a sector to the host containing the information in “Table 55 Identify device  
information” on Page 91-101.  
91  
   
5K320 SATA OEM Specification  
Word  
Content  
045xH  
Description  
00  
Drive classification, bit assignments:  
15 (=0): 1=ATAPI device, 0=ATA device  
14 (=0): 1=format speed tolerance gap required  
13 (=0): 1=track offset option available  
12 (=0): 1=data strobe offset option available  
11 (=0): 1=rotational speed tolerance > 0.5%  
10 (=1): 1=disk transfer rate > 10 Mbps  
9 (=0): 1=disk transfer rate > 5 Mbps but <= 10 Mbps  
8 (=0): 1=disk transfer rate <= 5 Mbps  
7 (=0): 1=removable cartridge device  
6 (=1): 1=fixed device  
*
*
*
*
*
*
*
*
*
*
5 (=0): 1=spindle motor control option implemented  
4 (=1): 1=head switch time > 15 us  
3 (=1): 1=not MFM encoded  
2 (=x): 1=Identify data incomplete  
1 (=1): 1=hard sectored  
*
0 (=0): Reserved  
01  
02  
Note.2  
xxxxh  
Number of cylinders in default translate mode  
Specific configuration  
C837h  
SET FEATURES subcommand is not required to spin-up  
and IDENTIFY DEVICE response is complete  
37C8h  
SET FEATURES subcommand is required to spin-up and  
IDENTIFY DEVICE response is incomplete  
03  
Note.2  
0
Number of heads in default translate mode  
Reserved  
04-05  
06  
*
*
003FH  
0
Number of sectors per track in default translate mode  
Reserved  
07-09  
10-19  
20  
XXXX  
0003H  
Serial number in ASCII (0 = not specified)  
Controller type:  
0003: dual ported, multiple sector buffer with look-ahead read  
Buffer size in number of sectors  
Obsolete  
21  
22  
Note.2  
00xxH  
XXXX  
Note.2  
8010H  
*
*
23-26  
27-46  
47  
Microcode version in ASCII  
Model number in ASCII  
Maximum number of sectors that can be transferred per interrupt on Read  
and Write Multiple commands  
15-8 : (=80h)  
7-0 : Maximum number of sectors that can be transferred per  
interrupt.  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Note.2 See following table “Table 64 Number of cylinders/heads/sectors by models for  
HTS5432XXL9SA00 / HTS5432XXL9A300” on Page 102  
Table 55 Identify device information  
92  
 
5K320 SATA OEM Specification  
Word  
Content  
4000H  
Description  
48  
49  
Trusted Computing feature set options  
15(=0) Always 0  
14(=1) Always 1  
13- 1(=0) Reserved  
0(=0) 1=Trusted Computing feature set is supported  
0F00H  
Capabilities, bit assignments:  
15-14 (=0) Reserved  
13 (=0) 0= Standby timer value are vendor specific  
12 (=0) Reserved  
11 (=1) 1= IORDY Supported  
10 (=1) 1= IORDY can be disabled  
9 (=1) 1=LBA Supported  
8 (=1) 1=DMA Supported  
7- 0 (=0) Reserved  
*
50  
4000H  
Capabilities  
15 (=0) 0=the contents of word 50 are valid  
14 (=1) 1=the contents of word 50 are valid  
13- 2 (=0) Reserved  
1 (=0) Obsolete  
0 (=0) 1=the device has a minimum Standby timer value that is  
device specific  
51  
52  
0200H  
0200H  
*
PIO data transfer cycle timing mode  
*
DMA data transfer cycle timing mode  
Refer Word 62 and 63  
53  
x007H  
Validity flag of the word  
15- 8 xxh = FFS Sense Level  
7- 3(=0) Reserved  
2(=1) 1=Word 88 is Valid  
1(=1) 1=Word 64-70 are Valid  
0(=1) 1=Word 54-58 are Valid  
54  
55  
56  
xxxxH  
xxxxH  
xxxxH  
xxxxH  
Number of current cylinders  
Number of current heads  
Number of current sectors per track  
57-58  
Current capacity in sectors  
Word 57 specifies the low word of the capacity  
59  
0xxxH  
Current Multiple setting. bit assignments  
15- 9 (=0) Reserved  
8 1= Multiple Sector Setting is Valid  
7- 0 xxh = Current setting for number of sectors  
Total Number of User Addressable Sectors  
Word 60 specifies the low word of the number  
FFFFFFFh=The 48-bit native max address is greater than 268,435,455  
60-61  
62  
Note.2  
0000H  
*
Reserved  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Note.2 See following table “Table 64 Number of cylinders/heads/sectors by models for  
HTS5432XXL9SA00 / HTS5432XXL9A300” on Page 102  
Table 56 Identify device information --- Continued ---  
93  
 
5K320 SATA OEM Specification  
Word  
Content  
0x07H  
Description  
63  
Multiword DMA Transfer Capability  
15-11(=0) Reserved  
10 1=Multiword DMA mode 2 is selected  
9 1=Multiword DMA mode 1 is selected  
8 1=Multiword DMA mode 0 is selected  
7- 3 (=0) Reserved  
2 (=1) 1=Multiword DMA mode 2 is supported  
1 (=1) 1=Multiword DMA mode 1 is supported  
0 (=1) 1=Multiword DMA mode 0 is supported  
64  
0003H  
Flow Control PIO Transfer Modes Supported  
15- 8 (=0) Reserved  
7- 0 (=3) Advanced PIO Transfer Modes Supported  
‘11’ = PIO Mode 3 and 4 Supported  
65  
66  
67  
68  
0078H  
0078H  
0078H  
0078H  
Minimum Multiword DMA Transfer Cycle Time Per Word  
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)  
Manufacturer’s Recommended Multiword DMA Transfer Cycle Time  
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)  
Minimum PIO Transfer Cycle Time Without Flow Control  
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)  
Minimum PIO Transfer Cycle Time With IORDY Flow Control  
15- 0 (=78h) Cycle time in nanoseconds (120ns, 16.6MB/s)  
Reserved  
69-74  
75  
0000H  
001FH  
Queue depth  
15-5(=0) Reserved  
4-0(=1Fh) Maximum queued depth - 1  
SATA capabilities  
76  
170xH  
15-13(=0) Reserved  
1=Native Command Queuing priority information  
supported  
12(=1)  
1=Unload while NCQ commands outstanding  
supported  
11(=0)  
10(=1) 1=Phy event counters supported  
1=Receipt of host-initiated interface power  
9(=1)  
management requests supported  
8(=1) 1=Native Command Queuing supported  
7-3(=0) Reserved  
**2(=x) 1=SATA Gen-2 speed (3.0Gbps) supported  
1(=1) 1=SATA Gen-1 speed (1.5Gbps) supported  
0(=0) Reserved  
77  
0000H  
Reserved  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Note.2 The ‘**’ mark depends on HTS5432XXL9SA00 or HTS5432XXL9A300.  
Table 57 Identify device information --- Continued ---  
94  
 
5K320 SATA OEM Specification  
Word  
Content  
005EH  
Description  
78  
SATA supported features  
15-7(=0) Reserved  
6(=1) 1=Software setting preservation supported  
5(=0) Reserved  
4(=1) 1=In-order data delivery supported  
1=Device initiated interface power management  
supported  
3(=1)  
2(=1) 1=DMA Setup Auto-Activate optimization supported  
1=Non-zero buffer offset in DMA Setup FIS  
supported  
1(=1)  
0(=0) Reserved  
79  
00xxH  
SATA enabled features  
15-7(=0) Reserved  
6(=x) 1=Software setting preservation enabled  
5(=0) Reserved  
4(=x) 1=In-order data delivery enabled  
1=Device initiated interface power management  
enabled  
3(=x)  
2(=x) 1=DMA Setup Auto-Activate optimization enabled  
1(=x) 1=Non-zero buffer offset in DMA Setup FIS enabled  
0(=0) Reserved  
80  
01FCH  
Major version number  
ATA-2.3 and ATA/ATAPI-4, 5, 6, 7, 8  
Minor version number—ATA8-ACS revision 3f --  
Command set supported  
81  
82  
0042H  
746BH  
15 (=0) Reserved  
14 (=1) 1=NOP command supported  
13 (=1) 1=READ BUFFER command supported  
12 (=1) 1=WRITE BUFFER command supported  
11 (=0) Reserved  
10 (=1) 1=Host Protected Area Feature Set supported  
9 (=0) 1=DEVICE RESET command supported  
8 (=0) 1=SERVICE interrupt supported  
7 (=0) 1=release interrupt supported  
6 (=1) 1=look-ahead supported  
5 (=1) 1=write cache supported  
4 (=0) 1=supports PACKET Command Feature Set  
3 (=1) 1=supports Power Management Feature Set  
2 (=0) 1=supports Removable Media Feature Set  
1 (=1) 1=supports Security Feature Set  
0 (=1) 1=supports S.M.A.R.T Feature Set  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Table 58 Identify device information --- Continued ---  
95  
 
5K320 SATA OEM Specification  
Word  
Content  
7F69H  
Description  
83  
Command set supported  
15 (=0) Always  
14 (=1) Always  
13 (=1) 1=FLUSH CACHE EXT command supported  
12 (=1) 1=FLUSH CACHE command supported  
11 (=1) 1=Device Configuration Overlay command supported  
10 (=1) 1=48-bit Address feature set supported  
9 (=0) Reserved  
8 (=1) 1=SET MAX security extension supported  
7 (=0) Reserved  
6 (=1) 1=SET FEATURES subcommand required to spin-up  
5 (=1) 1=Power-Up In Standby feature set supported  
4 (=0) 1=Removable Media Status Notification Feature Set  
supported  
3 (=1) 1=Advanced Power Management Feature Set  
supported  
2 (=0) 1=CFA Feature Set supported  
1 (=0) 1=READ/WRITE DMA QUEUED supported  
0 (=1) Download Microcode Command Supported  
84  
6163H  
Command set/feature supported extension  
15 (=0) Always  
14 (=1) Always  
13 (=1) 1=IDLE IMMEDIATE with UNLOAD FEATURE  
supported  
12- 9 (=0) Reserved  
8 (=1) 1=64-bit World wide name supported  
7 (=0) 1=WRITE DMA QUEUED FUA EXT command  
supported  
6 (=1) 1=WRITE DMA FUA EXT and WRITE MULTIPLE  
FUA EXT commands supported  
5 (=1) 1=General Purpose Logging feature set supported  
4- 2 (=0) Reserved  
1 (=1) 1=SMART self-test supported  
0 (=1) 1=SMART error logging supported  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Table 59 Identify device information --- Continued ---  
96  
 
5K320 SATA OEM Specification  
Word  
Content  
74xxH  
Description  
85  
Command set/feature enabled  
15 (=0) Obsolete  
14 (=1) 1=NOP command supported  
13 (=1) 1=READ BUFFER command supported  
12 (=1) 1=WRITE BUFFER command supported  
11 (=0) Reserved  
10 (=1) 1=Host Protected Area Feature Set supported  
9 (=0) 1=DEVICE RESET command supported  
8 (=0) 1=SERVICE interrupt enabled  
7 (=0) 1=release interrupt enabled  
6 (=x) 1=look-ahead enabled  
5 (=x) 1=write cache enabled  
4 (=0) 1=supports PACKET Command Feature Set  
3 (=1) 1=supports Power Management Feature Set  
2 (=0) 1=supports Removable Media Feature Set  
1 (=x) 1=Security Feature Set enabled  
0 (=x) 1=S.M.A.R.T Feature Set enabled  
86  
BxxxH  
Command set/feature enabled  
15 (=1) 1=Words 120:119 are valid  
*
*
14 (=0) Reserved  
13 (=1) 1=FLUSH CACHE EXT command supported  
12 (=1) 1= FLUSH CACHE command supported  
11 (=x) 1=Device Configuration Overlay supported  
10 (=1) 1= 48-bit Address feature set supported  
9 (=0) Reserved  
8 (=x) 1=SET MAX security extension enabled  
7 (=0) Reserved  
6 (=1) 1=SET FEATURES subcommand required to spin-up  
5 (=x) 1=Power-Up In Standby feature set has been enabled  
via the SET FEATURES command  
4 (=0) 1=Removable Media Status Notification Feature Set  
enabled  
3 (=x) 1=Advanced Power Management Feature Set enabled  
2 (=0) 1=CFA Feature Set supported  
1 (=0) 1=READ/WRITE DMA QUEUED command  
supported  
0 (=1) 1=DOWNLOAD MICROCODE command supported  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Table 60 Identify device information --- Continued ---  
97  
 
5K320 SATA OEM Specification  
Word  
Content  
6163H  
Description  
87  
Command set/feature enabled  
15 (=0) Always  
14 (=1) Always  
13 (=1) 1=IDLE IMMEDIATE with UNLOAD FEATURE  
supported  
12- 9 (=0) Reserved  
8 (=1) 1=64 bit World wide name supported  
7 (=0) 1=WRITE DMA QUEUED FUA EXT command  
supported  
6 (=1) 1=WRITE DMA FUA EXT and WRITE MULTIPLE  
FUA EXT command supported  
5 (=1) 1=General Purpose Logging feature set supported  
4- 2 (=0) Reserved  
1 (=1) 1=SMART self-test supported  
0 (=1) 1=SMART error logging supported  
88  
xx7FH  
Ultra DMA Transfer mode (mode 6 supported)  
15 (=0) Reserved  
14 (=x) 1=UltraDMA mode 6 is selected  
13 (=x) 1=UltraDMA mode 5 is selected  
12 (=x) 1=UltraDMA mode 4 is selected  
11 (=x) 1=UltraDMA mode 3 is selected  
10 (=x) 1=UltraDMA mode 2 is selected  
9 (=x) 1=UltraDMA mode 1 is selected  
8 (=x) 1=UltraDMA mode 0 is selected  
7 (=0) Reserved  
6 (=1) 1=UltraDMA mode 6 is supported  
5 (=1) 1=UltraDMA mode 5 is supported  
4 (=1) 1=UltraDMA mode 4 is supported  
3 (=1) 1=UltraDMA mode 3 is supported  
2 (=1) 1=UltraDMA mode 2 is supported  
1 (=1) 1=UltraDMA mode 1 is supported  
0 (=1) 1=UltraDMA mode 0 is supported  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Table 61 Identify device information --- Continued ---  
98  
 
5K320 SATA OEM Specification  
Word  
Content  
xxxxH  
Description  
89  
90  
91  
Time required for security erase unit completion  
Time= value(xxxxh)*2 [minutes]  
xxxxH  
40xxH  
Time required for Enhanced security erase completion  
Time= value(xxxxh)*2 [minutes]  
Current Advanced Power Management level  
15- 8 (=40h) Reserved  
7- 0 (=xxh) Currect Advanced Power Management level set by Set  
Features Command (01h to FEh)  
92  
93  
94  
95  
96  
97  
xxxxH  
0000H  
0000H  
0000H  
0000H  
0000H  
0000H  
Note.2  
0000H  
0000H  
7AB8H  
XXXX  
0000H  
4014H  
Current Master Password Revision Codes  
Reserved  
Reserved  
Stream Minimum Request Size  
Streaming Transfer Time – DMA  
Streaming Access Latency – DMA and PIO  
Streaming Performance Granularity  
Maximum user LBA address for 48-bit Address feature set  
Streaming Transfer Time - PIO  
Reserved  
98-99  
100-103  
104  
105-106  
107  
Inter seek delay time (1.5tt + 2.5tl)  
World Wide Name  
108-111  
112-118  
119  
Reserved  
Supported Setting  
15 (=0) Always  
14 (=1) Always  
13-6 (=0) Reserved  
5 (=0) 1=Free-fall Control feature set is supported  
4 (=1) 1=Download Microcode with mode 3 is supported  
3 (=0) 1=Read and Write DMA Ext GPL is supported  
2 (=1) 1=WRITE UNCORRECTABLE is supported  
1 (=0) 1=Write Read Verify feature set is supported  
0 (=0) Reserved  
120  
4014H  
Enabled Setting  
15 (=0) Always  
14 (=1) Always  
13-6 (=0) Reserved  
5 (=0) 1=Free-fall Control feature set is enabled  
4 (=1) 1=Download Microcode with mode 3 is supported  
3 (=0) 1=Read and Write DMA Ext GPL is supported  
2 (=1) 1=WRITE UNCORRECTABLE is supported  
1 (=0) 1=Write Read Verify feature set is enabled  
0 (=0) Reserved  
121-126  
127  
0000H  
0000H  
Reserved  
Removable Media Status Notification feature set  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
Table 62 Identify device information --- Continued ---  
99  
 
5K320 SATA OEM Specification  
Word  
128  
Content  
0xxxH  
Description  
Security status. Bit assignments  
15-9 (=0) Reserved  
8 (=x) Security Level 1= Maximum, 0= High  
7-6 (=0) Reserved  
5 (=1) 1=Enhanced security erase supported  
4 (=x) 1=Security count expired  
3 (=x) 1=Security Frozen  
2 (=x) 1=Security locked  
1 (=x) 1=Security enabled  
**0 (=1) 1=Security supported  
129  
000xH  
* Current Set Feature Option. Bit assignments  
15-4(=0) Reserved  
3(=x) 1=Auto reassign enabled  
2(=x) 1=Reverting enabled  
1(=x) 1=Read Look-ahead enabled  
0(=x) 1=Write Cache enabled  
130  
131  
xxxxH  
000xH  
* Reserved  
* Initial Power Mode Selection. Bit assignments  
15-1(=0) Reserved  
0(=x) Initial Power Mode 1= Standby, 0= Idle  
132-205  
206  
xxxxH  
003DH  
* Reserved  
SCT Command Transport  
15- 6(=0) Reserved  
5(=1) 1=SCT Data Tables supported  
4(=1) 1=SCT Features Control supported  
3(=1) 1=SCT Error Recovery Control supported  
2(=1) 1=SCT Write Same supported  
1(=0) 1=SCT Long Sector Access supported  
0(=1) 1=SCT Command Transport supported  
207 – 216  
217  
xxxxH  
1518H  
xxxxH  
101FH  
* Reserved  
Media Rotation Rate  
* Reserved  
Transport Major Revision Number  
218 - 221  
222  
15- 12 Transport Type 0=Parallel, 1=Serial, 2-15=Reserved  
11- 5(=0) Reserved  
4(=1) 1=SATA 2.6  
3(=1) 1=SATA 2.5  
2(=1) 1=SATA II: Extensions  
1(=1) 1=SATA 1.0a  
0(=1) 1=ATA8-AST  
223  
224 – 233  
234  
0021H  
xxxxH  
0001H  
0080H  
xxxxH  
xxA5H  
Transport Minor Revision Number – ATA8-AST Revision 0b  
* Reserved  
Minimum number of data blocks per Download Microcode for mode 3  
Maximum number of data blocks per Download Microcode for mode 3  
235  
236 - 254  
255  
* Reserved  
Integrity word  
15-8 (=xxh) Checksum  
7-0 (=A5h) Signature  
Note.1 The ‘*’ mark in ‘Content’ field indicates the use of those parameters that are vendor specific.  
100  
5K320 SATA OEM Specification  
Note.2 See following table “Table 64 Number of cylinders/heads/sectors by models for  
HTS5432XXL9SA00 / HTS5432XXL9A300” on Page 102  
Table 63 Identify device information --- Continued ---  
101  
 
5K320 SATA OEM Specification  
Model Number in ASCII Hitachi  
Hitachi  
Hitachi  
HTS543232L9SA00 HTS543225L9SA00 HTS543216L9SA00  
Number of cylinders  
Number of heads  
Buffer size  
3FFFh  
10h  
3FFFh  
10h  
3FFFh  
10h  
3795h  
3795h  
3795h  
Total number of user  
addressable sectors (word  
60-61)  
2542EAB0h  
FFFFFFFh  
FFFFFFFh  
Maximum user LBA  
2542EAB0h  
1D1C5970h  
12A19EB0h  
address for 48-bit Address  
feature set (word 100-103)  
Model Number in ASCII Hitachi  
Hitachi  
HTS543212L9SA00 HTS543280L9SA00  
Number of cylinders  
Number of heads  
Buffer size  
3FFFh  
10h  
3FFFh  
10h  
3795h  
3795h  
950F8B0h  
Total number of user  
addressable sectors (word  
60-61)  
DF94BB0h  
Maximum user LBA  
DF94BB0h  
950F8B0h  
address for 48-bit Address  
feature set (word 100-103)  
Model Number in ASCII Hitachi  
Hitachi  
Hitachi  
HTS543232L9A300 HTS543225L9A300 HTS543216L9A300  
Number of cylinders  
Number of heads  
Buffer size  
3FFFh  
10h  
3FFFh  
10h  
3FFFh  
10h  
3795h  
3795h  
3795h  
Total number of user  
addressable sectors (word  
60-61)  
2542EAB0h  
FFFFFFFh  
FFFFFFFh  
Maximum user LBA  
2542EAB0h  
1D1C5970h  
12A19EB0h  
address for 48-bit Address  
feature set (word 100-103)  
Model Number in ASCII Hitachi  
Hitachi  
HTS543212L9A300 HTS543280L9A300  
Number of cylinders  
Number of heads  
Buffer size  
3FFFh  
10h  
3FFFh  
10h  
3795h  
3795h  
950F8B0h  
Total number of user  
addressable sectors (word  
60-61)  
DF94BB0h  
Maximum user LBA  
DF94BB0h  
950F8B0h  
address for 48-bit Address  
feature set (word 100-103)  
Table 64 Number of cylinders/heads/sectors by models for HTS5432XXL9SA00 / HTS5432XXL9A300  
102  
 
5K320 SATA OEM Specification  
14.10 Idle (E3h/97h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 0 1 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 65 Idle Command (E3h/97h)  
When the power save mode is Standby mode, the Idle command causes the device to enter  
performance Idle mode immediately, and set auto power down timeout parameter(standby timer).  
And then the timer starts counting down. When the device’s power save mode is already any idle  
mode, the device keep that mode.  
When the Idle mode is entered, the device is spun up to operating speed. If the device is already  
spinning, the spin up sequence is not executed.  
During Idle mode the device is spinning and ready to respond to host commands immediately.  
Output Parameters To The Device  
Sector Count  
Timeout Parameter. If zero, the timeout interval(Standby Timer) is  
zero, the timeout interval is set for (Timeout Parameter x5) seconds.  
disabled. If other than  
The device will enter Standby mode automatically if the timeout interval expires with no  
device access from the host. The timeout interval will be reinitialized if there is a device  
access before the timeout interval expires.  
103  
   
5K320 SATA OEM Specification  
14.11 Idle Immediate (E1h/95h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 0 0 1  
Status  
...See Below...  
Unload Feature  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
0 1 0 0 0 1 0 0  
0 0 0 0 0 0 0 0  
0 1 0 0 1 1 0 0  
0 1 0 0 1 1 1 0  
0 1 0 1 0 1 0 1  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
1 1 0 0 0 1 0 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- D -  
-
-
-
Command  
1 1 1 0 0 0 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 66 Idle Immediate Command (E1h/95h)  
The Idle Immediate command causes the device to enter performance Idle mode.  
The device is spun up to operating speed. If the device is already spinning, the spin up sequence is  
not executed.  
During Idle mode the device is spinning and ready to respond to host commands immediately.  
The Idle Immediate command will not affect the auto power down timeout parameter.  
Unload Feature:  
The UNLOAD FEATURE of the IDLE IMMEDIATE command allows the host to immediately unload the heads.  
The device stops read look-ahead if it is in process. If the device is performing a write operation, the device  
suspends writing cached data onto the media as soon as possible. The data in the write cache is retained, and the  
device resumes writing the cached data onto the media after receiving a Software Reset, a Hardware Reset, or any  
new command except IDLE IMMEDIATE with UNLOAD FEATURE.  
104  
   
5K320 SATA OEM Specification  
14.12 Initialize Device Parameters (91h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- H H H H  
Command  
1 0 0 1 0 0 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
0
0
-
-
0
0
V
Table 67 Initialize Device Parameters Command (91h)  
The Initialize Device Parameters command enables the host to set the number of sectors per track  
and the number of heads minus 1, per cylinder. Words 54-58 in Identify Device Information reflects  
these parameters.  
The parameters remain in effect until the following events:  
Another Initialize Device Parameters command is received.  
The device is powered off.  
Soft reset occurs and the Set Feature option of CCh is set  
Output Parameters To The Device  
Sector Count  
The number of sectors per track. 0 does not mean there are 256 sectors per track, but there is no  
sector per track.  
H
The number of heads minus 1 per cylinder. The minimum is 0 and the maximum is 15.  
105  
   
5K320 SATA OEM Specification  
14.13 Read Buffer (E4h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 1 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 68 Read Buffer Command (E4h)  
The Read Buffer command transfers a sector of data from the sector buffer of device to the host.  
The sector is transferred through the Data Register 16 bits at a time.  
The sector transferred will be from the same part of the buffer written to by the last Write Buffer  
command. The contents of the sector may be different if any reads or writes have occurred since the  
Write Buffer command was issued.  
106  
   
5K320 SATA OEM Specification  
14.14 Read DMA(C8h/C9h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
1 1 0 0 1 0 0 R  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
V
V
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 69 Read DMA Command (C8h/C9h)  
The Read DMA command reads one or more sectors of data from disk media, then transfers the data  
from the device to the host.  
The sectors are transferred through the Data Register 16 bits at a time.  
The host initializes a slave-DMA channel prior to issuing the command. The data transfers are  
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one  
interrupt per command to indicate that data transfer has terminated and status is available.  
If an uncorrectable error occurs, the read will be terminated at the failing sector.  
Output Parameters To The Device  
Sector Count  
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors  
will be transferred.  
LBA Low  
The sector number of the first sector to be transferred. (L=0)  
In LBA mode, this register specifies LBA address bits 0 - 7 to be transferred. (L=1)  
The cylinder number of the first sector to be transferred. (L=0)  
In LBA mode, this register specifies LBA address bits 8 - 15 (Mid) 16 - 23 (High) to be  
transferred. (L=1)  
LBA High/Mid  
H
R
The head number of the first sector to be transferred. (L=0)  
In LBA mode, this register specifies LBA bits 24-27 to be transferred. (L=1)  
The retry bit, but this bit is ignored.  
Input Parameters From The Device  
Sector Count  
The number of requested sectors not transferred. This will be zero, unless an  
unrecoverable error occurs.  
LBA Low  
The sector number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
The cylinder number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
LBA High/Mid  
H
The head number of the sector to be transferred. (L=0)  
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)  
107  
   
5K320 SATA OEM Specification  
14.15 Read DMA Ext (25h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
7
-
6
5
4
3
2
1
0
Data Low  
Data Low  
108  
   
5K320 SATA OEM Specification  
14.16 Read FPDMA Queued (60h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Data Low  
Data High  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
V V V V V V V V Error  
V V V V V V V V  
...See Below...  
Previous  
Sector Count Current  
Previous  
T
P
T
-
T
-
T
-
T
-
-
-
-
-
-
-
Sector Count HOB=0  
HOB=1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
F
0
1
1
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
1
0
0
0
0
0
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
V
V
V
0
0
0
V
0
V
-
0
0
V
Table 71 Read FPDMA Queued Command (60h)  
The Read FPDMA Queued command reads one or more sectors of data from disk media, then  
transfers the data from the device to the host.  
If an uncorrectable error occurs, the read will be terminated at the failing sector.  
Output Parameters To The Device  
Feature Current  
Feature Previous  
T
The number of sectors to be transferred low order, bits (7:0)  
The number of sectors to be transferred high order, bits (15:8)  
TAG value. It shall be assigned to be different from all other queued commands.  
The value shall not exceed the maximum queue depth specified by the Word 75 of the  
Identify Device information.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
F
LBA (7:0)  
LBA (31:24)  
LBA (15:8)  
LBA (39:32)  
LBA (23:16)  
LBA (47:40)  
FUA bit. When the FUA bit is set to 1, the requested data is always retrieved from  
the media regardless of whether the data are held in the sector buffer or not. When  
the FUA bit is set to 0, the data may be retrieved from the media or from the cached  
data left by previously processed Read or Write commands.  
Priority bit. When the Priority bit is set to 1, the device attempts to provide better  
quality of service for the command than normal priority commands.  
P
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24)of the address of the first unrecoverable error.  
LBA (15:8)of the address of the first unrecoverable error.  
LBA (39:32)of the address of the first unrecoverable error.  
LBA (23:16)of the address of the first unrecoverable error.  
LBA (47:40)of the address of the first unrecoverable error.  
109  
   
5K320 SATA OEM Specification  
14.17 Read Log Ext(2Fh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Data Low  
Data High  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
- R- Error  
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
HOB=0  
HOB=1  
HOB=0  
HOB=1  
HOB=0  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
-
-
-
-
-
-
-
-
V V V V V V V V LBA Mid  
V V V V V V V V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA High  
Device  
-
-
-
-
-
-
-
-
Device  
Status  
Command  
0
0
1
0
1
1
1
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
V
V
V
0
0
0
V
0
V
-
0
0
V
Table 72 Read Log Ext Command (2Fh)  
This command returns the specified log to the host. The device shall interrupt for each DRQ block  
transferred.  
Output Parameters To The Device  
R
Phy Event Counter Reset bit. When Log address is 11h (Phy Event Counter) and this  
bit is set to 1, all Phy Event Counter values are reset to 0 after sending the current  
counter valules.  
Sector Count Current  
The number of sectors to be read from the specified log low order, bits (7:0). The log  
transferred by the drive shall start at the sector in the specified log at the specified  
offset, regardless of the sector count requested.  
Sector Count Previous  
LBA Low Current  
LBA Mid Current  
LBA Mid Previous  
The number of sectors to be read from the specified log high orders, bits (15:8).  
The log to be returned as described in the following table.  
The first sector of the log to be read low order, bits (7:0).  
The first sector of the log to be read high order, bits (15:8).  
Log  
Content  
Feature set  
Type  
address  
00h  
03h  
Log directory  
Extended Comprehensive SMART SMART  
N/A  
ReadOnly  
error ReadOnly  
error log  
logging  
07h  
10h  
Extended SMART self-test log  
Command Error  
SMART self-test ReadOnly  
Native Command ReadOnly  
Queuing  
11h  
Phy Event Counter  
PhyEventCounter ReadOnly  
80h-9Fh Host vendor specific  
SMART  
Read/Wri  
te  
Table 73 Log address definition  
110  
     
5K320 SATA OEM Specification  
The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit  
entries contained in the SMART self-test log sector shall also be included in the Comprehensive  
SMART self-test log sector with the 48-bit entries.  
If the feature set associated with the log specified in the Sector Number register is not supported or  
enabled, or if the values in the Sector Count, Sector Number or Cylinder Low registers are invalid,  
the device shall return command aborted.  
14.17.1 General purpose Log Directory  
The following table defines the 512 bytes that make up the General Purpose Log Directory.  
Description  
Bytes Offset  
General Purpose Logging Version  
2
1
1
1
1
00h  
02h  
03h  
04h  
05h  
Number of sectors in the log at log address 01h (7:0)  
Number of sectors in the log at log address 01h (15:8)  
Number of sectors in the log at log address 02h (7:0)  
Number of sectors in the log at log address 02h (15:8)  
...  
Number of sectors in the log at log address 80h (7:0)  
Number of sectors in the log at log address 80h (15:8)  
...  
1
1
100h  
101h  
Number of sectors in the log at log address FFh (7:0)  
Number of sectors in the log at log address FFh (15:8)  
1
1
1FEh  
1FFh  
512  
Table 74 General purpose Log Directory  
The value of the General Purpose Logging Version word shall be 0001h. A value of 0000h indicates  
that there is no General Purpose Log Directory.  
The logs at log addresses 80-9Fh shall each be defined as 16 sectors long.  
14.17.2 Extended comprehensive SMART error log  
The following table defines the format of each of the sectors that comprise the Extended  
Comprehensive SMART error log. Error log data structure shall not include errors attributed to the  
receipt of faulty commands such as command codes not implemented by the device or requests with  
invalid parameters or in valid addresses.  
111  
 
5K320 SATA OEM Specification  
Description  
Bytes Offset  
SMART error log version  
Reserved  
1
1
00h  
01h  
Error log index (7:0)  
Error log index (15:8)  
1st error log data structure  
2nd error log data structure  
3rd error log data structure  
4th error log data structure  
Device error count  
1
1
02h  
03h  
04h  
80h  
124  
124  
124  
124  
2
FCh  
178h  
1F4h  
1F6h  
1FFh  
Reserved  
Data structure checksum  
9
1
512  
Table 75 Extended comprehensive SMART error Log  
14.17.2.1  
Error Log version  
The value of this version shall be 01h.  
14.17.2.2  
Error log index  
This indicates the error log data structure representing the most recent error. If there have been no  
error log entries, it is cleared to 0. Valid values for the error log index are 0 to 4.  
14.17.2.3  
Extended Error log data structure  
An error log data structure shall be presented for each of the last four errors reported by the device.  
These error log data structure entries are viewed as a circular buffer. The fifth error shall create an  
error log structure that replaces the first error log data structure. The next error after that shall  
create an error log data structure that replaces the second error log structure, etc.  
Unused error log data structures shall be filled with zeros.  
Data format of each error log structure is shown below.  
Description  
Bytes Offset  
1st command data structure  
2nd command data structure  
3rd command data structure  
4th command data structure  
5th command data structure  
Error data structure  
18  
18  
18  
18  
18  
00h  
12h  
24h  
36h  
48h  
5Ah  
34  
124  
Table 76 Extended Error log data structure  
112  
   
5K320 SATA OEM Specification  
Command data structure:Data format of each command data structure is shown below.  
Description  
Bytes Offset  
Device Control register  
Features register (7:0) (see Note)  
Features register (15:8)  
Sector count register (7:0)  
Sector count register (15:8)  
Sector number register (7:0)  
Sector number register (15:8)  
Cylinder Low register (7:0)  
Cylinder Low register (15:8)  
Cylinder High register (7:0)  
Cylinder High register (15:8)  
Device register  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
Command register  
Reserved  
Timestamp (milliseconds from Power-on)  
18  
Note: bits (7:0) refer to the most recently written contents of the register. Bits (15:8) refer to the  
contents of the register prior to the most recent write to the register.  
Table 77 Command data structure  
Error data structure: Data format of error data structure is shown below.  
Description  
Bytes Offset  
Reserved  
Error register  
1
1
1
1
1
1
1
1
1
1
1
1
19  
1
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
1Fh  
20h  
Sector count register (7:0) (see Note)  
Sector count register (15:8) (see Note)  
Sector number register (7:0)  
Sector number register (15:8)  
Cylinder Low register (7:0)  
Cylinder Low register (15:8)  
Cylinder High register (7:0)  
Cylinder High register (15:8)  
Device register  
Status register  
Extended error data (vendor specific)  
State  
Life timestamp (hours)  
2
34  
Note: bits (7:0) refer to the contents if the register is read with bit 7 of the Device Control register  
cleared to zero. Bits (15:8) refer to the contents if the register is read with bit 7 of the Device Control  
register set to one.  
Table 78 Error data structure  
113  
   
5K320 SATA OEM Specification  
State shall contain a value indicating the state of the device when the command was issued to the  
device or the reset occurred as described below.  
Value  
x0h  
State  
Unknown  
x1h  
Sleep  
x2h  
Standby  
x3h  
Active/Idle  
x4h  
x5h-xAh  
xBh-xFh  
SMART Off-line or Self-test  
Reserved  
Vendor specific  
Note: The value of x is vendor specific.  
14.17.2.4  
Device error count  
This field shall contain the total number of errors attributable to the device that have been reported  
by the device during the life of the device. This count shall not include errors attributed to the  
receipt of faulty commands such as commands codes not implemented by the device or requests with  
invalid parameters or invalid addresses. If the maximum value for this field is reached the count  
shall remain at the maximum value when additional errors are encountered and logged.  
14.17.3 Extended Self-test log sector  
The following table defines the format of each of the sectors that comprise the Extended SMART  
self-test log.  
The Extended SMART self-test log sector shall support 48-bit and 28-bit addressing. All 28-bit  
entries contained in the SMART self-test log, defined in “Self-test log data structure” shall also be  
included in the Extended SMART self-test log with all 48-bit entries.  
Description  
Bytes Offset  
Self-test log data structure revision number  
Reserved  
1
1
1
1
26  
26  
00h  
01h  
02h  
03h  
04h  
1Eh  
Self-test descriptor index (7:0)  
Self-test descriptor index (15:8)  
Descriptor entry 1  
Descriptor entry 2  
...  
Descriptor entry 18  
Vendor specific  
Reserved  
26  
2
11  
1
1D8h  
1F2h  
1F4h  
1FFh  
Data structure checksum  
512  
Table 79 Extended Self-test log data structure  
These descriptor entries are viewed as a circular buffer. The nineteenth self-test shall create a  
descriptor entry that replaces descriptor entry 1. The next self-test after that shall create a  
descriptor entry that replaces descriptor entry 2, etc. All unused self-test descriptors shall be filled  
with zeros  
14.17.3.1  
Self-test log data structure revision number  
The value of this revision number shall be 01h.  
114  
 
5K320 SATA OEM Specification  
14.17.3.2  
Self-test descriptor index  
This indicates the most recent self-test descriptor. If there have been no self-tests, this is set to zero.  
Valid values for the Self-test descriptor index are 0 to 18.  
14.17.3.3  
Extended Self-test log descriptor entry  
The content of the self-test descriptor entry is shown below.  
Description  
Bytes Offset  
Self-test number  
1
1
2
1
1
1
1
1
1
00h  
01h  
02h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
Self-test execution status  
Power-on life timestamp in hours  
Self-test failure check point  
Failing LBA (7:0)  
Failing LBA (15:8)  
Failing LBA (23:16)  
Failing LBA (31:24)  
Failing LBA (39:32)  
Failing LBA (47:40)  
Vendor specific  
1
15  
26  
Table 80 Extended Self-test log descriptor entry  
14.17.4 Command Error  
The following table defines the format of the Command Error data structure.  
Byte  
7
6
5
4
3
2
1
0
0
NQ  
Rsv Rsv  
TAG  
1
2
Reserved  
Status  
3
Error  
4
LBA Low  
5
LBA Mid  
6
LBA High  
7
Device  
8
9
LBA Low Previous  
LBA Mid Previous  
10  
11  
LBA High Previous  
Reserved  
12  
Sector Count  
13  
Sector Count Previous  
Reserved  
Vendor Unique  
Data Structure Checksum  
14 – 255  
256 – 510  
511  
Table 81 Command Error information  
The TAG field (Byte 0 bits 4-0) contains the tag number corresponding to a queued command, if the  
NQ bit is cleared.  
The NQ field (Byte 0 bit 7) indicates whether the error condition was a result of a non-queued or not.  
If it is cleared, the error information corresponds to a queued command specified by the tag number  
indicated in the TAG field.  
The bytes 1 to 13 correspond to the contents of Shadow Register Block when the error was reported.  
115  
   
5K320 SATA OEM Specification  
The Data Structure Checksum (Byte 511) contains the 2’s complement of the sum of the first 511  
bytes in the data structure. The sum of all 512 bytes of the data structure will be zero when the  
checksum is correct.  
14.17.5 Phy Event Counter  
Phy Event Counters are a feature to obtain more information about Phy level events that occur on  
the interface. The counter values are not retained across power cycles. The counter values are  
preserved across COMRESET and software resets.  
14.17.5.1  
Counter Reset Mechanisms  
There are 2 mechanisms by which the host can explicitly cause the Phy counters to be reset. The  
first mechanism is to issue a BIST Activate FIS to the drive. The second mechanism uses the Read  
Log Ext command. When the drive receives a Read Log Ext command for log page 11h and bit 0 in  
Feature register is set to one, the drive returns the current counter values for the command and then  
resets all Phy event counter values.  
14.17.5.2  
Counter Identifiers  
Each counter begins with a 16-bit identifier. The following table defines the counter value for each  
identifier.  
For all counter descriptions, “transmitted” refers to items sent by the drive to the host and “received”  
refers to items received by the drive from the host.  
Bits 14:12 of the counter identifier convey the number of significant bits that counter uses. All  
counter values consumes a multiple of 16-bits. The valid values for bit 14:12 and the corresponding  
counter size are:  
1h  
2h  
3h  
4h  
16-bit counter  
32-bit counter  
48-bit counter  
64-bit counter  
Description  
Identifier  
(Bits 11:0)  
000h  
No counter value; marks end of counters in the page  
Command failed due to ICRC error  
001h  
009h  
00Ah  
00Bh  
Transfer from drive PhyRdy to drive PhyNRdy  
Signature D2H register FISes sent due to a COMRESET  
CRC errors within the FIS (received)  
00Dh  
Non-CRC errors within the FIS (received)  
Table 82 Phy Event Counter Identifier  
14.17.5.3  
Read Log Ext Log Page 11h  
The following table defines the format of the Phy Event counter data structure.  
116  
 
5K320 SATA OEM Specification  
Byte  
7
6
5
4
3
2
1
0
0
1
2
3
00h  
00h  
00h  
00h  
4
5
Counter 0001h Identifier  
6
7
Counter 0001h Value  
8
9
Counter 0009h Identifier  
Counter 0009 Value  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26 - 510  
511  
Counter 000Ah Identifier  
Counter 000Ah Value  
Counter 000Bh Identifier  
Counter 000Bh Value  
Counter 000Dh Identifier  
Counter 000Dh Value  
00h  
00h  
Reserved ( 00h )  
Data Structure Checksum  
Table 83 Phy Event Counter information  
The Data Structure Checksum (Byte 511) contains the 2’s complement of the sum of the first 511  
bytes in the data structure. The sum of all 512 bytes of the data structure will be zero when the  
checksum is correct.  
117  
 
5K320 SATA OEM Specification  
14.18 Read Multiple (C4h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
1 1 0 0 0 1 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 84 Read Multiple Command (C4h)  
The Read Multiple command reads one or more sectors of data from disk media, then transfers the  
data from the device to the host.  
The sectors are transferred through the Data Register 16 bits at a time. Command execution is  
identical to the Read Sectors command except that an interrupt is generated for each block (as  
defined by the Set Multiple command) instead of for each sector.  
Output Parameters To The Device  
Sector Count  
LBA Low  
LBA High/Mid  
H
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors  
will be transferred.  
The sector number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 0 - 7. (L=1)  
The cylinder number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)  
The head number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 24 - 27. (L=1)  
Input Parameters From The Device  
Sector Count  
LBA Low  
LBA High/Mid  
H
The number of requested sectors not transferred. This will be zero, unless an  
unrecoverable error occurs.  
The sector number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
The cylinder number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 8-15 (Mid), 16-23 (High). (L=1)  
The head number of the last transferred sector. (L=0)  
LBA mode, this register contains current LBA bits 24 - 27. (L=1)  
118  
   
5K320 SATA OEM Specification  
14.19 Read Multiple Ext (29h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
0
1
0
0
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
V
0
0
0
V
0
V
-
0
0
V
Table 85 Read Multiple Ext Command (29h)  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of sectors to be transferred low order, bits (7:0).  
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector  
Count register is specified, then 65,536 sectors will be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0)  
LBA (31:24)  
LBA (15:8)  
LBA (39:32)  
LBA (23:16)  
LBA (47:40)  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24)of the address of the first unrecoverable error.  
LBA (15:8)of the address of the first unrecoverable error.  
LBA (39:32)of the address of the first unrecoverable error.  
LBA (23:16)of the address of the first unrecoverable error.  
LBA (47:40)of the address of the first unrecoverable error.  
119  
   
5K320 SATA OEM Specification  
14.20 Read Native Max Address (F8h)  
Block Output Registers Command  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
-
-
L
-
-
-
- H H H H  
Command  
1 1 1 1 1 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 86 Read Native Max Address Command (F8h)  
This command returns the native max LBA/CYL of HDD which is not affected by Set Max Address  
command.  
The 48-bit native max address is greater than 268,435,455, the Read Native Max Address command  
return a value of 268,435,455.  
Output Parameters To The Device  
L
D
-
LBA mode.Indicates the addressing mode.L=0 specifies CHS mode and L=1 does LBA  
addressing mode.  
The device number bit. Indicates that the device number bit of the Device Register  
should be specified. D=0 selects the master device and D=1 selects the slave device.  
Indicates that the bit is not used.  
Input Parameters From The Device  
LBA Low  
In LBA mode, this register contains native max LBA bits 0 - 7. (L=1)  
In CHS mode, this register contains native max LBA Low. (L=0)  
LBA High/Mid  
120  
   
5K320 SATA OEM Specification  
14.21 Read Native Max Address Ext (27h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
-
-
-
-
-
-
-
-
-
-
-
-
0
6
-
5
-
-
-
-
-
-
-
-
-
-
-
-
-
1
4
-
-
-
-
-
-
-
-
-
-
-
-
-
0
3
-
-
-
-
-
-
-
-
-
-
-
-
-
0
2
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
1
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
Current  
-
...See Below...  
Previous  
-
Sector Count Current  
Previous  
-
Sector Count HOB=0  
HOB=1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
-
LBA Low  
LBA Mid  
LBA High  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
-
-
-
-
-
Device  
1
0
Device  
Status  
-
-
-
-
-
-
-
-
Command  
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
0
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 87 Read Native Max Address Ext Command (29h)  
This command returns the native max LBA of HDD which is not effected by Set Max Address Ext  
command.  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the Native max address.  
LBA (31:24)of the address of the Native max address.  
LBA (15:8)of the address of the Native max address.  
LBA (39:32)of the address of the Native max address.  
LBA (23:16)of the address of the first Native max address.  
LBA (47:40)of the address of the first Native max address.  
121  
   
5K320 SATA OEM Specification  
14.22 Read Sector(s) (20h/21h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
0 0 1 0 0 0 0 R  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 88 Read Sector(s) Command (20h/21h)  
The Read Sector(s) command reads one or more sectors of data from disk media, then transfers the  
data from the device to the host.  
The sectors are transferred through the Data Register 16 bits at a time.  
If an uncorrectable error occurs, the read will be terminated at the failing sector.  
Output Parameters To The Device  
Sector Count  
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors  
will be transferred.  
LBA Low  
The sector number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 0 - 7. (L=1)  
The cylinder number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)  
The head number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 24 - 27. (L=1)  
The retry bit, but this bit is ignored.  
LBA High/Mid  
H
R
Input Parameters From The Device  
Sector Count  
The number of requested sectors not transferred. This will be zero, unless an  
unrecoverable error occurs.  
LBA Low  
The sector number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
The cylinder number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
LBA High/Mid  
H
The head number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 24 - 27. （L=1）  
122  
   
5K320 SATA OEM Specification  
14.23 Read Sector(s) Ext (24h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
0
0
1
0
0
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
V
0
0
0
V
0
V
-
0
0
V
Table 89 Read Sector(s) Ext Command (24h)  
The Read Sector(s) Ext command reads from 1 to 65,536 sectors of data from disk media, then  
transfers the data from the device to the host.  
The sectors are transferred through the Data Register 16 bits at a time.  
If an uncorrectable error occurs, the read will be terminated at the failing sector.  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of sectors to be transferred low order, bits (7:0).  
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector  
Count register is specified, then 65,536 sectors will be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0)  
LBA (31:24)  
LBA (15:8)  
LBA (39:32)  
LBA (23:16)  
LBA (47:40)  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24)of the address of the first unrecoverable error.  
LBA (15:8)of the address of the first unrecoverable error.  
LBA (39:32)of the address of the first unrecoverable error.  
LBA (23:16)of the address of the first unrecoverable error.  
LBA (47:40)of the address of the first unrecoverable error.  
123  
   
5K320 SATA OEM Specification  
14.24 Read Verify Sector(s) (40h/41h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
0 0 1 0 0 0 0 R  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 90 Read Verify Sector(s) Command (40h/41h)  
The Read Verify Sector(s) verifies one or more sectors on the device. No data is transferred to the  
host.  
The difference of Read Sector(s) command and Read Verify Sector(s) command is whether the data is  
transferred to the host or not.  
If an uncorrectable error occurs, the read verify will be terminated at the failing sector.  
Output Parameters To The Device  
Sector Count  
The number of continuous sectors to be verified. If zero is specified, then 256 sectors  
will be verified.  
LBA Low  
The sector number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 0 - 7. (L=1)  
The cylinder number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)  
The head number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 24 - 27. (L=1)  
The retry bit, but this bit is ignored.  
LBA High/Mid  
H
R
Input Parameters From The Device  
Sector Count  
The number of requested sectors not verified. This will be zero, unless an unrecoverable  
error occurs.  
LBA Low  
The sector number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
The cylinder number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
LBA High/Mid  
H
The head number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)  
124  
   
5K320 SATA OEM Specification  
14.25 Read Verify Sector(s) Ext (42h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
0
0
0
1
0
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
V
0
0
0
V
0
V
-
0
0
V
Table 91 Read Verify Sector(s) Ext Command (42h)  
The Read Verify Sector(s) Ext verifies one or more sectors on the device. No data is transferred to the  
host.  
The difference between the Read Sector(s) Ext command and the Read Verify Sector(s) Ext command  
is whether the data is transferred to the host or not.  
If an uncorrectable error occurs, the Read Verify Sector(s) Ext will be terminated at the failing  
sector.  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of sectors to be transferred low order, bits (7:0).  
The number of sectors to be transferred high order, bits (15:8). If 0000h in the Sector  
Count register is specified, then 65,536 sectors will be verified.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0)  
LBA (31:24)  
LBA (15:8)  
LBA (39:32)  
LBA (23:16)  
LBA (47:40)  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24)of the address of the first unrecoverable error.  
LBA (15:8)of the address of the first unrecoverable error.  
LBA (39:32)of the address of the first unrecoverable error.  
LBA (23:16)of the address of the first unrecoverable error.  
LBA (47:40)of the address of the first unrecoverable error.  
125  
   
5K320 SATA OEM Specification  
14.26 Recalibrate (1xh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
0 0 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
V
0
0
V
0
V
-
0
0
V
Table 92 Recalibrate Command (1xh)  
The Recalibrate command moves the read/write heads from anywhere on the disk to cylinder 0.  
If the device cannot reach cylinder 0, T0N (Track 0 Not Found) will be set in the Error Register.  
126  
   
5K320 SATA OEM Specification  
14.27 Security Disable Password (F6h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 1 1 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 93 Security Disable Password Command (F6h)  
The Security Disable Password command disables the security mode feature ( device lock function).  
The Security Disable Password command requests a transfer of a single sector of data from the host  
including information specified in the following table. Then the device checks the transferred  
password. If the User Password or Master Password matches the given password, the device disables  
the security mode feature (device lock function). This command does not change the Master  
Password which may be re-activated later by setting User Password. This command should be  
executed in device unlock mode.  
Word  
00  
Description  
Control word  
bit 0  
: Identifier (1-Mater, 0-User)  
: Reserved  
bit 1-15  
01-16  
Password  
Reserved  
(32 bytes)  
17-255  
Table 94 Password Information for Security Disable Password command  
The device will compare the password sent from this host with that specified in the control word.  
Identifier  
Zero indicates that the device should check the supplied password against the user password  
stored internally. One indicates that the device should check the given password against the  
master password stored internally.  
127  
     
5K320 SATA OEM Specification  
14.28 Security Erase Prepare (F3h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 0 1 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 95 Security Erase Prepare Command (F3h)  
The Security Erase Prepare Command must be issued immediately before the Security Erase Unit  
Command to enable device erasing and unlocking.  
The Security Erase Prepare Command must be issued immediately before the Format Unit  
Command. This command is to prevent accidental erasure of the device.  
This command does not request to transfer data.  
128  
   
5K320 SATA OEM Specification  
14.29 Security Erase Unit (F4h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 1 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 96 Security Erase Unit Command (F4h)  
The Security Erase Unit command initializes all user data sectors, then disables the device lock  
function.  
Note that the Security Erase Unit command initializes from LBA 0 to Native Max LBA. Host Max  
LBA set by Initialize Drive Parameter or Set Max Address command is ignored. So the protected  
area by Set Max Address command is also initialized.  
This command requests to transfer a single sector data from the host including information specified  
in the following table.  
If the password does not match then the device rejects the command with an Aborted error.  
Word  
00  
Description  
Control word  
Identifier (1-Mater, 0-User)  
bit 0  
bit 1  
Erase mode (1-Enhanced Erase, 0-Normal Erase)  
bit 2-15  
Reserved  
01-16  
Password  
Reserved  
(32 bytes)  
17-255  
Table 97 Erase Unit Information  
Identifier  
Zero indicates that the device should check the supplied password against the user password  
stored internally. One indicates that the device should check the given password against the  
master password stored internally.  
The Security Erase Unit command erases all user data and disables the security mode feature (device lock function).  
So after completing this command, all user data will be initialized to zero with write operation. At this time, it is not  
verified with read operation whether the sector of data is initialized correctly. Also, the defective sector information  
and the reassigned sector information for the device are not updated. The security erase prepare command should be  
completed immediately prior to the Security Erase Unit command. If the device receives a Security Erase Unit  
command without a prior Security Erase Prepare command the device aborts the security erase unit command.  
129  
     
5K320 SATA OEM Specification  
This command disables the security mode feature (device lock function), however the master  
password is still stored internally within the device and may be re-activated later when a new user  
password is set. If you execute this command on disabling the security mode feature (device lock  
function), the password sent by the host is NOT compared with the password stored in the device for  
both the Master Password and the User Password, and then the device only erases all user data.  
The execution time of this command in Normal Erase mode is shown below.  
HTS543232L9SA00 / HTS543232L9A300  
HTS543225L9SA00 / HTS543225L9A300  
HTS543216L9SA00 / HTS543216L9A300  
HTS543212L9SA00 / HTS543212L9A300  
HTS543280L9SA00 / HTS543280L9A300  
126 min  
100min  
66 min  
50 min  
36 min  
The execution time of this command in Enhanced Erase mode is shown below.  
HTS543232L9SA00 / HTS543232L9A300  
HTS543225L9SA00 / HTS543225L9A300  
HTS543216L9SA00 / HTS543216L9A300  
HTS543212L9SA00 / HTS543212L9A300  
HTS543280L9SA00 / HTS543280L9A300  
128 min  
102 min  
68 min  
52 min  
38 min  
For the Bulk Encryption model, the execution time in Enhanced Erase Mode is less than 1 minute.  
130  
5K320 SATA OEM Specification  
14.30 Security Freeze Lock (F5h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 1 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 98 Security Freeze Lock Command (F5h)  
The Security Freeze Lock Command allows the device to enter frozen mode immediately.  
After this command is completed, the command which updates Security Mode Feature (Device Lock  
Function) is rejected.  
Frozen mode is quit only by Power off.  
The following commands are rejected when the device is in frozen mode. For detail, refer to “Table 35  
Command table for device lock operation” on Page 62-64.  
Security Set Password  
Security Unlock  
Security Disable Password  
Security Erase Unit  
131  
   
5K320 SATA OEM Specification  
14.31 Security Set Password (F1h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 0 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 99 Security Set Password Command (F1h)  
The Security Set Password command enables security mode feature (device lock function), and sets  
the master password or the user password.  
The security mode feature (device lock function) is enabled by this command, and the device is not  
locked immediately. The device is locked after next COMRESET with Software Setting  
Preservation disabled or power on reset. When the MASTER password is set by this command, the  
master password is registered internally, but the device is NOT locked after next power on reset.  
This command requests a transfer of a single sector of data from the host including the information  
specified in the following table.  
The data transferred controls the function of this command.  
Word  
00  
Description  
Control word  
bit 0  
: Identifier (1-Mater, 0-User)  
bit 1-7  
bit 8  
: Reserved  
: Security level (1-Maximum, 0-High)  
: Reserved  
bit 1-15  
01-16  
17-18  
Password (32 bytes)  
Master Password Revision Code  
(valid if Word 0 bit 0 = 1)  
19-255  
Reserved  
Table 100 Security Set Password Information  
Identifier  
Zero indicates that the device should check the supplied password against the user password  
stored internally. One indicates that the device should check the given password against the  
master password stored internally.  
132  
     
5K320 SATA OEM Specification  
Security Level  
Zero indicates High level, one indicates Maximum level. If the host sets High level and the  
password is forgotten, then the Master Password can be used to unlock the device. If the  
host sets Maximum level and the user password is forgotten, only an Security Erase  
Prepare/Security Unit command can unlock the device and all data will be lost.  
The text of the password - all 32 bytes are always significant.  
Password  
Master Password  
Revision Code  
The Revision Code field is set with Master password. If Identifier is User, the Revision  
Code is not set. The Revision Code field is returned in Identify Device word 92. The valid  
Revision Codes are 0000h to FFFDh. Default Master Password Revision Code is FFFEh.  
FFFFh is reserved.  
The setting of the Identifier and Security level bits interact as follows.  
Identifier=User / Security level = High  
The password supplied with the command will be saved as the new user password. The security  
mode feature (lock function) will be enabled from the next power on. The file may then be unlocked  
by either the user password or the previously set master password.  
Identifier=Master / Security level = High  
This combination will set a master password but will NOT enable the security mode feature (lock  
function).  
Identifier=User / Security level = Maximum  
The password supplied with the command will be saved as the new user password. The security  
mode feature (lock function) will be enabled from the next power on. The file may then be unlocked  
by only the user password. The master password previously set is still stored in the file but may  
NOT be used to unlock the device.  
Identifier=Master / Security level = Maximum  
This combination will set a master password but will NOT enable the security mode feature (lock  
function).  
133  
5K320 SATA OEM Specification  
14.32 Security Unlock (F2h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 1 0 0 1 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
V
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 101 Security Unlock Command (F2h)  
This command unlocks the password and causes the device to enter device unlock mode. If  
COMRESET with Software Setting Preservation disable or power on reset is done without executing  
the Security Disable Password command after this command is completed, the device will be in  
device lock mode. The password has not been changed yet.  
The Security Unlock command requests to transfer a single sector of data from the host including  
information specified in the following table.  
If the Identifier bit is set to master and the file is in high security mode then the password supplied  
will be compared with the stored master password. If the file is in maximum security mode then the  
security unlock will be rejected.  
If the Identifier bit is set to user, then the file compares the supplied password with the stored user  
password.  
If the password compare fails then the device returns an abort error to the host and decrements the  
unlock attempt counter. This counter is initially set to 5 and is decremented for each password  
mismatch. When this counter reaches zero then all password protected commands are rejected until  
a power off.  
Word  
00  
Description  
Control word  
: Identifier (1-Master, 0-User)  
: Reserved  
bit 0  
bit 1-15  
01-16  
Password  
Reserved  
(32 bytes)  
17-255  
Table 102 Security Unlock Information  
Identifier  
Zero indicates that device regards Password as User Password. One indicates that device  
regards Password as Master Password.  
The user can detect if the attempt to unlock the device has failed due to a mismatched password as this is the only  
reason that an abort error will be returned by the file AFTER the password information has been sent to the device.  
If an abort error is returned by the device BEFORE the password data has been sent to the file then another  
problem exists.  
134  
     
5K320 SATA OEM Specification  
14.33 Seek (7xh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
0 1 1 1  
-
-
-
-
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 103 Seek Command (7xh)  
The Seek command initiates a seek to the designated track and selects the designated head. The device need not  
be formatted for a seek to execute properly.  
Output Parameters To The Device  
LBA Low  
LBA High/Mid  
In LBA mode, this register specifies LBA address bits 0 - 7 for seek. (L=1)  
The cylinder number of the seek.  
In LBA mode, this register specifies LBA address bits 8 - 15 (Mid), 16 - 23 (High) for  
seek. (L=1)  
H
The head number of the seek.  
In LBA mode, this register specifies LBA address bits 24 - 27 for seek. (L=1)  
Input Parameters From The Device  
LBA Low  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
LBA High/Mid  
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
H
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)  
135  
   
5K320 SATA OEM Specification  
14.34 Sense Condition (F0h : vendor specific)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
0 0 0 0 0 0 0 1  
Error  
...See Below...  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- N  
-
-
-
-
-
-
Command  
1 1 1 1 0 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
V
0
V
0
0
V
V
V
-
V
-
0
V
Table 104 Sense Condition Command (F0h)  
The Sense Condition command is used to sense temperature in a device.  
This command is executable without spinning up even if a device is started with No Spin Up option.  
If this command is issued at the temperature out of range which is specified for operating condition,  
the error might be returned with IDN bit 1.  
Output Parameters To The Device  
Feature  
The Feature register must be set to 01h. All other value are rejected with  
setting ABORT bit in status register.  
Input Parameters From The Device  
Sector Count  
The Sector Count register contains result value.  
Value  
Description  
00h  
Temperature is equal to or lower than -20 degC  
Temperature is (Value / 2 - 20) deg C  
Temperature is higher than 107 degC  
01h-FEh  
FFh  
Not recommendable condition for start up. If over stressed condition is  
detected, this bit will be set to one.  
N
136  
   
5K320 SATA OEM Specification  
14.35 Set Features (EFh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
V V V V V V V V  
Note.1  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 1 1 1 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 105 Set Features Command (EFh)  
The Set Feature command is to establish the following parameters which affect the execution of  
certain features as shown in below table.  
ABT will be set to 1 in the Error Register if the Feature register contains any undefined values.  
After power on reset, the device is set to the following features as default.  
Write cache  
ECC bytes  
Read look-ahead  
Reverting to power on defaults  
Device-initiated interface power state  
transition  
: Enable  
: 4 bytes  
: Enable  
: Disable  
: Disable  
Software setting preservation  
: Enable  
Output Parameters To The Device  
Feature  
02H  
03H  
05H  
06H  
07H  
10H  
55H  
66H  
82H  
85H  
86H  
90H  
AAH  
CCH  
Destination code for this command  
Enable write cache (Note.2)  
Set transfer mode based on value in sector count register  
Enable Advanced Power Management  
Enable Power-Up in Standby feature set  
Power-Up in Standby feature set device spin-up  
Enable use of Serial ATA feature  
Disable read look-ahead feature  
Disable reverting to power on defaults  
Disable write cache  
Disable Advanced Power Management (Note.3)  
Disable Power-UP in Standby feature set  
Disable use of Serial ATA feature  
Enable read look-ahead feature  
Enable reverting to power on defaults  
Note 1.  
137  
   
5K320 SATA OEM Specification  
When Feature register is 03h (=Set Transfer mode), the Sector Count Register specifies the transfer  
mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode  
value.  
bits  
bits  
(7:3)  
00000  
(2:0)  
000  
PIO Default Transfer Mode  
PIO Default Transfer Mode, Disable IORDY  
00000  
001  
PIO Flow Control Transfer Mode x  
Multiword DMA mode x  
Ultra DMA mode x  
00001  
00100  
01000  
nnn  
nnn  
nnn  
(nnn=000,001,010,011,100)  
(nnn=000,001,010)  
(nnn=000,001,010,011,100,101)  
When Feature register is 05h (=Enable Advanced Power Management), the Sector Count Register specifies the  
Advanced Power Management level.  
C0h - FEh ...  
80h - BFh ...  
01h - 7Fh ...  
00h, FFh ...  
The deepest Power Saving mode is Active Idle  
The deepest Power Saving mode is Low power Idle  
The deepest Power Saving mode is Standby  
Aborted  
Note 2.  
If the number of auto reassigned sectors reaches the device’s reassignment capacity, the write cache  
function will be automatically disabled. Although the device still accepts the Set Features  
command (with Feature register = 02h) without error, the write cache function will remain disabled.  
For current write cache function status, please refer to the Identify Device Information(129word)  
by Identify Device command. Power off must not be done in 5 seconds after write command  
completion when write cache is enabled.  
Note 3.  
When Feature register is 85h (=Disable Advanced Power Management), the deepest Power Saving  
mode becomes Active Idle.  
Note 4.  
When the Feature register is set to 10h or 90h, the value set to the Sector Count register specifies the  
specific Serial ATA feature to enable or disable.  
When the Feature register is set to 10h or 90h, the value set to the Sector Count register specifies the  
specific Serial ATA feature to enable or disable.  
Sector count value  
Description  
Non-zero buffer offset in DMA setup FIS  
DMA setup FIS auto-activate optimization  
Device-initiated interface power state transitions  
Guaranteed in-order data delivery  
01h  
02h  
03h  
04h  
06h  
Software Settings Preservation  
138  
5K320 SATA OEM Specification  
14.36 Set Max Address (F9h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
V V V V V V V V  
- B  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
1 1 1 1 1 0 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 106 Set Max Address Command (F9h)  
The Set Max Address command overwrites the max LBA/CYL of HDD in a range of actual device  
capacities. The device receives this command, all accesses beyond that LBA/CYL are rejected with  
setting ABORT bit in status register. Identify device command and Identify device DMA command  
returns the LBA/CYL which is set via this command as a default value.  
This command implement SET Max security extension commands as subcommands. But regardless  
of Feature register value, the case this command is immediately preceded by a Read Native Max  
Address command, it is interpreted as a Set Max Address command.  
The Read Native Max Address command should be issued and completed immediately prior to  
issuing Set Max Address command. Otherwise this command is interpreted as a Set Max security  
extension command which is destinated by feature register. If Set Max security mode is in the  
Locked or Frozen, the Set Max Address command is aborted.  
For more information, see “12.10.2 Set Max security extension commands” on Page 66.  
In CHS mode, LBA High, LBA Mid specify the max cylinder number. The Head number of Device  
and LBA Low are ignored. The default value(See default CHS in Identify device information) is used  
for that.  
In LBA mode, the Head number of Device, LBA High, LBA Mid and LBA Low specify the max LBA.  
This command sets this LBA as the max LBA of the device.  
After a successful command completion, Identify Device response words (61:60) shall reflect the  
maximum address set with this command.  
If the 48-bit Address feature set is supported, the value placed in Identify Device response words  
(103:100) shall be the same as the value placed in words (61:60). However, if the device contains  
greater than 268,435,455 sectors, the capacity addressable with 28-bit commands, and the address  
requested is 268,435,455, the max address shall be changed to the native maximum address, the  
value placed in words (61:60) shall be 268,435,455 and the value placed in words (103:100) shall be  
the native maximum address.  
If a host protected area has been established by a Set Max Address Ext command, the device shall  
return command aborted.  
Output Parameters To The Device  
Feature  
Destination code for this command  
01h  
SET MAX SET PASSWORD  
139  
   
5K320 SATA OEM Specification  
02h  
03h  
04h  
SET MAX LOCK  
SET MAX UNLOCK  
SET MAX FREEZE LOCK  
When the Set Max ADDRESS command is executed, this register is  
ignored.  
B
Option bit for selection whether nonvolatile or volatile. B=0 is volatile  
condition. When B=1, MAX LBA/CYL which is set by Set Max  
ADDRESS command is preserved by POR. When B=0, MAX LBA/CYL  
which is set by Set Max ADDRESS command will be lost by POR.  
in LBA mode, this register contains LBA bits 0 - 7 which is to be  
input.(L=1)  
LBA Low  
In CHS mode, this register is ignored. (L=0)  
LBA High/Mid  
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High)  
which is to be set. (L=1)  
In CHS mode, this register contains max cylinder number which is to be  
set. (L=0)  
H
L
In LBA mode, this register contains LBA bits 24 - 27 which is to be  
input.(L=1)  
In CHS mode, this register is ignored. (L=0)  
LBA mode.Indicates the addressing mode.L=0 specifies CHS mode and  
L=1 does LBA addressing mode.  
Input Parameters From The Device  
LBA Low  
In LBA mode, this register contains Adjusted max LBA bits 0 - 7.(L=1)  
In CHS mode, this register contains max LBA Low(= 63). (L=0)  
In LBA mode, this register contains Adjusted max LBA bits 8 - 15 (Mid),  
16 - 23 (High). (L=1)  
LBA High/Mid  
In CHS mode, this register contains max cylinder number which is set.  
(L=0)  
H
In LBA mode, this register contains Adjusted max LBA bits 24 - 27. (L=1)  
In CHS mode, this register contains max head number(= 15).(L=0)  
140  
5K320 SATA OEM Specification  
14.37 Set Max Address Ext (37h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
-
-
-
-
-
6
-
-
-
-
-
-
5
-
-
-
-
-
-
4
-
-
-
-
-
-
3
-
-
-
-
-
-
2
-
-
-
-
-
-
1
-
-
-
-
-
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
Current  
-
...See Below...  
Previous  
-
Sector Count Current  
Previous  
B
-
Sector Count HOB=0  
HOB=1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
1
0
1
1
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
0
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 107 Set Max Address Ext Command (37h)  
This command is immediately preceded by a Read Native Max Address Ext command.  
This command overwrites the maximum number of Address of HDD in a range of actual device  
capacity. Once device receives this command, all accesses beyond that Address are rejected with  
setting ABORT bit in status register.  
When the address requested is greater than 268,435,455, words (103:100) shall be modified to reflect  
the requested value, but words (61:60) shall not modified. When the address requested is equal to or  
less than 268,435,455, words (103:100) shall be modified to reflect the requested value, and words  
(61:60) shall also be modified.  
If this command is not supported, the maximum value to be set exceeds the capacity of the device, a  
host protected area has been established by a Set Max Address command, the command is not  
immediately preceded by a Read Native Max Address Ext command, or the device is in the Set Max  
Locked or Set Max Frozen state, the device shall return command aborted.  
The device returns the command aborted for a second non-volatile Set Max Address Ext command  
until next power on.  
Output Parameters To The Device  
B
Option bit for selection whether nonvolatile or volatile. B=0 is volatile  
condition. When B=1, Max Address which is set by Set Max Address  
Ext command is preserved by POR. When B=0, Max Address which is  
set by Set Max Address Ext command will be lost by POR.  
Set Max LBA (7:0).  
LBA Low Current  
LBA Low Previous  
Set Max LBA (31:24).  
LBA Mid Current  
Set Max LBA (15:8).  
LBA Mid Previous  
Set Max LBA (39:32).  
LBA High Current  
Set Max LBA (23:16).  
LBA High Previous  
Input Parameters From The Device  
LBA Low (HOB=0)  
Set Max LBA (47:40).  
Set Max LBA (7:0).  
141  
   
5K320 SATA OEM Specification  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
Set Max LBA (31:24).  
Set Max LBA (15:8).  
Set Max LBA (39:32).  
Set Max LBA (23:16).  
Set Max LBA (47:40).  
142  
5K320 SATA OEM Specification  
14.38 Set Multiple (C6h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 0 0 0 1 1 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 108 Set Multiple Command (C6h)  
The Set Multiple command enables the device to perform Read and Write Multiple commands and  
establishes the block size for these commands. The block size is the number of sectors to be  
transferred for each interrupt.  
The default block size after power up is 0, and Read Multiple and Write Multiple commands are  
disabled.  
If an invalid block size is specified, an Abort error will be returned to the host, and Read Multiple  
and Write Multiple commands will be disabled.  
Output Parameters To The Device  
Sector Count  
The block size to be used for Read Multiple and Write Multiple commands. Valid  
block sizes can be selected from 0, 1, 2, 4, 8 or 16. If 0 is specified, then Read Multiple  
and Write Multiple commands are disabled.  
143  
   
5K320 SATA OEM Specification  
14.39 Sleep (E6h/99h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 1 1 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 109 Sleep Command (E6h/99h)  
This command is the only way to cause the device to enter Sleep Mode.  
When this command is issued, the device confirms the completion of the cached write commands.  
Then the device is spun down, and the interface becomes inactive. The only way to recover from  
Sleep Mode is with a software reset or a COMRESET.  
If the device is already spun down, the spin down sequence is not executed.  
144  
   
5K320 SATA OEM Specification  
14.40 S.M.A.R.T Function Set (B0h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
V V V V V V V V  
V V V V V V V V  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0 1 0 0 1 1 1 1  
1 1 0 0 0 0 1 0  
-
-
-
-
-
-
-
-
Command  
1 0 1 1 0 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 110 S.M.A.R.T. Function Set Command (B0h)  
The S.M.A.R.T. Function Set command provides access to Attribute Values, Attribute Thresholds  
and other low level subcommands that can be used for logging and reporting purposes and to  
accommodate special user needs. The S.M.A.R.T. Function Set command has several separate  
subcommands which are selectable via the device’s Features Register when the S.M.A.R.T. Function  
Set command is issued by the host.  
14.40.1 S.M.A.R.T. Sub commands  
In order to select a subcommand the host must write the subcommand code to the device’s Features  
Register before issuing the S.M.A.R.T. Function Set command. The subcommands and their  
respective codes are listed below.  
Code  
D0h  
D1h  
D2h  
D3h  
D4h  
D5h  
D6h  
D8h  
D9h  
DAh  
DBh  
Subcommand  
S.M.A.R.T. Read Attribute Values  
S.M.A.R.T. Read Attribute Thresholds  
S.M.A.R.T. Enable/disable Attribute Autosave  
S.M.A.R.T. Save Attribute Values  
S.M.A.R.T. Execute Off-line Immediate  
S.M.A.R.T. Read Log Sector  
S.M.A.R.T. Write Log Sector  
S.M.A.R.T. Enable Operations  
S.M.A.R.T. Disable Operations  
S.M.A.R.T. Return Status  
S.M.A.R.T. Enable/Disable Automatic Off-Line  
S.M.A.R.T. Read Attribute Values (Subcommand D0h)  
This subcommand returns the device’s Attribute Values to the host. Upon receipt of the S.M.A.R.T.  
Read Attribute Values subcommand from the host, the device saves any updated Attribute Values to  
the Attribute Data sectors, and then waits for the host to transfer the 512 bytes of Attribute Value  
information from the device.  
145  
   
5K320 SATA OEM Specification  
S.M.A.R.T. Read Attribute Thresholds (Subcommand  
D1h)  
This subcommand returns the device’s Attribute Thresholds to the host. Upon receipt of the  
S.M.A.R.T. Read Attribute Thresholds subcommand from the host, the device reads the Attribute  
Thresholds from the Attribute Threshold sectors and then waits for the host to transfer the 512  
bytes of Attribute Thresholds information from the device.  
S.M.A.R.T. Enable/Disable Attribute Autosave  
(Subcommand D2h)  
This subcommand enables and disables the attribute autosave feature of the device. The S.M.A.R.T.  
Enable/Disable Attribute Autosave subcommand allows the device to automatically save its updated  
Attribute Values to the Attribute Data Sector at the timing of the first transition to Active idle mode  
after 30 minutes since the last saving of Attribute Values; this subcommand causes the autosave  
feature to be disabled. The state of the Attribute Autosave feature (either enabled or disabled) will  
be preserved by the device across power cycle.  
A value of 00h written by the host into the device’s Sector Count Register before issuing the  
S.M.A.R.T. Enable/Disable Attribute Autosave subcommand will cause this feature to be disabled.  
Disabling this feature does not preclude the device from saving Attribute Values to the Attribute  
Data sectors during some other normal operation such as during a power-up or power-down.  
A value of F1h written by the host into the device’s Sector Count Register before issuing the  
S.M.A.R.T. Enable/Disable Attribute Autosave subcommand will cause this feature to be enabled.  
Any other non-zero value written by the host into this register before issuing the S.M.A.R.T.  
Enable/Disable Attribute Autosave subcommand will not change the current Autosave status but the  
device will respond with the error code specified in “Table 124 S.M.A.R.T. Error Codes” on Page 159.  
The S.M.A.R.T. Disable Operations subcommand disables the autosave feature along with the  
device’s S.M.A.R.T. operations.  
Upon the receipt of the subcommand from the host the device enables or disables the Autosave  
feature.  
S.M.A.R.T. Save Attribute Values (Subcommand D3h)  
This subcommand causes the device to immediately save any updated Attribute Values to the  
device’s Attribute Data sector regardless of the state of the Attribute Autosave feature. Upon receipt  
of the S.M.A.R.T. Save Attribute Values subcommand from the host, the device writes any updated  
Attribute Values to the Attribute Data sector.  
S.M.A.R.T. Execute Off-line Immediate (Subcommand  
D4h)  
This subcommand causes the device to immediately initiate the set of activities that collect Attribute  
data in an off-line mode (off-line routine) or execute a self-test routine in either captive or off-line  
mode.  
The LBA Low register shall be set to specify the operation to be executed.  
LBA Low  
Operation to be executed  
0
1
2
3
Execute S.M.A.R.T. off-line data collection routine immediately  
Execute S.M.A.R.T. Short self-test routine immediately in off-line mode  
Execute S.M.A.R.T. Extended self-test routine immediately in off-line mode  
Reserved  
4
Execute SMART Selective self-test routine immediately in off-line mode  
Abort off-line mode self-test routine  
Reserved  
Execute S.M.A.R.T. Short self-test routine immediately in captive mode  
Execute S.M.A.R.T. Extended self-test routine immediately in captive mode  
127  
128  
129  
130  
146  
5K320 SATA OEM Specification  
131  
132  
Reserved  
Execute SMART selective self-test routine immediately in captive mode  
Off-line mode: The device executes command completion before executing the specified routine.  
During execution of the routine the device will not set BSY nor clear DRDY. If the device is in the  
process of performing its routine and is interrupted by a new command from the host, the device will  
abort or suspend its routine and service the host within two seconds after receipt of the new  
command. After servicing the interrupting command, the device will resume its routine  
automatically or not start its routine depending on the interrupting command.  
Captive mode: When executing self-test in captive mode, the device sets BSY to one and executes the  
specified self-test routine after receipt of the command. At the end of the routine, the device sets the  
execution result in the Self-test execution status byte and ATA registers as below and executes  
command completion.  
Status  
Error  
LBA Mid  
LBA High  
Set ERR to one when self-test has failed  
Set ABRT to one when self-test has failed  
Set to F4h when self-test has failed  
Set to 2Ch when self-test has failed  
SMART Selective self-test routine  
When the value in the LBA Low register is 4 or 132, the Selective self-test routine shall be  
performed. This self-test routine shall include the initial tests performed by the Extended self-test  
routine plus a selectable read scan. The host shall not write the Selective self-test log while the  
execution of a Selective self-test command is in progress.  
The user may choose to do read scan only on specific areas of the media. To do this, user shall set the  
test spans desired in the Selective self-test log and set the flags in the Feature flags field of the  
Selective self-test log to indicate do not perform off-line scan. In this case, the test spans defined  
shall be read scanned in their entirety. The Selective self-test log is updated as the self-test proceeds  
indicating test progress. When all specified test spans have been completed, the test is terminated  
and the appropriate self-test execution status is reported in the S.M.A.R.T. READ DATA response  
depending on the occurrence of errors. The following figure shows an example of a Selective selftest  
definition with three test spans defined. In this example, the test terminates when all three test  
spans have been scanned.  
Figure 10 Selective self-test test span example  
After the scan of the selected spans described above, a user may wish to have the rest of media read  
scanned as an off-line scan. In this case, the user shall set the flag to enable off-line scan in addition  
to the other settings. If an error occurs during the scanning of the test spans, the error is reported in  
the self-test execution status in the S.M.A.R.T. READ DATA response and the off-line scan is not  
executed. When the test spans defined have been scanned, the device shall then set the offline scan  
pending and active flags in the Selective self-test log to one, the span under test to a value greater  
147  
 
5K320 SATA OEM Specification  
than five, the self-test execution status in the S.M.A.R.T. READ DATA response to 00h, set a value  
of 03h in the off-line data collection status in the S.M.A.R.T. READ DATA response and shall  
proceed to do an off-line read scan through all areas not included in the test spans. This off-line read  
scan shall completed as rapidly as possible, no pauses between block reads, and any errors  
encountered shall not be reported to the host. Instead error locations may be logged for future  
reallocation. If the device is powered-down before the off-line scan is completed, the off-line scan  
shall resume when the device is again powered up. From power-up, the resumption of the scan shall  
be delayed the time indicated in the Selective self-test pending time field in the Selective self-test log.  
During this delay time the pending flag shall be set to one and the active flag shall be set to zero in  
the Selective self-test log. Once the time expires, the active flag shall be set to one, and the off-line  
scan shall resume. When the entire media has been scanned, the off-line scan shall terminate, both  
the pending and active flags shall be cleared to zero, and the off-line data collection status in the  
S.M.A.R.T. READ DATA response shall be set to 02h indicating completion.  
During execution of the Selective self-test, the self-test executions time byte in the Device S.M.A.R.T.  
Data Structure may be updated but the accuracy may not be exact because of the nature of the test  
span segments. For this reason, the time to complete off-line testing and the self-test polling times  
are not valid. Progress through the test spans is indicated in the selective self-test log.  
A COMRESET or software reset shall abort the Selective self-test except when the pending bit is set  
to one in the Selective self-test log (see 14.40.7 Selective self-test log data structure). The receipt of a  
S.M.A.R.T. EXECUTE OFF-LINE IMMEDIATE command with 0Fh, Abort off-line test routine, in  
the LBA Low register shall abort Selective self-test regardless of where the device is in the execution  
of the command. If a second self-test is issued while a selective self-test is in progress, the selective  
self-test is aborted and the newly requested self-test is executed.  
S.M.A.R.T. Read Log Sector (Subcommand D5h)  
This command returns the specified log sector contents to the host.  
The 512 bytes data are returned at a command and the Sector Count value shall be set to one. The  
LBA Low shall be set to specify the log sector address.  
Log sector address  
Content  
Type  
00h  
Log Directory  
S.M.A.R.T. Error Log  
Read Only  
Read Only  
01h  
02h  
Comprehensive S.M.A.R.T. Error Log Read Only  
06h  
S.M.A.R.T. Self-test Log  
Selective self-test log  
Host vendor specific  
Read Only  
Read/Write  
Read/Write  
09h  
80h-9Fh  
Table 111 Log sector addresses  
S.M.A.R.T. Write Log Sector (Subcommand D6h)  
This command writes 512 bytes data to the specified log sector.  
The 512 bytes data are transferred at a command and the Sector Count value shall be set to one. The  
LBA Low shall be set to specify the log sector address (Table 111 Log sector addresses). If Read Only  
log sector is specified, the device returns ABRT error.  
S.M.A.R.T. Enable Operations (Subcommand D8h)  
This subcommand enables access to all S.M.A.R.T. capabilities within the device. Prior to receipt of a  
S.M.A.R.T. Enable Operations subcommand, Attribute Values are neither monitored nor saved by  
the device. The state of S.M.A.R.T. (either enabled or disabled) will be preserved by the device across  
power cycles. Once enabled, the receipt of subsequent S.M.A.R.T. Enable Operations subcommands  
will not affect any of the Attribute Values.  
Upon receipt of the S.M.A.R.T. Enable Operations subcommand from the host, the device enables  
S.M.A.R.T. capabilities and functions.  
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5K320 SATA OEM Specification  
S.M.A.R.T. Disable Operations (Subcommand D9h)  
This subcommand disables all S.M.A.R.T.capabilities within the device including the device’s  
attribute autosave feature. After receipt of this subcommand the device disables all S.M.A.R.T.  
operations. Non self-preserved Attribute Values will no longer be monitored. The state of  
S.M.A.R.T. (either enabled or disabled) is preserved by the device across power cycles. Note that  
this subcommand does not preclude the device’s power mode attribute autosaving.  
Upon receipt of the S.M.A.R.T. Disable Operations subcommand from the host, the device disables  
S.M.A.R.T. capabilities and functions.  
After receipt of the device of the S.M.A.R.T. Disable Operations subcommand from the host, all other  
S.M.A.R.T. subcommands—with the exception of S.M.A.R.T. Enable Operations—are disabled, and  
invalid and will be aborted by the device (including the S.M.A.R.T. Disable Operations subcommand),  
returning the error code as specified in “Table 124 S.M.A.R.T. Error Codes” on Page 159.  
Any Attribute Values accumulated and saved to volatile memory prior to receipt of the S.M.A.R.T.  
Disable Operations command will be preserved in the device’s Attribute Data Sectors. If the device is  
re-enabled, these Attribute Values will be updated, as needed, upon receipt of a S.M.A.R.T. Read  
Attribute Values or S.M.A.R.T. Save Attribute Values command.  
S.M.A.R.T. Return Status (Subcommand DAh)  
This command is used to communicate the reliability status of the device to the host’s request. Upon  
receipt of the S.M.A.R.T. Return Status subcommand the device asserts BSY, saves any updated  
Attribute Values to the reserved sector and compares the updated Attribute Values to the Attribute  
Thresholds.  
If the device does not detect a Threshold Exceeded Condition, or detects a Threshold Exceeded  
Condition but involving attributes are advisory, the device loads 4Fh into the LBA Mid register, C2h  
into the LBA High register.  
If the device detects a Threshold Exceeded Condition for prefailure attributes, the device loads F4h  
into the LBA Mid register, 2Ch into the LBA High register. Advisory attributes never result in  
negative reliability condition.  
S.M.A.R.T. Enable/Disable Automatic Off-Line  
(Subcommand DBh)  
This subcommand enables and disables the optional feature that cause the device to perform the set  
of off-line data collection activities that automatically collect attribute data in an off-line mode and  
then save this data to the device’s non-volatile memory. This subcommand may either cause the  
device to automatically initiate or resume performance of its off-line data collection activities or  
cause the automatic off-line data collection feature to be disabled. This subcommand also enables  
and disables the off-line read scanning feature that cause the device to perform the entire read  
scanning with defect reallocation as the part of the off-line data collection activities.  
The Sector Count register shall be set to specify the feature to be enabled or disabled.  
Sector Count  
Feature Description  
00h  
01h  
F8h  
F9h  
Disable Automatic Off-line  
Disable Off-line Read Scanning  
Enable Automatic Off-line  
Enable Off-line Read Scanning  
A value of zero written by the host into the device’s Sector Count register before issuing this  
subcommand shall cause the automatic off-line data collection feature to be disabled. Disabling this  
feature does not preclude the device from saving attribute values to non-volatile memory during  
some other normal operation such as during a power-on or power-off sequence or during an error  
recovery sequence.  
A value of one written by the host into the device’s Sector Count register before issuing this  
subcommand shall cause the off-line read scanning feature to be disabled. The Device does not  
perform the off-line read scanning at the off-line data collection activities which is initiated by the  
149  
5K320 SATA OEM Specification  
S.M.A.R.T. Execute Off-line Immediate(Subcommand D4h) or automatically if the off-line read  
scanning feature is disabled.  
A value of F8h written by the host into the device’s Sector Count register before issuing this  
subcommand shall cause the automatic Off-line data collection feature to be enabled.  
A value of F9 written by the host into the device’s Sector Count register before issuing this  
subcommand shall cause the off-line read scanning feature to be enabled. The Device perform the  
off-line read scanning at the off-line data collection activities which is initiated by the S.M.A.R.T.  
Execute Off-line Immediate(Subcommand D4h) even if the automatic off-line feature is disabled.  
Any other non-zero value written by the host into this register before issuing this subcommand is  
vender specific and will not change the current Automatic Off-Line Data Collection and Off-line  
Read Scanning status, but device may respond with the error code specified in “Table 124 S.M.A.R.T.  
Error Codes” on Page 159.  
14.40.2 Device Attributes Data Structure  
The following defines the 512 bytes that make up the Attribute Value information. This data  
structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values  
subcommand. All multi-byte fields shown in these data structures follow the ATA/ATAPI-6  
specification for byte ordering, namely that the least significant byte occupies the lowest numbered  
byte address location in the field.  
Description  
Bytes  
Offset  
Format  
binary  
Value  
0010h  
Data Structure Revision Number  
1st Device Attribute  
2
12  
..  
00h  
02h  
(*1)  
(*2)  
...  
...  
..  
30th Device Attribute  
12  
1
15Eh  
16Ah  
16Bh  
16Ch  
16Eh  
16Fh  
170h  
172h  
173h  
174h  
175h  
176h  
182h  
1FFh  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*1)  
(*2)  
(*2)  
(*2)  
(*2)  
(*2)  
5Bh  
0003h  
01h  
Off-line data collection status  
Self-test execution status  
Total time in seconds to complete off-line data collection activity  
Current segment pointer  
Off-line data collection capability  
S.M.A.R.T. capability  
1
2
1
1
2
S.M.A.R.T. device error logging capability  
Self-test failure check point  
Short self-test completion time in minutes  
Extended self-test completion time in minutes  
Reserved  
1
1
(*2)  
(*2)  
(*2)  
(*3)  
(*3)  
(*2)  
1
1
12  
125  
1
Vendor specific  
Data structure checksum  
(*1)  
512  
(*1) - See following definitions  
(*2) - Value varied by actual operating condition  
(*3) - Filled with 00h  
Table 112 Device Attribute Data Structure  
14.40.2.1  
Data Structure Revision Number  
The Data Structure Revision Number identifies which version of this data structure is implemented  
by the device. This revision number will be set to 0010h. This revision number identifies both the  
Attribute Value and Attribute Threshold Data structures.  
150  
 
5K320 SATA OEM Specification  
14.40.2.2  
Individual Attribute Data Structure  
The following defines the 12 bytes that make up the information for each Attribute entry in the  
Device Attribute Data Structure.  
Description  
Bytes  
Offset  
00h  
Format  
binary  
Attribute ID Number (01h to FFh)  
Status Flags  
1
2
01h  
bit flags  
Bit 0 Pre-Failure/Advisory  
Bit 1 On-line Collection  
Bit 2-5 Reserved (may either 0 or 1)  
Bit 6-15 Reserved (all 0)  
Attribute Value (valid values from 01h to FEh)  
00h invalid for attribute value – not to be used  
1
03h  
binary  
01h minimum value  
64h initial value for all attributes prior to any data collection  
FDh maximum value  
FEh value is not valid  
FFh invalid for attribute value - not to be used  
Reserved (may not be 0)  
Reserved (may not be 0)  
Reserved (00h)  
1
6
04h  
05h  
0Bh  
binary  
binary  
binary  
1
Total Bytes  
12  
Table 113 Individual Attribute Data Structure  
Attribute ID Numbers: Any non-zero value in the Attribute ID Number indicates an active attribute.  
The device supports following Attribute ID Numbers. Those marked with (*) indicate that  
corresponding Attribute Values can be either collected on-line or off-line.  
ID  
0
1
2
3
Attribute Name  
Indicates that this entry in the data structure is not used  
Raw Read Error Rate (*)  
Throughput Performance (*)  
Spin Up Time  
4
Start/Stop Count  
5
7
Reallocated Sector Count  
Seek Error Rate  
8
9
Seek Time Performance (*)  
Power-On Hours Count  
Spin Retry Count  
Device Power Cycle Count  
G Sense error rate  
Power off retract count  
Load/Unload cycle count  
Device Temperature  
Reallocation Event Count  
Current Pending Sector Count  
Off-Line Scan Uncorrectable Sector Count  
Ultra DMA CRC Error Count  
Load Retry Count  
10  
12  
191  
192  
193  
194  
196  
197  
198  
199  
223  
Status Flag Definitions:  
151  
 
5K320 SATA OEM Specification  
Bit  
0
Flag Name  
Definition  
If bit = 0, an Attribute Value less than or equal to its  
corresponding Attribute Threshold indicates an Advisory  
condition where the usage or age of the device has  
exceeded its intended design life period.  
Pre-Failure/Advisory bit  
If bit = 1, an Attribute Value less than or equal  
to its corresponding Attribute Threshold  
indicates a Pre-Failure condition where imminent  
loss of data is being predicted.  
1
On-Line Collective bit  
If bit = 0, the Attribute Value is updated only during  
Off-Line testing.  
If bit = 1, the Attribute Value is updated during On-Line  
testing or during both On-Line and Off-Line testing.  
2-5  
Reserved bits  
Reserved bits  
may either 0 or 1  
Always 0  
6-15  
Table 114 Status Flag Definitions  
Normalized Values: The device will perform conversion of the raw Attribute Values to transform  
them into normalized values, which the host can then compare with the Threshold values. A  
Threshold is the excursion limit for a normalized Attribute Value. In normalizing the raw data, the  
device will perform any necessary statistical validity checks to ensure that an instantaneous raw  
value is not improperly reflected in the normalized Attribute Value (i.e., one read error in the first 10  
reads being interpreted as exceeding the read error rate threshold when the subsequent 1 billion  
reads all execute without error). The end points for the normalized values for all Attributes will be 1  
(01h) at the low end, and 100 (64h) at the high end for the device. For Performance and Error Rate  
Attributes, values greater than 100 are also possible, up to a maximum value of 253 (FDh).  
14.40.2.3  
Off-Line Data Collection Status  
The value of this byte defines the current status of the off-line activities of the device. Bit 7 indicates  
Automatic Off-Line Data Collection Status.  
Bit 7  
0
1
Automatic Off-Line Data Collection Status  
Automatic Off-Line Data Collection is disabled.  
Automatic Off-Line Data Collection is enabled.  
Bits 0 thru 6 represents a hexadecimal status value reported by the device.  
Value  
Definition  
0
2
Off-line data collection never started  
All segments completed without errors. In this case, current segment pointer equals to total segments  
required.  
4
5
6
Off-line data collection suspended by interrupting command  
Off-line data collecting aborted by interrupting command  
Off-line data collection aborted with fatal error  
14.40.2.4  
Self-test execution status  
Bit  
0-3  
Definition  
Percent Self-test remaining  
An approximation of the percent of the self-test routine remaining until completion in ten percent  
increments. Valid values are 0 through 9.  
4-7  
Current Self-test execution status  
0
1
2
3
4
5
6
7
The self-test routine completed without error or has never been run  
The self-test routine aborted by the host  
The self-test routine interrupted by the host with a hard or soft reset  
The device was unable to complete the self-test routine due to a fatal error or unknown test error  
The self-test routine completed with unknown element failure  
The self-test routine completed with electrical element failure  
The self-test routine completed with servo element failure  
The self-test routine completed with read element failure  
152  
 
5K320 SATA OEM Specification  
15  
The self-test routine in progress  
14.40.2.5  
Total Time in Seconds to Complete Off-line Data  
Collection Activity  
This field tells the host how many seconds the device requires to complete the off-line data collection  
activity.  
14.40.2.6  
Current Segment Pointer  
This byte is a counter indicating the next segment to execute as an off-line data collection activity.  
Because the number of segments is 1, 01h is always returned in this field.  
14.40.2.7  
Off-Line Data Collection Capability  
Bit  
0
Definition  
Execute Off-line Immediate implemented bit  
0
1
S.M.A.R.T. Execute Off-line Immediate subcommand is not implemented  
S.M.A.R.T. Execute Off-line Immediate subcommand is implemented  
1
2
Enable/disable Automatic Off-line implemented bit  
0
1
S.M.A.R.T. Enable/disable Automatic Off-line subcommand is not implemented  
S.M.A.R.T. Enable/disable Automatic Off-line subcommand is implemented  
abort/restart off-line by host bit  
0
1
The device will suspend off-line data collection activity after an interrupting command and resume  
it after some vendor specific event  
The device will abort off-line data collection activity upon receipt of a new command  
3
4
Off-line Read Scanning implemented bit  
0
1
The device does not support Off-line Read Scanning  
The device supports Off-line Read Scanning  
Self-test implemented bit  
0
1
Self-test routine is not implemented  
Self-test routine is implemented  
5
6
Reserved (0)  
Selective self-test implemented bit  
0
1
Selective self-test routine is not implemented  
Selective self-test routine is implemented  
7
Reserved (0)  
14.40.2.8  
S.M.A.R.T. Capability  
This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h  
indicating that the device will save its Attribute Values prior to going into a power saving mode and  
supports the S.M.A.R.T. ENABLE/DISABLE ATTRIBUTE AUTOSAVE command.  
Bit  
0
Definition  
Pre-power mode attribute saving capability  
If bit = 1, the device will save its Attribute Values prior to going into a power saving  
mode (Standby or Sleep mode).  
1
Attribute autosave capability  
If bit = 1, the device supports the S.M.A.R.T. ENABLE/DISABLE ATTRIBUTE AUTOSAVE  
command.  
2-15  
Reserved (0)  
14.40.2.9  
Error Logging Capability  
Bit  
7-1  
Definition  
Reserved (0)  
0
Error Logging support bit  
If bit = 1, the device supports the Error Logging  
14.40.2.10  
Self-test failure check point  
This byte indicates the section of self-test where the device detected a failure.  
153  
5K320 SATA OEM Specification  
14.40.2.11  
Self-test completion time  
These bytes are the minimum time in minutes to complete self-test.  
14.40.2.12  
Data Structure Checksum  
The Data Structure Checksum is the 2’s compliment of the result of a simple 8-bit addition of the  
first 511 bytes in the data structure.  
14.40.3 Device Attribute Thresholds Data Structure  
The following defines the 512 bytes that make up the Attribute Threshold information. This data  
structure is accessed by the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All  
multi-byte fields shown in these data structures follow the ATA/ATAPI-6 specification for byte  
ordering, namely that the least significant byte occupies the lowest numbered byte address location  
in the field.  
The sequence of active Attribute Thresholds will appear in the same order as their corresponding  
Attribute Values.  
Description  
Bytes  
Offset  
Format  
binary  
(*1)  
Value  
0010h  
(*2)  
Data Structure Revision Number  
1st Attribute Threshold  
...  
2
12  
..  
00h  
02h  
...  
..  
30th Attribute Threshold  
Reserved  
12  
18  
131  
1
15Eh  
16Ah  
17Ch  
1FFh  
(*1)  
(*2)  
(*3)  
(*3)  
(*2)  
Vendor specific  
Data structure checksum  
512  
(*1) - See following definitions  
(*2) - Value varied by actual operating condition  
(*3) - Filled with 00h  
Table 115 Device Attribute Thresholds Data Structure  
14.40.3.1  
Data Structure Revision Number  
This value is the same as the value used in the Device Attributes Values Data Structure.  
14.40.3.2  
Individual Thresholds Data Structure  
The following defines the 12 bytes that make up the information for each Threshold entry in the  
Device Attribute Thresholds Data Structure. Attribute entries in the Individual Threshold Data  
Structure is in the same order and correspond to the entries in the Individual Attribute Data  
Structure.  
154  
 
5K320 SATA OEM Specification  
Description  
Bytes  
Offset  
Format  
binary  
binary  
Attribute ID Number (01h to FFh)  
1
1
00h  
01h  
Attribute Threshold (for comparison with Attribute Values  
from 00h to FFh)  
00h -  
“always passing” threshold value to be  
used for code test purposes  
minimum value for normal operation  
maximum value for normal operation  
invalid for threshold value  
01h -  
FDh -  
FEh -  
FFh -  
“always failing” threshold value to be used  
for code test purposes  
Reserved (00h)  
Total Bytes  
10  
12  
02h  
binary  
Table 116 Individual Threshold Data Structure  
14.40.3.3  
Attribute ID Numbers  
Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures.  
14.40.3.4  
Attribute Threshold  
These values are preset at the factory and are not meant to be changeable. However, the host  
might use “ S.M.A.R.T. Write Attribute Threshold” subcommand to override these preset values  
in the Threshold sectors.  
14.40.3.5  
Data Structure Checksum  
The Data Structure Checksum is the 2’s compliment of the result of a simple 8-bit addition of the  
first 511 bytes in the data structure.  
14.40.4 S.M.A.R.T. Log Directory  
Following table defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T.  
Log Directory is on S.M.A.R.T. Log Address zero and is defined as one sector long.  
Description  
Bytes Offset  
S.M.A.R.T. Logging Version  
Number of sectors in the log at log address 1  
Reserved  
Number of sectors in the log at log address 2  
Reserved  
…
2
1
1
1
1
…
1
00h  
02h  
03h  
04h  
05h  
…
Number of sectors in the log at log address 255  
Reserved  
1FEh  
1FFh  
1
512  
Table 117 SMART Log Directory  
The value of the S.M.A.R.T. Logging Version word shall be 01h. The logs at log addresses 80-9Fh  
are defined as 16 sectors long.  
14.40.5 S.M.A.R.T. error log sector  
Thefollowingdefinesthe512bytesthatmakeuptheS.M.A.R.T.errorlogsector.Allmulti-byte  
155  
   
5K320 SATA OEM Specification  
fieldsshowninthesedatastructuresfollowtheATA/ATAPI-6specificationsforbyteordering.  
Description  
Bytes Offset  
S.M.A.R.T. error log version  
Error log pointer  
1
1
00h  
01h  
1st error log data structure  
2nd error log data structure  
3rd error log data structure  
4th error log data structure  
5th error log data structure  
Device error count  
90  
90  
90  
90  
90  
2
02h  
5Ch  
B6h  
110h  
16Ah  
1C4h  
1C6h  
1FFh  
Reserved  
57  
1
Data structure checksum  
512  
Table 118 S.M.A.R.T. error log sector  
14.40.5.1 S.M.A.R.T. error log version  
This value is set to 01h.  
14.40.5.2  
This points the most recent error log data structure. Only values 1 through 5 are valid.  
Error log pointer  
14.40.5.3 Device error count  
This field contains the total number of errors. The value will not roll over.  
14.40.5.4 Error log data structure  
Data format of each error log structure is shown below.  
Description  
Bytes Offset  
1st error log data structure  
12  
12  
12  
12  
12  
30  
90  
00h  
0Ch  
18h  
24h  
30h  
3Ch  
2nd error log data structure  
3rd error log data structure  
4th error log data structure  
5th error log data structure  
Error data structure  
Table 119 Error log data structure  
156  
   
5K320 SATA OEM Specification  
Command data structure: Data format of each command data structure is shown below.  
Description  
Bytes Offset  
Device Control register  
Features register  
1
1
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
Sector count register  
LBA Low register  
1
1
LBA Mid register  
1
LBA High register  
Device register  
1
1
Command register  
Timestamp(milliseconds from Power On)  
1
4
12  
Table 120 Command data structure  
Error data structure: Data format of error data structure is shown below.  
Description  
Bytes Offset  
Reserved  
1
1
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
1Bh  
1Ch  
Error register  
Sector count register  
LBA Low register  
LBA Mid register  
LBA High register  
Device register  
1
1
1
1
1
Status register  
1
Extended error data (vendor specific)  
State  
19  
1
Life timestamp (hours)  
2
30  
Table 121 Error data structure  
State field contains a value indicating the device state when command was issued to the device.  
State  
Value  
x0h  
Unknown  
x1h  
Sleep  
x2h  
Standby  
x3h  
Active/Idle  
x4h  
S.M.A.R.T. Off-line or Self-test  
Reserved  
Vendor specific  
x5h-xAh  
xBh-xFh  
Note: The value of x is vendor specific  
157  
   
5K320 SATA OEM Specification  
14.40.6 Self-test log data structure  
Thefollowingdefinesthe512bytesthatmakeuptheSelf-testlogsector.Allmulti-bytefields  
shown in these data structures follow the ATA/ATAPI-7 specifications for byte ordering.  
Description  
Bytes Offset  
Data structure revision  
Self-test number  
Self-test execution status  
Life time power on hours  
Self-test failure check point  
LBA of first failure  
Vendor specific  
2
1
00h  
n*18h+02h  
n*18h+03h  
n*18h+04h  
n*18h+06h  
n*18h+07h  
n*18h+0Bh  
1
2
1
4
15  
...  
Vendor specific  
2
1
1FAh  
1FCh  
1FDh  
1FFh  
Self-test log pointer  
Reserved  
2
Data structure checksum  
1
512  
Note: n is 0 through 20  
Table 122 Self-test log data structure  
The data structure contains the descriptor of Self-test that the device has performed. Each  
descriptor is 24 bytes long and the self-test data structure is capable to contain up to 21  
descriptors.  
After 21 descriptors has been recorded, the oldest descriptor will be overwritten with new  
descriptor.  
Self-test log pointer points the most recent descriptor. When there is no descriptor the value  
is 0. When there is descriptor(s) the value is 1 through 21.  
158  
 
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14.40.7 Selective self-test log data structure  
The Selective self-test log is a log that may be both written and read by the host. This log  
allows the host to select the parameters for the self-test and to monitor the progress of the  
self-test. The following table defines the contents of the Selective self-test log which is  
512byteslong.Allmulti-bytefieldsshowninthesedatastructuresfollowthe specifications  
for byte ordering.  
Description  
Bytes Offset Read/Write  
Data structure revision  
Starting LBA for test span 1  
Ending LBA for test span 1  
Starting LBA for test span 2  
Ending LBA for test span 2  
Starting LBA for test span 3  
Ending LBA for test span 3  
Starting LBA for test span 4  
Ending LBA for test span 4  
Starting LBA for test span 5  
Ending LBA for test span 5  
Reserved  
2
8
8
8
8
8
8
8
8
8
8
256  
154  
8
2
2
00h  
02h  
0Ah  
12A  
1Ah  
22h  
2Ah  
32h  
3Ah  
42h  
4Ah  
52h  
152h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Reserved  
Vendor specific  
Vendor specific  
Current LBA under test  
Current span under test  
Feature flags  
1ECh Read  
1F4h  
1F6  
Read  
R/W  
Vendor specific  
4
1F8h  
Vendor specific  
Selective self test pending time  
Reserved  
Data structure checksum  
2
1
1
1FCh R/W  
1FEh Reserved  
1FFh R/W  
512  
Table 123 Selective self-test log data structure  
14.40.8 Error Reporting  
The following table shows the values returned in the Status and Error Registers when specific  
error conditions are encountered by a device.  
Error Condition  
Status Register  
51h  
Error Register  
04h  
A S.M.A.R.T. FUNCTION SET command was received  
by the device without the required key being loaded into  
the LBA High and LBA Mid registers.  
A S.M.A.R.T. FUNCTION SET command was received  
by the device with a subcommand value in the Features  
Register that is either invalid or not supported by this  
device.  
51h  
51h  
04h  
04h  
A S.M.A.R.T. FUNCTION SET command subcommand  
other than S.M.A.R.T. ENABLE OPERATIONS was  
received by the device while the device was in a  
“S.M.A.R.T. disabled” state.  
The device is unable to read its Attribute Values or  
Attribute Thresholds data structure.  
51h  
51h  
10h or 40h  
10h or 01h  
The device is unable to write to its Attribute Values data  
structure.  
Table 124 S.M.A.R.T. Error Codes  
159  
     
5K320 SATA OEM Specification  
14.41 Standby (E2h/96h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 0 1 0  
Error Register  
Status  
...See Below...  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 125 Standby Command (E2h/96h)  
The Standby command causes the device to enter the Standby Mode immediately, and set auto power  
down timeout parameter(standby timer).  
When this command is issued, the device confirms the completion of the cached write commands.  
Then the device is spun down, but the interface remains active.  
If the device is already spun down, the spin down sequence is not executed.  
During the Standby mode the device will respond to commands, but there is a delay while waiting  
for the spindle to reach operating speed.  
The timer starts counting down when the device returns to Idle mode.  
Output Parameters To The Device  
Timeout Parameter. If zero, the timeout interval(Standby Timer) is disabled. If other  
than zero, the timeout interval is set for (Timeout Parameter x5) seconds.  
When the automatic power down sequence is enabled,  
Sector Count  
The device will enter Standby mode automatically if the timeout interval expires with  
no device access from the host. The timeout interval will be reinitialized if there is a  
device access before the timeout interval expires.  
160  
   
5K320 SATA OEM Specification  
14.42 Standby Immediate (E0h/94h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 0 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 126 Standby Immediate Command (E0h/94h)  
The Standby Immediate command causes the device to enter Standby mode immediately.  
When this command is issued, the device confirms the completion of the cached write commands.  
Then the device is spun down, but the interface remains active.  
If the device is already spun down, the spin down sequence is not executed.  
DuringtheStandbymode, thedevicewillrespondtocommands, butthereisadelaywhilewaiting  
for the spindle to reach operating speed.  
The Standby Immediate command will not affect the auto power down timeout parameter.  
161  
   
5K320 SATA OEM Specification  
14.43 Write Buffer (E8h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Command  
1 1 1 0 1 0 0 0  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
0
0
V
0
0
0
V
0
-
-
0
0
V
Table 127 Write Buffer Command (E8h)  
The Write Buffer command transfers a sector of data from the host to the sector buffer of the  
device. The sectors of data are transferred through the Data Register 16 bits at a time.  
The Read Buffer and Write Buffer commands are synchronized such that sequential Write Buffer  
and Read Buffer commands access the same 512 byte within the buffer.  
162  
   
5K320 SATA OEM Specification  
14.44 Write DMA (CAh/CBh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
- H H H H  
-
-
-
- H H H H  
Command  
1 1 0 0 1 0 1 R  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
V
0
0
V
0
V
0
0
0
V
V
V
-
0
0
V
Table 128 Write DMA Command (CAh/CBh)  
The Write DMA command transfers one or more sectors of data from the host to the device, then  
the data is written to the disk media.  
The sectors of data are transferred through the Data Register 16 bits at a time.  
The host initializes a slave-DMA channel prior to issuing the command. Data transfers are  
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one  
interrupt per command to indicate that data transfer has terminated and status is available.  
If an uncorrectable error occurs, the write will be terminated at the failing sector.  
Output Parameters To The Device  
Sector Count  
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors  
will be transferred.  
LBA Low  
The sector number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 0 - 7. (L=1)  
The cylinder number of the first sector to be transferred. (L=0)  
LBA High/Mid  
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
The head number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 24 - 27. (L=1)  
The retry bit, but this bit is ignored.  
H
R
Input Parameters From The Device  
Sector Count  
The number of requested sectors not transferred. This will be zero, unless  
an unrecoverable error occurs.  
LBA Low  
LBA High/Mid  
H
The sector number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
The cylinder number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
The head number of the last transferred sector. (L=0) In LBA mode, this register  
contains current LBA bits 24 - 27. (L=1)  
163  
   
5K320 SATA OEM Specification  
14.45 Write DMA Ext (35h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
1
0
1
0
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 129 Write DMA Ext Command (35h)  
The Write DMA Ext command transfers one or more sectors of data from the host to the device,  
then the data is written to the disk media.  
The sectors of data are transferred through the Data Register 16 bits at a time.  
The host initializes a slave-DMA channel prior to issuing the command. Data transfers are  
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one  
interrupt per command to indicate that data transfer has terminated and status is available.  
If an uncorrectable error occurs, the write will be terminated at the failing sector  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of continuous sectors to be transferred low order, bits (7:0).  
The number of continuous sectors to be transferred high order bits (15:8). If 0000h in  
the Sector Count register is specified, then 65,536 sectors will be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0).  
LBA (31:24).  
LBA (15:8).  
LBA (39:32).  
LBA (23:16).  
LBA (47:40).  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24) of the address of the first unrecoverable error.  
LBA (15:8) of the address of the first unrecoverable error.  
LBA (39:32) of the address of the first unrecoverable error.  
LBA (23:16) of the address of the first unrecoverable error.  
LBA (47:40) of the address of the first unrecoverable error.  
164  
   
5K320 SATA OEM Specification  
14.46 Write DMA FUA Ext (3Dh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
1
1
1
0
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 130 Write DMA FUA Ext Command (3Dh)  
The Write DMA FUA Ext command transfers one or more sectors of data from the host to the device,  
then the data is written to the disk media. This command provides the same function as the  
Write DMA Ext command except that the transferred data shall be written to the media before  
the ending status for this command is reported also when write caching is enabled.  
The sectors of data are transferred through the Data Register 16 bits at a time.  
The host initializes a slave-DMA channel prior to issuing the command. Data transfers are  
qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one  
interrupt per command to indicate that data transfer has terminated and status is available.  
If an uncorrectable error occurs, the write will be terminated at the failing sector  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of continuous sectors to be transferred low order, bits (7:0).  
The number of continuous sectors to be transferred high order bits (15:8). If 0000h in  
the Sector Count register is specified, then 65,536 sectors will be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0).  
LBA (31:24).  
LBA (15:8).  
LBA (39:32).  
LBA (23:16).  
LBA (47:40).  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24) of the address of the first unrecoverable error.  
LBA (15:8) of the address of the first unrecoverable error.  
LBA (39:32) of the address of the first unrecoverable error.  
LBA (23:16) of the address of the first unrecoverable error.  
LBA (47:40) of the address of the first unrecoverable error.  
165  
   
5K320 SATA OEM Specification  
14.47 Write FPDMA Queued (61h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Data Low  
Data High  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
V V V V V V V V Error  
V V V V V V V V  
...See Below...  
Previous  
Sector Count Current  
Previous  
T
P
T
-
T
-
T
-
T
-
-
-
-
-
-
-
Sector Count HOB=0  
HOB=1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
F
0
1
1
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
1
0
0
0
0
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
V
0
V
0
0
0
V
0
V
-
0
0
V
Table 131 Write FPDMA Queued Command (61h)  
TheWriteFPDMAQueuedcommandtransfersoneormoresectorsofdatafromthehosttothedevice,  
then the data is written to the disk media.  
If an uncorrectable error occurs, the write will be terminated at the failing sector  
Output Parameters To The Device  
Feature Current  
Feature Previous  
T
The number of sectors to be transferred low order, bit (7:0)  
The number of sectors to be transferred high order, bit (15:8)  
TAG value. It shall be assigned to be different from all other queued commands.  
The value shall not exceed the maximum queue depth specified by the Word 75 of the  
Identify Device information.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
F
LBA (7:0).  
LBA (31:24).  
LBA (15:8).  
LBA (39:32).  
LBA (23:16).  
LBA (47:40).  
FUA bit. When the FUA bit is set to 1, the completion status is indicated after the  
transferred data are written to the media also when Write Cache is enabled. When the  
FUA bit is set to 0, the completion status may be indicated before the transferred data  
are written to the media successfully when Write Cache is enabled.  
Priority bit. When the Priority bit is set to 1, the device attempts to provide better  
quality of service for the command than normal priority commands.  
P
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24) of the address of the first unrecoverable error.  
LBA (15:8) of the address of the first unrecoverable error.  
LBA (39:32) of the address of the first unrecoverable error.  
LBA (23:16) of the address of the first unrecoverable error.  
LBA (47:40) of the address of the first unrecoverable error.  
166  
   
5K320 SATA OEM Specification  
14.48 Write Log Ext (3Fh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
HOB=0  
HOB=1  
HOB=0  
HOB=1  
HOB=0  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
-
-
-
-
-
-
-
-
V V V V V V V V LBA Mid  
V V V V V V V V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LBA High  
Device  
-
-
-
-
-
-
-
-
Device  
Status  
Command  
0
0
1
1
1
1
1
1
...See Below...  
Status Register  
Error Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
V
V
V
0
0
0
V
0
V
-
0
0
V
Table 132 Write Log Ext Command  
This command writes a specified number of 512 byte data sectors to the specific log. The device  
shall interrupt for each DRQ block transferred.  
Output Parameters To The Device  
Sector Count Current  
The number of sectors to be written to the specified log low  
order, bits (7:0).  
Sector Count Previous  
The number of sectors to be written to the specified log high  
orders, bits (15:8). If the number of sectors is greater than the  
number indicated in the Log directory, which is available in Log  
number zero, the device shall return command aborted. The log  
transferred to the device shall be stored by the device starting at  
the first sector in the specified log.  
Sector Number Current  
The log to be written as described in Table 111 Log sector  
addresses definition. If the host attempts to write to a read only  
log address, the device shall return command aborted.  
The first sector of the log to be written low order, bits (7:0).  
The first sector of the log to be written high order, bits (15:8)  
Cylinder Low Current  
Cylinder Low Previous  
If the feature set associated with the log specified in the Sector Number register is not  
supported or enabled, or if the values in the Sector Count, Sector Number or Cylinder Low  
registers are invalid, the device shall return command aborted. If the host attempts to write  
to a read only log address, the device shall return command aborted.  
167  
   
5K320 SATA OEM Specification  
14.49 Write Multiple (C5h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data  
7 6 5 4 3 2 1 0  
Register  
Data  
7 6 5 4 3 2 1 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feature  
Error  
...See Below...  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
Sector Count  
LBA Low  
LBA Mid  
LBA High  
Device  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
V V V V V V V V  
- L  
-
H H H H  
-
-
-
- H H H H  
-
Command  
1 1 0 0 0 1 0 1  
Status  
...See Below...  
Error Register  
Status Register  
7
6
5
0
4
3
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
IDN  
ABT T0N AM  
N
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
0
V
0
V
0
0
0
V
V
V
-
0
0
V
Table 133 Write Multiple Command (C5h)  
The Write Multiple command transfers one or more sectors from the host to the device, then  
the data is written to the disk media.  
Command execution is identical to the Write Sectors command except that an interrupt is  
generated for each block (as defined by the Set Multiple command) instead of for each sector.  
The sectors are transferred through the Data Register 16 bits at a time.  
Output Parameters To The Device  
Sector Count  
LBA Low  
LBA High/Mid  
H
The number of continuous sectors to be transferred. If zero is specified, then 256 sectors  
will be transferred.  
The sector number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 0 - 7. (L=1)  
The cylinder number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 8 - 15 (Mid), 16 - 23 (High). (L=1)  
The head number of the first sector to be transferred. (L=0)  
In LBA mode, this register contains LBA bits 24 - 27. (L=1)  
Input Parameters From The Device  
Sector Count  
The number of requested sectors not transferred. This will be zero, unless an  
unrecoverable error occurs.  
LBA Low  
The sector number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 0 - 7. (L=1)  
The cylinder number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 8 - 15 (Mid), 16 - 23 (High).  
(L=1)  
LBA High/Mid  
H
The head number of the last transferred sector. (L=0)  
In LBA mode, this register contains current LBA bits 24 - 27. (L=1)  
168  
   
5K320 SATA OEM Specification  
14.50 Write Multiple Ext (39h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
1
1
0
0
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 134 Write Multiple Ext Command (39h)  
The Write Multiple Ext command transfers one or more sectors from the host to the device, then  
the data is written to the disk media.  
Command execution is identical to the Write Sector(s) Ext command except that an interrupt  
isgeneratedforeachblock(asdefinedbytheSetMultiplecommand)insteadofforeachsector.  
The sectors are transferred through the Data Register 16 bits at a time.  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of continuous sectors to be transferred low order, bits (7:0)  
The number of continuous sectors to be transferred high order, bits (15:8). If 0000h in  
the Sector Count register is specified, then 65,536 sectors shall be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0).  
LBA (31:24).  
LBA (15:8).  
LBA (39:32).  
LBA (23:16).  
LBA (47:40).  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24) of the address of the first unrecoverable error.  
LBA (15:8) of the address of the first unrecoverable error.  
LBA (39:32) of the address of the first unrecoverable error.  
LBA (23:16) of the address of the first unrecoverable error.  
LBA (47:40) of the address of the first unrecoverable error.  
169  
   
5K320 SATA OEM Specification  
14.51 Write Multiple FUA Ext (CEh)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
1
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
1
0
0
1
1
1
0
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 135 Write Multiple FUA Ext Command (CEh)  
The Write Multiple FUA Ext command transfers one or more sectors from the host to the device,  
then the data is written to the disk media. This command provides the same function as the  
WriteMultipleExtcommandexceptthatthetransferreddatashallbewrittentothemediabefore  
the ending status for this command is reported also when write caching is enabled.  
Output Parameters To The Device  
Sector Count Current  
Sector Count Previous  
The number of continuous sectors to be transferred low order, bits (7:0)  
The number of continuous sectors to be transferred high order, bits (15:8). If 0000h in  
the Sector Count register is specified, then 65,536 sectors shall be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0).  
LBA (31:24).  
LBA (15:8).  
LBA (39:32).  
LBA (23:16).  
LBA (47:40).  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24) of the address of the first unrecoverable error.  
LBA (15:8) of the address of the first unrecoverable error.  
LBA (39:32) of the address of the first unrecoverable error.  
LBA (23:16) of the address of the first unrecoverable error.  
LBA (47:40) of the address of the first unrecoverable error.  
170  
   
5K320 SATA OEM Specification  
171  
   
5K320 SATA OEM Specification  
14.53 Write Sector(s) Ext (34h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
0
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
1
1
0
1
0
0
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
V
-
0
0
V
172  
   
5K320 SATA OEM Specification  
14.54 Write Uncorrectable Ext (45h)  
Command Block Output Registers  
Command Block Input Registers  
Register  
Data Low  
Data High  
Feature  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Register  
Data Low  
Data High  
Error  
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current  
-
-
-
-
-
-
-
-
...See Below...  
Previous  
-
-
-
-
-
-
-
-
Sector Count Current  
Previous  
V V V V V V V V Sector Count HOB=0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V V V V V V V V  
HOB=1  
LBA Low  
LBA Mid  
LBA High  
Current  
Previous  
Current  
Previous  
Current  
Previous  
V V V V V V V V LBA Low  
V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
HOB=0 V V V V V V V V  
HOB=1 V V V V V V V V  
V V V V V V V V LBA Mid  
V V V V V V V V  
V V V V V V V V LBA High  
V V V V V V V V  
Device  
-
1
1
-
-
-
-
-
-
Device  
Status  
-
-
-
-
-
-
-
-
Command  
0
0
0
0
1
0
1
...See Below...  
Error Register  
Status Register  
7
6
5
0
0
4
IDN  
V
3
0
0
2
1
0
7
6
5
4
3
2
1
0
CRC UNC  
ABT T0N AMN  
BSY RDY DF DSC DRQ COR IDX ERR  
0
0
V
0
0
0
V
0
V
-
0
0
V
Table 138 Write Uncorrectable Ext Command (45h)  
The Write Uncorrectable Ext command is used to cause the device to report an uncorrectable  
error when the target sector is subsequently read.  
When the feature field contains a value of 5xh, the Write Uncorrectable Ext command causes  
thedevicetoindicateafailurewhenreadstoanyofthesectorsthatarecontainedinspecified  
sectors. Theses sectors are referred to as “pseudo uncorrectable” sectors. In this case  
whenever a pseudo uncorrectable sector is accessed via a read command, the device performs  
normal error recovery and then set the UNC and ERR bits to indicate she sector is bad.  
When the feature field contains a value of Axh, the Write Uncorrectable Ext command causes  
the device to flag thespecified sector as “flagged uncorrectable”. Flagging a logical sector  
as uncorrectable causes the device to indicate a failure when reads to specified sectors are  
performed. These sectors are referred to as “flagged uncorrectable” sectors. In this case  
whenever a “flagged uncorrectable” sector is accessed via a read command, the device sets the  
UNC and ERR bits without normal error recovery to indicate the sector is bad.  
If the Uncorrectable options are set to A5h or 55h, then sectors that have been made pseudo  
uncorrectable are listed as failed in the standard error logs when read back. If the  
Uncorrectable options are set to 5Ah or AAh, then the reading of pseudo uncorrectable sectors  
are not logged as an error in any standardized error logs.  
The pseudo uncorrectable or flagged uncorrectable status of a sector remains through a power  
cycle.  
If an uncorrectable error occurs, the write will be terminated at the failing sector.  
Output Parameters To The Device  
Feature Current  
Uncorrectable options  
55h : Create a pseudo uncorrectable error with logging  
5Ah: Create a pseudo uncorrectable error without logging  
A5h: Create a flagged error with logging  
AAh: Create a flagged error without logging  
Other: Reserved (command is aborted)  
173  
   
5K320 SATA OEM Specification  
The number of continuous sectors to be marked low order, bits (7:0).  
The number of continuous sectors to be marked high order bits (15:8). If 0000h in the  
Sector Count Current  
Sector Count Previous  
Sector Count register is specified, then 65,536 sectors will be transferred.  
LBA Low Current  
LBA Low Previous  
LBA Mid Current  
LBA Mid Previous  
LBA High Current  
LBA High Previous  
LBA (7:0).  
LBA (31:24).  
LBA (15:8).  
LBA (39:32).  
LBA (23:16).  
LBA (47:40).  
Input Parameters From The Device  
LBA Low (HOB=0)  
LBA Low (HOB=1)  
LBA Mid (HOB=0)  
LBA Mid (HOB=1)  
LBA High (HOB=0)  
LBA High (HOB=1)  
LBA (7:0) of the address of the first unrecoverable error.  
LBA (31:24) of the address of the first unrecoverable error.  
LBA (15:8) of the address of the first unrecoverable error.  
LBA (39:32) of the address of the first unrecoverable error.  
LBA (23:16) of the address of the first unrecoverable error.  
LBA (47:40) of the address of the first unrecoverable error.  
174  
5K320 SATA OEM Specification  
15 Timings  
The timing of BSY and DRQ in Status Register are shown in the following table.  
The other timings are described in Functional Specification part.  
FUNCTION  
INTERVAL  
Device Ready  
START  
STOP  
TIMEOUT  
31 sec  
Power On and COMRESET  
Status Register  
Power On and After Power On  
COMRESET  
BSY=0 and RDY=1  
and sends a Register  
FIS to the host.  
Software  
Reset  
Device Busy  
After Software Reset  
Device Control Register  
RST=1 and sends a Register  
FIS to the Device.  
Status Register  
BSY=1  
400 ns  
31 sec  
Device Ready  
After Software Reset  
Device Control Register  
RST=0 and sends a Register  
FIS to the Device. After  
RST=1 and sends a Register  
FIS to the Device.  
Status Register  
BSY=0 and RDY=1  
and requests to send a  
Register FIS to the host.  
COMRESET Device Ready  
After COMRESET  
COMRESET Signal  
Asserted  
Status Register  
31 sec  
BSY=0 and RDY=1  
and sends a Register  
FIS to the Host.  
Data In  
Device Busy  
Sets proper values in the  
Status Register  
400 ns  
30 sec  
After a Register FIS to issue a registers and sends a Register BSY=1  
command FIS  
PIO SETUP FIS for data-in Status Register  
Command  
Status Register  
transfer  
BSY=1  
BSY=0 and DRQ=1  
and sends a PIO  
SETUP FIS to the host.  
Device Busy  
After Data Transfer In  
A PIO SETUP FIS is  
transferred to the host.  
Status Register  
BSY=1  
10 us  
Data Out  
Device Busy  
Sets proper values in the  
Status Register  
400 ns  
Command  
After a Register FIS to issue a registers and sends a Register BSY=1  
command  
FIS  
Device Busy  
After Data Transfer Out  
Sends a Data FIS to the device. Status Register  
BSY=1  
5 us  
PIO SETUP FIS for data-out Status Register  
Status Register  
30 sec  
transfer  
BSY=1  
BSY=0 and RDY=1  
and sends a PIO  
(Note.1)  
SETUP FIS to the host.  
Non-Data  
Command  
Device Busy  
Sets proper values in the  
Status Register  
400 ns  
After a Register FIS to issue a registers and sends a Register BSY=1  
command  
FIS  
A Register FIS to report  
Command Complete  
Status Register BSY=1  
Sets the status of the  
command to the Status  
Register and sends a  
Register FIS to the host  
30 sec  
(Note.2)  
DMA Data  
Transfer  
Command  
Device Busy  
Sets proper values in the  
Status Register  
400 ns  
After a Register FIS to issue a registers and sends a Register BSY=1  
command FIS  
Table 139 Timeout Values  
Command category is referred to “13 Command Protocol” on page 72.  
The abbreviations “ns”, “us”, “ms” and “sec” mean nanoseconds, microseconds, milliseconds and  
seconds, respectively.  
We recommend that the host system executes Soft reset and then retry to issue the command if  
the host system timeout would occur for the device.  
175  
   
5K320 SATA OEM Specification  
(Note.1)  
(Note.2)  
For SECURITY ERASE UNIT command, the execution time is referred to “14.29 Security  
Erase Unit (F4h)” on Page 129.  
FORMAT UNIT command, the execution time is referred to “14.8 Format Unit (F7h: Vendor  
Specific)” on Page 90.  
176  
5K320 SATA OEM Specification  
© Copyright Hitachi Global Storage Technologies  
Hitachi Global Storage Technologies  
3403 Yerba Buena Road  
San Jose, CA 95135  
Produced in the United States  
4/10  
All rights reserved Travelstar™ is a trademark of  
Hitachi Global Storage Technologies.  
Microsoft, Windows XP, and Windows are trademarks  
of Microsoft Corporation in the United States, other  
countries, or both.  
Other product names are trademarks or registered  
trademarks of their respective companies.  
References in this publication to Hitachi Global  
Storage Technologies products, programs or services  
177  

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