Transcend Information TS8GCF600 User Manual

TS8G~16GCF600

600X CompactFlash Card

Features

Description

• CompactFlash Specification Version 4.1 Complaint

• RoHS compliant products

Dedicated to fulfilling the demanding requirements of

performance-conscious photographers, Transcend

proudly releases its Extreme Plus 600X CompactFlash

cards with Turbo MLC technology. With its amazing

performance, the Transcend 600x CompactFlash

memory card allows the professional photographers

and enthusiasts to get the most from your digital single

lens reflex (DSLR) camera. Users are guaranteed to

makes consecutive shooting and non-stop video

recording and share their digital artwork with the world!

• Single Power Supply: 3.3V 5% or 5V 10%

• Operating Temperature: -25^oC to 85^oC

• Storage Temperature: -40^oC to 85^oC

• Operating/ Storage Humidity: 5% to 95%

• Operation Modes:

ꢀPC Card Memory Mode

ꢀPC Card IO Mode

ꢀTrue IDE Mode

• True IDE Mode supports:

ꢀUltra DMA Mode 0 to Ultra DMA Mode 6 (Ultra DMA

mode 5/6 must use Power supply: 3.3V)

Placement

ꢀMultiWord DMA Mode 0 to MultiWord DMA Mode 4

ꢀPIO Mode 0 to PIO Mode 6

• PC Card Mode supports up to Ultra DMA Mode 6

• True IDE mode: Fixed Disk (Standard)

• PC Card Mode: Removable Disk (Standard)

• Durability of Connector: 10,000 times

• Built-in 15 bit ECC (Error Correction Code) functionality

• Support Global Wear-Leveling to extend product life

• Compliant to CompactFlash, PC Card Mode, and ATA

standards

Power Consumption

Dimensions

Product

TS8GCF600 TS16GCF600

Standby

Read

2.4mA

2.5mA

Power

Consumption

222.8mA

218.1mA

232.8mA

211.5mA

(DC 3.3V @25 )

Write

* Maximum value

Transcend Information Inc.

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600X CompactFlash Card

Block Diagram

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600X CompactFlash Card

Transcend Information Inc.

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600X CompactFlash Card

Pin Assignments and Pin Type

PC Card Memory Mode

PC Card I/O Mode

True IDE Mode4

Num

Signal

Name

Type

Signal

Name

Type

In, Out

Type

Num

Signal

Name

Type

In, Out

Type

In, Out Type Pin Num

GND

D03

D04

D05

D06

D07

-CE1

A10

-OE

Ground

I1Z, OZ3

I3U

GND

D03

D04

D05

D06

D07

-CE1

A10

-OE

Ground

I1Z, OZ3

I3U

GND

D03

Ground

I1Z, OZ3

I3Z

I/O

D04

D05

D06

D07

-CS0

A10²

I1Z

I3U

-ATA SEL

I3U

A09

A08

A07

VCC

A06

A05

A04

A03

I1Z

A09

A08

A07

VCC

A06

A05

A04

A03

I1Z

A09²

A08²

A07²

VCC

A06²

A05²

A04²

A03²

I1Z

Power

I1Z

Power

I1Z

Power

I1Z

A02

A01

I1Z

A02

A01

I1Z

A02

A01

I1Z

A00

I1Z

A00

I1Z

A00

I1Z

D00

I/O

I1Z, OZ3

OT3

D00

I/O

I1Z, OZ3

OT3

D00

I/O

I1Z, OZ3

ON3

D01

D02

-IOIS16

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CE2¹

-IOCS16

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CS1¹

-CD2

-CD1

D11¹

D121

D13¹

D14¹

D15¹

-CE2¹

Ground

I1Z, OZ3

I3U

Ground

I1Z, OZ3

I3U

Ground

I1Z, OZ3

I3Z

I/O

-VS1

Ground

-VS1

Ground

-VS1

Ground

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PC Card Memory Mode

PC Card I/O Mode

True IDE Mode⁴

Num

Type

In, Out

Type

Num

Signal Name

Type

In, Out

Type

Num

Type

In, Out

Type

Signal Name

-HIOE⁷

HSTROBE⁸

-HDMARDY⁹

-HIOE

HSTROBE¹⁰

HDMARDY¹¹

I3U

HSTROBE¹⁰

-HDMARDY¹¹

I3U

I3Z

-IOWR

STOP^10,11

-WE

-IOWR

STOP^10,11

-WE

-IOWR⁷

STOP^8,9

-WE³

I3U

I3Z

I3U

READY

VCC

OT1

Power

I2Z

-IREQ

VCC

OT1

Power

I2Z

INTRQ

VCC

OZ1

Power

I2U

-CSEL⁵

-CSEL

-VS2

OPEN

I2Z

-VS2

OPEN

I2Z

-VS2

OPEN

I2Z

RESET

-RESET

IORDY⁷

-DDMARDY⁸

DSTROBE⁹

-WAIT

ON1

-DDMARDY¹⁰

DSTROBE¹¹

-INPACK

-DMARQ¹²

-REG

-DDMARDY¹⁰

DSTROBE¹¹

-INPACK

-DMARQ¹²

-REG

OT1

OT1¹³

OT1

I3U

OT1

I3U

DMARQ

OZ1

I3U

-DMACK ⁶

-DMACK ¹²

DMACK ¹²

BVD2

OT1

-SPKR

OT1

-DASP

I/O

I1U, ON1

BVD1

-STSCHG

-PDIAG

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

D08¹

D09¹

I/O

D08¹

D09¹

I/O

D08¹

D09¹

I/O

I1Z, OZ3

D10¹

GND

D10¹

GND

D10¹

GND

I1Z, OZ3

Ground

Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state

signals not to consume current.

2) The signal should be grounded by the host.

3) The signal should be tied to VCC by the host.

4) The mode is required for CompactFlash Storage Cards.

5) The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes,

it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC

Card A25 or grounded by the host.

6) If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA

operations are not active, the card shall ignore this signal,including a floating condition

7) Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.

8) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.

9) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active.

10) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active.

11) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active.

12) Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active.

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ꢁ

Input Leakage Current

Note: In Table 1 below, x refers to the characteristics described in table 2. For example, I1U indicates a pull-up resistor with a type 1

input characteristic.

Table 1: Input Leakage Current

Type

IxZ

Parameter

Symbol

Conditions

Vih = Vcc / Vil = Gnd

Vcc = 5.0V

MIN TYP MAX Units

Input Leakage Current

Pull-Up Resistor

-1

µA

IxU

RPU1

RPD1

50k

500k

Ohm

IxD

Pull-Down Resistor

Vcc = 5.0V

Note: The minimum pull-up resistor resistance meets the PCMCIA PC Card specification of 10k ohms but is intentionally higher in the

CompactFlash Specification to reduce power use.

ꢁ

Input Characteristics

Table 2: Input Characteristics

Type

Parameter

Symbol

Units

MIN

TYP

MAX

MIN

TYP

MAX

VCC = 3.3 V

VCC = 5.0 V

Volts

Input Voltage

CMOS

Vih

Vil

2.4

1.5

0.6

4.0 ¹

2.0

0.8

Input Voltage

CMOS

Vih

Vil

Input Voltage

CMOS Schmitt

Trigger

Vth

Vtl

1.8

1.0

2.8

2.0

Notes: 1) The host provides a logic output high voltage for a CMOS load of .9 x VCC. For a 5 volt product, this translates to .9 x

4.5 = 4.05 volts minimum Voh.

ꢁ

Output Drive Type

Note: In Table 3 below, x refers to the characteristics described in Table 4. For example, OT3 refers to Totem pole output with a type

3 output drive characteristic.

Table 3: Output Drive Type

Type

Output Type

Valid Conditions

Ioh & Iol

OTx

OZx

Totempole

Tri-State N-P Channel

Ioh & Iol

OPx

ONx

P-Channel Only

N-Channel Only

Ioh Only

Iol Only

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ꢁ

Output Drive Characteristics

Table 4: Output Drive Characteristics

Type

Parameter

Symbol

Conditions

MIN

TYP

MAX

Units

Vcc

-0.8V

Voh

Vol

Ioh = -4 mA

Output Voltage

Volts

Gnd

+0.4V

Iol = 4 mA

Vcc

-0.8V

Voh

Vol

Ioh = -4 mA

Iol = 4 mA

Output Voltage

Volts

Gnd

+0.4V

Vcc

-0.8V

Voh

Vol

Ioh = -4 mA

Iol = 4 mA

Volts

Gnd

+0.4V

Tri-State Leakage

Current

Vol = Gnd

Voh = Vcc

Ioz

-10

µA

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Signal Description

Signal Name

Dir.

Description

A10 – A00

8,10,11,12, These address lines along with the -REG signal are used to select the following:

14,15,16,17, The I/O port address registers within the CompactFlash Storage Card , the

(PC Card Memory Mode)

18,19,20

memory mapped port address registers within the CompactFlash Storage Card,

a byte in the card's information structure and its configuration control and status

registers.

A10 – A00

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

A02 - A00

18,19,20

In True IDE Mode, only A[02:00] are used to select the one of eight registers

in the Task File, the remaining address lines should be grounded by the

host.

(True IDE Mode)

BVD1

I/O

This signal is asserted high, as BVD1 is not supported.

(PC Card Memory Mode)

-STSCHG

This signal is asserted low to alert the host to changes in the READY and Write

Protect states, while the I/O interface is configured. Its use is controlled by the

Card Config and Status Register.

(PC Card I/O Mode)

Status Changed

-PDIAG

In the True IDE Mode, this input / output is the Pass Diagnostic signal in the

Master / Slave handshake protocol.

(True IDE Mode)

BVD2

I/O

This signal is asserted high, as BVD2 is not supported.

(PC Card Memory Mode)

-SPKR

This line is the Binary Audio output from the card. If the Card does not support

the Binary Audio function, this line should be held negated.

(PC Card I/O Mode)

-DASP

In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in

the Master/Slave handshake protocol.

(True IDE Mode)

-CD1, -CD2

26,25

These Card Detect pins are connected to ground on the CompactFlash Storage

Card. They are used by the host to determine that the CompactFlash Storage

Card is fully inserted into its socket.

(PC Card Memory Mode)

-CD1, -CD2

This signal is the same for all modes.

(PC Card I/O Mode)

-CD1, -CD2

(True IDE Mode)

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Signal Name

-CE1, -CE2

Dir.

Description

These input signals are used both to select the card and to indicate to the card

whether a byte or a word operation is being performed. -CE2 always accesses

the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the

word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1,

-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29,

Table 31, Table 35, Table 36 and Table 37.

7,32

(PC Card Memory Mode)

Card Enable

This signal is the same as the PC Card Memory Mode signal.

-CE1, -CE2

(PC Card I/O Mode)

Card Enable

In the True IDE Mode, -CS0 is the address range select for the task file

registers while -CS1 is used to select the Alternate Status Register and the

Device Control Register.

-CS0, -CS1

(True IDE Mode)

While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the

width of the transfers shall be 16 bits.

-CSEL

This signal is not used for this mode, but should be connected by the host to PC

Card A25 or grounded by the host.

(PC Card Memory Mode)

-CSEL

This signal is not used for this mode, but should be connected by the host to PC

Card A25 or grounded by the host.

(PC Card I/O Mode)

-CSEL

This internally pulled up signal is used to configure this device as a Master or a

Slave when configured in the True IDE Mode.

(True IDE Mode)

When this pin is grounded, this device is configured as a Master.

When the pin is open, this device is configured as a Slave.

D15 - D00

(PC Card Memory Mode)

31,30,29,28,

27,49,48,47,

6,5,4,3,2,

I/O

These lines carry the Data, Commands and Status information between the host

and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB

of the Odd Byte of the Word.

23, 22, 21

This signal is the same as the PC Card Memory Mode signal.

D15 - D00

(PC Card I/O Mode)

D15 - D00

(True IDE Mode)

In True IDE Mode, all Task File operations occur in byte mode on the low order

bus D[7:0] while all data transfers are 16 bit using D[15:0].

GND

1,50

Ground.

(PC Card Memory Mode)

GND

This signal is the same for all modes.

(PC Card I/O Mode)

GND

(True IDE Mode)

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Signal Name

Dir.

Description

This signal is not used in this mode.

-INPACK

(PC Card Memory Mode except

Ultra DMA Protocol Active)

The Input Acknowledge signal is asserted by the CompactFlash Storage Card

when the card is selected and responding to an I/O read cycle at the address

that is on the address bus. This signal is used by the host to control the enable of

any input data buffers between the CompactFlash Storage Card and the CPU.

-INPACK

(PC Card I/O Mode except Ultra

DMA Protocol Active)

Input Acknowledge

Hosts that support a single socket per interface logic, such as for Advanced

Timing Modes and Ultra DMA operation may ignore the –INPACK signal from

the device and manage their input buffers based solely on Card Enable signals.

This signal is a DMA Request that is used for DMA data transfers between host

and device. It shall be asserted by the device when it is ready to transfer data to

or from the host. For Multiword DMA transfers, the direction of data transfer is

controlled by -HIOE and -IOWR. This signal is used in a handshake manner with

(-)DMACK, i.e., the device shall wait until the host asserts (-)DMACK before

negating (-)DMARQ, and re-asserting (-)DMARQ if there is more data to

transfer.

-DMARQ

(PC Card Memory Mode -Ultra

DMA Protocol Active)

-DMARQ

(PC Card I/O Mode -Ultra DMA

Protocol Active)

DMARQ

(True IDE Mode)

In PCMCIA I/O Mode, the

performing an I/O Read cycle to the device. The host shall not initiate an I/O

Read cycle while DMARQ is asserted by the device.

DMARQ shall be ignored by the host while the host is

In True IDE Mode, DMARQ shall not be driven when the device is not selected in

the Drive-Head register.

While a DMA operation is in progress, -CS0 (-CE1)and -CS1 (-CE2) shall be

held negated and the width of the transfers shall be 16 bits.

If there is no hardware support for True IDE DMA mode in the host, this output

signal is not used and should not be connected at the host. In this case, the

BIOS must report that DMA mode is not supported by the host so that device

drivers will not attempt DMA mode operation.

A host that does not support DMA mode and implements both PC Card and True

IDE modes of operation need not alter the PC Card mode connections while in

True IDE mode as long as this does not prevent proper operation in any mode.

-HIOE

(PC Card Memory Mode except

Ultra DMA Protocol Active)

This signal is not used in this mode.

This is an I/O Read strobe generated by the host. This signal gates I/O data onto

the bus from the CompactFlash Storage Card when the card is configured to use

the I/O interface.

-HIOE

(PC Card I/O Mode except Ultra

DMA Protocol Active)

In True IDE Mode, while Ultra DMA mode is not active, this signal has the same

function as in PC Card I/O Mode.

-HIOE

(True IDE Mode – Except Ultra

DMA Protocol Active)

In all modes when Ultra DMA mode DMA Read is active, this signal is asserted

by the host to indicate that the host is ready to receive Ultra DMA data-in bursts.

The host may negate – HDMARDY to pause an Ultra DMA transfer.

-HDMARDY

(All Modes - Ultra DMA Protocol

DMA Read)

In all modes when Ultra DMA mode DMA Write is active, this signal is the data

out strobe generated by the host. Both the rising and falling edge of HSTROBE

cause data to be latched by the device. The host may stop generating

HSTROBE edges to pause an Ultra DMA data-out burst.

HSTROBE

(All Modes - Ultra DMA Protocol

DMA Write)

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Signal Name

-IOWR

(PC Card Memory Mode– Except

Ultra DMA Protocol Active)

Dir.

Description

This signal is not used in this mode.

The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into

the CompactFlash Storage Card controller registers when the CompactFlash

Storage Card is configured to use the I/O interface.

-IOWR

(PC Card I/O Mode –Except Ultra

DMA Protocol Active)

The clocking shall occur on the negative to positive edge of the signal (trailing

edge).

In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has

the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is

supported, this signal must be negated before entering Ultra DMA mode

protocol.

-IOWR

(True IDE Mode – Except Ultra

DMA Protocol Active)

In All Modes, while Ultra DMA mode protocol is active, the assertion of this

signal causes the termination of the Ultra DMA data burst.

STOP

(All Modes – Ultra DMA Protocol

Active)

-OE

(PC Card Memory Mode)

This is an Output Enable strobe generated by the host interface. It is used to

read data from the CompactFlash Storage Card in Memory Mode and to read

the CIS and configuration registers.

In PC Card I/O Mode, this signal is used to read the CIS and configuration

registers.

-OE

(PC Card I/O Mode)

-ATA SEL

(True IDE Mode)

To enable True IDE Mode this input should be grounded by the host.

READY

(PC Card Memory Mode)

In Memory Mode, this signal is set high when the CompactFlash Storage Card

is ready to accept a new data transfer operation and is held low when the card is

busy.

At power up and at Reset, the READY signal is held low (busy) until the

CompactFlash Storage Card has completed its power up or reset function. No

access of any type should be made to the CompactFlash Storage Card during

this time.

Note, however, that when a card is powered up and used with RESET

continuously disconnected or asserted, the Reset function of the RESET pin is

disabled. Consequently, the continuous assertion of RESET from the

application of power shall not cause the READY signal to remain continuously in

the busy state.

-IREQ

(PC Card I/O Mode)

I/O Operation – After the CompactFlash Storage Card Card has been

configured for I/O operation, this signal is used as -Interrupt Request. This line is

strobed low to generate a pulse mode interrupt or held low for a level mode

interrupt.

INTRQ

(True IDE Mode)

In True IDE Mode signal is the active high Interrupt Request to the host.

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Signal Name

Dir.

Description

This signal is used during Memory Cycles to distinguish between Common

Memory and Register (Attribute) Memory accesses. High for Common Memory,

Low for Attribute Memory.

-REG

(PC Card Memory Mode– Except

Ultra DMA Protocol Active)

Attribute Memory Select

In PC Card Memory Mode, when Ultra DMA Protocol is supported by the host

and the host has enabled Ultra DMA protocol on the card the, host shall keep the

-REG signal negated during the execution of any DMA Command by the device.

The signal shall also be active (low) during I/O Cycles when the I/O address is

on the Bus.

-REG

(PC Card I/O Mode –Except Ultra

DMA Protocol Active)

In PC Card I/O Mode, when Ultra DMA Protocol is supported by the host and the

host has enabled Ultra DMA protocol on the card the, host shall keep the -REG

signal asserted during the execution of any DMA Command by the device.

This is a DMA Acknowledge signal that is asserted by the host in response to

(-)DMARQ to initiate DMA transfers.

-DMACK

(PC Card Memory Mode when

Ultra DMA Protocol Active)

In True IDE Mode, while DMA operations are not active, the card shall ignore the

(-)DMACK signal, including a floating condition.

DMACK

(PC Card I/O Mode when Ultra

DMA Protocol Active)

If DMA operation is not supported by a True IDE Mode only host, this signal

should be driven high or connected to VCC by the host.

-DMACK

(True IDE Mode)

A host that does not support DMA mode and implements both PC Card and

True-IDE modes of operation need not alter the PC Card mode connections

while in True-IDE mode as long as this does not prevent proper operation all

modes.

RESET

The CompactFlash Storage Card is Reset when the RESET pin is high with the

following important exception:

(PC Card Memory Mode)

The host may leave the RESET pin open or keep it continually high from the

application of power without causing a continuous Reset of the card. Under

either of these conditions, the card shall emerge from power-up having

completed an initial Reset.

The CompactFlash Storage Card is also Reset when the Soft Reset bit in the

Card Configuration Option Register is set.

RESET

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

In the True IDE Mode, this input pin is the active low hardware reset from the

host.

-RESET

(True IDE Mode)

VCC

13,38

+5 V, +3.3 V power.

(PC Card Memory Mode)

VCC

This signal is the same for all modes.

(PC Card I/O Mode)

VCC

(True IDE Mode)

Transcend Information Inc.

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Signal Name

Dir.

Description

-VS1

-VS2

Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host

so that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is

reserved by PCMCIA for a secondary voltage and is not connected on the Card.

(PC Card Memory Mode)

-VS1

This signal is the same for all modes.

-VS2

(PC Card I/O Mode)

-VS1

This signal is the same for all modes.

-VS2

(True IDE Mode)

-WAIT

(PC Card Memory Mode – Except

Ultra DMA Protocol Active)

The -WAIT signal is driven low by the CompactFlash Storage Card to signal the

host to delay completion of a memory or I/O cycle that is in progress.

This signal is the same as the PC Card Memory Mode signal.

-WAIT

(PC Card I/O Mode –Except Ultra

DMA Protocol Active)

In True IDE Mode, except in Ultra DMA modes, this output signal may be used

as IORDY.

IORDY

(True IDE Mode – Except Ultra

DMA Protocol Active)

In all modes, when Ultra DMA mode DMA Write is active, this signal is asserted

by the device during a data burst to indicate that the device is ready to receive

Ultra DMA data out bursts. The device may negate -DDMARDY to pause an

Ultra DMA transfer.

-DDMARDY

(All Modes – Ultra DMA Write

Protocol Active)

In all modes, when Ultra DMA mode DMA Read is active, this signal is the data

in strobe generated by the device. Both the rising and falling edge of DSTROBE

cause data to be latched by the host. The device may stop generating

DSTROBE edges to pause an Ultra DMA data in burst.

DSTROBE

(All Modes – Ultra DMA Read

Protocol Active)

-WE

This is a signal driven by the host and used for strobing memory write data to the

registers of the CompactFlash Storage Card when the card is configured in the

memory interface mode. It is also used for writing the configuration registers.

(PC Card Memory Mode)

-WE

In PC Card I/O Mode, this signal is used for writing the configuration registers.

(PC Card I/O Mode)

-WE

In True IDE Mode, this input signal is not used and should be connected to VCC

(True IDE Mode)

(PC Card Memory Mode)

Write Protect

by the host.

Memory Mode – The CompactFlash Storage Card does not have a write protect

switch. This signal is held low after the completion of the reset initialization

sequence.

-IOIS16

(PC Card I/O Mode)

I/O Operation – When the CompactFlash Storage Card is configured for I/O

Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A

Low signal indicates that a 16 bit or odd byte only operation can be performed at

the addressed port.

In True IDE Mode this output signal is asserted low when this device is expecting

a word data transfer cycle.

-IOCS16

(True IDE Mode)

Transcend Information Inc.

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TS8G~16GCF600

600X CompactFlash Card

Electrical Specification

The following tables indicate all D.C. Characteristics for the CompactFlash Storage Card. Unless

otherwise stated, conditions are:

Vcc = 5V 10%

Vcc = 3.3V 5%

ꢁ

Absolute Maximum Conditions

ꢁ

DC Characteristics

CompactFlash Interface I/O at 5.0V

Parameter

Symbol

V_CC

Min.

4.5

Max.

5.5

Unit

Remark

Supply Voltage

V_CC

0.8

High level output voltage

Low level output voltage

V_OH

V_OL

0.8

Non-schmitt trigger

Schmitt trigger¹

4.0

High level input voltage

V_IH

V_IL

2.92

Non-schmitt trigger

Schmitt trigger¹

0.8

1.70

Low level input voltage

Pull up resistance²

Pull down resistance

R_PU

R_PD

KOhm

CompactFlash Interface I/O at 3.3V

Parameter

Symbol

V_CC

Min.

Max.

Unit

Remark

Supply Voltage

3.135

3.465

V_CC

0.8

High level output voltage

Low level output voltage

V_OH

V_OL

0.8

Non-schmitt trigger

Schmitt trigger¹

2.4

High level input voltage

V_IH

V_IL

2.05

Non-schmitt trigger

Schmitt trigger¹

0.6

1.25

141

172

Low level input voltage

Pull up resistance²

Pull down resistance

R_PU

R_PD

52.7

47.5

KOhm

1. Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW pins

2. Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW, CSEL (P35), PDIAG, DASP pins

Transcend Information Inc.

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600X CompactFlash Card

ꢁ

Input Power

ꢁ

Input Characteristics for UDMA mode >4

In UDMA modes greater than 4, the following characteristics apply. Voltage output high and low values shall be met

at the source connector to include the effect of series termination.

Table: Input Characteristics (UDMA Mode > 4)

Parameter

Symbol

V_DD3

V+

MIN

3.3 –8% 3.3% + 8% Volts

MAX

Units

DC supply voltage to drivers

Low to high input threshold

High to low input threshold

Difference between input thresholds:

((V+ _{current value}) - (V-_{current value}))

Average of thresholds:

1.5

1.0

2.0

1.5

Volts

V-

V_HYS

320

1.3

Volts

V_THRAVG

1.7

((V+ _{current value}) + (V-_{current value}))/2

ꢁ

Output Drive Characteristics for UDMA mode > 4

In UDMA modes greater than 4, the characteristics specified in the following table apply. Voltage output high and low

values shall be met at the source connector to include the effect of series termination.

Table: Output Drive Characteristics (UDMA Mode > 4)

Parameter

DC supply voltage to drivers

Symbol

V_DD3

MIN

MAX

3.3 –8% 3.3% + 8% Volts

Units

Voltage output high at -6 mA to +3 mA (at VoH2 the output shall

be able to supply and sink current toVDD3)

Voltage output low at 6 mA

V_oH2

V_oL2

V_DD3–0.51 V_DD3+0.3

0.51

Volts

Notes:

1) I^oLDASPshall be 12 mA minimum to meet legacy timing and signal integrity.

2) I^oHvalue at 400 A is insufficient in the case of DMARQ that is pulled low by a 5.6 k resistor.

3) Voltage output high and low values shall be met at the source connector to include the effect of series termination.

4) A device shall have less than 64 A of leakage current into a 6.2 K pull-down resistor while the INTRQ signal is in the released

state.

Transcend Information Inc.

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TS8G~16GCF600

600X CompactFlash Card

ꢁ

Signal Interface

Electrical specifications shall be maintained to ensure data reliability. Additional requirements are necessary for

Advanced Timing Modes and Ultra DMA modes operations. See next sections for additional information.

Item

Signal

-CE1

-CE2

-REG

-HIOE

-IOWR

-OE

Card¹⁰

Pull-up to V_CC500 K

Host¹⁰

50 K and

shall be sufficient to keep inputs inactive

when the pins are not connected at the

host.¹

Control Signal

1,2

Pull-up to V_CC500 K

50 K

-WE

1,2,9,

RESET

READY

-WAIT

Status Signal

Pull-up to V_CC

10 K

In PCMCIA PC Card modes Pull-up to V_CC

10 K

In True IDE mode, if DMA operation is

supported by the host, Pull-down to Gnd R

5.6 K

-INPACK

PC Card / True IDE hosts switch the pull-up

to pull down in True IDE mode if DMA

operation is supported.

The PC Card mode Pull-up may be left

active during True IDE mode if True IDE

DMA operation is not supported.

A[10:00]

-CSEL

D[15:00]

-CD[2:1]

-VS1

Address

Data Bus

Card Detect

Connected to GND in the card

Voltage Sense

Battery/Detect

Pull-up to Vcc 10 K

100K

-VS2

3.6

BVD[2:1]

Pull-up R

50 K

Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF ¹⁰at a DC current of 700

low state and 150 A high state, including pull-resistor. The socket shall be able to drive at least the following

load ¹⁰while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF

with DC current 700 A low state and 150 A high state per socket).

2) Resistor is optional.

3) Status Signals: the socket shall present a load to the card no larger than 50 pF ¹⁰at a DC current of 400 A low

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

¹⁰while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state.

4) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

10 while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state.

5) Status Signals: the socket shall present a load to the card no larger than 50 pF ¹⁰at a DC current of 400 A low

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

¹⁰while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 1100 A high state.

6) BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall

pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”

7) Address Signals: each card shall present a load of no more than 100pF ¹⁰at a DC current of 450 A low state and

150 A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing

requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450 A low state

and 150 A high state per socket).

8) Data Signals: the host and each card shall present a load no larger than 50pF ¹⁰at a DC current of 450 A and

150 A high state. The host and each card shall be able to drive at least the following load 10 while meeting all

AC timing requirements: 100pF with DC current 1.6mA low state and 300 A high state. This permits the host to

wire two sockets in parallel without derating the card access speeds.

9) Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used

in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal

operation the pull-up should be turned off once the Reset signal has been actively driven low by the host.

Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input

current leakage test.

10) Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for

CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the

implementation of CF Advanced Timing modes and Ultra DMA modes respectively.

ꢁ

Additional Requirements for CF Advanced Timing Modes

The CF Advanced Timing modes include PC Card I/O and Memory modes that are 100ns or faster, PC Card Ultra

DMA modes 3 or above and True IDE PIO Modes 5,6, Multiword DMA Modes 3,4 and True IDE Ultra DMA modes

3 or above.

When operating in CF Advanced timing modes, the host shall conform to the following requirements:

1) Only one CF device shall be attached to the CF Bus.

2) The host shall not present a load of more than 40pF to the device for all signals, including any cabling.

3) The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host

controller. 0.46 m (18 in) cables are not supported.

4) The -WAIT and IORDY signals shall be ignored by the host.

Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with

systems that do not support CF Advanced timing modes

Transcend Information Inc.

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600X CompactFlash Card

ꢁ

Ultra DMA Electrical Requirements

ꢂ

Host and Card signal capacitance limits for Ultra DMA operation

The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at

1 MHz.

The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at

1 MHz.

ꢂ

Series termination required for Ultra DMA operation

Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table

describes typical values for series termination at the host and the device.

Table: Typical Series Termination for Ultra DMA

Signal

Host Termination

22 ohm

Device Termination

82 ohm

-HIOE (-HDMARDY,HSTROBE)

-IOWR (STOP)

-CS0, -CS1

33 ohm

22 ohm

33 ohm

82 ohm

33 ohm

22 ohm

A00, A01, A02

-DMACK

D15 through D00

DMARQ

INTRQ

IORDY (-DDMARDY, DSTROBE)

-RESET

82 ohm

33 ohm

22 ohm

82 ohm

NOTE

Only those signals requiring termination are listed in this table. If a signal is not listed, series

termination is not required for operation in an Ultra DMA mode. Shows signals also requiring a pull-up or

pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver

and trace impedance to match the characteristic cable impedance.

Transcend Information Inc.

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Table: Ultra DMA Termination with Pull-up or Pull down Example

ꢂ

Printed Circuit Board (PCB) Trace Requirements for Ultra DMA

On any PCB for a host or device supporting Ultra DMA:

ꢀ

The longest D[15:00] trace shall be no more than 0.5" longer than either STROBE trace as measured from the

IC pin to the connector.

The shortest D[15:00] trace shall be no more than 0.5" shorter than either STROBE trace as measured from

the IC pin to the connector.

Ultra DMA Mode Cabling Requirement

ꢀ

Operation in Ultra DMA mode requires a crosstalk suppressing cable. The cable shall have a grounded line

between each signal line.

ꢀ

For True IDE mode operation using a cable with IDE (ATA) type 40 pin connectors it is recommended that the

host sense the cable type using the method described in the ANSI INCITS 361-2002 AT Attachment - 6

standard, to prevent use of Ultra DMA with a 40 conductor cable.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Attribute Memory Read Timing Specification

Attribute Memory access time is defined as 300 ns. Detailed timing specs are shown in Table below

Speed Version

Item

300 ns

Symbol

tc(R)

ta(A)

IEEE Symbol

tAVAV

tAVQV

Min ns.

300

Max ns.

Read Cycle Time

Address Access Time

300

150

100

Card Enable Access Time

Output Enable Access Time

Output Disable Time from CE

Output Disable Time from OE

Address Setup Time

Output Enable Time from CE

Output Enable Time from OE

Data Valid from Address Change

ta(CE)

ta(OE)

tdis(CE)

tdis(OE)

tsu (A)

ten(CE)

ten(OE)

tv(A)

tELQV

tGLQV

tEHQZ

tGHQZ

tAVGL

tELQNZ

tGLQNZ

tAXQX

Note: All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -CE signal or

both the -OE signal and the -WE signal shall be de-asserted between consecutive cycle operations.

Transcend Information Inc.

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600X CompactFlash Card

ꢁ

Configuration Register (Attribute Memory) Write Timing Specification

The Card Configuration write access time is defined as 250 ns. Detailed timing specifications are shown in Table

below.

Table: Configuration Register (Attribute Memory) Write Timing

Speed Version

Item

250 ns

Symbol

Min ns

250

150

Max ns

Write Cycle Time

Write Pulse Width

Address Setup Time

Write Recovery Time

Data Setup Time for WE

Data Hold Time

tc(W)

tw(HWE)

tsu(HA)

trec(HWE)

tsu(HD-HWEH)

th(HD)

Note: All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card .

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ꢁ

Common Memory Read Timing Specification

Cycle Time Mode:

250 ns

120 ns

100 ns

80 ns

IEEE

Symbol

Min Max Min Max Min Max Min Max

ns.

Item

Symbol

ns.

ns. ns.

Output Enable Access Time

ta(HOE)

tGLQV

125

Output Disable Time from HOE tdis(HOE)

tGHQZ

tAVGL

tGHAX

tELGL

tGHEH

100

Address Setup Time

tsu(HA)

th(HA)

Address Hold Time

CEx Setup before HOE

CEx Hold following HOE

Wait Delay Falling from HOE

Data Setup for Wait Release

Wait Width Time2

tsu(CEx)

th(CEx)

tv(IORDY-HOE) tGLWTV

na¹

tv(IORDY)

tw(IORDY)

tQVWTH

tWTLWTH

350

Notes:1) –WAIT is not supported in this mode.

2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in

nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -WAIT signal may be

ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the

Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally less in

this specification.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Common Memory Write Timing Specification

Cycle Time Mode: 250 ns

120 ns

100 ns

80 ns

IEEE

Symbol

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Item

Symbol

ns.

Data Setup before HWE

Data Hold following HWE

HWE Pulse Width

tsu (HD-HWEH)

th(HD)

tDVWH

tWMDX

tWLWH

tAVWL

150

tw(HWE)

Address Setup Time

tsu(HA)

CEx Setup before HWE

Write Recovery Time

Address Hold Time

tsu(CEx)

tELWL

trec(HWE)

th(HA)

tWMAX

tGHAX

CEx Hold following HWE

Wait Delay Falling from HWE

WE High from Wait Release

Wait Width Time2

th(CEx)

tGHEH

tv (IORDY-HWE)

tv(IORDY)

tw (IORDY)

tWLWTV

tWTHWH

tWTLWTH

350

Notes: 1) –WAIT is not supported in this mode.

2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in

nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT signal may be

ignored if the -HWE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined

from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is

intentionally less in this specification.

Transcend Information Inc.

V1.0

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600X CompactFlash Card

ꢁ

I/O Input (Read) Timing Specification

Cycle Time Mode: 250 ns

120 ns

100 ns

80 ns

ns.

IEEE

Symbol

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Item

Symbol

td(HIOE)

Data Delay after HIOE

tlGLQV

100

Data Hold following HIOE

HIOE Width Time

th(HIOE)

tlGHQX

tlGLIGH

tAVIGL

tlGHAX

tELIGL

165

tw(HIOE)

Address Setup before HIOE

Address Hold following HIOE

CEx Setup before HIOE

CEx Hold following HIOE

HREG Setup before HIOE

HREG Hold following HIOE

tsuA(HIOE)

thA(HIOE)

tsuCE(HIOE)

thCE(HIOE)

tsuREG (HIOE)

thREG (HIOE)

tlGHEH

tRGLIGL

tlGHRGH

Wait Delay Falling from HIOE²

tdWT(HIOE)

tlGLWTL

Na¹

Data Delay from Wait Rising²

Wait Width Time²

td(IORDY)

tw(IORDY)

tWTHQV

Na¹

tWTLWTH

350

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

I/O Output (Write) Timing Specification

Cycle Time Mode:

255 ns

120 ns

100 ns

80 ns

IEEE

Symbol

Min

ns.

Max

ns.

Min Max

ns. ns.

Min Max

ns. ns.

Min

ns.

Item

Symbol

tsu(HIOW)

ns.

Data Setup before HIOW

Data Hold following HIOW

HIOW Width Time

tDVIWH

tlWHDX

tlWLIWH

tAVIWL

165

th(HIOW)

tw(HIOW)

tsuA(HIOW)

Address Setup before HIOW

Address Hold following HIOW

CEx Setup before HIOW

thA(HIOW)

tlWHAX

tsuCE (HIOW)

thCE (HIOW)

tsuREG (HIOW)

thREG (HIOW)

tdWT(HIOW)

tdrHIOW (IORDY)

tELIWL

CEx Hold following HIOW

HREG Setup before HIOW

HREG Hold following HIOW

Wait Delay Falling from HIOW²

HIOW high from Wait high²

tlWHEH

tRGLIWL

tlWHRGH

tlWLWTL

tWTJIWH

Na¹

tWTLWT

Wait Width Time²

tw(IORDY)

350

Transcend Information Inc.

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600X CompactFlash Card

ꢁ

True IDE PIO Mode Read/Write Timing Specification

Mode

Item

Note

Cycle time (min)

600

383

240

180

120

100

Address Valid to HIOE/HIOW

setup (min)

t2i

HIOE/HIOW (min)

165

290

125

290

100

290

HIOE/HIOW (min) Register (8 bit)

HIOE/HIOW recovery time (min)

HIOW data setup (min)

HIOW data hold (min)

HIOE data setup (min)

HIOE data hold (min)

T6Z HIOE data tristate (max)

Address valid to -IOCS16

assertion (max)

n/a

Address valid to -IOCS16 released

(max)

n/a

HIOE/HIOW to address valid hold

Read Data Valid to IORDY active

(min), if IORDY initially low after tA

tRD

IORDY Setup time

na⁵

IORDY Pulse Width (max)

IORDY assertion to release (max)

1250 1250 1250 1250 1250 na⁵

na⁵

Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time)

total load. All times are in nanoseconds. Minimum time from -IORDY high to -HIOE high is 0 nsec, but minimum -HIOE width

shall still be met.

1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time

or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command

inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirement is

greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is

equal to or greater than the value reported in the device’s identify device data. A CompactFlash Storage Card

implementation shall support any legal host implementation.

2) This parameter specifies the time from the negation edge of -HIOE to the time that the data bus is no longer driven by the

CompactFlash Storage Card (tri-state).

3) The delay from the activation of -HIOE or -HIOW until the state of IORDY is first sampled. If IORDY is inactive then the host

shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash Storage Card is not driving

IORDY negated at tA after the activation of -HIOE or -HIOW, then t5 shall be met and tRD is not applicable. If the

CompactFlash Storage Card is driving IORDY negated at the time tA after the activation of -HIOE or -HIOW, then tRD shall

be met and t5 is not applicable.

4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.

5) IORDY is not supported in this mode.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

True IDE Multiword DMA Mode Read/Write Timing Specification

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Mode 3

(ns)

Mode 4

(ns)

Item

Note

Cycle time (min)

480

215

150

120

100

-HIOE / -HIOW asserted width (min)

-HIOE data access (max)

-HIOE data hold (min)

150

-HIOE/-HIOW data setup (min)

-HIOW data hold (min)

100

-HREG to –HIOE/-HIOW setup (min)

-HIOE / -HIOW to -HREG hold (min)

-HIOE negated width (min)

-HIOW negated width (min)

-HIOE to DMARQ delay (max)

-HIOW to DMARQ delay (max)

CEx valid to –HIOE / -HIOW

CEx hold

215

120

tKR

t^KW

t^LR

t^LW

Transcend Information Inc.

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600X CompactFlash Card

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

True IDE Ultra DMA Mode Read/Write Timing Specification

Ultra DMA operations can take place in any of the three basic interface modes: PC Card Memory mode, PC Card I/O

mode, and True IDE (the original mode to support UDMA). The usage of signals in each of the modes is shown in Table

24:Ultra DMA Signal Usage In Each Interface Mode

Pin # (Non

UDMA MEM

MODE)

PC CARD MEM

MODE UDMA

PC CARD IO MODE

UDMA

TRUE IDE MODE

UDMA

UDMA Signal

Type

DMARQ

HREG

HIOW

Output

Input

43 (-INPACK)

44 (-REG)

-DMARQ

-DMACK

STOP 1

-DMARQ

DMACK

STOP 1

DMARQ

-DMACK

STOP 1

Input

35 (-HIOW)

-HDMARDY(R) ¹,

-HDMARDY(R) ^{1, 2}

HSTROBE(W) ^{1, 3, 4}

-HDMARDY(R) ^{1, 2}

HSTROBE(W) ^{1, 3, 4}

HIOE

Input

34 (-HIOE)

42 (-WAIT)

2HSTROBE(W) ^{1, 3, 4}

-DDMARDY(W) ^{1, 3}

DSTROBE(R) ^{1. 2. 4}

-DDMARDY(W) ^{1, 3}

DSTROBE(R) ^{1. 2. 4}

-DDMARDY(W) ^{1, 3}

DSTROBE(R) ^{1. 2. 4}

IORDY

Output

HD [15:0]

HA [10:0]

CSEL

Bidir

Input

… (D[15:00])

… (A[10:00])

39 (-CSEL)

37 (READY)

D[15:00]

A[10:00]

-CSEL

D[15:00]

A[10:00]

-CSEL

D[15:00]

A[02:00] 5

-CSEL

Input

HIRQ

Output

READY

-INTRQ

INTRQ

CE1

CE2

7 (-CE1)

31 (-CE2)

-CE1

-CE2

-CE1

-CE2

-CS0

-CS1

Input

Notes:1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.

2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.

3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.

4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.

5) Address lines 03 through 10 are not used in True IDE mode.

Several signal lines are redefined to provide different functions during an Ultra DMA data burst. These lines assume their

UDMA definitions when:

an Ultra DMA mode is selected, and

a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and

the device asserts (-)DMARQ, and

the host asserts (-)DMACK.

These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of -DMACK by the

host at the termination of an Ultra DMA data burst.

With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the same agent (either

host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are given either to the

device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst.

During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for

propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both

edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the

data.

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is

capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to

select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less than or

Transcend Information Inc.

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TS8G~16GCF600

600X CompactFlash Card

equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at any given time.

All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall

also support all slower Ultra DMA modes.

An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset

sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to

defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable

reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA mode

and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA data burst. At the end of an Ultra DMA data burst

the host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two

values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra DMA data

bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error

has occurred before data transfer for the command is complete, the device may complete the transfer and report the error

or abort the command and report the error.

NOTE -If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the host

software driver regardless of whether all data requested by the command has been transferred.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Measure

UDMA

UDMA Mode

UDMA

Mode 1

UDMA

Mode 2

UDMA

Mode 3

UDMA

Mode 4

UDMA

Mode 5

Name

location (see

Mode 6

Note 2)

Min

240

112

230

15.0

5.0

Max

Min Max

160

Min Max

120

Min Max Min Max

Min

Max

Min

Max

16.8

Sender

Note 3

Sender

Recipient

Sender

Device

Host

t^2CYCTYP

tCYC

t2CYC

tDS

13.0

153

10.0

5.0

115

7.0

5.0

20.0

6.2

7.0

5.0

20.0

6.2

5.0

6.7

6.2

5.0

6.7

6.2

4.0

4.6

4.8

5.0

10.0

2.6

3.5

4.0

5.0

10.0

5.0

tDH

70.0

6.2

48.0

6.2

31.0

6.2

t^DVS

t^DVH

t^CS

15.0

5.0

10.0

5.0

7.0

5.0

t^CH

70.0

6.2

48.0

6.2

31.0

6.2

tCVS

tCVH

tZFS

tDZFS

t^FS

Host

Device

Sender

Device

Note 4

70.0

48.0

200

31.0

170

20.0

6.7

17.5

230

150

130

100

120

100

150

t^LI

Host

tMLI

Host

tUI

Note 5

Host

tAZ

t^ZAH

t^ZAD

t^ENV

t^RFS

tRP

Device

Host

Sender

Recipient

Device

Host

160

125

100

tIORDYZ

tZIORDY

tACK

t^SS

Sender

Notes:

1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.

2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement

location column. For example, in the case of tRFS, both STROBE and –DMARDY transitions are measured at

the sender connector.

3) The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

4) The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an

incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing

response shall be measured at the same connector.

5) The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but must

release the bus the allow for a bus turnaround.

Name

t^2CYCTYP

t^CYC

Comment

Notes

Typical sustained average two cycle time

Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)

Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to

next falling edge of STROBE)

t^2CYC

Data setup time at recipient (from data valid until STROBE edge)

Data hold time at recipient (from STROBE edge until data may become invalid)

Data valid setup time at sender (from data valid until STROBE edge)

Data valid hold time at sender (from STROBE edge until data may become invalid)

CRC word setup time at device

2, 5

tDS

tDH

tDVS

tDVH

t^CS

CRC word hold time device

t^CH

CRC word valid setup time at host (from CRC valid until -DMACK negation)

CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid)

Time from STROBE output released-to-driving until the first transition of critical timing.

Time from data output released-to-driving until the first transition of critical timing.

First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

Limited interlock time

t^CVS

t^CVH

t^ZFS

tDZFS

tFS

tLI

Interlock time with minimum

t^MLI

t^UI

Unlimited interlock time

Maximum time allowed for output drivers to release (from asserted or negated)

Minimum delay time required for output

t^AZ

t^ZAH

t^ZAD

drivers to assert or negate (from released)

Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and from

DMACK to STOP during data out burst initiation)

tENV

Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of -DMARDY)

Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)

Maximum time before releasing IORDY

tRFS

t^RP

t^IORDYZ

t^ZIORDY

t^ACK

Minimum time before driving IORDY

4, 6

Setup and hold times for -DMACK (before assertion or negation)

Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a

burst)

tSS

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Notes: 1) The parameters tUI, tMLI : (Ultra DMA Data-In Burst Device Termination Timing and Ultra DMA

Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender

interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a

signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a

limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.

2) 80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times

in modes greater than 2.

3) Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF

at the connector where the Data and STROBE signals have the same capacitive load value. Due to

reflections on the cable, these timing measurements are not valid in a normally functioning system.

4)For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has

a pull-up on IORDY- giving it a known state when released.

5)The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in

a configuration with a single device located at the end of the cable. This could result in the minimum

values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.

UDMA

Mode 0

(ns)

UDMA

Mode 1

(ns)

UDMA

Mode 2

(ns)

UDMA

Mode 3

(ns)

UDMA

Mode4

(ns)

UDMA

Mode 5

(ns)

UDMA

Mode 6

(ns)

Name

Min

14.7

4.8

Max

Min

9.7

Max

Min

6.8

Max

Min

6.8

Max

Min

4.8

9.5

9.0

Max

Min

2.3

2.8

6.0

Max

Min

2.3

2.8

5.2

Max

t^DSIC

t^DHIC

4.8

t^DVSIC

t^DVHIC

72.9

9.0

50.9

9.0

33.9

9.0

22.6

9.0

t^DSIC

Recipient IC data setup time (from data valid until STROBE edge) (see note 2)

Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2)

Sender IC data valid setup time (from data valid until STROBE edge) (see note 3)

t^DHIC

t^DVSIC

t^DVHIC

Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)

Notes: 1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.

2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4

V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC

and tDHIC timing (as measured through 1.5 V).

3)The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at

the IC where all signals have the same capacitive load value. Noise that may couple onto the output

signals from external sources has not been included in these values.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Name

Comment

Min Max

[V/ns] [V/ns]

Notes

SRISE

Rising Edge Slew Rate for any signal

Falling Edge Slew Rate for any signal

1.25

S^FALL

Note: 1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation

material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient

loading after the test point. All other signals should remain connected through to the recipient. The test

point may be located at any point between the sender’s series termination resistor and one half inch or

less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB,

an adjacent ground conductor shall also be cut within one half inch of the connector.

The test load and test points should then be soldered directly to the exposed source side connectors.

The test loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size

capacitor from the test point to ground. Slew rates shall be met for both capacitor values.

Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and

a 500 MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled

VOH level with data transitions at least 120 nsec apart. The settled VOH level shall be measured as

the average output high level under the defined testing conditions from 100 nsec after 80% of a rising

edge until 20% of the subsequent falling edge.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Card Configuration

The CompactFlash Storage Cards is identified by appropriate information in the Card Information Structure (CIS).

The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that

are located in the system. In addition, these registers provide a method for accessing status information about

the CompactFlash Storage Card that may be used to arbitrate between multiple interrupt sources on the same

interrupt level or to replace status information that appears on dedicated pins in memory cards that have

alternate use in I/O cards.

ꢁ

Multiple Function CompactFlash Storage Cards

Table: CompactFlash Storage Card Registers and Memory Space Decoding

-CE2 -CE1 -REG -OE -WE A10 A9 A8-A4 A3 A2 A1 A0

SELECTED SPACE

Standby and UDMA transfer

Configuration Registers Read

Common Memory Read (8 Bit D7-D0)

Common Memory Read (8 Bit D15-D8)

Common Memory Read (16 Bit D15-D0)

Configuration Registers Write

Common Memory Write (8 Bit D7-D0)

Common Memory Write (8 Bit D15-D8)

Common Memory Write (16 Bit D15-D0)

Card Information Structure Read

Invalid Access (CIS Write)

Invalid Access (Odd Attribute Read)

Invalid Access (Odd Attribute Write)

Invalid Access (Odd Attribute Read)

Invalid Access (Odd Attribute Write)

Transcend Information Inc.

V1.0

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600X CompactFlash Card

Table: PC Card Memory Mode UDMA Function

-DMARDY

-HIOE

STROBE

-WAIT

-DMARQ -DMACK STOP

-HIOW

DMA

CMD

A10-

A00

-CE2 -CE1

Operation

-INPACK

-REG

(R)-WAIT

(W)

(R)-HIOE

(W)

Standby

Device UDMA Transfer Request

(Assert DMARQ)

YES

Host Acknowledge Preparation

Static Host Acknowledge Preparation

YES

Static DMA Acknowledge (Stopped)

Static Burst Initiation / Active

Static Burst Transfer

/ or \

0 or 1

Static Data In Burst Host Pause

Static Data In Burst Device Pause

Static Data Out Burst Device Pause

Static Data Out Burst Host Pause

0 or 1

Static Device Initiating BurstTermination

Host Acknowledement of Device

Static

Initiated Burst Termination

YES

Static Host Initiating BurstTermination

Device Acknowledging Host Initiated

Burst Termination

Static

Device Aligning STROBE to Asserted

before CRC Transfer

Static

YES

Static CRC Data Transfer for UDMA Burst

Static Burst Completed

Table: CompactFlash Storage Card Configuration Registers Decoding

-CE2 -CE1 -REG -OE -WE A10 A9 A8-A4 A3 A2 A1 A0 SELECTED REGISTER

Configuration Option Reg Read

Configuration Option Reg Write

Card Status Register Read

Card Status Register Write

Pin Replacement Register Read

Pin Replacement Register Write

Socket and Copy Register Read

Socket and Copy Register Write

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Attribute Memory Function

Attribute memory is a space where CompactFlash Storage Card identification and configuration information

are stored, and is limited to 8 bit wide accesses only at even addresses. The card configuration registers are

also located here. For CompactFlash Storage Cards, the base address of the Card configuration registers is

200h.

Table: Attribute Memory Function

Function Mode

Standby Mode

DMA CMD -REG -CE2 -CE1 A10

A0 -OE -WE

D15-D8

D7-D0

Don’t Care

High Z

Standby Mode

UDMA Operation (see section

4.3.18: Ultra DMA Mode

Even

Byte

Yes

L¹

Odd Byte

Read/Write

Specification)

Timing

Read Byte Access CIS ROM

(8 bits)

Even

Byte

L²

High Z

Write Byte Access CIS (8 bits)

(Invalid)

Don’t

Care

Even

Byte

L²

Read

Byte

Access

Even

Byte

Configuration CompactFlash

Storage (8 bits)

High Z

Write

Byte

Access

Don’t

Care

Even

Byte

Configuration CompactFlash

Storage (8 bits)

Read Word Access CIS (16

bits)

Even

Byte

L²

Not Valid

Write Word Access CIS (16

bits) (Invalid)

Don’t

Care

Even

Byte

Read

Word

Access

Even

Byte

Configuration CompactFlash

Storage (16 bits)

L²

Not Valid

Write

Word

Access

Don’t

Care

Even

Byte

Configuration CompactFlash

Storage (16 bits)

L²

Notes: 1) In UDMA operation, the -REG (-DMACK) signal shall be asserted only in response to -DMARQ.

2) The -CE signals or both the -OE signal and the -WE signal shall be de-asserted between consecutive cycle operations.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Configuration Option Register (Base + 00h in Attribute Memory)

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Card Configuration and Status Register (Base + 02h in Attribute Memory)

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Pin Replacement Register (Base + 04h in Attribute Memory)

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Socket and Copy Register (Base + 06h in Attribute Memory)

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

I/O Transfer Function

The I/O transfer to or from the CompactFlash Storage can be either 8 or 16 bits. When a 16 bit accessible port

is addressed, the signal -IOIS16 is asserted by the CompactFlash Storage. Otherwise, the -IOIS16 signal is

de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the CompactFlash

Storage, the system shall generate a pair of 8 bit references to access the word‘s even byte and odd byte. The

CompactFlash Storage Card permits both 8 and 16 bit accesses to all of its I/O addresses, so -IOIS16 is

asserted for all addresses to which the CompactFlash Storage responds. The CompactFlash Storage Card

may request the host to extend the length of an input cycle until data is ready by asserting the -WAIT signal at

the start of the cycle.

Table: PCMCIA Mode I/O Function

DMA

Function Code

Standby Mode

-REG -CE2 -CE1

-HIOE

-HIOW

D15-D8

High Z

D7-D0

High Z

CMD

UDMA Write

UDMA Read

Write

Read

Odd Byte

Even Byte

High Z

Even-Byte

Odd-Byte

Byte Input Access (8 bits)

Byte Output Access (8 bits)

Don’t Care

Even-Byte

Odd-Byte

Word Input Access (16 bits)

Word Output Access (16 bits)

I/O Read Inhibit

Odd-Byte

Don’t Care

High Z

Even-Byte

Don’t Care

High Z

I/O Write Inhibit

High Byte Input Only (8 bits)

High Byte Output Only (8 bits)

Odd-Byte

High Z

Don’t Care

Transcend Information Inc.

V1.0

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Table: PC Card I/O Mode UDMA Function

-DMARDY STROBE

-DMARQ DMACK STOP

-HIOE

-HIOW (R)-WAIT

(W)

-WAIT

(R)-HIOE CMD

(W)

DMA

A10-

A00

-CE2 -CE1

Operation

-INPACK

-REG

Standby

Device UDMA Transfer Request

(Assert DMARQ)

YES

Host Acknowledge Preparation

DMA Acknowledge (Stopped)

Burst Initiation / Active

Static

/ or \

0 or 1

Burst Transfer

Data In Burst Host Pause

Data In Burst Device Pause

Data Out Burst Device Pause

Data Out Burst Host Pause

0 or 1

Static

Device Initiating BurstTermination

Host Acknowledement of Device

Initiated Burst Termination

0 or 1

YES

Static

Host Initiating BurstTermination

Device Acknowledging Host Initiated

Burst Termination

Device Aligning STROBE to Asserted

before CRC Transfer

YES

Static

CRC Data Transfer for UDMA Burst

Burst Completed

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Common Memory Transfer Function

The Common Memory transfer to or from the CompactFlash Storage can be either 8 or 16 bits.

Table: Common Memory Function

Function Code

DMA

-REG -CE2 -CE1 A0

-OE

-WE

D15-D8

D7-D0

Standby Mode

None

High Z

Don’t

Care

High Z

Even-Byte

Odd-Byte

Byte Read (8 bits)

Byte Write (8 bits)

Word Read (16 bits)

Word Write (16 bits)

Don’t

Care

Don’t Care

Even-Byte

Odd-Byte

Don’t

Care

Odd-Byte

Even-Byte

Don’t

Care

Don’t

Care

Odd Byte Read Only (8 bits)

Odd Byte Write Only (8 bits)

Odd-Byte

High Z

Don’t

Care

Don’t Care

Ultra DMA Write

Ultra DMA Read

Write

Read

Odd-Byte

Even-Byte

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

True IDE Mode I/O Transfer Function

The CompactFlash Storage Card can be configured in a True IDE Mode of operation. The CompactFlash Storage

Card is configured in this mode only when the -OE input signal is grounded by the host during the power off to

power on cycle. Optionally, CompactFlash Storage Cards may support the following optional detection methods:

1. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to PCMCIA mode upon

detecting a high level on the pin.

2. The card is permitted to re-arbitrate the interface mode determination following a transition of the (-)RESET pin.

3. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to True IDE mode upon

detection of a continuous low level on pin for an extended period of time.

Table: True IDE Mode I/O Function defines the function of the operations for the True IDE Mode.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Host Configuration Requirements for Master/Slave or New Timing Modes

The CF Advanced Timing modes include PCMCIA PC Card style I/O modes that are faster than the original 250

ns cycle time. These modes are not supported by the PCMCIA PC Card specification nor CF by cards based on

revisions of the CF specification before Revision 3.0. Hosts shall ensure that all cards accessed through a

common electrical interface are capable of operation at the desired, faster than 250 ns, I/O mode before

configuring the interface for that I/O mode.

Advanced Timing modes are PCMCIA PC Card style I/O modes that are 100 ns or faster, PC Card Memory

modes that are 100ns or faster, True IDE PIO Modes 5,6 and Multiword DMA Modes 3,4. These modes are

permitted to be used only when a single card is present and the host and card are connected directly, without a

cable exceeding 0.15m in length. Consequently, the host shall not configure a card into an Advanced Timing

Mode if two cards are sharing I/O lines, as in Master/Slave operation, nor if it is constructed such that a cable

exceeding 0.15 meters is required to connect the host to the card.

The load presented to the Host by cards supporting Ultra DMA is more controlled than that presented by other

CompactFlash cards. Therefore, the use of a card that does not support Ultra DMA in a Master/Slave

arrangement with a Ultra DMA card can affect the critical timing of the Ultra DMA transfers. The host shall not

configure a card into Ultra DMA mode when a card not supporting Ultra DMA is also present on the same

interface

When the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported

by both cards, but to achieve maximum performance it should use its highest performance mode that is also

supported by both cards.

Metaformat Overview

The goal of the Metaformat is to describe the requirements and capabilities of the CompactFlash Storage Card as

thoroughly as possible. This includes describing the power requirements, IO requirements, memory requirements,

manufacturer information and details about the services provided.

Table: Sample Device Info Tuple Information for Extended Speeds

Note: The value “1” defined for D3 of the N+0 words indicates that no write-protect switch controls writing the ATA

registers. The value “0” defined for D7 in the N+2 words indicates that there is not more than a single speed

extension byte.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

CF-ATA Drive Register Set Definition and Protocol

The CompactFlash Storage Card can be configured as a high performance I/O device through:

a) The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h

(secondary) with IRQ 14 (or other available IRQ).

b) Any system decoded 16 byte I/O block using any available IRQ.

c) Memory space.

The communication to or from the CompactFlash Storage Card is done using the Task File registers, which

provide all the necessary registers for control and status information related to the storage medium. The PCMCIA

interface connects peripherals to the host using four register mapping methods. Table 39 is a detailed description

of these methods:

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

I/O Primary and Secondary Address Configurations

Table: Primary and Secondary I/O Decoding

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Contiguous I/O Mapped Addressing

When the system decodes a contiguous block of I/O registers to select the CompactFlash Storage Card, the

registers are accessed in the block of I/O space decoded by the system as follows:

Table: Contiguous I/O Decoding

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Memory Mapped Addressing

When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the

common memory space window: 0-2K bytes as follows:

ꢁ

True IDE Mode Addressing

When the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows:

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the

CompactFlash device. These registers are often collectively referred to as the “task file.”

ꢂ

Data Register (Address - 1F0h[170h];Offset 0,8,9)

The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash

Storage Card data buffer and the Host. This register overlaps the Error Register.

Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)

This register contains additional information about the source of an error when an error is indicated in bit 0

of the Status register.

This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with

-CE2 low and -CE1 high.

Bit 7 (BBK/ICRC): this bit is set when a Bad Block is detected. This bit is also set when an interface CRC

error is detected in True IDE Ultra DMA modes of operation.

Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.

Bit 5: this bit is 0.

Bit 4 (IDNF): the requested sector ID is in error or cannot be found.

Bit 3: this bit is 0.

Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card

status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued.

Bit 1 This bit is 0.

Bit 0 (AMNF) This bit is set in case of a general error.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢂ

Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only)

This register provides information regarding features of the CompactFlash Storage Card that the host can

utilize. This register is also accessed in PC Card modes on data bits D15-D8 during a write operation to

Offset 0 with -CE2 low and -CE1 high.

ꢂ

Sector Count Register (Address - 1F2h[172h]; Offset 2)

This register contains the numbers of sectors of data requested to be transferred on a read or write

operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a count

of 256 sectors is specified. If the command was successful, this register is zero at command completion. If

not successfully completed, the register contains the number of sectors that need to be transferred in order

to complete the request.

ꢂ

Sector Number (LBA 7-0) Register (Address - 1F3h[173h]; Offset 3)

This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any

CompactFlash Storage Card data access for the subsequent command.

6.1.5.5 Cylinder Low (LBA 15-8) Register (Address - 1F4h[174h]; Offset 4)

This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block

Address.

Cylinder High (LBA 23-16) Register (Address - 1F5h[175h]; Offset 5)

This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block

Address.

Drive/Head (LBA 27-24) Register (Address 1F6h[176h]; Offset 6)

The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing

instead of cylinder/head/sector addressing.

Bit 7: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become

obsolete in a future revision of the specification. This bit is ignored by some controllers in some

commands.

Bit 6: LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA).

When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is

selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:

LBA7-LBA0: Sector Number Register D7-D0.

LBA15-LBA8: Cylinder Low Register D7-D0.

LBA23-LBA16: Cylinder High Register D7-D0.

LBA27-LBA24: Drive/Head Register bits HS3-HS0.

Bit 5: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become

obsolete in a future revisions of the specification. This bit is ignored by some controllers in some

commands.

Bit 4 (DRV): DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card)

1 is selected. Setting this bit to 1 is obsolete in PCMCIA modes of operation. If the obsolete functionality

is support by a CF Storage Card, the CompactFlash Storage Card is set to be Card 0 or 1 using the

copy field (Drive #) of the PCMCIA Socket & Copy configuration register.

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Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27

in the Logical Block Address mode.

Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26

in the Logical Block Address mode.

Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25

in the Logical Block Address mode.

Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24

in the Logical Block Address mode.

ꢂ

Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh)

These registers return the CompactFlash Storage Card status when read by the host. Reading

the Status register does clear a pending interrupt while reading the Auxiliary Status register does

not. The status bits are described as follows:

Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer

and registers and the host is locked out from accessing the command register and buffer. No other bits

in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card

shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.

Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card

operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is

ready to accept a command.

Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.

Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be

transferred either to or from the host through the Data register. During the data transfer of DMA

commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set

to one.

Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been

corrected. This condition does not terminate a multi-sector read operation.

Bit 1 (IDX): This bit is always set to 0.

Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the

Error register contain additional information describing the error. It is recommended that media access

commands (such as Read Sectors and Write Sectors) that end with an error condition should have the

address of the first sector in error in the command block registers.

Transcend Information Inc.

V1.0

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ꢂ

Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft

reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk

controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a

hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from

the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and

Status Register. This bit is set to 0 at power on and Reset.

Bit 0: this bit is ignored by the CompactFlash Storage Card.

Transcend Information Inc.

V1.0

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ꢂ

Card (Drive) Address Register (Address 3F7h[377h]; Offset Fh)

This register is provided for compatibility with the AT disk drive interface. It is recommended that this register

not be mapped into the host’s I/O space because of potential conflicts on Bit 7.

Bit 7: this bit is unknown.

Implementation Note:

Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller

operating at the same addresses as the CompactFlash Storage Card. Following are some possible

solutions to this problem for the PCMCIA implementation:

1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address

(377) or in an independently decoded Address Space when a Floppy Disk Controller is located at

the Primary addresses.

2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.

3) Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address

3F7h/377h when a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of

I/O address 3F7h/377h when a floppy controller is installed.

4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished

by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h

(or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional

Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to

accesses to I/O locations 3F7h and 377h. With either of these implementations, the host software

shall not attempt to use information in the Drive Address Register.

Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1.

Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.

Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.

Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.

Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.

Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.

Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

CF-ATA Command Set

CF-ATA Command Set summarizes the CF-ATA command set with the paragraphs that follow describing the

individual commands and the task file for each.

Command

Code

E5 or 98h

90h

–

LBA

–

Status

Support

Note

Check Power Mode

Execute Drive Diagnostic

Erase Sector

–

Support

C0h

–

Flush Cache

E7h

–

Format Track

50h

–

Identify Device

Idle

ECh

–

E3h or 97h

E1h or 95h

91h

–

Idle Immediate

Initialize Drive Parameters

–

Key Management

Structure Read

B9 (Feature

0-127)

–

NOT Support #1

Key Management Read

Keying Material

B9 (Feature

80)

Key Management Change

Key Management Value

B9 (Feature

81)

13 NOP

00h

–

Support

14 Read Buffer

15 Read DMA

E4h

Support

C8h

–

Support

16 Read Long Sector

17 Read Multiple

18 Read Sector(s)

19 Read Verify Sector(s)

20 Recalibrate

22h or 23h

C4h

NOT Support #2

Support

–

20h or 21h

40h or 41h

1Xh

Support

–

Support

21 Request Sense

03h

–

Support

Seek

7Xh

–

Support

Set Feature

EFh

–

Set Multiple Mode

Set Sleep Mode

Standby

C6h

E6h or 99h

E2 or 96h

E0 or 94h

Standby Immediate

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Security Disable Password F6h

–

Not Support

29 Security Erase Prepare

30 Security Erase Unit

31 Security Freeze Lock

32 Security Set Password

33 Security Unlock

34 Translate Sector

35 Wear Level

F3h

–

Not Support

Support

F4h

F5h

–

F1h

–

F2h

–

87h

–

F5h

Support

36 Write Buffer

E8h

–

Support

37 Write DMA

CAh

–

Support

38 Write Long Sector

39 Write Multiple

32h or 33h

C5h

Not Support

Support

40 Write Multiple w/o Erase

41 Write Sector(s)

CDh

30h or 31h

38h

42 Write Sector(s) w/o Erase

43 Write Verify

3Ch

#1: This command is optional, depending on the key Management scheme in use.

#2: Use of this command is not recommended by CFA.

Definitions

FR = Features Register

SC =Sector Count register (00H to FFH, 00H means 256 sectors)

SN = Sector Number register

CY = Cylinder Low/High register

DH = Head No. (0 to 15) of Drive/Head register

LBA = Logic Block Address Mode Support

– = Not used for the command

Y = Used for the command

Transcend Information Inc.

V1.0

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600X CompactFlash Card

ꢁ

Check Power Mode - 98h or E5h

If the CompactFlash Storage Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage

Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt.

If the CompactFlash Storage Card is in Idle mode, the CompactFlash Storage Card sets BSY, sets the Sector

Count Register to FFh, clears BSY and generates an interrupt.

Bit ->

Command (7)

C/D/H (6)

98h or E5h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

ꢁ

Execute Drive Diagnostic - 90h

When the diagnostic command is issued in a PCMCIA configuration mode, this command runs only on the

CompactFlash Storage Card that is addressed by the Drive/Head register. This is because PCMCIA card interface

does not allows for direct inter-drive communication (such as the ATA PDIAG and DASP signals). When the

diagnostic command is issued in the True IDE Mode, the Drive bit is ignored and the diagnostic command is

executed by both the Master and the Slave with the Master responding with status for both devices.

Bit ->

Command (7)

C/D/H (6)

90h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Diagnostic Codes are returned in the Error Register at the end of the command.

Code

01h

02h

03h

04h

05h

8Xh

Error Type

No Error Detected

Formatter Device Error

Sector Buffer Error

ECC Circuitry Error

Controlling Microprocessor Error

Slave Error in True IDE Mode

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Erase Sector(s) - C0h

This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write

Multiple without Erase command. There is no data transfer associated with this command but a Write Fault error

status can occur.

Bit ->

Command (7)

C/D/H (6)

C0h

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

Sector Count

ꢁ

Flush Cache – E7h

This command causes the card to complete writing data from its cache. The card returns status with RDY=1 and

DSC=1 after the data in the write cache buffer is written to the media. If the Compact Flash Storage Card does not

support the Flush Cache command, the Compact Flash Storage Card shall return command aborted.

Bit ->

Command (7)

C/D/H (6)

E7h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

ꢁ

Format Track - 50h

This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern

(typically FFh or 00h). To remain host backward compatible, the CompactFlash Storage Card expects a sector

buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command

although the information in the buffer is not used by the CompactFlash Storage Card. If LBA=1 then the number of

sectors to format is taken from the Sec Cnt register (0=256). The use of this command is not recommended.

Bit ->

Command (7)

C/D/H (6)

50h

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

X (LBA 7-0)

Count (LBA mode only)

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Identify Device – Ech

Bit ->

Command (7)

C/D/H (6)

ECh

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

The Identify Device command enables the host to receive parameter information from the

CompactFlash Storage Card. This command has the same protocol as the Read Sector(s) command. The

parameter words in the buffer have the arrangement and meanings defined in Table as below. All reserved

bits or words are zero. Hosts should not depend on Obsolete words in Identify Device containing 0. Table 47

specifies each field in the data returned by the Identify Device Command. In Table as below, X indicates a

numeric nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive.

Word

Address

Default

Value

Total

Bytes

Data Field Type Information

848Ah

0XXX

General configuration - signature for the CompactFlash Storage Card

General configuration – Bit Significant with ATA-4 definitions.

XXXXh

0000h

00XXh

0000h

XXXXh

0002h

0004h

XXXXh

8001h

0000h

0200h

0000h

Default number of cylinders

Reserved

Default number of heads

Obsolete

Default number of sectors per track

7-8

Number of sectors per card (Word 7 = MSW, Word 8 = LSW)

Obsolete

10-19

23-26

27-46

Serial number in ASCII (Right Justified)

Obsolete

Number of ECC bytes passed on Read/Write Long Commands

Firmware revision in ASCII. Big Endian Byte Order in Word

Model number in ASCII (Left Justified) Big Endian Byte Order in Word

Maximum number of sectors on Read/Write Multiple command

Reserved

Capabilities

Reserved

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V1.0

TS8G~16GCF600

600X CompactFlash Card

Word

Address

Default

Value

Total

Bytes

Data Field Type Information

PIO data transfer cycle timing mode

0200h

0000h

000Xh

XXXXh

01XXh

XXXXh

0000h

0007h

0003h

Obsolete

Field Validity

Current numbers of cylinders

Current numbers of heads

Current sectors per track

57-58

Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW)

Multiple sector setting

60-61

Total number of sectors addressable in LBA Mode

Reserved

Multiword DMA transfer. In PC Card modes this value shall be 0h

Advanced PIO modes supported

Minimum Multiword DMA transfer cycle time per word. In PC Card modes this value

shall be 0h

0078h

Recommended Multiword DMA transfer cycle time. In PC Card modes this

value shall be 0h

0078h

0000h

7028h

500Ch

4000h

XXXXh

007Fh

XXXXh

0000h

XXXXh

0000h

81F4h

0000h

Minimum PIO transfer cycle time without flow control

Minimum PIO transfer cycle time with IORDY flow control

Reserved

69-79

Major version number

Minor version number

Command sets supported

Command sets enabled

Ultra DMA Mode Supported and Selected

Time required for Security erase unit completion

Time required for Enhanced security erase unit completion

Current Advanced power management value

Master password revision code

Reserved

93-127

128

129-159

160

161

Security status

Vendor unique bytes

Power requirement description

Reserved

Transcend Information Inc.

V1.0

TS8G~16GCF600

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162

163

0000h

0092h

8D9Bh

0000h

Key management schemes supported

CF Advanced True IDE Timing Mode Capability and Setting

164

CF Advanced PC Card I/O and Memory Timing Mode Capability

165-175

176-255

140

Reserved

ꢂ

Word 0: General Configuration

This field indicates the general characteristics of the device. When Word 0 of the Identify drive information

is 848Ah then the device is a CompactFlash Storage Card and complies with the CFA specification and

CFA command set. It is recommended that PCMCIA modes of operation report only the 848Ah value as

they are always intended as removable devices.

Bits 15-0: CF Standard Configuration Value

Word 0 is 848Ah. This is the recommended value of Word 0.

Some operating systems require Bit 6 of Word 0 to be set to 1 (Non-removable device) to use the card as

the root storage device. The Card must be the root storage device when a host completely replaces

conventional disk storage with a CompactFlash Card in True IDE mode. To support this requirement and

provide capability for any future removable media Cards, alternatehandling of Word 0 is permitted.

Bits 15-0: CF Preferred Alternate Configuration Values

044Ah: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and

Removable Device while preserving all Retired bits in the word.

0040h: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and

Removable Device while zeroing all Retired bits in the word

Bit 15-12: Configuration Flag

If bits 15:12 are set to 8h then Word 0 shall be 848Ah.

If bits 15:12 are set to 0h then Bits 11:0 are set using the definitions below and the Card is required to

support for the CFA command set and report that in bit 2 of Word 83.

Bit 15:12 values other than 8h and 0h are prohibited.

Bits 11-8: Retired

These bits have retired ATA bit definitions. It is recommended that the value of these bits be either the

preferred value of 0h or the value of 4h that preserves the corresponding bits from the 848Ah CF signature

value.

Bit 7: Removable Media Device

If Bit 7 is set to 1, the Card contains media that can be removed during Card operation.

If Bit 7 is set to 0, the Card contains nonremovable media.

Bit 6: Not Removable Controller and/or Device

Alert! This bit will be considered for obsolescence in a future revision of this standard.

If Bit 6 is set to 1, the Card is intended to be nonremovable during operation.

If Bit 6 is set to 0, the Card is intended to be removable during operation.

Bits 5-0: Retired/Reserved

Alert! Bit 2 will be considered for definition in a future revision of this standard and shall be 0 at this

time.

Bits 5-1 have retired ATA bit definitions.

Bit 2 shall be 0.

Bit 0 is Reserved and shall be 0.

It is recommended that the value of bits 5-0 be either the preferred value of 00h or the value of 0Ah that

preserves the corresponding bits from the 848Ah CF signature value.

Transcend Information Inc.

V1.0

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600X CompactFlash Card

ꢂ

Word 1: Default Number of Cylinders

This field contains the number of translated cylinders in the default translation mode. This value will be the

same as the number of cylinders.

ꢂ

Word 3: Default Number of Heads

This field contains the number of translated heads in the default translation mode.

ꢂ

Word 6: Default Number of Sectors per Track

This field contains the number of sectors per track in the default translation mode.

Words 7-8: Number of Sectors per Card

This field contains the number of sectors per CompactFlash Storage Card. This double word

value is also the first invalid address in LBA translation mode.

ꢂ

Words 10-19: Serial Number

This field contains the serial number for this CompactFlash Storage Card and is right justified and padded

with spaces (20h).

Word 22: ECC Count

This field defines the number of ECC bytes used on each sector in the Read and Write Long commands.

This value shall be set to 0004h.

ꢂ

Words 23-26: Firmware Revision

This field contains the revision of the firmware for this product.

Words 27-46: Model Number

This field contains the model number for this product and is left justified and padded with spaces (20h).

Word 47: Read/Write Multiple Sector Count

Bits 15-8 shall be the recommended value of 80h or the permitted value of 00h. Bits 7-0 of this word define

the maximum number of sectors per block that the CompactFlash Storage Card supports for Read/Write

Multiple commands.

ꢂ

Word 49: Capabilities

Bit 13: Standby Timer

If bit 13 is set to 1 then the Standby timer is supported as defined by the IDLE command

If bit 13 is set to 0 then the Standby timer operation is defined by the vendor.

Bit 11: IORDY Supported

If bit 11 is set to 1 then this CompactFlash Storage Card supports IORDY operation.

If bit 11 is set to 0 then this CompactFlash Storage Card may support IORDY operation.

Bit 10: IORDY may be disabled

Bit 10 shall be set to 0, indicating that IORDY may not be disabled.

Bit 9: LBA supported

Bit 9 shall be set to 1, indicating that this CompactFlash Storage Card supports LBA mode addressing. CF

devices shall support LBA addressing.

Bit 8: DMA Supported If bit 8 is set to 1 then Read DMA and Write DMA commands are supported. Bit 8

shall be set to 0. Read/Write DMA commands are not currently permitted on CF cards.

ꢂ

PIO Data Transfer Cycle Timing Mode

The PIO transfer timing for each CompactFlash Storage Card falls into modes that have unique parametric

timing specifications. The value returned in Bits 15-8 shall be 00h for mode 0, 01h for mode 1, or 02h for

mode 2. Values 03h through FFh are reserved.

Translation Parameters Valid

Bit 0 shall be set to 1 indicating that words 54 to 58 are valid and reflect the current number of cylinders,

heads and sectors. If bit 1 of word 53 is set to 1, the values in words 64 through 70 are valid. If this bit is

cleared to 0, the values reported in words 64-70 are not valid. Any CompactFlash Storage Card that

supports PIO mode 3 or above shall set bit 1 of word 53 to one and support the fields contained in words

Transcend Information Inc.

V1.0

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64 through 70.

ꢂ

Current Number of Cylinders, Heads, Sectors/Track

These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the

current translation mode.

Current Capacity

This field contains the product of the current cylinders times heads times sectors.

ꢂ

Multiple Sector Setting

Bits 15-9 are reserved and shall be set to 0.

Bit 8 shall be set to 1 indicating that the Multiple Sector Setting is valid.

Bits 7-0 are the current setting for the number of sectors that shall be transferred per interrupt on

Read/Write Multiple commands.

ꢂ

Total Sectors Addressable in LBA Mode

This field contains the total number of user addressable sectors for the CompactFlash Storage Card in

LBA mode only.

Multiword DMA transfer

Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA

mode selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.

Only one of bits may be set to one in this field by the CompactFlash Storage Card to indicate the multiword

DMA mode which is currently selected. Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one,

indicates that Multiword DMA mode 0 has been selected. Bit 9, if set to one, indicates that Multiword DMA

mode 1 has been selected. Bit 10, if set to one, indicates that Multiword DMA mode 2 has been selected.

Selection of Multiword DMA modes 3 and above are specific to CompactFlash are reported in word 163,

Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings.

Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA

data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit

significant. Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate

the Multiword DMA modes it is capable of supporting.

Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage

Card supports Multiword DMA mode 0. Bit 1, if set to one, indicates that the CompactFlash Storage Card

supports Multiword DMA modes 1 and 0. Bit 2, if set to one, indicates that the CompactFlash Storage Card

supports Multiword DMA modes 2, 1 and 0. Support for Multiword DMA modes 3 and above are specific to

CompactFlash are reported in word 163, Word 163: CF Advanced True IDE Timing Mode Capabilities and

Settings.

ꢂ

Word 64: Advanced PIO transfer modes supported

Bits 7 through 0 of word 64 of the Identify Device parameter information is defined as the advanced PIO

data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit

significant. Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate

the advanced PIO modes it is capable of supporting.

Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage

Card supports PIO mode 3. Bit 1, if set to one, indicates that the CompactFlash StorageCard supports PIO

mode 4.

Support for PIO modes 5 and above are specific to CompactFlash are reported in word 163.

Word 65: Minimum Multiword DMA transfer cycle time

Word 65 of the parameter information of the Identify Device command is defined as the minimum

Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if

used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer.

If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the

minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

CompactFlash Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this

field is not supported, the Card shall return a value of zero in this field.

ꢂ

Recommended Multiword DMA transfer cycle time

Word 66 of the parameter information of the Identify Device command is defined as the recommended

Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the

host, may optimize the data transfer from by reducing the probability that the CompactFlash Storage Card

will need to negate the DMARQ signal during the transfer of a sector.

If this field is supported, bit 1 of word 53 shall be set to one. The value in word 66 shall not be less than the

value in word 65. This field shall be supported by all CompactFlash Storage Cards supporting DMA modes

1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a value of

zero in this field.

Word 67: Minimum PIO transfer cycle time without flow control

Word 67 of the parameter information of the Identify Device command is defined as the minimum PIO

transfer without flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if

used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer without

utilization of flow control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash

Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not

be less than the value reported in word 68. If bit 1 of word 53 is set to one because a CompactFlash

Storage Card supports a field in words 64-70 other than this field and the CompactFlash Storage Card

does not support this field, the CompactFlash Storage Card shall return a value of zero in this field.

Word 68: Minimum PIO transfer cycle time with IORDY

Word 68 of the parameter information of the Identify Device command is defined as the minimum PIO

transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time

that the CompactFlash Storage Card supports while performing data transfers while utilizing IORDY flow

control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash Storage Card that

supports PIO mode 3 or above shall support this field, and the value in word 68 shall be the fastest defined

PIO mode supported by the CompactFlash Storage Card. If bit 1 of word 53 is set to one because a

CompactFlash Storage Card supports a field in words 64-70 other than this field and the CompactFlash

Storage Card does not support this field, the CompactFlash Storage Card shall return a value of zero in

this field.

ꢂ

Words 82-84: Features/command sets supported

Words 82, 83, and 84 shall indicate features/command sets supported. The value 0000h or FFFFh was

placed in each of these words by CompactFlash Storage Cards prior to ATA-3 and shall be interpreted by

the host as meaning that features/command sets supported are not indicated. Bits 1 through 13 of word 83

and bits 0 through 13 of word 84 are reserved. Bit 14 of word 83 and word 84 shall be set to one and bit 15

of word 83 and word 84 shall be cleared to zero to provide indication that the features/command sets

supported words are valid. The values in these words should not be depended on by host implementers.

Bit 0 of word 82 shall be set to zero; the SMART feature set is not supported.

If bit 1 of word 82 is set to one, the Security Mode feature set is supported.

Bit 2 of word 82 shall be set to zero; the Removable Media feature set is not supported.

Bit 3 of word 82 shall be set to one; the Power Management feature set is supported.

Bit 4 of word 82 shall be set to zero; the Packet Command feature set is not supported.

If bit 5 of word 82 is set to one, write cache is supported.

If bit 6 of word 82 is set to one, look-ahead is supported.

Bit 7 of word 82 shall be set to zero; release interrupt is not supported.

Bit 8 of word 82 shall be set to zero; Service interrupt is not supported.

Bit 9 of word 82 shall be set to zero; the Device Reset command is not supported.

Bit 10 of word 82 shall be set to zero; the Host Protected Area feature set is not supported.

Bit 11 of word 82 is obsolete.

Bit 12 of word 82 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command.

Bit 13 of word 82 shall be set to one; the CompactFlash Storage Card supports the Read Buffer command.

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Bit 14 of word 82 shall be set to one; the CompactFlash Storage Card supports the NOP command.

Bit 15 of word 82 is obsolete.

Bit 0 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Download

Microcode command.

Bit 1 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA

Queued and Write DMA Queued commands.

Bit 2 of word 83 shall be set to one; the CompactFlash Storage Card supports the CFA feature set.

If bit 3 of word 83 is set to one, the CompactFlash Storage Card supports the Advanced Power

Management feature set.

Bit 4 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Removable

Media Status feature set.

ꢂ

Words 85-87: Features/command sets enabled

Words 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was

placed in each of these words by CompactFlash Storage Cards prior to ATA-4 and shall be interpreted by

the host as meaning that features/command sets enabled are not indicated. Bits 1 through 15 of word 86

are reserved. Bits 0-13 of word 87 are reserved. Bit 14 of word 87 shall be set to one and bit 15 of word 87

shall be cleared to zero to provide indication that the features/command sets enabled words are valid. The

values in these words should not be depended on by host implementers.

Bit 0 of word 85 shall be set to zero; the SMART feature set is not enabled.

If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the Security Set

Password command.

Bit 2 of word 85 shall be set to zero; the Removable Media feature set is not supported.

Bit 3 of word 85 shall be set to one; the Power Management feature set is supported.

Bit 4 of word 85 shall be set to zero; the Packet Command feature set is not enabled.

If bit 5 of word 85 is set to one, write cache is enabled.

If bit 6 of word 85 is set to one, look-ahead is enabled.

Bit 7 of word 85 shall be set to zero; release interrupt is not enabled.

Bit 8 of word 85 shall be set to zero; Service interrupt is not enabled.

Bit 9 of word 85 shall be set to zero; the Device Reset command is not supported.

Bit 10 of word 85 shall be set to zero; the Host Protected Area feature set is not supported.

Bit 11 of word 85 is obsolete.

Bit 12 of word 85 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command.

Bit 13 of word 85 shall be set to one; the CompactFlash Storage Card supports the Read Buffer command.

Bit 14 of word 85 shall be set to one; the CompactFlash Storage Card supports the NOP command.

Bit 15 of word 85 is obsolete.

Bit 0 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Download

Microcode command.

Bit 1 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA

Queued and Write DMA Queued commands.

If bit 2 of word 86 shall be set to one, the CompactFlash Storage Card supports the CFA feature set.

If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the Set

Features command.

Bit 4 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Removable

Media Status feature set.

ꢂ

Word 88: Ultra DMA Modes Supported and Selected

Word 88 identifies the Ultra DMA transfer modes supported by the device and indicates the mode that is

currently selected. Only one DMA mode shall be selected at any given time. If an Ultra DMA mode is

selected, then no Multiword DMA mode shall be selected. If a Multiword DMA mode is selected, then no

Ultra DMA mode shall be selected. Support of this word is mandatory if Ultra DMA is supported.

Bits 15: Reserved

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Bit 14: 1 = Ultra DMA mode 6 is selected, 0 = Ultra DMA mode 6 is not selected

Bit 13: 1 = Ultra DMA mode 5 is selected, 0 = Ultra DMA mode 5 is not selected

Bit 12: 1 = Ultra DMA mode 4 is selected, 0 = Ultra DMA mode 4 is not selected

Bit 11: 1 = Ultra DMA mode 3 is selected, 0 = Ultra DMA mode 3 is not selected

Bit 10: 1 = Ultra DMA mode 2 is selected, 0 = Ultra DMA mode 2 is not selected

Bit 9: 1 = Ultra DMA mode 1 is selected, 0 = Ultra DMA mode 1 is not selected

Bit 8: 1 = Ultra DMA mode 0 is selected, 0 = Ultra DMA mode 0 is not selected

Bits 7: Reserved

Bit 6: 1 = Ultra DMA mode 6 and below are supported. Bits 0-5 Shall be set to 1.

Bit 5: 1 = Ultra DMA mode 5 and below are supported. Bits 0-4 Shall be set to 1.

Bit 4: 1 = Ultra DMA mode 4 and below are supported. Bits 0-3 Shall be set to 1.

Bit 3: 1 = Ultra DMA mode 3 and below are supported, Bits 0-2 Shall be set to 1.

Bit 2: 1 = Ultra DMA mode 2 and below are supported. Bits 0-1 Shall be set to 1.

Bit 1: 1 = Ultra DMA mode 1 and below are supported. Bit 0 Shall be set to 1.

Bit 0: 1 = Ultra DMA mode 0 is supported

ꢂ

Word 89: Time required for Security erase unit completion

Word 89 specifies the time required for the Security Erase Unit command to complete. This command

shall be supported on CompactFlash Storage Cards that support security.

Value

Time

Value not specified

(Value * 2) minutes

>508 minutes

1-254

255

Word 90: Time required for Enhanced security erase unit completion

Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete.

This command shall be supported on CompactFlash Storage Cards that support security.

Value

Time

Value not specified

(Value * 2) minutes

>508 minutes

1-254

255

ꢂ

Word 91: Advanced power management level value

Bits 7-0 of word 91 contain the current Advanced Power Management level setting.

Word 128: Security Status

Bit 8: Security Level

If set to 1, indicates that security mode is enabled and the security level is maximum.

If set to 0 and security mode is enabled, indicates that the security level is high.

Bit 5: Enhanced security erase unit feature supported

If set to 1, indicates that the Enhanced security erase unit feature set is supported.

Bit 4: Expire

If set to 1, indicates that the security count has expired and Security Unlock and Security Erase Unit are

command aborted until a power-on reset or hard reset.

Bit 3: Freeze

If set to 1, indicates that the security is Frozen.

Bit 2: Lock

If set to 1, indicates that the security is locked.

Bit 1: Enable/Disable

If set to 1, indicates that the security is enabled.

If set to 0, indicates that the security is disabled.

Bit 0: Capability

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

If set to 1, indicates that CompactFlash Storage Card supports security mode feature set.

If set to 0, indicates that CompactFlash Storage Card does not support security mode feature set.

ꢂ

Word 160: Power Requirement Description

This word is required for CompactFlash Storage Cards that support power mode 1.

Bit 15: VLD

If set to 1, indicates that this word contains a valid power requirement description.

If set to 0, indicates that this word does not contain a power requirement description.

Bit 14: RSV

This bit is reserved and shall be 0.

Bit 13: -XP

If set to 1, indicates that the CompactFlash Storage Card does not have Power Level 1 commands.

If set to 0, indicates that the CompactFlash Storage Card has Power Level 1 commands

Bit 12: -XE

If set to 1, indicates that Power Level 1 commands are disabled.

If set to 0, indicates that Power Level 1 commands are enabled.

Bit 0-11: Maximum current

This field contains the CompactFlash Storage Card’s maximum current in mA.

ꢂ

Word 162: Key Management Schemes Supported

Bit 0: CPRM support

If set to 1, the device supports CPRM Scheme (Content Protection for Recordable Media)

If set to 0, the device does not support CPRM.

Bits 1-15 are reserved for future additional Key Management schemes.

Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings

This word describes the capabilities and current settings for CFA defined advanced timing modes using

the True IDE interface.

Notice! The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above

impose significant restrictions on the implementation of the host:

Additional Requirements for CF Advanced Timing Modes.

There are four separate fields defined that describe support and selection of Advanced PIO timing modes

and Advanced Multiword DMA timing modes. The older modes are reported in words 63 and 64.

Word 63: Multiword DMA transfer and 6.2.1.6.19: Word 64: Advanced PIO transfer modes supported.

Bits 2-0: Advanced True IDE PIO Mode Support Indicates the maximum True IDE PIO mode supported by

the card.

Value

Maximum PIO mode timing selected

Specified in word 64

PIO Mode 5

PIO Mode 6

3-7

Reserved

Bits 5-3: Advanced True IDE Multiword DMA Mode Support Indicates the maximum True IDE Multiword

DMA mode supported by the card.

Value

Maximum Multiword DMA timing mode supported

Specified in word 63

Multiword DMA Mode 3

Multiword DMA Mode 4

3-7

Reserved

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Bits 8-6: Advanced True IDE PIO Mode Selected Indicates the current True IDE PIO mode selected on the

card.

Value

Current PIO timing mode selected

Specified in word 64

PIO Mode 5

PIO Mode 6

3-7

Reserved

Bits 11-9: Advanced True IDE Multiword DMA Mode Selected Indicates the current True IDE Multiword

DMA Mode Selected on the card.

Value

Current Multiword DMA timing mode selected

Specified in word 63

Multiword DMA Mode 3

Multiword DMA Mode 4

Reserved

3-7

Bits 15-12 are reserved.

ꢂ

Word 164: CF Advanced PCMCIA I/O and Memory Timing Modes Capabilities and Settings

This word describes the capabilities and current settings for CFA defined advanced timing modes using

the Memory and PCMCIA I/O interface.

Notice: The use of PCMCIA I/O or Memory modes that are 100ns or faster impose significant

restrictions on the implementation of the host:

Additional Requirements for CF Advanced Timing Modes.

Bits 2-0: Maximum Advanced PCMCIA I/O Mode Support Indicates the maximum I/O timing mode

supported by the card.

Value

Maximum PCMCIA IO timing mode Supported

255ns Cycle PCMCIA I/O Mode

120ns Cycle PCMCIA I/O Mode

100ns Cycle PCMCIA I/O Mode

80ns Cycle PCMCIA I/O Mode

Reserved

4-7

Bits 5-3: Maximum Memory timing mode supported

Indicates the Maximum Memory timing mode supported by the card.

Value

Maximum Memory timing mode Supported

250ns Cycle Memory Mode

120ns Cycle Memory Mode

100ns Cycle Memory Mode

80ns Cycle Memory Mode

Reserved

4-7

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Bits 8-6: Maximum PC Card I/O UDMA timing mode supported Indicates the Maximum PC Card I/O UDMA

timing mode supported by the card when bit 15 is set.

Value Maximum PC Card I/O UDMA timing mode Supported

PC Card I/O UDMA mode 0 supported

PC Card I/O UDMA mode 1 supported

PC Card I/O UDMA mode 2 supported

PC Card I/O UDMA mode 3 supported

PC Card I/O UDMA mode 4 supported

PC Card I/O UDMA mode 5 supported

PC Card I/O UDMA mode 6 supported

Reserved

Bits 11-9: Maximum PC Card Memory UDMA timing mode supported Indicates the Maximum PC Card

Memory UDMA timing mode supported by the card when bit 15 is set.

Value Maximum PC Card Memory UDMA timing mode Supported

PC Card Memory UDMA mode 0 supported

PC Card Memory UDMA mode 1 supported

PC Card Memory UDMA mode 2 supported

PC Card Memory UDMA mode 3 supported

PC Card Memory UDMA mode 4 supported

PC Card Memory UDMA mode 5 supported

PC Card Memory UDMA mode 6 supported

Reserved

Bits 14-12: PC Card Memory or I/O UDMA timing mode selectedIndicates the PC Card Memory or I/O UDMA

timing mode selected by the card.

Value PC Card Memory or I/O UDMA timing mode Selected

PC Card I/O UDMA mode 0 selected

PC Card I/O UDMA mode 1 selected

PC Card I/O UDMA mode 2 selected

PC Card I/O UDMA mode 3 selected

PC Card I/O UDMA mode 4 selected

PC Card I/O UDMA mode 5 selected

PC Card I/O UDMA mode 6 selected

Reserved

Bit 15: PC Card Memory and IO Modes Supported

This bit, when set, indicates that the PC Card UDMA support values in bits 11-6 are valid. When this bit is

cleared, PC Card Memory and IO Modes are not supported by the device

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Idle - 97h or E3h

This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and

generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5

milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power

down mode is disabled. Note that this time base (5 msec) is different from the ATA specification.

Bit ->

Command (7)

C/D/H (6)

97h or E3h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Timer Count (5 msec increments)

ꢁ

Idle Immediate - 95h or E1h

This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and

generate an interrupt.

Bit ->

Command (7)

C/D/H (6)

95h or E1h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

ꢁ

Initialize Drive Parameters - 91h

This command enables the host to set the number of sectors per track and the number of heads per cylinder.

Only the Sector Count and the Card/Drive/Head registers are used by this command.

Bit ->

Command (7)

C/D/H (6)

91h

Drive

Max Head (no. of heads-1)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Sec Cnt (2)

Feature (1)

Number of Sectors

ꢁ

NOP - 00h

This command always fails with the CompactFlash Storage Card returning command aborted.

Bit ->

Command (7)

C/D/H (6)

00h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

ꢁ

Read Buffer - E4h

The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card’s

sector buffer. This command has the same protocol as the Read Sector(s) command.

Bit ->

Command (7)

C/D/H (6)

E4h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

ꢁ

Read DMA – C8h

ꢁ

Read Long Sector - 22h or 23h

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Read Multiple - C4h

Read Sector(s) - 20h or 21h

Read Verify Sector(s) - 40h or 41h

ꢁ

Recalibrate - 1Xh

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Request Sense - 03h

The extended error code is returned to the host in the Error Register.

ꢁ

Seek - 7Xh

ꢁ

Set Features – EFh

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Feature Supported

Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h

feature command is issued all data transfers shall occur on the low order D[7:0] data bus and the -IOIS16 signal

shall not be asserted for data register accesses. The host shall not enable this feature for DMA transfers.

Features 02h and 82h allow the host to enable or disable write cache in CompactFlash Storage Cards that

implement write cache. When the subcommand disable write cache is issued, the CompactFlash Storage Card

shall initiate the sequence to flush cache to non-volatile memory before command completion.

Feature 03h allows the host to select the PIO or Multiword DMA transfer mode by specifying a value in the

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode

value. One PIO mode shall be selected at all times. For Cards which support DMA, one Multiword DMA mode

shall be selected at all times. The host may change the selected modes by the Set Features command.

ꢁ

Set Multiple Mode - C6h

ꢁ

Set Sleep Mode- 99h or E6h

ꢁ

Standby - 96h or E2h

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Standby Immediate - 94h or E0h

ꢁ

Translate Sector - 87h

Translate Sector Information

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Wear Level - F5h

Write Buffer - E8h

Write DMA – CAh

ꢁ

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Write Long Sector - 32h or 33h

ꢁ

Write Multiple Command - C5h

ꢁ

Write Multiple without Erase – CDh

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Write Sector(s) - 30h or 31h

Write Sector(s) without Erase - 38h

Write Verify - 3Ch

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

ꢁ

Error Posting

Command

Error Register

UNC

Status Register

BBK

IDNF ABRT AMNF DRDY DWF

DSC

CORR ERR

Check Power Mode

Execute Drive Diagnostic1

Erase Sector(s)

Flush Cache

Format Track

Identify Device

Idle

Idle Immediate

Initialize Drive

Parameters

Key Management

Structure Read

Key Management Read

Keying Material

Key Management

Change Key

Management Value

NOP

Read Buffer

Read DMA

Read Multiple

Read Long Sector

Read Sector(s)

Read Verify Sectors

Recalibrate

Request Sense

Security Disable

Password

Security Erase Prepare

Security Erase Unit

Security Freeze Lock

Security Set Password

Security Unlock

Seek

Set Features

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Command

Error Register

UNC

Status Register

BBK

IDNF ABRT AMNF DRDY DWF

DSC

CORR ERR

Set Multiple Mode

Set Sleep Mode

Stand By

Stand By Immediate

Translate Sector

Wear Level

Write Buffer

Write DMA

Write Long Sector

Write Multiple

Write Multiple w/o Erase

Write Sector(s)

Write Sector(s) w/o Erase

Write Verify

Invalid Command Code

Error and Status Register summarizes the valid status and error value for all the CF-ATA Command set.

C.H.S. Table

Capacity

8GB

15538

31045

16GB

Transcend Information Inc.

V1.0

TS8G~16GCF600

600X CompactFlash Card

Ordering Information

TS XG CF600 X-^FS^oX^{rm Factor}

= SLC

-M = MLC

-I = Industrial (SLC)

Transcend Product

Capacity:

CompactFlash Card 600X

8G-16G = 8GB up to 16GB

The above technical information is based on industry standard data and has been tested to be reliable. However,

Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection

with the use of this product. Transcend reserves the right to make changes to the specifications at any time without

prior notice.

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E-mail: sales@transcend.co.jp

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Transcend Information Inc.

V1.0

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