Application Note: Embedded Processing
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Reference System: OPB IIC Using the
ML403 Evaluation Platform
Author: Paul Glover, Ed Meinelt, Lester Sanders
XAPP979 (v1.0) February 26, 2007
Summary
This application note describes how to build a reference system for the On-Chip Peripheral Bus
Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded
system in the ML403 Embedded Development Platform. The reference system is Base System
Builder (BSB) based.
An IIC primer is given and an OPB IIC register reference is provided. The Xilinx Microprocessor
Debugger (XMD) commands are used for verifying that the OPB IIC core operates correctly.
Several software projects illustrate how to configure the OPB IIC core, set up interrupts, and do
read and write operations. Some of the software projects interface the OPB IIC to the
MicroChip 24LC04B serial EEPROM with an IIC interface, while others interface to the
TotalPhase Aardvark Adapter, which provides IIC master and slave functionality. The procedure
for using ChipScope™ to analyze OPB IIC functionality is provided. The steps used to build a
Linux kernel using MontaVista are listed. Simulation output files for analyzing basic IIC
transactions are provided.
Included
Systems
This application note includes one reference system:
The project name used in xapp979.zip is ml403_ppc_opb_iic.
Required
Users must have the following tools, cables, peripherals, and licenses available and installed:
Hardware/Tools
•
•
•
•
•
•
Xilinx EDK 8.2.02i
Xilinx ISE 8.2.03
Xilinx Download Cable (Platform Cable USB or Parallel Cable IV)
Monta Vista Linux v2.4 Development Kit
Modeltech ModelSim v6.1d
ChipScope v8.2
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is
a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
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Introduction
Figure 4 shows the format of the data transfer of two bytes on the IIC bus, beginning with the
START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus.
After a START condition, an eight bit field is transmitted containing a 7 bit address and a single
Read/Write (R/W) bit. This 8 bit address/direction field is followed by an Acknowledge bit. After
the address/data field, an eight bit data field is followed by an acknowledge bit (A). The last 8-
bit data field is followed by a not acknowledge bit (A). This is followed by the STOP condition
(P).
A single message can contain multiple start conditions, or a repeated start, without intervening
STOP conditions.
In this data transfer, there are two acknowledge bits and one Not Acknowledge on the IIC bus.
The distinction between a Not Acknowledge and a No Acknowledge is that Not Acknowledge
occurs after a master has read a byte from a slave and a No Acknowledge occurs after a master
has written a byte to a slave.
A synchronized SCL is generated with its LOW period determined by the device with the
longest low period and its HIGH period determined by the device with the shortest HIGH
period.
Slave
Address
F
S
R/W
A
Data
A
Data
P
F
A
SDA
SCL
X979_04_012907
Figure 4: Data Transfer on the IIC Bus
ending with the STOP condition.
P
SDA
MSB
Acknowledgment
signal from receiver
Sr
Acknowledgment
signal from slave
Byte complete;
interrupt within slave
Clock lines held low while
interrupts are serviced
SCL
S
or
SR
Sr
or
P
1
2
7
8
9
ACK
1
2
3 - 8
9
ACK
STOP or
repeated START
condition
START or
repeated START
condition
X979_05_022307
Figure 5: Generic Data Transer on the IIC Bus
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Reference System Specifics
Figure 6 shows the acknowledge bit on the IIC bus.
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
SCL from
master
1
2
8
9
S
Clock pulse for
acknowledgment
START
condition
X979_06_012907
Figure 6: Acknowledge on the IIC Bus
Figure 7 shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters
monitor the IIC bus to determine if the bus is active. The bus is inactive when SCL and SDA are
high for a bus free period tBUF of 1.3 us (FAST) or 4.7 us (STD). If two or more masters
monitoring the IIC bus determine that the bus is free and begin a bus transaction
simultaneously, the IIC bus is arbitrated to determine which master owns the bus. The IIC is a
wired AND bus. This means that the bus is HIGH unless any component is driving it LOW.
Masters monitor the bus even after they have started a transaction as the master. If a master is
not driving the IIC bus low and the bus is low, the master knows that another master is driving
the IIC bus. If a master cannot get the SDA or SCL to go high it loses arbitration. When a master
loses arbitration, it stops transmission. The master driving the bus with the last low when the
other master(s) drives high becomes the master of the bus.
Master 1
Master 2
SDA
SCL
X979_07_012907
S
Figure 7: Arbitration of two Masters
Reference
System
Specifics
In addition to the PowerPC405 processor and OPB IIC, this system includes DDR and BRAM
block diagram. Table 1 provides the address map of the ML403 XC4VFX12. This is in the
system.mhs.
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Reference System Specifics
ML403 XC4VFX12 Address Map
Table 1: ML403 XC4VSX12 System Address Map
Peripheral
PLB_DDR
Instance
DDR_SDRAM_32Mx64
RS232_Uart_1
Base Address
0x00000000
0x40400000
0x41200000
0xFFFF8000
0x40800000
High Address
0x03FFFFFF
0x4040FFFF
0x4120FFFF
0xFFFFFFFF
0x4080FFFF
OPB UART16550
OPB INTC
opb_intc_0
PLB BRAM
OPB IIC
plb_bram_if_cntlr_0
IIC_EEPROM
OPB IIC Registers
Table 2: OPB IIC Registers
Register
Device Global Interrupt Enable
Interrupt Status Register
Interrupt Enable Register
Software Reset Register
Control Register
Address
C_BASEADDR + 0x01C
C_BASEADDR + 0x020
C_BASEADDR + 0x028
C_BASEADDR + 0x040
C_BASEADDR + 0x100
C_BASEADDR + 0x104
C_BASEADDR + 0x108
C_BASEADDR + 0x10C
C_BASEADDR + 0x110
C_BASEADDR + 0x114
C_BASEADDR + 0x118
C_BASEADDR + 0x11C
C_BASEADDR + 0x120
C_BASEADDR + 0x124
Status Register
Transmit FIFO
Receive FIFO
Slave Address Register
Transmit FIFO Occupancy
Receive FIFO Occupancy
Ten Bit Slave Address Register
Receive FIFO Programmable Depth Interrupt Register
General Purpose Output
Table 3 provides a description of the OPB IIC control register.
Table 3: OPB IIC Control Register
Bit(s)
Name
Description
0- 24
Reserved Reserved.
General Call Enable. Setting this bit High allows the OPB IIC to respond to a
general call address.
25
26
GC_EN
RSTA
Repeated Start. Writing a “1” to this bit generates a repeated START condition
on the bus if the OPB IIC Bus Interface is the current bus Master. Attempting a
repeated START at the wrong time, if the bus is owned by another Master, results
in a loss of arbitration. This bit is reset when the repeated start occurs. This bit
must be set prior to writing the new address to the Tx FIFO or DTR.
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Reference System Specifics
Table 3: OPB IIC Control Register (Contd)
Bit(s)
Name
Description
Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA
line during acknowledge cycles for both Master and Slave receivers.
Because Master receivers indicate the end of data reception by not
acknowledging the last byte of the transfer, this bit is used to end a Master
receiver transfer. As a slave, this bit must be set prior to receiving the byte to no
acknowledge.
27
TXAK
Transmit/Receive Mode Select. This bit selects the direction of Master/Slave
transfers. This bit does not control the Read/Write bit that is sent on the bus with
the address. The Read/Write bit that is sent with an address must be the LSB of
the address written into the transmit FIFO.
28
29
TX
Master/Slave Mode Select. When this bit is changed from 0 to 1, the OPB IIC
Bus Interface generates a START condition in Master mode. When this bit is
cleared, a STOP condition is generated and the OPB IIC Bus Interface switches
to Slave mode. When this bit is cleared by the hardware, because arbitration for
the bus has been lost, a STOP condition is not generated.
MSMS
Transmit FIFO Reset
Tx FIFO
Reset
. This bit must be set if arbitration is lost or if a transmit error
30
31
occurs to flush the FIFO.
EN
OPB IIC Enable. This bit must be set before any other CR bits have any effect.
Status Register (SR)
This register contains the status of the OPB IIC Bus Interface. All bits are cleared upon reset.
Table 4 provides a definition of the status register.
Table 4: Status Register Bit Definitions
Bit(s)
0 - 23
24
Name
Description
N/A
Reserved.
Tx_FIFO_ Transmit FIFO empty. This bit is set High when the transmit FIFO is
Empty empty.
25
26
Rc_FIFO_ Receive FIFO empty. This is set High when the receive FIFO is empty.
Empty
Rc_FIFO_ Receive FIFO full. This bit is set High when the receive FIFO is full.
Full
This bit is set only when all sixteen locations in the FIFO are full,
regardless of the value written into Rc_FIFO_PIRQ.
27
28
Tx_FIFO_F Transmit FIFO full. This bit is set High when the transmit FIFO is full.
ull
SRW
Slave Read/Write. When the IIC Bus Interface has been addressed as
a Slave (AAS is set), this bit indicates the value of the read/write bit
sent by the Master. This bit is only valid when a complete transfer has
occurred and no other transfers have been initiated. A “1” indicates
Master reading from Slave. A “0” indicates Master writing to Slave.
29
BB
Bus Busy. This bit indicates the status of the IIC bus. This bit is set
when a START condition is detected and cleared when a STOP
condition is detected.
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Reference System Specifics
Table 4: Status Register Bit Definitions (Contd)
Bit(s)
Name
Description
30
AAS
Addressed as Slave. When the address on the IIC bus matches the
Slave address in the Address Register (ADR), the IIC Bus Interface is
being addressed as a Slave and switches to Slave mode. If 10-bit
addressing is selected this device will only respond to a 10-bit address
or general call if enabled. This bit is cleared when a stop condition is
detected or a repeated start occurs.
31
ABGC
Addressed By a General Call. This bit is set high when another
master has issued a general call and the general call enable bit is set
high, CR(1) = ’1’.
Table 5: Interrupt Status Register
Bit
Name
TFHE
NAAS
AAS
Description
Transmit FIFO Half Empty
Not Addressed as Slave
Addressed as Slave
24
25
26
27
28
29
30
31
BNB
Bus is not Busy
RFF
Receive FiFO Full
TFE
Transmit FIFO Empty
Transmit Error/Slave Transmit Complete
Arbitration Lost
TE/STC
AL
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Reference System Specifics
Configuring the OPB IIC Core
Figure 8 shows how to specify the values of IIC generics in EDK. To access the dialog box in
the figure, double click on the OPB IIC core in the EDK System Assembly View..
X979_08_012907
Figure 8: Specifying the Values of OPB IIC Generics in EDK
Microchip 24LC04
The Microchip Technology 24LC04B-I/ST with 4-KB EEPROM is provided on the ML403 board
to store non-volatile data. The EEPROM write protect is tied off on the board to disable its
hardware write protect. The IIC bus is extended to the expansion connector to allow additional
devices to be added to the IIC bus.
Figure 9 shows IIC Bus Devices on the ML403.
SCL
SDA
XC4VSX12
Microchip
24LC04B
FPGA
I/O
Expansion
Header
X979_09_022307
Figure 9: ML403 IIC Bus
The 24LC04 is organized as two blocks of 256 bytes. It has a page write buffer of up to 16
bytes. The 24LC04 operates as an IIC slave. The 24LC04 accepts a control byte which
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ML403 Board Information
is ‘1010 for read and write operations. The A2, A1 bits are dont cares. The A0 bit is used by the
master device to select which of the two 256-word blocks of memory are accessed. The
24LC04 write transactions are either a byte write or a page write. The page write begins the
same as the byte write but instead of generating a stop condition the master transmits up to 16
data bytes to the 24LC04B. The 24LC04 supports current address, random, and sequential
read operations.
Slave
Address
R/W
A
S
1
0
1
0
A2 A1 A0
X979_10_012907
Figure 10: 24LC04 Control Byte Allocation
ML403 Board
Information
According to the MicroChip 24L024B data sheet, the ML403 board has a low-level output
current (IOL) of 3.0 mA at a VCC of 2.5v. The ML403 boards are shipped in the configuration
shown in Figure 11. The board must be modified for this design to work correctly. Replace the
10K Ohm R70 and R71resistors with 833 or 1K Ohm resistors. See Answer Record 24049 for
additional information.
C280 VCC2V5
0.1 µF
2
R70
10k
2
1
24LC04B - I / ST
R71
10k
1
2
3
4
8
7
6
5
A0
VCC
WP
A1
A2
A3
1
IIC_SCL
IIC_SDA
SCL
SDA
U9
TSSOPS
X979_11_022307
Figure 11: ML40x Schematic for IIC Connections
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ML403 Board Information
The resistors are located on the board as shown in Figure 12.
X979_12_022307
Figure 12: ML40x Resistors
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If additional IIC devices are connected to the bus via the expansion header as shown in
Figure 13, insert additional pull-up resistors on the external signals connected at pins 31 and
32. The resistor values are dependent on the voltage.
HDR 1 X 32
1
2
3
4
5
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
FPGA_PROM_CPLD_TMS
FPGA_PROM_CPLD_TCK
EXPANSION_TDO
CPLD_TDO
GPIO_LED_N
GPIO_SW_N
GPIO_LED_C
GPIO_SW_C
GPIO_LED_W
GPIO_SW_W
GPIO_LED_S
GPIO_SW_S
GPIO_LED_E
GPIO_SW_E
GPIO_LED_0
GPIO_LED_1
GPIO_LED_2
GPIO_LED_3
NC
VCC2V5
Level
Translation
MOSFETs
NC
IIC_SCL
IIC_SDA
J3
External pullups
connect here
X979_13_012
Internal pullups
connect here
Figure 13: Expansion Header
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ML403 Board Information
Figure 14 shows the FPGA pins driving the IIC Bus.
C12
IO_L8N_GC_LC_3_C12
C13
SMA_DIFF_CLK_IN_N
SMA_DIFF_CLK_IN_P
IIC_SCL
IO_L8P_GC_LC_3_C13
A17
IO_L7N_GC_LC_3_A17
B17
IIC_SDA
IO_L7P_GC_LC_3_B17
B10
DDR_CLK1_N
DDR_CLK1_P
DDR_A13
DDR_BA1
DDR_BA0
DDR_CLK_P
MOUSE_DATA
PHY_TXCLK
IO_L6N_GC_LC_3_B10
IO_L6P_GC_LC_3_A10
A10
A15
IO_L5N_GC_LC_3_A15
A16
IO_L5P_GC_LC_3_A16
B12
IO_L4N_GC_VREF_LC_3_B12
B13
C14
C15
IO_L4P_GC_LC_3_B13
IO_L3N_GC_LC_3_C14
IO_L3P_GC_LC_3_C15
A11
IO_L2N_GC_VRP_LC_3_A11
A12
GPIO_LED_2
GPIO_LED_3
MOUSE_CLK
PHY_RXC_RXCLK
IO_L2P_GC_VRN_LC_3_A12
B14
IO_L1P_GC_CC_LC_3_B14
B15
IO_L1P_GC_CC_LC_3_B15
FPGA_BANK3
2.5 VCC0
X979_14_012907
Figure 14: FPGA IIC Pins
TotalPhase Aardvark Adapter
In the reference design, the OPB IIC in the XC4VFX12 on the ML403 board interfaces to the IIC
in the Aardvark Adapter. The Aardvark IIC/SPI Embedded Systems interface is a multi-
functional host adapter. The Aardvark Control Center software interacts with the Aardvark
Adapter. The Control Center controls the functionality of the Aardvark Adapter. It uses the
Aardvark IIC/SPI Software API. the Aardvark Adapter has six functional modes. The IIC-related
modes are the IIC + SPI and IIC Bus Monitoring modes.
The Aardvark must be configured for use before the Aardvark Control Center software can be
used to send and receive messages. Configuring the Aardvark Adapter binds the instance of
the application with the available unit until the adapter is disconnected or the application is
terminated.
The Configure Aardvark Adapter window is organized into two major sections: list of available
adapters connected to the computer and list of the six operational modes. The main application
window is divided into two sections. The top section contains the modules used with the
Aardvark Adapter. The bottom section contains the transaction log which tracks all transactions
that the Aardvark sends or receives. The transaction log contains the time, read or write
transaction, master or slave, bit rate, address, number of bytes, and data.
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ML403 Board Information
Figure 15 shows the Aardvark Control Center GUI.
X979_15_012907
Figure 15: Aardvark Control Center
Interfacing to the OPB IIC on the ML403 Board to the Aardvark
Adapter
Figure 16 shows the principle interface blocks when transferring data between the OPB IIC in
the XC4VFX12 on the ML403 board and the IIC in the Aardvark Adapter.
ML403 - XCVFX12
DDR
PC
PPC
OPB IIC
Aardvark
Adaptor
USB
BRAM
X979_16_012907
Figure 16: Interfacing ML403 Board OPB IIC with the Aardvark Adapter
Executing the Reference System using the Pre-Built Bitstream and the
Compiled Software Applications
To execute the system using files inside the ml403_ppc_opb_IIC/ready_for_download
directory, follow these steps:
1. Change to the ml403_ppc_opb_IIC/ready_for_downloaddirectory.
2. Use iMPACT to download the bitstream by using the following:
impact -batch xapp.cmd
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ML403 Board Information
3. Invoke XMD and connect to the MicroBlaze processor by the following command:
xmd -opt xapp.opt
4. Download the executable by the following command
dow <path>/executable.elf
Executing the Reference System from EDK
To execute the system using EDK, follow these steps:
1. Open system.xmpinside EDK.
2. Use Hardware → Generate Bitstream to generate a bitstream
3. Download the bitstream to the board using Device Configuration → Download
Bitstream.
4. Invoke XMD with Debug Launch XMD.
5. Download the executable by the following command.
dow <path>/executable.elf
Verifying the Reference Design with Xilinx Microprocessor Debugger
After downloading the bitstream file, issue the following XMD commands to verify that the
ML403 reference design is set up correctly.
mrd 0x42600100 8
The expected value of the control register after a reset, located at 0x42600100 is 0x00000000.
The expected value of the status register, located at 0x42600104, is 0x000000C0. The reset
values of the Transmit and Receive FIFO registers are indeterminate. The reset values of the
Transmit and Receive FIFO Occupancy and the Address registers is 0.
Except for the Status, , Receive FIFO, and Transmit and Receive Occupancy registers, all
registers are writeable.
mwr 0x42600100 0xFFFFFFFF
mrd 0x42600100 1
Using XMD commands, verify that the OPB IIC registers can be written and read as defined in
Tables 2-5.
Software Projects
The reference system contains the following software projects. In each software project
directory, there is a srcsub-directory for the source code. The connections in Figure 9 are
used for the eeprom, low_level_eeprom, dynamic_eeprom, and low_level_dynamic_eeprom
mult_master and repeated_start project. These projects interface to the IIC Bus via the
Aardvark Adapter.
Projects interfacing to Microchip 24LC04
eeprom: This project transmits and receives data using the high level (L1) software driver. The
OPB IIC is the master and the 24LC04 is configured as the slave. The OPB IIC master writes
data into the 24LC04 and reads it back.
low_level_eeprom: This project transmits and receives data using the low level (L0) software
driver. The OPB IIC is the master and the 24LC04 is configured as the slave. The OPB IIC
master writes data into the 24LC04 and reads it back. This is a polled mode example.
dynamic_eeprom: This project transmits and receives data using the high level (L1) software
driver. The OPB IIC is the master and the 24LC04 is configured as the slave. The OPB IIC
master writes data into the 24LC04 and reads it back.
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low_level_dynamic_eeprom: This project transmits and receives data using the low level (L0)
software driver. The OPB IIC is the master and the 24LC04 is configured as the slave. The OPB
IIC master writes data into the 24LC04 and reads it back. This is a polled mode example.c
Projects interfacing to Aardvark Adapter
multi_master: This project transmits and receives data using the high level (L1) software
driver. The OPB IIC is an IIC master and the IIC in the Aardvark is a master. The Microchip
24LC04B is configured as a IIC slave. The WP pin of the 24LCO4 is hardwired to ground on the
ML403. The interrupt mode is used. The IIC master in the Aardvark Adapter writes the data to
the MicroChip 24LC04B with the No Stop option enabled. Any attempts to write data from the
OPB IIC master results in a Bus Busy status. The Aardvark Adapter releases the bus by
executing the FREE BUS command. When the bus is free, the OPB IIC master initiates a bus
transaction.
repeated_start: This project transmits and receives the data using the high level (L1) driver.
The IIC devices on the ML300/ML310/ML410 boards do not support the repeated start option.
The ML403 OPB IIC is configured as a master and the Aardvark Adapter IIC is configured as a
IIC slave. The OPB IIC writes the data to the Aardvark IIC in multiple transactions with the
repeated start option enabled. The external IIC device slave address is a 7 bit address defined
by SLAVE_ADDRESS. The number of bytes sent and received is defined by SEND_COUNT
and RECEIVE_COUNT.
Figure 17 shows the repeated start example.
Specify 0x70 as the Address. The SPI Control is not used. The transaction log shows 16 write
and 16 read transactions at address 70.
X979_17_012907
Figure 17: Repeated Start Example
slave: This project transmits and receives the data using the high level (L1) driver. The ML403
OPB IIC is configured as a slave and the Aardvark Adapter IIC is configured as a IIC master.
The Aardvark Adapter IIC writes the data in test_data to the OPB IIC and reads it back.
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Running the Applications
Figure 18 shows the slave example. The message is in transmit.txt, and is the sentence "Lester
was here.". The transaction log matches the message. The address is 0x70. Click Master
Write to generate the transaction.
X979 18 012907
Figure 18: Slave Example
Running the
Applications
In XPS, select the Applications tab under the Project Information Area to view the Software
Project.
project active and the remaining software projects inactive.
X979_19_012907
Figure 19: Selecting the eeprom Software Project
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Running the Applications
Select dynamic_eeprom and right click to build the project. If more than one software project
is used, make the unused software projects inactive.
Connect a serial cable to the RS232C port on the ML403 board. Start up a HyperTerminal. Set
Bits per second to 9600, Data bits to 8, Parity to None, and Flow Control to None, as shown in
X979_20_012907
Figure 20: HyperTerminal Parameters
From XPS, start XMD and enter rst. Invoke GDB and select Run to start the application as
any modifications on this reference system.
X979_21_012907
Figure 21: Running dynamic_eeprom in GDB
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Using ChipScope with OPB IIC
Using
ChipScope with
OPB IIC
To facilitate the use of ChipScope to analyze OPB IIC hardware, the iic.cdcfile is included in
the ml403_ppc_opb_iic/chipscopedirectory. The iic.cdcis used to insert a
ChipScope ILA core into the opb_iic core. The following steps are used to insert a core and
analyze OPB IIC problems with ChipScope.
1. Invoke XPS. Run Hardware → Generate Netlist.
2. In the iic.cdcfile, change the path <design_directory>name to the directory in which
the design files are installed. Three paths need to be changed.
3. Run Start → Programs → ChipScope Pro → ChipScope Inserter
Inserter setup GUI.
X979_22_012907
Figure 22: ChipScope Inserter Setup
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Using ChipScope with OPB IIC
Connections window. If there are any red data or trigger signals, correct them. The Filter
Pattern can be used to find net(s). As an example of using the Filter Pattern, enter intrin the
dialog box to locate interrupt signals. In the Net Selections area, select either Clock, Trigger,
or Data Signals. Select the net and click Make Connections.
X979_23_012907
Figure 23: Making Net Connections in ChipScope Inserter
7. Click Insert Core to insert the core into iic_eeprom_wrapper.ngo. In the
ml403_ppc_opb_IIC/implementationdirectory, copy iic_eeprom_wrapper.ngoto
iic_eeprom_wrapper.ngc.
8. In XPS, run Hardware → Generate Bitstream and Device Configuration → Download
Bitstream. Do not rerun Hardware → Generate Netlist, as this overwrites the
implementation/iic_eeprom_wrapper.ngcproduced by the step above. Verify that the
file size of the opb_iic_wrapper.ngcwith the inserted core is significantly larger than the
original version.
9. Invoke ChipScope Pro Core Analyzer by selecting
Start → Programs → ChipScope Pro → ChipScope Pro Analyzer
Click on the JTAG chain icon located at the top left of Analyzer GUI. Verify that the message in
the transcript window indicates that an ChipScope ICON is found.
10. The ChipScope Analyzer waveform viewer displays signals named DATA*. To replace the
DATA* signal names with the signal names specified in ChipScope Inserter, select File →
Import and enter iic.cdcin the dialog box.
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Using ChipScope with OPB IIC
The waveform viewer is more readable when buses rather than discrete signals are displayed.
The Reverse Bus Order operation below Add to Bus in the figure can be useful in analyzing
ChipScope results.
X979_24_022307
Figure 24: Setting Up the Chipscope Trigger
11. Set the trigger in the Trigger Setup window. The trigger used depends on the problem being
debugged. Change the Windows to N samples to a setting of 100. Arm the trigger by selecting
Trigger Setup → Arm, or clicking on the Arm icon.
As shown in Figure 24, the trigger setup is to trigger when gen_startis High.
12. Run XMD and/or GDB to activate the trigger patterns which cause ChipScope to display
meaningful output.
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Linux Kernel
13. ChipScope results are analyzed in the waveform window as shown in Figure 25. The
waveforms may be easier to read if the discrete signals are removed after they are renamed. To
share the results with remote colleagues, save the results in the waveform window as a Value
Change Dump (vcd) file. The vcd files can be translated and viewed in most simulators. The
vcd2wlf translator in Modeltech reads a vcd file and generates a wlf file for viewing in the
Modeltech waveform viewer. The vcd file can be opened in the Cadence Design System, Inc.
Simvision design tool by selecting File → Open Database.
X979_25_012907
Figure 25: ChipScope Analyzer Results
Linux Kernel
New users of MontaVista Linux should read XAPP 765 Getting Started with EDK and Monta
Vista Linux. The steps to build and boot a Linux kernel are given below. Steps 1-3, 7, 8 are run
on a Linux machine with MontaVista Professional Edition© installed.
1. Add /opt/montavista/pro/host/binand
/opt/montavista/pro/devkit/ppc/405/bin
to $PATH.
2. Change to the ml403_IIC/linuxdirectory.
3. Run
tar cf - -C /opt/montavista/pro/devkit/lsp/xilinx-ml300-
ppc_405/linux-2.4.20_mvl31/ . tar xf -
4. To generate the Linux LSP in XPS, enter Software → Software Platform Settings.
Select Kernel and Operating Systems, then select linux_mvl31 v1.00.c.
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Linux Kernel
6. Click Connect_Periphs and add the OPB_INTC, OPB_SYSACE, OPB_IIC, OPB_SPI,
X979_27_012907
Figure 27: Connected Peripherals
Click OK.
7. Select Software → Generate Libraries and BSPs to generate the LSP in
ml403_ppc_opb_iic/linux.
8. From ml403_ppc_opb_iic/linux, run
patch_nobspgen.
9. The ml403_ppc_opb_iic/linux/.config is used to define the contents of the Linux
kernel. Run
make oldconfig
An alternative is to enter make menuconfigand generate a new .configusing the following
options.
•
•
•
•
Select General Setup
Enable IIC. Disable PS/2 keyboard. Change to /dev/ram for booting from ramdisk.
Select Input Core Support. Disable all.
Select Character Devices. Disable Virtual. Leave Serial enabled. Disable Xilinx GPIO and
Touchscreen.
10. Run make clean dep zImage.initrd. Verify that the zImage.initrd.elf file is in
the ml403_ppc_opb_iic/linux/arch/ppc/boot/imagesdirectory.
11. Invoke Impact and download implementation/download.bitto XC4VFX12. Either
select Device Configuration → Download Bitstream from XPS or run the following
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Simulation
command from the command prompt:
impact -batch etc/download.cmd
12. Invoke XMD. From the ml403_ppc_opb_iic/linux directory, enter the following
commands in the XMD window.
rst
dow arch/ppc/boot/images/zImage.initrd.elf
con
13. View the output in the HyperTerminal window. Login as root.Enter cd / and ls -lto
view the contents of the mounted Linux partition.
14. An alternative to downloading the Linux kernel executable is to load it into CompactFlash.
The file used uses an ace file extension. To generate an ace file, run the command below
from the ml403_ppc_opb_iic directory.
xmd -tcl /genace.tcl -jprog -hw ./implementation/system.bit -ace
./implementation/ace_system_hw.ace -board ML403
Copy the ace file to a 64-512 MB CompactFlash (CF) card in a CompactFlash reader/writer.
Remove the CF card from the CF reader/writer and insert it into the CompactFlash slot (J22) on
the ML403 board. Power up the board.
Simulation
The ml403_ppc_opb_iic/simulationdirectory contains waveform log file, opb_iic.wlf, for
IIC transactions discussed in this section.
The opb_iic.wlf files are easily loaded into the Modeltech simulator using the File → Open
command, specifying the *.wlf file type.
The OPB IIC core has two Finite State Machine (FSM). The clock FSM has IDLE, START,
SCL_LOW_EDGE, SCL_LOW, SCL_HIGH_EDGE, SCL_HIGH, STOP_WAIT states. The main
FSM has IDLE, HEADER, ACK_HEADER, RCV_DATA, XMIT_DATA, ACK_DATA, and
WAIT_ACK states.
Figure 28 shows the two OPB IIC cores in the simulation. The simulation is a Bus Functional
Model simulatation of two OPB IIC cores. The IIC cores with addresses 20 and AA are
designated iic_20 and iic_AA, with C_BASEADDR of 0xE0000000and 0xE1000000,
respectively. Both cores connect to SCL and SDA. The stimuli is provided by writing the OPB
IIC registers.
As an example
write cr 41
enables the OPB IIC and sets the General Call enable. The address determines which OPB IIC
is the target of the write, with 0xE0000100for iic_20 and 0xE1000100for iic_AA. It may be
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Simulation
In most cases, after data is transmitted, the test waits for an interrupt from the OPB IIC.
BFM
SCL
IIC_20
IIC_AA
SDA
Base Address
Base Address
0xE0000000
0xE1000000
X979_28_012907
Figure 28: OPB IIC Simulation
Internal signal names used in the OPB IIC core are provided in Table 6.
Table 6: Internal Signals in OPB IIC
Signal Name
Functionality
Transmit acknowledge
Txak
Gc_en
General call address enbale
Receive overrun prevent
Data transmit register empty
Master/Slave select
Ro_prev
Dtre
Msms
Dtr(7:0)
Data Transmit Register
IIC Slave Address Register
10-bit Slave Address Register
Bus Busy
Adr(7:0)
Ten_adr(7:5)
Bb
Aas
Addressed as slave
Al
Arbitration lost
Srw
Slave read/write
Abgc
Addressed by general call
IIC data for microprocessor
New data received on IIC bus
Transmit FIFO Empty IRQs
SDA value when slave
Data_iic(7:0)
New_rcv_data
Tx_under_prev
slave_sda
master_sda
sm_stop
rsta_tx_under_prev
SDA value when master
Stop condition needs to be generated
Repeated start Tx underflow prevent
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Simulation
In the first test, which is shown in Figure 30, the OPB IIC registers are read to verify the correct
reset values. The interrupt registers are written and read. This occurs from 0 - 10 s. Following
this, an arbitration test is run. IIC_AA is initially the bus master, with the write CR_AA 0x0d.
X979_30_022307
Figure 30: Arbitrartion Lost Test Simulation
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Simulation
Figure 31 provides the Arbitration Lost test code. This pseudo-code can be tracked in the
simulation.
write ADR_20 0x20
write CR_20 40
write CR_AA 0x01
write ADR_AA AA
write IER_AA 0x04
write RC_FIFO_PIRQ_20 0x0
write DTR_AA 0x0
write CR_AA 0x0D -- Enables AA as master (5.9us)
write IPIER_20 0x01
write DTR_20 AA
write CR_20 0x0D -- Enables 20 as master
wait_for_intr(30)
read IPISR 0xD3 -- Arbitration lost (260 us)
write CR_20 0x01 -- Clears interrupt
X979_31_012907
Figure 31: Arbitration Lost Test Code
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Simulation
Figure 33 provides the test code used in the simulation with the OPB IIC with the AA address
as the master.
write CR_20 0x40 -- GC, En
write ADR_20 0x20 - Sets address as 0x20
write CR_AA 0x01 - Enable
write ADR_AA 0xAA
write RC_FIFO_PIRQ_AA 0x0
write IER_AA 0x04 -- Enable DTRE interrupt
write RC_FIFO_PIRQ 0x01 (473 us)
write DTR_20 0x3C
write DTR_20 0x55
write DTR_AA 0x0 -- General Call
write CR_AA 0x0D -- RSTA, TxAK, TX, MSMS, Enable
wait_for_intr
read SR_AA 0xC4 -- TFE, RFE, BB
read ISR_AA 0xD4 -- TFHE, DTRE
write CR_AA 0x35 RSTA, M S, EN (547 us)
write DTR_AA 0x21
write DTR_AA 0xFF
write IER_AA 0x08
wait_for_intr -- waiting for DRR_AA full
read SR_AA 0x0C -- SRW, BB (678 us)
write CR_AA 0x37 -- Clear FIFO
write CR_AA 0x35
read DRR_AA 0x3C
write ISR_AA 0xC*
write DTR_AA 0x21
wait_for_intr
read SR_AA 0x8C
read ISR_AA 0xCA -- TXER, DFF Full
write CR_AA 0x41
read DRR_AA 0x55 (787 us)
write ISR_AA 0xC8
write IRE_AA 0x10 -- Enable Bus is not Busy
wait_for_intr
X979_33_012907
Figure 33: Test code with iic_AA as Master
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Simulation
Figure 35 provides the test code for simulation with IIC_AA as master.
write DTR_20 0xF2
write DTR_20 0xA5
write DTR_20 0xD5
write DTR_20 0x96
read TX_FIFO_OCY 0x01
write DTR_20 0x87
write CR_20 0x0D -- Tx, MS, En
write RC_FIFO_PIRQ 0x01
write IER_AA 0x20 -- Enable AAS
wait_for_intr
write DTR_20 0x78
write DTR_20 0x60
write DTR_20 0x5A
write DTR_20 0x4B
read SR_AA C6 -- TFE, RFE, BB, AAS (893 us)
write DTR_AA 0x11
write DTR_20 0x3C
write DTR_20 0x2D
write DTR_AA 0x22
wrote DTR_20 0x1E
write IER_AA 0x47
read TX_FIFO_OCY_20 0x0F -- 1207 us
write DTR_20 0x0F
read TX_FIFO_OCY_20 0x0F
read SR_20 0x1C -- TFF, SRW, BB
write DTR_20 0x00
read TX_FIFO_OCY_20 0x0F
read SR_20 0x1C
write DTR_20 0xFF
read ISR_AA 0xA0 -- TFE, FFF
read SR_20 C4 -- TFE, RFE, BB
write IER_20 0x3F -- Enable DTRE
wait_for_intr -- DTRE occurs, D5 sent, and
throttle for 1500 ns
write DTR_20 0xC3 (928 us)
write DTR_AA AA
wait_for_intr -- DTRE occurs, C3, AA sent, and
throttle for 1500 ns
write CR 0x25 -- RSTA, Master Receive, MS, Enable
write DTR_20 0xF3
write RC_FIFO_PIRQ_AA 0x0D
write CR_20 0x2D -- RSTA,TXAK,
MS, EN Starts transmission
read DRR_20 0x22
read DRR_20 0xC3
read ISR_AA 0xEE
wait_for_intr -- DRR full occurred, repeated start,
F3 sent on bus
read ISR-20 0xCC -- RFF (1130 us)
read DRR_20 0x11 -- No Ack Master Receive
write CR_20 0x15
write IER_AA 0x08
wait_for_intr -- DRR_55 Full
read DRR_AA 0xE1 -- 1948 us
read DRR_AA 0xD2
read DRR_AA 0xC3
write ISR_20 0xCC
read DRR_AA 0xB4
write IER_20 0x3B
read DRR_AA 0xA5
wait_for_intr -- DRR full, 0x22 received, throttle
for 1500 ns
read DRR_AA 0x96
read DRR_AA 0x87
write DTR_20 0xF2 -- Most significant address
write DTR_20 0xD5 -- Least significant address
write DTR_20 E1
read DRR_AA 0x78
read DRR_AA 0x69
read DRR_AA 0x5A
read TX_FIFO_OCY 0x02read SR_AA 0x8E
read DRR_AA 0xAA
read DRR_AA 0x4B
read DRR_AA 0x3C
read SR_AA 0xCE
read DRR_AA 0x2D
write DTR_20 0xD2
read DRR_AA 0x1E
write DTR_20 0xC3
write DTR_20 0xB4
write CR_20 0x09 -- TxAK, EN
write DTR_20 0x55
read TX_FIFO_OCY_20 0x05
read SR_20 0x0C -- SRW, BB
X979_35_012907
Figure 35: Test Code for Simulation with iic_20 as Master
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References
References
XAPP765 Getting Started with EDK and MontaVista Linux
ML40x Embedded Development Platform User Guide UG080 (v2.5) May 24, 2006
ChipScope ILA Tools Tutorial
The IIC Bus Specification Version 2.1 January 2000 Philips Semiconductors
Revision
The following table shows the revision history for this document.
Date
Version
Revision
2/26/07
1.0
Initial Xilinx release.
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