Toshiba Projection Television TW40F80 User Manual
NTDPJTV05  
TECHNICAL TRAINING MANUAL  
N5SS CHASSIS  
PROJECTION TELEVISION  
TW40F80  
Only the different points from the training manual “N5SS chassis” with its file  
No. 026-9506 are described on this manual.  
For other parts common with “N5SS chassis”, please refer to the original manual  
with its file No. 026-9506.  
©1997 TOSHIBA AMERICA CONSUMER PRODUCTS, INC.  
NATIONAL SERVICE DIVISION  
TRAINING DEPARTMENT  
1420-B TOSHIBA DRIVE  
LEBANON, TENNESSEE 37087  
PHONE: (615)449-2360  
FAX: (615)444-7520  
www.toshiba.com/tacp  
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Contents Page 2  
SECTION V: WAC CIRCUIT .................................................................................... 37  
1. OUTLINE.................................................................................................................. 37  
2. CIRCUIT OPERATION .......................................................................................... 37  
3. BLOCK DIAGRAM ................................................................................................. 42  
4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS  
PROCEDURES......................................................................................................... 43  
SECTION VI: DUAL CIRCUIT ................................................................................ 45  
1. OUTLINE.................................................................................................................. 45  
2. PRINCIPLES OF OPERATION............................................................................. 45  
3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT ...................................... 46  
4. CIRCUIT OPERATION .......................................................................................... 47  
5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF  
MAIN IC.................................................................................................................... 51  
SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT .............................. 58  
1. OUTLINE.................................................................................................................. 58  
2. CIRCUIT DESCRIPTION ...................................................................................... 58  
SECTION VIII: VERTICAL OUTPUT CIRCUIT.................................................. 60  
1. OUTLINE.................................................................................................................. 60  
2. V OUTPUT CIRCUIT.............................................................................................. 61  
3. PROTECTION CIRCUIT FOR V DEFLECTION STOP ................................... 64  
4. RASTER POSITION SWITCHING CIRCUIT .................................................... 66  
SECTION IX: HORIZONTAL DEFLECTION CIRCUIT .................................... 67  
1. OUTLINE.................................................................................................................. 67  
2. HORIZONTAL DRIVE CIRCUIT......................................................................... 67  
3. BASIC OPERATION OF HORIZONTAL DRIVE............................................... 67  
4. HORIZONTAL OUTPUT CIRCUIT ..................................................................... 69  
5. HIGH VOLTAGE GENERATION CIRCUIT ....................................................... 76  
6. HIGH VOLTAGE CIRCUIT ................................................................................... 78  
7. X-RAY PROTECTION CIRCUIT.......................................................................... 80  
8. OVER CURRENT PROTECTION CIRCUIT ...................................................... 81  
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Contents Page 3  
SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT  
(SIDE DPC CIRCUIT)............................................................................................... 82  
1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP) ....................... 82  
2. DIODE MODULATOR CIRCUIT ......................................................................... 83  
3. ACTUAL CIRCUIT.................................................................................................. 84  
SECTION XI: DIGITAL CONVERGENCE CIRCUIT ......................................... 87  
1. OUTLINE.................................................................................................................. 87  
2. CIRCUIT DESCRIPTION ...................................................................................... 87  
3. PICTURE ADJUSTMENT ...................................................................................... 89  
4. CASE STUDY ........................................................................................................... 97  
5. TROUBLESHOOTING ........................................................................................... 98  
6. CONVERGENCE OUTPUT CIRCUIT................................................................. 99  
7. CONVERGENCE TROUBLESHOOTING CHART ......................................... 101  
OVERALL BLOCK DIAGRAM................................................................................102  
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SECTION I: OUTLINE  
2. MERITS OF BUS SYSTEM  
1. FEATURE  
2-1. Improved Serviceability  
The TW40F80 is a first PJ-TV with a wide screen aspect  
ratio of 16:9 we introduce to North U.S.A. markets.  
Most of the adjustments previously made by resetting vari-  
able resistors and/or capacitors can be made on the new chas-  
sis by operating the remote control and seeing the results on  
the TV screen. This allows seeing adjustments to be made  
without removing servicing speed and efficiency.  
As the basic chassis N5SS chassis is used.  
The future of the model TW40F80 is the use of the N5SS  
chassis. This chassis introduces a new bus system, devel-  
2
oped by the PHILIPS company, called the I C (or IIC) bus.  
IIC stands for Inter-Integrated Circuit control. This bus co-  
ordinates the transfer of data and control between ICs inside  
the TV. It is a bi-directional serial bus consisting of two lines,  
named SDA (Serial DATA), and SCL (Serial CLOCK). This  
bus control system is made possible through the use of digi-  
tal-to analog converters built into the ICs, allowing them to  
be addressed and controlled by strings of digital instructions.  
2-2. Reduction of Parts Count  
The use of digital-to-analog converters built into the ICs,  
allowing them to be controlled by software, has eliminated  
or reduced the requirement for many discrete parts such as  
potentiometers and trimmers, etc.  
The TW40F80 is a first wide TV with a double window sys-  
tem we introduce to North U.S.A. markets.  
2-3. Quality Control  
This central control of the adjustment data makes it easier to  
understand, analyze, and review the data, thus improving  
quality of the product.  
The size of the main and sub screens separated in left and  
right on the screen is the same as each other. So it is possible  
to enjoy two programs or video and TV program at the same  
time.  
The sub screen is equipped wit 9 screen search function and  
this is very convenient convenient to search a program you  
desire.  
Note:  
Only the different points from the manual  
“N5SS Chassis” with its file No. 026-9506  
are described on this manual. For other parts  
common with “N5SS Chassis”, please refer  
to the original manual with its File No. 026-  
9506.  
5
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C-Chassis  
3. SPECIFICATIONS  
Model  
TW56F80 TW40F80 TP61F90 TP61F80 TP55F80 TP55F81 TP50F90 TP50F60 TP50F61 TP50F50 TP50F51  
CRT  
7"  
7"  
7"  
7"  
7"  
7"  
7"  
7"  
7"  
7"  
7"  
CRT Source  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Hitach  
Remote H/U  
RMT Keys  
PIP  
Intell  
52 key  
2-TN  
Univ  
36 key  
2-TN  
Intell  
52 key  
2-TN  
Univ  
36 key  
2-TN  
Univ  
36 key  
2-TN  
Univ  
36 key  
2-TN  
Intell  
52 key  
2-TN  
Univ  
36 key  
2-TN  
Univ.  
36 key  
2-TN  
A-Univ  
42 key  
1-TN  
A-Univ  
42 key  
1-TN  
Dolby Surr  
Surround  
SAP  
ProLgc  
Dsp4Ch  
●
ProLgc  
Dy-Sur  
Dy-Sur  
Dy-Sur  
ProLgc  
●
●
Dsp4Ch Dsp4Ch Dsp4Ch Dsp4Ch Dsp4Ch  
●
●
●
●
●
●
●
●
●
●
●
●
●
Cyclone  
SBS  
●
●
●
●
●
●
●
●
●
●
●
Audio (W)  
28W  
28W  
28W  
28W  
28W  
28W  
28W  
28W  
28W  
28W  
28W  
Center  
Rear  
+20W  
+20W  
20W  
20W  
20W  
20W  
DIG  
20W  
20W  
DIG  
20W  
DIG  
Comb-Filter  
3D-Y/C 3D-Y/C 3D-Y/C 3D-Y/C  
DIG  
DIG  
DIG  
DIG  
DQF  
●
●
●
●
●
●
●
●
Scan-Modul  
VCC  
●
●
●
●
●
●
●
●
●
Black-Expan  
Color-D.E  
Pic-Prefer  
Color-Temp  
Flesh-Tone  
Nois-Reduce  
Hori-Resolu  
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800  
800  
800  
800  
800  
800  
800  
800  
800  
800  
800  
Fav-Channel  
Ch-Label  
3-Language  
Clock  
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Ch-Lock/Off  
C.Caption  
EDS  
New-OSD  
S/Sight  
●
●
●
●
●
●
S-Video In  
AV-In/Out  
Front-Term  
A(Var)-Out  
2RF-Term  
SPK-Term  
PIP Audio  
C-Ch-Input  
E/Jack  
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1+1  
1+2/1  
●
1
1
2/1  
2/1  
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S/S-Jack  
●
●
●
●
●
●
●
●
●
IR-B & 75W  
Adapter  
●
●
●
●
●
●
●
Rod-Antenna  
SPK-Box  
EZ RMT  
●
●
●
●
●
●
Cabinet  
TW56D90 40W30E TP61E90 TP61E80 TP55E80 TP55E81  
New  
New  
New  
New  
New  
*
6
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4. FRONT VIEW  
POWER indicator  
POWER  
POWER button  
Press to open  
the door.  
ANT / VIDEO button **  
ENTER button  
Behind the door  
ANT/  
VIDEO  
VOLUME  
CHANNEL  
S-VIDEO  
VIDEO  
AUDIO  
L/MCNO  
R
DEMO  
ENTER  
MENU  
IN-VIDEO   3  
MENU button  
CHANNEL  
/
buttons  
    / buttons  
VIDEO 3 INPUTS  
DEMO button  
VOLUME  
/
buttons  
    / buttons  
Fig. 1-1  
Note: [No] Owner's manual page.  
7
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5. REAR VIEW  
TV front  
Behind the door  
S-VIDEO  
VIDEO  
AUDIO  
L/MCNO  
R
IN-VIDEO   3  
VIDEO / AUDIO INPUT jacks (VIDEO 3)  
S-VIDEO INPUT jack (VIDEO 3)  
Fig. 1-2  
S-VIDEO INPUT jack  
(VIDEO 1)  
TV rear  
VARIABLE AUDIO  
OUTPUT jacks  
ANT   (75 ½)  
AMP  
VAR  
S-VIDEO  
R
L
ACC  
AMP  
Y
VIDEO  
TV  
C4  
VIDEO  
(+)  
(Ð)  
(+)  
(Ð)  
L
L
VIDEO  
VIDEO/AUDIO  
R
AUDIO  
R
AUDIO  
R
AMP  
EXT SPEAKER  
EXT INT  
MAIN SPEAKER  
VIDEO1 VIDEO2  
DVD  
N
CUT  
VIDEO / AUDIO  
INPUT jacks  
(VIDEO 1)  
VIDEO /  
AUDIO  
OUTPUT  
jacks  
EXTERNAL  
SPEAKER  
terminal  
VIDEO / AUDIO  
INPUT jacks  
(VIDEO 2)  
MAIN  
SPEAKER  
switch  
DVD INPUT  
jacks  
Fig. 1-3  
8
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6. REMOTE CONTROL VIEW  
Aim at the remote sensor on the TV  
RECALL* [ 26 ]  
TIMER* [ 38, 39 ]  
RECALL  
MUTE  
PIC -SIZE  
TV/VIDEO  
TV / CABLE / VCR switch [ 15 ]  
Set to " TV " to control the TV.  
POWER [ 20 ]  
MUTE* [ 26 ]  
TV / VIDEO* [ 55 ]  
Channel Number* [ 25 ]  
EDS* [ 27 ]  
2
5
8
0
3
6
1
4
7
CH  
CHANNEL  
/
 [ 25 ]  
 [ 25 ]  
CH  RTN* [ 26 ]  
9
CH RTN  
VOL  
VOLUME  
/
ENT  
100  
ADV/  
MENU [ 18 ]  
EDS  
MENU  
POP CH  
POP CH * [ 40 ]  
[ 18 ]  
ENTER [ 19 ]  
FAN * [ 46 ]  
/
/
/
FAV  
FAV  
ENTER  
POP CH  
* [ 40 ]  
FAN * [ 46 ]  
RESET  
EXIT  
ADV/  
POP  CH  
RESET * [ 33 ]  
EXIT * [ ON ]  
STOP SCURCE  
PLAY POP  
Owner's  Manual page  
TV/VCR  
REW  
FF  
REC  
CH SEARCH  
STILL  
SWAP  
POP functions* [40]  
(For " TV " and " CABLE " positions)  
TOSHIBA  
* These function do not have  
  duplicate locations on the TV.  
  They can be controlled only by  
  the Remote Control.  
Fig. 1-4  
Note: [No] Owner's Manual page.  
9
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7. CHASSIS LAYOUT  
6
1 2  
3
1 1  
9
1 3  
0
1 6  
9
1 3  
5
1 5  
9
1 3  
5
1 6  
5
1 6  
9
5
4
2 4  
5
1 6  
9
2 4  
1 6  
4
2 9  
4
2 9  
2 9  
10  
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8. CONSTRUCTION OF CHASSIS  
A110  
A505  
BIDT2  
4x12  2pcs  
A401  
A110B  
2pcs  
A522  
BIDT2  
4X12  18pcs  
K601  
A126  
A520  
PP 5x18  
4pcs  
A110A  
A101  
A517  
PBI 4X16  
8pcs  
A512  
BIDT2  
A517  
4x12  6pcs  
A201  
A353  
A351  
Z410  
A902  
B202  
A127  
A521  
BRT TBS 4x16  
2pcs  
A502  
PMM 4x16  
4pcs  
A128  
W661~  
W664  
PMM 4x16  
2pcs  
A205  
A506  
BRB TBS  
      4x16  4pcs  
A501  
BTA 4x16 16pcs  
A515  
PMM 4X16  
4pcs  
A106  
A508  
BIDT2  
4x12  2pcs  
A516  
K511  
PMS 3.8x28  
3pcs  
A523  
PMM 4x16  
2pcs  
A202  
A102  
A509  
A519  
BTA 4x16  4pcs  
BIDT2  
4x12  
5pcs  
A107  
A511  
PP4x14  
4pcs  
L462~  
L464  
K103  
A503  
A105  
PMM  
4x16  
8pcs  
A104  
A105  
L472~  
L474  
A510  
A508  
BIDT2  
4x12  
4pcs  
BRBTB  
5x16  
4pcs  
A104  
A513  
BIDT2  
4x12  
V901R  
V902G  
V903B  
A108  
Fig. 1-6  
11  
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SECTION II: TUNER, IF/MTS/S. PRO MODULE  
1. CIRCUIT BLOCK  
IF/MTS/S.PRO Module MVUS34S  
EL466L  
Tuner  
SIF  
output  
Sound  
Multiplex  
Circuit  
VIF/SIF  
Circuit  
SAW  
Filter  
S.PRO Circuit  
RF AGC  
C-IN  
R-IN L-IN  
TP12  
Video output  
TV  
R-OUT  
TV  
L-OUT  
C-OUT  
(L+R)  
-OUT  
R-OUT  
L-OUT  
To A/V switch circuit  
AFT output  
Fig. 2-1 Block diagram  
1-1. Outline  
(5) VIF/SIF circuit uses PLL sync detection system to  
improve performances shown below:  
(1) RF signals sent from an antenna are converted into in-  
termediate frequency band signals (video: 45.75 MHz,  
audio: 41.25 MHz) in the tuner. (Hereafter, these sig-  
nals are called IF signals.)  
•
•
Telop buzz in video over modulation  
DP, DG characteristics (video high-fidelity repro-  
duction)  
(2) The IF signals are band-limited in passing through a  
SAW filter.  
•
Cross color characteristic (coloring phenomenon  
at color less high frequency signal objects)  
(3) The IF signals band-limited are detected in the VIF  
circuit to develop video and AFT signals.  
(6) HIC SBX1637A-22 is used in the audio multiplexer  
circuit to minimize the size with increased performance.  
(4) The band-limited IF signals are detected in the SIF cir-  
cuit and the detected output is demodulated by the au-  
dio multiplexer, developing R and L channel outputs.  
These outputs are fed to the A/V switch circuit.  
2
(7) As a sound control processor, TA1217N is used. I C-  
bus data control the DAC inside the IC to perform  
switching of the audio multiplexer modes.  
(5) A sound processor (S.PRO.) is provided.  
1-2. Major Features  
(1) The VIF/SIF circuit is fabricated into a small module  
by using chip parts considerably.  
(2) As the tuner, EL466L that which contains an integrated  
PLL circuit is employed.  
(3) Wide band double SAW filter F1802R used.  
(4) FS (frequency synthesizer) type channel selection sys-  
tem employed.  
12  
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1-3. Audio Multiplex Demodulation Circuit  
Then, both are fed to the matrix circuit. At the same time,  
each of the stereo pilot signal fH and the SAP pilot signal  
5fH is also demodulated to obtain an identification voltage.  
With the identification voltage thus obtained and the user  
control voltage are used to control the matrix.  
The sound multiplex composite signal FM-detected in the  
PIF circuit enters pin 12 of HIC (hybrid IC) in passing  
through the separation adjustment VR RV2 and amplified.  
After the amplification, the signal is split into two: one en-  
ters a de-emphasis circuit, and only the main signal with the  
L-R signal and a SAP signal removed enters the matrix cir-  
cuit. At the same time, the other passes through various fil-  
ters and trap circuits, and the L-R signal is AM-demodu-  
lated, and the SAP is FM-demodulated.  
The audio signals obtained by demodulating the sound mul-  
tiplex signal develop at pin 10 and 11 of HIC and develop  
the terminals of 12 and 14 of the module.  
MVUS34S  
MPX  
Out  
TV  
DAC-out1  
TV  
DAC-out2  
(RFSW)  
R-Out (SURR ON/OFF) L-Out  
11  
15  
9
10  
12  
13  
14  
Monitor the input  
pin for multiplex  
sound IC  
Stereo  0V  
Other   5V  
SAP   0V  
OFF   0V  
ON    9V  
RF1    0V  
RF2    9V  
Other   5V  
TV waveform detection  
output (R)  
TV waveform detection  
output (L)  
To AV select circuit  
Fig. 2-2 Block diagram of MVUS34S  
Note:  
Table 2-1 Matrix for broadcasting conditions and  
reception mode  
Of the mode selection voltages, switching voltages for STE,  
SAP, MONO do not output outside the module.  
Output  
OSD display  
Stereo SAP  
They are used inside the module to control the BUS.  
Broad- Switching  
casted mode  
12 pin 14 pin  
(R)  
(L)  
Stereo STE  
SAP  
MONO  
Mono STE  
SAP  
R
R
L+R  
L+R  
L+R  
L+R  
L
L
L+R  
L+R  
L+R  
L+R  
–
–
–
–
–
–
•
•
•
–
–
–
MONO  
: Available, – : Not available  
•
Stereo STE  
R
SAP  
L+R  
L
SAP  
L+R  
• •  
• •  
• •  
+
SAP  
SAP MONO  
Mono STE  
L+R  
SAP  
L+R  
L+R  
SAP  
L+R  
–
–
•
+
SAP  
•
SAP MONO  
–
•
13  
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1-4. A.PRO Section (Audio Processor)  
All these processing are carried out according to the BUS  
signals sent from a microcomputer.  
The S.PRO section has following functions.  
(1) Woofer processing (L+R output)  
(2) High band, low band, balance control  
(3) Sound volume control, cyclone level control  
(4) Cyclone ON/OFF  
Fig. 2-3 shows a block diagram of the A.PRO IC.  
TA1217N  
29 36  
22 32  
1
27  
30  
9
8
28  
34  
26  
25  
L out  
R out  
Lin  
BALANCE  
TONE CONTROL  
30  
2
Rin  
Cin  
Center  
LEVEL  
VOLUME  
C out  
W out  
18  
10  
Woofer  
LEVEL  
17  
16  
15  
14  
13  
12  
11  
Win  
3
LPF  
I/O  
20  
21  
SDA  
SCL  
I2  C  
D/A  
CONV  
SAP Ident.  
STE Ident.  
23 22 19  
7
31 24  
4
5
6
R-in      C-in       L-in  
SCL     SDA     W-out   O-out     L-out        
From    From     From  
 A/V     Dolby      A/V  
to Q670   to Q640  to Q670            to Q670  
Via QS101  
Fig. 2-3 A.PRO block diagram  
14  
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Configuration of the audio circuit and signal flow are given  
in Fig. 2-4  
A/V PCB  
VIF+MTS+S.PRO  
FOR POP  
IF MODULE  
MODULE  
ICV01  
12  
14  
R
L
29  
31  
R
L
EQ  
ER  
6
7
L
CHILD  
TV  
MOTHER  
TV  
R
AUDIO  
2
1
L
L
PIP OUT  
(AUDIO)  
PIP  
OUTPUT  
R     L  
R     L  
L
11  
13  
3
(TW40F80 NOT USE)  
VIDEO 1  
R
R
VIDEO 1  
VIDEO 2  
R
L
VIDEO 2  
OR  
DVD  
VIDEO  
OUTPUT  
TERMINAL  
9
R
Q601  
VIF+MTS+A.PRO  
MODULE  
R
L
R     L  
VIDEO 3  
(FRONT INPUT)  
L
15  
17  
R
L
VIDEO 3  
25  
R OUT  
+
+
2
5
11  
R
FRONT  
SURROUND  
UNIT  
35  
37  
AS  
AR  
16  
18  
R
L
R
L
W OUT 22  
L OUT 24  
7
R
L
VARIABLE  
AUDIO OUTPUT  
TERMINAL  
AI  
AJ  
Fig. 2-4  
15  
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2. POP TUNER  
Label  
Name  
Lot No.  
1
15  
TUNER  
SAW  
VIF/SIF  
SECTION  
FILTER  
CIRCUIT  
Terminal No.  
Name  
NC  
1
2
RF AGC  
32V  
3
S-CLOCK  
S-DATA  
NC  
VIDEO  
OUTPUT OUTPUT  
AUDIO  
AFT  
OUTPUT  
4
5
Fig. 2-5  
6
ADDRESS  
5V  
7
8
RF AGC  
9V  
2-1. Outline  
9
The POP tuner (EL922L) consists of a tuner and an IF block  
integrated into one unit. The tuner receives RF signals in-  
duced on an antenna and develops an AFT output, video  
output, and audio output.  
10  
11  
12  
13  
14  
15  
AUDIO  
GND  
AFT  
NC  
The tuner has receive channels of 181 as in the tuner for the  
GND  
2
main screen and it is also controlled through the I C-bus.  
VIDEO  
As the IC for the IF, a PLL complete sync detection plus  
audio inter carrier system are employed.  
Fig. 2-6 Tuner terminal layout  
16  
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SECTION III: CHANNEL SELECTION CIRCUIT  
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM  
The channel selection circuit in the N5SS chassis employs  
POP and Double Window signal processing (QY03), IC for  
a bus system which performs a central control by connect-  
ing a channel selection microcomputer to a control IC in  
each circuit block through control lines called a bus. In the  
closed caption control (QM01), IC for WAC control (QX01),  
IC for 3D-YCS (QZ01), IC for AUTOLIVE (QK06).  
Differences from N5SS chassis are as follows;  
2
bus system which controls each IC, the I C bus system (two  
1. On-screen function inside microcomputer is used. Sepa-  
rate IC is not used for on-screen.  
line bus system) developed by Philips Co. Ltd. in the Neth-  
erlands has been employed.  
2. The microcomputer does not have the closed caption  
function, but controls separate IC for closed caption.  
2
The ICs controlled by the I C bus system are: IC for V/C/D  
signal processing (Q501), IC forA/V switching (QV01), IC for  
non volatile memory (QA02), Main and sub U/V tuners (H001,  
HY01), IC for deflection distortion correction (Q302), IC for  
2
3. The system uses two channels of I C bus. One is only  
for non-volatile memory.  
2. OPERATION OF CHANNEL SELECTION CIRCUIT  
Toshiba made 8 bit microcomputer TLCS-870 series for TV  
receiver, TMP87CS38N-3320 is employed for QA01.  
(4) CONTROL OF U/V TUNER UNIT (H001 Toshiba  
ELA12L, HY01 Toshiba EL922L)  
With this microcomputer, each IC and circuit shown below  
are controlled.  
•
A desired channel can be tuned by transferring a  
channel selection frequency data (divided ratio data)  
2
to the I C bus type frequency synthesizer equipped  
(1) CONTROL OF VIDEO/CHROMA/DEF SIGNAL  
PROCESS IC (Q501 Toshiba TA1222AN)  
in the tuner, and by setting a band switch data which  
selects the UHF or VHF band.  
•
•
•
Adjustments for uni-color, brightness, tint, color  
gain, sharpness and PIP uni-color  
(5) CONTROL OF DEFLECTION DISTORTION COR-  
RECTION IC (Q302 Toshiba TA8859P)  
Setting of adjustment memory values for sub-  
brightness, sub-color and sub-tint, etc.  
•
Sets adjustment memory value for vertical ampli-  
tude, linearity, horizontal amplitude, parabola, cor-  
ner, trapezoid distortion.  
Setting of memory values for video parameters such  
as white balance (RGB cutoff, GB drive) and  
gcorrection, etc.  
(6) CONTROL OF POP & Double Window SIGNAL PRO-  
CESS IC (QY03 Toshiba TC9092AF, QY91 Sony  
CXP85116B-514Q)  
•
Setting of video parameters of video modes (Stan-  
dard, Movie, Memory)  
•
Controls ON/OFF and 9 pictures serch of POP.  
(2) CONTROL OF A/V SWITCH IC (QV01 Toshiba  
TA1218N)  
(7) CONTROL OF CLOSED CAPTION/EDS (QM01  
Motorola XC144144P)  
•
Performs source switching for main screen and sub  
screen  
•
Controls Closed Caption/EDS.  
(8) CONTROL OF WAC (QX01 Toshiba TC9097F)  
Controls Wide Aspect.  
(9) CONTROL OF 3D-YCS (QZ01 Toshiba TC9086F)  
Controls ON/OFF of 3 Dimension Y/C separator.  
•
Performs source switching for TV and three video  
inputs  
•
(3) CONTROL OF NON-VOLATILE MEMORY IC  
(QA02 Microchip 24LC08BI/P)  
•
•
•
•
Memorizes data for video and audio signal adjust-  
ment values, volume and woofer adjustment val-  
ues, external input status, etc.  
(10) CONTROL OF VERTICAL AMPLITUDE (QK06  
Toshiba TMP87CM36N)  
•
Controls Wide Mode.  
Memorizes adjustment data for white balance (RGB  
cutoff, GB drive), sub-brightness, sub color, sub  
tint, etc.  
2
(11) CONTROL OF OSD (Do not I C BUS) (QR60 Fujitsu  
MB90091)  
•
Controls of OSD Menu.  
Memorizes deflection distortion correction value  
data adjusted for each unit.  
17  
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3. MICROCOMPUTER  
•
Self diagnosis function which utilizes ACK function of  
Microcomputer TMP87CS38N-3320 has 60k byte of ROM  
capacity and equipped with OSD function inside.  
2
I C is equipped  
•
•
Function indication is added to service mode.  
The specification is as follow.  
Remote control operation is equipped, and the control  
by set no touch is possible. (Bus connector in the con-  
ventional bus chassis is deleted.)  
•
•
•
•
Type name : TMP87CS38N-3320  
ROM : 60k byte  
RAM : 2k byte  
•
Substantial self diagnosis function  
Processing speed : 0.5ms (at 8MHz with Shortest com-  
(1) B/W composite video signal generating function  
(micom inside, green crossbar added)  
mand)  
•
•
•
•
Package : 42 pin shrink DIP  
(2) Generating function of audio signal equivalent to  
1kHz (micom inside)  
2
I C-BUS : two channels  
(3) Detecting function of power protection circuit opera-  
tion  
PWM : 14 bit x 1, 7 bit x 9  
ADC : 8 bit x 6 (Successive comparison system, Conver-  
(4) Detecting function of abnormality in IIC bus line  
sion time 20ms)  
IIC device controls through I2C bus. (Timing chart : See Fig.  
3-1)  
(5) Functions of LED blink indication and OSD indica-  
tion  
•
•
•
LED uses big current port for output only.  
(6) Block diagnosis function which uses new VCD and  
AV SW  
For clock oscillation, 8MHz ceramic oscillator is used.  
2
I C has two channels. One is for EPROM only.  
SDA  
SCL  
8
1 - 7  
9
1 - 7  
9
1 - 7  
9
8
R/W  
8
Start  
condition  
Address  
DATA  
Ack  
Ack  
Data  
Ack  
Stop  
condition  
Approx.180µS  
Some device may have no data,  
or may have data with several  
bytes continuing.  
Fig. 3-1  
18  
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4. MICROCOMPUTER TERMINAL FUNCTION  
TMP87CS38N3320 (QA01)  
VDD  
VDD  
42  
41  
40  
39  
38  
37  
36  
35  
34  
GND  
BAL  
1
2
3
4
5
6
7
8
9
GND  
I
ACP  
P57  
P32  
I
I
P40 (PWM0)  
P41 (PWM1)  
P42 (PWM2)  
P43 (PWM3)  
P44 (PWM4)  
P45 (PWM5)  
P46 (PWM6)  
P47 (PWM7)  
O
O
O
O
O
O
O
SS VD  
REM OUT  
MUTE  
2
I  C STOP  
P57  
I
SP MUTE  
NC  
SDA1  
SCL1  
SDA0  
IO  
O
I
IIC-  
 BUS  
SCL0  
POWER  
LED  
SYNC AV1  
RMT IN  
EXT SP  
RESET  
XOUT  
XIN  
(TC3)P31  
(RXIN)P30  
P20  
I
SSRST  
DVD CONT  
SCL0  
I
I
RESET  
XOUT  
I
33  
32  
10  
11  
P50 (PWM8/TC2)  
P51 (SCL1)  
O
O
IIC  
 -BUS  
IO  
I
I
I
XIN  
TEST  
0SC2  
0SC1  
VD  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
SDA0  
SYNC VCD  
PIPRST  
AFT2  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
P52 (SDA1)  
P53 (AINO/TC1)  
P54 (AIN1)  
GND  
  0  
I
O
I
0SC1  
P55 (AIN2)  
0SC2  
I
AFT1  
I
P56 (AIN3)  
VSYNC  
OSD RESET  
DATA  
I
KEY-A  
KEY-B  
SGV  
 0  
O
I
P60 (AIN4)  
P61 (AIN5)  
P62  
OSD RESET  
DATA  
BUSY  
CS  
I
O
O
BUSY  
CS  
SGA  
O
O
P63  
GND  
VSS  
CLK  
CLK  
Fig. 3-2  
19  
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<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >>  
No. Terminal Name  
Function  
In/Out  
Logic  
Remarks  
1
GND  
0V  
2
3
BAL  
INPUT BALANCE  
Out  
Out  
PWM out  
REM OUT  
REMOTE CONTROL  
SIGNAL OUT  
Remote control output  
4
5
6
7
8
MUTE  
SOUND MUTE OUT  
SPEAKER MUTE  
Out  
Out  
Out  
Out  
Sound mute output  
In muting = H  
SP MUTE  
DEF POW  
POWER  
LED  
POWER ON/OFF OUT  
Power control In ON = H  
POWER LED OUTPUT Out  
Power LED on-control  
LED lighting = L  
9
SS RST  
STARSIGHT RESET  
DVD CONTROL  
Out  
Out  
Out  
Reset = L  
0V  
0V  
10  
11  
DVD CONT  
SCL0  
DVD = L, Other = H  
IIC bus clock output 0  
IIC BUS CLOCK OUT  
12  
13  
SDA0  
SYNC VCD  
IIC BUS DATA IN/OUT In/Out  
IIC bus data input/output 0  
Main picture H. sync signal input  
H SYNC INPUT  
In  
14  
15  
16  
PIP RST  
AFT2 IN  
AFT1  
PIP RESET  
Out  
In  
Reset = L  
Sub tuner AFT S-curve input  
UV MAIN S-CURVE  
SIGNAL  
In  
Main tuner AFT S-curve  
signal input  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
KEY A  
KEY B  
SGV  
LOCAL KEY INPUT  
LOCAL KEY INPUT  
TEST SIGNAL OUT  
TEST AUDIO OUT  
POWER GROUNDING  
CLOCK OSD  
In  
Local key detection: 0 to 5V  
Local key detection: 0 to 5V  
In  
Out  
Out  
—
Test signal output In normal = L 0V  
SGA  
Test audio output In normal = L  
0V: Gounding voltage  
0V  
0V  
VSS  
CLK  
Out  
Out  
In  
At display on: Pulse  
At display on: Pulse  
At display on: Pulse  
At display on: Pulse  
CS  
CHIP SELECT  
BUSY  
DATA  
OSD RESET  
VSYNC  
OSC1  
OSC2  
TEST  
BUSY OSD  
DATA OSD  
Out  
Out  
In  
RESET OSD  
Reset = L  
VSYNC  
4.5MHz  
Pulse  
DISPLAY CLOCK  
DISPLAY CLOCK  
TEST MODE  
Out  
In  
Pulse  
Pulse  
In  
GND fixed  
0V  
XIN  
SYSTEM CLOCK  
SYSTEM CLOCK  
SYSTEM RESET  
In  
System clock input  
System clock output 8MHz  
8MHz pulse  
8MHz pulse  
XOUT  
RESET  
EXT SP  
RMT IN  
Out  
In  
System reset input (In reset = L) 5V  
EXTERNAL = L, INT = H  
EXTERNAL SPEAKER In  
REMOTE CONTROL  
SIGNAL INPUT  
In  
In remote control pulse input = L In reception of  
remote pulse  
36  
37  
38  
39  
40  
41  
42  
SYNC AV1  
SCL1  
HSYNC INPUT  
In  
External H. sync signal input  
IIC bus clock output 1  
IIC bus data input/output 1  
STOP = L  
Pulse  
Pulse  
Pulse  
IIC BUS CLOCK OUT  
Out  
SDA1  
IIC BUS DATA IN/OUT In/Out  
I2C STP  
SS VD  
ACP  
IIC BUS STOP  
STARSIGHT VD  
NSYNC INPUT  
POWER  
In  
In  
In  
—
VSYNC for Starsight  
AC pulse input  
Pulse  
5V  
VDD  
5V  
20  
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5. EEPROM (QA02)  
Type name is 24LC08BI/P or ST24C08CB6, and those are  
the same in pin allocation and function, and are exchange-  
EEPROM (Non volatile memory) has function which, in spite  
of power-off, memorizes the such condition as channel se-  
lecting data, last memory status, user control and digital pro-  
cessor data. The capacity of EEPROM is 8k bits.  
2
able each other. This IC controls through I C bus. The power  
supply of EEPROM and MICOM is common. Pin function  
of EEPROM is shown in Fig. 3-3.  
EEPROM(QA02)  
A0  
A1  
1
2
3
4
Vcc  + 5V  
NC  
8
7
6
5
Device adress  
GND  
A2  
SCL  
I2C-BUS line  
Vss  
SDA  
Fig. 3-3  
6. ON SCREEN FUNCTION  
QR60 is controlled by the microprocessor QA01 with the  
exclusive control signals of CLK, DATA, CS, BUSY, RE-  
SET.  
The OSD system of TW40F80 employs the external OSD  
IC (QR60, MB90091) to obtain high quality OSD.  
QA01 Microprocessor  
QR60 MB90091  
CLK  
22  
SCLK  
SCS  
R OUT  
G OUT  
B OUT  
54  
56  
58  
55  
16  
59  
60  
CS  
BUSY  
23  
24  
TRE  
61  
DATA  
SIN  
25  
26  
OSD RESET  
RESET  
VOB2  
VIDEO  
(YM)  
64  
Fig. 3-4  
21  
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7. SYSTEM BLOCK DIAGRAM  
QA01  
TMP87CS38N-XXXX  
HO01  
Main  U/V  tuner  
      ELA12L  
SDA SCL  
QA02  
SDA  1  
38  
37  
Memory  
24LC08BI/P  
SDA SCL  
SCL  1  
RMT  
Remote  
controller  
light  
receiving  
unit  
35  
5
6
HY01  
Sub  U/V  tuner  
      EL922L  
SDA SCL  
SCL  0  
SDA  0  
11  
12  
KEY-A  
KEY-B  
Key  
switch  
17  
18  
INT4  
40  
27  
V.sync  
pulse  
VSYNC  
Q501  
RST  
VDD  
33  
42  
1
Power  
supply  
circuit  
VCD  
    TA1222AN  
SDA SCL  
GND  
Remote  
controller  
output  
27 28  
RMT  OUT  
VSS  
21  
7
3
POWER  
ACP  
HO02  
41  
8
IF/MPX/A.PRO  
   MVUS5345  
SDA SCL  
LED  
Audio  mute  
MUTE  
4
5
21 20  
Speaker  
mute  
SP  MUTE  
XIN  
31  
32  
8MHz  
Clock  
QV01  
XOUT  
AV  SW  
    TA1218N  
SDA SCL  
25  
24  
SGV  
SGA  
19  
20  
Signal  
output  
DATA  
CLK  
25  
22  
23  
24  
26  
DPC  unit  
CS  
Main screen  
Sync  det.  
AFT  det.  
DATA CLK  
BUSY  
RESET  
SYNC-AV1  
AFT1  IN  
36  
16  
Sub screen  
Sync  det.  
AFT  det.  
QZ01  
SYNC-AV2  
AFT2  IN  
13  
2
YCS  
     TC9086F  
SDA SCL  
20 19  
QR60  
OSD  
   MB90091  
CLK DATA CS BUSY  
QH30  
QY91  
QY03  
C/C,EDS  
XC144144P  
SDA SCL  
DUAL  micro-  
processor  
POP  
      
TC9092F  
SDA SCL  
14  
55  
56  
58  
15  
54  
QX01  
WAC  
TC9097F  
Q701  
QK06  
CONVER  
T7K64  
AUTO  LIVE  
SDA SCL  
SDA SCL  
SDA SCL  
60  
44  
39  
59  
43  
40  
Fig. 3-5  
22  
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8. LOCAL KEY DETECTION METHOD  
Local key detection in the N5SS chassis is carried out by  
using analog like method which detects a voltage appears at  
local key input terminals (pins 17 and 18) of the microcom-  
puter when a key is pushed. With this method using two  
local key input terminals (pins 17 and 18), key detection up  
to maximum 14 keys will be carried out.  
17  
18  
SA08  
SA01  
The circuit diagram shown left is the local key circuit. As  
can be seen from the diagram, when one of keys among SA-  
01 to SA-08 is pressed, each of two input terminals (pins 17  
SA06  
SA05  
SA07  
SA02  
SA03  
SA04  
and 18) developes a voltage V corresponding to the key  
IN  
pressed. (The voltage measurement and key identification  
are carried out by an A/D converter inside the microproces-  
sor and the software.  
Fig. 3-6 Local key assignment  
Table 3-1 Local key assignment  
Key No.  
SA-02  
SA-03  
SA-04  
SA-05  
SA-06  
Function  
POWER  
CH UP  
Key No.  
Function  
SA-01  
DEMO START/STOP  
CH DN  
VOL UP  
VOL DN  
SA-07  
SA-08  
ANT/VIDEO, ADV  
MENU  
23  
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9. REMOTE CONTROL CODE ASSIGNMENT  
Custom codes are 40-BFH (TV set for North U.S.A.)  
Custom codes are 40-BFH (TV set for North U.S.A.)  
Applicable  
to remote  
control  
Applicable  
to remote  
control  
Code  
Applicable Conti-  
to TV set nuity  
Code  
Applicable Conti-  
to TV set nuity  
Function  
Function  
50H PIP STILL  
51H PIP ON/OFF  
52H Do not use. Old type core power ON  
53H PIP SWAP  
54H PIC SIZE  
00H  
01H  
02H  
03H  
04H  
05H  
06H  
07H  
08H  
09H  
0AH  
0 Channel  
1 Channel  
2 Channel  
3 Channel  
4 Channel  
5 Channel  
6 Channel  
6 Channel  
8 Channel  
8 Channel  
100 Channel  
55H DSP F/R  
56H WIDE/SCROLL  
57H CAPTION  
58H EXIT  
59H CYCLONE, SBS  
5AH SET UP  
5BH OPTION  
0BH ANT 1/2  
0CH RESET  
0DH AUDIO  
0EH PICTURE/FUNC  
0FH TV/VIDEO  
5CH SUB WOOFER UP  
5DH SUB WOOFER DOWN  
5EH  
5FH  
80H MENU  
81H EDS  
82H ADV UP  
83H ADV DWN  
84H  
85H GUIDE  
86H THEME  
87H LIST  
88H PIP CONTROL  
89H ENTER/TUNE  
8AH PAGE UP  
8BH DATA UP  
8CH PAGE DN  
8DH DATA DN  
8EH CANCEL  
8FH REC  
10H MUTE  
11H CHANNEL SEARCH  
12H POWER  
13H MTS  
14H ADD/ERASE  
15H TIMER/CLOCK  
16H AUTO PROGRAM  
17H CHANNEL RETURN  
18H DSP/SUR (TV/CATV)  
19H CONTROL UP  
1AH VOLUME UP  
1BH CHANNEL UP  
1CH RECALL  
1DH CONTROL DOWN  
1EH VOLUME DOWN  
1FH CHANNEL DOWN  
90H  
40H PIP LOCATE  
91H  
41H PIP LOCATE  
92H Do not use. Old type core power ON  
42H PIP LOCATE  
93H  
43H PIP LOCATE  
94H  
44H CARVER  
95H  
96H  
45H SURROUND UP  
46H SURROUND DOWN  
47H VOCAL ZOOM  
48H CHANNEL LOCK  
49H  
97H NOISE CLEAN  
98H  
99H  
9AH PIP VOLUME UP  
9BH  
9CH PIP CONTROL  
9DH  
4AH PIP CHANNEL UP  
4BH PIP CHANNEL DOWN  
4CH PIP STILL/RELEASE  
4DH PIP ZOOM, ZOOM SIZE  
9EH PIP VOLUME DOWN  
9FH  
4EH PIP LOCATE (CH SEARCH)  
4FH PIP SOURCE  
24  
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Custom codes are 40-BFH (TV set for North U.S.A.)  
Custom codes are 40-BFH (TV set for North U.S.A.)  
Code  
Applicable Conti-  
Function  
Code  
Applicable Conti-  
Function  
to TV set  
nuty  
to TV set  
nuty  
A0H SUB-BRIGHT ADJUSTMENT  
A1H G. DRIVE ADJUSTMENT  
A2H B. DRIVE ADJUSTMENT  
A3H  
D0H  
D1H  
D2H Do not use. Old type core power ON  
D3H  
A4H CUTOFF DRIVE 40H INITIALIZING,  
HORIZONTAL ONE LINE  
D4H  
D5H  
A5H R. CUTOFF ADJUSTMENT  
A6H G. CUTOFF ADJUSTMENT  
A7H B. CUTOFF ADJUSTMENT  
A8H MEMORY ALL AREA INITIALIZE  
A9H PIP BRIGHT ADJUSTMENT  
AAH SUB CONTRAST ADJUSTMENT  
ABH HOR, VER PICTURE POSITON ADJUSTMENT  
ACH SUB COLOR ADJUSTMENT  
ADH SUB TINT ADJUSTMNET  
AEH ADJUSTMENT-UP  
D6H  
D7H PIP VIDEO ADJ.  
D8H STILL, FRAME ADVANCE  
D9H  
DAH SPEED  
DBH  
DCH ZOOM  
DDH  
DEH  
DFH  
AFH ADJUSTMENT-DOWN  
E0H PINCUTION/EWCORER(PARA/CNR)  
B0H HORIZONTAL ONE LINE: SERVICE  
B1H DSP ON/OFF  
E1H VERTICALS-CUVECORRECTION/  
B2H TEXT-1  
VERTICALM-CURVE  
B3H TV/PIP VIDEO CHANGE-OVER  
B4H CAPTION-1  
CORRECTION(VSC/FVC)  
E2H  
B5H  
E3H  
B6H  
E4H  
B7H TV/CABLE CHANGE-OVER IN  
SAME TIME ON MAN AND SUB  
B8H HOTEL SETTING MENU  
B9H DATA 4 TIMES SPEED UP  
BAH DATA 4 TIMES SPEED DOWN  
BBH CHANGE-OVER OF HOTEL/NORMAL  
BCH PIP CENTER  
E5H  
E6H  
E7H  
E8H  
E9H  
EAH HORIZONTAL WIDTH (WID/PARA)  
EBH TRAPEZOIDECORRECTION(TRAP)  
ECH TEST TONE  
BDH M MODE  
EDH DOLBY  
BEH CAPTON OFF  
BFH ALL CHANNEL PRESET  
EEH 3 DIMENTIONAL Y/C SEPARATION  
EFH DPC  
C0H  
E0H  
STANDARD(HEIGHTLINEARITY)(VLIN/HIT)  
C1H DIRECT WIDE 1  
E1H WIDE (HEIGHT ® LINEARITY) (VLIN)  
C2H DIRECT FULL  
F2H SCROOL  
C3H  
C4H  
C5H  
C6H  
C7H  
C8H  
C9H  
CAH  
CBH  
CCH  
CDH  
CEH  
CFH  
F3H WIDE 1, 2, 3  
F4H  
F5H  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
FCH  
FDH  
FEH  
FFH  
25  
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9-1. Optional Setting for Each Model  
OPT0  
OPT1  
MODELS  
CN35F90  
CN35F95  
CX35F70  
TW56F80  
TW40F80  
TP61F90  
TP61F80  
TP55F80  
TP55F81  
TP50F90  
TP50F60  
TP50F61  
D7 D6 D5 D4 D3 D2 D1 D0 HEX D7 D6 D5 D4 D3 D2 D1 D0 HEX  
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
00H  
00H  
02H  
02H  
92H  
02H  
12H  
12H  
12H  
02H  
92H  
92H  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
00H  
00H  
00H  
1CH  
18H  
1CH  
18H  
10H  
10H  
14H  
10H  
10H  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
MODE:  
Fixed  
Normal00  
STD: 01  
HRC: 10  
1RC: 11  
• When the character generation is changed from  
MB90091-107 TO MB90091-108, D5 bit of OPT0 in  
the design data should be set to “1”.  
26  
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10. ENTERING TO SERVICE MODE  
12. SERVICE ADJUSTMENT  
1. PROCEDURE  
1. ADJUSTMENT MENU INDICATION ON/OFF :  
MENU key (on TV set)  
(1) Press once MUTE key of remote hand unit to indicate  
MUTE on screen.  
2. During display of adjustment menu, the followings are  
effective.  
(2) Press again MUTE key of remote hand unit to keep  
pressing until the next procedure.  
a) Selection of adjustment item :  
(3) In the status of above (2), wait for disappearing of in-  
dication on screen.  
POS UP/DN key (on TV/remote unit)  
b) Adjustment of each item :  
(4) In the status of above (3), press MENU (Channel set-  
ting) key on TV set.  
VOL UP/ DN key (on TV / remote unit)  
c) Direct selection of adjustment item  
R CUTOFF  
G CUTOFF  
B CUTOFF  
:
:
:
1 POS (remote unit)  
2 POS (remote unit)  
3 POS (remote unit)  
2. Service mode is not memorized as the last-memory.  
3. During service mode, indication S is displayed at upper  
right corner on screen.  
d) Data setting for PC unit adjustment  
SUB CONTRAST 4 POS (remote unit)  
5 POS (remote unit)  
6 POS (remote unit)  
:
11. TEST SIGNAL SELECTION  
SUB COLOR  
SUB TINT  
:
1. In OFF state of test signal, SGA terminal (Pin 20) and  
SGV terminal (Pin 21) are kept “L” condition.  
:
e) Horizontal line ON/OFF : VIDEO (on TV set)  
f) Test signal selection VIDEO (remote unit)  
2. The function of VIDEO test signal selection is cyclically  
changed with VIDEO key (remote unit).  
:
* In service mode, serviceable items are limited.  
Table 3-2  
Test Signal No.  
Name of Pattern  
Signal OFF  
3. Test audio signal ON / OFF : 8 POS (remote unit)  
* Test audio signal : 1 kHz  
0
1
All black signal + R single color (OSD)  
All black signal + G single color (OSD)  
All black signal + B single color (OSD)  
All black signal  
2
4. Self check display  
:
9 POS (remote unit)  
3
* Cyclic display (including ON/OFF)  
4
5
All white signal  
5. Initialization of memory :  
6
W/B  
CALL (remote unit) + POS UP (on TV set)  
6. Initialization of self check data :  
CALL (remote unit) + POS DN (on TV set)  
7. BUS OFF :  
CALL (remote unit) + VOL UP (on TV set)  
7
Black cross bar  
8
White cross bar  
9
Black cross hatch  
10  
11  
12  
13  
14  
15  
White cross hatch  
White cross dot  
Black cross dot  
H signal (bright area)  
H signal (dark area)  
Black cross + G signal color  
(3) SGA (audio test signal) output should be square wave  
of 1 kHz.  
27  
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13. FAILURE DIAGNOSIS PROCEDURE  
Model of N5SS chassis is equipped with self diagnosis func-  
tion inside for trouble shooting.  
13-1. Contents to be Confirmed by Customer  
Table 3-3  
Contents of self diagnosis  
Display items and actual operation  
A. DISPLAY OF FAILURE INFORMATION IN NO  
PICTURE (Condition of display)  
Power indicator lamp blinks and picture does not come.  
1. When power protection circuit operates;  
1. Power indicator red lamp blinks. (0.5 seconds interval)  
2. Power indicator red lamp blinks. (1 seconds interval)  
If these indication appears, repairing work is required.  
2
2. When I C-BUS line is shorted;  
13-2. Contents to be Confirmed in Service Work (Check in self diagnosis mode)  
Table 3-4  
Contents of self diagnosis  
Contents of self diagnosis  
Display items and actual operation  
Display items and actual operation  
< Countermeasure in case that phonomenon always arises >  
B. Detection of shortage in BUS line.  
(Example of screen display)  
SELF CHECK  
C. Check of comunication status in BUS line.  
D. Check of signal line by sync signal detection.  
E. Indication of part code of microcomputer (QA01).  
F. Number of operation of power protection circuit.  
E
F
Part coce of QA01  
NO. 239XXXX  
Number of operation of  
power protection circuit  
POWER: 000000  
B
C
BUS LINE: OK  
BUS CONT: OK  
Short check of bus line  
Communication check of  
busline  
BLOCK: UV                    V1  V2  
D
                                    QV01, QV01S  
13-3. Executing Self Diagnosis Function  
[CAUTION]  
13-3-1. Procedure  
(1) When executing block diagnosis, get the desired input  
mode (U/V BS VIDEO1, 2, 3) screen, and then enter  
the self diagnosis mode.  
(1) Set to service mode.  
(2) Pressing “9” key on remote unit displays self diagno-  
sis result on screen.  
(2) When diagnos other input mode, do again diagnosis  
operation.  
Every pressing changes mode as below.  
SERVICE mode  
SELF DIAGNOSIS mode  
(3) To exit from service mode, turn power off.  
28  
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13-4. Understanding Self Diagnosis Indication  
In case that phenomenon always arises. See Fig. 3-7 .  
(Example of screen display)  
SELF CHECK  
E
F
Part coce of QA01  
Number of operation of  
power protection circuit  
NO. 239XXXX  
POWER: 000000  
B
C
BUS LINE: OK  
BUS CONT: OK  
Short check of bus line  
Communication check of  
busline  
BLOCK: UV                    V1  V2  
D
                                    QV01, QV01S  
Fig. 3-7  
Table 3-5  
Item  
Contents  
Instruction of results  
BUS LINE  
Detection of bus line short  
Indication of OK for normal result, NG for abnormal  
Indication of OK for normal result  
Indication of failure place in abnormality  
(Failure place to be indicated)  
QA02 NG, H001 NG, Q501 NG, H002 NG, QV01 NG, Q302  
NG, QY02 NG, HY01 NG, QD04 NG, QM01 NG, Q701 NG  
BUS CONT  
Communication state of bus line  
Note:  
The indication of failure place is only one place though  
failure places are plural. When repair of a failure place  
finishes, the next failure place is indicated. (The order of  
priority of indication is left side.)  
*Indication by color  
BLOCK: UV1  
The sync signal part in each video signal  
supplied from each block is detected.  
Then by checking the existence or non of sync  
part, the result of self diagnosis is displayed  
on screen. Besides, when “9” key on remote  
unit is pressed, diagnosis operation is first  
executed once.  
• Normal block  
: Green  
: Cyan  
UV2  
V1  
• Non diagnosis block  
V2  
29  
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13-4-1. Clearing method of self diagnosis result  
White  
Yellow  
In the error count state of screen, press “CHANNEL DOWN”  
button on TV set pressing “DISPLAY” button on remote unit.  
Cyan  
Green  
Magenta  
Red  
Blue  
CAUTION:  
All ways keep the following caution, in the state of service  
mode screen.  
(COLOR BAR SIGNAL)  
Color elements are positioned in sequence of  
high brightness.  
• Do not press “CHANNEL UP” button. This will cause  
initialization of memory IC. (Replacement of memory  
IC is required.)  
• Do not initialize self diagnosis result. This will change  
user adjusting contents to factory setting value. (Adjust-  
ment is required.)  
13-4-2. Method utilizing inner signal  
(VIDEO INPUT 1 terminal should be open.)  
(1) With service mode screen, press VIDEO button on re-  
mote unit. If inner video signal can be received, QV01  
and after are normal.  
(2) With service mode screen, press “8” button on remote  
unit. If sound of 1 kHz can be heard, QV01 and after  
are normal.  
* By utilizing signal of VIDEO input terminal, each circuit  
can be checked. (Composite video signal, audio signal)  
30  
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14. TROUBLESHOOTING CHART  
14-1. TV does Not Turned ON  
TV does not turned on.  
YES  
Relay sound  
NO  
NG  
Check of voltage at pin 7 of QA01  
(DC 5V).  
OK  
Check power circuit.  
NG  
8MHz oscillation waveform  
at pin 32 of QA01.  
OK  
Check OSC circuit.  
Replace QA01.  
NG  
Pulse output at pins 37 and 38 of QA01.  
OK  
NG  
Voltage check at pin 32 of QA01  
(DC 5V)  
OK  
Check reset circuit.  
Check relay driving circuit.  
Replace QA01.  
31  
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14-2. No Acception of KEY-IN  
Key on TV  
NG  
Voltage change at pins 17, 18 of  
QA01 (5V to 0V).  
OK  
Check key-in circuit.  
Replace QA01.  
Remote unit key  
NG  
Pulse input at pin 35 of QA01,  
When remote unit key is pressed.  
OK  
Check tuner power circuit.  
Replace QA01  
14-3. No Picture (Snow Noise)  
No picture  
NG  
Voltage at pins of +5V, and 32V.  
OK  
Check H001.  
Check tuner power circuit.  
32  
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14-4. Memory Circuit Check  
Memory circuit check  
NG  
Voltage check at pin 8 of QA02 (5V).  
OK  
Check power circuit.  
NG  
Pulse input at pins 5 and 6 of QA02  
in memorizing operation.  
OK  
Check QA01.  
Replace QA02.  
Note: Use replacement parts for QA02.  
Adjust items of TV set adjustment.  
14-5. No Indication On Screen  
No indication on screen.  
NG  
Check of RESET at 5V.  
OK  
Replace QA01 or QR60 or QR63.  
NG  
Check of CLK, CS, BUSY, DATA at  
pin 22, 23, 24, 25 of QA01.  
"H" = 5V or puls?  
OK  
Replace QA01 or QR60.  
NG  
Check of character signal at pin 59, 60, 61  
of QR60 (5V(p-p)).  
OK  
Replace QR60.  
Check V/C/D circuit.  
33  
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SECTION IV: DVD SWITCH CIRCUIT  
1. DVD SWITCH BLOCK DIAGRAM  
Q501 VCD  
TA1222AN  
Y
53  
52  
51  
Q
I
DVD SWITCH UNIT  
QW01 TC4053BP  
WAC UNIT  
DUAL UNIT  
L
Y
Q
I
4
5
6
Y
Q
I
Y
Q
I
Y
H
L
Q (B - Y)  
H
L
13  
15  
C
Y
I (R- Y)  
Y
C
H
ZY01 Y/C SEPARATOR  
Sub Y.  
Sub  V.  
Sub C.  
"L" = Normal  
"H" = DVD  
QV01 AV SW  
TA1218N  
QA01  
 MAICROPROCESSOR  
42  
10  
MAIN  
DVD CONTROL  
Sub V.  
36  
34  
Y
2
2
I  C BUS  
I  C BUS  
C
21  
Insertion detection  
VIDEO2/ Y, Cr, Cb  
DVD  
VIDEO VIDEO  
3
1
Fig. 4-1  
34  
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2. OUTLINE  
In this model, the DVD input terminals are provided in or-  
der to receive the color difference signals (Y, Cr, Cb) out-  
put from a DVD player.  
The input identification for VIDEO 2 and DVD is carried  
out by setting pin 21 of QV01 TA1218N (AV SW IC) from  
“L” to “H” when the cable is connected to the Cb input ter-  
minal with a switch equipped.  
The luminance (Y) signal input for DVD input uses the  
VIDEO input terminal in common with the VIDEO 2 input.  
The terminals for color difference signal inputs Cr (R – Y)  
and Cb (B – Y) are used exclusively.  
The main microprocessor QA01 sets pin 10 of QA01 from  
2
“L” to “H” through I C bus when pin 21 of AW SW IC  
develops “H”.  
Open : at Cb input  
Cb input  
Cb to DVD SW unit  
RV28 100k  
+9v  
RV26  
75  
RV27  
10k  
21  
QV01 TA1218N  
Fig. 4-2  
35  
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SECTION V: WAC CIRCUIT  
1. OUTLINE  
and pass a low pass filter and amplifiers in the same way as the  
Y signal, and enter pins 1 and 78 of QX01 respectively.  
A wide aspect conversion (hereafter called WAC) process (3/4  
compression process in 4:3 mode and 1/2 compression process  
on left screen in double window mode) is performed inside the  
WAC unit (PB6348) in TW40F80.  
The Y , I and Q signals entered are clamped by built-in clamp  
circuit, converted into digital signals by the built-in A/D con-  
verter. Moreover, their read/write operations are rated up by twice  
or 3/4 times to perform a compression process of 1/2 or 3/4  
times inside the built-in line memory. And then, a black level  
signal is added to the open area (right half, or both sides of  
screen). Next, the signal is converted to an analog Y, I, and Q  
signals by a built-in D/A converter and output from pins 17, 13,  
and 9. Parameters of 1/2, 3/4 phase of the video signal, phase of  
Screen modes for TF40F80 contain THEATER WIDE1, THE-  
ATER WIDE 2, THEATER WIDE3, FULL, NORMAL and  
DOUBLE WINDOW modes. The video signal compression is  
carried out only when either the NORMAL or DOUBLE WIN-  
DOW mode is selected. In the modes other than the NORMAL  
and DOUBLE WINDOW mode, the video signal input to WAC  
unit is output without performing any process.  
2
the side panel, etc. are controlled through I C bus, control sig-  
The screen in the DOUBLE WINDOW mode creates a single  
screen by superimposing the left screen processed in the WAC  
unit on the right screen processed in the DUAL unit.  
nals of which enters from pins 7 and 8 of PX01.  
Thus processed signals are fed to a low pass filter to remove  
high frequency noises generated in QX01 and then fed to the  
QX03 switching IC. The compressed signal and a not compressed  
signal entered from PX01 are directly fed to QX03, and switched  
by a signal showing compression/not compression (NCS = out-  
put from pin 61 of QX01 and fed to the receive unit through  
pins 5, 6, and 7 of PX02.  
On the left screen, the video signal sent is time-compressed to 1/  
2 in horizontal direction to fit in the left half of the wide screen  
with 16:9 aspect ratio. In this case, a black level of DC is at-  
tached on the right half of the screen in this circuit. However,  
this is superimposed on the right screen, so nothing is visible on  
the screen.  
2-2-2. Clock Generation  
In the normal screen, the video signal is 3/4 time-compressed  
and side panels in the black level are added on sides of the screen.  
The system clock for QX01 is generated by QX02 according to  
an H reference signal supplied from pin 3 of PX02 and fed to  
QX01 through QX19 and QX40. (The frequency is adjusted to  
28.7 ± 0.2 MHz with LX18).  
2. CIRCUIT OPERATION  
The compressing operation is carried out by setting the write  
clock to 1/2 or 3/4 times by the built-in VCO with the reading  
clock fed to pin 47 of QX01.  
2-1. Configuration  
The WAC unit consists of a wide aspect conversion IC (QX01,  
TC9097F, working as a central device), clock generation IC  
(QX02, TA8667F), switch IC (QX03, TC4053BF), and periph-  
eral circuits (LPF, AMP, emitter follower, etc.). The QX01  
(TC9097F) contains anA/D converter, D/A converter, clamp cir-  
cuit, VCO circuit, etc. and performs compression process, etc.  
inside the IC for analog video signals entered according to con-  
trols through IIC bus, thus providing the signal as an analog sig-  
nal.  
2-2-3. Timing Pulse Generation  
Moreover, the WAC unit generates following timing pulses.  
(1) VPout  
Reference signal entered through pin 2 of PX02 enters pin  
3 of QX01, and outputs at pin 8 of PX02 after delayed by  
an amount required. The vertical reference signal is out-  
put in modes other than the normal and double window  
and fed to the vertical circuit. Accordingly, the raster be-  
comes an horizontal one when the unit is disconnected.  
2-2. Operation  
(2) HVBLK  
2-2-1. Signal Flow  
This pulse is a timing pulse showing a black extension  
mask period in the normal and double window modes. It  
outputs at pin 1 of PX02 and enters pin 30 of Q501 in the  
receive unit.  
Fig. 5-1 shows a block diagram of this circuit. A Y signal en-  
tered through pin 6 of PX01 passes a low pass filter an a 6 dB  
amplifier, and enters pin 3 of QX01. On the other hand, I and Q  
signals enter through pin 4 and 5 of PX01,  
36  
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Fig. 5-1 Wide aspect conversion unit block diagram (PB6348)  
37  
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• Pin Function  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65  
1
2
3
4
5
6
7
8
9
ISI  
BCP(TDI5) 64  
NC 63  
VRA2  
YSI  
SE42(TDI6) 62  
NCS(TDI7) 61  
SDA 60  
NC  
VBC  
VRD2  
VBD4  
VDD3(DA2)  
QSO  
SCL 59  
ACP(TMO0) 58  
VDP(TMO1) 57  
ISL(TMO2) 56  
NC 55  
10 NC  
11 VBD3  
12 VSS3(DA2)  
13 ISO  
QSL(TMO3) 54  
SPT(TMO4) 53  
VMO(TMO5) 52  
HRF(TMO6) 51  
VBL(TMO7) 50  
NC 49  
14 VRD1  
15 NC  
16 VDD2(DA1)  
17 YSO  
HBL(TMO8) 48  
RCK 47  
18 VBD2  
19 VSS2(DA1)  
20 VBD1  
21 VSS4(VCO1)  
22 VBV  
WCK 46  
VDD(DIG) 45  
NC 44  
VSS5(VCO2) 43  
NC 42  
23 NC  
24 VFL1  
VFL2 41  
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Fig. 5-2 Pin function of TC9097F (QFP 80 pin)  
38  
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Table 5-1 Names and functions of TC9097F  
No.  
1
Name  
ISI  
I/O  
I
Function  
I color signal input  
2
VRA2  
YSI  
–
I
Reference voltage (low level) for AD1, AD2  
3
Y signal input  
4
NC  
–
–
–
–
–
O
–
–
–
O
–
–
–
O
–
–
–
–
–
I
–
5
VBC  
VBD2  
VBD4  
AVDD  
QSO  
NC  
Bias for clamp 1  
6
Reference voltage for DA2, DA3  
7
Bias 2 (high level) for DA2, DA3  
8
Analog power  
9
Q color signal output  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
–
VBD3  
AGND  
ISO  
Bias 2 (low level) for DA2, DA3  
Analog ground  
I signal output  
VRD1  
NC  
Reference voltage for DA1  
–
AVDD  
YSO  
VBD2  
AGND  
VBD1  
AGND  
NC  
Analog power  
Y signal output  
Bias 1 (high level) for DA1  
Analog ground  
Bias 2 (high level) for DA1  
Analog ground  
–
VFV  
VFL1  
AVDD  
VLM  
VDD  
HDI  
Connected to VSS or VDD  
–
–
–
–
I
Connected to VDD  
Analog power  
1/2 VDD for line memory  
Digital power  
Composite sync signal input  
NC  
–
I
–
VD1  
V sync signal input  
RESET  
NC  
I
Reset input (Normally: High level, Reset: Low level)  
–
–
I
–
NC  
–
TST0  
TST1  
TST2  
NC  
Test mode setting (normally connected to VSS)  
Test mode setting (normally connected to VSS)  
Test mode setting (normally connected to VDD)  
–
I
I
–
39  
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No.  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
Name  
HDF  
GND  
AVDD  
VFL2  
NC  
I/O  
I
Function  
Ext. H sync signal input  
Digital ground  
Analog power  
Loop filter for VCO2  
–
–
–
I
–
–
–
–
–
O
–
–
–
O
–
–
–
O
–
–
–
–
–
I
AGND  
CKSEL  
VDD  
WCK  
RCK  
HBL  
NC  
Analog ground  
VDD  
Digital power  
Ext. clock input (memory write clock)  
Ext. clock input (memory read clock)  
H blanking signal  
VBL  
HRF  
VMO  
SPT  
V blanking signal  
H AFC reference signal  
H AFC mask signal  
Side panel timing signal  
Q signal select pulse  
–
QSL  
NC  
ISL  
I signal select pulse  
V drive pulse  
VDP  
ACP  
SCL  
Later stage clamp pulse  
2
I C SCL signal input  
2
SDA  
NCS  
SE42  
NC  
I C SDA signal input/output  
Prefilter switch signal 1  
–
–
–
–
I
Prefilter switch signal 2  
–
BCP  
TD14  
TD13  
TD12  
TD11  
TD10  
NC  
Prestage clamp pulse output  
Test input (normally connected to VSS)  
Test input (normally connected to VSS)  
Test input (normally connected to VSS)  
Test input (normally connected to VSS)  
Test input (normally connected to VSS)  
–
–
I
I
–
–
I
GND  
NC  
Digital ground  
NC  
I
AVDD  
VRA1  
I
Analog power  
–
Reference voltage for AD1, AD2  
40  
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No.  
76  
77  
78  
79  
80  
Name  
NC  
I/O  
–
Function  
–
VBM  
QSI  
–
Bias for MPX, clamp 2  
Q color signal input  
Bias for AD1, AD2  
Analog ground  
I
VBA  
AGND  
–
–
3. BLOCK DIAGRAM  
Fig. 5-3 TC9097F system block diagram  
41  
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4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS  
PROCEDURES  
4-1. Left Screen Picture Failure in Normal Mode/Double Window Modes  
(No Picture, Sync Distributed)  
Picture fallure  
(Normal/DW mode)  
Y
N
N
N
N
Y
N
Super live  
mode OK?  
Output at pins  5  ,  6  ,  
7  of PX02 OK?  
Check circuits other  
than WAC unit.  
N
Y
Check around  
of QX03.  
LX18 adjustment  
 OK?  
Readjustment  
Y
I2C bus pin  7  ,  8  
of PX01 OK?  
I2C bus line check.  
Y
Y
Check around  
QX02.  
Is clock at pin 47  
of QX01 OK?  
Output at pin  3  (HD)  
of PX02 OK?  
Y
N
Check receive  
circuit.  
Signals at pins  5  ,  6  ,  
7  of PX02 OK?  
Receive circuit check.  
N
QX01 input / output  
OK?  
Replace  
E2PROM OK?  
Replace QX01.  
Y
Check associated  
circuit (Tr.etc).  
END  
42  
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4-2. Raster Horizontal One  
Horizontal one  
Y
N
N
N
Output at pin  8  
of PX02 OK?  
Check V circuit.  
N
Output at pin  2  
of PX02 OK?  
Check receive circuit.  
Y
Check I 2  
C
Is output OK  
at I2C bus?  
bus line.  
Y
Data initlalization OK?  
Y
Replace QX01.  
END  
4-2-1. Adjustment Method  
(1) Disconnect any video inputs  
(2) Open RX-40.  
(3) Connect frequency counter to QX19 emitter.  
(4) Adjust LX18 until frequency reading of “28.7 MHz  
± 0.5 MHz” is obtained.  
43  
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SECTION VI: DUAL CIRCUIT  
1. OUTLINE  
DUAL circuit performs the signal process, etc. on the sub  
• 9-screen multi-search process  
screen and is composed of the followings as shown in Fig. 6-  
1.  
The sub screen process IC (TC9092AF) is the IC using the  
programmable technology and can realize various functions  
such as sub screen 1/2 compression, 9-screen multi-search,  
etc. by switching the program.  
• Video/color/deflection (V/C/D) process  
• On-screen display (OSD) superimposing process  
• Sub-screen process, memory  
The 9-screen multi-search process is carried out by selecting  
the channel on the right half of the wide screen with 16:9  
aspect ratio and the picture images received are projected on  
the 9 screens from the upper left screen in order.  
• Main/Sub screen picture superimposing process  
• Sub screen control microprocessor  
The search is carried out by approx. every 2 seconds repeat-  
edly. When the next picture image is searched, the picture  
image on the previous screen becomes a still picture. When  
the 9 screens are finished projecting (to the picture image on  
the right bottom screen), the search operation is carried out  
repeatedly from the upper left screen.)  
2. PRINCIPLES OF OPERATION  
DUAL circuit is composed of the following functions.  
(1) Double window sub screen 1/2 compression process  
(2) Sub screen still process  
(3) 9-screen multi-search process  
(4) Main/Sub screen superimposing process by YIQ sig-  
nal.  
44  
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3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT  
2M memory X2  
MSM518221-30ZS  
Y
Y
I
Sub screen  
process IC  
Main/Sub  
picture  
superimpose  
ON-screen  
display super  
impose  
Video/color/  
deflection  
process  IC  
From tuner  
SY  
R- Y  
B- Y  
R- Y  
B- Y  
TC9092AF  
TC4W53F  
MC74HC4053F  
Q
MC74HC4053F  
µPC1832GT  
I2C BUS  
SC  
OSD  
Y
I
Q
Y
I
Q
Sub screen  
control micro-  
processor  
I
Wide aspect  
conversion  
Q
TC9097F  
CXP85116B-514Q  
I2C BUS  
Control  
Y
I
Q
To CRT  
G
From main microprocessor  
From tuner  
SY  
V/C/D IC  
TA1222N  
B
R
SC  
Fig. 6-1  
45  
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4. CIRCUIT OPERATION  
4-1. Video/Color/Deflection Process Section  
Since the sync signal is added to the luminance signal, the  
signal is input to pin 39 of QY01 (SYNC SEP IN) and the  
sync signals of HD and VD are output to pins 10 and 11 of  
QY01. The HD signal is waveshaped by QY42.  
The video/color/deflection section is shown in Fig. 6-2.  
The luminance signal is supplied from pinY08 of PY01 and  
its frequency bandwidth is limited by the low pass filter (LPF)  
and then input to pin 36 of V/C/D IC (VIDEO IN). The Y  
signal output from pin 12 of PY01 superimposes the charac-  
ter signal on the video signal by QY49 and QY44, and then  
output to the sub screen process section.  
The HD signal (WHD1, WHD2) is used as the horizontal  
pulse for sub screen write and theVD signal (WVD) is as the  
vertical pulse for sub screen write in the sub screen process  
section.  
In the sub screen microcomputer section, various kinds of  
control signals (brightness, density, hue, etc.) are output from  
the sub screen control microprocessor QY91 and the signals  
are used for the level matching adjustment. So the setting for  
the sub screen cannot be made by the user. Furthermore, the  
OSD signal for OSD superimposing is output.  
QY49 and QY44 work as the analog switches. When the  
screen is displayed in DW, the switch operation is not car-  
ried out and the same signal as the input signal is output, and  
when the 9-screen multi-search process is carried out, the  
switch operation is carried out.  
The sub screen process IC control program is stored in the  
nonvolatile memory of the sub screen control microproces-  
sor QY91 in order to control the sub screen process IC  
The OSD signal superimposes the shade of character signal  
by QY49 and the character signal by QY44 on Y signal.  
On the other hand, the color signal is supplied from pinY15  
of PY01, limited its frequency bandwidth by the band pass  
filter (BPF) and then input to pin 34 of QY01 (COLOR IN).  
The color difference signals of the demodulated signal (R –  
Y) and ( B – Y) are output from pins 13 and 14 of QY01. In  
the same way as theY signal, the (R –Y) and (B –Y) signals  
are superimposed on the character signal with OSD signal  
by QY44.  
2
(TC9092AF), and the data is sent via I C bus.  
The GBR matrix circuit which converts theY, R –Y and B –  
Y signals into three primary color signal of G, B and R is  
used to convert the (R – Y) and (B – Y) signals into I and Q  
signals.  
In the GBR matrix circuit, each G, B and R output is output  
as G –Y, B – Y and R signals when theY signal is not input.  
Then the B – Y signal is converted to Q signal, R – Y to I  
signal pseudically by turning the phase by an angle of 33°.  
Thus, R –Y and B –Y signals are input to pins 18 and 19 of  
QY01, and the output signals from pins 23 and 24 are devel-  
oped as the I and Q converted signals pseudically. The am-  
plitude of the signals is amplified by 6 dB amplifier of QY23  
and the signals are output to the sub screen process section.  
46  
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I2C BUS(SCL,SDA)  
Sub  screen  microprocessor  section  
OSD  
OSD  
QY91  CXP85116B-514Q  
PY01  
QY44  
MC74HC4053F  
QY49  
TC4W53F  
SCLP 50  
QY01 µPC1832GT  
V/C/D  IC  
5
SCL  
9
11  
SDAP 48  
BLK 46  
B 43  
49 SCL2  
47 SDA2  
Y13  
Y14  
OSD  
SDA  
superimpose  
Y
Y  OUT 12  
7
1
12  
5
14  
4
R-Y  OUT 13  
B-Y  OUT 14  
COL 53  
20 COLOR  
21 TINT  
TIN 54  
S.COL 51  
CON 52  
2
15  
37 SUB  COL.  
38 CONTRAST  
41 fsc  SELECT  
42 PAL/NTSC  
R-Y  IN 18  
B-Y  IN 19  
fsc  SEL 62  
PAL/NTSC 61  
QY22  MM1031XMR  
3.58  
2
Control  
I
R  OUT(I) 23  
B  OUT(Q) 24  
6dB.  Amp  
6dB.  Amp  
3
3
1
1
Sub  screen  control  
microprocessor  
Q
39 SYNC  SEPA  
IN  
36 VIDEO  IN  
QY23  MM1031XMR  
QY42  TC74HC123AF  
PIP  VIDEO  
PIP  C  
L.P.F  
B.P.F  
Y08  
Y15  
WHD2  
WHD1  
1Q 13  
2Q  
Waveform  
shape  
HD  OUT 10  
VD  OUT 11  
1
1A  
34 CHROMA  IN  
5
WVD  
Fig. 6-2  
47  
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4-2. Sub Screen Process Section  
The sub screen process section is shown in Fig. 6-3.  
The horizontal sync signal RHD for reading-out and the ver-  
tical sync signal RVD for reading out input to pins 75 and 77  
of QY03 trigger the reading at 18.0 MHz which is created  
by 2/3-multiplying 27.0 MHz developed in LY101and then  
output as the analog signal.  
The Y, I and Q signals from the video/color/deflection pro-  
cess section are limited in their frequency bandwidth by the  
LPF in the prceeding stage and input to pins 6, 13 and 15 of  
QY03.  
The Y, I and Q signals converted for the sub screen are out-  
put from pins 95, 100 and 97 of QY03. The output signals  
are used for the input signals compressed by 1/2 in the hori-  
zontal direction in the double window mode and for the in-  
put signal compressed by 1/6 in the horizontal direction and  
by 1/3 in the vertical direction in 9-screen multi-search mode.  
The frequency of 18.5 MHz generated by LY102 is multi-  
plied by 1/2 inside QY03. The Y signal is sampled by 9.25  
MHz and the I and Q signals are sampled by 4.63 MHz (1/2  
frequency to multiplex) and then the signals are converted  
into 8-bit digital signals.  
The horizontal sync signal WHD (the signal mixed with  
WHD1 and WHD2 by QY43) for writing input to pins 21  
and 20 of QY03 and the vertical sync signal WVD for trig-  
ger writing on the field memory QY10 and QY11.  
Then the signals are smoothed by the LPF in the next stage  
then input to the main/sub screen superimposing section.  
QY03 TC9092AF  
Sub screen process IC  
Y
Y
I
6
95  
100  
97  
L.P.F  
L.P.F  
L.P.F  
Y IN  
Y OUT  
R-Y OUT(I)  
B-Y OUT(Q)  
L.P.F  
L.P.F  
L.P.F  
I
13  
15  
R-Y IN  
B-Y IN  
Q
Q
I2C BUS (SCL, SDA)  
YS  
70  
79  
80  
SCL  
SDA  
YS OUT  
QY10, QY11  
MSM518221-30ZS  
WVD  
2M  
memory  
Date in  
48  
32  
MWD 0  
MWD15  
20  
21  
FVS  
FHS  
WHD2  
WHD1  
OR  
circuit  
1
2
WHD  
4
QY43  
TC7S32F  
24  
25  
OSCSI  
OSCSO  
51  
65  
MRD 0  
MRD15  
LY102  
77  
75  
Date out  
FVM  
FHM  
PY01  
72  
73  
OSCMI  
RVD  
Y11  
OSCMO  
LY101  
RHD  
YS  
Y12  
Y01  
Fig. 6-3 Sub screen process section  
48  
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4-3. Main/Sub Screen Superimposing Section  
The main/sub screen superimposing section is shown in Fig.  
6-4.  
In normal mode (with only the main screen picture displayed),  
the YS signal voltage always goes low and the Y, I and Q  
signals from the digital unit are developed at pins 15, 4 and  
14 of QY48.  
The sub screen Y, I and Q signals sent from the sub screen  
process section and the main screen Y, I and Q signals sent  
from the digital unit through the receive circuit and etnered  
pins 3, 2, and 1 of PY02 are clamped at a same electrical  
potential and the former are fed to pins 1, 3, 13 and the latter  
fed to pins 2, 5 and 12 of QY48.  
The Y, I and Q signals for the main/sub screens superim-  
posed are developed at pinsY05, Y06 and Y04 of PY01 and  
then supplied to the receive circuit.  
The Y, I and Q signals for the main/sub screens superim-  
posed inside the receive circuit are entered to pins 53, 51 and  
52 of Q501 (TA1222N) and then fed to CRT. The video  
signal is processed in Q501 without distinguishing the sig-  
nals for main and sub screens, so the high picture quality can  
be obtained equally for both the screens.  
The clamp circuit contains a clamp pulse waveshaping SCP  
at pin 4 of PY02, analog switches for ever-voltage source E,  
QY46 and QY47 and clamp capacitors CY230 ~ CY232,  
CY238 ~ CY240.  
QY48 is an analog switch to feed the Y, I and Q signals for  
either sub screen or main screen to pins 15, 4 and 14 by the  
YS signal voltage fed to pins 9, 10 and 11. When the YS  
signal develops high, QY48 selects the signals for the sub  
screen and when low, QY48 selects the signals for the main  
screen. Consequently, the signals for both the main and sub  
screens are superimposed each other.  
QY48  MC74HC4053  
Clump  capacitor  
Y
I
CY231  
CY230  
CY232  
1
3
IY (Y IN)  
IZ (I IN)  
Q501  
TA1222N  
PY01  
YOUT  
Q
13 IX (Q IN)  
Y
I
R
G
B
YS  
11 A Y COM (Y OUT) 15  
53  
43  
42  
41  
Y05  
Y06  
I
10 B Z -COM (I OUT)  
4
51  
52  
Clump  capacitor  
CY239  
PY02  
Q
Q
9
2
5
C X-COM (Q OUT) 14  
Y04  
YD  
ID  
OY (Y IN)  
OZ (I IN)  
3
2
CY240  
QD  
CY238  
12 OX (Q IN)  
1
Main/Sub  picture  
superimpose  
QY46  
TC74HC4066AF  
QY47  
TC74HC4066AF  
SCP  
4
3
9
1
4
8
2
3
9
1
4
8
2
Analog  
SW  
Analog  
SW  
5
6
13  
5
6
13  
Clump  
pulse  
 Waveform  
shape  
Constant voltage  
source E  
Fig. 6-4 Main/Sub screen superimposing section  
49  
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5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF  
MAIN IC  
Fig. 6-5 QY01 mPC1832GT internal block diagram  
50  
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32fm VCO felter 1  
32fm VCO felter 1  
32fm VCO felter 1  
H.AFC filter  
1
2
3
4
5
6
7
8
9
42 PAL/NTSC  SW  
41 fsc SW  
40 H. sync det. filter  
39 Sync sepa input  
38 Contrast control  
37 Sab color control  
36 Composite video signal input  
35 Power supply (color)  
GND (sync)  
fv 50/60 SW  
Power supply (sync)  
Color killer output  
Blanking pulse output  
34 Separati color input  
33 GND (color)  
32 ACC filter  
HD pulse output 10  
VD pulse output 11  
Y output 12  
31 Io. filter  
R-Y output 13  
30 Color APC filter  
29 fsc VCO input (4.43MHz)  
28 fsc VCO input (3.58MHz)  
27 fsc VCO output  
26 Color killer filter  
25 B output  
B-Y output 14  
GND (video) 15  
Y input 16  
Power supply (video) 17  
R-Y input 18  
B-Y input 19  
24 G output  
Color control 20  
Tint control 21  
23 R output  
22 Clamp pulse input  
Fig. 6-6 QY01 mPC1832GT pin layout  
51  
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MPX  
CLAMP  
Fig. 6-7 QY03 TC9092AF internal block diagram  
52  
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50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31  
WE  
IE  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
MRD1  
MRD2  
MRD3  
MRD4  
MRD5  
MRD6  
MRD7  
MRD8  
MRD9  
MRD10  
RMD11  
RMD12  
MRD13  
MRD14  
MRD15  
RE  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
CKW  
VDD  
VSS  
OSCSO  
OSCSI  
VDD  
NFHS  
FHS  
FVS  
VDD  
VSS  
ADDVSS  
ADDVDD  
RYIN  
TC9092AF  
(TOP VIEW)  
ADBIAS  
RYIN  
RSTR  
CKR  
ADVREFC  
ADVDD  
CLAMPC  
ADVSS  
CLAMPY  
ADVSS  
YIN  
CKRI  
YSOUT  
VSS  
OSCMI  
OSCMO  
VDD  
8
7
FHM  
6
ADVREFY  
ADVDD  
DABIAS2  
DABIAS3  
DAVSS  
HFHM  
FVM  
5
4
VSS  
3
SCL  
2
SDA  
1
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  
Fig. 6-8 QY03 TC9092AF pin layout  
53  
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Table 6-1 QY03 TC9092AF pin list (No. 1)  
No.  
1
2
3
4
Pin name  
DAVSS  
DABIAS3  
DABIAS2  
ADVDD  
ADVREFY  
YIN  
I/O  
Pin function  
D/A GND  
D/A bias condenser connection terminal  
D/A bias condenser connection terminal  
A/D power supply  
A/D Y reference condenser connection terminal  
A/D Y input terminal  
5
6
I
I
7
8
9
ADVSS  
CLAMPY  
ADVSS  
CLAMPY  
ADVDD  
ADVREFC  
RYIN  
ADBIAS  
BYIN  
ADDVDD  
ADDVSS  
VSS  
A/D GND  
Y clamp bias condenser connection terminal  
A/D GND  
C clamp bias condenser connection terminal  
A/D power supply  
A/D reference condenser connection terminal  
A/D R – Y input terminal  
A/D bias condenser connection terminal  
A/D B– Y input terminal  
A/D digital power supply  
A/D digital GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
I
I
I
Digital GND  
Digital power supply  
VDD  
FVS  
FHS  
NFHS  
I
I
I
Sub screen vertical sync signal input  
Sub screen horizontal sync signal input  
Sub screen horizontal sync signal reversing input  
Digital power supply  
Oscillator connection terminal sub input  
Oscillator connection terminal sub output  
Digital GND  
VDD  
OSCSI  
OSCSO  
VSS  
VDD  
CKW  
I
O
Digital power supply  
O
O
O
O
O
O
O
O
O
O
O
O
Serial write clock output terminal  
Input enable output terminal  
Write enable output terminal  
Reset write output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Digital GND  
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
IE  
WE  
RSTW  
MWD15  
MWD14  
MWD13  
MWD12  
MWD11  
MWD10  
MWD9  
MWD8  
VSS  
MWD7  
MWD6  
MWD5  
MWD4  
MWD3  
MWD2  
MWD1  
MWD0  
VDD  
O
O
O
O
O
O
O
O
Data output terminal  
Data output terminal  
Data output terminal  
Data output terminal  
Digital power supply  
Data input terminal  
MRD0  
I
54  
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Table 6-2 QY03 TC9092AF pin list (No. 2)  
No.  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
Pin name  
MRD1  
MRD2  
MRD3  
MRD4  
MRD5  
MRD6  
MRD7  
MRD8  
MRD9  
MRD10  
MRD11  
MRD12  
MRD13  
MRD14  
MRD15  
RE  
RSTR  
CKR  
CKRI  
YSOUT  
VSS  
OSCMI  
OSCMO  
VDD  
FHM  
NFHM  
FVM  
VSS  
SCL  
SDA  
SDAINO  
VSS  
PROMDI  
PROMCK  
PROMRES  
ME  
RESET  
TEST1  
TESTAD  
VDD  
I/O  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Pin function  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
Data input terminal  
O
O
O
I
Read enable output terminal  
Read reset output terminal  
Serial read clock output terminal  
Memory read clock input  
Ys signal output terminal  
Digital GND  
Oscillator connection terminal main input  
Oscillator connection terminal main output  
Digital power supply  
Main screen horizontal sync signal input  
Main screen horizontal sync signal reversing input  
Main screen vertical sync signal input  
Digital GND  
O
I
O
I
I
I
I
I2C CK input terminal  
I2C data I/O terminal  
BID  
O
I2C data direction output terminal, Test output terminal  
Digital GND  
ROM data input terminal  
ROM clock output terminal  
ROM RESET output terminal  
MEMORY polarity control input terminal  
RESET input terminal  
I
O
O
I
I
I
TEST input terminal  
AD/DA TEST input terminal  
Digital power supply  
I
NC  
DAVREFY  
DABIAS1  
DAVDD  
YOUT  
DAVSS  
RYOUT  
DAVREFC  
DAVDD  
BYOUT  
I
D/A Y reference voltage input terminal (4V)  
D/A bias condenser connection terminal  
D/A power supply  
O
D/A Y output terminal  
D/A GND  
O
I
D/A R – Y output terminal  
D/A C reference voltage input terminal (3V)  
D/A power supply  
O
D/A B – Y output terminal  
55  
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Dout (X8)  
OE  
RE  
RSTR SRCK  
Controller  
Data - out  
buffer (X8)  
Serial Read  
512 Word serial read register (X8)  
Read line buffer  
Low-Half (X8)  
Read line buffer  
High-Half (X8)  
256 (X8)  
256 (X8)  
71 Word  
Sub-register (X8)  
256K (X8)  
X
Read/Write  
and refresh  
controller  
Memory  
Array  
De-  
coder  
71Word  
Sub-register (X8)  
Clock  
256 (X8)  
256 (X8)  
oscillator  
Write line buffer  
Low-Half (X8)  
Write line buffer  
High-Half (X8)  
512 Word serial write register (X8)  
VB3  
Generator  
Data - in  
Serial Write  
Controller  
Buffer (X8)  
Din (X8)  
IE  
WE  
RSTW SWCK  
Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagram  
WE  
Din0  
1
3
5
7
Terminal name  
Function  
IE  
2
4
6
SWCK  
SRCK  
WE  
Serial write clock  
Serial read clock  
Write enable  
Read enable  
Din1  
Din3  
Din4  
Din6  
RSTW  
NC  
Din2  
Vcc  
RE  
8
Din5  
9
IE  
Input enable  
Output enable  
Reset write  
10  
12  
14  
Din7  
11  
OE  
SWCK  
NC  
RSTW  
RSTR  
Din 0 – 7  
Dout 0 – 7  
13  
15  
Reset read  
RE  
16  
Data input  
OE  
17  
19  
21  
23  
Dout7  
Dout5  
Vss  
Data output  
18  
20  
22  
24  
26  
28  
Dout6  
Dout4  
Dout3  
Dout1  
RSTR  
V
V
Power supply (+5V)  
Ground (0V)  
Not connected  
CC  
SS  
NC  
Dout2  
Dout0  
SRCK  
25  
27  
28PIN ZIP  
Fig. 6-10 QY10/QY11 M518221-30ZS pin layout  
56  
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SECTION VII: 3-DIMENSION Y/C SEPARATOR CIRCUIT  
1. OUTLINE  
The 3DYC separation circuit uses a comb filter with a frame  
memory and ideally separates the Y (luminance) and color  
signal for still parts of a picture, thus providing a clean pic-  
ture without:  
2-2. Circuit Description  
Fig. 7-1 shows a block diagram of the YCS circuit.  
(1) A video signal sent through the AV switching circuit  
passes the input terminal (DG) and enters theYCS unit.  
(1) Dot interference causing at border areas of color pic-  
tures.  
(2) The video signal entered is limited in its band width in  
passing through an aliasing distortion elimination LPF  
consisting of LZ22, etc. , and then enters pin 56 of  
QZ01.  
(2) Excess color in vertical direction.  
However in a moving picture, as the picture moves between  
the first and second frames, good separation is not obtained.  
(3) At the same time, a fsc (3.58 MHz) signal being oscil-  
lated in the video signal color IC (Q501, AN1222AN)  
is fed to pin 28 of QZ01 and converted into a 4fsc  
(14.32 MHz), a drive clock frequency inside the IC.  
To prevent this, a motion detection is carried out in the 3D  
YC separation (hereafter calledYCS) unit (PB6347). When  
a picture moving is detected a 2D YC separation using a  
line memory is switched in and when not detected or for a  
still picture 3D YC separation is switched in, thereby cor-  
recting defects both the systems have and performing the  
ideal YC separation. The motion detection accuracy and  
smoothness of the switching, etc. are controlled through the  
IIC bus.  
(4) The video signal entered pin 56 of QZ01 is processed  
inside the IC and a luminance (Y) signal is developed  
at pin 48 of QZ01 and the color signal at the pin 51.  
(5) The Y signal developed at pin 48 of QZ01 passes a  
LPF (LZ20, etc.) which eliminates the clock signal  
component, amplified by a 6dB amplifier QZ21, etc.  
and comes out from the DC terminal as the Y signal.  
After completion of theY and S signal separation, a vertical  
contour correction is carried out for the Y signal.  
(6) At the same time, the color signal developed at pin 51  
of QZ01 passes a LPF (LZ21, etc.) which eliminates  
the clock component, amplified by 6dB by QZ23, etc.  
and comes out from DD terminal through a buffer of  
QZ24 as the C signal.  
2. CIRCUIT DESCRIPTION  
2-1. Configuration  
The YCS unit consists of a YC separation IC (QZ01,  
TC9086F) which plays major roles, 2 Mbyte field memory  
(QZ02, QZ03), clock generation IC (QZ04, TA8667F), and  
peripheral circuits (LPF, AMP,emitter followers, etc.).  
(7) QZ04 is generating a clock signal used to read and  
write the digital data between QZ03 and QZ04 based  
on the video signal.  
(QZ16 emitter: 28.6 MHz ± 0.2 MHz, adjusted by  
LZ25.)  
Of the above circuit blocks, QZ01 (TC9086F) includes an  
A/D converter, D/A converter, clamp circuit, 4fsc PLL cir-  
cuit, 1 line dot countermeasure circuit, vertical contour cor-  
rection logic circuit, etc. and provides a high separation with  
less variations.  
57  
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• Terminal description (PZ01)  
No.  
DH  
DC  
DE  
DD  
DB  
DG  
DA  
DF  
DI  
Signal name  
Voltage  
Comb through  
Y-Comb  
9V  
Comb through pulse for ED2 ID signal period (V frequency), 5V  
2V(p-p)  
+9V ± 0.5V  
0.6V(p-p) at burst  
GND  
C-Comb  
GND  
V-AV  
2V(p-p)  
5V  
+5V ± 0.5V  
0.4V(p-p), 3.58 MHz  
IIC bus data, 5V  
IIC bus clock, 5V  
fsc  
SDA1  
SCL1  
DJ  
PZ01  
QZ01 TC9090N  
36 KILL  
DH  
DC  
YOUT  
AMP  
LPF  
48  
QZ22  
QZ24  
QZ06  
QZ21  
LZ20 etc  
DE  
DD  
DB  
DG  
DA  
COUT  
AMP  
LPF  
51  
QZ23  
LZ21 etc  
56 CVIN  
LPF  
QZ07  
QZ05  
LZ23 etc  
8
FS2N  
28 FSC  
20 DATA  
 19 SLK  
DF  
DI  
DJ  
QZ04   TA8667F  
64 100  
QZ02  
QZ03  
QZ16  
QZ14  
LZ25  
28.6MHz  
Fig. 7-1 3-dimension Y/C separator unit block diagram  
58  
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SECTION VIII: VERTICAL OUTPUT CIRCUIT  
1. OUTLINE  
Q301 (LA7833S) contains the pump up circuit and the output  
circuit. V screen position switching function which lowers  
the V raster position by flowing an opposite DC current into  
the deflection yoke. This circuit is used selecting SUBTITLE  
and CINEMA MODE.  
The sync separation circuit, V pulse circuit, and blanking  
circuit are provided inside Q501 (TA1222AN). The saw tooth  
wave generation circuit and amplifier (V driver circuit) are  
provided inside Q302 (TA8859AP).  
Q302 TA8859AP  
Q301 LA7833S  
WAC  
SAWTOOTH  
WAVE  
PUMP UP  
CIRCUIT  
PULSE DELAY  
GENERATOR  
DEFLECTION  
AMP  
OUTPUT  
YOKE  
( I2C BUS)  
FEEDBACK  
MICROPROCESSOR  
CONTROL CIRCUIT  
( I2C BUS)  
Q501 TA1222AN  
V-RASTER SHIFT  
CIRCUIT  
V/C/D LSI  
SYNC SEP.V PULSE/  
BLANKING  
AUTO LIVE  
MICROPROCESSOR  
V-BLK  
Fig. 8-1  
1-1. Theory of Operation  
This voltage is applied to (+) input (non-inverted input) of  
an differential amplifier, A. As the amplification factor of A  
is sufficiently high, a deflection current flows so that the  
voltage V2 at point c becomes equal to the voltage at point  
The purpose of the V output circuit is to provide a sawtooth  
wave signal with good linearity inV period to the deflection  
yoke.  
When a switch S is opened, an electric charge charged up to  
a reference voltageVP discharges in an constant current rate,  
and a reference sawtooth voltage generates at point a .  
a .  
S: Switch  
Vp  
Differential  
amplifier  
L
A
a
C2  
R3  
c
V2  
R1      C2     R2  
V1  
Fig. 8-2  
59  
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2. V OUTPUT CIRCUIT  
2-1. Actual Circuit  
D309  
C322  
+9V  
R308       C308  
D308  
+35V  
D301  
C313  
15  
14  
13  
3
6
8
R329  
C321  
6
7
1
R303  
3
Q301  
4
L301             R336  
C307  
Q302  
Q501  
31  
2
5
R307  
L462+L463+L464  
R320  
R301  
R306  
R313  
C309  
C311  
C314  
C306  
R330  
C305  
R304  
R305  
C319  
Fig. 8-3  
2-2. Sawtooth Waveform Generation  
2-2-1. Circuit Operation  
The pulse generation circuit also works to fix the V ramp  
voltage at a reference voltage when the trigger pulse enters,  
so it can prevent the sawtooth wave start voltage from  
variations by horizontal components, thus improving  
interlacing characteristics.  
The sawtooth waveform generation circuit consists of as  
shown in Fig. 8-4. When a trigger pulse enters pin 13, it is  
differentiated in the waveform shape circuit and only the  
falling part is detected by the trigger detection circuit, to the  
waveform generation circuit is not susceptible to variations  
of input pulse width.  
WAVEFORM  
SHAPE  
TRIGGER  
DET.  
PULSE  
GAIN  
13  
AGC  
16  
V. LAMP  
15  
5Vp  
DC=0V  
14  
C321  
C322  
C323  
R329  
+
+9V  
Fig. 8-4  
60  
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2-3. V Output  
2-3-1. Circuit Operation  
Q3 turns on for first half of the scanning period and  
allows a positive current to flow into the deflection  
yoke (Q3 ® DY ® C306 ® R305 ® GND), and Q4  
turns on for last half of the scanning period and allows  
a negative current to flow into the deflection yoke  
(R305 ® C306 ® DY ® Q4). These operations are  
shown in Fig. 8-5.  
The V output circuit consists of a V driver circuit Q302,  
Pump-up circuit and output circuit Q301, and external circuit  
components.  
(1) Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4  
output stage connected in a SEPP amplifies the cur-  
rent and supplies a sawtooth waveform current to a  
deflection yoke.  
+35V  
D301                      C308  
D308  
63V  
V 3  
35V  
Q301  
6
3
GND  
D309    R308  
V 7  
V 2  
Q3  
35V  
7
2
GND  
63V  
BIAS  
CIRCUIT  
Q2  
Q4  
4
DY  
+
C306  
GND  
GND  
Q3 ON  
Q4 ON  
R305  
1
Fig. 8-5  
(2) In Fig. 8-6 (a), the power Vcc is expressed as a fixed  
level, and the positive and negative current flowing  
into the deflection yoke is a current (d) = current (b) +  
(c) in Fig. 8-6, and the emitter voltage of Q3 and Q4 is  
expressed as (e).  
(3) Q3 collector loss is i1 x Vce1 and the value is equal to  
multiplication of Fig. 8-6 (b) and slanted section of  
Fig. 8-6 (e), and Q4 collector loss is equal to multipli-  
cation of Fig. 8-6 (c) and dotted section of Fig. 8-6  
(e).  
Power Vcc  
GND   (b) Q3 Collector current i1  
GND   (c) Q4 Collector current i2  
Q3  
i1  
Vce 1  
Q4  
GND   (d) Deflection yoke current i1+i2  
Q2  
i2  
Vp  
Vcc  
1/2 Vcc  
GND  
(e)  
(a) Basic circuit  
Fig. 8-6  
61  
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(4) To decrease the collector loss of Q3, the power supply  
voltage is decreased during scanning period as shown  
in Fig. 8-7, and VCE1 decreases and the collector loss  
of Q3 also decreases.  
(6) Since pin 7 of a transistor switch inside Q301 is con-  
nected to the ground for the scanning period, the power  
supply (pin 3) of the output stage shows a voltage of  
(VCC – VF), and C308 is charged up to a voltage of  
(VCC – VF – VR) for this period.  
Q3 Collector loss decreases  
by amount of this area  
(7) First half of flyback period  
Current flows into L462 + L465 + L464 ® D1 ® C308  
® D308 ® VCC (+35V) ® GND ® R305 ® C306  
® L462 + L463 + L464 in this order, and the voltage  
across these is:  
Power supply  
for flyback period (Vp)  
Power supply  
for scanning period  
(Vcc)  
VP = VCC + VF + (VCC – VF – VR) + VF about 63V  
is applied to pin 3. In this case, D301 is cut off.  
Scanning period  
(8) Last half of flyback period  
Current flows into VCC ® switch ® D309 ® C308  
® Q301 (pin 3) ® Q3 ® L462 +L463 +L464 ®  
C306 ® R305 in this order, and a voltage of  
Flyback period  
Fig. 8-7 Output stage power supply voltage  
VP = VCC – VCE (sat) – VF + (VCC – VF – VR) –  
VCE (sat), about 56V is applied to pin 3.  
(9) In this way, a power supply voltage of about 35V is  
applied to the output stage for the scanning period and  
about 63V for flyback period.  
(5) In this way, the circuit which switches power supply  
circuit during scanning period and flyback period is  
called a pump-up circuit. The purpose of the pump-up  
circuit is to return the deflection yoke current rapidly  
for a short period (within the flyback period) by ap-  
plying a high voltage for the flyback period. The basic  
operation is shown in Fig. 8-8.  
D301                           C308  
D308  
D301                           C308  
D308  
Q301  
Q301  
6
3
6
3
D309  
R308  
D309  
R308  
VR  
Switch  
Switch  
7
7
Q3  
Q3  
D1  
D1  
First half  
L462+L463+L464  
L462+L463+L464  
2
2
+
+
Q4  
Q4  
C306  
C306  
R305  
R305  
Last half  
(a) Scanning period                                                                                              (b) Flyback period  
Fig. 8-8  
62  
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2-4. V Linearity Characteristic Correction  
2-4-1. S-character Correction  
2-4-2. Up-and Down-ward Linearity Balance  
(Up-and Down-ward Extension Correction)  
A voltage developed at pin 2 of Q301 is divided with resistors  
R307 and R303, and the voltage is applied to pin 6 of Q301  
to improve the linearity balance characteristic.  
A parabola component developed across C306 is integrated  
by R306 and C305, and the voltage is applied to pin 6 of  
Q302 to perform S-character correction.  
3. PROTECTION CIRCUIT FOR V DEFLECTION STOP  
Q301  
2
R352  
Q351  
12V 9V  
D350  
R351  
L462+L463+L464  
R354  
BLANKING  
CIRCUIT  
C306  
Q350  
C350  
D354  
Q353  
R350  
R305  
D353  
Fig. 8-9  
When the deflection current is not supplied to the deflection  
coils, one horizontal line appears on the screen. If this  
condition is not continued for a long time, no trouble will  
occur in a conventional TV. But in the projection TV, all the  
electron beams are directly concentrated at the fluorescent  
screen because of no shadow mask used, and burns out the  
screen instantly.  
Next, when theV deflection stops, the voltage across (R305)  
does not develop, so Q350 turns off, and both the Q351 and  
Q353 are turned off. Then, the picture blanking terminal  
pin 13 of ICA05 is set to high through R354 and D354  
connected to 90V power line, BLANKING CIRCUIT ON  
thus cutting off the projection tubes.  
To prevent this, the stop of theV deflection is detected when  
the horizontal one line occurs, and the video signals are  
blanked out so that the electron beams are not emitted.  
Volttage Across  
R305  
When the V deflection circuit is operating normally, a  
sawtooth wave voltage is obtained across (R305), so Q350  
repeats on-off operation in cycle of V sync. In this case, the  
collector voltage of Q35 is set to develop less than (12V-  
VBE (Q351)) with R352 and C350 as shown in Fig. 8-9.  
Accordingly, Q351 and Q353 are continuously turned on.  
As a result, diode D354 is turned off, giving no influence on  
the blanking operation.  
Q340 VBE  
Q350 BASE  
12V-VBE (Q341)  
Q351 Collector  
Fig. 8-10  
63  
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3-1. +35V Over Current Protection Circuit  
The over current protection circuit cuts off the power supply  
relay when it detects abnormal current increased in the +35V  
power line due to failure of the vertical deflection circuit.  
When the voltage increases across R370. and the voltage  
developed across R371 becomes higher than the Vbs of  
Q370, Q370 turns on and a voltage develops across R374  
due to the collector current flowing. When this voltage  
increases to a value higher than about 7V, Z801 operates,  
thus cutting off the power relay. When the circuit operates, a  
power LED provided will turn on and off in red.  
3-1-1. Theory of Operation  
Fig. 8-11 shows the circuit diagram of the over current  
protection circuit. When the load current of the +35V line  
increases, the voltage across a resistor of T370 will also  
increase.  
C303  
R370  
R327  
FBT  
+35V  
pin 6  
D302  
C310  
R372  
R371  
C370  
D421  
UZ22BSD  
Q370  
2SA933SQ  
D370  
UZ11BSB  
R373  
To pin 14 (GATE)  
of Z801  
R375  
C371  
R374  
Fig. 8-11  
64  
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4. RASTER POSITION SWITCHING CIRCUIT  
4-1. Outline  
So, adjust the center of the picture to the center of the screen  
When the vertical screen position adjustment is carried out  
on the projection TV, DC current is directly flown in the  
vertical deflection yoke and the raster cannot be moved up  
and down. (Because the raster is moved, the color distortion  
may occur.) Accordingly, the vertical screen position  
adjustment is carried out by the following method. (Only in  
CINEMA and SUBTITLE mode)  
in advance under the output V sync delayed.  
To do this, lower the raster position by flowing a DC current  
to the deflection yoke in the CINEMA and SUBTITLE  
mode.  
The operation above is carried out by the vertical screen  
position SW circuit.  
V sync pulse output from Q501 sync. separation circuit is  
once input to WAC, delayed and then output. The deflection  
circuit operates with the delayed sync signal. The screen  
upper side position moves up and down by varying the delay  
time. When the vertical position adjustment is carried out  
by WAC, the followings must be considered.  
4-2. Operation  
When CINEMA and SUBTITLE are selected in the screen  
mode, a zoom signal is input to the base of Q362 from the  
autolive circuit and Q362 turns on. Then, Q363 turns off  
and the base of Q364 develops H and Q364 turns on. The  
inverted DC current flows into the vertical deflection yoke  
from +35V power supply line.V power supply line and then  
the raster moves down.  
WAC becomes “through” except for CINEMA and  
SUBTITLE mode.  
The phase of the output V sync must not advance from that  
of WAC inputV sync. If it advances,Vertical jitter may occur  
when performing the search operation and the vertical  
position adjustment of a VTR.  
R364  
KETSU  
R363  
2R  
R365  
1R5.6K  
R362  
1R5.6K  
220  
R366  
33K  
R360  
33K  
Fig. 8-12  
Q364  
2SC2023  
R361  
12K  
R367  
12K  
Q366  
RN1204  
Q362  
RN1204  
Q367  
2SC2023  
Q363  
2SC1815Y  
Q365  
2SC1815Y  
D361  
S5965G  
+35V  
+12V  
P360  
Fig. 8-13  
Screen  
mask  
position  
Screen  
mask  
position  
Raster position  
Nomal mode (4:3, Full, Dramatic Wide)  
Mode in which the opposite current  
flows into D  (Cinema)  
Y
65  
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SECTION IX: HORIZONTAL DEFLECTION CIRCUIT  
2-1. Theory of Operation  
1. OUTLINE  
(1) When the power switch is on, the main power supply  
of 125V starts to rise. At the same time, AF power sup-  
ply 38V also rises.  
The H deflection circuit works to deflect a beam from left to  
right by flowing a sawtooth waveform of 15.625 kHz/15.735  
kHz into the DY H deflection coil.  
(2) With 38V line risen, Q430 base voltage which is cre-  
ated by dividing the audio power with R433 and D430  
also rises. Then, the transistor Q430 turns on and the  
H VCC is applied from the audio power line through  
R432 and D431 to pin 22 of Q501.  
2. HORIZONTAL DRIVE CIRCUIT  
The H drive circuit works to start the H output circuit by  
applying H VCC (Q501 DEF power source) to pin 22 of  
Q501 (TA1222N) and a bias to the H drive transistor Q402  
at the main power on.  
R432           Q430    D431  
35V  
Q501  
R433  
D430  
BB81  
H Vcc  
22  
81  
81  
L400  
BB80  
SIGNAL  
C431      C430    
Fig. 9-1 H drive circuit block diagram  
3. BASIC OPERATION OF HORIZONTAL DRIVE  
A sufficient current must flow into base of the horizontal  
output transistor to rapidly make it into a saturated (ON)  
condition or a cut off (OFF) condition. For this purpose, a  
drive amplifier is provided between the oscillator circuit and  
the output circuit to amplify and to waveshape the pulse volt-  
age.  
(2) To turn on the output transistor completely and to make  
the internal impedance low, a sufficiently high, for-  
ward drive voltage must be applied to the base and  
heavy base current ib must be flown. On the contrary,  
to completely turn off the transistor, a sufficiently high,  
reverse voltage must be applied to the base.  
(3) When the transistor is on (collector current is maxi-  
mum) condition with the sufficiently high forward volt-  
age applied to the base, the transistor can not be turned  
off immediately, if a reverse base bias is applied to the  
base because minority carriers storaged in the base can  
not be reduced to zero instantly. That is, a reverse cur-  
rent flows through an external circuit and gradually  
reduces to zero. The time lag required for the base cur-  
rent to disappear is called a storage time and falling  
time.  
3-1. Theory of Operation  
(1) The horizontal drive circuit works as a so called switch-  
ing circuit which applies a pulse voltage to the output  
transistor base and makes the transistor on when the  
voltage swings in forward direction and off in reverse  
direction.  
66  
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(4) To shorten the storage time and the falling time, a suf-  
ficiently high reverse bias voltage must be applied to  
allow a heavy reverse current to flow. This operation  
also stabilizes operation of the horizontal output tran-  
sistor.  
On period         OFF period  
+
0
t   Input waveform (b)  
-
+
Forward  
current  
ib  
t   Base current (c)  
0
Reverse  
current  
V
-
Falling  
time  
(a)  
Storage  
time  
Fig. 9-2  
3-2. Circuit Description  
(2) On the contrary, when Q1 inside IC501 is off (pin 8 is  
0V), base-emitter bias of Q402 becomes 0V and Q402  
turns off, and a collector pulse as shown in Fig. 9-3  
develops at the collector.  
In the N5SS chassis, the off drive system is employed.  
(1) When Q1 inside Q501 is turned on, Q402 base is for-  
ward biased through 9V ® pin 22 of Q501 (H. VCC)  
® pin 23 of Q501 (H. Out) ® R411/R410 resistor di-  
vider, and then, Q402 collector current flows through  
125V ® R416 ® T401. In this case, the H output tran-  
sistor Q404 turns on with the base-emitter reverse bi-  
ased because of the off drive system employed.  
The voltage is stepped down and Q404 is forward bi-  
ased with this voltage, thus turning on Q404.  
(3) In this way, by stepping down the voltage developed at  
primary winding of the drive transformer and by ap-  
plying it to Q404, a sufficient base current flows into  
Q404 base, thereby switching the Q404.  
Q501  
H. Vcc  
22  
T401  
H drive  
transistor  
C417  
1
3
C431  
R415  
C413  
Q1  
Q404  
H output  
transistor  
R411  
23  
2
4
R410  
Q402  
H drive  
transistor  
V1  
+
V2  
R416  
0V  
0V  
C416  
+125V  
9V  
VCP  
Fig. 9-3  
Q402  
ON  
Q402  
OFF  
67  
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HV  
4. HORIZONTAL OUTPUT CIRCUIT  
10  
The horizontal output circuit applies a 15.625 kHz/15.734  
kHz sawtooth wave current to the deflection coil with mu-  
tual action of the horizontal output transistor and the damper  
diode, and deflects the electron beam from left to right in  
horizontal direction.  
5
2
T461  
FBT  
S-charactor  
capacitor  
3
1
Q404  
H output  
Deflection yoke  
(H coil)  
8
(With damper diode)  
T401  
IC501  
H. out  
L464  
L463  
L462  
C440  
H drive  
transformer  
C343  
D444  
R415  
C444  
C418  
TP-33  
Q402  
H drive  
D461  
R441  
C423  
BB81  
83  
H
C463  
Q1  
23  
linearity  
coil  
R411  
R410  
C417  
C467  
L441  
D443  
L461  
C413  
C416  
To High Voltage  
Regulator Circuit  
+
C464  
R416  
+
Resonat  
capacitor  
To DPC output  
SIGNAL                              DEF/POWER PCB  
125V  
Diode modulator circuit  
Fig. 9-4  
4-1. Theory of Operation  
(a)    H output basic circuit  
4-1-1. Operation of Basic Circuit  
(1) To perform the horizontal scanning, a 15.625 kHz/  
15.735 kHz sawtooth wave current must be flown into  
the horizontal deflection coil. Theoretically speaking,  
this operation can be made with the circuit shown in  
Fig. 9-5 (a) and (b).  
H output  
transistor  
L
D
Co  
Deflection  
yoke  
Damper  
diode  
Resonant  
capacitor  
(2) As the switching operation of the circuit can be re-  
placed with switching operation of a transistor and a  
diode, the basic circuit of the horizontal output can be  
expressed by the circuit shown in Fig. 9-5 (a). That is,  
the transistor can be turned on or off by applying a  
pulse across the base emitter.A forward switching cur-  
rent flows for on-period, and a reverse switching cur-  
rent flows through the diode for off-period. This switch-  
ing is automatically carried out. The diode used for  
this purpose is called a damper diode.  
Vcc  
(b)    H output equivalent circuit  
SW2  
SW1  
Co  
L
Vcc  
Fig. 9-5  
68  
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Description of the basic circuit  
1. t1~t2:  
6. t4~t6:  
A positive pulse is applied to base of the output transistor  
from the drive circuit, and a forward base current is flowing.  
The output transistor is turned on in sufficient saturation area.  
As a result, the collector voltage is almost equal to the ground  
voltage and the deflection current increases from zero to a  
value in proportionally. (The current reaches maximum at  
t2, and a right half of picture is scanned up to this period.)  
For this period. C0 is charged with the deflection current  
having opposite polarity to that of the deflection current  
stated in "3.", and when the resonant capacitor voltage ex-  
ceeds VCC, the damper diode D conducts. The deflection  
current decreases along to an exponential function (approxi-  
mately linear) curve and reaches zero at t6. Here, operation  
returns to the state described under "1.", and the one period  
of the horizontal scanning completes. For this period a left  
half of the screen is scanned.  
2. t2:  
The base drive voltage rapidly changes to negative at t2 and  
the base current becomes zero. The output transistor turns  
off, collector current reduces to zero, and the deflection cur-  
rent stops to increase.  
In this way, in the horizontal deflection scanning, a current  
flowing through the damper diode scans the left half of the  
screen; the current developed by the horizontal output tran-  
sistor scans the right half of the screen; and for the flyback  
period, both the damper diode and the output transistor are  
cut off and the oscillation current of the circuit is used. Us-  
ing the oscillation current improves efficiency of the circuit.  
That is, about a half of deflection current (one fourth in terms  
of power) is sufficient for the horizontal output transistor.  
3. t2~t3:  
The drive voltage turns off at t2, but the deflection current  
can not reduce to zero immediately because of inherent na-  
ture of the coil and continues to flow, gradually decreasing  
by charging the resonant capacitor C0. At the same time, the  
capacitor voltage or the collector voltage is gradually in-  
creases, and reaches maximum voltage when the deflection  
current reaches zero at t3. Under this condition, all electro-  
magnetic energy in the deflection coil at t2 is transferred to  
the resonant capacitor in a form of electrostatic energy.  
t1           t2  t3 t4 t5      t6  
TR  
0
0
A
base voltage  
4. t3~t4:  
TR  
B
C
base current  
Since the charged energy in the resonant capacitor discharges  
through the deflection coil, the deflection current increases  
in reverse direction, and voltage at the capacitor gradually  
reduces. That is, the electrostatic energy in the resonant ca-  
pacitor is converted into a electromagnetic energy in this  
process.  
TR  
collector  
current  
0
0
D
D
E
damper  
current (SW2)  
5. t4:  
Switch  
current  
(TR, SW1)  
0
0
When the discharge is completed, the voltage reduces to zero,  
and the deflection current reaches maximum value in re-  
verse direction. The t2~t4 is the horizontal flyback period,  
and the electron beam is returned from right end to the left  
end on the screen by the deflection current stated above.  
The operation for this period is equivalent to a half cycle of  
the resonant phenomenon with L and C0, and the flyback  
period is determined by L and C0.  
F
Resonant  
capacitor  
current (Co)  
G
Deflection  
current (Lo)  
0
TR  
H
collector  
voltage  
0
Fig. 9-6  
69  
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Amplitude Correction  
t2  
θ2  
t1  
t2  
θ2  
t1  
To vary horizontal amplitude, it is necessary to vary a  
sawtooth wave current flowing into the deflection coil. These  
are two methods to vary the current; a method which varies  
t2 = t1  
t2 > t1  
θ1  
θ1  
<
=
θ2 θ1  
θ2 θ1  
L by connecting a variable inductance L in series with the  
H
deflection yoke, and a method which varies power supply  
voltage (across S-character capacitor) for the deflection yoke.  
As the DPC circuits is used in the this chassis, the later  
method which varies the deflection yoke power supply volt-  
age by modifying the bus data is used.  
(a) S-character correction                    (b)  
Fig. 9-7  
4-1-2. Linearity Correction (LIN)  
(1) S-curve Correction (S Capacitor)  
Pictures are expanded at left and right ends of the screen  
even if a sawtooth current with good linearity flows in  
the deflection coil when deflection angle of a picture  
tube increases. This is because projected image sizes  
on the screen are different at screen center area and  
the circumference area as shown in Fig. 9-7. To sup-  
press this expansion at the screen circumference, it is  
Cs  
TR  
D       Co  
LH  
Deflection coil  
necessary to set the deflection angle q to a large value  
1
Vcc  
(rapidly deflecting the electron beam) at the screen  
(a) H output circuit  
center area, and to set the deflection angle q to a small  
2
value (scanning the electron beam slowly) at the cir-  
cumference area as shown in Fig. 9-7.  
In the horizontal output circuit shown in Fig. 9-8, ca-  
pacitor C connected in series with the deflection coil  
S
L
is to block DC current. By properly selecting the  
H
(b) Sawtooth wave current  
value of C and by generating a parabolic voltage de-  
S
veloped by integrating the deflection coild current  
across the S capacitor, and by varying the deflection  
yoke voltage with the voltage, the scanning speed is  
decreased at beginning and end of the scanning, and  
increased at center area of the screen. The S curve cor-  
rection is carried out in this way, thereby obtaining  
pictures with good linearity.  
(c) Voltage across LH  
     Fast deflection  
Slow deflection  
(d) Synthesized current  
Fig. 9-8  
70  
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(2) Left-right Asymmetrical Correction (LIN coil)  
When a horizontal linearity coil L with a current char-  
1
acteristic as shown in Fig. 9-9 (c) is used, left side pic-  
ture will be compressed and right side picture will be  
expanded because the inductance is high at the left side  
on the screen and low at the right side. The left-right  
asymmetrical correction is carried out in this way, and  
pictures with good linearity in total are obtained.  
In the circuit shown in Fig. 9-9 (a), the deflection coil  
current iH does not flow straight as shown by a dotted  
line in the Fig. 9-9 (b) if the linearity coil does not  
exist, by flows as shown by the solid line because of  
effect of the diode for a first scanning (screen left side)  
and effect of resistance of the deflection coil for later  
half period of scanning (screen right side). That is, the  
deflection current becomes a sawtooth current with bad  
linearity, resulting in reproducing of asymmetrical pic-  
tures at left and right sides of the screen (left side ex-  
panded, right side compressed).  
(a)  
LH  
TR  
D       Co  
(a)  
LI  
L
C
Cs  
FBT  
TR  
LH  
D          Co  
Deflection  
coil  
iH  
Li  
Vcc  
Cs  
S-character  
capacitor  
(b)  Sawtooth wave current  
(b)  Deflection coil current  
                         Deflection coil current  
(iH)  
Fig. 9-10  
Resistance of LH  
Characteristic of D  
(Left)                     (Right)  
0
(c)  Linearity coil characteristic  
              Linearity coil characteristic  
Inductance  
(µH)  
(Left)                     (Right)  
Current (A)  
Fig. 9-9 Linearity coil  
71  
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4-2. White Peak Bending Correction Circuit  
4-2-1. Outline  
4-2-2. Operation Theory  
White peak area in screen picture may sometimes cause bend-  
ing in picture. See figure below.  
Fig. 9-11 shows circuit diagram. Video ripple in video out-  
put circuit power supply 200V suffers DC cut by C475, and  
is inverted in Q470, then input to pin 24 of Q501 via C481.  
Pin 24 of Q501 is a bending correction terminal. The volt-  
age which is applied to this terminal, controls phase of video  
signal to correct white peak bending.  
In TP48E60 series, correction signal which video ripple in  
video output circuit power supply 200V is input to pin 24  
(Bending correction terminal) of Q501. This corrects white  
peak bending.  
Q501  
R379  
24  
EHT  
Bending correction  
terminal  
C415  
BB91  
93  
Receiving Board  
Power, Def board  
9V  
200V  
R481  
R483  
D406  
C466  
C481 Inversion  
Q470  
R478  
T416  
3
C475  
D470  
D474  
R484  
R482  
White peak  
Bending by white peak  
Fig. 9-11 White peak bending correction circuit  
72  
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4-3. H Blanking  
4-3-2. Theory of Operation  
The H blanking circuit determines the flyback period pre-  
cisely from the AFC pulse in the FBT and applies the period  
to emitter of the video output stage transistor on the CRT-D  
PC board.  
4-3-1. Outline  
The H blanking circuit applies a blanking precisely for the  
horizontal flyback period so that undesirable pictures fold-  
ing does not appear at screen ends.  
This unit allows the users to adjust an horizontal amplitude  
adjustment, so, picture quality at screen ends will be im-  
proved. This is one of the purposes of the blanking circuit.  
4-3-3. Circuit Operation  
As can be seen from Fig. 9-12, the flyback period of the  
AFC pulse in the FBT starts at a negative side from 0V. To  
detects this, the DC component is cut with C493. This is,  
C493 is always charged through D487 with a negative side  
(about –17V) of theAFC pulse. As a result, a voltage at point  
A in the waveform rises from the ground level. This wave-  
form is sliced in a circuit (R486, D486) to detect the flyback  
period. Thus obtained voltage is applied to Q901, Q911, and  
Q921 through D904, D914, D927 and cuts off them thereby  
blanking the resters.  
Q487  
ON period  
Q921  
D486  
Slice level  
D927  
BLUE  
0V  
CRT/D  
Approx.  
10  
-17V  
Waveform at  
point  
AFC Pulse  
10  
Q911  
Fig. 9-12  
D914  
GREEN  
CRT/D  
10  
+35V  
10  
Q901  
D904  
R906  
P904  
Point  
A
RED  
CRT/D  
T461 (FBT)  
Q487  
R417  
AFC  
C493  
6
7
CRT-D DCB  
10  
R486  
L410  
Deflection/Power PCB  
P903  
D486  
Q489  
R409  
D487  
Q488  
R438  
V blanking  
Fig. 9-13  
73  
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4-4. 200V Low Voltage Protection  
4-4-2. Theory of Operation  
Fig. 9-14 shows a connection diagram.  
4-4-1. Outline  
Under a normal condition Q340 is always on because of about  
210V supplied from the 200V line. Accordingly Q340 col-  
lector is kept at about 6.2V or the zener voltage of D341 and  
Q341 is turned off.  
When the video output power supply 200V is stopped by  
some abnormality occurence, the current inside CPT in-  
creases abnormally. So the CPT may be damaged. To pre-  
vents this, a 200V low voltage protection circuit is provided.  
If some abnormality occurs and 200V line voltage lowers  
by less than about 160V. Q340 turns off and its collector  
voltage rises. So Q341 turns on. With Q341 turned on the  
voltage at pin 14 of Z801 (expander) exceeds a threshold  
voltage and pin 16 of Z80 is high level and makes the power  
relay turn off.  
DPC circuit  
R389  
Deflection circuit  
CRT-D Circuit  
-12V  
R390  
P301  
P350  
P405  
Q340  
200V  
1
2
1
2
R436  
8
8
Q341  
17  
17  
D340  
R391  
D341  
C340  
R392  
R879  
Z801  
D315  
R346  
GATE  
14  
PROTECTOR  
16  
C894  
Fig. 9-14  
74  
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5. HIGH VOLTAGE GENERATION CIRCUIT  
The high voltage generation circuit develops an anode volt-  
age for the picture tube, focus, screen, CRT heater, video  
output (210V) and so on by stepping up the pulse voltage  
developed for flyback period of the horizontal output cir-  
cuit with the FBT, and supplies the power to various cir-  
cuit.  
5-1. Theory of Operation  
AFC  
blanking  
CRT  
anode  
10  
9
Heater  
+12V-1  
R448  
C447  
C303  
4
Auxiliary  
winding  
+35V  
D408  
R327  
D302  
7
C310  
6
C460  
D460  
R469  
R443  
Focus pack  
-27.5V  
+210V  
5
D406  
3
C446  
C448  
Primary  
winding  
+125V  
2
R444  
1
ABL  
Q404  
C440  
C443 C444  
T401  
1040V(p-p)  
1H  
C463  
H deflection coil  
L462/L463/L464  
(15.625kHz)  
C418  
C467  
R441  
L441  
C423  
HIGH VOLTAGE DPC CIRCUIT  
REGULATOR  
CIRCUIT  
Fig. 9-15  
75  
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5-1-1. +210V  
For the flyback period, pulses are stacked up to DC +125V  
with FBT, and the voltage is rectified by D406 and filtered  
by C446.  
+125V  
0
5-1-2. +35V, 12V  
Pin 4 of the FBT is grounded and the shaded area of nega-  
tive pulse developed for opposite period of the flyback pe-  
riod is rectified, thus developing better regulation power  
supply.  
Fig. 9-16  
0
0
10  
5-1-3. –27V  
4
7
As a power for the DPC circuit, a negative pulse signal is  
rectified by D460 and filtered with C460, thus developing  
the –27V.  
+35V  
For +12V  
6
2
1
5-1-4. High Voltage  
Singular rectification system which uses a harmonics non-  
resonant type FBT is employed and a better high voltage  
regulation is obtained, so amplitude variation of pictures  
becomes low.  
0
Fig. 9-17  
G
F
G
Pulse  
E
Picture  
tube anode  
E
F
Picture  
Primary  
tube capacitor  
EH  
D
C
D
C
Stacked  
pulse of  
4 block  
EO  
B
B
A
Auxiliary  
A
1H  
15.735KHz  
ABL  
Fig. 9-18  
5-2. Operation Theory of the Harmonic Non-Resonant System and Tuned Waveforms  
The high voltage coil is of film multi-layer winding type  
Moreover, a capacitance between the internal and external  
coatings of the picture tube works as a smoothing capacitor.  
and the coils are isolated into seven blocks. Each block is  
connected through a diode.  
Focus voltage is obtained at point EO.  
The basic operation is described in the case of 4 blocks con-  
struction for simplification. Positive or negative pulse deter-  
mined by stray capacitance of each coil develops at terminal  
points ( A,B,C,D,E,F,G ) of each coil as shown in Fig. 9-  
18, and these pulses are stacked as shown, thus developing  
the high voltage.  
76  
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C2  
C + C  
6. HIGH VOLTAGE CIRCUIT  
6-1. High Voltage Regulator  
6-1-1. Outline  
V
V
V
=
=
V
V
1
2
3
CP1  
CP2  
CP  
CP  
1
2
2
2
C2  
C + C  
CP  
1
Generally, four kinds of methods exist to stabilize a high  
voltage in high voltage output circuits using the FBT:  
C2  
C + C  
=
V
CP2  
1
(1) Stabilization by varying the power supply voltage.  
The V  
developed across C2 is DC-clamped with a diode  
CP2  
(2) Stabilization by varying L value with a saturable reac-  
tance connected in series with the primary winding of  
the FBT.  
D1 and the resultant voltage is smoothed with a diode D2  
and a capacitor C3. Thus processed voltage is obtained at  
the point B . This voltage is used to provide a base current  
for the transistor Q1 or to flow the collector current. The  
voltage at the point B decreases with the circuit impedance  
(3) Stabilization by varying equivalent capacitance of the  
resonant capacitor C0.  
(4) Stabilization by superimposing a DC or pulse (this  
varies the high voltage) on a lower voltage side of the  
high voltage winding of the FBT.  
and finally lowers up to a V saturation voltage of Q1.  
CE  
Then, V  
is not clamped by D2 with the voltage at the  
CP2  
point B . Since the V is expressed as a sum of V  
and  
CP  
CP1  
In this unit, pulse transformer is eliminated and the regula-  
tor circuit using the method (3) is employed. The block dia-  
V
as shown by equation 3 , V decreases by amount  
CP2 CP  
the V  
is decreased. This varies the high voltage.  
CP2  
gram is shown in Fig. 9-19.  
Q1 collector current is controlled by Q1 base current which  
is an output of the comparison inverted amplifier. That is,  
the Q1 base current is controlled by a voltage obtained by  
comparing a detection voltage of the top breeder of the FBT  
(9.1V) and a DC voltage of 9V.  
Z450  
CR-BLOCK  
T461  
FBT  
Hotizonal  
ANODE  
output  
D
Y
Horizontal  
FBT  
125V  
PW output  
output  
C1  
L
H
L
P
+B  
CS  
D1  
C2  
C3  
-27V  
B
D2  
High voltage Reg.  
Q1  
High voltage  
Reg.  
output amp  
V.  
Ref.  
Fig. 9-19 Basic circuit for high voltage regulator  
emplyed in the unit  
Fig. 9-20  
6-1-2. Theory of Operation  
VCP = VCP1 + VCP2  
Fig. 9-20 shows a basic circuit of the high voltage regulator  
used in the unit.  
The high voltage regulator circuit splits a resonant capacitor  
C0 to C1 and C2. thereby dividing the collector voltage (V  
)
CP  
VCP 1  
VCP 2  
of the H output transistor with C1 and C2.  
Here, assume each voltage developed across C1 and C2 as  
and V , respectively,  
V
CP1  
CP1  
each relation can be expressed by the above equations  
1 ~ 3 .  
Fig. 9-21  
77  
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6-1-3. Actual  
As a result, Q480 collector current increases and Q480 col-  
lector voltage (at the point B ) decreases. Then, a peak value  
Fig. 9-22 shows the actual circuit used in the unit.  
A resonant capacitor C0 is also split into two capacitors C443  
and C444 in this circuit. The high voltage regulator cirucits  
is structured by splitting the C443 to two capacitors of C443  
and C448.  
of V  
across C418 is clamped by the diode D443 at the  
CP2  
collector voltage lowered, and the collector voltage V of  
CP  
Q404 (H output transistor) obtained as a sum of the voltage  
V
across C443 and V  
across L418 decreases. Then,  
CP2  
CP1  
Here, assume a high voltage increases and the detection volt-  
the high voltage also decreases.  
age E ' obtained by dividing the high voltage also increases  
D
When the high voltage lowers, the corrective operation is  
carried out in reverse order.  
in proportional to the high voltage. This makes the voltage  
E increase at pin 7. (The voltage is impedance transformed  
D
*
Resustors R451, R452, R453 and R455 are used to cor-  
rect undersirable influence (H amplitude increase at mini-  
by a voltage follower circuit consisting of op amplifier Q483  
at pin 7.)  
mum I ) by the H amplidude regulator.  
H
The voltage E and a 9V reference voltage developed by a  
D
3-terminal regulator Q420 are compared. When the E in-  
D
creases, the voltage at pin 2 of Q483 differential amplifier  
also increases, and the base current I of the high voltage  
B
transistor Q480 increases.  
FBT  
CR-BLOCK  
E
H
Horizontal  
output  
L462  
L463  
L464  
C443  
C444  
Q404  
C440  
-27V  
C
S
R460  
Q462  
125V  
R466  
C467  
R455  
E
D
'
R461/R469  
Q460  
D461  
L461  
R463  
R435  
C482  
Q483  
C464  
R454  
E
D
6
8
R453  
7
D443  
C419  
R452  
R451  
Q480  
B
R489  
D444  
C418  
R434  
R450  
R490  
4
3
2
R488  
C483  
R431  
R492  
Q420  
9V-1  
R494  
R439  
R487  
Fig. 9-22 Actual high voltage regulator circuit  
78  
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7. X-RAY PROTECTION CIRCUIT  
7-1. Outline  
In case picture tube using high voltage, when high voltage  
rises abnormally due to components failure and circuit mal-  
function, there is possible danger that X-RAY leakage in-  
creases to affect human body. To prevent it, X-RAY protec-  
tion circuit is equipped.  
7-2. Operation  
Then Q463 turns on. By this Tr6 and Tr6 turn on to make  
ON/OFF pulse at pin 7of QA01 in low level, Q846 and Q845  
turns off, then relay SR81 turns off. Tr6 and Tr7 are in thy-  
ristor-connection, and 5V of power holds protection opera-  
tion until main power switch is turned off. During circuit  
operation, power LED near main power switch blinks turn  
on and off in red.  
Figure 9-23 shows the circuit diagram. Supposing high volt-  
age rises abnormally due to some reason, pulse at pin 9 of  
T461 also rises, and detection voltage E rectified by D471  
D
and C471 in X-RAY protection circuit rises. When E rises,  
D
emitter voltage of Q464 divided by R459 and R462 becomes  
higher than [zener voltage (6.2V) of D458 + Q464 VBE ].  
This causes Q464 turns on to supply base current to Q463.  
Caution:  
• To restart TV set, repair failure first.  
5V  
Z801  
15  
R9  
R10  
12V  
ED  
Tr7  
Q463  
Q464  
R19  
R459  
R462  
R472  
C471  
T461  
9
C894  
Q846  
14  
Tr6  
RELAY  
SR80  
D471  
16  
C1  
R12  
R11  
C458  
D459  
R468  
R879  
R467  
Tr5  
R458  
D458  
Q845  
C459  
17  
Fig. 9-23 X-RAY protection circuit  
79  
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8. OVER CURRENT PROTECTION CIRCUIT  
8-1. Outline  
If main power (125V) current increases abnormally due to  
components failure, there is possible danger of the second-  
ary damage like failure getting involved in other part fail-  
ure, and abnormal heating. To prevent this, over current pro-  
tection circuit is equipped, which detects current of main B  
line to turn off power relay in abnormal situation.  
8-2. Operation  
Fig. 9-24 shows over current protection circuit. When the  
current of main B line increases abnormally due to the  
shortage in load of main B line, voltage drop arises across  
R470. By this voltage drop, when base-emitter voltage of Tr8  
in protector module (Z801) becomes approx. 0.7V or more,  
Tr8 turns on, and the voltage by divided ratio of R15 and R16  
is applied to cathode of ZD4. When this voltage becomes  
higherthanzenervoltageofZD4, ZD4turnsontosupplybase  
current to base of Tr6 via R14. This causes Tr5 ON and  
voltage at pin 16 of Z801 becomes low.  
Therefore, QB30 and Q843 turns off to set SR81 OFF. Tr6  
and Tr7 in Z801 are in thyristor-connection, and power 5V-  
1 supplied at pin 15 keeps protection operation for standby  
power until main power switch is turned off. During circuit  
operation, power LED near main power switch blinks in red.  
Caution:  
• To restart TV set, repair failure first.  
F470  
R470  
To T461  
MAIN B  
R471  
R479  
C472  
5V  
15  
2
1
MICON  
QA01#7  
R9  
ZD4  
R16  
R10  
Tr7  
RELAY  
SR80  
Tr8  
D1  
R15  
R14  
C1  
16  
Tr6  
Q845  
Q846  
R12  
R11  
Tr5  
Z801  
PROTECTOR MODULE  
17  
Fig. 9-24 Over current protection circuit  
80  
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SECTION X: DEFLECTION DISTORTION CORRECTION CIRCUIT  
(SIDE DPC CIRCUIT)  
1. DEFLECTION DISTORTION CORRECTION IC (TA8859CP)  
1-1. Outline  
(4) V picture position (neutral voltage setting)  
The deflection distortion correction IC (TA8859CP), in com-  
bination with a V/C/D IC (TA1222AN) which has a V pulse  
output, performs correction for various deflection distortions  
(5) V M-character correction  
(6) V EHT correction  
(7) H amplitude  
2
2
and V output through the I C bus control. All the I C bus  
controls are carried out by a microcomputer and can be con-  
trolled with the remote control.  
(8) L and R pin-cushion distortion correction I (entire area)  
– Not used for this model.  
(9) L and R pin-cushion distortion correction II (corner  
portions at top and bottom) – Not used for this model.  
1-2. Functions and Features  
The IC has functions of V RAMP voltage generation, V  
amplitude automatic switching (50/60 Hz), V linearity cor-  
rection, V amplification, EHT correction, side pincushion  
(10) H trapezoid distortion correction – Not used for this  
model.  
(11) H EHT correction  
2
correction, I C bus interface, etc. and controls following  
(12) V AGC time constant switching  
2
items through the I C bus lines.  
(1) V amplitude  
1-3. Block Diagram  
(2) V linearity  
Fig. 10-1 shows a block diagram of the basic circuit.  
(3) V S-character correction  
+9V  
16  
5
3
14  
15  
V. AGC time  
constant SW  
Trigger  
det  
Puise  
Gen.  
Waveform  
shape  
V. Rame  
13  
A G C  
V. Trigger-in  
control through  
bus  
H. trapezoid distortion  
correction  
V. M-Character  
correction  
V. linearity  
correction  
V. S-character  
correction  
L-R pincushion  
distortion correction I  
(Bus Control Signal)  
        SDA SCL  
L-R pincushion  
distortion correction II  
(Top & bottom comer section)  
V. Amplitude  
Adj.  
10  
9
Logic  
H.EHT  
correction  
V. screen  
position  
H.EHT  
input  
V. EHT  
correction  
12  
H. Amplitude  
Adj.  
2
EW-drive  
4
8
6
1
V drive     V. feedback                              EHT INPUT                                              EW feedback  
Fig. 10-1  
81  
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2. DIODE MODULATOR CIRCUIT  
In N5SS, the distortion correction is carried out by the ditigal  
convergence circuit. So the component of the diode modu-  
lator circuit is the same as that of conventional television,  
because it is used only for the horizontal oscillation adjust-  
ment.  
When the negative pulse developed at the point B is inte-  
grated with Lm and Csm, its average value appears at Csm  
as a negative voltage.  
By modulating this voltage with Q460, a waveform of Vm is  
obtained as shown in Fig. 10-3 b). As a result, the voltage  
Fig. 10-2 shows a basic circuit of the diode modulator used  
in the N5SS.  
V which is the sum of the power supply voltageV and the  
S
B
Vm is applied across the S-curve capacitor C . The V be-  
S
S
comes as a power source for the deflection yoke as shown in  
Fig. 10-4, is applied to the horizontal deflection yoke.  
A key point in the modulation circuit shown in Fig. 10-2 is  
to develop a negative pulse at point B .  
In this circuit, a current loop of the resonant circuit for flyback  
period is shown by an arrow, and the energy stored in L is  
DY  
transferred to resonant capacitors Cr, Crm in passing through  
Cr, Crm, C when the scanning completes. As a result, a  
S
positive, horizontal pulse as shown in Fig.  
10-3 a) will appear at Cr, and the current flows into Crm  
with the direction as shown. Then a pulse as shown in Fig.  
10-3 b) develops at the point B.  
On the other hand, since constant amplitude pulses across  
Cr, as shown in Fig. 10-3, are applied to the primary wind-  
ing, the high voltage of FBT also develops a constant volt-  
age.  
0
a) Waveform at point  A  
0
b) Waveform at point  B  
A
Fig. 10-3  
FBT  
LDY  
DD  
Cr  
H
OUT  
V
B
Vs  
Cs  
V
B
Lm  
B
Vm  
Q460  
DM  
VS  
Csm  
Crm  
0
Fig. 10-2  
Fig. 10-4  
82  
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3. ACTUAL CIRCUIT  
In the actual circuit, the resonant capacitor is split into two  
as shown in Fig. 10-7. One, C440, is inserted between the  
collector of the H. OUT transistor and ground and another  
C444 inserted between the collector and emitter. In Fig. 10-  
5, C440 is expressed as C and C444 as C , and the resonant  
1
2
FBT  
IP2  
IP1  
current path for the flyback period is shown by arrows.  
C
1
I
H
In a conventional circuit, when brightness of a picture tube  
varies, high voltage current varies and the high voltage also  
varies. As a result, horizontal amplitude also varies.  
LDY  
I
P
H.  
OUT  
IY1  
IY2  
I
C
S
Y
V
S
However, in this circuit, the horizontal amplitude variation  
can be suppressed to near zero if the high voltage current  
varies with variation of the high voltage.  
C
2
V
B
Lm  
When the scanning period completes, the energy stored in  
C
3
IP2  
IY1  
Vm  
the deflection yoke L  
is transferred to the resonant ca-  
DY  
Csm  
pacitor in a form of current I . In this case, the current is  
Y
split into two; I passing through C , C and I passing  
Y1  
1
3
Y2  
through C . In the same way, the energy stored in the pri-  
2
mary winding of the FBT is transferred to the resonant ca-  
Fig. 10-5  
pacitor in the form of I . In this case, the current (path) is  
P
also split into two; I passing through C and I passing  
P1  
1
P2  
through C , C . Concequently, the current differences be-  
2
3
tween I and I (I -I ) passes through C .  
Y1  
P2 Y1 P2  
3
When the high voltage current I reduces with a dark pic-  
H
ture, the current I in the primary circuit decreases, so I  
V
B
P
P1  
and I also decrease. However, a current flowing into (I  
-
P2  
Y1  
I ) increases as I decreases. As a result, the pulse devel-  
P2  
P2  
oping at the point B increases and the voltage Vm at Csm  
also increases as shown in Fig. 10-8. That is, when a dark  
VS  
picture appears, the voltage across S-curve capacitor C in-  
S
creases as shown in Fig. 10-8, the high voltage rises, and the  
0
horizontal amplitude is going to decrease. But, as V in-  
S
Vm  
creases, the deflection yoke current increases and this works  
to increase the horizontal amplitude. Accordingly, if the  
brightness of picture changes, the horizontal amplitude is  
maintained at a constant value. This is one of the fine fea-  
tures the circuit has.  
Fig. 10-6  
83  
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3-1. Basic Operation and Current Path  
3-1-1. Later Half Scanning Period  
3-1-2. First Half Scanning Period  
When the power is turned on, the power supply voltage V  
When the base drive current decreases and the H. OUT tran-  
B
is applied to C and Csm, and the C acts as a power source  
sistor is turned off, each energy stored in L , Lm, L of  
DY  
S
S
P
for a later half of the scanning period for which the H. OUT  
FTB is transferred to C , C and C , respectively, and the  
1
2
3
transistor is turned on, and the deflection current I flows in  
resonant current becomes zero at a center of the flyback pe-  
riod. Then, V and V pulses show a maximum amplitude.  
Y
the path as shown below.  
A
B
V
A
FBT  
V
A
LDY  
lP  
FBT  
I
Y
IP1  
C
1
C
2
LDY  
IY2  
IP2  
Cs  
lP  
I
Y
H.OUT  
+
Cs  
V
B
V
B
L
M
I
M
V
B
IDC  
V
B
CSM  
L
M
I
M
IDC  
D
M
CSM  
+
Fig. 10-9  
Fig. 10-7  
Voltage & current waveform in H period.  
I
Y
0
I
Y
0
V
A
0
I
M
0
IDC  
V
A
0
V
B
0
0
0
I
M
0
IDC  
C
C
1: IY1+IP1  
2: IY2+IP2  
C
C
1
2
V
B
0
Fig. 10-8  
C
3: IP2-IY1- M  
I
C
3
Fig. 10-10  
84  
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3-1-3. Later Half of Flyback Period  
3-1-4. First Half of Scanning Period  
All energy in the coil has been transferred to the resonant  
capacitors at the center of the flyback period, and the volt-  
age shows the maximum value. However, during next half  
of the flyback period, the energy of the resonat capacitor is  
discharged as a reverse current through respective coil. When  
When the flyback period completes, the damper diode D  
D
and the modulation diode D turn on, and the I and I  
M
Y
M
proportionally decrease from the maximum value to zero.  
The H. OUT transistor is turned on just preceding at the center  
of the scanning period, and repeats the steps 3-1-1 through  
3-1-4 stated above.  
the discharge has been completed, V and V becomes zero,  
A
B
and the deflection current in reverse direction becomes the  
V
A
maximum.  
V
A
L.O.P.T  
FBT  
LDY  
LDY  
IP2  
I
Y
I
P
IP1  
C
2
C
1
I
I
Y
D
D
C
S
C
S
IY2  
IY1  
V
B
V
B
V
B
V
B
C
3
L
M
L
M
M
I
M
D
M
IDC  
I
M
CSM  
CSM  
Fig. 10-11  
Fig. 10-13  
Voltage & current waveform in H period.  
Iy  
0
I
Y
0
V
A
0
0
V
A
0
I
M
IDC  
I
M
0
IDC  
V
B
0
V
B
0
C
C
1: IY1+IP1  
2: IY2+IP2  
C
C
1
2
0
0
Fig. 10-14  
C
3: IP2-Iy1-IM.  
C
3
Fig. 10-12  
85  
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SECTION XI: DIGITAL CONVERGENCE CIRCUIT  
2. CIRCUIT DESCRIPTION  
1. OUTLINE  
The digital convergence circuit develops outputs to correct  
screen distortion and perform color matching. The digital  
convergence circuit used is of an all digital type and allows  
good adjustments in comprise with a conventional analog type  
circuit.  
2-1. Configuration  
Fig. 11-1 shows a block diagram. The digital convergence  
unit consists of Q701 T7K64 which plays a major role, Q707  
2
PLL circuit which locks a sync entered, Q713 E PROM to  
store the data, and Q703-5 D/A converter which develops a  
correction wave form.  
Followings are features of the digital convergence circuit.  
1) No adjustment controls (volumes)  
2) Registration accuracy increased.  
3) Space saved  
The output signal from the Q703 – 705 D/A converter is  
amplified and wave form shaped by Q715, Q717 and Q719,  
and comes out from the unit.  
The clock signal for the PLL is adjusted by L719 to a refer-  
ence frequency of 32 ± 0.1MHz under no input status.  
4) Adjustment by a remote control  
The data adjusted are classed into 4 screens for each screen  
2
A test pattern generator is also built inside Q701 and devel-  
ops R, G, B signals and a Ys switching signal.  
mode. These data are stored on E PROMs inside the unit.  
The memory size used in this case is 4 Kbits per one screen.  
Each screen adjustment is carried out by calling the adjust-  
ment screen with the remote control unit supplied and the  
adjustment is carried out according to the dimensions speci-  
fied for each screen. The control of the unit is carried out in  
2-2. Circuit Description  
(1) With the power turned on, the unit is reset and enters  
an operation standby status. And a sync signal of the  
unit enters external Q707 and Q701. The signal en-  
tered Q707 is counted down by a counter inside the  
Q701 and this is used as the reference clock. Q701  
works in synchronization with the reference clock sig-  
nal and the sync signal.  
2
the I C format.  
(2) A command is sent from the microcomputer in the unit  
and Q701 is set up to load the data in Q713 to the in-  
ternal RAM. (8 (horizontal) x 7 (vertical) x 3 (color))  
(3) Q701 transfers a serial data specified to Q703 – 705  
according to the RAM data. In this case, interpolation  
for the RAM data is automatically carried out by a built  
-in digital filter inside Q701.  
(4) The serial data sent from Q701 are digital-analog con-  
verted by Q703 – 705, thus developing the analog type  
wave form.  
(5) The signals sent from Q703 – 705 are amplified Q715,  
Q717, Q719, respectively, and then filtered in the next  
stage to smooth and shape the wave form. Thus pro-  
cessed signals are used as H and V correction wave  
forms for R, G, and B signals.  
86  
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D A T A  
C L K  
L o a d  
S a v e  
Fig. 11-1 Block diagram  
87  
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3. PICTURE ADJUSTMENT  
The data adjusted manually through the screen by displaying  
the adjusting screen on the display is once written on RAM  
inside Q701. Adjust each adjusting point and store the modi-  
Four screens for Normal/Full, Theater wide 1, Theater Wide  
2, Theater Wide 3 are provided for the adjustments. When  
making the adjustments, receive the U/VHF or CABLE  
broadcasting signal or the built-in pattern signal of the mi-  
croprocessor to make a synchronization with the frequency  
of the adjusting screen with the unit..  
2
fied total data on RAM as correct one into Q713 E PROM.  
The adjustment is carried out for each screen mode, and its  
order is as follows; Normal/Full ® Theater Wide 1 ® the-  
ater Wide 2 ® Theater Wide 3. (When the adjustment value  
is saved after adjusting Normal/Full, the microprocessor cal-  
culates the adjustment values for Theater Wide 1, 2 and 3  
based on the adjustment value of Normal/Full mode and sets  
the values for Theater Wide 1, 2 and 3 to the closed values to  
require minimum adjustment.)  
This adjustment program is prepared as the microprocessor  
function of the set and it is possible to adjust by the remote  
controller attached.  
3-1. Outline of the Modification Process of  
the Storing Adjustment Data  
Set the convergence adjustment screen.  
The adjusted data is stored in the memory inside Q713  
2
E CPROM which is a non-volatile memory.  
The RAM data inside Q701 is lost when the power turns  
off. So the initial operation status is set by the software com-  
mand from the microprocessor QA01 every time when the  
unit turns on.  
Normal full  
color matching  
(R, B screen)  
Normal full distortion  
modification  
Theater wide 1  
distortion modification  
(G screen)  
Theater wide 1  
color matching  
(R, B screen)  
(G screen)  
1. Push "7" key of the remote  
    controller to save.  
1. Push "7" key of the remote  
    controller to save.  
2. turn "PIC-SIZE" key of the  
    remote controller ON  
2. turn "PIC-SIZE" key of the  
    remote controller ON  
Theater wide 2  
distortion modification  
(G screen)  
Theater wide 3  
distortion modification  
(G screen)  
Theater wide 3  
color matching  
(R, B screen)  
Theater wide 2  
color matching  
(R, B screen)  
END  
1. Push "7" key of the remote  
    controller to save.  
1. Push "7" key of the remote  
    controller to save.  
2. turn "PIC-SIZE" key of the  
    remote controller ON  
2. turn "PIC-SIZE" key of the  
    remote controller ON  
Fig. 11-2  
88  
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3-2. Service Mode  
3-2-1. Outline  
3-2-2. Entering/Exiting Mode  
The service mode, one of the functions this unit provides, is  
controlled by the microprocessor QA01 and .  
When the “MUTE” key on the remote controller is pressed,  
the screen display appears. Pushing the “MUTE” key again  
disappears the screen display.  
This mode is set by the special operation to avoid the easy  
operation by the user. Move the cursor to between the adjust-  
ment points of 8*7/each color and modify the data directly.  
Before entering the service mode, perform the center adjust-  
ment using the color unmatching adjustment in the user menu.  
In this status, when the “MENU” key on the set console is  
pushed while pushing the “MUTE” key, S is displayed on  
the upper right of the screen. When the “MENU” key is  
pressed again, the service data is displayed on the upper left  
on the screen.  
When “7” key on the remote controller is pressed in this sta-  
tus, the screen changes to display the cross hatch screen (the  
first screen described later) and the convergence adjustment  
screen appears.  
When “7” key is pressed again, the data storing operation is  
automatically carried out and the cross hatch + data display  
screen (the second screen described later) appears.  
When “7” key is pressed furthermore, the display returns to  
the initial screen.  
+
+ MENU  
X
X
Service data display  
(original picture)  
The first picture  
The second picture  
Remote  
"7" key  
Remote  
"7" key  
Remote "7" key  
+automatic save  
Fig. 11-3  
Note:  
When changing the convergence correction data, always be  
sure to perform the automatic storing operation. If the power  
turns off without carrying out the automatic storing opera-  
tion, the modified data is lost.  
89  
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3-2-3. Initial screen  
The screen mode is Normal/Full screen mode.  
Correction point: Vertical 8 * Horizontal 7 (® and -marks  
are the adjusting points.)  
Primary screen  
Secandary screen  
Cursor (Red) (Blinking)  
Y
1
2
Data display  
3
4
5
X:3  
Y:2  
C:R  
S:FULL  
6
7
X 1  
3
2
5
4
7
8
6
Screen frame  
Screen Center  
Adjusting point display  
X : Horizontal position display  
Y : Vertical position display  
C : Color display  
S : Screen mode display  
Fig. 11-4  
(1) First screen:  
(2) Second screen  
The initial cross hatch screen appears. The pattern col-  
ors are displayed with 3 colors. The cursor color is red  
and left blinking.  
When changing from the first screen to second screen, the  
convergence correction waveform is mute for 1 second. The  
2
modified data for this period is sent to Q713 E PROM from  
Q071 RAM and then stored.  
When the modification is carried out, the last memory  
status is displayed.  
The second screen is displayed upper left of the first screen,  
so the convergence adjustment cannot be carried out when  
the second screen is displayed.  
Cursor mode:  
Lighting: Data modification mode  
Blinking: Cursor move mode  
Note:  
• The adjusted data is automatically stored when the dis-  
play changes from the first screen to the second screen.  
So be sure to perform this operation after adjustment com-  
pletes.  
The display color shows the color which can modify  
the data.  
• Adjustment should be carried out with a corresponding  
signal received.  
90  
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3-2-4. Key function of remote control unit  
RECALL  
MUTE  
PIC SIZE  
TV/VIDEO  
100   Key  
0       Key  
ENT  Key  
5       Key  
Red test pattern ON/OFF  
Green test pattern ON/OFF  
Blue test pattern ON/OFF  
Cursor shift/data change  
mode chang over  
1
2
3
4
6
9
2
5
8
0
3
6
1
4
7
CH  
8
7
4
8       Key  
2       Key  
6       Key  
4       Key  
3       Key  
Cursor down/adjusting point down  
Cursor UP/adjusting point UP  
Cursor right/adjusting point right  
Cursor left/adjusting point left  
Cursor color change  
5
6
7
8
9
10  
9
CH RTN  
VOL  
5
3
1
2
ENT  
100  
10 7       Key  
Data save  
ADV/  
EDS  
MENU  
PCB CH  
FAV  
FAV  
ENTER  
RESET  
EXIT  
ADV/  
POP  CH  
STOP SCURCE  
PLAY PCP  
TV/VCR  
REW  
FF  
REC  
CH SEARCH  
STILL  
SWAP  
TOSHIBA  
Fig. 11-5  
91  
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3-2-5. Operation procedure  
(1) Set the screen to Normal or Full mode using the PIC-  
SIZE key on the remote controller.  
(8) When the adjusting position is determined, press “5”  
key on the remote controller to enter the cursor blink-  
ing status.  
(2) Set the unit to the service mode with MUTE + MUTE  
+ MENU keys pressed. (Entering to S mode.)  
(9) Set the cursor to the adjusting position by pressing “2”,  
“8”, “4” and “6”, and perform the pattern distortion  
correction and color matching adjustments.  
(3) Set the unit to the convergence adjusting mode by press-  
ing the “7” key on the remote controller. (Fist screen)  
(10) Press “5” key again and move the cursor. Perform the  
adjustment in the same way as described above.  
(4) Select the pattern to display by pressing 100, 0, ENT  
on the remote controller.  
(11) After the adjustment completes, perform the automatic  
storing operation by pressing “7” key.  
(Red adjustment; 100 ... ON, 0 ... ON, ENT... OFF)  
(Green adjustment; 100 ... OFF, 0 ... ON, ENT... ON)  
(Blue adjustment; 100 ... ON, 0 ... OFF, ENT... ON)  
(12) In the same way as described above, adjust WIDE 1,  
WIDE 2 and WIDE 3 screens using PIC-SIZE key.  
(5) Select the color to adjust by pressing “3” key on the  
remote controller.  
(13) When all of the screen mode adjustment complete,  
perform the automatic storing operation by pressing  
“7” key.  
(6) Confirm that the cursor is in the movable status (the  
cursor blinking status).  
(7) Select the adjusting position by pressing “8”, “4” and  
“6”.  
3-3. Each Screen Adjustment Method  
3-3-1. Normal/Full  
12xA  
2mm  
2mm  
Screen frame  
40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm  
          Dimension A: 73.5mm  Dimension B: 33.2mm  
Fig. 11-6  
92  
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3-3-2. Theater Wide1  
249  
213  
103.5  
Screen  
center  
0
7.5  
115  
217.5  
249  
40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm  
Fig. 11-7  
348.5  
298  
144  
Screen  
center  
0
10  
159  
303  
348.5  
56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm  
Fig. 11-8  
93  
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3-3-3. Theater Wide 2  
298.9  
256.2  
128.1  
Screen  
center  
0
128.1  
256.2  
298.9  
40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm  
Fig. 11-9  
361.8  
301.5  
180.9  
Screen  
center  
0
180.9  
301.5  
361.8  
56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm  
Fig. 11-10  
94  
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3-3-4. Theater Wide 3  
269.5  
231  
115.5  
Screen  
center  
0
115.5  
231  
269.5  
40 inches 16:9 Screen size: Horizontal 885mm x Vertical 498mm  
Fig. 11-11  
379.2  
325  
162.5  
Screen  
center  
0
162.5  
325  
379.2  
56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm  
Fig. 11-12  
95  
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4. CASE STUDY  
In many cases, a color deviation will be corrected by return-  
ing the HIT and WID data for the main deflection side to the  
initial values.  
4-2. When Convergence Unit is Replaced  
When replacing the convergence units, all screens must be  
adjusted basically. However, performing the adjustment as  
shown below will reduce the procedures considerably.  
Followings are cases which need readjustment of the conver-  
gence by all means.  
(1) Replace the memory (Q713) for the new unit with the  
memory (Q713) for the failure unit. Mount the con-  
vergence unit on the set and the screen status before  
replacement will be directly reproduced.  
4-1. When CRT is Replaced.  
When the CRT is replaced, readjustment of the main deflec-  
tion and color matching will be necessary. Perform the ad-  
justments as follows.  
(2) Mount the new unit with the old memory installed in  
combination on the set, and turn on the set. A screen as  
if it is moving vertically or horizontally will appear.  
(1) Replace two CRTs, blue and red.  
(3) Adjust each center of green, red, and blue with the cen-  
tering magnets again.  
(2) Perform horizontal adjustments for blue and red yokes  
to the green CRT. Mount the yokes and velocity modu-  
lation coils + alignments so that they closely touches  
the CRT without any clearance.  
(4) Check to see color deviation and screen size deviation  
among the colors. If deviated, perform the adjustment  
for the main deflection and the color matching for the  
convergence.  
(3) Adjust the red and blue alignments. (refer to item De-  
tailed adjustments for alignments)  
(4) Perform the center adjustment for the blue CRT center  
and the red CRT center to the green CRT center with  
the centering magnets.  
(5) Adjust the HIT, WID data to obtain the data which gives  
the most precision to the green.  
(6) Perform the color matching in terms of the convergence  
for each screen. In this case, do not move the green.  
(7) After completion of the convergence adjustment for  
each screen, replace the green CRT. For the green CRT,  
repeat the steps 2-5 to make the color matching in terms  
of the convergence by using the red and blue as the  
reference.  
96  
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5. TROUBLESHOOTING  
5-1. Adjusting Procedure in Replacing CRT  
Cut off  
User convergence enter check  
Centering  
Lens focus  
Electrical focus  
Yoke horizontal  
Convergence adjustment  
White balance  
End  
5-2. Adjusting Procedure in Replacing Convergence Unit/Main Def  
User convergence enter check  
Centering  
Convergence adjustment  
End  
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6. CONVERGENCE OUTPUT CIRCUIT  
6-1. Outline  
6-2-4. CONV-OUT mute  
In power-on operation, transistors Q765 and Q766 are made  
turned ON, and –15V is applied to pin 3 of CONV-OUT IC.  
These cause mute operation on CONV-OUT.  
This circuit current-amplifies digital convergence correction  
signal at output circuit, and drives by convergence yoke to  
perform picture adjustment.  
6-2-5. Operation of IC  
Digital convergence output signal 6ch adjustment is done.  
(H-R/G/B) (V-R/G/B)  
1) Q764 (TC74HC4050AP)  
Sync signal which is input from P711 1 VD, 2 HD, is,  
through buffer, supplied to digital convergence P708.  
6-2. Circuit Description  
2) 3-terminal source  
6-2-1. Signal flow  
Q754 (+5V) Q755 (+9V) Q756 (-9V)  
Source for digital convergence  
3) Q767 (TC4066BP)  
Signal which is corrected by digital convergence, is output to  
P708 (V, H R/G/B);  
is input to Q751 (V) R/G/B, and is output to P713, P714 and  
P715;  
P711 4 SDAM, 5 SCLM : microcomputer. Busline, through  
Q767, is input to Digital Convergence P709, and is controlled.  
is input to Q752 (H) R/G/B, and is output to P713, P714 and  
P715.  
4) To adjust from outside of digital convergence :  
Put adjusting jig into 6P socket of P720. Iscs turns from H to  
L, switch of Q767 is changed over. Then busline from mi-  
crocomputer is cut off.  
6-2-2. Over current protection circuit  
All currents of Power supply, -15V, +15V and +30V are de-  
tected to protect CONV-OUT IC from damage due to output  
short of CONV-OUT.  
P720 3 SCLU, 4 SDAU  
Controlled by external adjusting jig.  
Current value: Normal ± 15V approx. 700mA  
+30V approx. 200mA  
Detecting curren ±15V approx. 1.8A  
or more  
+30V approx. 700mA or more  
protecting operation  
6-2-3. Pump-up source  
CONV-OUT IC Q752 (H)  
Pin 10 (+15V/H, PV)  
Pin 5 (+30V)  
By HD input signal, pump-up is done only in horizontal re-  
tracing time.  
Pump-up  
Pump-up source waveform  
Horizontal correction wafeform  
+30V  
+30V  
+15V  
0V  
+15V  
0V  
-15V  
-15V  
Horizontal correction waveform  
Fig. 11-13  
98  
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6-3. Convergence Block Diagram  
P712  
+12V  
NC  
1
2
3
PROTECT  
P
+5V-1  
RESET  
1
2
3
4
5
POWER  
AC PULSE  
GND  
P711  
1
2
3
4
5
6
7
VD  
HD  
I2  CS  
SDAM  
SCLM  
GND  
DFAI  
P720  
1
2
3
4
5
6
GND  
INCS  
SCLU  
SDAU  
GND  
GND  
Fig. 11-14  
99  
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7. CONVERGENCE TROUBLESHOOTING CHART  
No Convergence  
correction wave.  
Relay operation sound  
at power on.  
Relay turns on  
once but immediately  
turns off.  
Reray ON  
OK  
Reray OFF  
Check screen modes  
of picture.  
Convergence PCB,  
pull out of P712.  
Protect  1  
Reray ON  
Reray ON  
Check power  
supply circuit.  
Check Q751, Q752  
and repair.  
Reray OFF  
Reray OFF  
Reray OFF  
Check P708 R/G/B  
correction wave.  
Proceed to "protection  
circuit diagnosis procedures".  
OK  
NG  
Check voltage at    
Check power supply  
±15V+30V pump up.  
circuit.  
Convergence output signals correction wave  
Pump-up  
OK  
NG  
Are output signals  
Check DEF PC13.  
applied to H, Vblk of P711.  
+30V  
OK  
NG  
Check voltage across  
±9V+5V Q754, Q755, Q756.  
Check Q754, Q755,  
Q756 and repair.  
0V  
OK  
-15V  
Vertical  
Q751  
Horizontal  
Q752  
(R/G/B)  
(R/G/B)  
Check signals of all IC  
and associated cirduits.  
Fig. 11-6  
100  
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QV01 A\V SW  
TA1218N  
A/V UNIT  
MAIN UNIT  
VIDEO1 (V, Y, C, L, R)  
VIDEO2  
V1  
V2  
VIDEO2(Y,L,R or DVD (L,R)  
(V.L.R) or  
DVD (Y.L.R)  
TV2  
DVD (Y,L,R)  
SCL  
SDA  
DVD (Y)  
HY01  
SCL  
DVD (Y, Cr, Cb)  
CVD (Cr, Cb)  
TV1-V, L, R  
TUNER/IF  
SDA  
H003  
DVD IN  
TV1  
TV2-V  
ATF2  
(V.L.R)  
RF  
SW  
SYNC-AV1  
L.R  
MONITOR OUT (V, L, R)  
VARI OUT (L,R)  
Q601  
FRONT  
LAMP  
LA4282  
V3(V.Y.C.L.R)  
PIP-V  
H001  
H002  
FRONT  
SURROUND  
UNIT  
L
TUNER  
SCL SDA  
TUNER  
V-AV  
Y . C  
ATF1 RWL  
L
R
SCLSDA  
V-AV  
Y . C  
QS101  
QS101  
R
L
+
+
R
L
L
+38V  
R
SURROUND  
SW  
R
W(SBS)  
EXT SP (L) FRONT  
EXT SP (R) FRONT  
S601  
EXT  
MUTE  
EXT SP  
FRONT  
QA01  
MICROCOMPUTER  
L
AFT2  
AFT1  
Y S / Y M  
MUTE  
L,  
R
FRONT SP  
OR CENTER SP  
EXT  
SPEAKER  
UNIT  
Q501  
Y . C VIDEO  
INT/EXT  
FRONT  
SYNC-AV1  
Y m / P o w e r o f f  
3D. Y/C  
SEPA.  
UNIT  
INT  
Y
S
I2C STOP  
SCL  
SCL  
SDA  
R
Y
C
Y
R
G
B
SDA  
BUFFER  
Y - I N  
QA02  
SCL  
SDA  
BUFFER  
BUFFER  
SYNC IN  
C-IN  
V.M. COIL  
S.V.M  
UNIT  
V.S.M  
I2C STOP  
DVD SW  
SYNC VCD  
MEMORY  
EEPROM  
24LC088 I/P  
+5V-1  
C
L472 L473 L474  
SCL  
SDA  
0
0
SCL  
SDA  
0
0
V.S.M.  
SYNC OUT  
(R)  
(G)  
(B)  
+125V DRIVE  
Y
Y
I
SW Y Cr Cd  
DVD SW  
UNIT  
SCL  
SDA  
VP  
TMP87CS38N  
-3320  
+12V  
Y
I
Y
I
WAC  
UNIT  
RETURN  
I
ABL  
SCLSDA  
CLK  
V-AV  
Y S  
Q
BLK  
Q
CLK  
Q
Q
OSD/EDS/  
CSP  
Y
HD  
I
Q
HEATER  
+200V  
BLK  
V901  
CS  
BUSY  
DATA  
CS  
BUSY  
ACP  
VIDEO/  
CHROMA  
TA1222AN  
R
G
B
ORT DRIVE  
(RED)  
CC/RGB SW  
UNITCP  
PICTURE  
TUBE (RED)  
Y
I
ZY01 CFM113  
UNIT  
DATA  
SCL  
SDA  
Y
OSD RST  
OSD RST  
Y
Q
30.7kV  
30.7kV  
30.7kV  
KEY  
KEY  
A
B
DUAL  
UNIT  
Y/C  
SEP.  
HD VD  
SUB  
V
OSD Y5  
I
FRONT  
Y
C
OSD  
OSD  
OSD  
SCP  
R
G
B
V902  
Q
UNIT  
C
SCP  
VIDEO  
INPUT  
3
ORT DRIVE  
(GREEN)  
UNIT  
HD  
VD  
Z410  
FUCAS PACK  
R
PICTURE  
TUBE (GREEN)  
H-OUT  
RMT OUT  
RMT  
TO CRT  
Q830  
FRONT  
KEYS  
RESET  
+5V-1  
FOCUS  
(G4)  
G
B
+5V-2  
POWER  
SCP  
SCL  
AUTO LIVE  
UNIT  
R
G
B
V903  
R
G
B
Q831  
TO CRT  
SCREEN  
(G2)  
ORT DRIVE  
(BULE)  
PICTURE  
TUBE (BULE)  
+5V-3  
SDA  
BLK  
FRONT  
UNIT  
UNIT  
DOF  
Eo  
POWER  
SWITCH  
Q832  
+9V-2  
PHOTO  
DIODE  
V
H
REMOTE  
SENSOR  
DEF YORK  
L462, L463, K464  
SUPER LIVE  
Q487, Q488, Q489  
Q751  
RV  
BV  
GV  
H-5  
CORECTION  
BLK  
V-BLK  
DPC  
UNIT  
V-STOP H-BLK  
ABL SELECT  
NORMAL  
CONVER OUTPUT  
AMP  
STB5V  
WF  
CIRCUIT  
STANDBY  
+5V REGU  
DPC WF  
SCL  
Q301  
V-BLK  
VERTICAL  
LA78335  
BLANKING  
OUT  
SDA  
VD  
IN  
+9V  
+35V  
L78MR05  
-27V  
RESET  
T400  
WIDE  
WIDE  
D840  
S1WA20  
T840  
TPW1459AZ  
V-SHIFT  
DIGITAL CONVERGENCE LNIT  
T801  
T802  
Q707  
Q703  
Q715  
Q719  
Q717  
OVER CURRENT  
PROTECT  
F801  
125V7A  
STK392-110  
RH  
LINE  
FILTER  
TRF3205M  
PLL  
HV  
AFC  
F890  
125V5A  
Q862  
QB43 QB30  
L462  
RED  
CONVER  
Y O K E  
POWER1  
UNIT  
10  
HEATER  
Q801  
DAC  
9
4
7
6
5
2
3
1
OVER VOLTAGE  
PROTECT  
+12V  
+38V  
AC120V  
60Hz  
RELAY  
DRIVE  
F860  
125V5A  
+9V-1  
Q420  
RH  
BH  
BH  
GH  
GH  
F889  
125V5A  
+12V  
FOCLS  
+35V  
-27V  
LOW VOLTAGE  
PROTECT  
Q705  
DAC  
L462  
BLUE  
CONVER  
Y O K E  
F870  
250V2A  
+125V  
Z450 CR BLOCK  
TPA5007  
D801  
F851 125V5A  
+125V  
+125V  
Q802  
T888  
HV REGU.  
CIRCUIT  
+30V  
D802-D805  
Z862  
Z801  
ABL  
8
Q755  
Q704  
DAC  
OVER  
VOLTAGE  
PROTECT  
Q483, Q480  
PHOTO COUPLER  
TLP621 (GR-L)  
PROTECTION  
HIC1019  
DIGITAL  
CONNER  
T7064  
Q402  
T461 FBT  
TFB3078AD  
L462  
Q401  
+15V  
-15V  
HOR.  
DRIVE  
+9V  
Q754  
+5V  
Q756  
-9V  
HOR.  
OUT  
GREEN  
CONVER  
Y O K E  
F850  
125V3.15A  
POWER  
RELAY  
SR81  
DC12VTV-8  
POWER  
PROTECT  
Q701  
Q713  
2SC1589  
2SC2253FA  
Q404  
DEF H.V UNIT  
Q752  
RH  
BH  
GH  
AMP  
STK392-110  
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