Texas Instruments Telephone TCM4300 User Manual

Data Manual

1996

Mixed-Signal Products

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TCM4300

Data Manual

Advanced RF Cellular Telephone Interface Circuit

(ARCTIC )

SLWS010F

October 1996

Printed on Recycled Paper

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IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any

semiconductor product or service without notice, and advises its customers to obtain the latest

version of relevant information to verify, before placing orders, that the information being relied

on is current.

TIwarrantsperformanceofitssemiconductorproductsandrelatedsoftwaretothespecifications

applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality

control techniques are utilized to the extent TI deems necessary to support this warranty.

Specific testing of all parameters of each device is not necessarily performed, except those

mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death,

personal injury, or severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES

OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer.

Use of TI products in such applications requires the written approval of an appropriate TI officer.

Questions concerning potential risk applications should be directed to TI through a local SC

sales office.

In order to minimize risks associated with the customer’s applications, adequate design and

operating safeguards should be provided by the customer to minimize inherent or procedural

hazards.

TI assumes no liability for applications assistance, customer product design, software

performance, or infringement of patents or services described herein. Nor does TI warrant or

represent that any license, either express or implied, is granted under any patent right, copyright,

mask work right, or other intellectual property right of TI covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

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Contents

Section

Title

Page

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.2 TCM4300 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

1.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . 2–1

2.2 Dissipation Rating Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.4 Electrical Characteristics Over Full Range Of Operating Conditions . . . . . . . . . . . 2–2

2.4.1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.4.2 Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.4.3 Terminal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) . . . . . . . 2–3

2.4.5 Transmit I and Q Channel Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.4.6 Auxiliary D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.4.7 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT) . . . . . . . . . . . . 2–5

2.4.8 Auxiliary D/A Converters Slope (LCDCONTR) . . . . . . . . . . . . . . . . . . . . . . 2–5

2.4.9 RSSI/Battery A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2.5 Operating Characteristics Over Full Range of Operating Conditions . . . . . . . . . . 2–6

2.5.1 Receive (RX) Channel Frequency Response

(RXI, RXQ Input in Digital Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

2.5.2 Receive (RX) Channel Frequency Response

(FM Input in Analog Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

2.5.3 Transmit (TX) Channel Frequency Response (Digital Mode) . . . . . . . . . . 2–6

2.5.4 Transmit (TX) Channel Frequency Response (Analog Mode) . . . . . . . . . 2–7

Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1 MCLKOUT Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.2 TCM4300 to Microcontroller Interface Timing Requirements

(Mitsubishi Read Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.3 TCM4300 to Microcontroller Interface Timing Requirements

(Mitsubishi Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3.4 TCM4300 to Microcontroller Interface Timing Requirements

(Intel Read Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

3.5 TCM4300 to Microcontroller Interface Timing Requirements

(Intel Write Cycle)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

3.6 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 16-Bit Read Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

3.7 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 16-Bit Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.8 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 8-Bit Read Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

iii

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3.9 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 8-Bit Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) . . . . . . . . . 3–10

3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) . . . . . . . . . 3–11

Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.1 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.2 Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4.3 Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

4.4 Transmit Burst Operation (Digital Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

4.5 Transmit I And Q Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

4.6 Wide-Band Data Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

4.7 Wide-band Data Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4.8 Wide-band Data Demodulator General Information . . . . . . . . . . . . . . . . . . . . . . . . 4–9

4.9 Auxiliary DACs, LCD Contrast Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.10 RSSI, Battery Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.11 Timing And Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4.11.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.11.2 Speech-Codec Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.11.3 Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.11.4 Sample Interrupt SINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

4.11.5 Phase-Adjustment Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

4.12 Frequency Synthesizer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

4.13 Power Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

4.14 Microcontroller-DSP Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4.15 Microcontroller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

4.16 Wide-Band Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

4.17 Microcontroller Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

4.18 LCD Contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

4.19 DSP Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

4.20 Wide-Band Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

4.21 Base Station Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

4.22 DSP Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

4.23 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

4.23.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

4.23.2 Internal Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

4.24 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29

4.24.1 Intel Microcontroller Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29

4.24.2 Mitsubishi Microcontroller Mode of Operation . . . . . . . . . . . . . . . . . . . . . 4–30

4.24.3 Motorola Microcontroller Mode of Operation . . . . . . . . . . . . . . . . . . . . . . 4–30

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

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List of Illustrations

Figure

Title

Page

3–1

3–2

MCLKOUT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Read Cycle, MTS [1:0] = 10) . . . . . . . . . . . . . . . . . . . . . . 3–2

Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Write Cycle, MTS [1:0] = 10) . . . . . . . . . . . . . . . . . . . . . . 3–3

Microcontroller Interface Timing Requirements

(Intel Configuration Read Cycle, MTS [1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Microcontroller Interface Timing Requirements

(Intel Configuration Write Cycle, MTS [1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Microcontroller Interface Timing Requirements

(Motorola 16-Bit Read Cycle, MTS [1:0] = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Microcontroller Interface Timing Requirements

(Motorola 16-Bit Write Cycle, MTS [1:0] = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Microcontroller Interface Timing Requirements

(Motorola 8-Bit Read Cycle, MTS [1:0] = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Microcontroller Interface Timing Requirements

3–3

3–4

3–5

3–6

3–7

3–8

3–9

(Motorola 8-Bit Write Cycle, MTS [1:0] = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

3–10 TCM4300 to DSP Interface (Read Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

3–11 TCM4300 to DSP Interface (Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

4–1

4–2

4–3

4–4

4–5

4–6

4–7

4–8

4–9

Power Ramp-Up/Ramp-Down TIming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Transmit Power Ramp-Up/Ramp-Down Functional Diagram . . . . . . . . . . . . . . . . . 4–7

WBD Manchester-Coded Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

Codec Master and Sample Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Timing and Clock Generation for 38.88-MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

Synthesizer Interface Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16

Contents of SynData Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Example Synthesizer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

Internal and External Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

4–10 Microcontroller-DSP Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

4–11 DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

4–12 Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

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List of Tables

Table

Title

Page

4–1

4–2

4–3

4–4

4–5

4–6

4–7

4–8

4–9

TCM4300 Receive Channel Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

RXIP, RXIN, RXQP, and RXQN Inputs (AV = 3 V, 4.5 V, 5 V) . . . . . . . . . . . . . . 4–2

Receive (RX) Channel Frequency Response (FM Input in Analog Mode) . . . . . . 4–3

Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) . 4–3

Transmit (TX) I and Q Channel Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Transmit (TX) Channel Frequency Response (Digital Mode) . . . . . . . . . . . . . . . . . 4–5

Transmit (TX) Channel Frequency Response (Analog Mode) . . . . . . . . . . . . . . . . 4–5

Typical Bit-Error-Rate Performance (WBD_BW = 000) . . . . . . . . . . . . . . . . . . . . . . 4–8

Bits in Control Register WBDCtrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

4–10 Auxiliary D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

4–11 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT) . . . . . . . . . . . . . . . . . . . 4–10

4–12 Auxiliary D/A Converters Slope (LCDCONTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4–13 RSSI/Battery A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

4–14 Synthesizer Control Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

4–15 External Power Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

4–16 Microcontroller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

4–17 Microcontroller Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

4–18 WBDCtrl Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

4–19 MStatCtrl Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24

4–20 DSP Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

4–21 DSP Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25

4–22 DStatCtrl Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27

4–23 Power-On Reset Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

4–24 Microcontroller Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29

4–25 Microcontroller Interface Connections for Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . 4–29

4–26 Microcontroller Interface Connections for Mitsubishi Mode . . . . . . . . . . . . . . . . . . . 4–30

4–27 Microcontroller Interface Connections for Motorola Mode (8 bits) . . . . . . . . . . . . . 4–30

4–28 Microcontroller Interface Connections for Motorola Mode (16 bits) . . . . . . . . . . . . 4–31

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1 Introduction

Texas Instruments (TI ) TCM4300 IS-54B advanced RF cellular telephone interface circuit (ARCTIC )

provides a baseband interface between the digital signal processor (DSP), the microcontroller, and the RF

modulator/demodulator in a dual-mode IS-54B cellular telephone. See the TCM4300 functional block

diagram.

In the analog mode, the TCM4300 provides all required baseband filtering as well as transmit D/A

conversion and receive A/D conversion using dual 10-bit sigma-delta converters. In addition, a WBD

wide-band data (WBD) –10 kb/s Manchester frequency shift key (FSK) demodulator is provided to allow

reduced DSP processing load during subscriber standby mode.

In the digital mode, the TCM4300 accepts I and Q baseband data and performs A/D and D/A conversion

and square-root raised-cosine filtering using dual 10-bit sigma-delta converters. The TCM4300 also has a

π/4-DQPSK modulation encoder for dibit-to-symbol conversion in the digital transmit mode.

The microcontroller interface is compatible with a wide range of microcontrollers. A microcontroller can be

used to communicate with the user interface (keyboard, display, etc.) and to program up to three frequency

synthesizers by using the on-chip synthesizer interface circuit.

The TCM4300 provides advanced power control to minimize the power consumption of many dual-mode

telephone functional blocks such as the speech codec, FM receiver, I and Q demodulator, transmitter signal

processor, and RF power amplifier. In addition, the TCM4300 is designed to reduce system power

consumption through low-voltage operation and standby mode.

The TCM4300 is offered in the 100-pin PZ package and is characterized for free-air operation from

–40°C to 85°C.

1.1 Features

•

Compliance With TIA IS-54B Dual-Mode Cellular Standard

Baseband Transmit Digital-to-Analog (D/A) Conversion and Receive Analog-to-Digital (A/D)

Conversion in Analog Transmit Mode Using Dual 10-Bit Sigma-Delta Converters

•

Square Root Raised Cosine (SQRC) Filtering in the Digital Mode Using Dual 10-Bit Sigma-Delta

Converters

π/4-Differential Quadrature Phase-Shift Key (DQPSK) Modulation Encoder in Digital Transmit

Mode

Power Control Supervision for Radio Frequency (RF) Power Amplifier, Automatic Frequency

Control (AFC), Automatic Gain Control (AGC), and Synthesizer

•

Received Signal Strength Indicator (RSSI) and Battery-Level A/D Conversion Circuitry

Internal Clock Generation

Wide-Band Data Clock Recovery and Manchester Decoding

General-Purpose Digital Signal Processor (DSP) and Microcontroller Interface

3.3-V and 5-V Operation

Low Power Consumption

TI and ARCTIC are trademarks of Texas Instruments Incorporated.

1–1

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1.2 TCM4300 Functional Block Diagram

Low-

Pass

Filter

Digital Filter

TXIP

TXIN

TXI (04b)

D/A

Analog

Mode (LPF)

π/4 Shifted

DQPSK

Modulation

TX Data

Registers

Low-

Pass

Filter

TXQP

TXQN

Digital

Mode (SQRC)

D/A

TXQ (05b)

ModeSel

Offset

0Fh

10h

DSP

Interface

Anti-

aliasing

Filter

Digital Filter

RXIP

RXIN

RXI 02h

Control

Data

CONTROL

DATA

A/D

Analog

Mode (LPF)

Sample

Address

ADDRESS

Anti-

aliasing

Filter

RXQN

RXQP

Digital

Mode (SQRC)

RXQ 03h

Internal

RESET

Power On

RESET

RSINL

Low-

Pass

Filter

Wide-band

Data

Demodulator

WBD

00h

RSOUTH

RSOUTL

SINT

MCCLK

CSCLK

CMCLK

WBD

Control

01h

00h

Internal

Clocks

AUX

D/As

Clock

Generation

and

XTAL

MCLKIN

MCLKOUT

AGC

AFC

D/A

09h(D)

Clock

Oscillator

38.88MHz

Timing

Adjustment

Logic

0Ah(D)

VCM

Common Mode Input

Control

Registers

Bias

Control

RBIAS

0Bh(D)

PWRCONT

Vref

Ref

Gen

PAEN

OUT1

FMRXEN

IQRXEN

TXEN

VHR

0Ch

DStatCtrl

REFCAP

Power

Control

MWBDFINT

SCEN

0Eh

MStatCtrl

SYNOL

TXONIND

DWBDINT

CINT

DINT

DSP to

Microcontroller

FIFO

06h

01h

06h

01h

Microcontroller

to DSP FIFO

SYNCLK

SYNDTA

Synthesizer

Interface

03h – 09h

SYNLE

[2:0]

Micro-

controller

Interface

RSSI

0Bh

RSSI

BAT

Control

CONTROL

DATA

A/D

D/A

BAT

0Ch

Data

Address

ADDRESS

LCD

0Dh

LCDCONTR

1–2

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1.3 Pin Assignments

PZ PACKAGE

(TOP VIEW)

BAT

RSSI

AV REF

DSPA0

DSPA1

DSPA2

DSPA3

RXQN

RXQP

DSPCSL

DSPRW

DSPSTRBL

MCLKOUT

XTAL

AV RX

RXIN

RXIP

AGC

AFC

AV RX

MCLKIN

VHR

VCM

PWRCONT

TXIP

MCCLK

RSOUTL

RSOUTH

RSINL

MCD7

TXIN

AV TX

MCD6

MCD5

MCD4

MCD3

MCD2

MCD1

MCD0

TXQP

TXQN

AV TX

TXEN

TXONIND

PAEN

1–3

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1.4 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

AFC

NO.

Automatic frequency control. The AFC DAC output provides the means to adjust

system temperature-compensated reference oscillator (TCXO).

AGC

Automatic gain control. The AGC digital-to-analog converter (DAC) output can be

used to control the gain of system receiver circuits.

AV REF

—

Analog supply voltage for FM receive path. Power applied to AV REF powers the

FM receive path circuitry.

AV RX

Analogsupplyvoltageforreceivepath. PowerappliedtoAV RXpowersthereceive

path circuitry.

AV TX

Analog supply voltage for transmit path. Power applied to AV TX powers the

transmit path circuitry.

AV REF

—

Analog ground for REFCAP

Analog ground for receive path

Analog ground for transmit path

AV RX

AV TX

BAT

Battery strength monitor. A sample of the battery voltage is applied to BAT, and this

sample monitors the battery strength.

CINT

Controller data interrupt. CINT is the microcontroller data interrupt (active low) signal

that is sent to the DSP. CINT is caused by a microcontroller write to the Send-C

interrupt register location.

CMCLK

CSCLK

DINT

Codec master clock. CMCLK provides a 2.048-MHz clock that is used as the master

clock and bit clock for the speech codec.

Codec sample clock. CSCLK provides an 8-kHz frame synchronization pulse for the

speech codec. CSCLK is also connected to the DSP for speech sample interrupts.

Microcontroller interrupt request. DINT is output when the DSP writes to the SEND

DINT register location. DINT can be active high or low according to the levels of the

MTS0 and MTS1 signals.

DSPA0

DSPA1

DSPA2

DSPA3

DSPCSL

DSP 4-bit parallel address bus. DSPA0 through DSPA3 provides the address bus for

the DSP interface. DSPA3 is the MSB, and DSPA0 is the LSB.

DSP chip select (active low). A low signal at DSPCSL enables the specific DSP

addressed.

DSPD0

DSPD1

DSPD2

DSPD3

DSPD4

DSPD5

DSPD6

DSPD7

DSPD8

DSPD9

I/O/Z DSP 10-bit parallel data bus. DSPD0 through DSPD9 provide a 10-bit data bus for the

DSP. DSPD9 is the MSB, and DSPD0 is the LSB.

†

Z = high impedance

1–4

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1.4 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

DSPRW

DSP read/write. A high on DSPRW enables a read operation and a low enables

a write operation to the DSP.

DSPSTRBL

DSP strobe low. The DSPSTRL (active low) is used in conjunction with DSPCSL

to enable read/write operations to the DSP.

35, 45, 63,

75, 90

—

Digital power supply. All supply terminals must be connected together.

34, 46, 65,

76, 91

Digital ground. All supply terminals must be connected together.

DWBDINT

DSP wide-band data interrupt (active low). The DWBDINT output goes low to

indicate that the wide-band data (WBD) demodulation circuits have traffic on

them.

Frequency modulation. FM terminal is connected to the output of the FM

discriminator.

FMRXEN

IQRXEN

LCDCONTR

FM receive path enable. A high output from FMRXEN can be used to enable the

power for the receiver FM path.

In-phase and quadrature receive path enable. A high output on IQRXEN can be

used to enable the power for receiver I/Q path.

Liquid-crystal display (LCD) contrast. This LCDCONTR control DAC can be

used to control the amount of drive to the liquid crystal display.

MCLKOUT

MCA0

Master clock out. MCLKOUT is a buffered version of MCLKIN.

Microcontroller 5-bit parallel address bus. MCA0 through MCA4 provide a 5-bit

bus to address the microcontroller. MCA4 is the MSB, and MCA0 is the LSB.

MCA1

MCA2

MCA3

MCA4

MCCLK

Microcontroller clock. MCCLK provides an adjustable frequency with 1.215 MHz

at powerup.

MCCSH

MCCSL

Microcontroller interface chip-select. A high at MCCSH in conjunction with a low

at MCCSL allows the microcontroller to read from or write to the TCM4300.

Microcontroller interface chip-select. A low at MCCSL in conjunction with a high

at the MCCSH allows the microcontroller to read from or write to the TCM4300.

MCD0

MCD1

MCD2

MCD3

MCD4

MCD5

MCD6

MCD7

I/O/Z Microcontroller 8-bit parallel data bus. MCD0 through MCD7 provides an 8-bit

parallel data bus to send/receive data to/from the microcontroller. MCD7 is the

MSB, and MCD0 is the LSB.

†

Z = high impedance

1–5

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1.4 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

MCDS

Microcontroller data strobe. MCDS is configured by the signals present on MTS0 and

MTS1.

MCLKIN

Master clock input. The MCLKIN frequency input requirement is 38.88 MHz ±100 ppm.

A crystal can be connected between MCLKIN and XTAL to provide an oscillator circuit.

As an alternative, XTAL can be left open and an external TTL/CMOS-level clock signal

can be connected to MCLKIN.

MCRW

MTS0

Microcontroller read/write. Microcontroller read/write operations are selected in

accordance with the signals present on MTS0 and MTS1.

Microcontroller type select configuration-control inputs. The interface is controlled by

MTS (1:0) as follows:

00 – Intel microcontroller interface characteristics

10 – Mitsubishi and Motorola microcontroller 16-bit bus interface characteristics

01 – Motorola microcontroller 8-bit bus characteristics

11 – Reserved

MTS1

MWBDFINT

Microcontroller interrupt request. A wide-band data-ready interrupt is output when the

WBD demodulator is in analog mode or when a frame interrupt is sent by the DSP in

digital mode. MWDBFINT can be active high or low according to the levels of the MTS0

and MTS1 signals.

OUT1

PAEN

Output number 1. OUT1 provides a user-defined general purpose data or control signal.

Power amplifier enable. PAEN can be used to enable the transmit power amplifier. This

signal is active high.

PWRCONT

RBIAS

Power amplifier (PA) power control. The PWRCONT DAC output can be used to control

the amount of power output from the PA.

Input for bias current-setting resistor. To achieve correct bias voltage, a 100-kΩ, 1%

tolerance resistor connected between RBIAS and AV

is recommended.

REFCAP

100

Reference decoupling capacitor. For proper decoupling, It is recommended that a

3.3 µFcapacitorinparallelwitha470-pFcapacitorbeconnectedbetweenREFCAPand

ground.

RSINL

RSSI

Reset input low. An active low applied to RSINL resets the TCM4300.

Received signal strength indicator. RSSI samples received signal strength.

RSOUTH

Reset out high. An active high is output from RSOUTH for 10 ms after the TCM4300 is

powered up.

RSOUTL

RXIN

Reset out low. An active low is output from RSOUTL for 10 ms after the TCM4300 is

powered up.

Negative receive input. The in-phase differential negative baseband received signal is

applied to RXIN.

RXIP

Positive receive input. The in-phase differential positive baseband received signal is

applied to RXIP.

RXQN

RXQP

Negative receive input. The quadrature negative baseband received signal is applied

to RXQN.

Positive receive input. The quadrature differential positive baseband received signal is

applied to RXQP.

Intel is a trademark of Intel Corporation.

Mitsubishi is a trademark of Mitsubishi Inc.

Motorola is a trademark of Motorola, Inc.

1–6

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1.4 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

SCEN

Speech CODEC enable. A high out from SCEN can enable the speech CODEC.

SINT

Sample interrupt. SINT is active low. In the analog mode, SINT occurs at 40 kHz; in the

digital mode, SINT occurs at 48.6 kHz.

SYNCLK

SYNDTA

SYNLE0

SYNLE1

SYNLE2

SYNOL

TXEN

Synthesizer clock. SYNCLK clocks the serial data stream.

Synthesizer serial-data. SYNDTA provides the serial bit stream output.

Synthesizer 0, 1, and 2 latch enables. An active high on SYNLE0, SYNLE1, and

SYNLE2 indicates that the latch is enabled.

Synthesizer out-of-lock. An active high at SYNOL indicates a synthesizer is not locked.

Transmit power enable. An active high output from TXEN can be used to enable various

system transmitter-circuit devices.

TXIN

In-phase differential negative baseband transmit. The negative component of the

differential baseband transmit signal is output from TXIN.

TXIP

In-phase differential positive baseband transmit. The positive component of the

differential baseband transmit signal is output from TXIP.

TXONIND

TXQN

TXQP

VCM

Transmit on indicator. A signal is applied to TXONIND to indicate that power is applied

to the power amplifier.

Quadrature differential negative baseband transmit. The negative component of the

quadrature differential transmit signal is output from TXQN.

Quadrature differential positive baseband transmit. The positive component of the

quadrature differential transmit signal is output from TXQP.

Voltagecommonmode. VCMestablishesthedcoperatingpointfortransmitoutputsand

can be tied to VHR.

VHR

Voltage half-rail. The voltage level at VHR is approximately 0.5 × AV . VHR

establishes the dc operating point for receive inputs.

XTAL

13, 97

—

Substrate ground

Crystal input. A crystal connected between XTAL and MCLIN forms an oscillator circuit.

1–7

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2 Electrical Specifications

This section lists the electrical specifications, the absolute maximum ratings, the recommended operating

conditions and operating characteristics for the TCM4300 Advanced RF Cellular Telephone Interface

Circuit.

2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

†

(unless otherwise noted)

Supply voltage range:

(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . .

(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . V –0.3 V to DV

–0.3 V to AV

+0.3 V

Input voltage range, V : Digital signals . . . . . . . . . . . . . . . . . V –0.3 V to DV

Analog signals . . . . . . . . . . . . . . . .

–0.3 V to AV

Output voltage range, V : Digital signals . . . . . . . . . . . . . . . . . . . . . . . . . . . V to DV

Analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . .

to AV

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated

under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect DV

2. Maximum supplied voltage should not exceed 6 V.

3. Voltage values are with respect to AV

2.2 Dissipation Rating Table

≤ 25°C

DERATING FACTOR

= 85°C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING

1530 mW

15.25 mW/°C

615 mW

2–1

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2.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Supply voltage, DV

5.5

High-level input voltage, V

Digital

0.7 DV

DV +0.3

Low-level input voltage, V

High-level output voltage, V

0.3 DV

0.7 DV

0.5

Low-level output voltage, V

High-level output current at 3 V, I

Low-level output current at 3 V, I

High-level output current at 5 V, I

Low-level output current at 5 V, I

Load capacitance, transmit I and Q channel outputs

VCM input voltage range, transmit I and Q channel outputs

Load resistance, auxiliary DACs

1.3

AV –1.3

kΩ

°C

Load capacitance, auxiliary DACs

Operating free-air temperature, T

–40

2.4 Electrical Characteristics Over Full Range Of Operating Conditions (Unless

Otherwise Noted)

2.4.1

Power Consumption

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

= 3 V,

= 3 V

250

Analog transmitting and receiving

Digital receiving

= 5.5 V,

= 3 V,

= 5.5 V

= 3 V

275

= 5.5 V,

= 3 V,

= 5.5 V

= 3 V

225

250

Digital transmitting

= 5.5 V,

= 3 V,

= 5.5 V

= 3 V

210

250

MCLKOUT enabled

MCLKOUT disabled

MCLKOUT enabled

MCLKOUT disabled

= 3 V,

= 3 V

Idle mode

= 5.5 V,

= 3 V,

= 5.5 V

= 3 V

150

160

Digital mode, 1/3 transmitting +1/3 receiving

+ 1/3 standby

= 5.5 V,

= 5.5 V

205

220

†

All typical values are at T = 25°C.

2.4.2

Reference Characteristics

‡

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

High-level output voltage

0.5 AV –0.2

0.5 AV +0.2

OH(VHR)

FMVOX or IQRXEN

or TXEN = high

100

Ω

Output resistance

FMVOX or IQRXEN

or TXEN = low

kΩ

‡

All typical values are at DV

= 5 V, AV

= 5 V, and T = 25°C

2–2

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2.4.3

Terminal Impedance

†

FUNCTION

MIN TYP

MAX

UNIT

kΩ

Receive channel input impedance (single ended), RXIP/N and RXQP/N

Transmit channel output impedance (single ended), TXIP/N and TXQP/N

FM input impedance, WBD

100

Ω

200

240

180

kΩ

MCLKOUT at 3.3 V

MCLKOUT impedance

Ω

MCLKOUT at 5 V

†

All typical values are at DV

= 5 V, AV

= 5 V, and T = 25°C, unless otherwise specified.

2.4.4

RXIP, RXIN, RXQP, and RXQN Inputs (AV

= 3 V, 4.5 V, 5 V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range

0.3

AV –0.3

Differential

0.5

Input voltage for full-

scale digital output

Vp-p

Single ended

Differential

0.125

Nominal operating

level

‡

Vp-p

Single ended

Input CMRR (RXI, RXQ)

Sampling frequency, SINT (digital

mode)

48.6

kHz

Sampling frequency, SINT (analog

mode)

kHz

Receive error vector magnitude (EVM)

I/Q sample timing skew

Input signal 0 – 15 kHz

bits

A/D resolution

Signal to noise-plus distortion

Integral nonlinearity

Input at full scale – 1 dB

0 dB to –60 dB input

LSB

Gain error (I or Q channel)

Gain mismatch between I and Q

Differential dc offset voltage

FM input sensitivity, full scale

±7%

±0.3

±30

2.5

Vp-p

(

14 kHz deviation)

FM input dc offset (relative to VHR)

±80

–50

FM input idle channel noise, below

full-scale input

FM gain error

±6%

Power supply rejection

f = 0 kHz to 15 kHz

‡

Provides 12 dB headroom for AGC fading conditions.

2–3

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2.4.5

Transmit I and Q Channel Outputs

PARAMETER

MIN

TYP

2.24

1.12

1.5

MAX

UNIT

Differential

Peak output voltage full scale, centered at VCM

Single ended

Differential

Nominal output-level (constellation radius) centered

at VCM

Single ended

0.75

±200

Low-level drift

PPM/°C

Transmit error vector magnitude (EVM)

Resolution

bits

S/(N+D) ratio at differential outputs

Gain error (I or Q channel)

±8%

±12%

Gain mismatch between I and Q

Gain sampling mismatch between I and Q

Zero code error differential

±0.3

±80

Zero code error, each output, with respect to VCM

±80

Zero code error, I to Q, with respect to other channel (differential or

single ended)

±10

Load impedance, between P and N terminals

Transmit offset DACs I and Q resolution

kΩ

bits

LSB

3.4

Transmit offset DACs I and Q average step size

Transmit offset DACs I and Q full-scale positive output

Transmit offset DACs I and Q full-scale negative output

Transmit offset DACs differential nonlinearity

Transmit offset DACs integral nonlinearity

2.9

3.9

105.4

–108.8

±1.1

2.4.6

Auxiliary D/A Converters

PARAMETER

TEST CONDITIONS

MIN

0.2

TYP

MAX

2.5

UNIT

†

> 3 V ,

AUXFS [1:0] = 00

†

Output range

> 4.5 V , AUXFS [1:0] = 10

†

> 5 V ,

AUXFS [1:0] = 11

4.5

Resolution AGC, AFC, PWRCONT

DACs

bits

Resolution LCDCONTR DAC

Gain + offset error (full scale) AGC,

AFC, PWRCONT DAC

±3%

Gain + offset error (full scale)

LCDCONTR DAC

±7%

Differential nonlinearity

Integral nonlinearity

±0.75

±1

LSB

±1

†

Range settings depends only on AUXFS [1:0]. The supply voltage is not detected.

2–4

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2.4.7

Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT)

NOMINAL OUTPUT VOLTAGE

NOMINAL LSB

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 256†

(MAX VALUE)

AUXFS[1:0]

SETTING

FOR DIGITAL CODE = 128

SLOPE

VALUE

(V)

(MIDRANGE)

(V)

2.5/256

Do not use

4/256

0.0098

Do not use

0.0156

1.25

Do not use

2.5

Do not use

4.5/256

0.0176

2.25

4.5

†

The maximum input code is 255. The value shown for 256 is extrapolated.

2.4.8

Auxiliary D/A Converters Slope (LCDCONTR)

NOMINAL OUTPUT VOLT-

AGE FOR DIGITAL CODE = 8

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 16

NOMINAL LSB

VALUE

AUXFS[1:0]

SETTING

SLOPE

(MIDRANGE)

(V)

(MAX VALUE)

(V)

2.5/16

Do not use

4/16

0.1563

Do not use

0.2500

1.25

Do not use

2.5

Do not use

4.5/16

0.2813

2.25

4.5

‡

The maximum input code is 15. The value shown for 16 is extrapolated.

2.4.9

RSSI/Battery A/D Converter

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input range

= 3 V, 4.5 V, 5 V

0.2

Resolution

bits

µs

Conversion time

= 3 V, 4.5 V, 5 V

Gain + offset error (full scale)

Differential nonlinearity

Integral nonlinearity

Input resistance

±3%

±0.75

±4%

±1

LSB

MΩ

±1

2–5

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2.5 Operating Characteristics Over Full Range of Operating Conditions

(Unless Otherwise Noted)

2.5.1

Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.125 V peak-to-peak, 0 kHz to 8 kHz (see Note 4)

0.125 V peak-to-peak, 8 kHz to 15 kHz (see Note 5)

0.125 V peak-to-peak, 16.2 kHz to 18 kHz (see Note 5)

0.125 V peak-to-peak, 18 kHz to 45 kHz (see Note 5)

0.125 V peak-to-peak, 45 kHz to 75 kHz (see Note 5)

0.125 V peak-to-peak, > 75 kHz

±0.5 ±0.75

±1

–26

–30

–46

–60

Frequency

response

Peak-to-peak

group delay

distortion

0.125 V peak-to-peak, 0 kHz to 15 kHz

µs

Absolute channel

delay, RXI, Q IN to 0.125 V peak-to-peak, 0 kHz to 15 kHz

digital OUT

325

µs

NOTES: 4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response

5. Stopband

2.5.2

Receive (RX) Channel Frequency Response (FM Input in Analog Mode)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.5 V peak-to-peak, 0 kHz to 6 kHz (see Note 6)

2.5 V peak-to-peak, 20 kHz to 30 kHz (see Note 5)

2.5 V peak-to-peak, 34 kHz to 46 kHz (see Note 7)

±0.5

Frequency response

–18

–48

Peak-to-peak group

delay distortion

2.5 V peak-to-peak, 0 kHz to 6 kHz

µs

Absolute channel delay 2.5 V peak-to-peak, 0 kHz to 6 kHz

400

µs

NOTES: 5. Stopband

6. Ripple magnitude

7. Stopband and multiples of stopband

2.5.3

Transmit (TX) Channel Frequency Response (Digital Mode)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

±0.3

±0.5

UNIT

0 kHz to 8 kHz (see Note 4)

8 kHz to 15 kHz (see Note 4)

20 kHz to 45 kHz (see Note 5)

45 kHz to 75 kHz (see Note 5)

> 75 kHz (see Note 5)

–29

–55

–60

Frequency response

Any 30 kHz band centered at > 90 kHz (see Note 5)

Peak-to-peak group

delay distortion

0 kHz to 15 kHz

µs

Absolute channel delay

0 kHz to 15 kHz

320

µs

NOTES: 4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response

5. Stopband

2–6

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2.5.4

Transmit (TX) Channel Frequency Response (Analog Mode)

PARAMETER

TEST CONDITIONS

0 kHz to 8 kHz (see Note 4)

MIN

TYP

MAX

±0.5

UNIT

8 kHz to 15 kHz (see Note 4)

20 kHz to 45 kHz (see Note 5)

45 kHz to 75 kHz (see Note 5)

> 75 kHz (see Note 5)

–31

–70

Frequency response

Any 30 kHz band centered at > 90 kHz (see Note 5)

Peak-to-peak group

delay distortion

0 kHz to 15 kHz

µs

Absolute channel delay

0 kHz to 15 kHz

540

µs

NOTES: 4. Ripple magnitude

5. Stopband

2–7

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2–8

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3 Parameter Measurement Information

This section contains the timing waveforms and parameter values for MCLKOUT and several

microcontroller interface configurations possible when using the TCM4300. The timing parameters are

contained in Section 3.1 through Section 3.11. The timing waveforms are shown in Figures 3–1 through

3–11. All parameters shown in the separate waveforms have their values listed in an associated table. Not

all parameter values listed in the tables are necessarily shown in an associated waveform.

3.1 MCLKOUT Timing Requirements (see Figure 3–1 and Note 1)

MIN NOM

MAX

UNIT

Pulse duration , MCLKOUT high

Pulse duration, MCLKOUT low

Rise time, MCLKOUT

Fall time, MCLKOUT

NOTE 1: Tested with 15 pF loading on MCLKOUT

MCLKOUT

Figure 3–1. MCLKOUT Timing Diagram

3–1

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3.2 TCM4300 to Microcontroller Interface Timing Requirements (Mitsubishi

Read Cycle) (see Figure 3–2 and Note 2)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write MCRW stable before falling edge of

strobe MCDS

TRW

su(R/W)

h(R/W)

su(RA)

h(RA)

(SU)

(HO)

(SU)

(HO)

(EN)

Hold time, read/write MCRW stable after rising edge of

strobe MCDS

Setup time, read address MCS stable before falling edge of

strobe MCDS

TRA

TRD

Hold time, read address MCA stable after rising edge of

strobe MCDS

Enable time, read data on falling edge of strobe MCDS to

TCM4300 driving data bus MCD

en(RD)

Read data valid time on falling edge of strobe MCDS to

valid data MCD

v(R)

(DV)

(INV)

(DIS)

Data MCD invalid after rising edge of strobe MCDS

TRD

inv

Disable time, read data. TCM4300 releases MCD data bus

after rising edge of strobe MCDS

dis(RD)

Hold time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCDS

TCS

h(CS)

(HO)

Setup time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCDS

TCS

su(CS)

(SU)

NOTE 2: Timings are based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

90%

10%

90%

10%

MCDS

(see Note A)

su(R/W)

h(R/W)

90%

MCRW

su(RA)

h(RA)

MCA4–MCA0

v(R)

dis(RD)

inv

en(RD)

MCD7–MCD0

MCCSH

90%

10%

su(CS)

h(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–2. Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Read Cycle, MTS [1:0] = 10)

3–2

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3.3 TCM4300 to Microcontroller Interface Timing Requirements (Mitsubishi

Write Cycle) (see Figure 3–3 and Note 2)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write MCRW stable before falling edge of

strobe MCDS

TRW

TWA

TWD

su(R/W)

h(R/W)

su(WA)

h(WA)

(SU)

(HO)

(SU)

(HO)

(SU)

Hold time, read/write MCRW stable after rising edge of

strobe MCDS

Setup time, write/address MCA stable before falling edge

of strobe MCDS

Hold time, write address MCA stable after rising edge of

strobe MCDS

Setup time, write data stable MCD before rising edge of

strobe MCDS

su(W)

Hold time, write data stable MCD after rising edge of strobe

MCDS

h(W)

(HO)

(STB)

(HO)

Pulse duration, write strobe pulse width low on MCDS

TWR

TCS

w(WSTB)

h(CS)

Hold time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCDS

Setup time, chip select stable MCCSH and MCCSL before

falling edge of strobe MCDS

TCS

(SU)

su(CS)

NOTE 2: Timings based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

w(WSTB)

90%

MCDS

(see Note A)

10%

h(R/W)

su(R/W)

MCRW

10%

su(WA)

MCA4–MCA0

su(W)

h(W)

MCD7–MCD0

MCCSH

90%

h(CS)

su(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–3. Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Write Cycle, MTS [1:0] = 10)

3–3

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3.4 TCM4300 to Microcontroller Interface Timing Requirements (Intel Read

Cycle) (see Figure 3–4 and Note 3)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read address MCA stable before falling edge of

strobe MCDS

TRA

TRD

su(RA)

(SU)

(HO)

(EN)

Hold time, read address MCA stable after rising edge of

strobe MCDS

h(RA)

Enable time, read data on falling edge of strobe MCDS to

TCM4300 driving data bus MCD

en(RD)

Valid time, read data on falling edge of strobe MCDS to

valid data MCD

v(RD)

(DV)

(INV)

(DIS)

Data MCD invalid after rising edge of strobe MCDS

TRD

inv

Disable time, read data. TCM4300 releases MCD data bus

after rising edge of strobe MCDS

dis(RD)

Setup time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCDS

TCS

su(CS)

h(CS)

(SU)

(HO)

Hold time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCDS

TCS

NOTE 3: Timings are based upon Intel 80C186 (16 MHz).

90%

10%

90%

MCDS

(see Note A)

10%

MCRW

su(RA)

h(RA)

MCA4–MCA0

v(RD)

dis(RD)

inv

en(RD)

MCD7–MCD0

MCCSH

90%

10%

h(CS)

su(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–4. Microcontroller Interface Timing Requirements

(Intel Configuration Read Cycle, MTS [1:0] = 00)

3–4

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3.5 TCM4300 to Microcontroller Interface Timing Requirements (Intel Write

Cycle) (see Figure 3–5 and Note 3)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, write address MCA stable before falling edge

of strobe MCRW

TWA

TWD

su(WA)

h(WA)

su(W)

(SU)

(HO)

(SU)

Hold time, write address MCA stable after rising edge of

strobe MCRW

Setup time, write data stable MCD before rising edge of

strobe MCRW

Hold time, write data stable MCD after rising edge of

strobe MCRW

h(W)

(HO)

Pulse duration, write strobe pulse width low on MCRW

TWR

(STB)

w(WSTB)

su(CS)

Setup time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCRW

TCS

(SU)

(HO)

Hold time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCRW

TCS

h(CS)

NOTE 3: Timings are based upon Intel 8C186 (16 MHz).

MCDS

w(WSTB)

90%

MCRW

(see Note A)

10%

h(WA)

su(WA)

MCA4–MCA0

su(W)

h(W)

MCD7–MCD0

MCCSH

90%

h(CS)

su(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCRW active.

Figure 3–5. Microcontroller Interface Timing Requirements

(Intel Configuration Write Cycle, MTS [1:0] = 00)

3–5

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3.6 TCM4300 to Microcontroller Interface Timing Requirements (Motorola

16-Bit Read Cycle) (see Figure 3–6 and Note 4)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write MCRW stable before falling edge of

strobe MCDS

TRW

su(R/W)

h(R/W)

su(RA)

h(RA)

(SU)

(HO)

(SU)

(HO)

(EN)

Hold time, read/write MCRW stable after rising edge of

strobe MCDS

Setup time, read address MCA stable before falling edge of

strobe MCDS

TRA

TRD

Hold time, read address MCA stable after rising edge of

strobe MCDS

Enable time, read data on falling edge of strobe MCDS to

TCM4300 driving data bus MCD

en(RD)

Valid time, read data on falling edge of strobe MCDS to

valid data MCD

v(RD)

(DV)

(INV)

(DIS)

Data (MCD) invalid after rising edge of strobe MCDS

TRD

inv

Disable time, read data. TCM4300 releases MCD data bus

after rising edge of strobe MCDS

dis(RD)

Hold time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCDS

TCS

h(CS)

(HO)

Setup time, chip select stable MCCSH and MCCSL before

rising edge of strobe MCDS

TCS

(SU)

su(CS)

NOTE 4: Timings are based upon Motorola 68HC000 (16.67 MHz) and Motorola 68302 (16 MHz).

90%

10%

90%

10%

MCDS

(see Note A)

h(R/W)

90%

su(R/W)

90%

MCRW

su(RA)

h(RA)

MCA0–MCA4

dis(RD)

v(RD)

en(RD)

inv

MCD0–MCD7

MCCSH

90%

10%

su(CS)

h(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–6. Microcontroller Interface Timing Requirements

(Motorola 16-Bit Read Cycle, MTS [1:0] = 10)

3–6

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3.7 TCM4300 to Microcontroller Interface Timing Requirements (Motorola

16-Bit Write Cycle) (see Figure 3–7 and Note 4)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write MCRW stable before falling edge of

strobe MCDS

TRW

TWA

TWD

su(R/W)

h(R/W)

su(WA)

h(WA)

(SU)

(HO)

(SU)

(HO)

(SU)

Hold time, read/write MCRW stable after rising edge of

strobe MCDS

Setup time, write address MCA stable before falling edge

of strobe MCDS

Hold time, write address MCA stable after rising edge of

strobe MCDS

Setup time, write data stable MCD before rising edge of

strobe MCDS

su(W)

Hold time, write data stable MCD after rising edge of strobe

MCDS

h(W)

(HO)

(STB)

(HO)

Pulse duration, write strobe pulse width low on MCDS

TWR

TCS

w(WSTB)

h(CS)

Hold time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCDS

Setup time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCDS

TCS

(SU)

su(CS)

NOTE 4: Timings are based upon Motorola 68HC000 (16.67 MHz) and Motorola 68302 (16 MHz).

w(WSTB)

90%

MCDS

10%

(see Note A)

h(R/W)

su(R/W)

MCRW

10%

h(WA)

su(WA)

MCA0–MCA4

su(W)

h(W)

MCD0–MCD7

MCCSH

90%

h(CS)

su(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–7. Microcontroller Interface Timing Requirements

(Motorola 16-Bit Write Cycle, MTS [1:0] = 10)

3–7

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3.8 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit

Read Cycle) (see Figure 3–8 and Note 5)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write MCRW stable before rising edge of

strobe MCDS

TRW

su(R/W)

h(R/W)

su(RA)

h(RA)

(SU)

(HO)

(SU)

(HO)

(EN)

Hold time, read/write MCRW stable after falling edge of

strobe MCDS

TRW

Setup time, read address MCA stable before rising edge of

strobe MCDS

TRA

TRD

Hold time, read address MCA stable after falling edge of

strobe MCDS

Enable time, read data on rising edge of strobe MCDS to

TCM4300 driving data bus MCD

en(RD)

Valid time, read data on rising edge of strobe MCDS to valid

data MCD

v(RD)

(DV)

(INV)

(DIS)

Data MCD invalid after falling edge of strobe MCDS

TRD

inv

Disable time, read data. TCM4300 releases MDS data bus

after falling edge of strobe MCDS

dis(RD)

Hold time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCDS

TCS

h(CS)

(HO)

Setup time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCDS

TCS

(SU)

su(CS)

NOTE 5: Timings are based upon Motorola 68HC11D3 (3 MHz) and Motorola 68HC11G5 (2.1 MHz).

90%

MCDS

(see Note A)

10%

su(R/W)

90%

h(R/W)

90%

MCRW

su(RA)

h(RA)

MCA0–MCA4

v(RD)

dis(RD)

inv

en(RD)

MCD0–MCD7

MCCSH

90%

10%

su(CS)

h(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–8. Microcontroller Interface Timing Requirements

(Motorola 8-Bit Read Cycle, MTS [1:0] = 01)

3–8

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3.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit

Write Cycle) (see Figure 3–9 and Note 5)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write MCRW stable before rising edge of

strobe MCDS

TRW

TWA

TWD

su(R/W)

h(R/W)

su(WA)

h(WA)

(SU)

(HO)

(SU)

(HO)

(SU)

Hold time, read/write MCRW stable after falling edge of

strobe MCDS

Setup time, write address MCA stable before rising edge of

strobe MCDS

Hold time, write address MCA stable after falling edge of

strobe MCDS

Setup time, write data stable MCD before falling edge of

strobe MCDS

su(W)

Hold time, write data stable MCD after falling edge of

strobe MCDS

h(W)

(HO)

(STB)

(HO)

Pulse duration, write strobe pulse width high on MCDS

TWR

TCS

w(WSTB)

h(CS)

Hold time, chip select MCCSH and MCCSL stable before

rising edge of strobe MCDS

Setup time, chip select MCCSH and MCCSL stable before

falling edge of strobe MCDS

TCS

(SU)

su(CS)

NOTE 5: Timings are based upon Motorola 68HC11D3 (3 MHz) and Motorola 68HC11G5 (2.1 MHz).

w(WSTB)

MCDS

(see Note A)

90%

10%

su(R/W)

h(R/W)

MCRW

10%

h(WA)

su(WA)

MCA0–MCA4

su(W)

h(W)

MCD0–MCD7

MCCSH

90%

h(CS)

su(CS)

MCCSL

10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3–9. Microcontroller Interface Timing Requirements

(Motorola 8-Bit Write Cycle, MTS [1:0] = 01)

3–9

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3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) (see

Figure 3–10)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write DSPRW stable before falling edge of

strobe DSPSTRBL

TRW

su(R/W)

h(R/W)

su(CS)

h(CS)

su(RA)

h(RA)

en(R)

(SU)

(HO)

(SU)

(HO)

Hold time, read/write DSPRW stable after rising edge of

strobe DSPSTRBL

TRW

Setup time, chip select stable DSPCSL before falling edge

of strobe DSPSTRBL

TCS

Hold time, chip select DSPCSL stable after rising edge of

strobe DSPSTRBL

Setup time, read address DSPA stable before strobe

DSPSTRBL goes low

TWA

TRD

(SU)

(HO)

(EN)

(DV)

(INV)

(DIS)

Hold time, read address DSPA stable after strobe

DSPSTRBL goes high

Enable time, read data on falling edge of strobe DSPSTRBL

to TCM4300 driving data bus DSPD

Delay read data valid time on falling edge of strobe

DSPSTRBL to valid data DSPD

d(DV)

h(R)

Hold time, read data DSPD invalid after rising edge of

strobe DSPSTRBL

TRD

Disable time, read data. TCM4300 releases data bus after

rising edge of strobe DSPSTRBL

dis(R)

DSPCSL

10%

h(CS)

su(CS)

90%

10%

90%

10%

DSPSTRBL

DSPRW

h(R/W)

su(R/W)

90%

su(RA)

h(RA)

DSPA

DSPD

h(R)

en(R)

dis(R)

d(DV)

Figure 3–10. TCM4300 to DSP Interface (Read Cycle)

3–10

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3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) (see

Figure 3–11)

ALTERNATE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write DSPRW stable before falling edge of

strobe DSPSTRBL

TRW

su(R/W)

h(R/W)

su(CS)

h(CS)

(SU)

(HO)

(SU)

(HO)

Hold time, read/write DSPRW stable after rising edge of

strobe DSPSTRBL

TRW

Setup time, chip select stable DSPCSL before falling edge

of strobe DSPSTRBL

TCS

Hold time, chip select DSPCSL stable after rising edge of

strobe DSPSTRBL

Setup time, write address DSPA stable before falling edge

of strobe DSPSTRBL

TWA

TWD

su(WA)

h(WA)

su(W)

(SU)

(HO)

(SU)

Hold time, write address DSPA stable after rising edge of

strobe DSPSTRBL

Setup time, write data stable DSPD before rising edge of

strobe DSPSTRBL

Hold time, write data stable DSPD after rising edge of

strobe DSPSTRBL

h(W)

(HO)

Pulse duration, write strobe pulse width low on DSPSTRBL

TWR

w(WSTB)

(STB)

DSPCSL

10%

su(CS)

h(CS)

w(WSTB)

90%

10%

DSPSTRBL

10%

su(R/W)

h(R/W)

DSPRW

su(WA)

h(WA)

DSPA

DSPD

su(W)

h(W)

Figure 3–11. TCM4300 to DSP Interface (Write Cycle)

3–11

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3–12

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4 Principles of Operation

This section describes the operation of the TCM4300 in detail.

NOTE:

Timing diagrams and associated tables are contained in Section 3 of this data

manual.

4.1 Data Transfer

The interface to both the system digital signal processor and microcontroller is in the form of 2s complement.

4.2 Receive Section

The mode of operation is determined by the state of the MODE, FMVOX, IQRXEN, and FMRXEN bits of

the DStatCtrl register, as shown in Table 4–1.

Table 4–1. TCM4300 Receive Channel Control Signals

CONTROL SIGNAL

MODE

ANALOG MODE

DIGITAL MODE

FMVOX

IQRXEN

FMRXEN

In the digital mode (MODE=1), the receive section accepts RXIP, RXIN, RXQP, and RXQN analog inputs.

These inputs are passed to continuous-time antialiasing filters (AAF), baseband filtering, and A/D

conversion blocks, and then to sample registers where 10-bit registers can be read. The sample rate is

48.6 ksps.

In the analog mode (MODE = 0), the FMVOX bit of the DStatCtrl register enables or disables the Q side of

the receiver channel, and the FMRXEN bit controls the external functions. In the digital mode, IQRXEN

enables both the I and Q receive channels and external functions as well.

To save power, the receive I and Q channels are enabled separately. This operation occurs because in the

analog mode, only the Q channel is used. When the FMVOX bit is set to 1, it controls the input multiplexer,

connectstheFMinputtothereceiverRXQPsignal, andconnectstheRXQNsignaltoVHR. WhentheMODE

control bit and the IQRXEN control bit are set to 1, both sides of the receive channel are enabled for use

in the digital mode.

The input signals RXIP, RXIN and RXQP, RXQN are differential pair signals (see Table 4–2). Differential

signals are used to minimize the pickup of interference, ground, and supply noise, while maintaining a larger

signal level. In single-ended applications, the unused RXIN and RXQN terminals must be connected to VHR

or to an externally supplied bias voltage equal to the dc value of the input signal, and the input signal level

must be adjusted in the RF circuitry to provide the proper signal level so that the digital output codes are

properly calibrated (0.5 V peak-to-peak corresponds to full-scale digital output). In the analog mode, the

RXQN input is internally referenced to VHR. Alternatively, the unused inputs can be connected to VHR and

the used inputs can be capacitively coupled. Note that when the RX and FM inputs are capacitively coupled,

it is recommended that the input terminals be connected to VHR using a bias resistor.

4–1

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Table 4–2. RXIP, RXIN, RXQP, and RXQN Inputs (AV

= 3 V, 4.5 V, 5 V)

PARAMETER

Input voltage range

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.3

AV –0.3

Differential

0.5

Input voltage for full- scale

digital output

Vp-p

Single ended

Differential

0.125

†

Vp-p

Nominal operating level

Input CMRR (RXI, RXQ)

Single ended

Sampling frequency, SINT (digital mode)

Sampling frequency, SINT (analog mode)

Receive error vector magnitude (EVM)

I/Q sample timing skew

48.6

kHz

Input signal 0 – 15 kHz

Bits

A/D resolution

Signal to noise-plus distortion

Integral nonlinearity

Input at full scale – 1 dB

0 dB to –60 dB input

LSB

Gain error (I or Q channel)

±7%

±0.3

±30

Gain mismatch between I and Q

Differential dc offset voltage

FM input sensitivity, for full scale (±14 kHz

2.5

Vp-p

deviation)

FM input dc offset (wrt VHR)

±80

–50

FM input idle channel noise, below full scale

input

FM gain error

±6%

Power supply rejection

f = 0 kHz to 15 kHz

†

Provides 12 dB headroom for AGC fading conditions.

It is recommended that the single-ended output of an external FM discriminator be capacitively coupled to

the FM terminal for analog mode voice and WBD reception. An external bias resistor is needed to bias the

FMterminaltoVHR. ThesignalatthisterminalisconveyedtotheQsideofthereceiverusingthemultiplexer,

and the other Q input is connected internally to the VHR reference voltage. The I input of the receive section

circuitry is disabled in the analog mode. The FM signal passes through the antialiasing filter, as specified

in Table 4–3, before passing through the A/D converter. The signal at the FM terminal is also routed directly

to the WBD demodulator through a low-pass filter (LPF) with the –3 dB point at 270 kHz.

4–2

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Table 4–3. Receive (RX) Channel Frequency Response (FM Input in Analog Mode)

PARAMETER

TEST CONDITIONS

0 kHz to 6 kHz (see Note 1)

MIN

TYP

MAX

UNIT

±0.5

Frequency response

2.5 V peak-to-peak

20 kHz to 30 kHz (see Note 2)

34 kHz to 46 kHz (see Note 3)

–18

–48

Peak-to-peak group

delay distortion

2.5 V peak-to-peak, 0 kHz to 6 kHz

µs

Absolute channel delay 2.5 V peak-to-peak, 0 kHz to 6 kHz

400

µs

NOTES: 1. Ripple magnitude

2. Stopband

3. Stopband and multiples of stopband

The VHR can provide a bias voltage for the received inputs when capacitively coupled from the RF section.

To meet noise requirements, the VHR output should have an external decoupling capacitor connected to

ground. The VHR output buffer is enabled by the OR of TXEN, FMVOX, and IQRXEN. The VHR output is

high impedance otherwise.

In the digital mode, both the I and Q receive sides are enabled. Table 4–4 lists the receive channel frequency

response.

Table 4–4. Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode)

PARAMETER

TEST CONDITIONS

0 kHz to 8 kHz (see Note 4)

MIN

TYP

MAX

UNIT

±0.5 ±0.75

8 kHz to 15 kHz (see Note 4)

16.2 kHz to 18 kHz (see Note 2)

18 kHz to 45 kHz (see Note 2)

45 kHz to 75 kHz (see Note 2)

> 75 kHz

±1

–26

–30

–46

–60

Frequency

response

0.125 V peak-to-peak

Peak-to-peak

group delay

distortion

0.125 V peak-to-peak, 0 kHz to 15 kHz

µs

Absolute channel

delay, RXI, Q IN to 0.125 V peak-to-peak, 0 kHz to 15 kHz

digital OUT

325

µs

NOTES: 2. Stopband

4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response.

When the I and Q sample conversion is complete and the data is placed in the RXI and RXQ sample

registers, the SINT interrupt line is asserted to indicate the presence of that data. This occurs at 48.6-kHz

rate in the digital mode and at 40-kHz rate in the analog mode. In the analog mode, only the RXQ conversion

path is used, and the RXI path is powered down.

4.3 Transmit Section

The transmit section operates in two distinct modes, digital or analog. The mode of operation is determined

by the MODE bit of the DStatCtrl register. In the digital mode, data is input to the transmit section by writing

to the TXI register. The resulting output is a π/4 DQPSK-modulated time division multiplexed (TDM) burst.

In the analog mode, the data is in the form of direct I and Q samples which are written to both the TXI and

TXQ registers, then D/A converted, filtered, and output through TXIP, TXIN, TXQP, and TXQN. The I and

Q outputs are zero-IF FM signals; that is, no baseband connection is necessary for FM transmission.

In the digital mode (MODE = 1), the data is written to the TXI register using the SINT interrupt to synchronize

the data transfer. The TCM4300 performs parallel-to-serial conversion of the bits in the TXI register and

encodes the resulting bit stream as π/4 DQPSK data samples. These samples are then filtered by a digital

4–3

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square-root raised-cosine (SQRC) shaping filter with a roll-off rate of α = 0.35 and converted to sampled

analog form by two 9-bit digital-to-analog converters (DACs). The output of the DAC is then filtered by a

continuous-time resistance-capacitance (RC) filter.

The TCM4300 generates a power amplifier (PA) control signal, PAEN, to enable the power supply for the

PA. The start and stop times of the TDM burst are controlled by writing to a single bit, TXGO, in the DSP

DStatCtrl register.

In the analog mode (MODE = 0), the DSP writes 8-bit I and Q samples into the TXI and TXQ data registers

at a 40-ksps rate. These writes are timed by the SINT interrupt signal. The samples are fed to a low-pass

filter before D/A conversion. In the transmit analog mode, PAEN is always set to 1.

The transmit section provides differential I and Q outputs (see Table 4-5) for both analog and digital modes.

ThedifferentialdcoffsetfortheTXIandTXQoutputscanbeindependentlyadjustedusingthetransmitoffset

registers.

Table 4–5. Transmit (TX) I and Q Channel Outputs

PARAMETER

MIN

TYP

2.24

1.12

1.5

MAX

UNIT

Differential

Peak output voltage full scale, centered at VCM

Single ended

Differential

Nominal output-level (constellation radius) centered at

VCM

Single ended

0.75

±200

Low-level drift

PPM/°C

Transmit error vector magnitude (EVM)

Resolution

bits

S/(N+D) ratio at differential outputs

Gain error (I or Q channel)

±8%

±12%

Gain mismatch between I and Q

Gain sampling mismatch between I and Q

Zero code error differential

±0.3

±80

Zero code error, each output, with respect to VCM

±80

Zero code error, I to Q, with respect to other channel (differential or

single ended)

±10

Load impedance, between P and N terminals

Transmit offset DACs I and Q resolution

kΩ

bits

LSB

3.4

Transmit offset DACs I and Q average step size

Transmit offset DACs I and Q full-scale positive output

Transmit offset DACs I and Q full-scale negative output

Transmit offset DACs differential nonlinearity

Transmit offset DACs integral nonlinearity

2.9

3.9

105.4

–108.8

±1.1

Modulation Error: In the digital mode, during the transmit burst, the complex output of the transmitter circuits

consists of an ideal output s = I + jQ + error e = e + je . In Table 4-5, the modulation error vector

ideal

magnitude (EVM) is defined as the peak value of the magnitude of e relative to the ideal output:

|e|

|s|

Modulation error percentage

100

Table 4–6 and Table 4–7 show the frequency response of the transmit section for digital and analog mode,

respectively.

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Table 4–6. Transmit (TX) Channel Frequency Response (Digital Mode)

PARAMETER

TEST CONDITIONS

0 kHz to 8 kHz (see Note 4)

MIN

TYP

MAX

±0.3

±0.5

UNIT

8 kHz to 15 kHz (see Note 4)

20 kHz to 45 kHz (see Note 2)

–29

–55

–60

Frequency response

45 kHz to 75 kHz (see Note 2)

> 75 kHz (see Note 2)

Any 30 kHz band centered at > 90 kHz (see Note 2)

Peak-to-peak group

delay distortion

0 kHz to 15 kHz

µs

Absolute channel delay

NOTES: 2. Stopband

320

µs

4. Deviation from ideal 0.35 SQRC response

Table 4–7. Transmit (TX) Channel Frequency Response (Analog Mode)

PARAMETER

TEST CONDITIONS

0 kHz to 8 kHz (see Note 1)

MIN

TYP

MAX

±0.5

UNIT

8 kHz to 15 kHz (see Note 1)

20 kHz to 45 kHz (see Note 2)

–31

Frequency response

45 kHz to 75 kHz (see Note 2)

–70

> 75 kHz (see Note 2)

Any 30 kHz band centered at > 90 kHz (see Note 2)

Peak-to-peak group

delay distortion

0 kHz to 15 kHz

µs

Absolute channel delay

0 kHz to 15 kHz

540

µs

NOTES: 1. Ripple magnitude

2. Stopband

4.4 Transmit Burst Operation (Digital Mode)

Inthedigitalmode, theTCM4300performsallencoding, signalprocessing, andpowerrampingfortheburst.

Start and stop timing of the variable length bursts are set by means of the TXGO bit in the DStatCtrl

period = 1/24.3 kHz). The burst is initiated by the DSP writing 1 to 5 dibits to the TXI register, a small

positive-delay offset value d to the base station (BST) register, and a 1 to the TXGO bit in the DStatCtrl

The TXGO bit is sampled on the falling edge of SINT. The transmit outputs are held at zero differential

voltage (each output terminal is held at the voltage supplied to the VCM input terminal) for 9.5 SINT periods

(195.5µs)plusBSToffsetdelayafterSINThasdetectedTXGOhigh;thenthetransmitoutputsbegintoramp

to the initialπ/4 DQPSK constellation value. The shape of the ramp is the transient resulting from the internal

SQRC filtering. At the same time that the transmit outputs are beginning to ramp, the PAEN digital output

goes high. This output can enable the power amplifier of a cellular radio transmitter. The TCM4300 transmit

outputs reach the first π/4 DQPSK constellation value (maximum effect point, MEP) 6 SINT periods (3

symbol periods) after the start of the ramp.

The bit stream to be encoded as π/4 DQPSK symbols is generated by right shifts on each SINT of the TXI

PreviouslywrittendatacontinuestopropagatethroughtheTCM4300internalfiltersuntilthelastπ/4DQPSK

constellation value (last MEP) occurs at the transmit outputs 15.5 SINT periods (318.9 µs) plus BST offset

4–5

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delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decay

to zero differential voltage (each output at the voltage supplied to the VCM input terminal). The shape of the

decay is the transient resulting from the internal SQRC filtering. The transmit outputs are held at zero

differentialvoltage6SINTperiods(3symbolperiods)afterthestartofthedecay. AtthistimethePAENdigital

output is set low (see Figure 4–1 and Figure 4–2).

Nonzero values of the BST offset register increase the delays of both the transmit waveforms and PAEN

relative to the edges of TXGO after it is internally sampled by SINT. The delays are increased in increments

of 1/4 SINT (1/8 symbol period).

For delays of 1 SINT or greater, the fractional part of the delay can be achieved using the BST offset register

with the remaining integer SINT delay implemented externally by delaying the writing to TXGO and TXI.

The relative timing of PAEN and the transmit waveforms is not affected by the BST offset register.

The IS-54 standard describes shortened bursts and normal bursts. The two types differ in duration and

number of transmitted bursts, burst length being determined by the TXGO bit.

N+3 SINT Periods

(N = Total number of bits sent)

19.5 SINT Periods +d(T/8)

6 SINT Periods

9.5 SINT Periods

15.5 SINT Periods +d(T/8)

†

d(T/8)

SINT

TXGO

TXI data bit

PAEN

TXI/Q output ramp

Input Bits

>>>

Dibit transmission

First MEP

Last MEP

†

Total delay = d (SINT/4 or T/8) where d = integer value (0,1,2,3) written to the BST offset register.

Figure 4–1. Power Ramp-Up/Ramp-Down TIming Diagram

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Dibit

BST Offset

Delay

Channel Delay

(15.5 SINT Periods)

TXI,

TXQ

Transmit Channel Delay + d(T/8)

Occurs from last symbol (2 SINT periods)

before TXGO goes low

CLK

TXGO

Delay = 0, 1/4, 1/2, 3/4

BST Offset

Delay

PAEN Delay

SINT

PAEN

9.5

SYNOL

MPAEN

19.5

CLK

PAEN Delay + d(T/8)

TXGO high: 9.5 SINT periods + d(T/8): PAEN high

TXGO low: 19.5 SINT periods + d(T/8): PAEN low

Figure 4–2. Transmit Power Ramp-Up/Ramp-Down Functional Diagram

4.5 Transmit I And Q Output Level

In the digital mode, the output level at TXI and TXQ is controlled by the TCM4300. During the burst, but not

2 1/2

including ramp-up or ramp-down periods, the average output level (I + Q )

should approximate the

specified value. There is no variable level control for TXI and TXQ within the TCM4300 other than the fixed

ramping. In the analog mode, the output of the TCM4300 depends only on the sample values written to the

TXI and TXQ registers.

There are small differences in the average output power levels between the digital and the analog modes.

These differences require compensation at the system level by a small attenuation in the sample values of

the analog output.

When a change in transmit power is necessary, the microcontroller can change the value sent to the

PWRCONT DAC, the output of which can be connected to a voltage-controlled attenuator in the transmit

path of the RF section.

4.6 Wide-Band Data Demodulator

The wide-band data demodulator (WBDD) module demodulates the FM signal and outputs a

Manchester-decoded data stream. The WBDD is used for receiving the analog control channels of the

forward control channel (FOCC) and the forward voice channel (FVC). The bit error rate (BER) performance

requirements are listed in Table 4–8.

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Table 4–8. Typical Bit-Error-Rate Performance (WBD_BW = 000)

TEST CONDITIONS

PARAMETER

MIN

MAX

UNIT

MEAN CNR

–5

0.4

0.279

0.143

Bit error rate

0.056

0.0192

0.00623

0.00199

The WBDD is controlled by the bits in the control register WBDCtrl (see Table 4–9).

Table 4–9. Bits in Control Register WBDCtrl

NAME

WBD_LCKD

WBD_ON

WBD_BW

BIT CODE

FUNCTION

—

Indicates whether edge detector is locked (1) or unlocked (0)

Turns the WBDD module on/off (1/0)

Sets the appropriate PLL bandwidth

000

001

010

011

100

101

110

20 Hz

39 Hz

78 Hz

156 Hz

313 Hz

625 Hz

1250 Hz

WBD_LCKD: This bit reduces the effects of signal dropouts due to fading. In the Manchester-coded signal,

there are two types of data edges. One type occurs at the midpoint of each data bit, and the other occurs

randomly, depending on the transmitted data sequence. Inside the WBDD, an edge detector rapidly

synchronizes itself to the midpoint edges when the WBD_LCKD bit clears to 0. However, when a signal

dropout occurs, the edge detector may momentarily lock to the wrong edge because it cannot distinguish

the midpoint edges from the data edges. A small number of additional bits may be lost in this instance.

WhentheWBD_LCKDbitissetto1, theedgedetectorusestheWBDDinternalphaselockloop(PLL)output

to distinguish the correct edge. Once acquisition of data has occurred, when this bit is set to 1, the loss of

bits due to signal dropouts is restricted to the fade duration only.

When the WBDD PLL is not synchronized, as at power up, the WBD_LCKD bit must be cleared to 0 to allow

edge synchronization to the data.

WBD_BW: The variable bandwidth is required for fast acquisition in the beginning using a wide bandwidth

for the PLL, and a narrower bandwidth is used afterwards to reduce the likelihood of noise causing loss of

synchronization.

The WBDCtrl register is accessible by both the DSP and the microcontroller.

4.7 Wide-band Data Interrupts

The WBDD operates whenever WBD_ON is high, and it does not require the receive channels to be

enabled. While WBD_ON is high, every 800 µs, 8 bits are placed in the WBD register, which is accessible

by both the DSP and the microcontroller ports. This value should be written at the same time as WBD_ON

is initially set high.

4–8

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At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 µs

(8 bits/10 kHz). These interrupts are individually cleared when the WBD register is read by the

corresponding processor. They can also be cleared by their respective processor by writing a 1 to the

corresponding clear WBD bit.

There is one WBD control register. It can be written to by either processor port.

4.8 Wide-band Data Demodulator General Information

TheWBDDrecoversthetransmitterclockfromthedatastream, whichisManchesterencoded, anddecodes

the data bits. Consideration at the system level is required to ensure data integrity.

The WBD stream carries with it a 10-kHz clock. The Manchester-coded data format contains a transition

at the middle of every bit-clock period, which aids in clock recovery. The polarity of the transition is

data-dependent. In a typical Manchester-coded WBD stream, a positive voltage for the first half of the data

sequencebittimefollowedbyanegativevoltageforthesecondhalfofthedatasequencebittimerepresents

the value 0 in the data sequence. Likewise, a negative voltage followed by a transition to a positive voltage

represents the value 1 in the data sequence. This is illustrated in Figure 4–3. The WBD stream can also be

seen as the exclusive-OR of the clock and data sequence. The data sequence is in nonreturn to zero (NRZ)

format.

Data

Sequence

WBD

Stream

Recovered Clock

10 kHz

Figure 4–3. WBD Manchester-Coded Data Stream

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4.9 Auxiliary DACs, LCD Contrast Converter

Auxiliary DACs generate AFC, AGC and power control signals for the RF system. These three D/A

converters are updated when the corresponding data is received from the DSP. In fewer than 5 µs after the

corresponding registers are written to, the output has settled to within 1 LSB of its new value (see

Table 4–10).

Table 4–10. Auxiliary D/A Converters

PARAMETER

TEST CONDITIONS

MIN

0.2

TYP

MAX

2.5

UNIT

†

> 3 V ,

AUXFS [1:0] = 00

†

Output range

> 4.5 V , AUXFS [1:0] = 10

†

> 5 V ,

AUXFS [1:0] = 11

4.5

Resolution AGC, AFC, PWRCONT

DACs

bits

Resolution LCDCONTR DAC

Gain + offset error (full scale) AGC,

AFC, PWRCONT DAC

±3%

Gain + offset error (full scale)

LCDCONTR DAC

±7%

Differential nonlinearity

Integral nonlinearity

±0.75

±1

LSB

±0.75

±1

†

Range settings depends only on AUXFS [1:0]. The supply voltage is not detected.

The LCDCONTR output is used by the microcontroller to adjust the contrast of the liquid-crystal display

(LCD). This converter is a separate 4-bit DAC.

The auxiliary DACs can be powered down. The AGC and AFC DACs have dedicated bits in the MIntCtrl

LCDCONTR DACisenabledwhentheLCDENbitoftheLCDD/Aregisterclearsto0, thefourdatabitsbeing

left justified. The AFC, AGC, and PWRCONT DACs are disabled after powerup or after a reset of the

TCM4300. After power up or reset, the default AUXFS[1:0] is 00. When the DACs are powered down, their

output terminals go to a high-impedance state and can tolerate any voltage present on the terminal that falls

within the supply range.

The slope and the corresponding output values for the auxiliary DACs are listed in Table 4–11 and

Table 4–12.

Table 4–11. Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT)

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 128

(MIDRANGE)

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 256

NOMINAL LSB

VALUE

‡

AUXFS[1:0]

SETTING

SLOPE

(MAX VALUE)

(V)

2.5/256

Do not use

4/256

0.0098

Do not use

0.0156

1.25

Do not use

2.5

Do not use

4.5/256

0.0176

2.25

4.5

‡

The maximum input code is 255. The value shown for 256 is extrapolated.

4–10

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4.9 Auxiliary DACs, LCD Contrast Converter (continued)

Table 4–12. Auxiliary D/A Converters Slope (LCDCONTR)

NOMINAL OUTPUT VOLT-

AGE FOR DIGITAL CODE = 8

(MIDRANGE)

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 16†

NOMINAL LSB

VALUE

AUXFS[1:0]

SETTING

SLOPE

(MAX VALUE)

(V)

2.5/16

Do not use

4/16

0.1563

Do not use

0.2500

1.25

Do not use

2.5

Do not use

4.5/16

0.2813

2.25

4.5

†

The maximum input code is 15. The value shown for 16 is extrapolated.

4.10 RSSI, Battery Monitor

The received signal strength indicator (RSSI) and battery (BAT) strength monitor share a common register.

The input source is determined by writing any value to the mapped register location for that analog-to-digital

converter (ADC) (see Table 4–13), and the result of the conversion is stored in both register locations. The

conversion process is initiated when the register is written to. The CVRDY bit in the MStatCtrl register is set

to 1 to show completion of the conversion process. Reading from either of the register locations causes the

CVRDY bit to change to 0. The RSSI allows the mobile unit to choose the proper control channels and to

report signal levels to the base stations.

When the CVRDY bit in the MStatCtrl register goes to 1, this indicates that the latest RSSI or battery voltage

A/D conversion has been completed and can be read from the RSSI or BAT register location. CVRDY clears

to 0 when the microcontroller reads either of these locations.

Table 4–13. RSSI/Battery A/D Converter

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input range

= 3 V, 4.5 V, 5 V

0.2

Resolution

bits

µs

Conversion time

Gain + offset error (full scale)

Differential nonlinearity

Integral nonlinearity

±3%

±0.75

±4%

±1

LSB

MΩ

±1

Input resistance

In order to save power, the entire RSSI/battery converter circuit is powered down when no A/D conversions

are requested for 40 µs. The microcontroller writes to RSSI or BAT registers, causing power to be applied

to the converter circuit. Power is applied to the converter circuit until the data value has been latched into

the corresponding register, at which time power to the converter is removed. Data remains in the result

registers after the converter is powered down.

4.11 Timing And Clock Generation

The digital timing generation system uses a 38.88-MHz master clock as shown in Figure 4–4. The upper

waveform shows the clock generation for clocks that must be phase adjusted in order to synchronize the

mobile unit with the received symbol stream in the digital mode. In the analog mode, these clocks operate

without phase adjustments. The bottom waveform of Figure 4–4 shows the clocks that are directly derived

from the master clock.

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Codec Master Clock 2.048 MHz

CMCLK

Codec Sample Clock 8 kHz

CSCLK

Figure 4–4. Codec Master and Sample Clock Timing

4.11.1 Clock Generation

There are three options for generating the master clock. A fundamental crystal or a third-overtone crystal

with a frequency of 38.88 MHz can be connected between the MCLKIN and the XTAL terminals or an

external clock source can be connected directly to the MCLKIN terminal. The MCLKOUT is a buffered

masterclockoutputatthesamefrequencyasMCLKIN. MCLKOUTcanbeusedasthesourceclockforother

devices in the system. Setting the MCLKEN bit in the MStatCtrl register enables or disables this output. The

MCLKOUT enable is synchronous with MCLKIN to eliminate abnormal cycles of the clock output.

All output clocks are derived from the master clock (MCLKIN). The sample clocks for the digital and analog

modes, the 8-kHz speech codec sample clock, and the clocks for the A/D and D/A functions are also derived

from the master clock.

4.11.2 Speech-Codec Clock Generation

The TCM4300 generates two clock outputs for use with speech codecs: the 2.048-MHz CMCLK and the

8-kHz CSCLK. These clocks are generated so that each CSCLK period contains exactly 256 cycles of

CMCLK. Since 2.048 MHz is not an integer division of the 38.88-MHz MCLKIN, one out of every 64 CMCLK

cycles is 18 MCLKIN periods long, and the remaining 63 out of 64 are 19 MCLKIN periods long. The average

frequency of MCLKIN is therefore

MCLKIN

2.048092 MHz

CSCLK is exactly CMCLK divided by 256 (see Figure 4–4).

To save power, the codec clocks are only generated by TCM4300 when the SCEN bit of the DStatCtrl

available as an output.

4.11.3 Microcontroller Clock

Avariablemodulusdividerprovidesaselectionoffrequenciesforuseasamicrocontrollerclock. Themaster

clock is divided by an integer from 32 to 2, giving a wide range of frequencies available to the microcontroller

(1.215 MHz to 19.88 MHz). The modulus can be changed by writing to the microcontroller clock register.

The output duty cycle is within the requirements of most microcontrollers, that is, from 40% to 60%. At

power-on reset, the clock divider defaults to 1.215 MHz.

4.11.4 Sample Interrupt SINT

The SINT interrupt signal is the primary timing signal for the TCM4300 interface. The primary function of

the SINT is to indicate the ready condition to receive or transmit data. It also conveys timing marks to allow

for the synchronization of system DSP functions. In the digital mode, SINT is used in conjunction with the

received sync word to track cellular system timing. The SINT can be disabled by writing a 1 to the SDIS bit

of the DIntCtrl register. When enabled, the SINT operates continuously at 48.6 kHz in the digital mode and

at40kHzintheanalogmode. TheSINTsignaldoesnotrequireaninterruptacknowledge. TheSINTisactive

low for 5.5 MCLK cycles (141.5 ns) in the analog mode and 6.5 MCLK cycles (167.2 ns) in the digital mode.

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4.11.5 Phase-Adjustment Strategy

For an IS-54 system in the digital mode, receiver sample timing must be phase adjusted to synchronize the

A/D conversions to optimum sampling points of the received symbols, and to synchronize the mobile unit

timing to the base station timing. This is done by temporarily increasing or decreasing the periods of the

clocks to be adjusted. To avoid undesirable transients, each cycle of the clock being adjusted is altered by

only one period of MCLKIN. A total adjustment equivalent to multiple MCLKIN periods is accomplished by

altering multiple cycles of the clock being adjusted. The number of cycles altered is controlled by internal

counters.

In the TCM4300 there are two clocks which must be adjusted: CMCLK and an internal 9.72-MHz clock from

which SINT is derived. Each of these clocks has an associated counter that counts the number of cycles

that have been lengthened or shortened by one MCLKIN period each and thus detects when the total

adjustmentis complete. These counters are shown in Figure 4–5 as Adjust Counter A and Adjust Counter B.

The magnitude of the 2s complement value written to the timing adjustment register determines the number

ofcyclesoftheclockstobelengthenedorshortenedbyoneMCLKINperiodeachtoachievethetotaldesired

timing adjustment in units of MCLKIN periods. If a negative number is written, the clock periods are

lengthened for the duration of the timing adjustment, resulting in a timing delay. If a positive number is

written, the clock periods are shortened for the duration of the timing adjustment, resulting in a timing

advance.

The divider generates CMCLK normally divides MCLKIN by either 19 or 18. When the CMCLK period is

beinglengthenedduringatimingadjustment, MCLKINisdividedbyeither20or19. WhentheCMCLKperiod

is being shortened, MCLKIN is divided by either 18 or 17 (see subsection 4.11.2). The divider used to

generate a 9.72-MHz clock divides by 4 during normal operation, by 5 when its period is being lengthened

during timing adjustments, and by 3 when its period is being shortened during timing adjustments.

Because CMCLK and the 9.72-MHz internal clock have different periods, and the timing adjustments are

limited to one period of MCLKIN per period of the clock, these clocks take different times to complete the

entire timing adjustment. Because the total adjustment is the same number of MCLKIN periods for both

clocks, the relative phases of the two clocks are the same after the adjustment as they were before.

Both adjust counters reach zero when the adjustment is complete, so there is no need to write to the timing

adjustment register until another timing adjustment is required. For each write to the timing adjustment

The output of each adjustment counter is fed to a variable modulus divider. For counter A, there are three

possible moduli, 3, 4, and 5. For counter B there are four possible moduli, 17, 18, 19, and 20.

4–13

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2.048-MHz Codec Master Clock CMCLK

÷ 17, 18, 19, 20

= 0

÷ 256

Bits 0–5

RCO

Adjust

8-kHz Codec Sample Clock CSCLK

Counter B

From DSP

Phase-Adjusted

9.72-MHz Clock

Adjust

Counter A

Analog/Digital

40.0/48.6-kHz A/D Sample Clock (SINT)

38.88 MHz

MCLKIN

÷ 243/

÷ 200

÷ 3, 4, 5

Analog/Digital

Mode (MODE bit)

Frequency Synth. Clock 303.75 kHz

WBD Demod. 6.48 MHz

ADC Clocks

Clock

Divider

Chain

From

Micro-

DAC Clocks

controller

Microcontroller Clock MCCLK

÷ N

N = (2, 3, . . . 32)

Sync.

Enable

Logic

External Clock Output MCLKOUT

MCLKEN

Figure 4–5. Timing and Clock Generation for 38.88-MHz Clock

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4.12 Frequency Synthesizer Interface

The synthesizer interface provides a means of programming three synthesizers. The synthesizer-side

outputs are a data line, a clock line, and three latch enable lines that separately strobe data into each

synthesizer. The control inputs are registers mapped into the microcontroller address space. The status of

the interface can be monitored to determine when the programming operation has been completed.

The synthesizer interface is designed to be general purpose. Most of the currently available synthesizers

can be accommodated by programming the interface according to the required synthesizer data and logic

level formats.

The output of the synthesizer interface consists of five signals. SYNCLK is the common data clock for all

attached synthesizer chips. The clock rate is MCLK/128 (≈304 kHz). The clock pulse has a 50% duty factor.

The serial data output SYNDTA is common to all synthesizers. Three strobe signals, SYNLE0, SYNLE1,

and SYNLE2, are provided. There is one for each synthesizer chip. The attributes of this interface are

controlled by means of the synthesizer control registers, SynCtrl0, SynCtrl1, and SynCtrl2. These attributes

determine:

•

The polarity of the clock (rising or falling edge)

Whether data is shifted left or right

The number of bits sent to the synthesizer

The timing and polarity of the latch enable bits

The selection of which synthesizer to program

Programming of the synthesizers is accomplished by writing to four microcontroller-mapped data registers.

These registers are chained to form a 32-bit data shift register that can be operated in either shift left or shift

right mode. This register set can accommodate various formats of synthesizer control data. When fewer

than 32 bits of data are to be transmitted, the significant data bits must be justified such that the first bit to

be transferred is either the LSB or the MSB of the register set, as defined by the control register for LSB or

MSB first operation. All 32 bits of the data register are transmitted each time (see Section 4.15 for register

location and Figure 4–6 for a representative block diagram of the frequency synthesizer interface).

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CLKPOL

NUMCLKS

Control

Registers

LOWVAL

HIGHVAL

SEL[2:0]

Ready

and

MSB/LSB FIRST

Timing Logic

SYNRDY To MStatCtrl Register

SYNDTA

SYNLE0

32-Bit Data

µC

Bus

SEL 0

MSB/LSB

FIRST

DMUX

SYNLE1

SYNLE2

SEL 1

SEL 2

HIGHVAL

A = B

LOWVAL

A = B

CLKPOL

NUMCLKS

Clock

Circuit

B ≤ A

SYNCLK

BIT CNT

[0 . . . 31]

303.75 KHz

Figure 4–6. Synthesizer Interface Circuit Block Diagram

4–16

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The SynData0 register contains the least significant bits of the 32-bit data register. SynData3 contains the

most significant bits. The bits in the SynCtrl0, SynCtrl1, and SynCtrl2 registers are allocated as shown in

Figure 4–7.

7–5

4–0

SynCtrl0

SynCtrl1

SynCtrl2

SEL[2:0]

LOWVAL

7–6

4–0

MSB/LSB

FIRST

Reserved

HIGHVAL

7–6

4–0

Reserved

CLKPOL

NUMCLKS

Figure 4–7. Contents of SynData Registers

Table 4–14 identifies the meaning of each of the bit fields in SynCtrl[2:0].

Table 4–14. Synthesizer Control Fields

NAME

CLKPOL

DESCRIPTION

This is a 1-bit field. When CLKPOL = 1, the SYNCLK signal is a positive-going, 50% duty cycle

pulse. CLKPOL = 0 reverses the polarity of SYNCLK.

NUMCLKS

HIGHVAL

LOWVAL

This 5-bit field defines the total number of clock pulses that are to be produced on SYNCLK. The

value written into NUMCLKS is the desired number of output clock pulses, with one exception:

When 32 clock pulses are desired, all zeroes are written into NUMCLKS.

This 5-bit field defines when the strobe signal for the selected synthesizer is driven high. HIGHVAL

is the bit number at which the signal changes state. Bits being transferred on SYNDTA are

sequentially designated 0, 1, . . . 31, independent of any MSB/LSB selection.

The value written into this 5-bit field affects the strobe signal for the selected synthesizer. LOWVAL

is the bit number at which the strobe signal is driven low. The first bit transferred out of the serial

interface is defined to occur at bit-time 0, independent of any MSB/LSB selection.

MSB/LSB FIRST Writing a 0 to MSB/LSB FIRST causes the LSB (SynData0[0]) to be the first bit sent to SYNDTA

of the serial synthesizer interface. Writing a 1 to this bit programs the block for MSB first operation,

SynData3[7].

SEL[2:0]

This is a 3 bit field that selects which synthesizer strobe line is active. A 1 in any of the SELx bits

activates the corresponding latch enable.

In the status register MStatCtrl, two bits, SYNOL and SYNRDY, are dedicated to the synthesizers. The first

is an out-of-lock indicator that comes from the SYNOL input terminal. When the SYNOL input terminal is

connected to the OR of the out-of-lock signals from the external synthesizers, the lock condition of the

synthesizers can be monitored by reading the MStatCtrl register. A high on SYNOL also prevents the PAEN

output from being asserted and forces the TXI and TXQ outputs to zero. The SYNRDY bit, active high,

indicates when the synthesizer interface is idle and ready for programming. When SYNRDY is low, the

synthesizer interface is busy.

Controlling the synthesizer interface is straightforward. The microcontroller checks to see if the SYNRDY

bitislow. Whenitislow, thesynthesizerinterfaceisnotready. WhenSYNRDYgoeshigh, themicrocontroller

programs the desired information into the four registers. When the microcontroller write to the SynCtrl2

latch enable according to the format established in the registers. SYNRDY returns high when the entire

operation is complete.

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Up to 31 data bits plus a latch enable (SYNLE0,1,2) can be programmed in one programming cycle. When

data greater than or equal to 32 bits must be programmed, TI recommends using two or more programming

cycles with data in each cycle and a latch enable in the final programming cycle. Two or more programming

cycles are recommended because all programming cycles must contain at least one SYNCLK pulse,

whereas the latch enable can be suppressed in any programming cycle.

Figure 4–8 shows an example of the synthesizer output signals. In this case, an 18-bit pattern, 0x10664,

was chosen to write into synthesizer 1 with a positive-going latch enable pulse at the eighteenth bit. In order

to do so, the microcontroller writes the values 00h into SynData0, 00h into SynData1, 99h into SynData2,

41h into SynData3, 52h into SynCtrl0, 31h into SynCtrl1, and 32h into SynCtrl2.

SYNCLK

SYNDTA

SYNLE1

SYNLE0, 2

SYNRDY

Figure 4–8. Example Synthesizer Output

4.13 Power Control Port

For systems requiring minimum system current consumption, power can be provided to each functional part

of the TCM4300 only when that function is required for proper system operation. To accomplish this, the

TCM4300 provides six external power control signals accessible through the DStatCtrl and MStatCtrl

registers. These signals can be used to minimize the on time of the functional units. These power control

signals are SCEN, FMRXEN, IQRXEN, TXEN, PAEN, and OUT1 (see Table 4–15). The polarity of each of

these signals is high enable, low disable.

Table 4-15. External Power Control Signals

RESET

NAME

SCEN

SUGGESTED EXTERNAL APPLICATION

VALUE

Speech codec (microphone/speaker interface circuit) enable

FM demodulator enable

FMRXEN

IQRXEN

TXEN

I and Q receive enable. IQRXEN enables the QPSK demodulator and the AGC amplifier

Transmit enable. TXEN enables power to the transmitter signal processing circuits: QPSK

modulator, voltage-controlled amplifier, driver amplifier, PA negative bias. This signal can

be used to enable these subsystems only during the transmit burst in digital mode.

OUT1

PAEN

User defined

Power amplifier enable. PAEN enables power to PA.

4–18

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In addition to allowing control of power to external functional modules, these power control bits combined

with other control bits are used to control internal TCM4300 functions. This control system is shown in

Figure 4–9.

WBD_ON

FMRXEN

WBD

Ctrl

WBD Demodulator Circuit

SC Clock Generation

Q-Side Input MUX

OUT1

MIntCtrl

SCEN

FMRXEN

FMVOX

OUT1

VHR High Drive Enable

(Hi-Z when disabled)

Q-Side RX Enable

I-Side RX Enable

DStatCtrl

IQRXEN

TXEN

MODE

TXGO

TX and RX Filter Select

TX Signal Processing

PWRCONT, Enable (Hi-z when disabled)

SYNOL

PAEN

Transmitter

Control

MStatCtrl

Circuits

TXONIND

MPAEN

Figure 4–9. Internal and External Power Control Logic

To allow for further system power savings, the TCM4300 receive I and Q channels are enabled separately

because only the Q side is used in analog mode. The FMVOX bit controls the Q-side input multiplexer. When

FMVOX is high, the QP side of the receiver is connected to the FM input terminal, the QN input is connected

to the VHR reference voltage, and the Q side of the receiver is powered up. The MODE bit controls the

Q-side filter characteristics for digital or analog mode. The IQRXEN bit enables both the I and Q receiver

sides. The bit IQRXEN can be set high while still in analog mode (FMVOX high or MODE low) to allow

sufficient power-up settling time for the external receiver I and Q circuits.

Setting the MODE bit low connects RXQP to the FM input and RXQN to VHR.

In the digital mode (MODE bit set high), setting IQRXEN high turns on both sides of the receiver. The TXEN

enables the internal transmit functions. When the TXEN bit is set low, the PWRCONT output goes to a

high-impedance state and the PAEN output is set low. The TXEN signal can be used to power down most

of the external transmit circuits between transmit bursts.

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In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. The

SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock.

The PAEN signal is gated by SYNOL to prevent off-channel transmissions.

The TXEN, IQRXEN, FMVOX, and MODE signals are generated by sampling the corresponding bits of the

DStatCtrl register with the internal SINT. The effect of a write to the DStatCtrl register on these signals does

not appear until the next SINT after the write.

4.14 Microcontroller-DSP Communications

The microcontroller and the DSP communicate by means of two separate 32-byte first-in first-out (FIFO)

buffers. Figure 4–10 illustrates this scheme. The microcontroller writes to FIFO A, but data read from the

same address comes from FIFO B. On the DSP side, the situation is reversed.

Send CINT,

CINT Status,

Clear DINT

CINT

FIFO A

µC

DSP

DINT

FIFO B

Send DINT,

DINT Status,

Clear CINT

Figure 4–10. Microcontroller-DSP Data Buffers

To send data to the DSP, the microcontroller writes data to FIFO A. To indicate to the DSP that FIFO A is

ready to be read, the microcontroller writes a 1 to the Send-C bit of the microcontroller interrupt control

registerMIntCtrl. Whenthishappens, theDSPinterruptlineCINTgoesactive, signalingtotheDSPthatdata

is waiting. At the same time, the value that can be read from the Clear-C bit in the DIntCtrl register goes from

0 to 1, indicating that the interrupt is pending. When the DSP writes a 1 to the Clear-C bit, the CINT line

returns to the inactive state and the value that can be read from Clear-C is 0. The microcontroller cannot

deassert the CINT line.

The microcontroller-DSP communications interface is symmetric. Data sent from the DSP to the

microcontroller is handled as described above, with the roles of A and B FIFOs and C and D bits and

interrupts reversed. When the number of reads exceeds the number of writes from the other side, the values

read are undefined.

4–20

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4.15 Microcontroller Register Map

The microcontroller can access 17 locations within the TCM4300. The register locations are 8 bits wide as

shown in Table 4–16 and Table 4–17.

Table 4–16. Microcontroller Register Map

ADDR

00h

01h

02h

03h

04h

05h

06h

07h

NAME

WBDCtrl

WBD

WBD_LCKD WBD_ON

MSB

WBD_BW

Reserved

LSB

FIFO

MSB

Clear WBD

MSB

FIFO A(B) Microcontroller to DSP (DSP to microcontroller)

MIntCtrl

SynData0

SynData1

SynData2

SynData3

SynCtrl0

Clear-F

Clear-D

Send-C

AGCEN

AFCEN

FMRXEN Reserved

LSB

MSB

SEL[2:0]

LOWVAL

HIGHVAL

NUMCLKS

MSB/LSB

FIRST

08h

SynCtrl1

Reserved

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

SynCtrl2

MCClock

RSSI A/D

BAT A/D

Reserved

CLKPOL

MSB

LSB

MSB

LSB

LCD D/A

MStatCtrl

TXI Offset

TXQ Offset

LSD

TXONIND SYNRDY MCLKEN CVRDY

Reserved

AuxFS1

LCDEN

SYNOL

AuxFS0

MPAEN

LSB

Reserved

Sign

MSB

LSB

4–21

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Table 4–17. Microcontroller Register Definitions