DEM-DAI3793A/3794A EVM
User's Guide
July 2007
AIP Consumer Audio—TI Japan
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Contents
Preface ............................................................................................................................... 9
1
Description .............................................................................................................. 11
1.1
Introduction—PCM3793A/94A .................................................................................. 12
1.1.1 Key Features.............................................................................................. 12
Pin Assignments and Terminal Functions...................................................................... 14
DEM-DAI3793A/3794A EVM Description ...................................................................... 15
1.2
1.3
2
3
Getting Started ......................................................................................................... 17
2.1
2.2
2.3
Electrostatic Discharge Warning ................................................................................ 18
Unpacking the EVM............................................................................................... 18
Default Configuration ............................................................................................. 19
Set-Up Guide ........................................................................................................... 21
3.1
Basic Operating Set-Up .......................................................................................... 22
Software Control and Operation................................................................................. 22
3.2.1 User Interface Panel ..................................................................................... 22
3.2.2 Power On/Off Sequence ................................................................................ 23
3.2.3 Module Function Controls ............................................................................... 23
3.2.4 LC89052T (DIR: Digital Audio I/F Receiver) Control Window...................................... 39
3.2.5 Register Setting History ................................................................................. 40
3.2.6 Register Direct Access .................................................................................. 42
3.2
4
5
Switches and Connectors .......................................................................................... 43
4.1
4.2
4.3
4.4
Overview............................................................................................................ 44
Motherboard ....................................................................................................... 44
Daughter Card #1 (PCM3793A)................................................................................. 46
Daughter Card #2 (DIR: LC89052T and DIT: DIT4096) ..................................................... 48
Evaluation and Measurements ................................................................................... 49
5.1
5.2
5.3
5.4
Slave Mode With Audio Precision SYS-2722 (Default Setting) ............................................. 50
Master Mode with Audio Precision SYS-2722................................................................. 52
Combined Master and Slave Modes With PSIA-2722........................................................ 54
Measurements for Dynamic Characteristics ................................................................... 55
5.4.1 Digital-to-Analog (D/A) Performance .................................................................. 56
5.4.2 Analog-to-Digital (A/D) Performance .................................................................. 57
5.4.3 Speaker Output Power Performance .................................................................. 57
5.4.4 Amplitude Versus Frequency Performance........................................................... 59
Connection Diagram for Practical Applications................................................................ 61
5.5.1 Filter Consideration for Speaker Output............................................................... 62
5.5
6
Schematic, PCB Layout, and Bill of Materials ............................................................... 63
6.1
6.2
6.3
Schematics......................................................................................................... 64
Printed Circuit Board Layout..................................................................................... 66
Component List.................................................................................................... 71
A
Reference .csv Files, Interfacing to DSPs, and Package Information ............................... 73
Reference .csv Files .............................................................................................. 74
Related Signal Flow Diagrams ......................................................................... 75
A.1
A
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A.2
A.3
Interfacing to DSPs ............................................................................................... 98
A.2.1 Register Control with DSP Interface ................................................................... 99
Package Information .............................................................................................. 99
Important Notices ............................................................................................................. 100
4
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List of Figures
1-1
1-2
1-3
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
PCM3793A Pin Assignments ............................................................................................. 14
PCM3794A Pin Assignments ............................................................................................. 14
DEM-DAI3793A/3794A EVM System Diagram......................................................................... 15
EVM Configuration ......................................................................................................... 19
EVM and External Equipment Connections ............................................................................ 20
User Interface Window .................................................................................................... 22
Communication Error Message .......................................................................................... 23
Power On/Off Sequence Function Buttons ............................................................................. 23
Internal Module Power Up/Down Function Menu Tab................................................................. 24
Ramp Up Wave Form with Default Setting ............................................................................. 26
Ramp Down Wave Form with Default Setting.......................................................................... 26
Record Function Menu Tab............................................................................................... 26
EVM Modules Corresponding to Record Function..................................................................... 27
Playback Function Menu Tab............................................................................................. 28
3-10 Modules Corresponding to Playback Function ......................................................................... 29
3-11 ALC Function Menu Tab .................................................................................................. 30
3-12 ALC Compression and Expansion Characteristics .................................................................... 30
3-13 Signal Processing 1 Function Menu Tab................................................................................ 31
3-14 Three-Band Tone Control (Bass, Mid, Treble) ......................................................................... 31
3-15 Notch Filter Characteristic Model ........................................................................................ 33
3-16 Example of Measured Notch Filter Characteristic ..................................................................... 33
3-17 Signal Processing 2 Function Menu Tab................................................................................ 34
3-18 Analog Path Function Menu Tab......................................................................................... 35
3-19 Modules Corresponding to Analog Path Function ..................................................................... 36
3-20 Audio Interface Function Menu Tab ..................................................................................... 37
3-21 Status Detect Function Menu Tab ....................................................................................... 38
3-22 Digital Amplifier Function Menu Tab..................................................................................... 39
3-23 LC89052 Interface Format Selection Options .......................................................................... 39
3-24 Register Setting History Window......................................................................................... 40
3-25 Opening and Modifying a .csv File....................................................................................... 41
3-26 Register Direct Access Dialog............................................................................................ 42
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
EVM Configuration ......................................................................................................... 44
Analog Input Configuration (Daughter Card #1)........................................................................ 46
Analog Output Configuration (Daughter Card #1) ..................................................................... 47
Slave Mode Configuration With SYS-2722 ............................................................................. 50
Jumper Configuration for Slave Mode (Default)........................................................................ 51
Master Mode Configuration With SYS-2722............................................................................ 52
Jumper Configuration for Master Mode ................................................................................. 53
Combined Master and Slave Mode Configuration with SYS-2722 .................................................. 54
Jumper Configuration for Combined Master and Slave Modes ...................................................... 55
Speaker Output Filter Configuration ..................................................................................... 58
A/D Amplitude vs Frequency Result: BPZ (Zero Data) Input......................................................... 59
A/D Amplitude vs Frequency Result: –60dB Input..................................................................... 59
5-10 A/D Amplitude vs Frequency Result: –1dB Input ...................................................................... 59
5-11 D/A Amplitude vs Frequency Result: BPZ (Zero Data) Input......................................................... 60
5-12 D/A Amplitude vs Frequency Result: –60dB Input..................................................................... 60
5-13 D/A Amplitude vs Frequency Result: 0dB Input........................................................................ 60
5-14 D/A Amplitude vs Frequency Result: Wide Range to 130kHz, BPZ (Zero Data) Input ........................... 60
5-15 Basic Connection Diagram................................................................................................ 61
5-16 Recommended Ferrite Bead Filter for Speaker Output ............................................................... 62
5-17 Connection for Headphone Output and Insertion Detection.......................................................... 62
6-1
PCM3793A DEM-PCM3793RHB-A Connector (Daughter Card #1) ................................................ 64
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6-2
6-3
6-4
6-5
6-6
6-7
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
PCM3793A DEM-PCM3793RHB-A (Daughter Card #1).............................................................. 65
PCM3793A DEM-PCM3793RHB-A Board Layout—Silkscreen Side................................................ 66
PCM3793A DEM-PCM3793RHB-A Board Layout—Component Side .............................................. 67
PCM3793A DEM-PCM3793RHB-A Board Layout—Inner Layer 2 .................................................. 68
PCM3793A DEM-PCM3793RHB-A Board Layout—Inner Layer 3 .................................................. 69
PCM3793A DEM-PCM3793RHB-A Board Layout—Solder Side .................................................... 70
Line Output and Headphone Output..................................................................................... 75
Headphone Output with Sound Effect ................................................................................... 76
Cap-Less Headphone Output............................................................................................. 77
Headphone Output with Line Input (AIN2L/AIN2R).................................................................... 78
Headphone Output with Mono Mic Input (AIN1L, +20dB) ............................................................ 79
Headphone Output with Mono Diff Mic Input (AIN1L/AIN1R, +20dB)............................................... 80
Stereo Speaker Output .................................................................................................... 81
Mono Speaker Output ..................................................................................................... 82
Speaker Output with Line Input (AIN2L/AIN2R)........................................................................ 83
A-10 Speaker Output with Mono Mic Input (AIN1L, +20dB) ................................................................ 84
A-11 Speaker Output with Mono Diff Mic Input (AIN1L/AIN1R, +20dB)................................................... 85
A-12 Line Input (AIN2L/AIN2R) to Headphone Output ...................................................................... 86
A-13 Mono Line Input (AIN2L) to Headphone Output ....................................................................... 87
A-14 Mono Mic Input (AIN1L, +20dB) to Headphone Output ............................................................... 88
A-15 Mono Diff Mic Input (AIN1L/AIN1R, +20dB) to Headphone Output ................................................. 89
A-16 Mono Mic Input (AIN1L, +20dB) to Speaker Output................................................................... 90
A-17 Line Input (AIN3L/AIN3R) ................................................................................................. 91
A-18 Mic Input (AIN1L/AIN1R, +20dB)......................................................................................... 92
A-19 Mic Input (AIN1L/AIN1R, +20dB) with ALC............................................................................. 93
A-20 Mono Mic Input (AIN1L, +20dB).......................................................................................... 94
A-21 Mono Mic Input (AIN1L, +20dB) with ALC .............................................................................. 95
A-22 Mono Diff Mic Input (AIN1L/AIN1R, +20dB) ............................................................................ 96
A-23 Mono Diff Mic Input (AIN1L/AIN1R, +20dB) with ALC ................................................................ 97
A-24 Slave Mode Operation..................................................................................................... 98
A-25 Master Mode Operation ................................................................................................... 98
6
List of Figures
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List of Tables
1-1
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
6-1
A-1
A-2
PCM3793A/94A Terminal Functions..................................................................................... 14
Register Mapping for Power Up/Down Module......................................................................... 24
PCM3793A/94A Resistor 125(7dh) RES[4:0]: Resistor Value Control.............................................. 25
PCM3793A/94A Resistor 125(7dh) PMT[1:0]: Power Up/Down Time Control and Register Direct Access ... 25
Main Power Supply and Regulator....................................................................................... 44
Power-Supply Terminals for PCM3793A Power-Supply Pins ....................................................... 44
Audio I/O .................................................................................................................... 45
I/F Controller (MSP430, TUSB3410) .................................................................................... 45
Analog Input and Output—Daughter Card #1 .......................................................................... 46
Analog Input and Output—Daughter Card #2 .......................................................................... 48
Audio Clock and Input Data Control Format—Daughter Card #2.................................................... 48
D/A Line Output Parameters.............................................................................................. 56
16Ω Headphone Output Inserted in Headphone Jack J6............................................................. 56
A/D Line Input Parameters................................................................................................ 57
Stereo Speaker Output Parameters ..................................................................................... 57
Recommended External Parts for Basic Connection Diagram....................................................... 61
Bill of Materials ............................................................................................................. 71
.csv Files .................................................................................................................... 74
Recommended Power-On Sequence for PCM3793A ................................................................. 99
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SYS-2722, PSIA-2722 are registered trademarks of Audio Precision, Inc.
SPI is a trademark of Motorola, Inc.
I2S, I2C are trademarks of NXP Semiconductors.
TOSLINK is a trademark of Toshiba Corporation.
All other trademarks are the property of their respective owners.
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Preface
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Read This First
About This Manual
This document provides the information needed to set up and operate the DEM-DAI3793A/3794A EVM
evaluation module, a test platform for the 16-bit, low-power PCM3793A/PCM3794A stereo audio codecs.
For a more detailed description of the PCM3793A/94A products, please refer to the product data sheets
available from the Texas Instruments web site at http://www.ti.com. Support documents are listed in the
sections of this guide entitled Related Documentation from Texas Instruments and Additional
Documentation.
How to Use This Manual
Throughout this document, the abbreviation EVM and the term evaluation module are synonymous with
the DEM-DAI3793A/3794A EVM. The abbreviation PCM3793A/94A refers to the PCM3793A/94A family of
devices. Unless specifically noted, the information presented in this manual applies to both the PCM3793A
and the PCM3794A.
(codecs). The PCM3793A/94A block diagram and primary features are also discussed.
conditions, and the default switch and jumper configuration. This chapter also discusses the EVM
controller software
Chapter 3 is the hardware setup guide for the EVM, providing all of the necessary information needed to
configure the EVM switches and jumpers for product evaluation.
performance evaluation using an audio analyzer. It also presents the process for measuring dynamic
characteristics and provides example characteristic data.
Chapter 6 includes the EVM electrical schematics, printed circuit board (PCB) layout, and the bill of
materials.
Information About Cautions and Warnings
This document contains caution statements.
CAUTION
This is an example of a caution statement. A caution statement describes a
situation that could potentially damage your software or equipment.
The information in a caution or a warning is provided for your protection. Please read each caution and
warning carefully.
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Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
The following documents provide information regarding Texas Instruments integrated circuits used in the
last character of the literature number corresponds to the document revision that is current at the time of
the writing of this User’s Guide. Newer revisions may be available from the TI web site at
http://www.ti.com/ or call the Texas Instruments Literature Response Center at (800) 477–8924 or the
Product Information Center at (972) 644–5580. When ordering, identify the document(s) by both title and
literature number.
Data Sheet
Literature Number
SLAS529A
PCM3793A/PCM3794A Product
data sheet
DIT4096 Product data sheet
SBOS225B
Additional Documentation
The following document provides information regarding selected non-TI components that are used in the
assembly of the DEM-DAI3793A/3794A EVM. This document is available from the corresponding
manufacturer.
Device/Document
LC89052
Manufacturer
Sanyo Corporation
If You Need Assistance
If you have questions regarding either the use of this evaluation module or the information contained in the
accompanying documentation, please contact the Texas Instruments Product Information Center at (972)
644–5580 or visit the TI web site at www.ti.com.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense is required to
take whatever measures may be required to correct this interference.
Trademarks
All trademarks are the property of their respective owners.
10
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Chapter 1
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Description
The DEM-DAI3793A/3794A EVM is a complete evaluation platform for the PCM3793A/PCM3794A 16-bit,
low-power stereo audio codec with microphone bias, headphone, and digital speaker. All necessary
connectors and circuitry are provided for interfacing to audio test systems and commercial audio
equipment.
Topic .................................................................................................. Page
1.1
1.2
1.3
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Introduction—PCM3793A/94A
1.1 Introduction—PCM3793A/94A
The PCM3793A/94A is a low-power stereo codec designed for portable digital audio applications. The
device integrates a stereo digital speaker amplifier, headphone amplifier, line amplifier, line input, boost
amplifier, microphone bias, programmable gain control, analog mixing, sound effects, and automatic level
control (ALC) features. (The PCM3794A has no speaker amplifiers.)
It is available in a 5 × 5 QFN package to reduce the overall device footprint. The PCM3793A/94A accepts
Right-Justified, Left-Justified, I2S™, and digital signal processing (DSP) formats, providing an easy
interface to audio DSPs, as well as decoders and encoder chips. Sampling rates up to 50kHz are
supported. The user-programmable functions are accessible through a two- or three-wire serial control
port.
1.1.1 Key Features
Major features of the PCM3793A/94A include:
•
Analog Front End:
–
–
–
–
Stereo single-ended input with multiplexer (mux)
Mono differential input
Stereo programmable gain amplifier (PGA)
Microphone amplifier (20dB) and bias
•
•
Analog Back End:
–
–
–
Stereo/Mono line output with volume
Stereo/Mono headphone amplifier with volume and capless mode
Stereo/Mono digital speaker amplifier (BTL) with volume
Analog Performance:
–
–
–
–
Dynamic range: 93dB (digital-to-audio converter [DAC])
Dynamic range: 90dB (analog-to-digital converter [ADC])
40mW + 40mW headphone output at RL = 16Ω
700mW + 700mW speaker output at RL = 8Ω
•
•
Power Supply Voltage
–
–
–
–
1.71V to 3.6V for digital I/O section
1.71V to 3.6V for digital core section
2.4V to 3.6V for analog section
2.4V to 3.6V for power amplifier section
Low Power Dissipation:
–
–
–
7mW in playback, 1.8V/2.4V, 48kHz
13mW in record, 1.8V/2.4V, 48kHz
3.3μW in power-down
•
•
•
•
Sampling Frequency: 5kHz to 50kHz
Automatic Level Control for Recording
Operation From a Single Clock Input without PLL
System Clock:
–
Common-audio clock (256fS/384fS), 12MHz/24MHz, 13MHz/26MHz, 13.5MHz/27MHz,
19.2MHz/38.4MHz, 19.68MHz/39.36MHz
•
•
Headphone Plug Insert Detection
I2C™ or SPI™ Serial Control
12
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Introduction—PCM3793A/94A
blank
•
Programmable Function by Register Control:
–
–
–
–
–
–
–
–
–
–
–
–
Digital attenuation of DAC: 0dB to –62dB
Digital gain of DAC: 0dB, 6dB, 12dB, 18dB
Power up/down control for each module
6dB to –70dB gain for analog outputs
30dB to –12dB gain for analog inputs
0dB/20dB selectable for microphone input
0dB to –21dB gain for analog mixing
Parameter settings for ALC
Three-band tone control and 3D sound
High-pass filter: 4Hz, 120Hz, 240Hz
Two-stage programmable notch filter
Analog mixing control
•
•
•
•
Pop-Noise Reduction Circuit
Short and Thermal Protection Circuit
Package: 5mm × 5mm QFN Package
Operating Temperature Range: –40°C to +85°C
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Pin Assignments and Terminal Functions
1.2 Pin Assignments and Terminal Functions
Figure 1-1 and Figure 1-2 show the pin assignments for the PCM3793A/94A. Table 1-1 lists the terminal
functions.
PCM3793ARHB
(TOP VIEW)
PCM3794ARHB
(TOP VIEW)
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
25
16
15
14
13
12
11
10
9
25
16
15
14
13
12
11
10
9
AIN2L
HPOR/LOR
SPOLP
AIN2L
HPOR/LOR
26
27
28
29
30
31
32
26
27
28
29
30
31
32
NC
AIN1R
AIN1L
AIN1R
AIN1L
SPOLN
NC
MODE
MS/ADR
MD/SDA
MC/SCL
LRCK
MODE
MS/ADR
MD/SDA
MC/SCL
LRCK
PGND
PGND
VPA
VPA
SPORP
SPORN
HPCOM/MONO
NC
NC
HPCOM/MONO
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Figure 1-1. PCM3793A Pin Assignments
Figure 1-2. PCM3794A Pin Assignments
Table 1-1. PCM3793A/94A Terminal Functions
TERMINAL
NAME
PCM3793ARHB
PCM3794ARHB
I/O
DESCRIPTION
AGND
19
27
26
25
24
23
22
1
19
27
26
25
24
23
22
1
–
I
Ground for analog
AIN1L
Analog input 1 for L-channel
Analog input 1 for R-channel
Analog input 2 for L-channel
Analog input 2 for R-channel
Analog input 3 for L-channel
Analog input 3 for R-channel
AIN1R
I
AIN2L
I
AIN2R
I
AIN3L
I
AIN3R
I
BCK
I/O Serial bit clock
DGND
6
6
–
I
Digital ground
DIN
2
2
Serial audio data input
DOUT
3
3
O
I
Serial audio data output
HDTI
8
8
Headphone plug insertion detection
Headphone common/mono line output
Headphone/lineout for R-channel
Headphone/lineout for L-channel
HPCOM/MONO
HPOL/LOL
HPOR/LOR
LRCK
9
9
O
O
O
17
16
32
31
30
21
28
29
13
17
16
32
31
30
21
28
29
13
I/O Left and right channel clock
Mode control clock for three-wire/two-wire interface
I/O Mode control data for three-wire/two-wire interface
MC/SCL
MD/SDA
MICB
I
O
I
Microphone bias source output
MODE
MS/ADR
PGND
Two- or three-wire interface selection (low: SPI; high: I2C)
Mode control select for three-wire/two-wire interface
Ground for speaker power amplifier
I
–
14
Description
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DEM-DAI3793A/3794A EVM Description
Table 1-1. PCM3793A/94A Terminal Functions (continued)
TERMINAL
NAME
PCM3793ARHB
PCM3794ARHB
I/O
I
DESCRIPTION
SCKI
SPOLN
SPOLP
SPORN
SPORP
VCC
7
7
–
System clock
14
15
10
11
20
18
5
O
O
O
O
–
Speaker output L-channel for negative (PCM3793A only)
Speaker output L-channel for positive (PCM3793A only)
Speaker output R-channel for negative (PCM3793A only)
Speaker output R-channel for positive (PCM3793A only)
Analog power supply
–
–
–
20
18
5
VCOM
VDD
–
Analog common voltage
–
Power supply for digital core
VIO
4
4
–
Power supply for digital I/O
VPA
12
12
–
Power supply for power amplifier
1.3 DEM-DAI3793A/3794A EVM Description
The DEM-DAI3793A/3794A evaluation module permits user control of the entire PCM3793A/94A system.
The EVM allows users to test playback with and without digital input; recording through digital input/output
with an optical cable or RCA jacks; a line input/output; stereo speaker output (PCM3793A only);
Figure 1-3. DEM-DAI3793A/3794A EVM System Diagram
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Description
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Chapter 2
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Getting Started
This chapter provides information regarding DEM-DAI3793A/3794A EVM handling and unpacking,
absolute operating conditions, and a description of the factory default switch and jumper configuration.
Topic .................................................................................................. Page
2.1
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Electrostatic Discharge Warning
2.1 Electrostatic Discharge Warning
Many of the components on the DEM-DAI3793A/3794A EVM are susceptible to damage by electrostatic
discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking
and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
CAUTION
Failure to observe ESD handling procedures may result in damage to EVM
components.
2.2 Unpacking the EVM
Upon opening the DEM-DAI3793A/3794A EVM package, please check to make sure that the following
items are included:
•
•
•
One DEM-DAI/LPC-USB (Motherboard)
If any of these items are missing, please contact the Texas Instruments Product Information Center
nearest you to inquire about a replacement.
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Default Configuration
2.3 Default Configuration
Figure 2-1 and Figure 2-2 illustrate the default EVM configuration and the default external equipment
connection configuration, respectively.
Figure 2-1. EVM Configuration
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Default Configuration
Figure 2-2. EVM and External Equipment Connections
The factory default configuration for the DEM-DAI3793A/3794A EVM is listed below.
Motherboard:
•
•
CN101, CN102: Connect dc power supply positive lead (+) to CN101 and negative lead (–) to CN102
SW301: Set Opt or Coax output for the proper cable connection
Daughter Card #1 (DEM-PCM3793RHB-A):
•
•
JP14, JP15, JP16, JP17, and JP19: these jumper pins should not be used
Daughter Card #2 (DEM-TRVC/LPC):
•
•
•
SW001: Set Opt or Coax for S/PDIF input to DIR:LC89052T
SW002: Set to silkscreen SW002 RESET side (releasing reset)
SW003: Set X’tal to use onboard crystal oscillator
There is no need to change the setting of the shorting plugs for basic operation. Jumper settings strongly
depend on the audio interface.
20
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Chapter 3
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Set-Up Guide
This chapter discusses how to set up the DEM-DAI3793A/3794A EVM and describes the EVM software.
Topic .................................................................................................. Page
3.2
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Basic Operating Set-Up
3.1 Basic Operating Set-Up
Follow these steps to set up the DEM-DAI3793A/3794A EVM for operation.
Step 1. When using the kit for the first time, install the TUSB3410 VCP (Virtual COM Port) driver to
the host PC. To install the driver, refer to the Virtual COM Port Driver Installation
Instructions.pdf located in the DEM-DAI3793 folder of the software CD or available through
Step 2. Connect the audio signal sources and/or receiver, using one of these connections:
•
•
S/PDIF cable (optical or coaxial)
Analog input/output (RCA)
Step 3. Connect microphone, speakers, headphone, an audio amplifier, or measurement equipment,
if necessary.
Step 4. Confirm that jumpers CN103–CN107 are shorted.
Step 5. Connect the USB cable between the host PC and the motherboard (CN201).
Step 6. Apply +6V to +10V to the motherboard (CN101, CN102 for power supply).
Step 7. Execute EVM3793A.exe.
When the installation is complete, the EVM software is ready to use.
3.2 Software Control and Operation
This section of the user's guide reviews the operation and configuration of the EVM controller software.
3.2.1 User Interface Panel
After finishing the installation process (as explained in Section 3.1), the user interface panel shown in
Figure 3-1. User Interface Window
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Software Control and Operation
Check to see that a Ready notation appears in the lower left-hand corner after successful I2C
communication is established. Otherwise, you will see an error box showing a communication error (as
Figure 3-2. Communication Error Message
If you received this message, confirm the set-up procedures and restart the software. Shut it down and
then execute EVM3793A.exe.
•
•
•
•
Module controller, for functions such as playback, signal processing, audio format, and so forth;
Power on/off sequence controller
Register setting history controller
Register direct access controller
3.2.2 Power On/Off Sequence
By default, each module is set without any of the checkboxes toggled in the Power Up/Down menu. All
modules are set to a power-down condition.
powering up the module manually.
Figure 3-3. Power On/Off Sequence Function Buttons
Note: If pressing the Power On/Off sequence button has no effect, check to see that the two
files power_on.csv and power_off.csv are located in the same folder on the PC as the
EVM software (EVM3793A.exe).
3.2.3 Module Function Controls
The DEM-DAI3793A/3794A EVM controller software contains 10 tabs:
•
•
•
•
•
•
•
•
•
•
Power Up/Down: to power up and power down each module
Record: executes gain control for ADC input
Playback: executes headphone/speaker gain control and digital ATT
ALC: tunes the Automatic Level Control function
Audio Interface: selects the audio interface for ADC and DAC
Status Detect: controls headphone short detection and speaker thermal protection
This section discusses each of these tab operations and controls.
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Software Control and Operation
3.2.3.1 Power Up/Down
the appropriate checkboxes to power up or power down a specific module. Table 3-1 shows the register
mapping for each module setting.
Abbreviations such as DAL/DAR, MXL/MXR, and ADL/ADR stand for corresponding modules that are
Figure 3-4. Internal Module Power Up/Down Function Menu Tab
Table 3-1. Register Mapping for Power Up/Down Module
Check Box
Internal Module
Register
Reg#73 bit7 [PBIS]
Analog Bias
Vcom
Analog bias
Analog common voltage
Headphone common/mono-out buffer
Analog mixer L-ch
Reg#74 bit0 [PCOM]
Reg#73 bit4 [PHPC]
Reg#72 bit0 [PMXL]
Reg#72 bit1 [PMXR]
Reg#73 bit2 [PHPL]
Reg#73 bit3 [PHPR]
Reg#73 bit5 [PDAL]
Reg#73 bit6 [PDAR]
Reg#73 bit0 [PSPL]
Reg#73 bit1 [PSPR]
Reg#82 bit0 [PADL]
Reg#82 bit1 [PADR]
Reg#82 bit4 [PAIL]
Reg#82 bit5 [PAIR]
Reg#82 bit3 [PADS]
Reg#82 bit2 [PMCB]
HP COM/MONO (HPC)
Mixer L-ch (XML)
Mixer R-ch (XMR)
Analog mixer R-ch
HP/Line out L-ch (HPL)
HP/Line out R-ch (HPR)
DAC L-ch (DAL)
Headphone / Line out amp L-ch
Headphone / Line out amp R-ch
DAC and interpolation filter L-ch
DAC and interpolation filter R-ch
Speaker amp L-ch
DAC R-ch (DAR)
Speaker out L-ch (SPL)
Speaker out R-ch (SPR)
ADC L-ch (ADL)
Speaker amp R-ch
ADC and decimation filter L-ch
ADC and decimation filter R-ch
Gain amp L-ch (PG1 and PG5)
Gain amp R-ch (PG2 and PG6)
D2S for AIN1
ADC R-ch (ADR)
Gain AMP L-ch (PG1, PG5)
Gain AMP R-ch (PG2, PG6)
Diff amp (D2S)
Mic Bias (MCB)
Mic bias amp
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Power Up/Down Time (ms) Options
Power Up/Down Time (ms) Options
It is possible to select the VCOM ramp up/down time from GND level to a common voltage level or
vice-versa by choosing a VCOM capacitor value and time by choosing one of the available checkboxes. A
4.7μF VCOM capacitor is chosen as the default setting (this capacitor is also mounted on the EVM).
The 4.7μF VCOM capacitor is the recommended value for operating the EVM. This configuration is the
To select a different VCOM value, choose the appropriate value from the VCOM capacitor drop-down menu.
Be sure to change the capacitor on the EVM to the same value (1.0μF, 2.2μF or 10μF).
The combination of PTM[1:0] and RES[4:0] determines the VCOM ramp up/down time, as described in
To set the ramp up or down time without directly accessing the registers, users can select a VCOM
capacitor value and time in the group box. The ramp up waveform with the default setting is shown in
Table 3-2. PCM3793A/94A Resistor 125(7dh)
RES[4:0]: Resistor Value Control
RES [4:0]
VCOM Resistor Value
10000
11000
11100
11110
Others
60 kΩ
24 kΩ
12 kΩ
6 kΩ
Reserved
Table 3-3. PCM3793A/94A Resistor 125(7dh) PMT[1:0]: Power Up/Down Time Control and
Register Direct Access
VCOM Capacitor
Power-Up Time
[ms]
Power-Down Time
[ms]
Register Direct
Access
[μF]
RES[4:0]
11110
PTM[1:0]
10
00
11
450
750
0x7D1E
11100
11000
10000
11110
11100
11000
10000
11110
11100
11000
10000
11110
11100
11000
10000
900
—
1500
—
0x7D7C
—
Do not set
Do not set
—
—
—
4.7
2.2
1.0
01
250
450
900
—
400
750
1500
—
0x7D3E
0x7D1C (default)
0x7D78
—
00
11
Do not set
10
100
250
450
900
—
300
400
750
1500
—
0x7D5E
0x7D3C
0x7D18
0x7D70
—
01
00
11
Do not set
10
01
00
100
250
450
300
400
750
0x7D5C
0x7D38
0x7D10
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Power Up/Down Time (ms) Options
Figure 3-5. Ramp Up Wave Form with Default
Setting
Figure 3-6. Ramp Down Wave Form with
Default Setting
3.2.3.2 Record
Figure 3-7. Record Function Menu Tab
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Gain Control for ADC Input Options
PCM3794A has no Speaker Output
3
Module of Possible Power Up/Down
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
Clock
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Serial Interface (SPI/I2C)
Manager
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
1
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
2
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure 3-8. EVM Modules Corresponding to Record Function
Gain Control for ADC Input Options
Move the L-ch (PG3) and R-ch (PG4) sliders to adjust the gain of the incoming analog signal inputs to the
ADC.
•
•
The L-ch slider manipulates the programmable gain amp (PG3) placed in front of the ADC.
The R-ch slider controls the programmable gain amp (PG4) placed in front of the ADC.
Digital Mute (ATR) Options
Click the respective Digital mute (ATR) checkboxes if a mute function is needed for the ADC digital output.
•
•
The mute checkbox enables a digital soft mute on the ADC for each channel.
Mute waiting control enables a mute control.
Digital Out Mute Control Options
Select the Digital out mute control drop-down menu to enable the mute time control.
•
Apply wait or no wait for the ADC mute.
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Headphone Gain Control Options
PCM3794A has no Speaker Output
9
Module of Possible Power Up/Down
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
7
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
8
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
4
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
5
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
6
Figure 3-10. Modules Corresponding to Playback Function
Headphone Gain Control Options
Move the L-ch (HPL) and R-ch (HPR) sliders to adjust the gain of the analog output from the headphone
amplifier.
Select the Output configuration drop-down menu to select either stereo or mono output.
•
•
•
•
The L-ch slider controls the Headphone/Line amp gain
The R-ch slider controls the Headphone/Line amp gain
Select the output channel to be stereo, mono (single-ended), or mono (differential)
The HP com drop-down list determines the HPCOM/MONO pin function.
Speaker Gain Control Options
Move the L-ch (SPL) and R-ch (SPR) sliders to adjust the gain of the analog output from the speaker
amplifier.
Select the Output configuration drop-down menu to select either stereo or mono output.
•
•
•
The L-ch slider controls the speaker amp gain
The R-ch slider controls the speaker amp gain
Select the output channel to be either stereo or mono
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Digital Attenuation (ATP) Options
Digital Attenuation (ATP) Options
Move the L-ch and R-ch sliders to adjust the gain of the incoming digital signals prior to conversion by the
DAC.
•
•
•
•
The L-ch slider adjusts the DAC digital attenuator level
The R-ch slider controls the DAC digital attenuator level
Select the output channel to be either stereo or mono
The digital boost option enables a gain control of 0dB, +6dB, +12dB, or +18dB for the DAC digital input
3.2.3.4 ALC (Automatic Level Control)
Figure 3-11. ALC Function Menu Tab
Auto Level Control (Record) Options
Select Recovery time and Attack time using the respective drop-down menu and corresponding gain
control for each option to use the automatic level control function.
Compression is defined as avoiding degradation of sound quality by saturation when there are strong
or excessively large sound data input.
Expansion means to boost weak or low input data in order to adjust the moderate amplitude level for
recording.
0dB
Compression
(-2dB, -6dB, -12dB)
Expansion
(0dB, +6dB, +14dB, +24dB)
0dB
Input Amplitude
Figure 3-12. ALC Compression and Expansion Characteristics
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Source Options
3.2.3.5 Signal Processing I
Figure 3-13. Signal Processing 1 Function Menu Tab
Source Options
Select the Source input to choose either the audio processing unit digital input (DAC) or digital output
(ADC). Internal audio processing can be applied to either the DAC or the ADC. This option also allows
users to choose an audio source.
Output Options
Select the Source drop-down menu to choose between a stereo or mono configuration.
The output configuration can be selected by choosing stereo or mono.
•
Tone Control Options
Move the Bass, Mid, and Treble sliders to adjust the tone control gain. The tones are controlled by the
15
10
5
0
-5
-10
-15
10
100
1k
10k
100k
Frequency (Hz)
Figure 3-14. Three-Band Tone Control (Bass, Mid, Treble)
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3D Effect Options
3D Effect Options
By implementing a 3D effect in this option box, the PCM3793A is enabled to provide 3D sound to the
headphone and speaker outputs with low power consumption during either ADC or DAC operation. Check
the 3D effect, then select an Effect type and an Efficiency drop-down menu to obtain the desired 3D
enhancement.
Effect type means the selection of a band-pass filter (BPF); the BPF filters the sound, and enables a high
percentage of heavy 3D enhancements to be applied to the signal.
Effect type and efficiency are controlled through the use of checkboxes.
Notch Filter 1 Coefficient, Notch Filter 2 Coefficient Options
In some applications, incoming noise such as motor control noise, CCD noise and other mechanical noise
may not be negligible. The PCM3793A provides a very useful function to reduce such interference with the
notch filter function.
When the checkbox of Notch Filter 1 Coefficient or Notch Filter 2 Coefficient is checked, coefficient a1 and
a2 of the notch filter can be programmed at each edit box.
Load the values of fc, fb and fS into the Filter Calculator group box.
Click Apply to Filter 1 or Apply to Filter 2. The calculated coefficient will then appear in the a1 and a2 edit
box.
Finally, click the Update button for each Notch filter coefficient. To complete the notch filter operation, the
Update button must be clicked.
Note that Update step is required each time new or different parameters are loaded to the dialog box.
Follow these steps to update the notch filter coefficient:
Step 1. Click the checkbox of Notch Filter 1 Coefficient or Notch Filter 2 Coefficient.
Step 2. Input the parameter values fc, fb and fS.
Step 3. Click Apply to Filter 1 or Apply to Filter 2.
Step 4. Update for each notch filter coefficient.
Each coefficient is calculated using the following equations.
a1 = –(1 + a2)cos(ωo)
a2 = [1 – tan(ωb/2)] / [1 + tan(ωb/2)]
where:
•
•
•
•
•
fS = sampling frequency
fc = center frequency
fb = bandwidth
ωo = 2πfc/fS represents the angular center frequency
ωb = 2πfb/fS is the parameter to adjust bandwidth
Given: fS = 16kHz, fc = 0.5kHz, fb = 0.2kHz
a2 = 0.924390492 (converted decimal to hex: 3B29h)
a1 = –1.887413868 (converted decimal to hex: 8735h)
a2: F[215:208] = 3Bh, F[207:200] = 29h
a1: F[115:108] = 87h, F[107:100] = 35h
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Notch Filter 1 Coefficient, Notch Filter 2 Coefficient Options
Figure 3-15 illustrates the notch filter characteristic. All users can select any frequencies that can be used
by the application system based on the notch filter coefficient theory discussed here.
fc: Center Frequency
0dB
-3dB
fb: Bandwidth Frequency
Frequency (Hz)
Figure 3-15. Notch Filter Characteristic Model
Figure 3-16. Example of Measured Notch Filter Characteristic
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DAC Oversampling Control Options
3.2.3.6 Signal Processing 2
Figure 3-17. Signal Processing 2 Function Menu Tab
DAC Oversampling Control Options
Select the DAC oversampling control menu to determine the DAC oversampling rate. The oversampling
control can be set to either 128fS or a range of 192fS, 256fS, and 384fS.
The DAC oversampling rate range (for 192fS, 256fS, and 384fS) will be selected when the sampling
frequency of input data is lower than 24kHz. This oversampling rate moves the out-of-band noise caused
by the delta-sigma modulator to a higher frequency domain.
Zero Cross Control Options
Select the Zero cross control to enable the zero crossing function. When zero crossing is enabled, digital
attenuation and the analog volume level change at the zero crossing point to avoid an audible zipper
noise.
De-Emphasis Filter Options
Select the De-emphasis filter option menu to enable the de-emphasis filter. De-emphasis can be disabled
or enabled for an appropriate sampling frequency.
High-Pass Filter Options
Choose the High Pass Filter menu to determine the center frequency (fc) of the incoming analog signal
inputs to the ADC.
The cutoff frequency of the ADC high-pass filter is provided as a sampling frequency of 48kHz in this drop
down menu, so that the cutoff will be scaled down to the corresponding value when sampling frequencies
other than 48kHz (such as 16kHz or 22.05kHz) are used.
The ADC high-pass filter cutoff frequency can be set from this option.
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Analog Input Options
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
14
16
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
10
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
12
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
11
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
13
15
17
Switches SW1 to SW6
Figure 3-19. Modules Corresponding to Analog Path Function
Analog Input Options
This option selects the appropriate MUX for the respective left or right channel.
•
•
MUX1 selects the L-channel source (AIN1/AIN2/AIN3).
MUX2 selects the R-channel source (AIN1/AIN2/AIN3).
D2S Select Options
The analog input can be configured as single-end or differential. Select the D2S drop-down menu to
choose between differential or single-ended inputs. If differential is selected, AIN1L and AIN1R are used
as differential inputs.
Analog Mixer Options
The analog input, DAC output, and other channels of the analog input can be combined as an analog
mixer source. To combine the sources, select the Analog Mixer menu to combine the DAC output and
incoming stereo or mono analog signal input through PG1/PG5 or PG2/PG6.
Mic Boost Options
This checkbox sets (or resets) the +20dB microphone pre-amp PG1 (L-ch) or PG2 (R-ch).
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PG5 Gain and PG6 Gain Options
PG5 Gain and PG6 Gain Options
PG5 gain (for the left channel) or PG6 (for the right channel) can be adjusted from the available
drop-down menu.
3.2.3.8 Audio Interface
Figure 3-20. Audio Interface Function Menu Tab
Audio Interface Setting 1 Options
Use this section of the menu to set the audio data format for the DAC input and ADC output, and set the
mode as Master or Slave. Bit length is fixed at 16 bits.
Audio Interface Setting 2 Options
Use this section of the menu when working in Master mode.
•
•
•
MSR: sets system clock rate
NPR: sets system clock divider rate
BCK: chooses between normal and burst BCK output
Burst operation of BCK in master mode will contribute to greater overall reduction in power consumption.
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HP Detection Options
3.2.3.9 Status Detect
Figure 3-21. Status Detect Function Menu Tab
HP Detection Options
Use this section of the menu to enable or disable the HP insertion detection process. You can also the
HDTI pin logical polarity using the drop-down list box.
HP COM Short Detection Options
This section of the menu allows you to enable or disable HP COM port short detection. When short
detection recovery is set to Release, the status bit will automatically reset to '0'.
HP Short Detection, L-Ch; HP Detection, R-Ch
These sections of the menu enable or disable HP short detection for the left channel and right channel,
respectively. When short detection recovery is set to Release, the status bit will automatically reset to '0'.
Speaker Short Detection, L-Ch; Speaker Short Detection, R-Ch
These menu sections enable or disable speaker short detection for the left channel and right channel,
respectively. When short detection recovery is set to Release, the status bit will automatically reset to '0'.
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Speaker Short Detection, L-Ch; Speaker Short Detection, R-Ch
3.2.3.10 Digital Amplifier
Figure 3-22. Digital Amplifier Function Menu Tab
Setting the operating speed of the Class-D speaker amplifier depends on the performance requirements;
click the checkbox to enable this function. Spectrum Spreading control (with Low, Mid, or High options)
and the Switching frequency (1.5MHz to 3MHz) can be selected here. Using this feature will help reduce
EMI noise. As the spectrum spreading control moves to high, the effect will be remarkable. Note, however,
that the signal-to-noise ratio (SNR) performance of the speaker output is affected by this function.
3.2.4 LC89052T (DIR: Digital Audio I/F Receiver) Control Window
Figure 3-23. LC89052 Interface Format Selection Options
3.2.4.1 Audio Clock/Data Control Options
There are several options available for the audio clock and data control features in the
DEM-DAI3793A/3794A EVM software.
For the system audio clock control, users can select any of these options:
•
•
•
PLL SCK: Selects the system clock rate for the PCM3793A.
XIN SCK or E-SCK: Selects the crystal oscillator frequency on Daughter Card #2
CKOUT Div: Selects the dividing rate for CKOUT
The serial audio data format is controlled by the other part of the drop-down menu; see Figure 3-23.
Select the data format for the DAC interface of the PCM3793A (it should match with the DAC setting on
the Audio Interface tab).
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Speaker Short Detection, L-Ch; Speaker Short Detection, R-Ch
3.2.5 Register Setting History
When any checkboxes are selected on any tab of the software GUI (including power up/down operation,
corresponding resistor address, and so forth), the register value is automatically written into the register
setting history panel. These parameters can then be saved, allowing users to identify a particular
sequence setting that was sent to the device under test.
Any operating sequence settings can be saved as a comma-separated value (*.csv) file, with an
identifiable name. This archive feature is useful when the same sequence settings are required for
continued testing. The list of available *.csv files refreshes and displays when the Clear button is clicked.
Figure 3-24. Register Setting History Window
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Speaker Short Detection, L-Ch; Speaker Short Detection, R-Ch
3.2.5.1 Modifying a .csv File
The .csv file stores a sequence of register settings for the PCM3793A. To load a given register setting, it
should be written in hex code, as shown in Figure 3-25; use the left row for resistor addresses and the
right row for resistor values.
Figure 3-25. Opening and Modifying a .csv File
A sleep line can be inserted for implementing an interval (or wait) time until executing the next line of the
file. If the cell is blank, no wait time will be executed. Files can be imported and exported using the Open
script and Save register snapshot options.
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Speaker Short Detection, L-Ch; Speaker Short Detection, R-Ch
3.2.6 Register Direct Access
Read function:
The Read function is only available in I2C mode. The register value can be read in I2C mode. To read
the value, enter the Address number (in hex code format) in the left box and click the Read button.
Data corresponding to the address appears.
Write function:
This window also enables the user to write the register value directly. Enter the Address number and
data (both in hex code format) in the respective fields and click the Write button.
Figure 3-26. Register Direct Access Dialog
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Chapter 4
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Switches and Connectors
This chapter reviews the DEM-DAI3793A/3794A EVM switch and jumper configuration.
Topic .................................................................................................. Page
4.3
4.4
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Overview
4.1 Overview
Note: Silkscreen symbol CN320 is not printed on the motherboard, but it is located in the position described.
Figure 4-1. EVM Configuration
4.2 Motherboard
motherboard.
Table 4-1. Main Power Supply and Regulator
Connectors
CN101
CN102
Main Power Supply and Regulator
+6V to 10V Main Power Supply
GND
Table 4-2. Power-Supply Terminals for PCM3793A
Power-Supply Pins
Connectors
CN103
PCM3793A Power-Supply Pins
VPA
CN104
CN105
CN106
CN107
Not used. Do not care about short or open.
VCC
VDD
VIO
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Motherboard
Table 4-3. Audio I/O
Connectors
Audio I/O Pins
CN108
CN109
CN110
CN111
CN112
CN113
CN114
Analog audio input for AIN3L
Analog audio input for AIN3R
Analog audio output for HPOL/LOL
Analog audio output for HPOR/LOR
Analog audio output for HPCOM/MONO
Not used
Analog audio input for AIN1L/AIN2L (Selected by JP12:1-2 for
AIN1L, 2-3 for AIN2L on Daughter Card #1)
CN115
Analog audio input for AIN1R/AIN2R (Selected by JP13:1-2 for
AIN1R, 2-3 for AIN2R on Daughter Card #1)
CN116
CN117
U301
Not used
Not used
TOSLINK™. S/PDIF Optical output
S/PDIF coaxial output
CN301
SW301
U302
Toggle switch. Opt/Coax selector for S/PDIF output
TOSLINK. S/PDIF Optical output
S/PDIF coaxial input
CN302
CN305
2x9 header pins to connect digital audio I/F for ADC/DAC. If using
external signal source, all shorting plugs should be removed.
CN306
CN307
BNC connector to provide external clock for LC89052T (DIR: S/PDIF
receiver) on Daughter Card or PCM3793 directly as E-SCK.
2x5 header pins. System clock and bit clock selection to provide
DIT4096 (DIT: S/PDIF transmitter).SCK and BCK should be provided
from LC89052T as initial setting.
CN308, CN309–CN316
CN317
2x9 header pins and SMA connecters (x8) for connecting digital
audio I/F with external devices or equipment. If using this feature, all
shorting plugs on CN305 should be removed.
3x10 header pins. Path of I2C/SPI-interface selection (via USB or
parallel port). Selected USB port for initial configuration. (Parallel
port is not available.)
CN320
2x3 header pins. Word (L/R) clock selection (Master or Slave mode).
Selected Slave mode as initial.
Table 4-4. I/F Controller (MSP430, TUSB3410)
Connectors
CN201
I/F Controller(MSP430, TUSB3410)
USB connector type-B
CN202
SW201
JTAG port
Push switch. RESET for MSP430/TUSB3410
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Daughter Card #1 (PCM3793A)
4.3 Daughter Card #1 (PCM3793A)
Table 4-5. Analog Input and Output—Daughter Card #1
Connectors
Analog Input and Output of Daughter Card #1
Stereo microphone input
J1
J2
Monaural microphone input
J3
Speaker output terminal for L-ch
Speaker output terminal for R-ch
Headphone output (Cap-less)
J4
J5
J6
Headphone output
JP5
JP8
JP9
JP10
JP11
JP12
JP13
JP18
System clock select. 1-2: External clock; 3-4: SPDIF
1-2: AIN1L / 2-3: JP10
1-2: AIN1R / 2-3: JP11
1-2: JP8 / 2-3: J2
1-2: J1 / 2-3: J2
Analog input select L-channel 1-2: AIN1L / 2-3: AIN2L
Analog input select R-channel 1-2: AIN1R / 2-3: AIN2R
Headphone detection select. 1-2: J5 or J6 / 2-3: Motherboard
Simplified descriptions of the analog input and output configuration for Daughter Card #1 are shown in
Connected to
AINL
CN114 of motherboard
Connected to
AINR
CN115 of motherboard
JP8 JP12
1
PCM3793A
JP10
2
1
AIN1L
AIN2L
L-Ch
1
3
2
2
J1
(Stereo mic)
3
3
R-Ch
JP9 JP13
1
JP11
2
L-Ch
1
AIN1R
AIN2R
1
3
2
2
J2
(Mono mic)
3
3
R-Ch
Connected to
AINL
AINR
CN108 of motherboard
Connected to
CN109 of motherboard
Figure 4-2. Analog Input Configuration (Daughter Card #1)
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Daughter Card #1 (PCM3793A)
PCM3793A
HPCOM/MONO
Connected to
CN112 of motherboard
MONO
SPOLN
SPOLP
J3
SPOUT (L-Ch)
SPORN
SPORP
J4
SPOUT (R-Ch)
LINE OUT
(L-Ch)
Connected to
CN110 of motherboard
LINE OUT
(R-Ch)
Connected to
CN111 of motherboard
J5
HPOUT (Cap-less)
J6
HPOUT
Figure 4-3. Analog Output Configuration (Daughter Card #1)
CAUTION
Do not insert a headphone to J5 and J6 at the same time. Doing so connects
resistors in parallel.
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Daughter Card #2 (DIR: LC89052T and DIT: DIT4096)
4.4 Daughter Card #2 (DIR: LC89052T and DIT: DIT4096)
Table 4-6. Analog Input and Output—Daughter Card #2
Connectors
Analog Input and Output of Daughter Card #2
Toggle switch. Opt/Coax selector for S/PDIF input
SW001
SW002
SW003
Toggle switch. Reset/Power-down LC89052T and DIT4096
Clock source selection for LC89052T (Onboard crystal oscillator or
external source from CN306 of motherboard)
SW004
SW005
DIP switch. Sets channel-status data of the DIT4096(1). Note that the
OFF state of this switch sets a HIGH level. Channel-status data can
be set up if needed. It is also possible to connect a microcontroller.
DIP switch. Sets the DIT4096 system clock and data format. Note
that the OFF state of this switch sets a HIGH level.
(1)
Table 4-7. Audio Clock and Input Data Control
Format—Daughter Card #2
CLK0
CLK1
System Clock
L
L
Not used
L
H
L
256fS (initial setting)
H
H
384fS
512fS
H
FMT0
FMT1
Input Data Format
L
L
24-bit, left-justified, MSB-first
24-bit, I2S (initial setting)
L
H
L
H
H
24-bit, right-justified, MSB-first
16-bit, right-justified, MSB-first
H
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Chapter 5
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Evaluation and Measurements
This chapter discusses how to set up jumpers on the DEM-DAI3793A/3794A EVM motherboard for
®
®
performance evaluation using the Audio Precision SYS-2722 or PSIA-2722 audio analyzers. The
process of measuring dynamic characteristics is then presented, along with example characteristic data.
Topic .................................................................................................. Page
5.1
5.2
5.3
5.4
5.5
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Slave Mode With Audio Precision SYS-2722 (Default Setting)
5.1 Slave Mode With Audio Precision SYS-2722 (Default Setting)
These jumper configurations for the DEM-DAI3793A/3794A EVM motherboard are the default device
managed.
SCKI
Clock
Manager
U302
CN302
ADC
DAC
BCK
LRCK
DIN
U301
DOUT
DIT: DIT4096
CN301
PCM3793A
Daughter card #2
Daughter card #1
Figure 5-1. Slave Mode Configuration With SYS-2722
To put the DEM-DAI3793A/3794A EVM motherboard into the default slave mode configuration, connect
the S/PDIF input and output to optical jumper U302 (or coaxial jumper CN302) and jumper U301 (or
jumper CN301). Then select SW301 and SW001, respectively. Refer to the jumper combination shown in
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Slave Mode With Audio Precision SYS-2722 (Default Setting)
CN305
T-SCLK
T-BCK
T-LRCK
TX-DATA
E-SCLK
R-SCLK
R-BCK
All short
R-LRCK
RX-DATA
CN307
E-SCK
SCK
from U003 (DIR: LC89052T) on Daughter Card #2
from U003 (DIR: LC89052T) on Daughter Card #2
Short plug
Short plug
T-SCLK
BCK
T-BCK
CN308
GND
T-SCK
T-BCK
T-LRCK
TX-DATA
R-SCLK
R-BCK
R-LRCK
RX-DATA
All open
CN320
Short plug
Short plug
Figure 5-2. Jumper Configuration for Slave Mode (Default)
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Master Mode with Audio Precision SYS-2722
5.2 Master Mode with Audio Precision SYS-2722
To enable the DEM-DAI3793A/3794A EVM motherboard for use in Master mode, the path of the S/PDIF
input to the PCM3793A through DIR is not available for use. LRCK and BCK change the respective output
states at the PCM3793A side in master mode; the respective jumpers of R-BCK, R-LRCK, and RX-DATA
should be removed from CN305 to avoid conflict between the input and output of these clocks.
Furthermore, in this situation, DIN to the PCM3793A is also invalid because DIR LC89052T does not
receive clocks (LC89052T cannot work in slave mode). Therefore, any analog output from the DAC is
invalid because there is no data input.
However, in this configuration, users can confirm master mode operation of both LRCK and BCK from
PCM3793A with a digital oscilloscope. Users can easily identify master mode without the use of other
external equipment such as the PSIA-2722 analyzer.
The PCM3793A has no integrated internal PLL. However, the clock manager function can provide LRCK
SCKI
Clock
Manager
U302
CN302
ADC
DAC
BCK
LRCK
DIN
U301
DOUT
DIT: DIT4096
CN301
PCM3793A
Daughter card #2
Daughter card #1
Isolated by
CN305
Figure 5-3. Master Mode Configuration With SYS-2722
into master mode configuration.
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Master Mode with Audio Precision SYS-2722
CN305
T-SCLK
T-BCK
T-LRCK
TX-DATA
E-SCLK
R-SCLK
R-BCK
Short plug
R-LRCK
RX-DATA
CN307
E-SCK
SCK
from U003 (DIR: LC89052T) on Daughter Card #2
Short plug
T-SCLK
BCK
from U003 (DIR: LC89052T) on Daughter Card #2
Short plug
T-BCK
CN308
GND
T-SCK
T-BCK
T-LRCK
TX-DATA
R-SCLK
R-BCK
R-LRCK
RX-DATA
All open
CN320
Short plug
Figure 5-4. Jumper Configuration for Master Mode
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Combined Master and Slave Modes With PSIA-2722
5.3 Combined Master and Slave Modes With PSIA-2722
modes of the PCM3793A at the same time without setup jumpers on the motherboard if the user has
access to the PSIA-2722 analyzer.
SCKI
Clock
Manager
PSIA-2722
ADC
BCK
DAC
Slave
Master
Slave
LRCK
Master
DIN
DOUT
PCM3793A
Daughter card #1
Figure 5-5. Combined Master and Slave Mode Configuration with SYS-2722
configuration.
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Measurements for Dynamic Characteristics
CN305
T-SCLK
T-BCK
T-LRCK
TX-DATA
E-SCLK
R-SCLK
R-BCK
All open
R-LRCK
RX-DATA
CN307
E-SCK
SCK
from U003 (DIR: LC89052T) on Daughter Card #2
Short plug
Short plug
T-SCLK
BCK
from U003 (DIR: LC89052T) on Daughter Card #2
T-BCK
CN308
GND
Short plug
T-SCK
T-BCK
T-LRCK
TX-DATA
R-SCLK
R-BCK
R-LRCK
RX-DATA
PSIA-2722
CN320
Short plug
Figure 5-6. Jumper Configuration for Combined Master and Slave Modes
5.4 Measurements for Dynamic Characteristics
Typical dynamic performance graphs for digital-to-analog converters (DACs) generally represent four
performance characteristics (in addition to other specifications): total harmonic distortion and noise
(THD+N); signal-to-noise ratio (SNR); dynamic range (DR); and channel separation. These graphs also
specify the test environment and measurement conditions required in order to meet typical performance
values defined in the product data sheet.
For the DEM-DAI3793A/3794A EVM, the evaluation environment specifications are:
•
•
•
•
•
Equipment used: Audio Precision, System Two Cascade Plus
Audio Data format: 16-bit Left-Justified
SCKI / BCK / LRCK (fS): 256fS / 64fS / 48 kHz
Power supply: VDD = VIO = VCC = VPA = 3.3V (Regulated down from 10V applied to the motherboard)
Temperature: Room/ambient
Once the lab or test environment is configured according to these parameters, start the EVM software (as
discussed in Section 3.2). Click All Power On in the startup window or execute power_on.csv, and then
execute the .csv file that corresponds to the appropriate measurement path discussed in the subsequent
sections of this chapter.
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Measurements for Dynamic Characteristics
5.4.1 Digital-to-Analog (D/A) Performance
Measurement path: 01.Line Output and Headphone Output
csv file: 01_DAC_Line_Output_and_Headphone_Output.csv
Table 5-1. D/A Line Output Parameters
Power Supply
3.3V
Parameter
Filter Setting
RL (kΩ)
10
LOL
LOR
THD+N (0dBFS at 1kHz)
SNR (BPZ input)
400Hz—20kHz AES-17
0.007%
93.1dB
0.008%
93.0dB
22Hz—20kHz SPCL +
A-weighting
10
DR (–60dBFS input)
22Hz—20kHz SPCL +
A-weighting
10
10
93.1dB
90.5dB
92.9dB
90.4dB
Channel Separation
(BPZ input for target
channel)
22Hz—20kHz AES-17
Table 5-2. 16Ω Headphone Output Inserted in Headphone Jack J6
Power Supply
3.3V
Parameter
Filter Setting
RL (Ω)
HPOL
HPOR
THD+N (40mW, HP
volume = –1dB)
400Hz—20kHz AES-17
16
0.028%
0.027%
SNR (BPZ input)
22Hz—20kHz SPCL +
A-weighting
16
16
93.1dB
93.4dB
93.0dB
93.1dB
DR (–60dBFS input)
22Hz—20kHz SPCL +
A-weighting
powered down, and other functions should be set with these parameters:
•
•
•
•
•
•
•
Speaker Amp: Disabled
ADC L-channel and ADC R-channel: Disabled
ALC: Off
Volume: 0dB
Analog mixing: Disabled
RL = 10kΩ for the line output
RL = 16Ω inserted in the J6 headphone jack for the headphone output
The bundled .csv file automatically sets the device to these conditions.
Note: The headphone volume should be changed from 0dB to –1dB and the signal input level of
the Audio Precision analyzer should be changed to 40mW output power when THD+N is
measured at 16Ω.
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Measurements for Dynamic Characteristics
5.4.2 Analog-to-Digital (A/D) Performance
Measurement path: 17.Line Input (AIN3L/AIN3R)
csv file: 17_ADC_Line_Input.csv
Table 5-3. A/D Line Input Parameters
Power Supply
3.3V
Parameter
Filter Setting
Left Channel
0.009%
Right Channel
0.009%
THD+N ( –1dB at 1kHz)
SNR (BPZ input)
400Hz—20kHz AES-17
22Hz—20kHz SPCL +
A-weighting
90.4dB
90.5dB
DR (–60dBFS input)
22Hz—20kHz AES-17 +
A-weighting
90.6dB
87.8dB
90.3dB
87.8dB
Channel Separation
22Hz—20kHz AES-17
(BPZ input for target channel)
To obtain the performance results shown in Table 5-3, the speaker/headphone module should be powered
down, and other functions should be set with these parameters:
•
•
•
•
•
•
Headphone and Speaker Amp: Disabled
DAC L-channel and DAC R-channel: Disabled
ALC: Off
Mic boost: 0dB
Analog mixing: Disabled
All PGA: 0dB
The bundled .csv file automatically sets the device to these conditions.
5.4.3 Speaker Output Power Performance
Measurement path: 07.Stereo Speaker Output
csv file: 07_DAC_Stereo_Speaker_Output_8ohms.csv
Table 5-4. Stereo Speaker Output Parameters
Power Supply
3.3V
Parameter
Speaker Volume
+6dB
RL (Ω)
SPOL
SPOR
Output Power
8
594.2mW
594.1mW
(THD+N = 10%)
and other functions should be set with these parameters:
•
•
•
•
•
Headphone Amp: Disabled
ADC L-channel and ADC R-channel: Disabled
Speaker volume: +6dB
ALC: Off
RL: 8Ω
The bundled .csv file automatically sets the device to these conditions, except for the speaker volume;
adjust the speaker volume to +6dB manually after the .csv file is loaded.
Note: Adjust the input signal level of the Audio Precision analyzer to meet the target THD+N =
10%.
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Measurements for Dynamic Characteristics
5.4.3.1 LC Low-Pass Filter
Daughter Card #2 provides an LC low-pass filter (LPF) to obtain a clean analog signal from the
pulse-width modulated (PWM) output of the speaker output. This configuration is shown in Figure 5-7.
Additionally, a snubber circuit is inserted into the signal line to achieve the best output power performance
by suppressing ringing in the PWM pulse; however, a snubber circuit will have negligible effects in the end
system.
SPOL
SPOR
J3
J4
Snubber Circuit
LC LPF
TP2
-
Audio
Analyzer
L1 22mH
(1)
SPOLN
SPOLP
J3
Differential
Input
L2 22mH
RL
R5
330W
R6
330W
8W
C8
0.82mF
C9
0.82mF
+
TP1
C11
2.2mF
C12
2.2mF
1
fC
=
» 37.5 [kHz]
2 ´ p ´ LC
Note (1): Same configuration at SPORN/SPORP
Figure 5-7. Speaker Output Filter Configuration
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Measurements for Dynamic Characteristics
5.4.4 Amplitude Versus Frequency Performance
5.4.4.1 A/D Spectrum
Measurement path: 17.Line Input (AIN3L/AIN3R)
csv file: 17_ADC_Line_Input.csv
Note that an unweighted filter and an AES17 bandwidth of 22Hz to 20kHz should be set to obtain precise
spectrum results.
AMPLITUDE vs FREQUENCY
BPZ (Zero Data) Input
AMPLITUDE vs FREQUENCY
0
-20
0
-20
-60dB Input
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 5-8. A/D Amplitude vs Frequency
Result: BPZ (Zero Data) Input
Figure 5-9. A/D Amplitude vs Frequency
Result: –60dB Input
AMPLITUDE vs FREQUENCY
0
-20
-1dB Input
-40
-60
-80
-100
-120
-140
0
5
10
15
20
Frequency (kHz)
Figure 5-10. A/D Amplitude vs Frequency
Result: –1dB Input
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Measurements for Dynamic Characteristics
5.4.4.2 D/A Spectrum
Measurement path: 01.Line Output and Headphone Output
csv file: 01_DAC_Line_Output_and_Headphone_Output.csv
Note that an unweighted filter and an AES17 bandwidth of 22Hz to 20kHz should be set to obtain precise
spectrum results.
AMPLITUDE vs FREQUENCY
BPZ (Zero Data) Input
AMPLITUDE vs FREQUENCY
0
-20
0
-20
-60dB Input
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
Figure 5-11. D/A Amplitude vs Frequency
Result: BPZ (Zero Data) Input
Figure 5-12. D/A Amplitude vs Frequency
Result: –60dB Input
AMPLITUDE vs FREQUENCY
AMPLITUDE vs FREQUENCY
Wide Range to 130kHz
0
-20
0dB Input
0
BPZ (Zero Data) Input
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
20
40
60
80
100
120
Frequency (kHz)
Frequency (kHz)
Figure 5-13. D/A Amplitude vs Frequency
Result: 0dB Input
Figure 5-14. D/A Amplitude vs Frequency
Result: Wide Range to 130kHz, BPZ (Zero
Data) Input
60
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Connection Diagram for Practical Applications
5.5 Connection Diagram for Practical Applications
The PCM3793A/94A Daughter Card has been configured to measure dynamic audio performance by
common audio analyzer equipment.
In a practical application (such as portable audio player or cellular phone), simple components set up as
To Regulator
(4) VIO
SCKI (7)
C8
BCK (1)
(5) VDD
C9
LRCK (32)
DIN (2)
(6) DGND
(20) VCC
DOUT (3)
C10
MS/ADR (29)
MD/SDA (30)
MC/SCL (31)
MODE (28)
(19) AGND
(12) VPA
C11
Low or High
(13) PGND
PCM3793A/94A
R3
(8) HDTI
R1 R2
MICB (21)
C12
(17) HPOL/LOL
(16) HPOR/LOR
C1
C2
C3
C4
C5
C6
Stereo
Headphone
AIN1L (27)
AIN1R (26)
AIN2L (25)
C13
Monaural
Line Output
(9) HPCOM/MONO
C14
AIN2R (24)
AIN3L (23)
R4
AIN3R (22)
VCOM (18)
(15) SPOLP
(14) SPOLN
C7
(11) SPORP
(10) SPORN
Figure 5-15. Basic Connection Diagram
Table 5-5. Recommended External Parts for Basic Connection Diagram
Component
Recommended Value
Component
Recommended Value
10μF–220μF
C1—C6
C7
1μF
C12, C13
C14
1μF–10μF
0.1μF
1μF–10μF
2.2kΩ
C8
R1, R2
R3
C9, C10
C11
1μF–4.7μF
4.7μF–10μF
33kΩ
R4
10kΩ
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Connection Diagram for Practical Applications
5.5.1 Filter Consideration for Speaker Output
For a practical application such as a portable audio player or cellular phone, a ferrite chip bead will be a
connections for headphone output and insertion detection.
B1
SPOLP/
SPORP
C15
B2
SPOLN/
SPORN
C16
Refer to the product data sheet for further information on this application circuit. C15 and C16 = 1nF, B1 and B2 Ferrite
Chip Bead : NEC/Tokin: N2012ZPS121.
Figure 5-16. Recommended Ferrite Bead Filter for Speaker Output
Conventional Mode
Capless Mode
VCC
VCC
HP Jack
HDTI
HP Jack
HDTI
HPOL
HPOR
PGND
HPOL
+
HPOR
+
PGND
HPCOM
HPCOM
Figure 5-17. Connection for Headphone Output and Insertion Detection
62
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Chapter 6
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Schematic, PCB Layout, and Bill of Materials
This chapter provides the electrical and physical layout information for the DEM-DAI3793A/3794A EVM.
The bill of materials is included for component and manufacturer reference.
Topic .................................................................................................. Page
6.2
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Schematics
6.1 Schematics
Figure 6-1. PCM3793A DEM-PCM3793RHB-A Connector (Daughter Card #1)
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Schematics
Figure 6-2. PCM3793A DEM-PCM3793RHB-A (Daughter Card #1)
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Printed Circuit Board Layout
6.2 Printed Circuit Board Layout
DEM-DAI3793A/3794A EVM.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing DEM-DAI3793A/3794A EVM
PCBs.
Figure 6-3. PCM3793A DEM-PCM3793RHB-A Board Layout—Silkscreen Side
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Printed Circuit Board Layout
Figure 6-4. PCM3793A DEM-PCM3793RHB-A Board Layout—Component Side
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Printed Circuit Board Layout
Figure 6-5. PCM3793A DEM-PCM3793RHB-A Board Layout—Inner Layer 2
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Printed Circuit Board Layout
Figure 6-6. PCM3793A DEM-PCM3793RHB-A Board Layout—Inner Layer 3
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Printed Circuit Board Layout
Figure 6-7. PCM3793A DEM-PCM3793RHB-A Board Layout—Solder Side
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Component List
6.3 Component List
Table 6-1. Bill of Materials
RefDes
Count
5
Description
Part Number
MFR
KOA
R3, R5, R6, R7,
R8
330Ω
CF1/4C-33ΩJ
CP1—CP4
4
0.1μF
GRM188F5E104ZA01D Murata
1
C8, C9, C13, C14
R4
4
1
2
4
2
1
2
4
0.82μF
100kΩ,
10kΩ
ECQV1H824J
CF1/4C-100kΩJ
CF1/4C-10kΩJ
R3A-16V100M
ECEV1HA010NR
R3A-50V10M
Nissei
KOA
R9, R10
C3, C4, C6, C10
C1, C2
KOA
10μF/16V
1μF
Elna
Panasonic
Elna
C5
1μF/50V
2.2kΩ
R1, R2
CF1/4C-2.2kΩJ
R3A-50V22M
KOA
C11, C12, C15,
C16
2.2μF/50V
Elna
C17, C18
L1—L4
2
4
220μF
R3A-4V2200M
22R223
Elna
22μH
Newport
Components
JP5
JP8—JP13, JP18
C7
1
7
1
4
2
2
2
1
2x2 Pin
3-Pin
A1-4PA-2.54DSA
A2-3PA-2.54DSA
R3A-25V47M
Hirose
Hirose
4.7μF/25V
Test Pin
Elna
TP1—TP4
J1, J2
LC-2-G
MAC8
HSJ1493-01-040
MKDSN1.5/2-5.08
HSJ1493-01-040
PCM3793A/94A
Hosiden
J3, J4
Phoenix Contact
Hosiden
J5, J6
U1
16-bit Stereo Audio Codec, 5mm x 5mm QFN, 32-pin
Texas Instruments
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Appendix A
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Reference .csv Files, Interfacing to DSPs, and Package
Information
Topic .................................................................................................. Page
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Reference .csv Files
A.1 Reference .csv Files
The .csv files are bundled with the DEM-DAI3793A/3794A EVM Controller. These files enable users to
execute register settings corresponding to the specific operating modes discussed in the product data
sheet by importing them into the software.
performed with the power_on.csv command; otherwise, these files will not work properly.
An All Active operation is recommended to start up the device, and can be executed by just clicking the All
Table A-1. .csv Files
Operating Mode
.csv File Name
All Power Down
All Active
power_off.csv
power_on.csv
Playback with Digital Input
01
02
03
04
05
06
Line Output and Headphone Output
01_DAC_Line_Output_and_Headphone_Output.csv
02_DAC_Headphone_Output_with_Sound_Effect.csv
03_DAC_Cap_Less_Headphone_Output.csv
Headphone Output with Sound Effect
Cap Less Headphone Output
Headphone Output with Line Input (AIN2L/AIN2R)
04_DAC_Headphone_Output_with_Line_Input.csv
Headphone Output with Mono Mic Input (AIN1L, +20dB) 05_DAC_Headphone_Output_with_Mono_Mic_Input.csv
Headphone Output with Mono Diff Mic Input
(AIN1L/AIN1R, +20dB)
06_DAC_Headphone_Output_with_Mono_Diff_Mic_Input.
csv
07
08
09
10
11
Stereo Speaker Output
07_DAC_Stereo_Speaker_Output.csv
Mono Speaker Output
08_DAC_Mono_Speaker_Output.csv
Speaker Output with Line Input (AIN2L/AIN2R)
Speaker Output with Mono Mic Input (AIN1L, +20dB)
09_DAC_Speaker_Output_with_Line_Input.csv
10_DAC_Speaker_Output_with_Mono_Mic_Input.csv
Speaker Output with Mono Diff Mic Input (AIN1L/AIN1R, 11_DAC_Speaker_Output_with_Mono_Diff_Mic_Input.csv
+20dB)
Playback without Digital Input
12
13
14
15
Line Input (AIN2L/AIN2R) to Headphone Output
12_Line_Input_to_Headphone_Output.csv
Mono Line Input (AIN2L) to Headphone Output
13_Mono_Line_Input_to_Headphone_Output.csv
14_Mono_Mic_Input_to_Headphone_Output.csv
15_Mono_Diff_Mic_Input_to_Headphone_Output.csv
Mono Mic Input (AIN1L, +20dB) to Headphone Output
Mono Diff Mic Input (AIN1L/AIN1R, +20dB) to
Headphone Output
16
Mono Mic Input (AIN1L, +20dB) to Speaker Output
16_Mono_Mic_Input_to_Speaker_Output.csv
Recording
17
18
19
20
21
22
23
Line Input (AIN3L/AIN3R)
17_ADC_Line_Input.csv
Mic Input (AIN1L/AIN1R, +20dB)
18_ADC_Mic_Input.csv
Mic Input (AIN1L/AIN1R, +20dB) with ALC
Mono Mic Input (AIN1L, +20dB)
19_ADC_Mic_Input_with_ALC.csv
20_ADC_Mono_Mic_Input.csv
Mono Mic Input (AIN1L, +20dB) with ALC
Mono Diff Mic Input (AIN1L/AIN1R, +20dB)
Mono Diff Mic Input (AIN1L/AIN1R, +20dB) with ALC
21_ADC_Mono_Mic_Input_with_ALC.csv
22_ADC_Mono_Diff_Mic_Input.csv
23_ADC_Mono_Diff_Mic_Input_with_ALC.csv
74
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Reference .csv Files
A
Related Signal Flow Diagrams
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-1. Line Output and Headphone Output
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-2. Headphone Output with Sound Effect
76
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-3. Cap-Less Headphone Output
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-4. Headphone Output with Line Input (AIN2L/AIN2R)
78
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-5. Headphone Output with Mono Mic Input (AIN1L, +20dB)
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-6. Headphone Output with Mono Diff Mic Input (AIN1L/AIN1R, +20dB)
80
Reference .csv Files, Interfacing to DSPs, and Package Information
SBAU127–July 2007
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-7. Stereo Speaker Output
SBAU127–July 2007
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Reference .csv Files, Interfacing to DSPs, and Package Information
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-8. Mono Speaker Output
82
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
SBAU127–July 2007
Submit Documentation Feedback
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-9. Speaker Output with Line Input (AIN2L/AIN2R)
SBAU127–July 2007
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Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-10. Speaker Output with Mono Mic Input (AIN1L, +20dB)
84
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
SBAU127–July 2007
Submit Documentation Feedback
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-11. Speaker Output with Mono Diff Mic Input (AIN1L/AIN1R, +20dB)
SBAU127–July 2007
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Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
85
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-12. Line Input (AIN2L/AIN2R) to Headphone Output
86
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
SBAU127–July 2007
Submit Documentation Feedback
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-13. Mono Line Input (AIN2L) to Headphone Output
SBAU127–July 2007
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Reference .csv Files, Interfacing to DSPs, and Package Information
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www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-14. Mono Mic Input (AIN1L, +20dB) to Headphone Output
88
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
SBAU127–July 2007
Submit Documentation Feedback
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-15. Mono Diff Mic Input (AIN1L/AIN1R, +20dB) to Headphone Output
SBAU127–July 2007
Submit Documentation Feedback
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
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www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-16. Mono Mic Input (AIN1L, +20dB) to Speaker Output
90
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
SBAU127–July 2007
Submit Documentation Feedback
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-17. Line Input (AIN3L/AIN3R)
SBAU127–July 2007
Submit Documentation Feedback
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
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www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-18. Mic Input (AIN1L/AIN1R, +20dB)
92
Reference .csv Files, Interfacing to DSPs, and Package Information
Download from Www.Somanuals.com. All Manuals Search And Download.
SBAU127–July 2007
Submit Documentation Feedback
www.ti.com
Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-19. Mic Input (AIN1L/AIN1R, +20dB) with ALC
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-20. Mono Mic Input (AIN1L, +20dB)
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PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-21. Mono Mic Input (AIN1L, +20dB) with ALC
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Reference .csv Files
PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-22. Mono Diff Mic Input (AIN1L/AIN1R, +20dB)
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PCM3794A has no Speaker Output
Module of Possible Power Up/Down
Signal path
MD/ MC/
SDA SCL
MS/
ADR MODE
SCKI
DOUT BCK LRCK DIN
Audio Interface
Power On
Reset
Power
Up/Down
Manager
SPL
Clock
Manager
Serial Interface (SPI/I2C)
SPOLP
SPOLN
DGC
(0dB/+6dB/+12dB/+18dB)
ATR
(Mute)
+6dB to -70dB
PG1
PG5
SPR
ATP
(0dB to -62dB, Mute)
AIN3L
AIN2L
AIN1L
SPORP
SPORN
Analog Input L-Channel
0dB/
+20dB
0dB to
-21dB
+6dB to -70dB
SW1
DAL
ADL
HPL
MXL
PG3
SW2
SW3
LOUT
HPOL/
LOL
DS
DS
+30dB to
-12dB
Digital
Filter
Digital
Filter
+
+
D2S
ADC
DAC
+6dB to
-70dB
DAR
SW6
SW5
+
MONO
MXR
ADR
PG4
PG6
+30dB to
-12dB
Digital
Filter
Digital
Filter
DS
DS
ADC
DAC
ROUT
HPR
HPOR/
LOR
PG2
SW4
AIN1R
AIN2R
AIN3R
+6dB to
-70dB
Analog Input R-Channel
0dB/
+20dB
0dB to
-21dB
MCB
Mic Bias
HPCOM/
MONO
MONO
COM
MICB
VCOM
HPC
HPOL
HPOR
Silent Pop Noise
Controller
COM
HDTI
V
COM
VIO
VDD DGND VPA
PGND VCC AGND
Figure A-23. Mono Diff Mic Input (AIN1L/AIN1R, +20dB) with ALC
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Interfacing to DSPs
A.2 Interfacing to DSPs
Refer to the following examples for interfacing the PCM3793A to a digital signal processor (DSP) in either
slave or master mode. To implement master mode, MSTR = 1 of register 84 (54h) enables master mode
Example A-1. Slave Mode Operation
SCKI
Clock
Manager
BCK
DSP
LRCK
ADC
DAC
DOUT
PCM3793A
Figure A-24. Slave Mode Operation
Example A-2. Master Mode Operation
SCKI
Clock
Manager
BCK
DSP
LRCK
ADC
DAC
DOUT
PCM3793A
Figure A-25. Master Mode Operation
Where:
•
•
•
•
•
SCKI: Audio clock (256fS / 384fS)
BCK: Clock for audio transfer (32fS / 48fS / 64fS)
LRCK: Sampling rate clock (fS)
DIN: Audio data input for DAC (I2S, Left-Justified, Right-Justified, DSP)
DOUT: Audio data output from ADC (I2S, Left-Justified, Right-Justified, DSP)
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Package Information
A.2.1 Register Control with DSP Interface
the table indicate specific register settings that must be configured for the device to properly operate with
a DSP interface.
Table A-2. Recommended Power-On Sequence for PCM3793A
REGISTER
STEP
1
SETTINGS
NOTE
–
Turn on all power supplies.(1)
2
4027h
4127h
4227h
4327h
4427h
4527h
4620h
4BC0h
5102h
5A10h
49E0h
5601h
4803h
5811h
49FCh
4C03h
4A01h
523Fh
5711h
4F0Ch
500Ch
–
Headphone amplifier L-ch volume (–6dB)(2)
Headphone amplifier R-ch volume (–6dB)(2)
Speaker amplifier L-ch volume (–6dB)(2)
Speaker amplifier R-ch volume (–6dB)(2)
Digital attenuator L-ch (–24dB)(2)
3
4
5
6
7
8(3)
Digital attenuator R-ch (–24dB)(2)
DAC audio interface format (left-justified)(4)
9
Headphone detection enable and inverting polarity. Short and thermal detection enable.
ADC audio interface format (left-justified)(4)
VCOM ramp up/down time control. PG1, PG2 gain control (0dB)
DAC (DAL, DAR) and analog bias power up
Zero-cross detection enable
10(3)
11
12(5)
13(5)
14
15
16
17
18
19
20
21
22
23
24
Analog mixer (MXL, MXR) power up
Analog mixer input (SW2, SW5) select
Headphone amplifier (HPL, HPR, HPC) power up
Speaker amplifier shut down release
VCOM power up
Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up
Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select
Analog input L-ch (PG3) volume (0dB)(2)
Analog input R-ch (PG4) volume (0dB)(2)
Any settings for other devices or wait time, 450ms(6) (7)
Speaker amplifier (SPL, SPR) power up (5)
49FFh
(1)
VDD should be turn on prior to or simultaneously with the other power supplies. It is recommended to set register data with the
system clock input after turning all power supplies on.
(2)
(3)
(4)
(5)
(6)
Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off.
I2S: 4620h; Left-Justified: 4601h; Right-Justified: 4602h; DSP: 4603h.
Audio interface format should be set to match the DSP or decoder being used.
Between steps 12 and 13, add this value for slave configuration: 5400h. For master configuration, add: 5440h.
The PCM3793A requires time for VCOM to reach the common level from GND level. The delay depends on the capacitor value
for VCOM and the setting of register 125 PTM[1:0], RES[4:0]. The default setting is 450ms at VCOM = 4.7μs.
The PCM3794A does not require this setting because it has no speaker output.
(7)
A.3 Package Information
Packaging information includes a thermal pad mechanical drawing and an example board layout. These
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