ADS5423/24/33 and ADS5411 EVM
User Guide
User's Guide
February 2006
SLWU020B
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Contents
1
2
Overview ................................................................................................................... 5
1.1
1.2
1.3
Purpose .............................................................................................................. 5
EVM Basic Functions............................................................................................... 5
Power Requirements ............................................................................................... 5
1.3.1 Voltage Limits .............................................................................................. 5
EVM Operational Procedure ...................................................................................... 5
1.4
Circuit Description ..................................................................................................... 7
2.1
Schematic Diagram................................................................................................. 7
Circuit Function ..................................................................................................... 7
2.2.1 Analog Inputs .............................................................................................. 7
2.2.2 Power........................................................................................................ 7
2.2.3 Outputs...................................................................................................... 7
2.2
3
4
Parts List .................................................................................................................. 9
Physical Description ................................................................................................. 11
4.1
PCB Layout ........................................................................................................ 11
Schematics......................................................................................................... 17
4.2
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Contents
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List of Figures
4-1
4-2
4-3
4-4
4-5
4-6
Top Layer.................................................................................................................... 11
Layer 2, Ground Plane .................................................................................................... 12
Layer 3, Power Plane #1 .................................................................................................. 13
Layer 4, Power Plane #2 .................................................................................................. 14
Layer 5, Ground Plane .................................................................................................... 15
Layer 6, Bottom Layer .................................................................................................... 16
List of Tables
1-1
2-1
2-2
3-1
Three Pin Jumper List Table ............................................................................................... 6
Output Connector J9 ........................................................................................................ 8
Test Point Description....................................................................................................... 8
Bill of Materials for EVM .................................................................................................... 9
4
List of Figures
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Chapter 1
SLWU020B–February 2005–Revised February 2006
Overview
This User’s Guide document gives a general overview of the ADS5423/24/33 and ADS5411 evaluation
module (EVM) and provides a general description of the features and functions to be considered while
using this module.
1.1 Purpose
The EVM provides a platform for evaluating the ADS5423/24/33 14-bit analog-to-digital converter (ADC)
under various signals, references, and supply conditions. This evaluation module also allows the
evaluation of the ADS5411, an 11-bit analog-to-digital converter. This document should be used in
combination with the EVM schematic diagram supplied.
1.2 EVM Basic Functions
Analog input to the ADC is provided via external SMA connectors. The single-ended input the user
provides is converted into a differential signal at the input of the device. One input path uses a differential
amplifier, while the other input is transformer coupled.
The EVM provides an external SMA connector for input of the ADC clock. The single-ended input the user
provides is converted into a differential signal at the input of the device.
Digital output from the EVM is via a 40-pin connector. The digital outputs from the ADC are buffered
before going to the connector.
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC
analog and digital supplies, the external buffer supply, and the differential amplifier supply.
1.3 Power Requirements
The EVM can be powered directly with only two supplies: a 3.3-V supply for the ADC digital driver supply
and external buffer supply, and 5 V for the ADC analog supply if using the EVM with transformer coupled
analog inputs. If using the differential amplifier analog inputs, ±5 V is required. Provision has also been
made to allow the EVM to be powered with independent 3.3-V supplies to provide higher performance.
1.3.1 Voltage Limits
Exceeding the maximum input voltages can damage EVM components. Under voltage may cause
improper operation of some or all of the EVM components.
1.4 EVM Operational Procedure
The EVM provides a flexible means of evaluating the ADS5423/24/33 or ADS5411 in a number of modes
of operation. A basic setup procedure that can be used as a board confidence check is as follows:
SLWU020B–February 2005–Revised February 2006
Overview
5
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EVM Operational Procedure
Table 1-1. Three Pin Jumper List Table
JUMPER
FUNCTION
LOCATION: PINS 1–2
LOCATION: PINS 2–3
Source provided from Diff Amp
DEFAULT
SJP3
Provides AIN+ source to ADC Source provided from T2
device
1–2
SJP4
Provides AIN– source to ADC Source provided from Diff Amp Source provided from T2
device
2-3
2. Connect supplies to the EVM as follows:
+5 V (4.75 V–5.25 V) ADC analog supply to J3 and return to J2.
+3.3 V (3 V–3.6 V) digital buffer supply to J4 and J1 and return to J6
3. Switch power supplies on.
4. Use a function generator with 50-Ω output to input a 105-MHz, 0-V offset, 1-Vrms sine-wave signal into
J5. The frequency of the clock must be within the specification for the device speed grade.
5. Supply an input signal by using a frequency generator with a 50-Ω output to provide a 15.5 MHz, 0-V
offset, –1-dBFS amplitude sine-wave signal into J11. A full-scale input tone into the ADC device is a
differential 2.2 Vpp and dBFS can be calculated by using the following formula:
captured max code * captured min code
* dBFS + 20 log
, where N is the number of bits.
2N
6. The digital pattern on the output connector J9 should now represent a 2's compliment sine wave and
can be monitored using a logic analyzer.
6
Overview
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Chapter 2
SLWU020B–February 2005–Revised February 2006
Circuit Description
2.1 Schematic Diagram
The schematic diagram for the EVM is attached at the end of this document.
2.2 Circuit Function
The following paragraphs describe the function of EVM circuits. See the relevant data sheet for the device
operating characteristics.
2.2.1 Analog Inputs
The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier
inputs from a single-ended source. The default configuration uses the transformer configuration for which
the layout has been optimized to give the best performance. The inputs are provided via SMA connectors
J11 for transformer coupled input and J10 for differential amplifier input. To setup for one of these options,
the EVM must be configured as follows:
1. For a 1:1 transformer coupled input to the ADC, a single ended source is connected to J11. SJP3 has
pins 1 and 2 shorted and SJP4 has pins 2 and 3 shorted. This is the default configuration for the EVM.
2. For a differential input into the amplifier, the input source is connected to J10. SJP3 has pins 2 and 3
shorted and SJP4 has pins 1 and 2 shorted. ±5VDC must be connected to the board to provide power
to U3 and U4 for this configuration.
2.2.2 Power
Power is supplied to the EVM via banana jack sockets. A separate connection is provided for a +3.3V
digital buffer supply (J1 and J2), 5-V analog supply (J3 and J2), ±5-V amplifier supply (J7, J8, and J12),
and 3.3-V external buffer supply (J4 and J6). A single 3.3-V buffer supply could be used by installing L6.
In this case, connect the 3.3 V to J1 and the return to J2.
2.2.3 Outputs
The data outputs from the ADC are buffered using a Texas Instruments SN74AVC16244. Output data
header J9 is a standard 40-pin header on a 100-mil grid, and allows easy connection to a logic analyzer.
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Circuit Description
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Circuit Function
Table 2-1. Output Connector J9
J9 PIN
DESCRIPTION
J9 PIN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
1
2
CLK
GND
DATA BIT 6
GND
3
NC
DATA BIT 7
GND
4
GND
5
NC
DATA BIT 8
GND
6
GND
7
NC
DATA BIT 9
GND
8
GND
9
DATA BIT 0 (LSB)
GND
DATA BIT 10
GND
10
11
12
13
14
15
16
17
18
19
20
DATA BIT 1
GND
DATA BIT 11
GND
DATA BIT 2
GND
DATA BIT 12
GND
DATA BIT 3
GND
DATA BIT 13 (MSB)
GND
DATA BIT 4
GND
OVERFLOW
GND
DATA BIT 5
GND
DRVDD
GND
Table 2-2. Test Point Description
TEST POINT
FUNCTION
J14
J17
Monitor Vref (AVDD/2)
Monitor DMID (DVDD/2)
8
Circuit Description
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Chapter 3
SLWU020B–February 2005–Revised February 2006
Parts List
Table 3-1. Bill of Materials for EVM
VALUE
QTY
PART NUMBER
VENDOR
REF DES
NOT
INSTALLED
CAPACITORS
0.1 µF, 25 V, +80/–20%
4
6
ECJ-0EF1E104Z
Panasonic
C1, C2, C3, C4
Capacitor
0.01 µF, 25 V, +80/–20%
Capacitor
ECJ-0EF1E103Z
Panasonic
C30, C31, C32, C33,
C34, C35
220 pF, 50 V, 5%, Capacitor
22 pF, 50 V, 5%, Capacitor
220 pF, 50 V, 5%, Capacitor
0.01 µF,16 V, 10% Capacitor
6
1
3
7
ECJ-OEC1H221J
ECJ-1VC1H220J
ECJ-1VC1H221J
ECJ-1VB1C103K
Panasonic
Panasonic
Panasonic
Panasonic
C41–C46
C26
C47, C48, C49
C27, C28, C29, C36,
C37, C38, C39
0.1 µF,16 V, 10% Capacitor
12
ECJ-1VB1C104K
Panasonic
C6, C8, C11, C12,
C14, C16, C17, C18,
C19, C24, C25, C40
470 pF,50 V, 5% Capacitor
10 µF, 10 V, 10%, Capacitor
33 µF, 10 V, 10% Capacitor
4
1
5
ECJ-1VC1H471J
ECS-T1AX106R
ECS-T1AX336R
Panasonic
Panasonic
Panasonic
C20, C21, C22, C23
C15
C5, C7, C9, C10,
C13
RESISTORS
51.1 Ω
2
2
4
5
CTS_742
CTS_742
CTS
CTS
R5, R25
R7, R8
0 Ω
24.9 Ω resistor, 1/16 W, 1%
49.9 Ω resistor, 1/16 W, 1 %
ERJ-3EKF24R9V
ERJ-6EKF49R9V
Panasonic
Panasonic
R6, R11, R12, R27
R1, R4, R10, R18,
R23
R9
36.5 Ω resistor, 1/16 W, 1%
499 Ω resistor, 1/16 W, 1%
0 Ω resistor, 1/16 W, 1%
200 Ω resistor, 1/16 W, 1%
2
4
1
0
ERJ-6EKF36R5V
ERJ-6EKF4990V
ERJ-6ENF0R00V
ERJ-3RKF2000X
Panasonic
Panasonic
Panasonic
Panasonic
R2, R3
R14, R15, R16, R17
R24
R13
FERRITE BEAD, JUMPER, TRANSFORMER, JACKS, CONN etc.
Ferrite Bead
5
1
1
3
1
1
5
3
1
2
EXC-ML32A680U
ADT1-1WT
ADT4-1WT
16F3627
Minicircuits
Minicircuits
NEWARK
Keystone
Keystone
Allied
L1–L5
ADT1-1WT
T2
T3
ADT4-1WT
SMA End Small
Red Test Point
Black Test Point
Red Banana Jack
Black Banana Jack
40-Pin IDC Connector
3 Circuit Jumper
J5, J10, J11
J14
5001K-ND
5000K-ND
J17
ST-351A
Allied
J1, J3, J4, J8, J12
J2, J6, J7
J9
ST-351B
Samtec
TSW-120-07-L-D
SJP3, SJP4
SLWU020B–February 2005–Revised February 2006
Parts List
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Table 3-1. Bill of Materials for EVM (continued)
VALUE
QTY
PART NUMBER
VENDOR
REF DES
NOT
INSTALLED
ICs
ADS5423/24/33 or ADS5411
1
ADS5423/24/33 or
ADS5411
Texas Instruments
U1
SN74AVC16244
THS4503
1
1
1
SN74AVC16244DGG
THS4503
Texas Instruments
Texas Instruments
Texas Instruments
U2
U3
U4
THS4601
THS4601
Surface Mount Jumper Location: SJP3 (2–1), SJP4 (2–3)
10
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Chapter 4
SLWU020B–February 2005–Revised February 2006
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components
used on the module.
4.1 PCB Layout
The EVM is constructed on a 6-layer, 4.77-inch × 3.4-inch, 0.062-inch thick PCB using FR-4 material. The
Figure 4-1. Top Layer
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Physical Description
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PCB Layout
Figure 4-2. Layer 2, Ground Plane
12
Physical Description
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PCB Layout
Figure 4-3. Layer 3, Power Plane #1
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Physical Description
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PCB Layout
Figure 4-4. Layer 4, Power Plane #2
14
Physical Description
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PCB Layout
Figure 4-5. Layer 5, Ground Plane
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Physical Description
15
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PCB Layout
Figure 4-6. Layer 6, Bottom Layer
16
Physical Description
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Schematics
4.2 Schematics
SLWU020B–February 2005–Revised February 2006
Physical Description
17
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
+VCC
J10
SMA_PCB_MT_MOD
R17
499
R14
499
R6
1
J5
T3
24.9
SMA_PCB_MT_MOD
C1
ADT 4-1WT
U3
1
3
5
1
4
2
6
CLK+
CLK-
R10
49.9
CLK+ (Sh 2)
THS4503
.1uF
C2
R4
NC
+VCC
49.9
8
2
1
5
4
C26
+
VCM
CLK- (Sh 2)
VOUT-
.1uF
20pF
R23
VOCM
C40
.1uF
VOUT+
-
49.9
-VCC
-VCC
-VCC
U4
2
3
6
R24
0
VREF
VREF (Sh 2)
R16
499
R15
499
R27
24.9
THS4601
+VCC
R18
49.9
(2-1)
R11
24.9
2
AIN+
SJP3
AIN+ (Sh 2)
J11
(2-1)
SMA_PCB_MT_MOD
T2
ADT 1-1WT
1
1
5
3
6
2
4
R2
36.5
R13
200
R9
49.9
R3
36.5
(Note 1)
(Note 1)
(2-3)
C24
.1uF
R12
24.9
SJP4
2
AIN-
AIN- (Sh 2)
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2
3
4
5
6
D
C
B
A
D
C
B
A
3.3V_DVDD
J14
RED
VREF
(Sh 1) VREF
C25
.1uF
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
DVDD
AVSS
VBG
D3
D2
3
J17
BLACK
D1
4
VSS
D0
U1A
CLK+
CLK-
5
(Sh 1) CLK+
+ENC
-ENC
LVSS
LVDD
CVDD
CVSS
+AIN
DMID
DVSS
DVDD
OVR
6
ADS5424
(Sh 1) CLK-
7
8
9
DNC
10
11
12
13
AVDD
ADVSS
ADVDD
PBKG
AIN+
AIN-
(Sh 1) AIN+
(Sh 1)
AIN-
-AIN
AVSS
5V_AVDD
C3
.1uF
C4
.1uF
U1B
ADS5424
61
62
63
64
65
66
67
68
69
70
71
72
73
86
85
84
83
82
81
80
79
78
77
76
75
74
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
PPAD
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
DRVDD
C16
.1uF
C17
.1uF
C18
.1uF
C19
.1uF
C20
C21
C22
C23
C15
+
470pF 470pF 470pF 470pF
10uF
U2
SN74AVC16244DGG
4 OE
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
3 OE
4A4
4A3
GND
4A2
4A1
VCC
3A4
3A3
GND
3A2
3A1
2A4
2A3
GND
2A2
2A1
VCC
1A4
1A3
GND
1A2
1A1
2 OE
R1
DRY
(SH 1)
DRY
4Y4
4Y3
GND
4Y2
4Y1
VCC
3Y4
3Y3
GND
3Y2
3Y1
2Y4
2Y3
GND
2Y2
2Y1
VCC
1Y4
1Y3
GND
1Y2
1Y1
1 0E
220
R7
0
DRVDD
R5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
D13
D12
D11
D10
D9
D8
D7
D6
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D13
J9
39 40
D12
D11
D10
D9
OVR/
37 38
35 36
33 34
31 32
29 30
27 28
25 26
23 24
21 22
19 20
17 18
15 16
13 14
11 12
D8
D7
D6
220
(SH 1)
R25
D5
D4
D3
D2
D1
D0
OVR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D5
D4
D3
D2
D1
R8
0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
8
9
7
5
3
1
10
8
6
4
2
7
D0
OVR
6
5
CLK
220
4
OVR/
40PIN_IDC
3
2
1
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2
3
4
5
6
+3.3VA-PS
DRVDD
J4
L5
1
2
D
C
B
A
D
C
B
A
DRVDD
J6
C13
C14
.1uF
+
33uF
GND
L6
(Note 1)
1
2
3.3V_DVDD
J1
L1
1
2
DVDD
J2
C5
C6
C27
.01uF
C28
C29
C47
C48
C49
+
33uF
.1uF
.01uF
.01uF
200pF 200pF
200pF
GND
C8
C30
.01uF
C31
C32
C33
C34
.01uF
C35
.01uF
C41
C42
C43
C44
C45
C46
C7
+
.1uF
.01uF
.01uF
.01uF
200pF
200pF
200pF
200pF
200pF
200pF
33uF
5V_AVDD
J3
L2
1
2
AVDD
J8
+VCC
L3
1
2
+VCC
J7
C9
C11
.1uF
C36
C37
.01uF
+
33uF
.01uF
GND
C12
.1uF
C38
C39
C10
33uF
+
.01uF
.01uF
-VCC
J12
L4
1
2
-VEE
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Schematics
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a
finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being
provided are not intended to be complete in terms of required design-, marketing-, and/or
manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or
circuit boards. This evaluation board/kit does not fall within the scope of the European Union
directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these
directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the
board/kit may be returned within 30 days from the date of delivery for a full refund. THE
FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY,
INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR
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The user assumes all responsibility and liability for proper and safe handling of the goods. Further,
the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the
open construction of the product, it is the user’s responsibility to take any and all appropriate
precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY
SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the
user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s
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temperatures and voltages. For additional information on TI’s environmental and/or safety
No license is granted under any patent right or other intellectual property right of TI covering or
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22
Physical Description
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Schematics
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a
finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices
pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against
radio frequency interference. Operation of this equipment in other environments may cause
interference with radio communications, in which case the user at his own expense will be
required to take whatever measures may be required to correct this interference.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the AVDD voltage range of –0.3 V to 3.8 V and the
DVDD voltage range of –0.3 V to 3.8 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage
to the EVM. If there are questions concerning the input range, please contact a TI field
representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User's Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification, please
contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
25°C. The EVM is designed to operate properly with certain components above 50°C as long as
the input and output ranges are maintained. These components include but are not limited to
linear regulators, switching transistors, pass transistors, and current sense resistors. These types
of devices can be identified using the EVM schematic located in the EVM User's Guide. When
placing measurement probes near these devices during operation, please be aware that these
devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
SLWU020B–February 2005–Revised February 2006
Physical Description
23
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
Automotive
Broadband
Digital Control
Military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
microcontroller.ti.com
Telephony
Low Power
Wireless
Video & Imaging
Wireless
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