User's Guide
SLAU204–December 2006
DAC8555EVM User's Guide
This user’s guide describes the characteristics, operation and use of the DAC8555
Evaluation Module (EVM). It covers all matters related to proper use and configuration
of this EVM along with the devices that it supports. The physical printed circuit board
(PCB) layout, schematic diagram and circuit descriptions are also included. For a more
detailed description of the DAC8555, see the product data sheet available from the
listed in the section of this guide entitled Related Documentation from Texas
Instruments. Throughout this document, the acronym EVM and the phrases evaluation
module and demonstration board are synonymous with the DAC8555EVM.
TMS320C5000, TMS320C6000 are trademarks of Texas Instruments.
LabVIEW is a trademark of National Instruments.
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1
Overview
1
Overview
This section gives a general overview of the DAC8555EVM and describes some of the factors that must
be considered when using this demonstration board.
1.1 Features
The DAC8555EVM is a simple evaluation module designed for a quick and easy way to evaluate the
functionality and performance of the high-resolution, quad-channel, serial input DAC8555 digital-to-analog
converter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TI
DSP-based system.
1.2 Power Requirements
This subsection describes the power requirements for this device.
1.2.1
Supply Voltage
The DC power supply requirement for the digital section (VDD) of this EVM is typically +5V connected to
the J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card)
and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements for
the analog section of this EVM are: VCC and VSS range from +15.75V to –15.75V (maximum), connecting
through J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5VA connects through
terminals J5-3 or J3-3, and the +3.3VA connects through terminal J3-8. All of the analog power supplies
are referenced to analog ground through terminals J1-2 and J3-6.
The analog power supply for the device under test, U1, can be powered by either +5VA or +3.3VA by
selecting the proper position of jumper JMP7. This configuration allows the DAC8555 analog section to
operate from either supply power while the I/O and digital section are powered by +5V, VDD
.
The VCC supply source is primarily used to provide the positive rail of the external output op amp, U2, the
reference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can be
selected between VSS and AGND via jumper JMP10. The external op amp is installed as an option to
provide output signal conditioning or to boost capacitive load drive, or for other desired output mode
requirements.
CAUTION
To avoid potential damage to the EVM board, be sure that the correct cables
are connected to their respective terminals as labeled on the EVM board.
Stresses above the maximum listed voltage ratings may cause permanent
damage to the device.
1.2.2
Reference Voltage
The +5V precision voltage reference is provided to supply the external voltage reference for the DAC
through the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes through
an adjustable 100kΩ potentiometer, R15, in series with 20kΩ, R16, to allow the user to adjust the
reference voltage to its desired settings. The voltage reference is then buffered through U4A as seen by
the device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, in
order to allow the user to connect another external reference source if the onboard reference circuit is not
desired. The external voltage reference should not exceed +5V DC.
The REF02 precision reference is powered by VCC (+15V) through either terminal J1-3 or J3-1.
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Overview
CAUTION
When applying an external voltage reference through TP2 or J4-20, make sure
that it does not exceed +5V maximum. External voltage references in excess of
+5V can permanently damage the DAC8555 being tested (U1).
1.3 EVM Basic Functions
The DAC8555EVM is designed to provide a demonstration platform for testing certain operational
characteristics of the DAC8555 digital-to-analog converter. Functional evaluation of the DAC8555 can be
accomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.
Headers J2A (top side) and J2B (bottom side) are pass-through connectors provided to interface a host
processor or waveform generator with the DAC8555EVM using a custom-built cable. These connectors
enable the control signals and data to pass between the host and the device.
A mating adapter interface card (5-6k adapter interface) is also available to fit with TI’s TMS320C5000™
and TMS320C6000™ DSP Starter Kits (DSKs). This card resolves most of the trouble involved with
building a custom cable. Additionally, there is also an MSP430-based platform (HPA449) that uses the
MSP430F449 microprocessor, to which this EVM can connect and interface as well. For more details or
information regarding the 5-6k adapter interface card or the HPA449 platform, please contact your Texas
Instruments representative, visit the TI web site or email the Data Converter Applications Support Team at
The DAC outputs can be monitored through the selected pins of the J4 header connector. All outputs can
be switched through their respective jumpers—JMP11, JMP12, JMP13 and JMP14—for the purpose of
stacking. Stacking allows a total of eight DAC channels to be used, provided the SYNC signals are unique
for each EVM board stacked.
In addition, the option of selecting one DAC output that can be fed to the noninverting side of the output
op amp, U2, is also possible by using a jumper across the selected pins of J4. The output op amp (U2)
must first be correctly configured for the desired waveform characteristic. For more information, refer to
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Overview
VCC
VSS
VCC
GND
VSS
(J1)
(J5)
+3.3VA
VDD
GND
VDD
(J3A)
(J3B)
+5VA
+3.3VA
External
Reference
Module
+5VA
JMP16
JMP8
TP2
RSTSEL
RST
EN
(J2A)
(J2B)
VREFH
JMP11
JMP12
JMP13
JMP14
DIN
JMP15
LDAC
SCLK
SYNC
(J4A)
(J4B)
DAC Module
RSTSEL
8 CH
4 CH
Output
Buffer
RST
VREFL
Module
DAC Out
JMP5
VREFH
JMP4
JMP3
TP4
JMP6
TP3
JMP9
JMP10
VSS
Figure 1. DAC8555EVM Functional Block Diagram
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PCB Design and Performance
1.3.1
Related Documentation from Texas Instruments
The following documents provide information regarding Texas Instrument integrated circuits used in the
assembly of the DAC8555EVM. The latest revisions of these documents are available from the TI web site
Data Sheet
DAC8555
REF02
Literature Number
SLAS475
SBVS003
OPA627
OPA2132
SBOS165
SBOS054
2
PCB Design and Performance
This section discusses the layout design of the DAC8555EVM PCB, describing the physical and
mechanical characteristics of the EVM as well as a brief description of the demonstration board test
performance procedures performed. The list of components used in this evaluation module is also
included.
2.1 PCB Layout
The DAC8555EVM is designed to preserve the performance quality of the DAC8555, the device under
test (DUT), as specified in the data sheet. In order to take full advantage of the EVM capabilities, use care
during the schematic design phase to properly select the right components and to build the circuit
correctly. The circuit design should include adequate bypassing, identifying and managing the analog and
digital signals, and understanding the components' electrical and mechanical attributes.
The primary design concerns during the layout process are optimal component placement and proper
signal routing. Place the bypass capacitors as close as possible to the device pins, and properly separate
the analog and digital signals from each other. In the layout process, carefully consider the placement of
the power and ground planes. A solid plane is ideal, but because of its greater cost, a split plane can
sometimes be used satisfactorily. When considering a split plane design, analyze the component
placement and carefully split the board into its analog and digital sections starting from the DUT. The
ground plane plays an important role in controlling the noise and other effects that otherwise contribute to
the error of the DAC output. To ensure that the return currents are handled properly, route the appropriate
signals only in their respective sections, meaning that the analog traces should only lay directly above or
below the analog section and the digital traces in the digital section. Minimize trace length, but use the
largest possible trace width allowable within the design. These design practices are illustrated in Figure 2
The DAC8555EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.
The PCB has a dimension of 43,1800mm (1.7000in) by 82,5500mm (3.2500in), and the board thickness is
Note: Board layouts are not to scale. These are intended to show how the board is laid out; they
are not intended to be used for manufacturing DAC8555EVM PCBs.
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PCB Design and Performance
Figure 2. DAC8555EVM PCB—Top Silkscreen Image
Figure 3. DAC8555EVM PCB—Layer 1 (Top Signal Layer)
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PCB Design and Performance
Figure 4. DAC8555EVM PCB—Layer 2 (Ground Plane)
Figure 5. DAC8555EVM PCB—Layer 3 (Power Plane)
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Figure 6. DAC8555EVM PCB—Layer 4 (Bottom Signal Layer)
Figure 7. DAC8555EVM PCB—Bottom Silkscreen Image
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PCB Design and Performance
Figure 8. DAC8555EVM—Drill Drawing
2.2 EVM Performance
The EVM performance test is executed using a high-density DAC bench test board, an Agilent 3458A
digital multimeter and a PC running LabVIEW™ software. The EVM board is tested for linearity for all
codes between 485 and 64741. The DUT is then allowed to settle for 1ms before the meter is read. This
process is repeated for all codes to generate the measurements for INL and DNL.
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Figure 9. INL and DNL Characterization Graph of DAC A
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PCB Design and Performance
Figure 10. INL and DNL Characterization Graph of DAC B
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Figure 11. INL and DNL Characterization Graph of DAC C
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PCB Design and Performance
Figure 12. INL and DNL Characterization Graph of DAC D
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2.3 Bill of Materials
Table 1. DAC8555EVM Parts List
QTY
PER
MFR
ITEM
BOARD
Ref Des
R11–R14
MFR
Panasonic
PART NUMBER
DESCRIPTION
Chip Resistor, 0Ω, 1/10W, 0603
Chip Resistor, 100Ω, 1/4W, 1206
1
2
4
1
ERJ-3GEY0R00V
ERJ-8GEYJ101V
R24
Panasonic
Panasonic
Not
Installed
2
7
R5, R6
ERJ-3GEYJ302V
ERJ-3EKF1002V
Chip Resistor, 3kΩ, 1/10W, 0603
R1–R4, R7, R8,
R9
3
Panasonic
Chip Resistor, 10kΩ, 1/16W, 0603
4
5
6
1
1
1
R16
R10
R15
Panasonic
Bourns
ERJ-3EKF2002V
3214W-1-203E
3214W-1-104E
Chip Resistor, 20kΩ, 1/16W, 0603
Series 5T Pot., 20kΩ, BOURNS_32X4W
Series 5T Pot., 100kΩ, BOURNS_32X4W
Bourns
Not
Installed
7
R17–R23
Panasonic
Chip Resistor, 1/4W 1206
7
8
1
4
2
3
C12
TDK
TDK
TDK
TDK
C1608C0G1H102J
C1608X7R1E104K
C2012X7R1E105K
C3216X7R1C106M
Multilayer Ceramic Capacitor, 1nF, 0603 C0G
Multilayer Ceramic Capacitor, 0.1µF, 0603 X7R
Multilayer Ceramic Capacitor, 1µF, 0805 X7R
Multilayer Ceramic Capacitor, 10µF, 1206 X7R
C4–C7
9
C10, C11
C1, C2, C3
10
Not
Installed
2
1
C8, C9
U1
TDK
Multilayer Ceramic Capacitor, 1206
16-bit, Quad Voltage Output, Serial Input DAC,
TSSOP-16
11
Texas Instruments
DAC8555IPW
12
13
14
1
1
1
U2
U3
U4
Texas Instruments
Texas Instruments
Texas Instruments
OPA627AU
REF02AU
8-SOP(D) Precision Op Amp
+5V, 8-SOP(D) Precision Voltage Reference
8-SOP(D) Dual Precision Op Amp
OPA2132UA
Not
Installed
2
J1, J5
On-Shore Technology
ED555/3DS
3-Pin Terminal Connector
SMT Header, 10x2x0.1, 20-pin, .025in2
SMT Header, 5x2x0.1, 10-pin, .025in2
SMT Socket, 10x2x0.1, 20-pin, .025in2
SMT Socket, 5x2x0.1, 10-pin, .025in2
2-position Jumper_ .1in spacing
3-position Jumper_ .1in spacing
Testpoint, Large-Loop
15
16
17
18
19
20
21
2
1
J2A, J4A
J3A
Samtec
TSM-110-01-L-DV-P
TSM-105-01-L-DV-P
SSW-110-22-F-D-VS-K
SSW-105-22-F-D-VS-K
TSW-102-07-G-S
TSW-103-07-G-S
5011
Samtec
2
J2B, J4B
J3B
Samtec
1
Samtec
6
JMP1–JMP6
JMP7–JMP16
TP4
Samtec
10
1
Samtec
Keystone Electronics
Not
Installed
TP1, TP2, TP3,
TP5, TP6
5
Keystone Electronics
Samtec
5000
Testpoint, Mini-Loop
Shorting Block
22
16
N/A
SNT-100-BK-G-H
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EVM Operation
3
EVM Operation
This section covers the operation of the EVM in detail, in order to provide guidance to the user in
evaluating the onboard DAC as well as how to interface the EVM to a specific host processor. Refer to the
DAC8555 datasheet for information about its serial interface and other related topics. The EVM board is
factory-tested and configured.
3.1 Default Settings
Table 2. Factory Default Jumper Settings
Reference
JMP1
Jumper Position Function
CLOSE
CLOSE
CLOSE
OPEN
ENABLE pin is tied to DGND
JMP2
LDAC pin is tied to DGND. Software LDAC is used.
RSTSEL pin is tied to DGND.
JMP3
JMP4
RST pin is tied to VDD.
VREFH is not routed to the inverting input of the op amp for voltage offset with gain of 2
output.
JMP5
OPEN
JMP6
JMP7
OPEN
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
Output op amp U2 is not configured for a gain of 2.
Analog supply for the DAC8555 is +5VA.
Onboard external buffered reference U3 is routed to VREFH.
VREFL is tied to AGND.
JPM8
JMP9
JMP10
JMP11
JMP12
JMP13
JMP14
JMP15
JMP16
Negative supply rail of U2 op amp is supplied with VSS
DAC output A (VOUTA) is routed to J4-2.
DAC output B (VOUTB) is routed to J4-4.
DAC output C (VOUTC) is routed to J4-6.
DAC output D (VOUTD) is routed to J4-8.
.
J4-1 is connected to the noninverting input of the output op amp U2.
J4-5 is connected to the output of the op amp U2.
3.2 Host Processor Interface
The host processor drives the DAC. Thus, proper DAC operation depends on a successful configuration
between the host processor and the EVM board. In addition, properly written code is also required to
operate the DAC.
As discussed earlier, a custom cable can be made specific to the host interface platform. The EVM allows
interface to the host processor through header connector J2 for the serial control signals and the serial
data input. The output can be monitored through header connector J4.
An interface adapter card is also available for specific TI DSP DSKs as well as an MSP430-based
microprocessor (see Section 1.3 of this manual). Using the interface card alleviates the tedious task of
building customized cables and allows easy configuration of a simple evaluation system.
The DAC8555 interfaces with any host processor capable of handling SPI protocols or the popular TI
DSPs. For more information regarding the DAC8555 data interface, please refer to the DAC8555
datasheet.
3.3 EVM Stacking
Stacking multiple EVMS is possible if there is a need to evaluate two DAC8555s, yielding a total of eight
output channels. A maximum of two EVMs can be stacked since the output terminal, J4, dictates the
channels are mapped into the output terminal, J4, with respect to the jumper positions of JMP11, JMP12,
JMP13, and JMP14.
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EVM Operation
Table 3. DAC Output Channel Mapping
Reference
Jumper Position
Function
1-2
2-3
1-2
2-3
1-2
2-3
1-2
2-3
DAC output A (VOUTA) is routed to J4-2.
DAC output A (VOUTA) is routed to J4-10.
DAC output B (VOUTB) is routed to J4-4.
DAC output B (VOUTB) is routed to J4-12.
DAC output C (VOUTC) is routed to J4-6.
DAC output C (VOUTC) is routed to J4-14.
DAC output D (VOUTD) is routed to J4-8.
DAC output D (VOUTD) is routed to J4-16.
JMP11
JMP12
JMP13
JMP14
In order to allow exclusive control of each EVM, different SYNC signals must be selected for each
DAC8555. This difference is not easily accomplished as it involves hardware alterations. The EVM board
that sits on the bottom of the stack can use the SYNC signal coming from J2B-7. The pin of J2A-7 can be
cut so that the SYNC signal coming from the bottom EVM board in the stack does not pass through. The
EVM board that sits on top can use the CNTL signal coming from J2-1. The signal of J2-1 must be
jumpered across to J2-7 of the EVM board that sits on the top of the stack. The LDAC, SYNC and
ENABLE control signals are shared. The DAC8555 only responds when the correct SYNC signal is
generated.
The raw outputs of the DAC can be probed through the even numbered pins of J4, the output terminal,
which also provides mechanical stability when stacking or plugging into any interface card. In addition, it
provides easy access for monitoring up to eight DAC channels when stacking two EVMs together.
3.4 Output Op Amp
The DAC8555EVM includes an optional signal conditioning circuit for the DAC output through an external
operational amplifier, U2. The output op amp is set to unity gain configuration by default. Only one DAC
output channel can be monitored at any given time. JMP15 selects which pin of J4 is the input. Either J4-1
or J4-3 can be used as the op amp signal input. The default setting for JMP15 selects J4-1. A shorting
jumper can be placed between one of the DAC outputs and the op amp input. For example, a jumper
across J4-1 and J4-2 places the DAC A output as the input for the op amp if board jumpers are in the
default position. If JMP15 is in the alternate position, then a shorting block between J4-3 and J4-2 makes
the DAC B output the input to the op amp.
The output of U2 passes through JMP16. In the default position, the output connects to J4-5. When
JMP16 is in the alternate position, the output from U2 connects to J4-7. The output can be monitored
from, or passed to, another device from the J4 connector.
The jumper arrangement of JMP15 and JMP16 connecting to J4 allows U2 to be used in the stacked
The following subsections describe the different configurations of the output amplifier, U2.
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EVM Operation
3.4.1
Unity Gain Output
The buffered output configuration can be used to prevent loading of the DAC8555, though it may add
some slight distortion because of the feedback resistor and capacitor. The feedback circuit can be altered
by simply desoldering R8 and C12 and replacing them with components of desired value. If desired, R8
and C12 can be removed altogether by replacing R8 with a 0Ω resistor.
Table 4 shows the jumper setting for the unity gain configuration of the DAC external output buffer in
unipolar or bipolar mode.
Table 4. Unity Gain Output Jumper Settings
Jumper Setting
Reference
JMP5
Unipolar
Open
2-3
Bipolar
Open
1-2
Function
Disconnect VREFH from the inverting input of the op amp.
Supplies VSS to the negative rail of the op amp or ties it to AGND.
Disconnect negative input of op amp from the gain resistor, R9.
JMP10
JMP6
Open
Open
3.4.2
Output Gain of 2
There are two types of configurations that will yield an output gain of 2, depending on the setup of jumpers
JMP5 and JMP6. These configurations allow the user to choose whether the DAC output will use VREF
H
Table 5. Output Gain of 2 Jumper Settings
Jumper Setting
Reference
Unipolar
Bipolar
Function
Inverting input of the output op amp U2 is connected to VREFH for use as its offset
voltage with a gain of 2. JMP6 must be open.
Close
Close
JMP5
VREFH is disconnected from the inverting input of the output op amp U2. JMP6 must be
closed.
Open
2-3
Open
1-2
Supplies power, VSS, to the negative rail of op amp U2 for bipolar mode, or ties it to
AGND for unipolar mode.
JMP10
JMP6
Configures op amp U2 for a gain of 2 output without a voltage offset. JMP5 must be
open.
Close
Open
Close
Open
Inverting input of op amp U2 is disconnected from the gain resistor, R9. JMP5 must be
closed.
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EVM Operation
3.4.3
Capacitive Load Drive
It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op
amps may become unstable, depending on the op amp configuration, gain, and load value. These factors
are just few of the issues that can affect op amp stability and should be considered during implementation.
In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads.
Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistor
even improves the capacitive load drive capability.
Table 6. Capacitive Load Drive Output Jumper Settings
Jumper Setting
Reference
Unipolar
Bipolar
Function
JMP5
Open
Open
VREFH is disconnected from the inverting input of the output op amp U2.
Supplies power, VSS, to the negative rail of op amp U2 for bipolar mode, or ties it to AGND
for unipolar mode.
JMP10
JMP6
2-3
1-2
Capacitive load drive output of DAC is routed to pin 2 of JMP6 and may be used as the
output terminal.
Open
Open
3.5 Optional Signal Conditioning Op-Amp (U4B)
One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the other
half is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desires
to implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not
populated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so it
is up to the user on how to connect the (±) input signals to this op amp. No test point has been made
available for the output because of space restrictions, but a wire can be soldered to the output of the op
amp via an unused component pad that connects to it. The op amp circuit can be configured by populating
the corresponding components to those that match the circuit design while leaving all other unused
component footprints unpopulated.
3.6 Jumper Settings
Table 7. Jumper Settings and Functions
Reference
Jumper Setting(1)
Function
ENABLE pin is set high through pull-up resistor R1. ENABLE can be driven by GPIO2,
J2-8.
JMP1
ENABLE pin is set low and DAC is enabled.
LDAC pin is set high through pull-up resistor R2. LDAC can be driven by GPIO0, J2-2.
LDAC pin is set low and DAC update is accomplished via software.
JMP2
JMP3
RSTSEL pin is set high through pull-up resistor R3. RSTSEL can be driven by GPIO4,
J2-14.
RSTSEL pin is set low.
(1)
Indicates the corresponding pins that are shorted or closed.
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EVM Operation
Table 7. Jumper Settings and Functions (continued)
Reference
Jumper Setting(1)
Function
RST pin is set high through pull-up resistor R4. RST can be driven by GPIO5, J2-19.
RST pin is set low.
JMP4
JMP5
JMP6
Disconnects VREFH to the inverting input of the op amp U2.
Connects VREFH to the inverting input of the op amp U2.
Disconnects the inverting input of the op amp U2 from the gain resistor, R9.
Connects the inverting input of the op amp U2 from the gain resistor, R9 for output gain of
2.
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
+5V analog supply is selected for AVDD
.
JMP7
JMP8
+3.3V analog supply is selected for AVDD
.
Routes the adjustable, buffered, onboard +5V reference to the VREFH input of the
DAC8555.
Routes the user-supplied reference from TP2 or J4-20 to the VREFH input of the
DAC8555.
VREFL is tied to AGND.
JMP9
Routes the user-supplied negative reference from TP3 or J4-18 to the VREFL input of the
DAC8555. This voltage should be within the range of 0V to VREFH.
Negative supply rail of the op amp U2 is powered by VSS for bipolar operation.
Negative supply rail of the op amp U2 is tied to AGND for unipolar operation.
Routes VOUTA to J4-2.
JMP10
JMP11
Routes VOUTA to J4-10.
20
DAC8555EVM User's Guide
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SLAU204–December 2006
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EVM Operation
Table 7. Jumper Settings and Functions (continued)
Reference
Jumper Setting(1)
Function
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
Routes VOUTB to J4-4.
JMP12
JMP13
JMP14
JMP15
JMP16
Routes VOUTB to J4-12.
Routes VOUTC to J4-6.
Routes VOUTC to J4-14.
Routes VOUTD to J4-8.
Routes VOUTD to J4-16.
Routes J4-1 to U2 noninverting input.
Routes J4-3 to U2 noninverting input.
Routes U2 output to J4-5.
Routes U2 output to J4-7.
SLAU204–December 2006
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DAC8555EVM User's Guide
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21
Schematic
4
Schematic
22
DAC8555EVM User's Guide
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SLAU204–December 2006
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REVISION HISTORY
ENGINEERING CHANGE NUMBER
REV
APPROVED
JMP7
+5VA
+3.3VA
VDD
VCC
AVDD
D
C
B
A
D
C
B
A
C11
1uF
VDD
R1
R2
R3
10K
R4
R5
NI
R6
NI
10K
10K
10K
C5
C2
R14
0
0.1uF 10uF
U2_+IN
JMP5
3
2
U2
C7
C3
10uF
0.1uF
R24
U2_OUT
6
100
U2_-IN
OPA627AU
1
2
U1
AVDD
4
12
3
JMP15
OPA IN
IO_V/DVDD
VrefH
R7
10K
J4A
VrefH
VrefL
LDAC
ENABLE
16
15
14
13
2
4
6
1
3
5
7
VSS
LDAC
A0(+)
A1(+)
A2(+)
A3(+)
A4
A5
A6
A7
REF-
REF+
A0(-)
A1(-)
A2(-)
JMP11
1
2
3
ENABLE
RSTSEL
RST
5
OUT_A
OUT_B
8
VrefL
A3(-)
JMP10
RSTSEL
RST
10
12
14
16
18
20
9
AGND
AGND
AGND
VCOM
AGND
AGND
11
13
15
17
19
OUT A
JMP12
C10
1uF
-REFin
+REFin
1
2
3
R11
R12
0
0
SDI
11
10
9
Din
R8
1
2
7
8
VoutA
VoutB
VoutC
VoutD
SCLK
SYNC
10K
OUTPUT HEADER
SCLK
SYNC
OUT B
JMP13
C12
OUT_C
OUT_D
1
2
3
1nF
R9
J4A (TOP) = SAM_TSM-110-01-L-DV-P
J4B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K
6
GND
JMP6
2
1
DAC8555IPW
OUT C
JMP14
10K
1
2
3
VCC
OUT D
JMP16
OPA OUT
VCC
U3
VIN
TP1
2
6
5
VOUT
TRIM
C6
0.1uF
REF OUT
3
TEMP
C1
10uF
C4
0.1uF
REF02AU
R15
2
3
2
1
100K
JMP8
1
1
3
U4A
OPA2132UA
2
3
R10 20K
VrefH
R16
20k
TP2
+REFin
-REFin
J2A
CNTL GPIO0
CLKX DGND
CLKR GPIO1
EXTERNAL
REFERENCE
LDAC
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
SCLK
SYNC
SDI
TP3
NOTE: Voltage range of -REFin input should not exceed
0 - VrefH.
R13
0
ENABLE
RSTSEL
JMP9
3
FSX
FSR
DX
DR
INT
GPIO2
DGND
GPIO3
GPIO4
SCL
2
1
VrefL
TP4
TOUT DGND
GPIO5 SDA
C8
RST
AGND
DAUGHTER-SERIAL
NI
R17
NI
J2A (TOP) = SAM_TSM-110-01-L-DV-P
J2B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K
R18
NI
U4B
R19 NI
R20 NI
TP5
+Vin
TP6
-Vin
5
R23
NI
7
6
+3.3VD +1.8VD +5VA VCC
VSS
-5VA +3.3VA VDD
J1
J5
OPA2227UA
J3A
+VA
R21
NI
1
3
5
7
9
2
4
6
8
R22
NI
-VA
-5VA
+5VA
ti
DGND AGND
+1.8VD VD1
+3.3VD +5VD
DATA ACQUISITION PRODUCTS
HIGH-PERFORMANCE ANALOG DIVISION
SEMICONDUCTOR GROUP
C9
NI
10
DAUGHTER-POWER
6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA
VSS
VCC
VDD
+5VA
VCC = +15V Analog
TITLE
ENGINEER J. PARGUIAN
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog
DAC8555EVM
J3A (TOP) = SAM_TSM-105-01-L-DV-P
J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-K
DRAWN BY R. BENJAMIN
DOCUMENT CONTROL NO6. 486604
SIZE B
DATE11-Oct-2006
REV
A
SHEET 1 OF
1
FILE C:\USERDATA\Projects\DAC8555\DAC8555EVM.ddb
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PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general customer use. It generates, uses, and
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of–15.75V to +15.75V and the output voltage range of –15V to
+15V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 60°C. The EVM is designed to
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