User's Guide
SBAU159–October 2009
DAC7716EVM
DAC7716EVM
This user's guide describes the characteristics, operation, and use of the DAC7716EVM. The evaluation
DAC7716 is a quad, high-accuracy, 12-bit R-2-R digital-to-analog converter (DAC). The device features
low-power operation, good linearity, and the ability to use different reference voltages for the output
channels. This EVM allows evaluation of all aspects of the DAC7716. Complete circuit descriptions,
schematic diagrams, and bill of material are included in this document.
The following related documents are available through the Texas Instruments web site at
EVM-Compatible Device Data Sheets
Device
Literature Number
All trademarks are the property of their respective owners.
1
SBAU159–October 2009
DAC7716EVM
Copyright © 2009, Texas Instruments Incorporated
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Analog Interface
2
Analog Interface
For maximum flexibility, the DAC7716EVM can interface to multiple analog sources. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row, header at J1. This header
provides access to the analog input and output pins of the DAC. Consult Samtec at
http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options.
Table 1 summarizes the pinouts for analog interface J1.
Table 1. J1: Analog Interface Pinout
Pin Number
J1.1
Signal
SGND-0
VOUT-0
Description
Signal GND DAC output 0
Analog output 0
J1.2
J1.3
SGND-1
VOUT-1
Signal GND DAC output 1
Analog output 1
J1.4
J1.5
SGND-2
VOUT-2
Signal GND DAC output 2
Analog output 2
J1.6
J1.7
SGND-3
VOUT-3
Signal GND DAC output 3
Analog output 3
J1.8
J1.9-13 (odd)
J1.10
AGND
Analog ground connections
Auxiliary analog input
Monitor output after buffer
—
AIN
J1.14
VMON_BUF
Unused
AGND
J1.15
J1.17-19 (odd)
J1.18
Analog ground connections
RefGND
Reference ground pins on the
DAC7716 (see below)
J1.20
EXTREF+
External reference source input (+
side of reference input)
J1.12
J1.16
Unused
Unused
—
—
The analog interface is populated on the top of the evaluation model. This configuration makes it possible
to stack multiple EVMs to run them in daisy-chain mode. J4 can be installed with a 90-degree connector to
allow access to the analog outputs if multiple EVMs are stacked. The J1B connector can be installed if the
part is used as a standalone board.
The DAC7716 can be configured with an output gain of 2 or 4. By default, the analog outputs of the
DAC7716EVM are configured with a gain of 4. If a gain of 2 is desired, the proper jumper must be
installed (JP2-JP5, depending on the output channel), and the command register must be set accordingly.
The SGND pins of the DAC7716 are connected to the ground of the evaluation board.
The Auxiliary Analog Input pin can be further protected from over-voltage and over-driving conditions. A
Schottky diode (D1) can be installed to protect the DAC7716 from an input over-voltage condition. An op
amp buffer is placed on the VMON output to limit the current that passes through the pin.
The DAC7716EVM has an external reference voltage option. If an external reference voltage is used,
switches S2 and S3 must be properly configured. Use the EXTREF+ (J1.20) to apply an external
reference voltage.
The DAC7716 is designed to have the REFGND-A and REFGND-B pins within 0.3V of the AGND.
Therefore, we recommend not using the RefGND pin when connecting an external reference. Connect the
ground source of the reference voltage to the ground of the board (J1.19). See the Reference Voltage
section for more information.
3
Digital Interface
The DAC7716EVM is a serial input data converter. The evaluation module is designed for interfacing to
multiple control platforms.
3
SBAU159–October 2009
DAC7716EVM
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Digital Interface
3.1 Serial Data Interface
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row,
header/socket combination at J2. This header/socket provides access to the digital control and serial data
pins from both J2A (top side) and J2B (bottom side) of the connector. Consult Samtec at
http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options.
Table 2 describes the serial interface pins.
Table 2. J2: Serial Interface Pins(1)
Pin No.
J2.1
Signal Name
Unused
I/O Type
—
Pullup
—
Function
J2.2
GPIO-0
In/Out
In
High
None
GPIO-0
J2.3 J2.5
SCLK
DAC7716 SPI
clock; pins are
shorted together
J2.4
J2.6
DGND
GPIO-1
CS
In/Out
In/Out
In
None
High
Digital ground
GPIO-1
J2.7 J2.9
None
SPI bus chip select;
pins are shorted
together
J2.8
Uni/Bip A
In
High
Output mode select
of Group A
J2.10
J2.11
DGND
In/Out
In/Out
None
None
Digital ground
SDO/SDI
DAC7716 SPI data
in/out
J2.12
Uni/Bip B
In
High
Output mode select
of Group B
J2.13
J2.14
J2.15
Unused
RST
—
In
In
—
High
High
Input register reset
LDAC
GPIO signal to
control LDAC for
DAC output latch
update
J2.16
J2.17
Unused
LDAC
—
In
—
High
Alternate GPIO
signal to control
LDAC for DAC
output latch update
J2.18
J2.19
J2.20
DGND
Unused
Unused
In/Out
—
None
—
Digital ground
—
—
(1)
Group A contains VOUT-0 and VOUT-1. Group B contains VOUT-2 and VOUT-3.
The SCLK signal and the CS signal can each be controlled by two different pins on J2. Pins J2.3 and J2.5
have been shorted together, as well as pins J2.7 and J2.9.
Pins J2.8, J2.12, J2.14, J2.15, and J2.17 have weak pull-up/pulldown resistors. These resistors provide
default settings for many of the control pins. J2.3, J2.5, J2.7, J2.9, J2.11 correspond directly to DAC7716
Control signals to and from the DAC7716 can be accessed through the digital interface, or switches and
jumpers found directly on the EVM. The /LDAC, Uni/Bip A, Uni/Bip B, and RST signals are initially pulled
high through 10kΩ resistors and can be controlled by switch S1 or through J2.
The load DAC (LDAC) pin is connected via jumper JP1 to either the J2.15 or J2.17 pin. Updating the DAC
registers can be completed in two different ways. LDAC can either be tied to ground, in which case the
input registers are immediately updated, or LDAC can be pulled high. Therefore, the DAC registers update
when LDAC is taken low. Switch S1.1 can be closed to hold the LDAC low. See the DAC7716 data sheet
for more information on updating the DAC.
4
DAC7716EVM
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Power Supplies
4
Power Supplies
Samtec part numbers SSW-105-22-F-D-VS-K and TSM-105-01-T-DV-P provide a 5-pin, dual-row,
header/socket combination at J3. Table 3 lists the configuration details for J3. The voltage inputs to the
DAC can be applied directly to the device. The DAC7716 requires multiple power supplies to operate.
AVDD, AVSS, DVDD, and IOVDD are required to properly power the DAC.
Table 3. J3 Configuration: Power-Supply Input
Pin No.
J3.1
Pin Name
+VA
Function
+4.75V to +24V analog supply
–18V to –4.75V analog supply
+5V analog supply
–5V analog supply
Digital ground input
Analog ground input
1.8V digital supply
3.3V digital supply
Not used
Required
Yes
J3.2
–VA
Yes
J3.3
+5VA
No
J3.4
–5VA
No
J3.5
DGND
AGND
+1.8VD
+3.3VD
VD1
Yes
J3.6
Yes
J3.7
Optional
Optional
No
J3.8
J3.9
J3.10
+5VD
+5V
Yes
The Digital and Analog ground inputs are short-circuited internally through a ground plane.
The dc logic voltage for the DAC7716 (IOVDD) is selectable between +3.3VD, +1.8VD, or +5VD via the
JP8 jumper. These power-supply voltages are referenced to digital ground.
The DAC7716EVM is designed to work in either unipolar and bipolar mode. Each mode requires different
power-supply connections. Consult the DAC7716 data sheet for the restrictions on the power supplies for
the two operating modes.
5
Reference Voltage
The DAC7716EVM has the ability to use two different reference sources simultaneously for different
output channels. REFA and REFB control the reference voltages for the DAC. Output channels VOUT-0 and
VOUT-1 use REFA as a reference. REFB is used as a reference for output channels VOUT-2 and VOUT-3.
The evaluation module has three options for supplying reference voltages to the DAC7716. Switch S3
(REFA) and S2 (REFB) can select the reference voltage from the REF5050 (U5), REF5025 (U4) or use an
external reference. The REF5050 supplies 5.0V to the reference. The REF5025 supplies 2.5V to the
reference. These reference voltages are additionally filtered through an RC filter before connecting to the
DAC7716. The TL751L08 is used to voltage regulate +VA to properly power the REF5025 and REF5050.
When using an external reference, make sure that the ground terminal (from the external source) is
connected to the ground of the EVM board. There is a built-in diode in the DAC7716 that does not allow
the RefGND-A/RefGND-B to have more than a 0.3V difference from the board AGND on the DAC. A
jumper across pins 2 and 3 on JP6 and JP7 connects the RefGND-A and RefGND-B to the ground of the
board.
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EVM Operation
Note that if an external reference voltage is input to J1.20, it will be filtered through a first-order, low-pass
RC filter. To input your own reference signal without this filter, connect the reference signal directly to TP1
Figure 1. Reference Test Points
6
EVM Operation
This section provides information on the analog input, digital control, and general operating conditions of
the DAC7716EVM.
6.1 Analog Output
The DAC7716 has four analog outputs that are available through the J1 header or the J4 header. The J4
header is designed to use 90-degree Samtec pins (not installed) when multiple EVMs are stacked to be
used in daisy-chain mode.
Jumpers J5-J8 control the gain of the individual output channels by connecting additional feedback
resistors to the internal op amp buffer. See the DAC7716 data sheet for more information on setting the
gain. Each analog output is able to swing ±16V in bipolar mode and 0 to 20V in unipolar mode.
The signal ground, SGND-N (for the output signals), are connected to header J1 and are short-circuited to
the board ground. All of the output signals are referenced to the ground of the board.
VMON is the channel monitor output. It can relay any of the four analog output signals or the AIN signal. The
VMON signal is buffered and current-limited through the OPA227 (U2). By default, the VMON pin is in 3-state
mode, causing the op amp to saturate. In order to avoid the op amp saturating to a rail, a 200kΩ resistor is
put in place. The resistor serves as a load for the op amp when the VMON pin is in 3-state mode. However,
as a result, there is an error of ~1% on the VMON_BUF signal when relaying a signal.
6.2 Digital Control
The digital control signals can be applied directly to J1 (top or bottom side). The modular DAC7716EVM
can also be connected directly to a DSP or microcontroller interface board.
No specific evaluation software is provided with this EVM; however, various code examples are available
that show how to use EVMs with a variety of digital signal processors from Texas Instruments. Check the
examples. The EVM Gerber files are also available on request.
6
DAC7716EVM
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EVM Operation
6.3 Default Jumper Settings and Switch Positions
Figure 2 shows the jumpers found on the EVM and the respective factory default conditions for each.
Figure 2. DAC7716EVM Default Jumper Locations
Jumper JP1 controls whether the LDAC signal is controlled by J2.15 or J2.17. By default, the LDAC signal
is controlled by J2.17 but can be changed using JP1.
Jumpers JP2, JP3, JP4, and JP5 are used to control the gain of the individual DAC channels. By default,
the jumpers are removed, resulting in each DAC channel having a gain of 4. The gain of the output
channel is 2 when the corresponding jumper is in place.
JP6 and JP7 control the signals applied to REFGND-A and REFGND-B on the DAC7716. By default, a
jumper is placed across JP6.2 and JP6.3 as well as JP7.2 and JP7.3. This jumper connects REFGND-A
and REFGND-B to the ground of the board when an onboard reference is used. When an external
reference source is used, it is recommended that this jumper stay in place and configure the external
reference source to share a common ground with the EVM. See the Reference Voltage section for more
information.
Jumper JP8 is used to control the digital voltage for IOVDD. By default, a jumper is in place to short-circuit
pins JP8.1 and JP8.2 to use a 3.3V digital supply. If pins JP8.3 and JP8.4 are connected, a 1.8V digital
supply will be used. If pins JP8.5 and JP8.6 are connected, a 5V digital supply will be used for IOVDD.
Jumper JP9 is not installed. If the user desires to disconnect RFB1 from VOUT1, the trace between JP9
must be cut. JP9 can then be installed.
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Schematics and Layout
Switch S1 allows the user to pull down four control signals to ground. LDAC, Uni/Bip B, RST, and Uni/Bip
A can be pulled low using the switch. By default, switch position S1.1 is open, causing LDAC to be
connected to ground. Switches S1.2 and S1.4 are open to short-circuit Uni/Bip A and Uni/Bip B to ground.
This configuration sets the DAC7716 to bipolar mode (default). Figure 3 shows the default settings for
switch S1.
Figure 3. Default Settings for Switch S1 (LDAC Low)
Switch S2 controls the reference voltage selection for Ref B. When the switch is furthest left (position 1),
the onboard 5V reference is used from the REF5050. When the switch is in the middle position (position
2), the onboard 2.5V reference is used from the REF5025. If the switch is moved to the right (position 3),
Ref B is set up to use an external reference. Pins J1.18 (Ref–) and J1.20 (Ref+) are used to apply an
external reference voltage.
Switch S3 controls the reference voltage selection for Ref A. The switch has the same functionality as
switch S2. By default, switch S2 and switch S3 are set to use the 5V onboard reference, as Figure 4
shows.
Figure 4. Default Settings for Switch S2 and S3
Schematics and Layout
7
Schematics for the DAC7716EVM are appended to this user's guide. The bill of materials is provided in
7.1 Bill of Materials
NOTE: All components should be compliant with the European Union Restriction on Use of
Hazardous Substances (RoHS) Directive. Some part numbers may be either leaded or
RoHS. Verify that purchased components are RoHS-compliant. (For more information about
8
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Schematics and Layout
space
Table 4. DAC7716EVM Bill of Materials(1)
Item No.
Qty
1
Ref Des
Description
Manufacturer
Mfr Part Number
1
2
N/A
Printed wiring board
Texas Instruments 6508538
6
C1, C6, C10,
C11, C14, C15
Capacitor, ceramic 1.0µF 16V X5R
10% 0603
TDK
C1608X5R1C105K
GRM31CR61E106KA12L
3
4
7
4
C2, C3, C4,
C5, C7, C8,
C9
Capacitor, ceramic 10µF 25V X5R
1206 10%
MuRata
C12, C13,
C16, C 17
Capacitor, ceramic 10µF 10V 0603
X5R 20%
Panasonic
ECJ-1VB1A106M
5
6
7
0
3
5
D1
Not installed
N/A
N/A
JP1, JP6, JP7
Header strip, 3-pin (1x3)
Header strip, 2-pin (1x2)
Samtec
Samtec
TSW-103-07-L-S
TSW-102-07-L-S
JP2, JP3, JP4,
JP5, JP9
8
9
1
2
JP8
Header strip, 6-pin (2x3)
Samtec
Samtec
TSW-103-07-L-D
J1A, J2A
(Top Side)
10-Pin, Dual Row, SM Header (20
Pos.)
TSM-110-01-T-DV-P
10
11
12
13
0
1
1
1
J1B
(Bottom Side)
Not installed
N/A
N/A
J2B
(Bottom Side)
10-Pin, Dual Row, SM Header (20
Pos.)
Samtec
Samtec
Samtec
SSW-110-22-F-D-VS-K
TSM-105-01-T-DV-P
SSW-105-22-F-D-VS-K
J3A
(Top Side)
J3B(2)
5-Pin, Dual Row, SM Header (10 Pos.)
5-Pin, Dual Row, SM Header (10 Pos.)
(Bottom Side)
14
15
0
5
J4
Not installed
N/A
N/A
R1, R2, R3,
R4, R5
Resistor 33 Ω 1/10W 5% 0603 SMD
Panasonic
ERJ-3GEYJ330V
16
6
R6, R7, R8,
Resistor 10 kΩ 1/10W 5% 0603 SMD
Yageo
RC0603JR-0710KL
R9, R10, R11
17
18
19
20
21
2
2
1
1
2
R12, R13
R14, R15
R16
Resistor 1.0 kΩ 1/10W 5% 0603 SMD
Resistor 1.0 Ω 1/10W 5% 0603
Resistor 200 kΩ 1/10W 1% 0603 SMD
Switch Dip Tape 4 pos
Panasonic
Panasonic
Panasonic
C&K
ERJ-3GEYJ102V
ERJ-3GEYJ1R0V
ERJ-3EKF2003V
TDA04H0SB1R
SS14MDP2
S1
S2, S3
SW SLIDE ULTRA MINI SP3T TOP
ACT
NKK
22
23
24
3
2
1
TP1, TP2 ,TP3
TP4, TP5
U1
Test Point - Single .025 Pin, Red
Test Point - Single .025 Pin, Black
Keystone
Keystone
5000
5001
Quad, 12-bit, High Accuracy DAC,
TQFP Package
Texas Instruments DAC7716SPFB
25
1
U2
OPA227, Differential Operational
Amplifier
Texas Instruments OPA227UA
26
27
28
29
1
1
1
8
U3
U4
Single output, 8V voltage regulator
Precision Voltage reference 2.5V
Precision Voltage reference 5.0V
0.100 Shunt - Black
Texas Instruments TL750L08CD
Texas Instruments REF5025AID
Texas Instruments REF5050AID
U5
N/A
Samtec
SNT-100-BK-T
(1)
(2)
Manufacturer and part number for items may be substituted with electrically equivalent items.
J3B parts are not shown in the schematic diagram. J3B is installed on the bottom side of the PWB opposite to J3A.
9
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1
2
3
4
5
6
REVISION HISTORY
ENGINEERING CHANGE NUMBER
REV
APPROVED
IOVDD
+VA
-VA
+5VD
LDAC
SDO
CS
C3
10uF
C4
10uF
C6
1uF
C1
1uF
C2
10uF
C5
10uF
SCLK
D
D
C
B
A
GPIO-0
1
3
5
7
9
2
4
6
8
10
GPIO-1
Uni/Bip A
C7
R6 R7 R8
10k 10k 10k
R9 R10 R11
10k 10k 10k
+VA
U2
2
10uF
OPA227
Uni/Bip B
RST
11 12
13 14
15 16
17 18
19 20
D1B
6
3
C8
R1
R16
CS
SCLK
SDI
SDO
LDAC
2
3
4
5
6
34
33
33
33
33
33
CS
SCLK
SDI
SDO
LDAC
Vmon
-VA
R2
R3
R4
R5
Serial Header Top
J2A
J1A
A0(-)
A1(-)
A2(-)
200k
10uF
15
17
16
18
1
3
5
7
9
11
13
15
17
19
2
4
6
8
Vout-0
Vout-1
Vout-2
Vout-3
Vout-0
RFB1-0
RFB2-0
SGND-0
A0(+)
A1(+)
A2(+)
A3(+)
A4
A5
A6
A7
REF-
REF+
J4
A3(-)
8
7
6
5
4
3
2
1
47
10 Vmon_buf
12
14 Ain
16
18 ExtREF-
20 ExtREF+
Ain
AGND
AGND
AGND
VCOM
AGND
AGND
23
21
22
20
JP1
3POS_JUMPER
Vout-1
RFB1-1
RFB2-1
SGND-1
Uni/Bip A
Uni/Bip B
RST
10
48
U1
DAC7716
Uni/Bip A
Uni/Bip B
JP9
JP2
36
37
1
25
24
19
12
42
NC
NC
NC
NC
NC
NC
NC
NC
GPIO-0
GPIO-1
46
44
45
43
Vout-2
RFB1-2
RFB2-2
SGND-2
DAUGHTER-ANALOG
JP3
JP4
HEADER-8
GPIO-0
Analog to only be populated at top of board
1
3
5
7
9
2
4
6
8
10
C
GPIO-1
Uni/Bip A
S1
DIPSWITCH-4
38
40
39
41
J1B
Vout-3
RFB1-3
RFB2-3
SGND-3
1
3
5
7
9
2
4
6
8
Uni/Bip B
RST
11 12
13 14
15 16
17 18
19 20
7
RST
JP5
10
D1A
11 12
13 14
15 16
17 18
19 20
Serial Header Bottom
J2B
TP3
SDI
DAUGHTER ANALOG BOTTOM
-VA
CS
SCLK
JP6 and JP7 control the RefGND
JP7
3POS_JUMPER
+VA
TP1
R12
1k
B
3
2
1
3
2C
1
C
JP6
U3
TL750L08
3POS_JUMPER
NKK_SS14MDP2
S2
1
Output
TP4
TP5
C16
10uF
8
5
4
U5
VIN
TEMP
GND TRIM
Input
NC
2
3
6
2
3
4
6
5
Com
VOUT
C9
10uF
C10
1uF
Com
NC
R14
1
REF5050
Com
ExtREF+
C14
1uF
C12
10uF
+3.3VD +1.8VD +5VA
+VA
-VA
-5VA
+5VD
J3
+VA
+5VA
DGND AGND
+1.8VD VD1
1
3
5
7
9
2
4
6
8
-VA
-5VA
U4
2
3
4
6
5
VIN
TEMP
GND TRIM
VOUT
C11
1uF
10
TP2
+3.3VD +5VD
R15
1
REF5025
DAUGHTER-POWER
R13
1k
C15
1uF
ti
C13
10uF
S3
A
C17
10uF
NKK_SS14MDP2
PRECISION ANALOG PRODUCTS
HIGH-PERFORMANCE ANALOG DIVISION
SEMICONDUCTOR GROUP
5411 EAST WILLIAMS BOULEVARD, TUCSON, AZ 85711 USA
JP8
TITLE
JPR-2X3
IOVDD
ENGINEERT. Calabria
DAC8734EVM
DRAWN BYT. Calabria
DOCUMENT CONTROL NO.6508538
SIZE B
DATE
REV
A
SHEET
OF
FILE
1
2
3
4
5
6
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
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FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of –16.5V to +21V and the output voltage range of –15V to +15V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +30° C. The EVM is designed to
operate properly with certain components above +60° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
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Copyright © 2009, Texas Instruments Incorporated
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