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Implementation
Guide
August 2000
PCI Bus Solutions
SCPU007
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Preface
Read This First
About This Manual
This manual is intended to assist the designer who is attempting to implement
a solution using the PCI4450 or PCI4451. Much, but not all, of the information
contained herein can also be found elsewhere. However, the smaller size of
this manual, as well as its organization by topics of primary interest to the
hardware designer, make it a much more usable source regarding those
problems most likely to be encountered in the design process.
How to Use This Manual
This document contains the following chapters:
Chapter 1, PCI445X Device, provides the designer with information and
examples beyond that contained in the data manuals, which will be useful for
implementing solutions using the PCI4450 or PCI4451.
AppendixA, GlobalResetOnlyBits, PMEContextBitscontainstabularlistings
of those register bits that can only be cleared by a global reset, and of those
register bits used in conjunction with power management events.
Appendix B, PME and RI Behavior, provides truth tables that explain events
and conditions which can wake up a device that has been placed in partially
functional state for power conservation.
Appendix C, PCI445X Buffer Types, lists the type of signal buffering used for
input and/or output on each terminal of the device.
Notational Conventions
This document uses the following conventions.
- Program listings, program examples, and interactive displays are shown
in a special typefacesimilar to a typewriter’s. Examples use a bold
versionof the special typeface for emphasis; interactive displays use a
bold versionof the special typeface to distinguish commands that you
iii
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Contents
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001
0012 0005 0003
0013 0005 0006
0014 0006
.field
.field
.field
.even
1, 2
3, 4
6, 3
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities
- In syntax descriptions, the instruction, command, or directive is in a bold
typefacefontandparametersareinanitalictypeface. Portionsofasyntax
that are in bold should be entered as shown; portions of a syntax that are
in italics describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect “section name”, address
.asect is the directive. This directive has two parameters, indicated by
section name and address. When you use .asect, the first parameter must
be an actual section name, enclosed in double quotes; the second
parameter must be an address.
- Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK 16–bit constant [, shift]
The LALK instruction has two parameters. The first parameter, 16-bit
constant, is required. The second parameter, shift, is optional. As this
syntax shows, if you use the optional second parameter, you must
precede it with a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path-
name (they are not optional).
- Braces ( { and } ) indicate a list. The symbol | (read as or) separates items
within the list. Here’s an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
- Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this
directive is:
.byte value [, ... , value ]
1
n
iv
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Trademarks
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.
Related Documentation From Texas Instruments
PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet, SCPS046
PCI4451 GFN/GJG PC Card and OHCI Controller Data Manual, SCPS054
OHCI.Lynx Configuration Information Application Report, SLLA077
PHY Layout Recommendations Application Report, SLLA020A
TSB41LV03A Data Sheet, SLLS364
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
MicroStar BGA is a trademark of Texas Instruments.
TI is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation. (Windows 95, Windows )
v
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vi
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Contents
1
PCI445X Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
System Features Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.1 Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.2 G_RST and PRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.3 PME and RI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.4 ZV Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.5 EEPROM for Subsystem Vendor and Subsystem ID Registers . . . . . . . . . . . . 1-3
1.1.6 PCI and ISA Style Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.7 Socket Power Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.8 Distributed DMA (DDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.9 Optional PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.10 Socket Activity LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.11 MFUNC7–MFUNC0 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.12 Miscellaneous Functions Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.1 Clamping Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.2 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.2.3 PC Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2
1.3
2
1.2.4 2-Wire (I C) Interface for EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Sample PCI445X EEPROM Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2
1.3.1 P C Interface for TPS22x6 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.2 Zoomed Video (ZV) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.3 Interrupt Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.3.4 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.3.5 Requirement of Pullup/Pulldown Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
BIOS Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.4.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.4.2 System Sleeping State Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.4.3 Docking System Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Important Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.5.1 G_RST Clamping Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.5.2 PME/RI_OUT Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.5.3 Serialized IRQ Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.5.4 Socket Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.4
1.5
2
1.5.5 External CLOCK Frequency for P C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
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Contents
A
B
C
Global Reset Only Bits, PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 Global Reset Only Bits/PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
PME and RI Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 PME and RI Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
PCI445X Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1 PCI445X Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
viii
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Figures
1–1
1–2
1–3
1–4
1–5
1–6
1–7
Typical System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Serialized Interrupt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
EEPROM 2-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
TPS22X6 Power Switch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Example of a ZV Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Distributed DMA Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
G_RST and V
Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
CCP
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Tables
1–1
1–2
1–3
1–4
1–5
A–1
A–2
B–1
B–2
C–1
C–2
Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
PC Card Interface Pullup Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
PCI Bus Interface Pullup Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Miscellaneous Terminals Pullup Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Required Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Global Reset Only Cleared Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
PME Context Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
CardBus CTSCHG and Wake-Up Signals Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
16-Bit Card RI/STSCHG and Wake-Up Signals Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . B-2
PCI445X Terminal Function Assignment and Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Buffer Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
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Chapter 1
PCI445X Device
This implementation guide assists platform hardware developers designing
with the PCI445X dual socket PC card and 1394 open host controller interface
(OHCI) link layer controller (LLC). The PCI445X designation refers to any
device in the PCI445X family, for example, the PCI4450 or PCI4451 device.
The document includes an overview of the PCI445X function and features,
terminal assignments and pinout illustrations, PCI445X I/O electrical
characteristics, identification of required passive components and
recommendations for system implementation, and PHY/Link interface signal
isolation considerations.
Advantages of the PCI445X device:
- G_RST (Section 1.1.2)
- Internal ring oscillator (Section 1.3.1)
- Zoomed video auto-detect function (Sections 1.1.4, 1.3.2)
- Integrated IEEE1394 OHCI link layer controller
Topic
Page
1.1 System Features Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.3 Sample PCI445X EEPROM Data File . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.4 BIOS Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.5 Important Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1-1
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Figure 1–1 illustrates a platform using the PCI445X device along with the
TSB41LV03 3-port PHY, which provides the necessary interface to implement
a 3-port IEEE1394 node.
Figure 1–1. Typical System Architecture
North
Bridge
CPU
Memory
PCI Bus
19
South
Bridge
Sound
Controller
Graphics
Controller
PCI445X
ZV
Socket
Power
4
Power
Switch
Audio
Codec
14
PC Card
2
EEPROM
Interrupt / PME / RI
TSB41LV03A
PHY
1-2
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System Features Selection
1.1 System Features Selection
Thissectionexplainsselectablesystemfeatures. Featureselectionisrequired
for GPIO and MFUNC terminal assignments and PCI445X register
initialization. Detailed system implementation methods are described in the
following sections. All functions cannot necessarily be used at the same time,
because of the limitations of programmable multifunction terminals (i.e.,
MFUNC7–MFUNC0).
1.1.1 Package Types
The Texas Instruments PCI445X device is offered in two package types:
256-terminal ball grid array (BGA) and 257-terminal MicroStar BGA .
MicroStar BGA is a type of chip scale packaging (CSP).
1.1.2 G_RST and PRST
The PCI445X device has two reset inputs, G_RST and PRST. G_RST resets
all registers and state-machines; PRST resets registers that are not required
to maintain context in a low power state (see Table A–1 and Table A–2). If the
system does not support a wake-up event from D3-state (hot or cold), then
these terminals can be tied together.
1.1.3 PME and RI Signaling
For supporting a wake-up event, a power management event (PME) and/or
an RI signal should be signaled to the system. PME is available only on the
RI_OUT/PME terminal. RI_OUT is available on RI_OUT/PME or MFUNC7.
PME and RI_OUT signals are usually connected to the south bridge or
embedded controller (EC). Detailed PME and RI signal behavior is explained
later.
1.1.4 ZV Support
The PCI445X device has internal zoomed video (ZV) buffers. It can support
three ZV sources, from two PC cards and one external source. Refer to the
detailed implementation guide in Section 1.3.2. The PCI445X device has the
ZV autodetect function for supporting a third external zoomed video source.
ZVSTAT and ZVPCLK are required to support the third source. (The ZV
autodetect function needs ZVPCLK for input, and ZVSTAT for enabling.)
ZVSTAT can be assigned on the MFUNC0, MFUNC1, or MFUNC4 terminal.
1.1.5 EEPROM for Subsystem Vendor and Subsystem ID Registers
Subsystem vendor ID and subsystem ID registers (PCI offsets 40h and 42h)
can be loaded from EEPROM through a two-wire serial interface. These
registers can be configured by BIOS if the PCI445X device is implemented on
the motherboard, by setting the SUBSYSRW bit (system control register, PCI
offset 80h, bit 5). EEPROM may be required for docking systems and is
required for add-in cards. The EEPROM interface terminals SDA and SCL are
1-3
PCI445X Device
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System Features Selection
automatically assigned on the dedicated SDA and SCL terminals. A pullup
resistor (typically 10 kΩ) must be added on SDA and SCL when using an
EEPROM. The value of the pullup resistor can vary for different EEPROMs.
Refer to the EEPROM data sheet or contact the manufacturer for the
recommended pullup resistor value.
1.1.6 PCI and ISA Style Interrupt
The PCI445X device provides three modes of interrupt signaling:
- Parallel PCI interrupts only
- Parallel PCI interrupts and serialized ISA interrupts
- Serialized PCI interrupts and serialized ISA interrupts
Three PCI interrupts (INTA, INTB, and INTC) may be used and signaled in
either the parallel mode using the MFUNC terminals or in the serial mode. The
number of PCI interrupts may be reduced by setting the INTRTIE bit (system
control register, PCI offset 80h, bit 29), which allows both the CardBus
functions (function 0 and function 1) to report and use INTA or by setting the
TIEALL bit (system control register, PCI offset 80h, bit 28) which allows all 3
functions (both CardBus + OHCI) to report and use INTA.
1.1.7 Socket Power Switches
The PCI445X device supports TPS2206 and TPS2216 power switches. Refer
to the detailed explanation on each data sheet. The interface between the
power switch and the PCI445X device is serialized, so an external or internal
clock source is required. By default an external power switch clock is assumed
but this can be changed to use the oscillator internal to the PCI445X device
2
by setting P CCLK bit (system control register, PCI offset 80h, bit 27).
1.1.8 Distributed DMA (DDMA)
Most of the systems do not use this function. This function needs PCGNT and
PCREQ signals. PCGNT can be assigned to the MFUNC2 or MFUNC3
terminal. PCREQ can be assigned to the MFUNC0, MFUNC4, or MFUNC7
terminal. (See Section 1.3.4.5, Distributed DMA.)
1.1.9 Optional PCI Signals
1.1.9.1 CLKRUN
CLKRUN is the primary method for power reduction on the PCI bus. Most of
the notebook PCs implement CLKRUN. The PCI445X device has a dedicated
CLKRUN terminal. If it is not used, then a pulldown resistor is required to
prevent oscillations on this input.
1.1.9.2 LOCK
This signal can be assigned on the MFUNC1, MFUNC3 or MFUNC7 terminal.
1-4
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System Features Selection
1.1.10 Socket Activity LEDs
SocketactivitysignalscanbeassignedonMFUNC4(slot1), MFUNC3 (slot 2),
MFUNC5 (OHCI_LED), MFUNC6 (OHCI_LED), and MFUNC7 (OHCI_LED).
1.1.11 MFUNC7–MFUNC0 Terminal Assignments
After selecting required functions for the system, multifunction terminals
MFUNC7–MFUNC0 are ready to be assigned. Texas Instruments offers
Windows-based software, named TIROUTE.EXE, to assist with terminal
assignment.
1.1.12 Miscellaneous Functions Description
1.1.12.1 Serialized Interrupt Control
Serialized interrupt signaling is described below.
Figure 1–2. Serialized Interrupt Signal
PCLK
IRQSER
START Frame
IRQ0
IRQ1
SMI
IRQ3
INTD
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ10 IRQ11 IRQ12
PCLK
IRQSER
IRQ13 IRQ14 IRQ15 IOCHCK INTA
INTB
INTC
STOP Frame
The start frame width may vary from four to eight PCI clock cycles. The STOP
frame width is two clock cycles for quiet mode and three clock cycles for
continuous mode. Default mode is continuous mode for all slave devices and
a host device. PIIX4 does not support IRQ0, IRQ8, and IRQ13.
The PCI445X can generate serial IRQ frames for ISA and PCI interrupts.
Below are related registers and their definitions.
- INTMODE bits (device control register, PCI offset 92h, bits 2–1). Select
interrupt mode
- SER_STEP bits (system control register, PCI offset 80h, bits 31–30).
Change PCI interrupt data frame (serial interrupts only)
- INTRTIE bit (system control register, PCI offset 80h, bit 29). Tie CardBus
PCI interrupts to INTA
- TIEALL bit (system control register, PCI offset 80h, bit 28). Tie all PCI
interrupts internally
Refer to the Serialized IRQ Support for PCI Systems specification,
revision 6.0.
1.1.12.2 CSC Interrupt Routing for Windows Compatibility
The CSC interrupt routing control bit (diagnostic register, PCI offset 93h, bit 5)
should be set to 1 (default) to keep Windows compatibility.
1-5
PCI445X Device
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System Features Selection
1.1.12.3 Asynchronous CSC Interrupt Generation
The ASYNC_CSC bit (diagnostic register, PCI offset 93h, bit 0) controls the
CSC interrupt signaling method. If this bit is set to 0, then CSC is generated
synchronously to PCLK (recommended). By default this bit is set to 1, which
is the asynchronous mode.
1.1.12.4 CardBus Reserved Terminal Signaling
The CardBus interface has reserved terminals. Usually the CardBus controller
drives these terminals low. If the CBRSVD bit (system control register, PCI
offset 80h, bit 22) is set to 0, then the CardBus reserved terminal signals are
in a high-impedance state when a CardBus card is inserted in the socket.
1.1.12.5 Memory Burst R/W Operation Control
Memory read bursting is controlled via the MRBURSTDN bit (system control
register, PCI offset 80h, bit 15) for downstream burst transactions (PCI-to-PC
Card) and the MRBURSTUP bit (system control register, PCI offset 80h,
bit 14) for upstream burst transactions (PC Card-to-PCI). Memory write
bursting is controlled via the POSTEN bit (bridge control register, PCI offset
3Eh, bit 10). This bit enables write posting if disabled. No write data can be
accepted (including burst writes) until any previous write data has been
forwardedtoitsdestination. Bydefault, writepostingandupstreamreadbursts
are disabled.
1.1.12.6 Power Savings Mode
The PCI445X device has a proprietary power-saving mode. It can be disabled
by changing the PWRSAVINGS bit (system control register, PCI offset 80h,
bit 6) to 0. When this bit is enabled (default), PCI CLOCK is internally gated
for a nonfunctioning circuit. For example, the CardBus interface does not
function when a 16-bit card is inserted. This power-saving mode will not
degrade performance; therefore, the default setting is recommended.
1.1.12.7 PME/RI_OUT Terminal Control Clarification
PME/RI_OUT terminal can be set up to signal a combination of these events.
The terminal is set up using the PME/RI_OUT bit (system control register, PCI
offset 80h, bit 0), the RIENB bit (card control register, PCI offset 91h, bit 7), and
PME enable bit (power management control/status, PCI offset A4h, bit 8). If
the terminal is set up as RI_OUT and RIENB has ring indicate enabled, then
this signal follows the RI_OUT signal for 16-bit I/O cards. If RIENB has ring
indicate disabled but PME has PME enabled, then this line reflects the state
of the PMESTAT bit (power management control/status, PCI offset A4h,
bit 15). If both PME and ring indicate are disabled, then the line remains high.
If the line is configured as PME and PME is enabled, then this line follows the
state of the PMESTAT bit; otherwise, the line remains high.
1.1.12.8 CLKRUN Control
PCLK can be kept running using CLKRUN protocol by setting the KEEPCLK
bit (system control register, PCI offset 80h, bit 1) to 1.
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CCLK can be slowed down rather than stopped by CCLKRUN. If CCLKRUN
is set, the CLKCTRLEN (CardBus socket 20h, bit 16) and CLKCTR (CardBus
socket 20h, bit 0) bits are both set to 1. The clock is slowed down to 1/16. In
this mode the PCI clock is not allowed to stop.
1.1.12.9 SMI
A PC card power change event can be reported to the system as SMI (IRQ2
or CSC). It can be controlled with the SMIROUTE, SMISTATUS, and SMIENB
bits (system control register, PCI offset 80h, bits 26, 25, and 24, respectively).
1.1.12.10 Socket Power Lock
Socket power can be protected from software control in the D3 state. It can
hot
be done with the socket power lock bit (device control register, PCI offset 92h,
bit 7).
1.1.12.11V
Protection
CC
TheVCCPROTbit(systemcontrolregister,PCIoffset80h,bit21)controlsV
CC
protection for 16-bit cards. This feature protects applying the wrong (higher)
V
to the 16-bit card. If a 3.3-V-only card is inserted, then it protects against
CC
applying 5 V to the card. Default is 0 (enabled).
1.1.12.12 ZV Port Control and Auto Detect Function
Internal zoomed video buffers can be controlled with the ZV autodetect
function. It can be turned on by setting the zoomed video autodetect bit
(multimedia control register, PCI offset 84h, bit 5) to 1. Autodetect priority
encoding bits (multimedia control register, PCI offset 84h, bits 4–2) can control
the priority scheme.
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1.2 System Implementation
This section describes signal connection for each interface, PCI bus, PC card
2
2
interface,I Cinterface,P Cinterface,ZVinterface,interruptinterface(parallel
and serial), miscellaneous signals, and the PHY-Link interface. It also explains
pullup/pulldown resistor requirements.
1.2.1 Clamping Rails
The PCI445X device has three clamping rails: V
, V
, and V
. V
CCA CCB
CCP CCA
and V
are not power supplies for PC cards. After a card is powered up, the
CCB
supply voltage to the card is fed back into the V
(or V
) input to the
CCA
CCB
controller. This provides the controller a clamping level for signals to the card.
Technically the power switch controlling V is also supplying power to the
CCA
card via this signal, but actually V
supplies power to the card.
is not a signal via which the controller
CCA
The PCI445X device only drives out a maximum signal of 3.3 V due to the
3.3-V core. This is not a problem, as 3.3 V is still seen as a logic 1 to a 5-V
system.
- V
CCA
and V
CCB
PC Card interface clamping rails. CD1, CD2, VS1, VS2, and STSCHG/RI
are not clamped, because these terminals should be able to signal without
V
/V
.
CCA CCB
- V
CCP
PCI bus interface clamping rail. It includes the MFUNC7/LOCK,
2
MFUNC7–MFUNC0, IRQSER, GRST, and P C terminals. It excludes
INTA, INTB, INTC, and PME.
Note:
The PME/RI_OUT terminal uses an open drain (OD) buffer.
1.2.2 PCI Bus Interface
- PCLK, AD31–AD0, C/BE3–C/BE0, PAR, DEVSEL, FRAME, STOP,
TRDY, IRDY, GNT, REQ
These terminals can be connected to the system PCI bus directly. GNT
and REQ are dedicated signals from the PCI bus arbitrator.
- PERR, SERR, and LOCK
PERR and SERR are required signals. LOCK is an optional signal and
available in MFUNC1, MFUNC3, and MFUNC7.
- IDSEL
IfthereisapulldownonLATCH, thentheIDSELwillberoutedtoAD23, but
the consequence of this is that the system designer must use AD23 as
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IDSEL, there is no alternative. If another AD line is to be used for IDSEL,
then the system designer must leave the pullup off LATCH and use
MFUNC7 to route IDSEL. Also, if AD23 is used, then the resistive coupling
should not be used.
Refer to the Implementation Note: System Generation of IDSEL in the PCI
Local Bus Specification, Revision 2.2 (section 3.2.2.3.5). PCI Local Bus
Specification, Revision 2.2 (section 4.2.6, footnote 31) recommends
resistive coupling. A 100-Ω resistor is recommended.
- PRST (PCI reset) and G_RST (Global reset)
G_RST initializes all of the registers and state-machines of the PCI445X
device, and PRST does not. G_RST should be asserted during power-on
and rebooting. It puts the PCI445X device into the initialized state. PRST
does not initialize global-reset-only bits and, if PME is enabled, PME
context bits. Refer to Table A–1, Global Reset Only Cleared Bits, and
Table A–2, PME Context Bits. PRST is connected to PCI RESET; G_RST
requires a special signal in the motherboard. It will come from the chipset.
If the system does not support wake-up from D3
then PRST and
cold,
G_RST can be tied together. Note that G_RST and PRST are clamped to
V
CCP.
- INTA, INTB, and INTC
WhenusingoneoftheparallelPCIinterruptmodes, INTA, INTB, andINTC
should be connected to the PCI interrupt lines. If the INTRTIE bit (system
control register, PCI offset 80h, bit 29) is set, then both CardBus functions
(functions 0 and 1) will signal and report INTA, and only INTAand INTCwill
need to be routed. If the TIEALL bit (system control register, PCI offset
80h, bit 28) is set, then all functions (0, 1, and 2) will report INTA and INTA
will be the only interrupt required.
- CLKRUN
This signal is optional. However, if saving power is a concern, this signal
should be implemented. Refer to the PCI Mobile Design Guide
Revision 1.1 (Section 2).
- PME
This signal is required for the ACPI systems. In a notebook PC, this signal
is usually connected to the south bridge (ex., PIIX4) or embedded
controller (EC). The PME terminal uses an open-drain type buffer.
Note: Pullup Resistor Requirements
A pullup resistor is required for each of the following terminals: IRDY, TRDY,
FRAME, STOP, DEVSEL, PERR, SERR, LOCK, PRST, G_RST, INTA, INTB,
INTC, CLKRUN, and PME.
1-9
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1.2.3 PC Card Interface
The PC Card interface has two modes: the 16-bit interface mode and the
CardBus 32-bit interface mode.
- Damping resistor on CCLK terminal
A series-damping resistor is recommended on the CCLK signal. The
damping resistor is system dependent. If line impedance is in the 60–90-Ω
range, a 47-Ω resistor is recommended (see PC Card Standard,
Revision 7).
- CD line filtering
PCI445X device has the advanced CDx line filtering circuit. It provides
90 µs of noise immunity. A 270-pF filtering capacitor is still recommended
for each of the power supply terminals: V , V
, and V
.
CC CCS
CCP
- Socket power supply
Socket power is supplied through TPS22X6 power switches. The
PCI445X device requires V
device(s) on the bus.
and V
for the protection of the other
CCA
CCB
2
1.2.4 2-Wire (I C) Interface for EEPROM
The PCI445X device can load configuration registers from EEPROM after
G_RST assertion. The SDA and SCL lines require pullup resistors to enable
this function. Depending on the EEPROM requirements, the SDA and SCL
lines must be pulled up to 3.3 V or 5 V.
Figure 1–3. EEPROM 2-Wire Interface
SDA
SCL
EEPROM
TPS22X6
PCI445X
EEPROM slave address should be 101 0000b.
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Table 1–1.Registers and Bits Loadable Through Serial EEPROM
Register Offset
Register
Bits Loaded From
EEPROM
The following are configuration registers for the OHCI function (function 2)
PCI register (2Ch)
PCI register (2Dh)
PCI register (3Eh)
PCI register (F0h)
PCI register (F4h)
OHCI register (24h)
OHCI register (28h)
PCI subsystem ID
15–0
15–0
PCI vendor ID
PCI maximum latency, minimum grant
11–8, 3–0
PCI miscellaneous configuration
Link enhancements control
1394 global unique ID Hi
15, 13, 10, 3–0
7, 2, 1
31–0
1394 global unique ID Lo
31–0
The following are configuration registers for PC Card functions (functions 0 and 1)
PCI register (40h)
Subsystem vendor ID
Subsystem ID
15–0
PCI register (42h)
PCI register (80h)
PCI register (86h)
PCI register (89h)
PCI register (8Bh)
PCI register (8Ch)
15–0
System control
31–24, 22–14, 6–3, 1, 0
General control
3–0
7, 6, 3–0
3–0
General-purpose event enable
General-purpose output
Multifunction routing
30–28, 26–24, 22–20,
18–16, 14–12, 10–8,
6–4, 2–0
PCI register (91h)
PCI register (92h)
PCI register (93h)
PCI register (A2h)
PCI register
Card control
7, 6, 2–0
7, 6, 2–0
7, 5, 0
15
Device control
Diagnostic
Power management capabilities
ExCA ID and revision
7–0
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1.3 Sample PCI445X EEPROM Data File
Following is an example EEPROM data file used with the PCI445X device:
;PCI4450 default EEPROM Data File
;Register 0xXX Binary
;–––––––– –––– ––––––
Description
–––––––––––
00
4 bits)/PCI min gnt (lower 4 bits)
0x43 ;01000011 PCI max_lat (lower
01
0x4C ;01001100 PCI Subsystem Vendor ID (lsbyte) ** Insert
your SSVID LSB
02
0x10 ;00010000 PCI Subsystem Vendor ID (msbyte) ** Insert
your SSVID MSB
03
0x11 ;00010001 PCI Subsystem ID (lsbyte)
** Insert
** Insert
Control
your SSID LSB
04
0x80 ;10000000 PCI Subsystem ID (Msbyte)
your SSID MSB
05
defaults
0xC2 ;11000010 Link
Enhancement
Register/HC
06
0x40 ;01000000 MiniROM_Addr
07
0x56 ;01010110 1394 GUIDHi (lsbyte)** Insert GUIDHi byte
0x28 ;00101000 1394 GUIDHi (lsbyte)** Insert GUIDHi byte
0x00 ;00000000 1394 GUIDHi (msbyte)** Insert GUIDHi byte
0x08 ;00001000 1394 GUIDHi (msbyte)** Insert GUIDHi byte
0xXX ;XXXXXXXX 1394 GUIDLo (lsbyte)** GUIDLo byte 0 auto
008
109
20A
30B
incremented from ;serial.dat
0C
0xXX ;XXXXXXXX 1394 GUIDLo (lsbyte)** GUIDLo byte 1 auto
incremented from ;serial.dat
0D
0xXX ;XXXXXXXX 1394 GUIDLo (msbyte)** GUIDLo byte 2 auto
incremented from ;serial.dat
0E
0xXX ;XXXXXXXX 1394 GUIDLo (msbyte)** GUIDLo byte 3 auto
incremented from ;serial.dat
0F
10
11
12
13
19
1A
1B
1C
0xXX ;XXXXXXXX ROM CRC (Calculated by EELynx)
0x10 ;00010000 Link_Enh Byte 1
0x00 ;00000000 PCI Misc Byte 0
0x24 ;00100100 PCI Misc Byte 1
0xFF ;11111111 this area reserved
0xFF ;11111111
0xFF ;11111111
0xFF ;11111111
0xFF ;11111111
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1D
1E
1F
0xFF ;11111111
0xFF ;11111111
0xFF ;11111111
20
and 1)
0x00 ;00000000 Flag Byte (if 0xFF do not load Function 0
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
0x12 ;00010010 SubSys Byte 3 ** Insert your SSVID MSB
0x34 ;00110100 SubSys Byte 2 ** Insert your SSVID LSB
0x56 ;01010110 SubSys Byte 1 ** Insert your SSID MSB
0x78 ;01111000 SubSys Byte 0 ** Insert your SSID LSB
0x60 ;01100000 SysCtrl Byte 0
0xB0 ;10110000 SysCtrl Byte 1
0x44 ;01000100 SysCtrl Byte 2
0x08 ;00001000 SysCtrl Byte 3
0x00 ;00000000 General Control
0x00 ;00000000 GP Event Enable
0x00 ;00000000 GP Output
0x22 ;00100010 MF Route Byte 0
0x22 ;00100010 MF Route Byte 1
0x22 ;00100010 MF Route Byte 2
0x04 ;00000100 MF Route Byte 3
0x02 ;00000010 Card Control
0x66 ;01100110 Device Control
0x61 ;01100001 Diagnostic
0x00 ;00000000 PMC Byte 1
0x82 ;10000010 ExCA ID and Rev
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2
1.3.1 P C Interface for TPS22X6 Power Switch
The interface between the PCI445X device and TPS22X6 power switch is
2
serializedtoreducethenumberofsignallines. TheP Cinterfacerequiresonly
three lines to control the switch. As a PCI445X default, the CLOCK signal is
selected from an external source. It is usually provided from RTC, 32.768 kHz.
The PCI445X device can also generate this clock from an internal ring
oscillator. The typical frequency of the internal ring oscillator is 16 kHz. If using
the internal clock source, then a pulldown resistor is required on the CLOCK
terminal. If arranging for D3 wake implementation, then connect the power
switch RESET terminal to GRST.
Figure 1–4. TPS22X6 Power Switch Interface
V
V
PPA
SLOT
A
CLOCK
DATA
CCA
V
V
CCB
CCA
TPS22X6
V
PPB
PCI445X
SLOT
B
LATCH
V
CCB
Pulldown on
CLOCK
1.3.2 Zoomed Video (ZV) Interface
The PCI445X device has an internally buffered and selectable ZV interface.
It supports three ZV sources, two from PC Cards and one from an external
source. An auto ZV detect function provides software independent ZV
switching. The autoZVdetectfunctionsensesthepixelclocks, arbitratesthree
inputs, and selects one of them according to priority bits.
Figure 1–5. Example of a ZV Interface
3rd ZV
Source
Buffer
ZVPCLK ZVSTAT
PCI445X
19
4
Graphic
Controller
SLOT
A
23
23
SLOT
B
Stereo
Audio
Codec
Sound
Controller
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If the third ZV source is not implemented, ZVPCLK and ZVSTAT are not
required. To support ZV audio, an audio codec device is required for L and R
sound decoding.
1.3.3 Interrupt Signaling Interface
- Serialized Interrupt Interface
The serialized interrupt (ISA and PCI) interface is a single-line interface,
IRQSER. A pullup resistor is required on this terminal. The signal is
synchronous to PCLK, so PCLK is a required signal. Please remember
that SUSPEND gates PCLK internally. Usually this signal is connected to
the south bridge (ex., PIIX4). The IRQSER signal is sharable with other
devices.
- Parallel PCI Interrupt
See Section 1.2.2, PCI Bus Interface.
1.3.4 Miscellaneous Signals
1.3.4.1 SUSPEND
The SUSPEND signal gates the PRST and G_RST signals from the PCI445X
device. SUSPEND also gates PCLK inside the PCI445X device in order to
minimize power consumption. Gating PCLK makes the IRQSER state
machine stop until SUSPEND is deasserted. Two requirements for
implementing suspend mode are that the PCI bus must not be parked on the
PCI445X device and IRQSER signaling is not proceeding when SUSPEND is
asserted.
1.3.4.2 RI_OUT and PME
RI_OUT can be programmed on the RI_OUT/PME or MFUNC7 terminal. PME
can be programmed only on the RI_OUT/PME terminal. To support both
RI_OUT and PME in a system, the RI_OUT/PME terminal must be
programmedasPME. Thesesignalsareusuallyconnectedtothesouthbridge
(ex., PIIX4) or an embedded controller (EC). Buffers of the RI_OUT/PME type
are open-drain; therefore, a pullup resistor is required on this terminal.
1.3.4.3 SPKROUT
SPKROUT is a dedicated terminal and it is usually mixed to PC sound, and
connected to a sound device.
1.3.4.4 Activity LEDs
Activity LEDs can be programmed on MFUNC terminals. These signals are
active-high and driven for 64 ms duration.
1.3.4.5 Distributed DMA (DDMA)
The PCI445X device supports both PC/PCI (centralized) DMA and a
distributed DMA slave engine for 16-bit PC Card DMA support.
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Figure 1–6. Distributed DMA Signal Connection
PCREQ
South
Bridge
PCI445X
PCGNT
(ex., PIIX4)
1.3.5 Requirement of Pullup/Pulldown Resistors
Note:
The PCI445X device has integrated pullup resistors and does not require
external pullups.
†
‡
Table 1–2.PC Card Interface Pullup Resistor List
Terminal Name
Terminal Name
Terminal Name
(16-bit Memory PC Card)
(16-bit I/O PC Card) (CardBus PC Card)
Pull Up to Voltage
CD1
CD2
VS1
CD1
CCD1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CD2
CCD2
CC
VS1
CVS1
CC
VS2
VS2
CVS2
CC
A19
A19
CBLOCK
CSTOP
CDEVSEL
CTRDY
CRST
or V
or V
or V
or V
or V
or V
or V
or V
or V
or V
or V
or V
or V
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCA
CCB
CCB
CCB
CCB
CCB
CCB
CCB
CCB
CCB
CCB
CCB
CCB
CCB
A20
A20
A21
A21
A22
A22
RESET
WAIT
RFU
BVD2
BVD1
A14
RESET
WAIT
INPACK
SPKR
STSCHG
A14
CSERR
CREQ
CAUDIO
CSTSCHG
CPERR
CINT
READY
A15
IREQ
A15
CIRDY
CCLKRUN
WP
IOIS16
†
‡
The PCI445X device has integrated pullup resistors and does not require external pullups.
CFRAME needs a pullup resistor, but it should be implemented on each PC Card.
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Table 1–3.PCI Bus Interface Pullup Resistor List
PCI Signal
FRAME
TRDY
Pull-Up Voltage
V
V
V
V
V
V
V
V
CCP
CCP
CCP
CCP
CCP
CCP
CCP
CCP
IRDY
DEVSEL
STOP
SERR
PERR
LOCK
INTA
INTB
INTC
V
CCP
CLKRUN
PRST
V
V
V
CCP
CCP
CCP
G_RST
PME
System dependent
The pullup/pulldown on MFUNC depends on how it is implemented. Some
signals may require pullups, others pulldowns, and for a GPI or GPO only the
system designer would know how that line should be pulled.
Table 1–4.Miscellaneous Terminals Pullup Resistor List
PCI Signal
Required Situation
Pullup/Pulldown
Voltage
MFUNC7–MFUNC4 N/C or used as output
V
V
or GND
or GND
CCP
CCP
MFUNC3–MFUNC0 N/C or used as output
(GPIO3–GPIO0)
MFUNC7(LOCK)
CLOCK
N/C or used as output
V
CCP
Internal OSC is selected
If MFUNC7 is used for IDSEL
GND
GND
LATCH
IRQSER
V
CCP
RI_OUT/PME
SUSPEND
System dependent
System dependent
Note: Removing clamping voltage makes all the clamped signals low.
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Table 1–5.Required Pullup/Pulldown Resistors
Signal
Resistor
Recommended
Condition
Value (Ω)
LPS
Pulldown (Default)
1.0 k
Required
Note: All pullup/pulldown resistor value recommendations are provided as guidelines only. The best value for an individual
design varies depending upon board characteristics, standard design rules and practices, etc.
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1.4 BIOS Considerations
1.4.1 Initialization
This section explains which registers require initialization, but does not
discuss detailed information about the registers themselves. Refer to the
corresponding specifications.
Reference white paper:
1.4.1.1 PCI Standard Registers Initialization
- Command register (PCI offset 04h: 16-bit)
Set to 0007h (enables bus master control, memory space control, and I/O
space control)
- Cache line size register (PCI offset 0Ch: 8-bit)
Set to 08h (It is dependent on host-to-PCI bridge specification). It enables
memory read line and memory read multiple command.
- Latency timer (PCI offset 0Dh: 8-bit)
This register should reflect each PC Card requirement, but Windows does
not do so. Therefore, system imlementers should determine the value. A
detailed description of this register is in the PCI Local Bus Interface
Specification. Typical setting for this register is 40h.
- CardBussocketregisters/ExCAbaseaddress(PCIoffset10h:32-bit)
It should be set to 0000 0000h (default).
- CardBus latency timer register (PCI offset 1Bh: 8-bit)
Setup of this register is not required because the CardBus bus is a
single-device bus, and the PCI445X device does not deassert CGNT until
a transaction is finished. (It does not mean that the PCI445X device
continues the transaction. The PCI445X device would terminate and
disconnect or abort the transaction as required).
- Memory and I/O windows (PCI offset 1Ch – 3Fh)
All memory and I/O windows should be closed (set to base > limit).
- Interrupt line register (PCI offset 3Ch: 8-bit)
This register is set to FFh (default).
- Subsystem vendor ID and subsystem ID registers (PCI offsets 40h
and 42h: 16-bit/16-bit)
These registers can be set through EEPROM or BIOS. These registers
are read-only as default. Before writing to the registers, the SUBSYSRW
bit (system control register, PCI offset 80h, bit 5) should be set to 1. After
setting up the registers, the SUBSYSRW bit should be set 0 to protect
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against unexpected overwriting. The values are system and vendor
dependent.
- PCCard 16-bit I/F legacy mode base address register (PCI offset 44h:
32-bit)
Set to 0000 03E1h (16-bit mode) and set to 0000 0001 (CardBus mode) in
response to a disable call.
- Power management capabilities register (PCI offset A2h: 16-bit)
If the system does not support V
in D3
state, then clear bit 15.
cold
AUX
- Power management control/status register (PCI offset A4h: 16-bit)
Clear bit 15 by writing a 1. This should be done after all the other
initialization for the PCI445X device is finished. Make sure that the
PCI445X device is in the D0 state, especially after reboot.
1.4.1.2 PCI TI Proprietary Registers Initialization
The registers listed below should be set up according to system requirements.
Refer to Section 1.1.12.
- System control register (PCI offset 80h: 32-bit)
- Multimedia control register (PCI offset 84h: 8-bit)
- GPIO3–GPIO0 control registers (PCI offset 88h – 8Bh: 8-bit)
- Multifunction routing register (PCI offset 8Ch: 32-bit)
- Card control register (PCI offset 91h: 8-bit)
- Device control register (PCI offset 92h: 8-bit)
- Diagnostic register (PCI offset 93h: 8-bit)
- DMA socket register 0 and 1 (PCI offset 94h, 98h: 32-bit)
- GPE control/status register (PCI offset A8h: 16-bit)
- ExCA identification and revision (ExCA offset 800h: 8-bit)
- Socket power management register (CardBus socket registers offset 20h:
32-bit)
1.4.2 System Sleeping State Consideration
Supporting sleeping states, such as SUSPEND, STANDBY, and
HIBERNATION are important for a notebook PC environment. The following
describes the sleeping state in APM systems:
1) SUSPEND
Reset signals G_RST and PRST are gated while SUSPEND is asserted.
PowerconsumptionofthePCI445XdeviceislowifSUSPENDisasserted.
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System Implementation
2) Register save/restore
Register content is not preserved in the sleeping state (it depends on the
system implementation). Therefore, BIOS should restore the register
content. Under Windows98, most of the register content is saved and
restored by the pci.vxd and cbss.vxd.
3) Troubleshooting tips for sleep/resume issues
Symptoms of sleep/resume issues are:
J
J
J
System hung up during resume
PC Card does not work after resume
PC Card is not recognized after resume
The probable reason for these problems is that the register content is not
preserved correctly. Checking the register content before taking the system to
the sleep mode and after resuming from the sleep mode may shed some light.
If some of the register settings are not the same after resuming from the sleep
mode, then the BIOS most likely did not restore those values.
1.4.3 Docking System Consideration
Subsystem IDs can be assigned as long as the SUBSYSRW bit (system
control register, PCI offset 80h, bit 5) is set. It is better to do this from EEPROM
as no driver will be running to set the SSID up after a hot-dock/warm-dock.
2
Therefore, the IDs should be loaded through the I C interface using an
EEPROM.
1-21
PCI445X Device
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Important Information
1.5 Important Information
This section clarifies important system implementation.
1.5.1 G_RST Clamping Rail
G_RST is clamped to V
, so removing V
causes assertion of G_RST.
CCP
CCP
Figure 1–7. G_RST and V
Relationship
CCP
V
V
= 0
CCP
CCP
V
CCP
removed
G_RST
G_RST
All other signals with clamping rails behave the same way.
1.5.2 PME/RI_OUT Bit Definition
If PME is selected, only PME is signaled on the PME/RI_OUT terminal. If
RI_OUT is selected, only RI_OUT is signaled. The PCI445X device can signal
PME and RI_OUT as completely separated signals. In this case RI_OUT
should be assigned on the MFUNC terminal.
1.5.3 Serialized IRQ Data Stream
PCI clock is needed for operation of the PCI445X serialized IRQ
state-machine. During SUSPEND assertion, the PCI445X device stops the
IRQSER stream. Before asserting SUSPEND, IRQSER must be stopped.
1.5.4 Socket Power Control
An internal or external CLOCK source is needed for the socket power control
2
through the P C interface. The internal ring oscillator is on while the core V
CC
is applied to the PCI445X device. External CLOCK source is dependent on the
system.
2
1.5.5 External CLOCK Frequency for P C Interface
2
If an external P C CLOCK is used, then it will affect:
- Advanced CD line noise filtering
- VS test speed
- TPS22X6 power control interface speed
Use of the internal ring oscillator is recommended. Recommended external
CLOCK source is the 32.768-kHz real-time clock (RTC).
1-22
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Appendix A
Global Reset Only Bits, PME Context Bits
Topic
Page
A.1 Global Reset Only Bits/PME Context Bits
A-2
A-1
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Global Reset Only Bits/PME Context Bits
A.1 Global Reset Only Bits/PME Context Bits
Table A–1.Global Reset Only Cleared Bits
Register Name
Space
PCI
Offset
40h
Bit
Subsystem IDs
31–0
31–1
PC card 16-bit legacy mode base address
System control
PCI
44h
PCI
80h
31–29, 27–24, 22–14, 6–3,
1–0
Multimedia control
General status
GPIO0 control
GPIO1 control
GPIO2 control
GPIO3 control
MFUNC routing
Retry status
84h
85h
88h
89h
8Ah
8Bh
8Ch
90h
91h
92h
93h
94h
98h
A8h
7–0
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
2–0
7, 6, 4, 3, 1, 0
7, 6, 3, 1, 0
7, 6, 4, 3, 1, 0
7, 6, 3, 1, 0
31–0
7–1
Card control
7, 6, 2, 1, 0
7–0
Device control
Diagnostic
7–0
Socket DMA register 0
Socket DMA register 1
GPE control/status
1–0
15–0
10, 9, 8, 2, 1, 0
Note: The following link registers are reset by global reset only.
- PCI subsystem identification register—PCI offset 2Ch
- MIN_GNT and MAX_LAT register—PCI offset 3Eh
- PCI OHCI control register—PCI offset 40h
- Power management control and status register—PCI offset 48h
- PCI miscellaneous and configuration register—PCI offset F0h
- Link enhancement control register—PCI offset F4h
However, there is no support in the OS for the PME-type wake events of the
1394 peripherals at this time.
A-2
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Global Reset Only Bits/PME Context Bits
Table A–2.PME Context Bits
Register Name
Space
PCI
Offset
3Eh
Bit
6
Bridge control
Power management capabilities
Power management control/status
ExCA power control
PCI
A2h
15
PCI
A4h
15, 8
ExCA
ExCA
ExCA
ExCA
802h, 842h 4, 3, 1, 0
803h/843h
ExCA interrupt and general control
ExCA card status change
ExCA card status change interrupt
CardBus socket event
6
804h/844h 3, 2, 1, 0
805h/845h 3, 2, 1, 0
CardBus 00h
CardBus 04h
CardBus 10h
3, 2, 1, 0
CardBus socket mask
3, 2, 1, 0
CardBus socket status
6, 5, 4, 2, 1, 0
- Global reset only bits are cleared (to default value) only when G_RST is
asserted.
- PMEcontextbitsarenotcleared(todefaultvalue)byPRSTifthePME_EN
bit is set to 1.
- Both G_RST and PRST can be gated by asserting the SUSPEND signal.
A-3
Global Reset Only Bits, PME Context Bits
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A-4
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Appendix B
PME and RI Behavior
This appendix clarifies PME and RI signal behavior. These signals are
important to support the wake-up event from a PC Card (CardBus and 16-bit
cards.)
Topic
Page
B.1 PME and RI Behavior
B-2
B-1
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B.1 PME and RI Behavior
Table B–1.CardBus CTSCHG and Wake-Up Signals Truth Table
RINGEN RIMUX RIENB PME_EN PME_STAT RI_OUT/PME
MFUNC7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
–––
–––
Latched CSTSCHG –––
–––
–––
–––
–––
–––
–––
Latched CSTSCHG –––
––– –––
Latched CSTSCHG –––
––– –––
Latched CSTSCHG –––
CSTSCHG
CSTSCHG
–––
CSTSCHG
CSTSCHG
–––
Latched CSTSCHG –––
–––
CSTSCHG
Latched CSTSCHG CSTSCHG
Table B–2.16-Bit Card RI/STSCHG and Wake-Up Signals Truth Table
RINGEN RIMUX
RIENB PME_EN PME_STAT RI_OUT/PME
MFUNC7
–––
–––
–––
RI
0
1
1
1
1
1
1
1
1
–––
0
–––
0
–––
0
–––
–––
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
–––
0
0
1
Latched RI
RI
0
1
0
0
1
1
RI
RI
1
0
0
–––
–––
–––
RI
1
0
1
Latched RI
–––
1
1
0
1
1
1
Latched RI
RI
B-2
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Appendix C
PCI445X Buffer Types
Topic
Page
C.1 PCI445X Buffer Types
C-2
C-1
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PCI445X Buffer Types
C.1 PCI445X Buffer Types
Table C–1. PCI445X Terminal Function Assignment and Buffer Types
Signal Name
Terminal Type
Signal Name
A_CAD28
A_CAD29
A_CAD30
A_CAD31
A_CAUDIO
A_CBLOCK
A_CC/BE0
A_CC/BE1
A_CC/BE2
A_CC/BE3
A_CCD1
Terminal Type
A_CAD0
B8
A7
C8
A6
B7
B6
C7
D7
C6
C5
B4
A3
C4
D5
B2
B3
A2
F1
G3
G2
H3
H1
J4
TS
TS
TS
TS
TS
TS
TS
TS
TSO
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
P
N2
N3
P1
D9
M1
D2
A4
C3
F2
J1
TS
TS
TS
TS
I
A_CAD1
A_CAD2
A_CAD3
A_CAD4
A_CAD5
P
A_CAD6
TS
TS
TS
TS
I
A_CAD7
A_CAD8
A_CAD9
A_CAD10
A_CAD11
A_CAD12
A_CAD13
A_CAD14
A_CAD15
A_CAD16
A_CAD17
A_CAD18
A_CAD19
A_CAD20
A_CAD21
A_CAD22
A_CAD23
A_CAD24
A_CAD25
A_CAD26
A_CAD27
A8
M4
E3
M3
D1
G4
C1
L2
A_CCD2
TS
TS
STS
STS
STS
STS
I
A_CCLK
A_CLKRUN
A_CDEVSEL
A_CFRAME
A_CGNT
A_CINT
A_CIRDY
A_CPAR
E1
C2
D3
J3
STS
TS
STS
I
TS
TS
TS
TS
TS
TS
TS
TS
A_CPERR
A_CREQ
A_CRST
H2
L3
O
J2
A_CSERR
A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
I
K2
K3
K1
N1
E4
M2
E2
L1
STS
I
STS
I/O
Note: The voltage sense terminals (VS1/CVS1, VS2/CVS2) are always driven low except under the following conditions:
1) High-impedance state during RESET
2) Toggle during socket interrogation
C-2
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PCI445X Buffer Types
Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)
Signal Name
A_CVS2
A_RSVD
A_RSVD
A_RSVD
AD0
Terminal Type
Signal Name
Terminal Type
G1
I/O
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
AD25
N20
M17
M18
M19
M20
L19
L18
J19
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
A5
AD26
B1
AD27
P2
AD28
V13
Y14
W14
Y15
W15
Y16
U14
V15
Y17
V16
W17
Y18
U16
V17
W18
Y19
T18
T19
T20
R18
P17
R19
R20
P18
N19
AD29
AD1
AD30
AD2
AD31
AD3
B_CAD0
B_CAD1
B_CAD2
B_CAD3
B_CAD4
B_CAD5
B_CAD6
B_CAD7
B_CAD8
B_CAD9
B_CAD10
B_CAD11
B_CAD12
B_CAD13
B_CAD14
B_CAD15
B_CAD16
B_CAD17
B_CAD18
B_CAD19
B_CAD20
B_CAD21
AD4
J17
AD5
J18
AD6
H19
H20
G20
H18
F20
G18
E20
G17
F18
E18
D20
C20
D19
E17
C16
B16
A16
D14
A15
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
Note: The voltage sense terminals (VS1/CVS1, VS2/CVS2) are always driven low except under the following conditions:
1) High-impedance state during RESET
2) Toggle during socket interrogation
C-3
PCI445X Buffer Types
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PCI445X Buffer Types
Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)
Signal Name
B_CAD22
B_CAD23
B_CAD24
B_CAD25
B_CAD26
B_CAD27
B_CAD28
B_CAD29
B_CAD30
B_CAD31
B_CAUDIO
B_CBLOCK
B_CC/BE0
B_CC/BE1
B_CC/BE2
B_CC/BE3
B_CCD1
Terminal Type
Signal Name
B_CSERR
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
B_RSVD
B_RSVD
B_RSVD
C/BE0
Terminal Type
C14
A14
A13
D12
C12
C10
D10
A9
TS
TS
TS
TS
TS
TS
TS
TS
TS
TS
I
B11
A20
A11
C17
B12
C15
C9
STS
STS
I
STS
I/O
I/O
TS
TS
TS
TS
TS
TS
TS
O
C19
G19
W16
V18
U20
N18
K18
U12
V12
U19
V20
Y12
A1
B9
D9
C11
C18
F19
D18
A17
C13
J20
B10
B17
B18
A18
A19
A12
D16
A10
B20
B19
B14
B15
C/BE1
STS
TS
TS
TS
I
C/BE2
C/BE3
CLKRUN
CLOCK
DATA
O
O
I
DEVSEL
FRAME
G_RST
GND
STS
STS
I
B_CCD2
I
B_CCLK
TS
STS
STS
O
B_CDEVSEL
B_CFRAME
B_CGNT
P
GND
D4
P
GND
D8
P
B_CINT
I
GND
D13
D17
H4
P
B_CIRDY
B_CLKRUN
B_CPAR
STS
STS
TS
STS
I
GND
P
GND
P
GND
H17
N4
P
B_CPERR
B_CREQ
GND
P
GND
N17
U4
P
B_CRST
O
GND
P
Note: The voltage sense terminals (VS1/CVS1, VS2/CVS2) are always driven low except under the following conditions:
1) High-impedance state during RESET
2) Toggle during socket interrogation
C-4
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PCI445X Buffer Types
Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)
Signal Name
Terminal Type
Signal Name
PHY_DATA6
PHY_DATA7
PHY_LREQ
PME/RI_OUT
PRST
Terminal Type
GND
U8
P
U9
TS
TS
O
GND
U13
U17
K20
P20
T17
W13
W12
Y6
P
V9
GND
P
Y5
GNT
I
Y13
K19
L20
W10
Y9
OD
I
IDSEL/MFUNC7
IRDY
I/O
STS
TS
TS
I
REQ
O
IRQSER
LATCH
SCL
TS
TS
OD
O
SDA
LINKON
LPS
SERR
Y20
V11
V19
U11
U18
B5
W5
W11
Y11
Y10
V10
W9
V5
O
SPKROUT
STOP
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PAR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
STS
I
STS
I
SUSPEND
TRDY
STS
P
VCCA
VCCA
F3
P
VCCA
L4
P
Y4
VCCB
B13
E19
P19
V14
D6
P
W19
K17
W20
V6
VCCB
P
PCLK
VCCP
P
PERR
STS
I
VCCP
P
PHY_CLK
PHY_CTL0
PHY_CTL1
PHY_DATA0
PHY_DATA1
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
P
U7
TS
TS
TS
TS
TS
TS
TS
TS
D11
D15
F4
P
W6
V7
P
P
W7
Y7
F17
K4
P
P
V8
L17
R4
P
W8
Y8
P
R17
P
C-5
PCI445X Buffer Types
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PCI445X Buffer Types
Table C–1. PCI445X Terminal Function Assignment and Buffer Types (Continued)
Signal Name
Terminal Type
Signal Name
ZV_UV4
ZV_UV5
ZV_UV6
ZV_UV7
ZV_VSYNC
ZV_Y0
Terminal Type
VCC3.3
U6
U10
U15
P3
P
W1
Y1
W2
Y2
R2
T1
P4
R3
T2
U1
T3
U2
V1
TSO
TSO
TSO
TSO
TS
VCC3.3
P
VCC3.3
P
ZV_HREF
ZV_LRCLK
ZV_MCLK
ZV_PCLK
ZV_SCLK
ZV_SDATA
ZV_UV0
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
V4
W4
Y3
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
ZV_Y1
W3
U5
T4
ZV_Y2
ZV_Y3
ZV_Y4
ZV_UV1
V2
ZV_Y5
ZV_UV2
U3
V3
ZV_Y6
ZV_UV3
ZV_Y7
C-6
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PCI445X Buffer Types
Table C–2. Buffer Type Abbreviations
Buffer Type
Description
I/O
I
Standard input/output
Standard input only
Standard output only
Open drain
O
OD
P
Power, GND, or clamp rail
STS
Sustained 3-state bidirectional. An active-low signal must be driven high for one cycle
before deasserting.
TS
3-state bidirectional
3-state output only
TSO
C-7
PCI445X Buffer Types
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C-8
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