Si5351A/B/C
2
I C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
Glitchless frequency changes
Separate voltage supply pins:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output-output delay
Available in 3 packages types:
10-MSOP: 3 outputs
10-MSOP
2
I C user definable configuration
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: 100 ps pp
Configurable spread spectrum selectable
at each output
24-QSOP
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
Supports static phase offset
Programmable rise/fall time control
Supports HCSL compatible swing
Applications
20-QFN
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
Ordering Information:
2
The Si5351 is an I C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. The Si5351B eliminates the need for higher cost, custom pullable
crystals while providing reliable operation over a wide tuning range. The Si5351C offers
the same flexibility but synchronizes to an external reference clock (CLKIN).
See page 66
Functional Block Diagram
XA
XA
XB
Multi
Synth
0
Multi
Synth
0
Multi
PLLA
PLLB
Synth
XA
XB
0
OSC
OSC
PLL
PLLA
Multi
Synth
1
Multi
Synth
1
Multi
Synth
1
OSC
XB
Multi
Synth
2
Multi
Synth
VCXO
VC
PLLB
2
CLKIN
Multi
Synth
3
Multi
Synth
3
Multi
Synth
N
I2C
Multi
Synth
4
Multi
Synth
4
SSEN
OEB
Si5351A
Multi
Synth
5
Multi
Synth
5
N = 2 or 7
Multi
Synth
6
Multi
Synth
6
I2C
I2C
Multi
Synth
7
Multi
Synth
7
SSEN
OEB
INTR
OEB
Si5351C
Si5351B
Preliminary Rev. 0.95 8/11
Copyright © 2011 by Silicon Laboratories
Si5351A/B/C
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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Si5351A/B/C
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .19
5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.6. Replacing a Crystal with a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . .62
10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . .63
11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . .64
12. Si5351A Pin Descriptions (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
14. Package Outline (24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
15. Package Outline (20-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
16. Package Outline (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Preliminary Rev. 0.95
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Si5351A/B/C
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
3.0
Typ
25
Max
85
Unit
°C
V
Ambient Temperature
T
A
3.3
2.5
1.8
2.5
3.3
3.60
2.75
1.89
2.75
3.60
Core Supply Voltage
V
DD
2.25
1.71
2.25
3.0
V
V
Output Buffer Voltage
V
V
DDOx
V
Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that both voltage rails are powered at the same time.
Table 2. DC Characteristics
(V = 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C)
DD
A
Parameter
Symbol
Test Condition
Enabled 3 outputs
Min
—
Typ
22
Max
35
Unit
mA
mA
µA
Core Supply Current
I
Enabled 8 outputs
—
27
45
DD
Power Down (PDN = V
)
—
—
20
DD
Output Buffer Supply Current
(Per Output)*
I
C = 5 pF
—
2.2
5
mA
DDOx
L
CLKIN, SDA, SCL
Vin < 3.6 V
I
—
—
—
—
10
30
µA
µA
CLKIN
Input Current
I
VC
VC
8 mA output drive current.
Output Impedance
Z
—
85
—
O
*Note: Output clocks less than or equal to 100 MHz.
4
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Si5351A/B/C
Table 3. AC Characteristics
(V = 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C)
DD
A
Parameter
Symbol
Test Condition
From V = V to valid
Min
Typ
Max
Unit
DD
DDmin
Power-up Time
T
output clock, C = 5 pF,
—
1
10
ms
RDY
L
f
> 1 MHz
CLKn
From OEB pulled low to valid
clock output, C = 5 pF,
Output Enable Time
Output Phase Offset
T
—
—
10
µs
OE
L
f
> 1 MHz
CLKn
P
—
333
—
—
ps/step
STEP
Down spread
Center spread
–0.1
±0.1
–2.5
±1.5
%
%
Spread Spectrum Frequency
Deviation
SS
DEV
—
Spread Spectrum Modulation
Rate
SS
30
31.5
33
kHz
MOD
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range
VCXO Gain (configurable)
Vc
0
V
/2
V
V
ppm/V
%
DD
DD
Kv
Vc = 10–90% of V , V = 3.3 V 18
—
150
+5
DD
DD
VCXO Control Voltage Linearity
KVL
Vc = 10–90% of V
–5
±30
—
—
DD
VCXO Pull Range
(configurable)
PR
V
= 3.3 V*
0
±240
—
ppm
kHz
DD
VCXO Modulation Bandwidth
10
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
Table 4. Input Clock Characteristics
(V = 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C)
DD
A
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
V
CLKIN Input Low Voltage
CLKIN Input High Voltage
CLKIN Frequency Range
V
–0.1
0.7 x V
10
—
—
—
0.3 x V
3.60
IL
DD
V
V
IH
DD
f
100
MHz
CLKIN
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Si5351A/B/C
Table 5. Output Clock Characteristics
(V = 2.5 V ±10%, or 3.3 V ±10%, T = –40 to 85 °C)
DD
A
Parameter
Symbol
Test Condition
Min
0.008
—
Typ
—
5
Max
160
15
Units
MHz
pF
Frequency Range
Load Capacitance
F
CLK
C
L
Measured at V /2,
DD
Duty Cycle
DC
45
50
55
%
f
= 50 MHz
CLK
t
0.5
0.5
1
1.5
1.5
—
ns
ns
r
20%–80%, C = 5 pF,
Drive Strength = 8 mA
L
Rise/Fall Time
t
1
f
Output High Voltage
Output Low Voltage
Period Jitter
V
V
– 0.6
DD
—
—
35
60
30
V
OH
C = 5 pF
L
V
—
0.6
100
110
90
V
OL
J
—
—
—
ps pk-pk
ps pk-pk
ps pk
PER
J
PER_VCXO
Measured over 10k cycles
Measured over 10k cycles
12 kHz–20 MHz
Period Jitter VCXO
Cycle-to-Cycle Jitter
J
CC
Cycle-to-Cycle Jitter
VCXO
J
—
50
95
ps pk
CC_VCXO
RMS Phase Jitter
J
—
—
3.5
8.5
11
ps rms
ps rms
RMS
RMS Phase Jitter VCXO J
18.5
RMS_VCXO
Table 6. Crystal Requirements1,2
Parameter
Symbol
Min
25
6
Typ
—
Max
Unit
MHz
pF
Crystal Frequency
Load Capacitance
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
f
27
12
XTAL
C
—
L
r
—
—
—
150
100
ESR
d
—
µW
L
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors.
2. Refer to “AN551: Crystal Selection Guide” for more details.
6
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Si5351A/B/C
Parameter
Symbol
Test Condition
Standard Mode
Fast Mode
Unit
100 kbps
400 kbps
Min
Max
Min
Max
LOW Level
Input Voltage
0.3 x V
DDI2
V
–0.5
–0.5
0.3 x V
V
V
ILI2C
DDI2C
C
HIGH Level
Input Voltage
0.7 x V
DDI2
V
3.63
0.7 x V
3.63
IHI2C
DDI2C
C
Hysteresis of
Schmitt Trigger
Inputs
V
—
—
0.1
0
—
V
V
HYS
LOW Level
V
= 2.5/3.3 V
0
0.4
0.4
DDI2C
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current
V
OLI2C
V
= 1.8 V
—
—
0
0.2 x V
V
DDI2C
DDI2C
Input Current
I
–10
—
10
4
–10
—
10
4
µA
pF
II2C
Capacitance for
Each I/O Pin
C
V
= –0.1 to V
IN DDI2C
II2C
2
I C Bus
Timeout
T
Timeout Enabled
25
35
25
35
ms
TO
Notes:
2
1. Refer to NXP’s UM10204 I C-bus specification and user manual, revision 03, for further details, go to:
2
2. Only I C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
Table 8. Thermal Characteristics
Parameter
Symbol
Test Condition
Package
10-MSOP
24-QSOP
20-QFN
Value
131
80
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance
Junction to Ambient
Still Air
JA
51
10-MSOP
24-QSOP
20-QFN
43
Thermal Resistance
Junction to Case
Still Air
31
JC
16
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Si5351A/B/C
Table 9. Absolute Maximum Ratings1
Parameter
Symbol
Test Condition
Value
–0.5 to 3.8
Unit
V
DC Supply Voltage
V
DD_max
V
CLKIN, SCL, SDA
VC
–0.5 to 3.8
V
IN_CLKIN
Input Voltage
V
–0.5 to (VDD+0.3)
–0.5 to 1.3 V
–55 to 150
V
IN_VC
V
Pins XA, XB
V
IN_XA/B
Junction Temperature
T
°C
J
Soldering Temperature (Pb-free
profile)
T
260
°C
PEAK
Soldering Temperature Time at
TPEAK (Pb-free profile)
T
20–40
Sec
P
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
8
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Si5351A/B/C
2. Detailed Block Diagrams
VDDO
VDD
Si5351A 3-Output
PLL
A
MultiSynth
R0
0
CLK0
CLK1
XA
OSC
PLL
B
XB
MultiSynth
R1
1
SDA
I2C
MultiSynth
R2
2
CLK2
Interface
SCL
10-MSOP
GND
VDD
Si5351A 8-Output
VDDOA
CLK0
MultiSynth
R0
R1
R2
R3
R4
R5
R6
R7
PLL
A
0
XA
MultiSynth
1
CLK1
OSC
VDDOB
CLK2
PLL
B
XB
MultiSynth
2
MultiSynth
3
CLK3
A0
VDDOC
CLK4
MultiSynth
4
I2C
Interface
SDA
CLK5
MultiSynth
5
SCL
VDDOD
CLK6
MultiSynth
6
OEB
Control
Logic
CLK7
MultiSynth
7
SSEN
20-QFN, 24-QSOP
GND
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices
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Si5351A/B/C
VDD
Si5351B
VDDOA
CLK0
MultiSynth
0
R0
XA
XB
PLL
OSC
MultiSynth
1
CLK1
R1
R2
R3
R4
R5
R6
R7
VDDOB
CLK2
MultiSynth
2
VCXO
VC
MultiSynth
3
CLK3
VDDOC
CLK4
MultiSynth
4
SDA
SCL
I2C
Interface
MultiSynth
5
CLK5
VDDOD
CLK6
MultiSynth
6
OEB
Control
Logic
SSEN
CLK7
MultiSynth
7
20-QFN, 24-QSOP
GND
VDD
Si5351C
VDDOA
MultiSynth
R0
R1
R2
R3
R4
R5
R6
R7
XA
XB
CLK0
CLK1
0
PLL
A
OSC
MultiSynth
1
VDDOB
CLK2
MultiSynth
2
PLL
B
CLKIN
SDA
MultiSynth
3
CLK3
VDDOC
CLK4
MultiSynth
4
I2C
Interface
MultiSynth
5
CLK5
SCL
INTR
VDDOD
CLK6
MultiSynth
6
Control
Logic
OEB
CLK7
MultiSynth
7
20-QFN, 24-QSOP
GND
Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices
10
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Si5351A/B/C
3. Functional Description
2
The Si5351 is a versatile I C programmable clock generator that is ideally suited for replacing crystals, crystal
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a clock input (CLKIN), or a control voltage input (VC)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 8 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Input
Stage
Synthesis
Stage 1
Synthesis
Stage 2
Output
Stage
VDDOA
Multi
Synth
0
R0
R1
R2
R3
R4
R5
R6
R7
CLK0
CLK1
Multi
Synth
1
Div
CLKIN
PLL A
VDDOB
Multi
Synth
2
(SSC)
CLK2
CLK3
XA
XB
PLL B
(VCXO)
Multi
Synth
3
OSC
XTAL
VDDOC
Multi
Synth
4
CLK4
CLK5
Multi
Synth
5
VCXO
VC
VDDOD
Multi
Synth
6
CLK6
CLK7
Multi
Synth
7
Figure 3. Si5351 Block Diagram
3.1. Input Stage
3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors (C ) are provided to eliminate the need for external components when connecting a crystal
L
to the Si5351. Options for internal load capacitors are 6, 8, or 10 pF. Crystals with alternate load capacitance
requirements are supported using additional external load capacitors as shown in Figure 4. Refer to application
note AN551 for crystal recommendations.
CL
XA
XB
CL
Selectable internal
load capacitors
6 pF, 8 pF, 10 pF
CL
CL
Optional
Additional external
load capacitors
(< 2 pF)
Figure 4. External XTAL with Optional Load Capacitors
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Si5351A/B/C
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 9 on page 15.
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-
resolution MultiSynth fractional dividers to generate frequencies in the range of 1 MHz to 100 MHz. It is also
possible to generate two unique frequencies up to 160 MHz on two or more of the outputs.
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
Since the VCXO already generates a high-frequency intermediate clock, it is fed directly into the second stage of
synthesis. The MultiSynth high-resolution dividers synthesize the VCXO center frequency to any frequency in the
range of ~391 kHz to 160 MHz. The center frequency is then controlled (or pulled) by the VC input. An interesting
feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This creates a
VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 8 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
Fixed Frequency
Crystal (non-pullable)
XA
XB
Multi
The clock frequency
generated from CLK0 is
controlled by the VC input
OSC
R0
Synth
0
CLK0
CLK1
CLK2
VC
Multi
Synth
1
Control
Voltage
R1
R2
VCXO
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
Multi
Synth
2
frequencies
Figure 5. Using the Si5351 as a Multi-Output VCXO
3.3. Output Stage
An additional level of division (R) is available at the output stage for generating clocks as low as 8 kHz. All output
drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage
signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
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3.4. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB
Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB or to the
VCXO.
The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
between system performance and EMI compliance.
Reduced
Amplitude
and EMI
Reduced
Amplitude
and EMI
Center
Frequency
Amplitude
fc
fc
fc
No Spread
Spectrum
Center Spread
Down Spread
Figure 6. Available Spread Spectrum Profiles
3.5. Control Pins (OEB, SSEN)
The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
3.5.1. Output Enable (OEB)
The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
held low, and disabled when pulled high. When disabled, the output state is configurable as disabled high, disabled
low, or disabled in high-impedance.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
going into a disabled state.
3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only
This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
evaluating the effect of using spread spectrum clocks during EMI compliance testing.
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4. I2C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
2
2
I C interface. The following is a list of the common features that are controllable through the I C interface. A
summary of register functions is shown in Section 7.
Read Status Indicators
Loss of signal (LOS) for the CLKIN input
Loss of lock (LOL) for PLLA and PLLB
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
n
Output divider values (2 , n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
2
The I C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
2
The I C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
2
I C specification.
VDD
>1k
>1k
Si5351
SCL
SDA
I2C Bus
4.7 k
INTR
A0
I2C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Figure 7. I2C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
2
require more than one Si5351 on a single I C bus.
6
5
4
3
2
1
0
Slave Address
1
1
0
0
0
0
0/1
A0
Figure 8. Si5351 I2C Slave Address
2
Data is transferred MSB first in 8-bit words as specified by the I C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
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Write Operation – Single Byte
Slv Addr [6:0] Reg Addr [7:0]
S
0
A
A
Data [7:0]
A
A
P
Write Operation - Burst (Auto Address Increment)
Slv Addr [6:0] Reg Addr [7:0] Data [7:0]
S
0
A
A
Data [7:0]
A
P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P– STOPcondition
Figure 9. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Read Operation – Single Byte
S
Slv Addr [6:0]
0
A
Reg Addr [7:0]
A
P
P
S
Slv Addr [6:0]
1
A
Data [7:0]
N
Read Operation - Burst (Auto Address Increment)
S
S
Slv Addr [6:0]
Slv Addr [6:0]
0
1
A
A
Reg Addr [7:0]
Data [7:0]
A
P
A
Data [7:0]
N
P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P– STOPcondition
Figure 10. I2C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 7. The timing specifications and
2
2
timing diagram for the I C bus is compatible with the I C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
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5. Configuring the Si5351
2
The Si5351 is a highly flexible clock generator which is entirely configurable through its I C interface. The device’s
default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time
programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for
applications that need a clock present at power-up (e.g., for providing a clock to a processor).
Power-Up
NVM
(OTP)
RAM
Default
Config
I2C
Figure 11. Si5351 Memory Configuration
During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the
device configuration that will be used during normal operation. Any changes to the device configuration after
2
power-up are made by reading and writing to registers in the RAM space through the I C interface. A detailed
register map is shown in Section "8. Register Descriptions" on page 25.
5.1. Writing a Custom Configuration to RAM
To simplify device configuration, Silicon Labs has released the ClockBuilder Desktop. The software serves two
purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the
EVB when connected to a host PC.
The optimal configuration can be saved from the software in text files that can be used in any system, which
2
configures the device over I C. ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and
runs on Windows XP, Windows Vista, and Windows 7.
2
Once the configuration file has been saved, the device can be programmed via I C by following the steps shown in
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Disable Outputs
Set CLKx_DIS high; Reg. 3 = 0xFF
Powerdown all output drivers
Reg. 16, 17, 18, 19, 20, 21, 22, 23 =
0x80
Set interrupt masks
(see register 2 description)
Write new configuration to device using
the contents of the register map
generated by ClockBuilder Desktop. This
step also powers up the output drivers.
(Registers 15-92 and 149-170)
Register
Map
Use ClockBuilder
Desktop v3.1 or later
Apply PLLA and PLLB soft reset
Reg. 177 = 0xAC
Enable desired outputs
(see Register 3)
Figure 12. I2C Programming Procedure
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5.2. Si5351 Application Examples
The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show
how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
5.3. Replacing Crystals and Crystal Oscillators
Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies
for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
48 MHz
Ethernet
PHY
OSC
PLL
27 MHz
Multi
Synth
1
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Multi
Synth
6
CLK6
CLK7
22.5792 MHz
33.3333 MHz
Multi
Synth
7
CPU
Si5351A
Note: Si5351A replaces crystals, XOs, and PLLs.
Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs
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5.4. Replacing Crystals, Crystal Oscillators, and VCXOs
The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video
applications. An example is shown in Figure 14.
Free-running
Clocks
Ethernet
PHY
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
OSC
PLL
27 MHz
Multi
Synth
1
48 MHz
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
VC
VCXO
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Synchronous
Clocks
Si5351B
Note: FBW = 10 kHz
Figure 14. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs
5.5. Replacing Crystals, Crystal Oscillators, and PLLs
The Si5350C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
Free-running
Clocks
Ethernet
PHY
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
48 MHz
OSC
PLL
25 MHz
Multi
Synth
1
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
CLKIN
PLL
54 MHz
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Si5351C
Synchronous
Clocks
Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
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5.6. Replacing a Crystal with a Clock
The Si5351 can be driven with a clock signal through the XA input pin.
VIN = 1 VPP
25/27 MHz
Multi
Synth
0
PLLA
PLLB
XA
Multi
Synth
1
0.1 µF
OSC
XB
Multi
Synth
N
Note: Float the XB input while driving
the XA input with a clock
Figure 16. Si5351 Driven by a Clock Signal
5.7. HCSL Compatible Outputs
The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair. See register setting CLKx_INV.
ZO = 70
R1
Multi
Synth
0
PLLA
PLLB
0
511
240
R2
OSC
HCSL
CLKIN
ZO = 70
R1
Multi
Synth
1
0
511
240
R2
Multi
Synth
N
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 17. Si5350C Output is HCSL Compatible
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6. Design Considerations
The Si5351 is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for
additional layout recommendations.
6.1. Power Supply Decoupling/Filtering
The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 µF
decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and VDDOx
pins as possible without using vias.
6.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. If a minimum output-to-output skew is important, then all VDDOx must be applied
before VDD. Unused VDDOx pins should be tied to VDD.
6.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.4. External Crystal Load Capacitors
The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is
insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load
capacitors are used, they should be placed as close to the XA/XB pads as possible. See AN554 for more details.
6.5. Unused Pins
Unused voltage control pin should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "5.6. Replacing a Crystal with a Clock" on page 20 when using
XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left floating.
Unused VDDOx pins should be tied to VDD.
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6.6. Trace Characteristics
The Si5351A/B/C features various output current drives ranging from 2 to 8 mA (default). It is recommended to
configure the trace characteristics as shown in Figure 18 when an output drive setting of 8 mA is used.
ZO = 85 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Length = No Restrictions
Figure 18. Recommended Trace Characteristics with 8 mA Drive Strength Setting
Note: Jitter is only specified at 6 and 8 mA drive strength.
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7. Register Map Summary
The following is a summary of the register map used to read status, control, and configure the Si5351.
Register
7
6
5
4
3
2
1
0
0
1
SYS_INIT
LOL_B
LOL_A
LOS
REVID[1:0]
SYSCAL_
STKY
LOS_B_
STKY
LOL_A_
STKY
LOS_
STKY
2
SYSCAL_
MASK
LOS_B_
MASK
LOL_A _
MASK
LOS_
MASK
3
4–8
9
CLK7_EN
CLK6_EN
CLK5_EN
CLK4_EN
CLK3_EN
CLK2_EN
OEB_CLK2
PLLA_SRC
CLK1_EN
OEB_CLK1
0
CLK0_EN
OEB_CLK0
0
Reserved
OEB_CLK3
Reserved
PLLB_SRC
OEB_CLK7
OEB_CLK6
OEB_CLK5
OEB_CLK4
10–14
15
0
0
0
0
16
CLK0_PDN
CLK1_PDN
CLK2_PDN
CLK3_PDN
CLK4_PDN
CLK5_PDN
CLK6_PDN
CLK7_PDN
MS0_INT
MS1_INT
MS2_INT
MS3_INT
MS4_INT
MS5_INT
FBA_INT
FBB_INT
MS0_SRC
MS1_SRC
MS2_SRC
MS3_SRC
MS4_SRC
MS5_SRC
MS6_SRC
MS6_SRC
CLK0_INV
CLK1_INV
CLK2_INV
CLK3_INV
CLK4_INV
CLK5_INV
CLK6_INV
CLK7_INV
CLK0_SRC[1:0]
CLK0_IDRV[1:0]
17
CLK1_SRC[1:0]
CLK2_SRC[1:0]
CLK3_SRC[1:0]
CLK4_SRC[1:0]
CLK5_SRC[1:0]
CLK6_SRC[1:0]
CLK7_SRC[1:0]
CLK1_DIS_STATE
CLK5_DIS_STATE
CLK1_IDRV[1:0]
CLK2_IDRV[1:0]
CLK3_IDRV[1:0]
CLK4_IDRV[1:0]
CLK5_IDRV[1:0]
CLK6_IDRV[1:0]
CLK7_IDRV[1:0]
CLK0_DIS_STATE
CLK4_DIS_STATE
18
19
20
21
22
23
24
CLK3_DIS_STATE
CLK7_DIS_STATE
CLK2_DIS_STATE
CLK6_DIS_STATE
25
26–41
PLL, MultiSynth, and output clock delay offset Configuration Registers.
Use ClockBuilder Desktop Software to Determine These Register Values.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
MS0_P3[15:8]
MS0_P3[7:0]
R0_DIV[2:0]
MS0_P1[17:16]
MS1_P1[17:16]
MS2_P1[17:16]
MS0_P1[15:8]
MS0_P1[7:0]
MS0_P3[19:16]
MS0_P2[19:16]
MS1_P2[19:16]
MS2_P2[19:16]
MS0_P2[15:8]
MS0_P2[7:0]
MS1_P3[15:8]
MS1_P3[7:0]
R1_DIV[2:0]
MS1_P1[15:8]
MS1_P1[7:0]
MS1_P3[19:16]
MS1_P2[15:8]
MS1_P2[7:0]
MS2_P3[15:8]
MS2_P3[7:0]
R2_DIV[2:0]
MS2_P1[15:8]
MS2_P1[7:0]
MS2_P3[19:16]
MS2_P2[15:8]
MS2_P2[7:0]
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Si5351A/B/C
Register
66
7
6
5
4
3
MS3_P3[15:8]
MS3_P3[7:0]
2
1
0
67
68
R3_DIV[2:0]
MS3_P1[17:16]
MS4_P1[17:16]
MS5_P1[17:16]
69
MS3_P1[15:8]
MS3_P1[7:0]
70
71
MS3_P3[19:16]
MS3_P2[19:16]
72
MS3_P2[15:8]
MS3_P2[7:0]
MS4_P3[15:8]
MS4_P3[7:0]
73
74
75
76
R4_DIV[2:0]
77
MS4_P1[15:8]
MS4_P1[7:0]
78
79
MS4_P3[19:16]
MS4_P2[19:16]
80
MS4_P2[15:8]
MS4_P2[7:0]
MS5_P3[15:8]
MS5_P3[7:0]
81
82
83
84
R5_DIV[2:0]
85
MS5_P1[15:8]
MS5_P1[7:0]
86
87
MS5_P3[19:16]
MS5_P2[19:16]
88
MS5_P2[15:8]
MS5_P2[7:0]
MS6_P1[7:0]
MS7_P1[7:0]
89
90
91
92
R7_DIV[2:0]
R6_DIV[2:0]
93–164
PLL, MultiSynth, and output clock delay offset Configuration Registers.
Use ClockBuilder Desktop Software to Determine These Register Values.
165
166
CLK0_PHOFF[7:0]
CLK1_PHOFF[7:0]
CLK2_PHOFF[7:0]
CLK3_PHOFF[7:0]
CLK4_PHOFF[7:0]
CLK5_PHOFF[7:0]
Reserved
167
168
189
170
173–176
177
PLLB_RST
PLLA_RST
178–182
183
Reserved
XTAL_CL
184–255
Reserved
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8. Register Descriptions
Register 0. Device Status
Bit
D7
SYS_INIT
R
D6
LOL_B
R
D5
LOL_A
R
D4
LOS
R
D3
D2
D1
D0
Name
Type
REVID[1:0]
R
R
R
Reset value = 0000 0000
Bit
Name
SYS_INIT System Initialization Status.
Function
7
During power up the device copies the content of the NVM into RAM and performs a system
initialization. The device is not operational until initialization is complete. It is not recom-
2
mended to read or write registers in RAM through the I C interface until initialization is com-
plete. An interrupt will be triggered (INTR pin = 0, Si5351C only) during the system
initialization period.
0: System initialization is complete. Device is ready.
1: Device is in system initialization mode.
6
LOL_B
LOL_A
LOS
PLLB Loss Of Lock Status.
Si5351A/C only. PLLB will operate in a locked state when it has a valid reference from CLKIN
or XTAL. A loss of lock will occur if the frequency of the reference clock forces the PLL to
triggered (INTR pin = 0, Si5351C) during a LOL condition.
0: PLL B is locked.
1: PLL B is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
5
PLL A Loss Of Lock Status.
PLL A will operate in a locked state when it has a valid reference from CLKIN or XTAL. A loss
of lock will occur if the frequency of the reference clock forces the PLL to operate outside of
(INTR pin = 0, Si5351C only) during a LOL condition.
0: PLL A is operating normally.
1: PLL A is unlocked. When the device is in this state it will trigger an interrupt causing the
INTR pin to go low (Si5351C only).
4
CLKIN Loss Of Signal (Si5351C Only).
A loss of signal status indicates if the reference clock fails to meet the minimum requirements
Si5351C only) during a LOS condition.
0: Valid clock signal at the CLKIN pin.
1: Loss of signal detected at the CLKIN pin.
3:2
Reserved Leave as default.
1:0 REVID[1:0] Revision ID. Device revision number. Set at the factory.
Preliminary Rev. 0.95
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Si5351A/B/C
Register 1. Interrupt Status Sticky
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SYS_INIT_STKY LOL_B_STKY LOL_A_STKY LOS_STKY
R/W R/W R/W R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
SYS_INIT_STKY System Calibration Status Sticky Bit.
The SYS_INIT_STKY bit is triggered when the SYS_INIT bit (register 0, bit 7) is trig-
gered high. It remains high until cleared. Writing a 0 to this register bit will cause it to
clear.
0: No SYS_INIT interrupt has occurred since it was last cleared.
1: A SYS_INIT interrupt has occurred since it was last cleared.
6
5
LOL_B_STKY
LOL_A_STKY
LOS_STKY
Reserved
PLLB Loss Of Lock Status Sticky Bit.
The LOL_B_STKY bit is triggered when the LOL_B bit (register 0, bit 6) is triggered
high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No PLL B interrupt has occurred since it was last cleared.
1: A PLL B interrupt has occurred since it was last cleared.
PLLA Loss Of Lock Status Sticky Bit.
The LOL_A_STKY bit is triggered when the LOL_A bit (register 0, bit 5) is triggered
high. It remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No PLLA interrupt has occurred since it was last cleared.
1: A PLLA interrupt has occurred since it was last cleared.
4
CLKIN Loss Of Signal Sticky Bit (Si5351C Only).
The LOS_STKY bit is triggered when the LOS bit (register 0, bit 4) is triggered high. It
remains high until cleared. Writing a 0 to this register bit will cause it to clear.
0: No LOS interrupt has occurred since it was last cleared.
1: A LOS interrupt has occurred since it was last cleared.
3:0
Leave as default.
26
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Si5351A/B/C
Register 2. Interrupt Status Mask
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SYS_INIT_MASK LOL_B_MASK LOL_A_MASK LOS_MASK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
SYS_INIT_MASK System Initialization Status Mask.
Function
7
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when
SYS_INIT is asserted.
0: Do not mask the SYS_INIT interrupt.
1: Mask the SYS_INIT interrupt.
6
5
LOL_B_MASK PLLB Loss Of Lock Status Mask.
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOL_B
is asserted.
0: Do not mask the LOL_B interrupt.
1: Mask the LOL_B interrupt.
LOL_A_MASK PLL A Loss Of Lock Status Mask.
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOL_A
is asserted.
0: Do not mask the LOL_A interrupt.
1: Mask the LOL_A interrupt.
4
LOS_MASK
Reserved
CLKIN Loss Of Signal Mask (Si5351C Only).
Use this mask bit to prevent the INTR pin (Si5351C only) from going low when LOS is
asserted.
0: Do not mask the LOS interrupt.
1: Mask the LOS interrupt.
3:0
Leave as default.
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Si5351A/B/C
Register 3. Output Enable Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK7_OEB CLK6_OEB CLK5_OEB CLK4_OEB CLK3_OEB CLK2_OEB CLK1_OEB CLK0_OEB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit Name
Function
7:0 CLKx_OEB Output Disable for CLKx.
Where x = 0, 1, 2, 3, 4, 5, 6, 7
0: Enable CLKx output.
1: Disable CLKx output.
Register 9. OEB Pin Enable Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
OEB_CLK7 OEB_CLK6 OEB_CLK5 OEB_CLK4 OEB_CLK3 OEB_CLK2 OEB_CLK1 OEB_CLK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit Name
Function
7:0 OEB_CLKx OEB pin enable control of CLKx.
Where x = 0, 1, 2, 3, 4, 5, 6, 7
0: OEB pin controls enable/disable state of CLKx output.
1: OEB pin does not control enable/disable state of CLKx output.
28
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Si5351A/B/C
Register 15. PLL Input Source
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PLLB_SRC PLLA_SRC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
7:4
3
Name
Function
Reserved
Leave as default.
PLLB_SRC Input Source Select for PLLB.
0: Select the XTAL input as the reference clock for PLLB (Si5351A/C only).
1: Select the CLKIN input as the reference clock for PLLB (Si5351C only).
2
PLLA_SRC Input Source Select for PLLA.
0: Select the XTAL input as the reference clock for PLLA.
1: Select the CLKIN input as the reference clock for PLLA (Si5351C only).
1:0
Reserved
Leave as default.
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Si5351A/B/C
Register 16. CLK0 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK0_PDN MS0_INT MS0_SRC CLK0_INV
R/W R/W R/W R/W
CLK0_SRC[1:0]
R/W
CLK0_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK0_PDN
Clock 0 Power Down.
This bit allows powering down the CLK0 output driver to conserve power when the out-
put is unused.
0: CLK0 is powered up.
1: CLK0 is powered down.
6
MS0_INT
MultiSynth 0 Integer Mode.
This bit can be used to force MS0 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK0.
0: MS0 operates in fractional division mode.
1: MS0 operates in integer mode.
5
4
MS0_SRC
CLK0_INV
MultiSynth Source Select for CLK0.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 0 Invert.
0: Output Clock 0 is not inverted.
1: Output Clock 0 is inverted.
3:2 CLK0_SRC[1:0] Output Clock 0 Input Source.
These bits determine the input source for CLK0.
00: Select the XTAL as the clock source for CLK0. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK0 directly to the oscillator which
generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK0. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK0 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK0. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK0_IDRV[1:0] CLK0 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
30
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Register 17. CLK1 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK1_PDN MS1_INT MS1_SRC CLK1_INV
R/W R/W R/W R/W
CLK1_SRC[1:0]
R/W
CLK1_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK1_PDN
Clock 1 Power Down.
This bit allows powering down the CLK1 output driver to conserve power when the out-
put is unused.
0: CLK1 is powered up.
1: CLK1 is powered down.
6
MS1_INT
MultiSynth 1 Integer Mode.
This bit can be used to force MS1 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK1.
0: MS1 operates in fractional division mode.
1: MS1 operates in integer mode.
5
4
MS1_SRC
CLK1_INV
MultiSynth Source Select for CLK1.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 1 Invert.
0: Output Clock 1 is not inverted.
1: Output Clock 1 is inverted.
3:2 CLK1_SRC[1:0] Output Clock 1 Input Source.
These bits determine the input source for CLK1.
00: Select the XTAL as the clock source for CLK1. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK1 directly to the oscillator which
generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK1. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK1 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK1. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK1_IDRV[1:0] CLK1 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
Preliminary Rev. 0.95
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Si5351A/B/C
Register 18. CLK2 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK2_PDN MS2_INT MS2_SRC CLK2_INV
R/W R/W R/W R/W
CLK2_SRC[1:0]
R/W
CLK2_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK2_PDN
Clock 2 Power Down.
This bit allows powering down the CLK2 output driver to conserve power when the out-
put is unused.
0: CLK2 is powered up.
1: CLK2 is powered down.
6
MS2_INT
MultiSynth 2 Integer Mode.
This bit can be used to force MS2 into Integer mode to improve jitter performance. Note
that the fractional mode is necessary when a delay offset is specified for CLK2.
0: MS2 operates in fractional division mode.
1: MS2 operates in integer mode.
5
4
MS2_SRC
CLK2_INV
MultiSynth Source Select for CLK2.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 2 Invert.
0: Output Clock 2 is not inverted.
1: Output Clock 2 is inverted.
3:2 CLK2_SRC[1:0] Output Clock 2 Input Source.
These bits determine the input source for CLK2.
00: Select the XTAL as the clock source for CLK2. This option by-passes both synthesis
stages (PLL/VCXO & MultiSynth) and connects CLK2 directly to the oscillator which gen-
erates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK2. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK2 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK2. Select this option when using the Si5351
to generate free-running or synchronous clocks.
1:0 CLK2_IDRV[1:0] CLK2 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
32
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Register 19. CLK3 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK3_PDN MS3_INT MS3_SRC CLK3_INV
R/W R/W R/W R/W
CLK3_SRC[1:0]
R/W
CLK3_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK3_PDN
Clock 3 Power Down.
This bit allows powering down the CLK3 output driver to conserve power when the out-
put is unused.
0: CLK3 is powered up.
1: CLK3 is powered down.
6
MS3_INT
MultiSynth 3 Integer Mode.
This bit can be used to force MS3 into Integer mode to improve jitter performance.
Note that the fractional mode is necessary when a delay offset is specified for CLK3.
0: MS3 operates in fractional division mode.
1: MS3 operates in integer mode.
5
4
MS3_SRC
CLK3_INV
MultiSynth Source Select for CLK3.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 3 Invert.
0: Output Clock 3 is not inverted.
1: Output Clock 3 is inverted.
3:2
CLK3_SRC[1:0] Output Clock 3 Input Source.
These bits determine the input source for CLK3.
1:0 CLK3_IDRV[1:0] CLK3 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
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Register 20. CLK4 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK4_PDN MS4_INT MS4_SRC CLK4_INV
R/W R/W R/W R/W
CLK4_SRC[1:0]
R/W
CLK4_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK4_PDN
Clock 4 Power Down.
This bit allows powering down the CLK4 output driver to conserve power when the out-
put is unused.
0: CLK4 is powered up.
1: CLK4 is powered down.
6
MS4_INT
MultiSynth 4 Integer Mode.
This bit can be used to force MS4 into Integer mode to improve jitter performance.
Note that the fractional mode is necessary when a delay offset is specified for CLK4.
0: MS4 operates in fractional division mode.
1: MS4 operates in integer mode.
5
4
MS4_SRC
CLK4_INV
MultiSynth Source Select for CLK4.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 4 Invert.
0: Output Clock 4 is not inverted.
1: Output Clock 4 is inverted.
3:2
CLK4_SRC[1:0] Output Clock 4 Input Source.
These bits determine the input source for CLK4.
00: Select the XTAL as the clock source for CLK4. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK4 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK4. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK4 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK4. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK4_IDRV[1:0] CLK4 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
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Register 21. CLK5 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK5_PDN MS5_INT MS5_SRC CLK5_INV
R/W R/W R/W R/W
CLK5_SRC[1:0]
R/W
CLK5_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK5_PDN
Clock 5 Power Down.
This bit allows powering down the CLK5 output driver to conserve power when the out-
put is unused.
0: CLK4 is powered up.
1: CLK4 is powered down.
6
MS5_INT
MultiSynth 5 Integer Mode.
This bit can be used to force MS5 into Integer mode to improve jitter performance.
Note that the fractional mode is necessary when a delay offset is specified for CLK4.
0: MS5 operates in fractional division mode.
1: MS5 operates in integer mode.
5
4
MS5_SRC
CLK5_INV
MultiSynth Source Select for CLK5.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
Output Clock 5 Invert.
0: Output Clock 5 is not inverted.
1: Output Clock 5 is inverted.
3:2
CLK5_SRC[1:0] Output Clock 5 Input Source.
These bits determine the input source for CLK5.
00: Select the XTAL as the clock source for CLK5. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK5 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK5. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK5 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK5. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK5_IDRV[1:0] CLK5 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
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Si5351A/B/C
Register 22. CLK6 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK6_PDN FBA_INT MS6_SRC CLK6_INV
R/W R/W R/W R/W
CLK6_SRC[1:0]
R/W
CLK6_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK6_PDN
Clock 7 Power Down.
This bit allows powering down the CLK6 output driver to conserve power when the out-
put is unused.
0: CLK6 is powered up.
1: CLK6 is powered down.
6
5
FBA_INT
FBA MultiSynth Integer Mode.
Set this bit according to ClockBuilder Desktop generated register map file.
MS6_SRC
MultiSynth Source Select for CLK6.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
4
CLK6_INV
Output Clock 6 Invert.
0: Output Clock 6 is not inverted.
1: Output Clock 6 is inverted.
3:2
CLK6_SRC[1:0] Output Clock 0 Input Source.
These bits determine the input source for CLK6.
00: Select the XTAL as the clock source for CLK6. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK6 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK6. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK6 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK6. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK6_IDRV[1:0] CLK6 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
36
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Register 23. CLK7 Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK7_PDN FBB_INT MS7_SRC CLK7_INV
R/W R/W R/W R/W
CLK7_SRC[1:0]
R/W
CLK7_IDRV[1:0]
R/W
Reset value = 0000 0000
Bit
Name
Function
7
CLK7_PDN
Clock 7 Power Down.
This bit allows powering down the CLK7 output driver to conserve power when the out-
put is unused.
0: CLK7 is powered up.
1: CLK7 is powered down.
6
5
FBB_INT
FBB MultiSynth Integer Mode.
Set this bit according to ClockBuilder Desktop generated register map file.
MS7_SRC
MultiSynth Source Select for CLK7.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
4
CLK7_INV
Output Clock 7 Invert.
0: Output Clock 7 is not inverted.
1: Output Clock 7 is inverted.
3:2
CLK7_SRC[1:0] Output Clock 0 Input Source.
These bits determine the input source for CLK7.
00: Select the XTAL as the clock source for CLK7. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK7 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK7. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK7 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK7. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK7_IDRV[1:0] CLK7 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
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Register 24. CLK3–0 Disable State
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK3_DIS_STATE
R/W
CLK2_DIS_STATE
R/W
CLK1_DIS_STATE
R/W
CLK0_DIS_STATE
R/W
Reset value = 0000 0000
Bit
Name
CLKx_DIS_STATE Clock x Disable State.
Function
7:0
Where x = 0, 1, 2, 3. These 2 bits determine the state of the CLKx output when dis-
abled. Individual output clocks can be disabled using register Output Enable Con-
trol located at address 3. Outputs are also disabled using the OEB pin.
00: CLKx is set to a LOW state when disabled.
01: CLKx is set to a HIGH state when disabled.
10: CLKx is set to a HIGH IMPEDANCE state when disabled.
11: CLKx is NEVER DISABLED.
Register 25. CLK7–4 Disable State
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CLK7_DIS_STATE
R/W
CLK6_DIS_STATE
R/W
CLK5_DIS_STATE
R/W
CLK4_DIS_STATE
R/W
Reset value = 0000 0000
Bit
Name
CLKx_DIS_STATE Clock x Disable State.
Function
7:0
Where x = 4, 5, 6, 7. These 2 bits determine the state of the CLKx output when dis-
abled. Individual output clocks can be disabled using register Output Enable Con-
trol located at address 3. Outputs are also disabled using the OEB pin.
00: CLKx is set to a LOW state when disabled.
01: CLKx is set to a HIGH state when disabled.
10: CLKx is set to a HIGH IMPEDANCE state when disabled.
11: CLKx is NEVER DISABLED.
38
Preliminary Rev. 0.95
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Register 42. Multisynth0 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
MS0_P3[15:8]
R/W
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS0_P3[15:8]
Multisynth0 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth0 Divider.
Register 43. Multisynth0 Parameters
Bit
D7
D6
D5
D4
MS0_P3[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS0_P3[7:0]
Multisynth0 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth0 Divider.
Preliminary Rev. 0.95
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Register 44. Multisynth0 Parameters
Bit
D7
D6
D5
R0_DIV[2:0]
R/W
D4
D3
D2
D1
D0
Name
Type
MS0_P1[17:16]
R/W
R/W
R/W
R/W
Reset value = xxxx xxxx
Bit
7
Name
Unused
Function
6:4
R0_DIV[2:0]
R0 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3:2
1:0
Reserved
MS0_P1[17:16]
Multisynth0 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
MultiSynth0 divider.
Register 45. Multisynth0 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS0_P1[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS0_P1[15:8]
Multisynth0 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
MultiSynth1 divider.
40
Preliminary Rev. 0.95
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Register 46. Multisynth0 Parameters
Bit
D7
D6
D5
D4
MS0_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS0_P1[7:0]
Multisynth0 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
MultiSynth1 divider.
Register 47. Multisynth0 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS0_P3[19:16]
R/W
MS0_P2[19:16]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:4
MS0_P3[19:16]
Multisynth0 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth0 Divider
3:0
MS0_P2[19:16]
Multisynth0 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 Divider.
Register 48. Multisynth0 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS0_P2[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS0_P2[15:8]
Multisynth0 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 Divider.
Preliminary Rev. 0.95
41
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Register 49. Multisynth0 Parameters
Bit
D7
D6
D5
D4
MS0_P2[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS0_P2[7:0]
Multisynth0 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 Divider.
Register 50. Multisynth1 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS1_P3[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P3[15:8]
Multisynth1 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth1 Divider.
Register 51. Multisynth1 Parameters
Bit
D7
D6
D5
D4
MS1_P3[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P3[7:0]
Multisynth1 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth1 Divider.
42
Preliminary Rev. 0.95
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Register 52. Multisynth1 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
R1_DIV[2:0]
MS1_P1[17:16]
R/W
Name
R/W
R/W
R/W
R/W
Type
Reset value = xxxx xxxx
Bit
7
Name
Unused
Function
6:4
R1_DIV[2:0]
R1 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3:2
1:0
Reserved
MS1_P1[17:16]
Multisynth1 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
MultiSynth1 divider.
Register 53. Multisynth1 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS1_P1[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P1[15:8]
Multisynth1 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
MultiSynth1 divider.
Preliminary Rev. 0.95
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Register 54. Multisynth1 Parameters
Bit
D7
D6
D5
D4
MS1_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P1[7:0]
Multisynth1 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
MultiSynth1 divider.
Register 55. Multisynth1 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS1_P3[19:16]
R/W
MS1_P2[19:16]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:4
MS1_P3[19:16]
Multisynth1 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth1 Divider
3:0
MS1_P2[19:16]
Multisynth1 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 Divider.
Register 56. Multisynth1 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS1_P2[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P2[15:8]
Multisynth1 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 divider.
44
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Register 57. Multisynth1 Parameters
Bit
D7
D6
D5
D4
MS1_P2[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P2[7:0]
Multisynth1 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth1 divider.
Register 58. Multisynth1 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS1_P3[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P3[15:8]
Multisynth1 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth1 divider.
Register 59. Multisynth1 Parameters
Bit
D7
D6
D5
D4
MS1_P3[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS1_P3[7:0]
Multisynth1 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the MultiSynth1 divider.
Preliminary Rev. 0.95
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Register 60. Multisynth2 Parameters
Bit
D7
D6
D5
R2_DIV[2:0]
R/W
D4
D3
D2
D1
D0
Name
Type
MS2_P1[17:16]
R/W
R/W
R/W
R/W
Reset value = xxxx xxxx
Bit
7
Name
Unused
Function
6:4
R2_DIV[2:0]
R2 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3:2
1:0
Reserved
MS2_P1[17:16]
Multisynth2 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth2 divider.
Register 61. Multisynth2 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS2_P1[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS2_P1[15:8]
Multisynth2 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth2 divider.
46
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Register 62. Multisynth2 Parameters
Bit
D7
D6
D5
D4
MS2_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS2_P1[7:0]
Multisynth2 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth2 divider.
Register 63. Multisynth2 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS2_P3[19:16]
R/W
MS2_P2[19:16]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:4
MS2_P3[19:16]
Multisynth2 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth2 divider
3:0
MS2_P2[19:16]
Multisynth2 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth2 divider.
Register 64. Multisynth2 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS2_P2[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS2_P2[15:8]
Multisynth2 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth2 divider.
Preliminary Rev. 0.95
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Register 65. Multisynth2 Parameters
Bit
D7
D6
D5
D4
MS2_P2[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS2_P2[7:0]
Multisynth2 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth2 divider.
Register 66. Multisynth3 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS3_P3[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS3_P3[15:8]
Multisynth3 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth3 divider.
Register 67. Multisynth3 Parameters
Bit
D7
D6
D5
D4
MS3_P3[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS3_P3[7:0]
Multisynth3 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth3 divider.
48
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Register 68. Multisynth3 Parameters
Bit
D7
D6
D5
R3_DIV[2:0]
R/W
D4
D3
D2
D1
D0
Name
Type
MS3_P1[17:16]
R/W
R/W
R/W
R/W
Reset value = xxxx xxxx
Bit
7
Name
Unused
Function
6:4
R3_DIV[2:0]
R3 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3:2
1:0
Reserved
MS3_P1[17:16]
Multisynth3 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth3 divider.
Register 69. Multisynth3 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS3_P1[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS3_P1[15:8]
Multisynth3 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth3 divider.
Preliminary Rev. 0.95
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Register 70. Multisynth3 Parameters
Bit
D7
D6
D5
D4
MS3_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS3_P1[7:0]
Multisynth3 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth3 divider.
Register 71. Multisynth3 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS3_P3[19:16]
R/W
MS3_P2[19:16]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:4
MS3_P3[19:16]
Multisynth3 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth3 divider
3:0
MS3_P2[19:16]
Multisynth3 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth3 divider.
Register 72. Multisynth3 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS3_P2[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS3_P2[15:8]
Multisynth3 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth3 divider.
50
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Register 73. Multisynth3 Parameters
Bit
D7
D6
D5
D4
MS3_P2[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS3_P2[7:0]
Multisynth3 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth3 divider.
Register 74. Multisynth4 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS4_P3[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS4_P3[15:8]
Multisynth4 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth4 divider.
Register 75. Multisynth4 Parameters
Bit
D7
D6
D5
D4
MS4_P3[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS4_P3[7:0]
Multisynth4 Parameter 3.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth4 divider.
Preliminary Rev. 0.95
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Register 76. Multisynth4 Parameters
Bit
D7
D6
D5
R4_DIV[2:0]
R/W
D4
D3
D2
D1
D0
Name
Type
MS4_P1[17:16]
R/W
R/W
R/W
R/W
Reset value = xxxx xxxx
Bit
7
Name
Unused
Function
6:4
R4_DIV[2:0]
R4 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3:2
1:0
Reserved
MS4_P1[17:16]
Multisynth4 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth4 divider.
Register 77. Multisynth4 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS4_P1[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS4_P1[15:8]
Multisynth4 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth4 divider.
52
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Register 78. Multisynth4 Parameters
Bit
D7
D6
D5
D4
MS4_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS4_P1[7:0]
Multisynth4 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth4 divider.
Register 79. Multisynth4 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS4_P3[19:16]
R/W
MS4_P2[19:16]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:4
MS4_P3[19:16]
Multisynth4 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth4 divider
3:0
MS4_P2[19:16]
Multisynth4 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth4 divider.
Register 80. Multisynth4 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS4_P2[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS4_P2[15:8]
Multisynth4 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth4 Divider.
Preliminary Rev. 0.95
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Register 81. Multisynth4 Parameters
Bit
D7
D6
D5
D4
MS4_P2[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS4_P2[7:0]
Multisynth4 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth4 divider.
Register 82. Multisynth5 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS5_P3[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS5_P3[15:8]
Multisynth5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth5 divider.
Register 83. Multisynth5 Parameters
Bit
D7
D6
D5
D4
MS5_P3[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS5_P3[7:0]
Multisynth5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth5 divider.
54
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Register 84. Multisynth5 Parameters
Bit
D7
D6
D5
R5_DIV[2:0]
R/W
D4
D3
D2
D1
D0
Name
Type
MS5_P1[17:16]
R/W
R/W
R/W
R/W
Reset value = xxxx xxxx
Bit
7
Name
Unused
Function
6:4
R5_DIV[2:0]
R5 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3:2
1:0
Reserved
MS5_P1[17:16]
Multisynth5 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth5 divider.
Register 85. Multisynth5 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS5_P1[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS5_P1[15:8]
Multisynth5 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth5 divider.
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Register 86. Multisynth5 Parameters
Bit
D7
D6
D5
D4
MS5_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS5_P1[7:0]
Multisynth5 Parameter 1.
This 18-bit number is an encoded representation of the integer part of the
Multisynth5 divider.
Register 87. Multisynth5 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS5_P3[19:16]
R/W
MS5_P2[19:16]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:4
MS5_P3[19:16]
Multisynth5 Parameter 3.
This 20-bit number is an encoded representation of the denominator for the frac-
tional part of the Multisynth5 divider
3:0
MS5_P2[19:16]
Multisynth5 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the MultiSynth5 divider.
Register 88. Multisynth5 Parameters
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
MS5_P2[15:8]
R/W
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS5_P2[15:8]
Multisynth5 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth5 Divider.
56
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Register 89. Multisynth5 Parameters
Bit
D7
D6
D5
D4
MS5_P2[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS5_P2[7:0]
Multisynth5 Parameter 2.
This 20-bit number is an encoded representation of the numerator for the fractional
part of the Multisynth5 Divider.
Register 90. Multisynth6 Parameters
Bit
D7
D6
D5
D4
MS6_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS6_P1[7:0]
Multisynth6 Parameter 1.
This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be
even integers greater than or equal to 6. All other divide values are invalid.
Register 91. Multisynth7 Parameters
Bit
D7
D6
D5
D4
MS7_P1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = xxxx xxxx
Bit
Name
Function
7:0
MS7_P1[7:0]
Multisynth7 Parameter 1.
This 8-bit number is the Multisynth6 divide ratio. Multisynth6 divide ratio can only be
even integers greater than or equal to 6. All other divide values are invalid.
Preliminary Rev. 0.95
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Register 92. Clock 6 and 7 Output Divider
Bit
D7
D6
D5
R7_DIV[2:0]
R/W
D4
D3
D2
D1
R6_DIV[2:0]
R/W
D0
Name
Type
R/W
R/W
Reset value = xxxx xxxx
Bit
7
Name
Function
Reserved
R7_DIV[2:0]
Leave as default.
6:4
R7 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
3
Reserved
Leave as default.
1:0
R6_DIV[2:0]
R6 Output Divider.
000b: Divide by 1
001b: Divide by 2
010b: Divide by 4
011b: Divide by 8
100b: Divide by 16
101b: Divide by 32
110b: Divide by 64
111b: Divide by 128
58
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Register 165. CLK0 Initial Phase Offset
Bit
D7
D6
D5
D4
D3
CLK0_PHOFF[6:0]
R/W
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
Reserved
Only write 0 to this bit.
6:0 CLK0_PHOFF[6:0] Clock 0 Initial Phase Offset.
CLK0_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Register 166. CLK1 Initial Phase Offset
Bit
D7
D6
D5
D4
D3
CLK1_PHOFF[6:0]
R/W
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
Reserved
Only write 0 to this bit.
6:0 CLK1_PHOFF[6:0] Clock 1 Initial Phase Offset.
CLK1_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Register 167. CLK2 Initial Phase Offset
Bit
D7
D6
D5
D4
D3
CLK2_PHOFF[6:0]
R/W
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
Reserved
Only write 0 to this bit.
6:0 CLK2_PHOFF[6:0] Clock 2 Initial Phase Offset.
CLK2_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Preliminary Rev. 0.95
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Register 168. CLK3 Initial Phase Offset
Bit
D7
D6
D5
D4
D3
CLK3_PHOFF[6:0]
R/W
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
Reserved
Only write 0 to this bit.
6:0 CLK3_PHOFF[6:0] Clock 3 Initial Phase Offset.
CLK3_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Register 169. CLK4 Initial Phase Offset
Bit
D7
D6
D5
D4
D3
CLK4_PHOFF[6:0]
R/W
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
Reserved
Only write 0 to this bit.
6:0 CLK4_PHOFF[6:0] Clock 4 Initial Phase Offset.
CLK4_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
Register 170. CLK5 Initial Phase Offset
Bit
D7
D6
D5
D4
D3
CLK5_PHOFF[6:0]
R/W
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
Function
7
Reserved
Only write 0 to this bit.
6:0 CLK5_PHOFF[6:0] Clock 5 Initial Phase Offset.
CLK5_PHOFF[6:0] is an unsigned integer with one LSB equivalent to a time delay of
Tvco/4, where Tvco is the period of the VCO/PLL associated with this output.
60
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Si5351A/B/C
Register 177. PLL Reset
Bit
D7
PLLB_RST
R/W
D6
D5
PLLA_RST
R/W
D4
D3
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0000 0000
Bit
Name
PLLB_RST PLLB_Reset.
Writing a 1 to this bit will reset PLLB. This is a self clearing bit (Si5351A/C only).
Reserved Leave as default.
PLLA_RST PLLA_Reset.
Writing a 1 to this bit will reset PLLA. This is a self clearing bit.
Reserved Leave as default.
Function
7
6
5
4:0
Register 183. Crystal Internal Load Capacitance
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
XTAL_CL[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 11xx xxxx
Bit
Name
Function
7:6 XTAL_CL[1:0] Crystal Load Capacitance Selection.
These 2 bits determine the internal load capacitance value for the crystal. See "3.1.1.
00: Reserved. Do not select this option.
01: Internal CL = 6 pF.
10: Internal CL = 8 pF.
11: Internal CL = 10 pF (default).
5:0
Reserved
Leave as default.
Preliminary Rev. 0.95
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Si5351A/B/C
9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP)
Si5351A 20-QFN
Top View
Si5351A 24-QSOP
Top View
CLK5
VDDOC
CLK4
CLK6
1
2
3
24
23
22
CLK7
VDD0D
XA
XB
1
2
3
4
5
15
14
13
12
11
CLK7
VDD
GND
CLK0
CLK1
4
21
20
19
18
17
16
15
VDDOD
CLK0
5
GND
PAD
A0
XA
XB
GND
6
VDDOA
GND
7
SCL
SDA
CLK1
GND
A0
8
VDDOA
VDD0B
CLK2
CLK3
9
SCL
SDA
10
11
12
14
13
SSEN
OEB
Table 10. Si5351A Pin Descriptions
Pin Type*
Pin Number
20-QFN 24-QSOP
Pin Name
Function
XA
XB
1
2
6
I
I
Input pin for external crystal.
7
Input pin for external crystal.
Output clock 0.
Output clock 1.
Output clock 2.
Output clock 3.
Output clock 4.
Output clock 5.
Output clock 6.
Output clock 7.
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
A0
13
12
9
21
20
15
14
3
O
O
O
O
O
O
O
O
I
8
19
17
16
15
3
1
24
23
9
2
I C address bit.
2
SCL
4
10
11
12
13
4
I
I C bus serial clock input. Pull-up to VDD core with 1 k
2
SDA
5
I/O
I
I C bus serial data input. Pull-up to VDD core with 1 k
SSEN
OEB
6
Spread spectrum enable. High = enabled, Low = disabled.
Output driver enable. Low = enabled, High = disabled.
Core voltage supply pin. See 6.2.
7
I
VDD
20
11
10
18
14
P
P
P
P
P
P
VDDOA
VDDOB
VDDOC
VDDOD
GND
18
16
2
Output voltage supply pin for CLK0 and CLK1. See 6.2.
Output voltage supply pin for CLK2 and CLK3. See 6.2.
Output voltage supply pin for CLK4 and CLK5. See 6.2.
Output voltage supply pin for CLK6 and CLK7. See 6.2.
Ground. Use multiple vias to ensure a solid path to GND.
22
Center Pad 5, 8, 17, 19
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
62
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Si5351A/B/C
10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP)
Si5351B 24-QSOP
Top View
Si5351B 20-QFN
Top View
CLK5
VDDOC
CLK4
1
2
3
24
23
22
CLK6
CLK7
VDD0D
CLK7
XA
XB
1
2
3
4
5
15
14
13
12
11
VDD
GND
XA
4
5
21
20
CLK0
CLK1
GND
VDDOD
CLK0
GND
PAD
6
19
18
17
16
15
14
13
VC
XB
7
VDDOA
GND
CLK1
SCL
SDA
GND
VC
8
VDDOA
9
VDD0B
CLK2
SCL
10
11
12
SDA
CLK3
OEB
SSEN
Table 11. Si5351B Pin Descriptions
Pin Type*
Pin Number
Pin Name
Function
20-QFN
1
24-QSOP
XA
XB
6
I
I
Input pin for external crystal
2
7
Input pin for external crystal
Output clock 0
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
VC
13
12
9
21
20
15
14
3
O
O
O
O
O
O
O
O
I
Output clock 1
Output clock 2
8
Output clock 3
19
17
16
15
3
Output clock 4
1
Output clock 5
24
23
9
Output clock 6
Output clock 7
VCXO control voltage input
2
SCL
4
10
11
12
13
4
I
I C bus serial clock input. Pull-up to VDD core with 1 k
2
SDA
5
I/O
I
I C bus serial data input. Pull-up to VDD core with 1 k
SSEN
OEB
6
Spread spectrum enable. High = enabled, Low = disabled.
Output driver enable. Low = enabled, High = disabled.
Core voltage supply pin
7
I
VDD
20
11
10
18
14
P
P
P
P
P
P
VDDOA
VDDOB
VDDOC
VDDOD
GND
18
16
2
Output voltage supply pin for CLK0 and CLK1. See 6.2
Output voltage supply pin for CLK2 and CLK3. See 6.2
Output voltage supply pin for CLK4 and CLK5. See 6.2
Output voltage supply pin for CLK6 and CLK7. See 6.2
Ground
22
Center Pad 5, 8, 17, 19
*Note: I = Input, O = Output, P = Power
*Note: Input pins are not internally pulled up.
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Si5351A/B/C
11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP)
Si5351C 24-QSOP
Top View
Si5351C 20-QFN
Top View
CLK5
VDDOC
CLK4
CLK6
1
2
3
24
23
22
CLK7
VDD0D
XA
XB
1
2
3
4
5
15 CLK7
VDD
GND
CLK0
CLK1
4
21
20
19
18
17
16
15
14 VDDOD
5
GND
PAD
XA
XB
GND
6
13
INTR
SCL
SDA
CLK0
12 CLK1
11 VDDOA
VDDOA
GND
7
GND
INTR
SCL
8
VDD0B
CLK2
CLK3
OEB
9
10
SDA
CLKIN
11
12
14
13
Table 12. Si5351C Pin Descriptions
Pin Type*
Pin Number
Pin Name
Function
20-QFN
24-QSOP
XA
1
2
6
7
I
Input pin for external crystal.
XB
I
Input pin for external crystal.
Output clock 0.
Output clock 1.
Output clock 2.
Output clock 3.
Output clock 4.
Output clock 5.
Output clock 6.
Output clock 7.
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
INTR
13
12
9
21
20
15
14
3
O
O
O
O
O
O
O
O
O
8
19
17
16
15
3
1
24
23
9
Interrupt pin. Open drain active low output, requires a pull-up
resistor greater than 1 k
2
SCL
SDA
4
5
10
11
12
13
4
I
I/O
I
I C bus serial clock input. Pull-up to VDD core with 1 k
2
I C bus serial data input. Pull-up to VDD core with 1 k
CLKIN
OEB
6
PLL clock input.
7
I
Output driver enable. Low = enabled, High = disabled.
Core voltage supply pin
VDD
20
11
10
18
14
P
P
P
P
P
P
VDDOA
VDDOB
VDDOC
VDDOD
GND
18
16
2
Output voltage supply pin for CLK0 and CLK1. See 6.2
Output voltage supply pin for CLK2 and CLK3. See 6.2
Output voltage supply pin for CLK4 and CLK5. See 6.2
Output voltage supply pin for CLK6 and CLK7. See 6.2
Ground.
22
Center Pad 5, 8, 17, 19
Notes:
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
64
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Si5351A/B/C
12. Si5351A Pin Descriptions (10-Pin MSOP)
Si5351A 10-MSOP
Top View
VDD
XA
CLK0
CLK1
GND
1
2
3
10
9
XB
8
SCL
SDA
VDDO
CLK2
4
5
7
6
Table 13. Si5351A 10-MSOP Pin Descriptions
Pin
Number
Pin Name
Pin Type*
Function
10-MSOP
XA
2
3
I
I
Input pin for external crystal.
Input pin for external crystal.
Output clock 0.
XB
CLK0
CLK1
CLK2
SCL
10
9
O
O
O
I
Output clock 1.
6
Output clock 2.
2
4
Serial clock input for the I C bus. This pin must be pulled-up using a pull-
up resistor of at least 1 k.
2
SDA
5
I/O
Serial data input for the I C bus. This pin must be pulled-up using a pull-up
resistor of at least 1 k.
VDD
1
7
P
P
Core voltage supply pin.
VDDO
Output voltage supply pin for CLK0, CLK1, and CLK2. See "6.2. Power
GND
8
P
Ground.
*Note: I = Input, O = Output, P = Power
Preliminary Rev. 0.95
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Si5351A/B/C
13. Ordering Information
Si5351X
A
XX
*Note: The 10-MSOP is only
available in the Si5351A variant.
GT = 10-MSOP*
GM = 20-QFN
GU = 24-QSOP
A = Product Revision A
A = Crystal In
B = Crystal In + VCXO
C = Crystal In + CLKIN
Figure 19. Device Part Numbers
An evaluation kit containing ClockBuilder Desktop software and hardware enable easy evaluatin of the Si5351A/B/C.
Si535X
XXXXX
EVB
EVB = Evaluation Kit
20-QFN
XXXXX =
24-QSOP
Figure 20. Si5351A/B/C Evaluation Kit
66
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Si5351A/B/C
14. Package Outline (24-Pin QSOP)
Table 14. 24-QSOP Package Dimensions
Dimension
Min
—
Nom
—
Max
1.75
0.25
0.30
0.25
8.75
A
A1
b
0.10
0.19
0.15
8.55
—
—
c
—
D
8.65
E
6.00 BSC
3.90
E1
e
3.81
0.40
0
3.99
1.27
8
0.635 BSC
—
L
L2
q
0.25 BSC
—
aaa
bbb
ccc
0.10
0.17
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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Si5351A/B/C
15. Package Outline (20-Pin QFN)
Table 15. Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
b
0.02
0.25
D
4.00 BSC
2.70
D2
e
2.65
2.75
0.50 BSC
4.00 BSC
2.70
E
E2
L
2.65
0.30
2.75
0.50
0.10
0.10
0.08
0.10
0.10
0.40
aaa
bbb
ccc
ddd
eee
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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16. Package Outline (10-Pin MSOP)
Table 16. 24-QSOP Package Dimensions
Dimension
Min
—
Nom
Max
1.10
0.15
0.95
0.33
0.23
A
A1
A2
b
—
—
0.00
0.75
0.17
0.08
0.85
—
c
—
D
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
E
E1
e
L
0.40
0.80
L2
q
0.25 BSC
—
0
8
aaa
bbb
ccc
ddd
—
—
—
—
—
0.20
0.25
0.10
0.08
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Preliminary Rev. 0.95
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Si5351A/B/C
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.9
Updated max output frequency.
Added register descriptions.
Revision 0.9 to Revision 0.95
Added 1.8 V VDDO support.
70
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Si5351A/B/C
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