Renesas Stereo System M32R FPU User Guide

REJ09B0112-0101Z

M32R-FPU

Software Manual

RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

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current document available.

Rev. 1.01

Revision date: Oct 31, 2003

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M32R-FPU Software Manual

REVISION HISTORY

Rev.

Date

Description

Summary

Page

1.00 Jan 08, 2003

–

First edition issued

1.01 Oct 31, 2003 APPENDICES-3 Hexadecimal Instruction Code Table corrected (BTST instruction)

APPENDICES-8 Appendix Figure 3.1.1 corrected

Incorrect) *The E1 stage of the FDIV instruction requires 13 cycles.

Correct) *The E1 stage of the FDIV instruction requires 14 cycles.

APPENDICES-10 Appendix Figure 3.2.1 corrected

Incorrect) LD1 Correct) LDI

APPENDICES-13 Appendix Figure 3.2.4 corrected

Incorrect) ADD R1,R6,R7 Correct) FMADD R1,R6,R7

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Table of contents

CHAPTER 1 CPU PROGRAMMING MODEL

1.1 CPU register .......................................................................................................... 1-2

1.2 General-purpose registers ...................................................................................... 1-2

1.3 Control registers ..................................................................................................... 1-3

1.3.1 Processor status word register: PSW (CR0) ...................................... 1-4

1.3.2 Condition bit register: CBR (CR1) ...................................................... 1-5

1.3.3 Interrupt stack pointer: SPI (CR2)

User stack pointer: SPU (CR3) .......................................................... 1-5

1.3.4 Backup PC: BPC (CR6) ..................................................................... 1-5

1.3.5 Floating-Point Status Register: FPSR (CR7) ..................................... 1-6

1.3.6 Floating-Point Exceptions (FPE) ........................................................ 1-8

1.4 Accumulator ............................................................................................................ 1-11

1.5 Program counter ..................................................................................................... 1-11

1.6 Data format ............................................................................................................. 1-12

1.6.1 Data type ............................................................................................ 1-12

1.6.2 Data format......................................................................................... 1-13

1.7 Addressing mode .................................................................................................... 1-15

CHAPTER 2 INSTRUCTION SET

2.1 Instruction set overview ......................................................................................... 2-2

2.1.1 Load/store instructions ....................................................................... 2-2

2.1.2 Transfer instructions ........................................................................... 2-4

2.1.3 Operation instructions ........................................................................ 2-4

2.1.4 Branch instructions ............................................................................. 2-6

2.1.5 EIT-related instructions ...................................................................... 2-8

2.1.6 DSP function instructions ................................................................... 2-8

2.1.7 Floating-point Instructions .................................................................. 2-11

2.1.8 Bit Operation Instructions ................................................................... 2-11

2.2 Instruction format ................................................................................................... 2-12

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CHAPTER 3 INSTRUCTIONS

3.1 Conventions for instruction description ................................................................... 3-2

3.2 Instruction description ............................................................................................. 3-5

APPENDIX

Appendix 1 Hexadecimal Instraction Code .................................................................. Appendix-2

Appendix 2 Instruction List........................................................................................... Appendix-4

Appendix 3 Pipeline Processing .................................................................................. Appendix-8

Appendix 3.1 Instructions and Pipeline Processing .................................... Appendix-8

Appendix 3.2 Pipeline Basic Operation ....................................................... Appendix-10

Appendix 4 Instruction Execution Time ....................................................................... Appendix-17

Appendix 5 IEEE754 Specification Overview .............................................................. Appendix-18

Appendix 5.1 Floating Point Formats .......................................................... Appendix-18

Appendix 5.2 Rounding ............................................................................... Appendix-20

Appendix 5.3 Exceptions ............................................................................. Appendix-20

Appendix 6 M32R-FPU Specification Supplemental Explanation ...................................... Appendix-23

Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU)

vs. two instructions (FMUL and FADD) ................................. Appendix-23

Appendix 6.1.1 Rounding Mode ............................................................ Appendix-23

Appendix 6.1.2 Exception occurring in Step 1 ....................................... Appendix-23

Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU ........... Appendix-28

Appendix 7 Precautions ............................................................................................... Appendix-29

Appendix 7.1 Precautions to be taken when aligning data........................... Appendix-29

INDEX

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CHAPTER 1

CPU PROGRAMMIING MODEL

1.1

1.2

1.3

1.4

1.5

1.6

1.7

CPU Register

General-purpose Registers

Control Registers

Accumulator

Program Counter

Data Format

Addressing Mode

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CPU PROGRAMMING MODEL

1.1 CPU Register

The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16

general-purpose registers, 6 control registers, an accumulator and a program

counter. The accumulator is of 56-bit configuration, and all other registers are a 32-

bit configuration.

1.2 General-purpose Registers

The 16 general-purpose registers (R0 – R15) are of 32-bit width and are used to

retain data and base addresses, as well as for integer calculations, floating-point

operations, etc. R14 is used as the link register and R15 as the stack pointer. The link

instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are

alternately represented by R15 depending on the value of the Stack Mode (SM) bit in

the Processor Status Word Register (PSW).

At reset release, the value of the general-purpose registers is undefined.

b31

R10

R11

R12

R13

R14 (Link register)

R15 (Stack pointer)

(Note 1)

Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW.

Figure 1.2.1 General-purpose Registers

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CPU PROGRAMMING MODEL

1.3 Control Registers

There are 6 control registers which are the Processor Status Word Register (PSW),

the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack

Pointer (SPU), the Backup PC (BPC) and the Floating-point Status Register (FPSR).

The dedicated MVTC and MVFC instructions are used for writing and reading these

control registers.

In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW

instruction or the CLRPSW instruction.

CRn

b31

CR0

CR1

CR2

CR3

PSW

CBR

SPI

Processor Status Register

Condition Bit Register

Interrupt Stack Pointer

User Stack Pointer

SPU

Backup PC

CR6

CR7

BPC

FPSR

Floating-point Status Register

Notes: • CRn (n = 0 - 3, 6 and 7) denotes the control register number.

• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.

• The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW instruction or the CLRPSW

instruction.

Figure 1.3.1 Control Registers

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CPU PROGRAMMING MODEL

1.3 Control Registers

1.3.1 Processor Status Word Register: PSW (CR0)

b15

b16

b31

BSM BIE

BPSW field

PSW field

< At reset release: "B'0000 0000 0000 0000 ??00 000? 0000 0000 >

Bit Name

Function

0-15 No function assigned. Fix to "0".

BSM

Saves value of SM bit when EIT occurs

Saves value of IE bit when EIT occurs

Backup SM Bit

BIE

Backup IE Bit

18-22 No function assigned. Fix to "0".

Saves value of C bit when EIT occurs

Backup C Bit

0: Uses R15 as the interrupt stack pointer

1: Uses R15 as the user stack pointer

0: Does not accept interrupt

Stack Mode Bit

Interrupt Enable Bit

1: Accepts interrupt

26-30 No function assigned. Fix to "0".

Indicates carry, borrow and overflow resulting

from operations (instruction dependent)

Condition Bit

The Processor Status Word Register (PSW) indicates the M32R-FPU status. It

consists of the current PSW field which is regularly used, and the BPSW field where

a copy of the PSW field is saved when EIT occurs.

The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and

the Condition (C) bit.

The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt

Enable (BIE) bit and the Backup Condition (BC) bit.

At reset release, BSM, BIE and BC are undefined. All other bits are "0".

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CPU PROGRAMMING MODEL

1.3 Control Registers

1.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its

Condition (C) bit. The value written to the PSW register's C bit is reflected in this

instruction is ignored.)

At reset release, the value of CBR is "H'0000 0000".

b31

CBR

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0

0 0 0 0 0 0 0

0 0 0

1.3.3 Interrupt Stack Pointer: SPI (CR2)

User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the

address of the current stack pointer. These registers can be accessed as the

general-purpose register R15. R15 switches between representing the SPI and

SPU depending on the value of the Stack Mode (SM) bit in the PSW.

At reset release, the value of the SPI and SPU are undefined.

b31

SPI

b31

SPU

1.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when

an EIT occurs. Bit 31 is fixed to "0".

When an EIT occurs, the register sets either the PC value when the EIT occurred or

the PC value for the next instruction depending on the type of EIT. The BPC value

is loaded to the PC when the RTE instruction is executed. However, the values of

the lower 2 bits of the PC are always "00" when returned (PC always returns to the

word-aligned address).

At reset release, the value of the BPC is undefined.

b31

BPC

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1.3 Control Registers

1.3.5 Floating-point Status Register: FPSR (CR7)

b15

b16

b31

Bit Name

Function

Reflects the logical sum of FU, FZ, FO and FV.

–

Floating-point Exception

Summary Bit

Set to "1" when an inexact exception occurs

(if EIT processing is unexecuted (Note 1)).

Once set, the flag retains the value "1" until

it is cleared to "0" in software.

Inexact Exception Flag

Set to "1" when an underflow exception occurs

(if EIT processing is unexecuted (Note 1)).

Once set, the flag retains the value "1" until

it is cleared to "0" in software.

Underflow Exception Flag

Set to "1" when a zero divide exception occurs

(if EIT processing is unexecuted (Note 1)).

Once set, the flag retains the value "1" until

it is cleared to "0" in software.

Zero Divide Exception Flag

Set to "1" when an overflow exception occurs

(if EIT processing is unexecuted (Note 1)).

Once set, the flag retains the value "1" until

it is cleared to "0" in software.

Overflow Exception Flag

Set to "1" when an invalid operation exception

occurs (if EIT processing is unexecuted (Note 1)).

Once set, the flag retains the value "1" until

it is cleared to "0" in software.

Invalid Operation Exception

Flag

6–16

No function assigned. Fix to "0".

0: Mask EIT processing to be executed when an

inexact exception occurs

Inexact Exception Enable

Bit

1: Execute EIT processing when an inexact

exception occurs

0: Mask EIT processing to be executed when an

underflow exception occurs

Underflow Exception Enable

Bit

1: Execute EIT processing when an underflow

exception occurs

0: Mask EIT processing to be executed when a

zero divide exception occurs

Zero Divide Exception

Enable Bit

1: Execute EIT processing when a zero divide

exception occurs

0: Mask EIT processing to be executed when an

overflow exception occurs

Overflow Exception

Enable Bit

1: Execute EIT processing when an overflow

exception occurs

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CPU PROGRAMMING MODEL

1.3 Control Registers

0: Mask EIT processing to be executed when an

invalid operation exception occurs

Invalid Operation Exception

Enable Bit

1: Execute EIT processing when an invalid

operation exception occurs

No function assigned. Fix to "0".

0: Handle the denormalized number as a

denormalized number

Denormalized Number Zero

Flash Bit (Note 2)

1: Handle the denormalized number as zero

0: No unimplemented operation exception occurred .

1: An unimplemented operation exception occurred.

When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

0: No inexact exception occurred.

R (Note 3)

Unimplemented Operation

Exception Cause Bit

Inexact Exception Cause

Bit

1: An inexact exception occurred.

When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

0: No underflow exception occurred.

Underflow Exception Cause

Bit

1: An underflow exception occurred.

When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

0: No zero divide exception occurred.

1: A zero divide exception occurred.

Zero Divide Exception

Cause Bit

When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

0: No overflow exception occurred.

Overflow Exception

Cause Bit

1: An overflow exception occurred.

When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

0: No invalid operation exception occurred.

1: An invalid operation exception occurred.

When the bit is set to "1", the execution of an

FPU operation instruction will clear it to "0".

00: Round to Nearest

Invalid Operation Exception

Cause Bit

30, 31

Rounding Mode Selection Bit 01: Round toward Zero

10: Round toward +Infinity

11: Round toward -Infinity

Note 1: ‘If EIT processing is unexecuted’ means whenever one of the exceptions occurs, enable bits

17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two

exceptions occur at the same time and their corresponding exception enable bits are

set differently (one enabled, and the other masked), EIT processing is executed. In this

case, these two flags do not change state regardless of the enable bit settings.

Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented

exception occurs.

Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had

before the write).

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CPU PROGRAMMING MODEL

1.3 Control Registers

1.3.6 Floating-point Exceptions (FPE)

Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or

one of the five exceptions specified in the IEEE754 standard (OVF/UDF/IXCT/

DIV0/IVLD) is detected. Each exception processing is outlined below.

(1) Overflow Exception (OVF)

The exception occurs when the absolute value of the operation result exceeds the

largest describable precision in the floating-point format. The following table shows

the operation results when an OVF occurs.

Operation Result (Content of the Destination Register)

Rounding Mode Sign of the Result

When the OVF EIT processing

is masked (Note 1)

When the OVF EIT processing

is executed (Note 2)

–infinity

+infinity

–

+MAX

–infinity

+infinity

–MAX

No change

+MAX

–MAX

Nearest

+infinity

–infinity

Note 1: When the Overflow Exception Enable (EO) bit (FPSR register bit 20) = "0"

Note 2: When the Overflow Exception Enable (EO) bit (FPSR register bit 20) = "1"

Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.

• +MAX = H'7F7F FFFF, –MAX = H'FF7F FFFF

(2) Underflow Exception (UDF)

The exception occurs when the absolute value of the operation result is less than

the largest describable precision in the floating-point format. The following table

shows the operation results when a UDF occurs.

Operation Result (Content of the Destination Register)

When UDF EIT processing is masked (Note 1)

DN = 0: An unimplemented exception occurs

DN = 1: 0 is returned

When UDF EIT processing is executed (Note 2)

No change

Note 1: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "0"

Note 2: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "1"

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1.3 Control Registers

(3) Inexact Exception (IXCT)

The exception occurs when the operation result differs from a result led out with an

infinite range of precision. The following table shows the operation results and the

respective conditions in which each IXCT occurs.

Operation Result (Content of the Destination Register)

Occurrence Condition

When the IXCT EIT processing is

masked (Note 1)

When the IXCT EIT processing is

executed (Note 2)

Overflow occurs in OVF

masked condition

Reference OVF operation results

No change

Rounding occurs

Rounded value

No change

Note 1: When the Inexact Exception Enable (EX) bit (FPSR register bit 17) = "0"

Note 2: When the Inexact Exception Enable (EX) bit (FPSR register bit 17) = "1"

(4) Zero Division Exception (DIV0)

The exception occurs when a finite nonzero value is divided by zero. The following

table shows the operation results when a DIV0 occurs.

Operation Result (Content of the Destination Register)

Dividend

When the DIV0 EIT processing is

masked (Note 1)

When the DIV0 EIT processing is

executed (Note 2)

Nonzero finite value

±infinity (Sign is derived by exclusive-

No change

ORing the signs of divisor and dividend)

Note 1: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "0"

Note 2: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "1"

Please note that the DIV0 EIT processing does not occur in the following conditions.

Dividend

Behavior

An invalid operation exception occurs

No exception occur (with the result "infinity")

infinity

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1.3 Control Registers

(5) Invalid Operation Exception (IVLD)

The exception occurs when an invalid operation is executed. The following table shows

the operation results and the respective conditions in which each IVLD occurs.

Occurrence Condition

Operation Result (Content of the Destination Register)

When the IVLD EIT processing When the IVLD EIT

is masked (Note 1)

processing is executed

(Note 2)

Operation for SNaN operand

+infinity -(+infinity), -infinity -(-infinity)

0 ✕✕infinity

QNaN

0 ÷ 0, infinity ÷ infinity

When FTOI

Return value when

instruction

pre-conversion signed bit is:

"0" = H’7FFF FFFF

When an integer conversion

overflowed

was executed

No change

"1" = H’8000 0000

When NaN or Infinity was

converted into an integer

When FTOS

instruction

Return value when

pre-conversion signed bit is:

"0" = H’0000 7FFF

was executed

"1" = H’FFF 8000

When < or > comparison was

performed on NaN

Comparison results

(comparison invalid)

Note 1: When the Invalid Operation Exception Enable (EV) bit (FPSR register bit 21) = "0"

Note 2: When the Invalid Operation Exception Enable (EV) bit (FPSR register bit 21) = "1"

Notes: • NaN (Not a Number)

SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is “0”. When

SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful

in identifying program bugs when used as the initial value in a variable. However,

SNaNs cannot be generated by hardware.

QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when

QNaN is used as the source operand in an operation, an IVLD will not occur (excluding

comparison and format conversion). Because a result can be checked by the arithmetic

operations, QNaN allows the user to debug without executing an EIT processing.

QNaNs are created by hardware.

(6) Unimplemented Exception (UIPL)

The exception occurs when the Denormalized Number Zero Flash (DN) bit (FPSR

(Note 1).

Because the UIPL has no enable bits available, it cannot be masked when they

occur. The destination register remains unchanged.

Note: • A UDF occurs when the intermediate result of an operation is a denormalized

number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs.

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1.4 Accumulator

The Accumulator (ACC) is a 56-bit register used for DSP function instructions.

The accumulator is handled as a 64-bit register when accessed for read or write.

When reading data from the accumulator, the value of bit 8 is sign-extended. When

writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used

for the multiply instruction "MUL", in which case the accumulator value is destroyed

by instruction execution.

Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The

MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0-31)

and the low-order 32 bits (bits 32-63), respectively.

Use the MVFACHI, MVFACLO, and MVFACMI instructions for reading data from the

accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from

the high-order 32 bits (bits 0-31), the low-order 32 bits (bits 32-63) and the middle 32

bits (bits 16-47), respectively.

At reset release, the value of accumulator is undefined.

read range with MVFACMI instruction

(Note 1)

7 8

31 32

47 48

b63

ACC

read/write range with

MVTACHI or MVFACHI instruction

read/write range with

MVTACLO or MVFACLO instruction

Note 1: When read, bits 0 to 7 always show the sign-extended value of bit 8. Writing to this bit field is

ignored.

1.5 Program Counter

The Program Counter (PC) is a 32-bit counter that retains the address of the

instruction being executed. Since the M32R CPU instruction starts with even-

numbered addresses, the LSB (bit 31) is always "0".

At reset release, the value of the PC is "H’0000 0000."

b31

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1.6 Data Format

1.6.1 Data Type

The data types that can be handled by the M32R-FPU instruction set are signed or

unsigned 8, 16, and 32-bit integers and single-precision floating-point numbers.

The signed integers are represented by 2's complements.

signed byte (8-bit) integer

unsigned byte (8-bit) integer

b15

signed halfword (16-bit) integer

unsigned halfword (16-bit) integer

b31

signed word (32-bit) integer

unsigned word (32-bit) integer

floating-point single precision values

S: Sign bit

E: Exponent field

F: Fraction field

Figure 1.6.1 Data Type

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1.6 Data Format

1.6.2 Data Format

(1) Data format in a register

The data sizes in the M32R-FPU registers are always words (32 bits).

When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the

data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH

instructions) to a word (32-bit) quantity before being loaded into the register.

When storing data from a register into a memory, the 32-bit data, the 16-bit data on

the LSB side and the 8-bit data on the LSB side of the register are stored into

memory by the ST, STH and STB instructions, respectively.

from memory

(LDB, LDUB instruction)

< load >

sign-extention (LDB instruction) or

zero-extention (LDUB instruction)

b31

byte

sign-extention (LDH instruction) or

from memory (LDH, LDUH instruction)

zero-extention (LDUH instruction)

b31

halfword

from memory (LD instruction)

b31

word

< store >

b31

byte

to memory (STB instruction)

b31

halfword

to memory (STH instruction)

b31

word

to memory (ST instruction)

Figure 1.6.2 Data Format in a Register

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1.6 Data Format

(2) Data format in memory

The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits).

Although byte data can be located at any address, halfword and word data must be

located at the addresses aligned with a halfword boundary (least significant

address bit = "0") or a word boundary (two low-order address bits = "00"),

respectively. If an attempt is made to access memory data that overlaps the

halfword or word boundary, an address exception occurs.

Address

+0 address

+1 address

+2 address

+3 address

15 16

23 24

b31

byte

halfword

half

word

halfword

word

Figure 1.6.3 Data Format in Memory

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1.7 Addressing Mode

M32R-FPU supports the following addressing modes.

(1) Register direct [R or CR]

The general-purpose register or the control register to be processed is

specified.

(2) Register indirect [@R]

The contents of the register specify the address of the memory. This mode

can be used by all load/store instructions.

(3) Register relative indirect [@(disp, R)]

(The contents of the register) + (16-bit immediate value which is sign-

extended to 32 bits) specify the address of the memory.

(4) Register indirect and register update

• Adds 4 to register contents [@R+]

The contents of the register specify the memory address, then 4 is added to

the register contents.

(Can only be specified with LD instruction).

• Add 2 to register contents [@R+] [M32R-FPU extended addressing mode]

The contents of the register specify the memory address, then 2 is added to

the register contents.

(Can only be specified with STH instruction).

• Add 4 to register contents [@+R]

The contents of the register is added by 4, the register contents specify the

memory address.

(Can only be specified with ST instruction).

• Subtract 4 to register contents [@–R]

The content of the register is decreased by 4, then the register contents

specify the memory address.

(Can only be specified with ST instruction).

(5) immediate [#imm]

The 4-, 5-, 8-, 16- or 24-bit immediate value.

(6) PC relative [pcdisp]

(The contents of PC) + (8, 16, or 24-bit displacement which is sign-extended

to 32 bits and 2 bits left-shifted) specify the address of memory.

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CPU PROGRAMMING MODEL

1.7 Addressing Mode

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CHAPTER 2

INSTRUCTION SET

2.1 Instruction set overview

2.2 Instruction format

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INSTRUCTION SET

2.1 Instruction set overview

The M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture.

Memory is accessed by using the load/store instructions and other operations are

executed by using register-to-register operation instructions.

M32R CPU supports compound instructions such as " load & address update" and "store

& address update" which are useful for high-speed data transfer.

2.1.1 Load/store instructions

The load/store instructions carry out data transfers between a register and a memory.

Load

LDB

Load byte

LDUB

LDH

Load unsigned byte

Load halfword

Load unsigned halfword

Load locked

Store

LDUH

LOCK

STB

Store byte

STH

Store halfword

Store unlocked

UNLOCK

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INSTRUCTION SET

2.1 Instruction set overview

Three types of addressing modes can be specified for load/store instructions.

(1) Register indirect

The contents of the register specify the address. This mode can be used by all load/

store instructions.

(2) Register relative indirect

(The contents of the register) + (32-bit sign-extended 16-bit immediate value)

specifies the address. This mode can be used by all except LOCK and UNLOCK

instructions.

(3) Register indirect and register update

• Adds 4 to register contents [@R+]

The contents of the register specify the memory address, then 4 is added to the

(Can only be specified with LD instruction).

• Add 2 to register contents [@R+] [M32R-FPU extended addressing mode]

The contents of the register specify the memory address, then 2 is added to the

(Can only be specified with STH instruction).

• Add 4 to register contents [@+R]

The contents of the register is added by 4, the register contents specity the

memory address.

(Can only be specified with ST instruction).

• Subtract 4 to register contents [@–R]

The content of the register is decreased by 4, then the register contents specify

the memory address.

(Can only be specified with ST instruction).

When accessing halfword and word size data, it is necessary to specify the address on

the halfword boundary or the word boundary (Halfword size should be such that the low-

order 2 bits of the address are "00" or "10", and word size should be such that the low

order 2 bits of the address are "00"). If an unaligned address is specified, an address

exception occurs.

When accessing byte data or halfword data with load instructions, the high-order bits are

sign-extended or zero-extended to 32 bits, and loaded to a register.

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INSTRUCTION SET

2.1 Instruction set overview

2.1.2 Transfer instructions

The transfer instructions carry out data transfers between registers or a register and an

immediate value.

LD24

LDI

Load 24-bit immediate

Load immediate

Move register

MVFC

MVTC

SETH

Move from control register

Move to control register

Set high-order 16-bit

2.1.3 Operation instructions

Compare, arithmetic/logic operation, multiply and divide, and shift are carried out

between registers.

• compare instructions

CMP

Compare

CMPI

CMPU

CMPUI

Compare immediate

Compare unsigned

Compare unsigned immediate

• arithmetic operation instructions

ADD

Add

ADD3

ADDI

ADDV

ADDV3

ADDX

NEG

Add 3-operand

Add immediate

Add with overflow checking

Add 3-operand with overflow checking

Add with carry

Negate

SUB

Subtract

SUBV

SUBX

Subtract with overflow checking

Subtract with borrow

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INSTRUCTION SET

2.1 Instruction set overview

• logic operation instructions

AND

AND3

NOT

AND

AND 3-operand

Logical NOT

OR3

XOR

XOR3

OR 3-operand

Exclusive OR

Exclusive OR 3-operand

• multiply/divide instructions

DIV

Divide

DIVU

MUL

REM

REMU

Divide unsigned

Multiply

Remainder

Remainder unsigned

• shift instructions

SLL

Shift left logical

SLL3

SLLI

SRA

Shift left logical 3-operand

Shift left logical immediate

Shift right arithmetic

SRA3

SRAI

SRL

Shift right arithmetic 3-operand

Shift right arithmetic immediate

Shift right logical

SRL3

SRLI

Shift right logical 3-operand

Shift right logical immediate

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INSTRUCTION SET

2.1 Instruction set overview

2.1.4 Branch instructions

The branch instructions are used to change the program flow.

Branch on C-bit

BEQ

BEQZ

BGEZ

BGTZ

Branch on equal to

Branch on equal to zero

Branch on greater than or equal to zero

Branch on greater than zero

Branch and link

BLEZ

BLTZ

BNC

BNE

BNEZ

BRA

Branch on less than or equal to zero

Branch on less than zero

Branch on not C-bit

Branch on not equal to

Branch on not equal to zero

Branch

Jump and link

JMP

NOP

Jump

No operation

Only a word-aligned (word boundary) address can be specified for the branch address.

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INSTRUCTION SET

2.1 Instruction set overview

The addressing mode of the BRA, BL, BC and BNC instructions can specify an 8-bit or

24-bit immediate value. The addressing mode of the BEQ, BNE, BEQZ, BNEZ, BLTZ,

BGEZ, BLEZ, and BGTZ instructions can specify a 16-bit immediate value.

In the JMP and JL instructions, the register value becomes the branch address.

However, the low-order 2-bit value of the register is ignored. In other branch

instructions, (PC value of branch instruction) + (sign-extended and 2 bits left-shifted

immediate value) becomes the branch address. However, the low order 2-bit value of the

address becomes "00" when addition is carried out. For example, refer to Figure 2.1.1.

When instruction A or B is a branch instruction, branching to instruction G, the

immediate value of either instruction A or B becomes 4.

Simultaneous with execution of branching by the JL or BL instructions for subroutine

calls, the PC value of the return address is stored in R14. The low-order 2-bit value of

the address stored in R14 (PC value of the branch instruction + 4 ) is always cleared to

"0". For example, refer to Figure 2.1.1. If an instruction A or B is a JL or BL instruction,

the return address becomes that of the instruction C.

1 word (32 bits)

address

H'00

branch instruction

instruction A

instruction B

H'04

H'08

H'0C

H'10

instruction C

instruction G

instruction D

instruction H

instruction E

instruction F

Fig. 2.1.1 Branch addresses of branch instruction

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INSTRUCTION SET

2.1 Instruction set overview

2.1.5 EIT-related instructions

The EIT-related instructions carry out the EIT events (Exception, Interrupt and Trap).

Trap initiation and return from EIT are EIT-related instructions.

TRAP

RTE

Trap

Return from EIT

2.1.6 DSP function instructions

The DSP function instructions carry out multiplication of 32 bits x 16 bits and 16 bits x 16

bits or multiply and add operation; there are also instructions to round off data in the

accumulator and carry out transfer of data between the accumulator and a general-

purpose register.

MACHI

Multiply-accumulate high-order halfwords

Multiply-accumulate low-order halfwords

Multiply-accumulate word and high-order halfword

Multiply-accumulate word and low-order halfword

Multiply high-order halfwords

MACLO

MACWHI

MACWLO

MULHI

MULLO

Multiply low-order halfwords

MULWHI

MULWLO

MVFACHI

MVFACLO

MVFACMI

MVTACHI

MVTACLO

RAC

Multiply word and high-order halfword

Multiply word and low-order halfword

Move high-order word from accumulator

Move low-order word from accumulator

Move middle-order word from accumulator

Move high-order word to accumulator

Move low-order word to accumulator

Round accumulator

RACH

Round accumulator halfword

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INSTRUCTION SET

2.1 Instruction set overview

Rsrc1

15 16

Rsrc2

15 16

MULHI instruction

MULLO instruction

ACC

Rsrc1

Rsrc2

15 16

32 bits

MULWHI instruction

MULWLO instruction

ACC

Rsrc1

15 16

Rsrc2

15 16

ACC

MACHI instruction

MACLO instruction

ACC

Rsrc1

Rsrc2

15 16

32 bits

ACC

MACWHI instruction

MACWLO instruction

ACC

Note: The location in the accumulator of the result and the appropriate sign extension are performed

in the execution of the DSP function instruction. Refer to Chapter 3 for details.

Fig. 2.1.2 DSP function instruction operation 1 (multiply, multiply and accumulate)

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INSTRUCTION SET

2.1 Instruction set overview

< word size round off >

< halfword size round off >

ACC

RAC instruction

data

RACH instruction

sign

data

Note: The actual operation is processed in two steps.

Refer to Chapter 3 for details.

Fig. 2.1.3 DSP function instruction operation 2 (round off)

MVFACMI instruction

15 16

31 32

ACC

47 48

Rsrc

MVFACHI

instruction

MVFACLO

instruction

MVTACHI

instruction

MVTACLO

instruction

31 32

ACC

Rdest

Fig. 2.1.4 DSP function instruction operation 3 (transfer between accumulator and register)

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INSTRUCTION SET

2.1 Instruction set overview

2.1.7 Floating-point Instructions

The following instructions execute floating-point operations.

FADD

FSUB

FMUL

FDIV

FMADD

FMSUB

ITOF

Floating-point add

Floating-point subtract

Floating-point multiply

Floating-point divede

Floating-point multiply and add

Floating-point multiply and subtract

Integer to float

UTOF

FTOI

Unsigned integer to float

Float to integer

FTOS

FCMP

FCMPE

Float to short

Floating-point compare

Floating-point compare with exeption if unordered

2.1.8 Bit Operation Instructions

These instructions determine the operation of the bit specified by the register or

memory.

BSET

Bit set

BCLR

BTST

Bit clear

Bit test

SETPSW

CLRPSW

Set PSW

Clear PSW

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INSTRUCTION SET

2.2 Instruction format

There are two major instruction formats: two 16-bit instructions packed together within a

word boundary, and a single 32-bit instruction (see Figure 2.2.1). Figure 2.2.2 shows

the instruction format of M32R CPU.

1 word

address

+ 0

+ 1

+ 2

+ 3

16-bit instruction A

16-bit instruction B

1 word

+ 0

+ 1

+ 2

+ 3

32-bit instruction

Fig. 2.2.1 16-bit instruction and 32-bit instruction

< 16-bit instruction >

= R1 op

op1

op2

Branch (Short Displacement)

op1 cond

< 32-bit instruction >

op1

op2

= R2 op

Compare and Branch

= R1 op

Branch

op1 cond

Floating-point 2-operand

(Rd=op(Rs))

op1

op2

op3

op4

0000

Floating-point 3-operand

(Rd=Rs1 op Rs2)

Rs1

Rs2

Fig. 2.2.2 Instruction format of M32R CPU

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INSTRUCTION SET

2.2 Instruction format

The MSB (Most Significant Bit) of a 32-bit instruction is always "1". The MSB of a 16-bit

instruction in the high-order halfword is always "0" (instruction A in Figure 2.2.3),

however the processing of the following 16-bit instruction depends on the MSB of the

instruction.

In Figure 2.2.3, if the MSB of the instruction B is "0", instructions A and B are executed

sequentially; B is executed after A. If the MSB of the instruction B is "1", instructions A

and B are executed in parallel.

The current implementation allows only the NOP instruction as instruction B for parallel

execution. The MSB of the NOP instruction used for word arraignment adjustment is

changed to "1" automatically by a standard Mitsubishi assembler, then the M32R-FPU

can execute this instruction without requiring any clock cycles.

MSB

< instruction execution sequence >

16-bit instruction A

16-bit instruction B

[instruction A] --> [instruction B] sequential

[instruction A] & [instruction B] parallel

32-bit instruction

NOP instruction

inserted by assembler

0111 0000 0000 0000

NOP instruction whose MSB is changed to "1"

1111 0000 0000 0000

[instruction A] & [NOP] parallel

16-bit instruction A

32-bit instruction

Fig. 2.2.3 Processing of 16-bit instructions

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INSTRUCTION SET

2.2 Instruction format

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CHAPTER 3

INSTRUCTIONS

3.1 Conventions for instruction

description

3.2 Instruction description

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INSTRUCTIONS

3.1 Conventions for instruction description

Conventions for instruction description are summarized below.

[Mnemonic]

Shows the mnemonic and possible operands (operation target) using assembly

language notation.

Table 3.1.1 Operand list

symbol(see note) addressing mode

operation target

control register

general-purpose registers (R0 - R15)

Mcontrol registers (CR0 = PSW, CR1 = CBR, CR2 = SPI,

CR3 = SPU, CR6 = BPC, CR7 = FPSR)

memory specified by register contents as address

@(disp,R)

indirect

memory specified by (register contents) + (sign-extended value of

16-bit displacement) as address

@R+

@+R

@-R

contents, hen the register contents specify the memory address.)

immediate value (refer to each instruction description)

Contents of byte data bit position

#imm

immediate

#bitpos

pcdisp

Bit position

PC relative

memory specified by (PC contents) + (8, 16, or 24-bit displacement

which is sign-extended to 32 bits and 2 bits left-shifted) as address

Note: When expressing Rsrc or Rdest as an operand, a general-purpose register numbers (0 - 15) should be

substituted for src or dest. When expressing CRsrc or CRdest, control register numbers (0 - 3, 6, 7)

should be substituted for src or dest.

[Function]

Indicates the operation performed by one instruction. Notation is in accordance with C

language notation.

Table 3.1.2 Operation expression (operator)

operator

meaning

addition (binomial operator)

subtraction (binomial operator)

multiplication (binomial operator)

division (binomial operator)

✽

remainder operation (binomial operator)

increment (monomial operator)

decrement (monomial operator)

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INSTRUCTIONS

3.1 Conventions for instruction description

Table 3.1.3 Operation expression (operator) (cont.)

operator

meaning

sign invert (monomial operator)

substitute right side into left side (substitute operator)

adds right and left variables and substitute into left side (substitute operator)

subtract right variable from left variable and substitute into left side (substitute operator)

greater than (relational operator)

less than (relational operator)

greater than or equal to (relational operator)

less than or equal to (relational operator)

equal (relational operator)

not equal (relational operator)

| |

AND (logical operator)

OR (logical operator)

NOT (logical operator)

execute a conditional expression (conditional operator)

Table 3.1.4 Operation expression (bit operator)

operator

meaning

bits are left-shifted

bits are right-shifted

bit product (AND)

bit sum (OR)

bit exclusive or (EXOR)

bit invert

Table 3.1.5 Data type

expression

sign

yes

bit length

range

signed char

signed short

signed int

–128 to +127

–32,768 to +32,767

–2,147,483,648 to +2,147,483,647

0 to 255

unsigned char

unsigned short

unsigned int

signed64bit

0 to 655,535

0 to 4,294,967,295

signed 64-bit integer (with accumulator)

yes

Table 3.1.6 Data type (floating-point)

expression

float

floating-point format

single precision values format

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INSTRUCTIONS

3.1 Conventions for instruction description

[Description]

Describes the operation performed by the instruction and any condition bit change.

[EIT occurrence]

Shows possible EIT events (Exception, Interrupt, Trap) which may occur as the result of

the instruction's execution. Only address exception (AE), floating-point exception (FPE)

and trap (TRAP) may result from an instruction execution.

[Instruction format]

Shows the bit level instruction pattern (16 bits or 32 bits). Source and/or destination

displacement value is put in the imm or disp field, its maximum size being determined by

the width of the field provided for the particular instruction. Refer to 2.2 Instruction

format for detail.

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INSTRUCTIONS

3.2 Instruction description

This section lists M32R-FPU instructions in alphabetical order. Each page is laid out

as shown below.

arithmetic oper

instruction name

(instruction type and

full name are in center)

ADD

Add

[Mnemonic]

instruction mnemonic

Add Rdest,Rsrc

[Function]

Add

instruction function

(expression corresponds to

C language method)

Rdest = Rdest + Rsrc;

[Description]

instruction description

and effect on condition bit (C)

ADD adds Rsrc to Rdest and puts the result in

The condition bit (C) is unchanged.

EIT events which may

occur when this

instruction is executed

[EIT occurrence]

None

16- or 32-bit instruction format

[Instruction format]

0000 dest 1010 src

Add Rde

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INSTRUCTIONS

3.2 Instruction description

arithmetic/logic operation

ADD

Add

[Mnemonic]

ADD Rdest,Rsrc

[Function]

Add

Rdest = Rdest + Rsrc;

[Description]

ADD adds Rsrc to Rdest and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest 1010 src

ADD Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

ADD3

Add 3-operand

[Mnemonic]

ADD3 Rdest,Rsrc,#imm16

[Function]

Add

Rdest = Rsrc + ( signed short ) imm16;

[Description]

ADD3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest. The immediate

value is sign-extended to 32 bits before the operation.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1000 dest 1010 src

imm16

ADD3 Rdest,Rsrc,#imm16

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

ADDI

Add immediate

[Mnemonic]

ADDI Rdest,#imm8

[Function]

Add

Rdest = Rdest + ( signed char ) imm8;

[Description]

ADDI adds the 8-bit immediate value to Rdest and puts the result in Rdest.

The immediate value is sign-extended to 32 bits before the operation.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0100 dest imm8

ADDI Rdest,#imm8

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

ADDV

Add with overflow checking

[Mnemonic]

ADDV Rdest,Rsrc

[Function]

Add

Rdest = ( signed ) Rdest + ( signed ) Rsrc;

C = overflow ? 1 : 0;

[Description]

ADDV adds Rsrc to Rdest and puts the result in Rdest.

The condition bit (C) is set when the addition results in overflow; otherwise it is cleared.

[EIT occurrence]

None

[Encoding]

0000 dest 1000 src

ADDV Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

ADDV3

Add 3-operand with overflow checking

[Mnemonic]

ADDV3 Rdest,Rsrc,#imm16

[Function]

Add

Rdest = ( signed ) Rsrc + ( signed ) ( ( signed short ) imm16 );

C = overflow ? 1 : 0;

[Description]

ADDV3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest. The immediate

value is sign-extended to 32 bits before it is added to Rsrc.

The condition bit (C) is set when the addition results in overflow; otherwise it is cleared.

[EIT occurrence]

None

[Encoding]

1000 dest 1000 src

imm16

ADDV3 Rdest,Rsrc,#imm16

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

ADDX

Add with carry

[Mnemonic]

ADDX Rdest,Rsrc

[Function]

Add

Rdest = ( unsigned ) Rdest + ( unsigned ) Rsrc + C;

C = carry_out ? 1 : 0;

[Description]

ADDX adds Rsrc and C to Rdest, and puts the result in Rdest.

The condition bit (C) is set when the addition result cannot be represented by a 32-bit unsigned

integer; otherwise it is cleared.

[EIT occurrence]

None

[Encoding]

0000 dest 1001 src

ADDX Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

logic operation instruction

AND

[Mnemonic]

AND Rdest,Rsrc

[Function]

Logical AND

Rdest = Rdest & Rsrc;

[Description]

AND computes the logical AND of the corresponding bits of Rdest and Rsrc and puts the result

in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest 1100 src

AND Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

logic operation instruction

AND3

AND 3-operand

[Mnemonic]

AND3 Rdest,Rsrc,#imm16

[Function]

Logical AND

Rdest = Rsrc & ( unsigned short ) imm16;

[Description]

AND3 computes the logical AND of the corresponding bits of Rsrc and the 16-bit immediate

value, which is zero-extended to 32 bits, and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1000 dest

1100 src

imm16

AND3 Rdest,Rsrc,#imm16

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INSTRUCTIONS

3.2 Instruction description

branch instruction

Bit clear

M32R-FPU Extended Instruction

[Mnemonic]

(1) BC pcdisp8

(2) BC pcdisp24

[Function]

Branch

(1) if ( C==1 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 );

(2) if ( C==1 ) PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 );

where

#define sign_extend(x) ( ( ( signed ) ( (x)<< 8 ) ) >>8 )

[Description]

BC causes a branch to the specified label when the condition bit (C) is 1.

There are two instruction formats; which allows software, such as an assembler, to decide on

the better format.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

pcdisp8

0111 1100

1111 1100

BC pcdisp8

pcdisp24

BC pcdisp24

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INSTRUCTIONS

3.2 Instruction description

bit operation

Bit clear

BCLR

[M32R-FPU Extended Instruction]

[Mnemonic]

BCLR #bitpos,@(disp16,Rsrc)

[Function]

Bit operation for memory contents Set 0 to specified bit.

* ( signed char* ) ( Rsrc + ( signed short ) disp16 ) & = ~ ( 1<< ( 7-bitpos ) ) ;

[Description]

BCLR reads the byte data in the memory at the address specified by the Rsrc combined with

the 16-bit displacement, and then stores the value of the bit that was specified by bitpos to be set

to “0”. The displacement is sign-extended before the address calculation. bitpos becomes 0 to 7;

MSB becomes 0 and LSB becomes 7. The memory is accessed in bytes. The LOCK bit is on

while the BCLR instruction is executed, and is cleared when the execution is completed. The

LOCK bit is internal to the CPU and cannot be directly read or written to by the user.

Condition bit C remains unchanged.

The LOCK bit is internal to the CPU and is the control bit for receiving all bus right requests

from circuits other than the CPU.

Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to

the type of MCU.

[EIT occurrence]

None

[Encoding]

bitpos

1010

0111 src

disp16

BCLR #bitpos,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BEQ

Branch on equal to

[Mnemonic]

BEQ Rsrc1,Rsrc2,pcdisp16

[Function]

Branch

if ( Rsrc1 == Rsrc2 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2);

[Description]

BEQ causes a branch to the specified label when Rsrc1 is equal to Rsrc2.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 src1 0000 src2

pcdisp16

BEQ Rsrc1,Rsrc2,pcdisp16

3-16

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BEQZ

Branch on equal to zero

[Mnemonic]

BEQZ Rsrc,pcdisp16

[Function]

Branch

if ( Rsrc == 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2);

[Description]

BEQZ causes a branch to the specified label when Rsrc is equal to zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 0000 1000 src

BEQZ Rsrc,pcdisp16

pcdisp16

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BGEZ

Branch on greater than or equal to zero

[Mnemonic]

BGEZ Rsrc,pcdisp16

[Function]

Branch

if ( (signed) Rsrc >= 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2);

[Description]

BGEZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is

greater than or equal to zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 0000 1011 src

BGEZ Rsrc,pcdisp16

pcdisp16

3-18

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BGTZ

Branch on greater than zero

[Mnemonic]

BGTZ Rsrc,pcdisp16

[Function]

Branch

if ((signed) Rsrc > 0) PC = (PC & 0xfffffffc) + ( ( (signed short) pcdisp16 ) << 2);

[Description]

BGTZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is

greater than zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 0000 1101 src

BGTZ Rsrc,pcdisp16

pcdisp16

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INSTRUCTIONS

3.2 Instruction description

branch instruction

Branch and link

[Mnemonic]

(1) BL pcdisp8

(2) BL pcdisp24

[Function]

Subroutine call (PC relative)

(1) R14 = ( PC & 0xfffffffc ) + 4;

PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 );

(2) R14 = ( PC & 0xfffffffc ) + 4;

PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 );

where

#define sign_extend(x) ( ( ( signed ) ( (x)<< 8 ) ) >>8 )

[Description]

BL causes an unconditional branch to the address specified by the label and puts the return

address in R14.

There are two instruction formats; this allows software, such as an assembler, to decide on the

better format.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

pcdisp8

0111 1110

1111 1110

BL pcdisp8

pcdisp24

BL pcdisp24

3-20

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BLEZ

Branch on less than or equal to zero

[Mnemonic]

BLEZ Rsrc,pcdisp16

[Function]

Branch

if ((signed) Rsrc <= 0) PC = (PC & 0xfffffffc) + (((signed short) pcdisp16) << 2);

[Description]

BLEZ causes a branch to the specified label when the contents of Rsrc treated as a signed 32-

bit value, is less than or equal to zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 0000 1100 src

BLEZ Rsrc,pcdisp16

pcdisp16

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BLTZ

Branch on less than zero

[Mnemonic]

BLTZ Rsrc,pcdisp16

[Function]

Branch

if ((signed) Rsrc < 0) PC = (PC & 0xfffffffc) + (((signed short) pcdisp16) << 2);

[Description]

BLTZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is less

than zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 0000 1010 src

BLTZ Rsrc,pcdisp16

pcdisp16

3-22

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BNC

Branch on not C-bit

[Mnemonic]

(1) BNC pcdisp8

(2) BNC pcdisp24

[Function]

Branch

(1) if (C==0) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 );

(2) if (C==0) PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 );

where

#define sign_extend(x) ( ( ( signed ) ( (x)<< 8 ) ) >>8 )

[Description]

BNC branches to the specified label when the condition bit (C) is 0.

There are two instruction formats; this allows software, such as an assembler, to decide on the

better format.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

pcdisp8

0111 1101

1111 1101

BNC pcdisp8

pcdisp24

BNC pcdisp24

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BNE

Branch on not equal to

[Mnemonic]

BNE Rsrc1,Rsrc2,pcdisp16

[Function]

Branch

if ( Rsrc1 != Rsrc2 ) PC = ( PC & 0xfffffffc ) + ((( signed short ) pcdisp16) << 2);

[Description]

BNE causes a branch to the specified label when Rsrc1 is not equal to Rsrc2.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 src1 0001 src2

pcdisp16

BNE Rsrc1,Rsrc2,pcdisp16

3-24

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BNEZ

Branch on not equal to zero

[Mnemonic]

BNEZ Rsrc,pcdisp16

[Function]

Branch

if ( Rsrc != 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2);

[Description]

BNEZ causes a branch to the specified label when Rsrc is not equal to zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1011 0000 1001 src

BNEZ Rsrc,pcdisp16

pcdisp16

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INSTRUCTIONS

3.2 Instruction description

branch instruction

BRA

Branch

[Mnemonic]

(1) BRA pcdisp8

(2) BRA pcdisp24

[Function]

Branch

(1) PC = ( PC & 0xfffffffc ) + ( ( ( signed char ) pcdisp8 ) << 2 );

(2) PC = ( PC & 0xfffffffc ) + ( sign_extend ( pcdisp24 ) << 2 );

where

#define sign_extend(x) ( ( ( signed ) ( (x)<< 8 ) ) >>8 )

[Description]

BRA causes an unconditional branch to the address specified by the label.

There are two instruction formats; this allows software, such as an assembler, to decide on the

better format.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

pcdisp8

0111 1111

1111 1111

BRA pcdisp8

pcdisp24

BRA pcdisp24

3-26

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INSTRUCTIONS

3.2 Instruction description

bit operation Instructions

Bit set

BSET

[M32R-FPU Extended Instruction]

[Mnemonic]

BSET #bitpos,@(disp16,Rsrc)

[Function]

Bit operation for memory contents Set 0 to specified bit.

* ( signed char* ) ( Rsrc + ( signed short ) disp16 ) : = ( 1<< ( 7-bitpos ) ) ;

[Description]

BSET reads the byte data in the memory at the address specified by the Rsrc combined with

the 16-bit displacement, and then stores the value of the bit that was specified by bitpos to be set

to “1”. The displacement is sign-extended before the address calculation. bitpos becomes 0 to 7;

MSB becomes 0 and LSB becomes 7. The memory is accessed in bytes. The LOCK bit is on

while the BSET instruction is executed, and is cleared when the execution is completed. The

LOCK bit is internal to the CPU and cannot be directly read or written to by the user.

Condition bit C remains unchanged.

The LOCK bit is internal to the CPU and is the control bit for receiving all bus right requests

from circuits other than the CPU.

Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to

the type of MCU.

[EIT occurrence]

None

[Encoding]

bitpos

1010

0110 src

disp16

BSET #bitpos,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

bit operation Instructions

Bit test

BTST

[M32R-FPU Extended Instruction]

[Mnemonic]

BTST #bitpos,Rsrc

[Function]

Remove the bit specified by the register.

C = Rsrc >> ( 7-bitpos ) ) &1;

[Description]

Take out the bit specified as bitpos within the Rsrc lower eight bits and sets it in the condition

bit (C). bitpos becomes 0 to 7, MSB becomes 0 and LSB becomes 7.

[EIT occurrence]

None

[Encoding]

bitpos

BTST #bitpos,Rsrc

0000

1111 src

3-28

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INSTRUCTIONS

3.2 Instruction description

bit operation Instructions

Clear PSW

CLRPSW

[M32R-FPU Extended Instruction]

[Mnemonic]

CLRPSW #imm8

[Function]

Set the undefined SM, IE, and C bits of PSW to 0.

PSW& = ~imm8 : 0xffffff00

[Description]

Set the AND result s of the reverse value of b0 (MSB), b1, and b7 (LSB) of the 8-bit immediate

value and bits SM, IE, and C of PSW to the corresponding SM, IE, and C bits. When b7 (LSB) or

#imm8 is 1, the condition bit (C) goes to 0. All other bits remain unchanged.

[EIT occurrence]

None

[Encoding]

imm8

0111 0010

CLRPSW #imm8

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INSTRUCTIONS

3.2 Instruction description

compare instruction

CMP

Compare

[Mnemonic]

CMP Rsrc1,Rsrc2

[Function]

Compare

C = ( ( signed ) Rsrc1 < ( signed ) Rsrc2 ) ? 1:0;

[Description]

The condition bit (C) is set to 1 when Rsrc1 is less than Rsrc2. The operands are treated as

signed 32-bit values.

[EIT occurrence]

None

[Encoding]

0000 src1 0100 src2 CMP Rsrc1,Rsrc2

3-30

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INSTRUCTIONS

3.2 Instruction description

compare instruction

CMPI

Compare immediate

[Mnemonic]

CMPI Rsrc,#imm16

[Function]

Compare

C = ( ( signed ) Rsrc < ( signed short ) imm16 ) ? 1:0;

[Description]

The condition bit (C) is set when Rsrc is less than 16-bit immediate value. The operands are

treated as signed 32-bit values. The immediate value is sign-extended to 32-bit before the opera-

tion.

[EIT occurrence]

None

[Encoding]

1000 0000 0100 src

CMPI Rsrc,#imm16

imm16

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INSTRUCTIONS

3.2 Instruction description

compare instruction

CMPU

Compare unsigned

[Mnemonic]

CMPU Rsrc1,Rsrc2

[Function]

Compare

C = ( ( unsigned ) Rsrc1 < ( unsigned ) Rsrc2 ) ? 1:0;

[Description]

The condition bit (C) is set when Rsrc1 is less than Rsrc2. The operands are treated as un-

signed 32-bit values.

[EIT occurrence]

None

[Encoding]

0000 src1 0101 src2 CMPU Rsrc1,Rsrc2

3-32

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INSTRUCTIONS

3.2 Instruction description

compare instruction

CMPUI

Compare unsigned immediate

[Mnemonic]

CMPUI Rsrc,#imm16

[Function]

Compare

C = ( ( unsigned ) Rsrc < ( unsigned ) ( ( signed short ) imm16 ) ) ? 1:0;

[Description]

The condition bit (C) is set when Rsrc is less than the 16-bit immediate value. The operands

are treated as unsigned 32-bit values. The immediate value is sign-extended to 32-bit before the

operation.

[EIT occurrence]

None

[Encoding]

1000 0000 0101 src

CMPUI Rsrc,#imm16

imm16

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INSTRUCTIONS

3.2 Instruction description

multiply and divide instruction

DIV

Divide

[Mnemonic]

DIV Rdest,Rsrc

[Function]

Signed division

Rdest = ( signed ) Rdest / ( signed ) Rsrc;

[Description]

DIV divides Rdest by Rsrc and puts the quotient in Rdest.

The operands are treated as signed 32-bit values and the result is rounded toward zero.

The condition bit (C) is unchanged.

When Rsrc is zero, Rdest is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 0000 src 0000 0000 0000 0000

DIV Rdest,Rsrc

3-34

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INSTRUCTIONS

3.2 Instruction description

multiply and divide instruction

DIVU

Divide unsigned

[Mnemonic]

DIVU Rdest,Rsrc

[Function]

Unsigned division

Rdest = ( unsigned ) Rdest / ( unsigned ) Rsrc;

[Description]

DIVU divides Rdest by Rsrc and puts the quotient in Rdest.

The operands are treated as unsigned 32-bit values and the result is rounded toward zero.

The condition bit (C) is unchanged.

When Rsrc is zero, Rdest is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 0001 src 0000 0000 0000 0000

DIVU Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Floating-point add

FADD

[M32R-FPU Extended Instruction]

[Mnemonic]

FADD Rdest,Rsrc1,Rsrc2

[Function]

Floating-point add

Rdest = Rsrc1 + Rsrc2 ;

[Description]

Add the floating-point single precision values stored in Rsrc1 and Rsrc2 and store the result in

Rdest. The result is rounded according to the RM field of FPSR. The DN bit of FPSR handles the

modification of denormalized numbers. The condition bit (C) remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Overflow (OVF)

• Underflow (UDF)

• Inexact Exception (IXCT)

[Encoding]

1101 src1 0000 src2 0000 dest 0000 0000

FADD Rdest,Rsrc1,Rsrc2

3-36

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point addd

FADD

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN = 0

Rsrc2

Normalized

Number

Denormalized

Number

-0

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

add

-0

(Note)

-0

-Infinity

(Note)

IVLD

+Infinity

-Infinity

+Infinity

IVLD

Rsrc1

-Infinity

Denormalized

Number

UIPL

QNaN

SNaN

QNaN

IVLD

DN = 1

Rsrc2

Normalized

Number

Denormalized

Number

Denormalized

Number

-0, -

+0, +

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

Normalized Number

Denormalized

add

+0, +

(Note)

-0

-Infinity

Number

Normalized

Number

Denormalized

-0, -

(Note)

Number

Rsrc1

IVLD

+Infinity

-Infinity

QNaN

SNaN

+Infinity

IVLD

-Infinity

QNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point compare

FCMP

[M32R-FPU Extended Instruction]

[Mnemonic]

FCMP Rdest,Rsrc1,Rsrc2

[Function]

Floating-point compare

Rdest = (comparison results of Rsrc1 and Rsrc2);

When at least one value, either Rsrc1 or Rsrc2, is SNaN, a floating-point exception (other than

Invalid Operation Exception) occurs.

[Description]

Compare the floating-point single precision values stored in Rsrc1 and Rsrc2 and store the

result in Rdest. The results of the comparison can be determined y the following methods.

Typical instructions used to

Rdest

Comparison Results

determine comparison results

b0=0

All bits, b1 to b31, are 0.

Rsrc1=Rsrc2

beqz Rdest, LABEL

bgtz Rdest, LABEL

b1 to b9=111 1111 11,

Comparison invalid

Bits b10 to b31 are an undefined.

All others

Rsrc1>Rsrc2

Rsrc1<Rsrc2

b0=1

Bits b1 to b31 are an undefined.

bltz Rdest, LABEL

The DN bit of FPSR handles the conversion of denormalized numbers. The condition bit (C)

remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

[Encoding]

1101 src1 0000 src2 0000 dest 1100 0000

FCMP Rdest,Rsrc1,Rsrc2

3-38

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point compare

FCMP

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN = 0

Rsrc2

+Infinity

Normalized

Number

Denormalized

Number

-0

-Infinity

QNaN

SNaN

Normalized

Number

comparison

-0

-Infinity

00000000

+Infinity

-Infinity

+Infinity

-Infinity

00000000

Rsrc1

00000000

Denormalized

Number

UIPL

comparison

invalid

QNaN

SNaN

IVLD

SNaN

DN = 1

Rsrc2

Denormalized

Number

Denormalized

-0, -

Number

Normalized

Number

+0, +

+Infinity

-Infinity

+Infinity

QNaN

Normalized Number

Denormalized

comparison

-Infinity

+0, +

Number

00000000

Denormalized

-0, -

Number

+Infinity

-Infinity

00000000

Rsrc1

+Infinity

-Infinity

QNaN

SNaN

00000000

comparison

invalid

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

FCMPE

Floating-point compare with exception

if unordered

[M32R-FPU Extended Instruction]

[Mnemonic]

FCMPE Rdest,Rsrc1,Rsrc2

[Function]

Floating-point compare

Rdest = (comparison results of Rsrc1 and Rsrc2);

When at least one value, either Rsrc1 or Rsrc2, is QNaN or SNaN, a floating-point exception

(other than Invalid Operation Exception) occurs.

[Description]

Compare the floating-point single precision values stored in Rsrc1 and Rsrc2 and store the

result in Rdest. The results of the comparison can be determined y the following methods.

Typical instructions used to

Rdest

Comparison Results

determine comparison results

b0=0

All bits, b1 to b31, are 0.

b1 to b9=111 1111 11,

Rsrc1=Rsrc2

beqz Rdest, LABEL

bgtz Rdest, LABEL

Comparison invalid

Bits b10 to b31 are an undefined.

(Note)

All others

Rsrc1>Rsrc2

Rsrc1<Rsrc2

b0=1

Bits b1 to b31 are an undefined.

bltz Rdest, LABEL

Note: Only when EV bit (b21 of FPSR Register) = “0”.

The DN bit of FPSR handles the conversion of denormalized numbers. The condition bit (C)

remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

[Encoding]

1101 src1 0000 src2 0000 dest 1101 0000

FCMPE Rdest,Rsrc1,Rsrc2

3-40

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point compare with exception

if unordered

FCMPE

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN = 0

Rsrc2

+Infinity

Normalized

Number

Denormalized

Number

-0

-Infinity

QNaN

SNaN

Normalized

Number

comparison

-0

-Infinity

00000000

+Infinity

-Infinity

+Infinity

-Infinity

00000000

Rsrc1

00000000

Denormalized

Number

UIPL

QNaN

SNaN

IVLD

DN = 1

Rsrc2

Denormalized

Number

Denormalized

-0, -

Number

Normalized

Number

+0, +

+Infinity

-Infinity

+Infinity

QNaN

SNaN

Normalized Number

comparison

Denormalized

+0, +

-Infinity

Number

00000000

Denormalized

Number

-0, -

Rsrc1

00000000

+Infinity

-Infinity

QNaN

SNaN

+Infinity

-Infinity

00000000

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Floating-point divide

FDIV

[M32R-FPU Extended Instruction]

[Mnemonic]

FDIV Rdest,Rsrc1,Rsrc2

[Function]

Floating-point divide

Rdest = Rsrc1 / Rsrc2 ;

[Description]

Divide the floating-point single precision value stored in Rsrc1 by the floating-point single pre-

cision value stored in Rsrc1 and store the result in Rdest. The result is rounded according to the

RM field of FPSR. The DN bit of FPSR handles the modification of denormalized numbers. The

condition bit (C) remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Overflow (OVF)

• Underflow (UDF)

• Inexact Exception (IXCT)

• Zero Divide Exception (DIV0)

[Encoding]

1101 src1 0000 src2 0010 dest 0000 0000

FDIV Rdest,Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point divide

FDIV

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN = 0

Rsrc2

+Infinity -Infinity

Denormalized

Number

Normalized

Number

-0

QNaN

SNaN

Normalized

Number

divide

DIV0

IVLD

-0

+Infinity

-Infinity

+Infinity

-Infinity

+Infinity

Rsrc1

Infinity

IVLD

Denormalized

Number

UIPL

QNaN

SNaN

QNaN

IVLD

DN = 1

Rsrc2

Denormalized

Number

Denormalized

-0, -

Number

Normalized

Number

+0, +

+Infinity

-Infinity

QNaN

SNaN

Normalized Number

divide

DIV0

Denormalized

+0, +

-0

Number

IVLD

Denormalized

-0, -

Number

+Infinity

-Infinity

+Infinity

-Infinity

QNaN

SNaN

Rsrc1

Infinity

IVLD

QNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

DIV0: Zero Divide Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

FMADD

Floating-point multiply and add

[M32R-FPU Extended Instruction]

[Mnemonic]

FMADD Rdest,Rsrc1,Rsrc2

[Function]

Floating-point multiply and add

Rdest = Rdest + Rsrc1 * Rsrc2 ;

[Description]

This instruction is executed in the following 2 steps.

ꢀꢀStep 1

Multiply the floating-point single precision value stored in Rsrc1 by the floating-point single

precision value stored in Rsrc2.

The multiplication result is rounded toward 0 regardless of the value in the RM field of FPSR.

ꢀꢀStep 2

Add the result of Step 1 (the rounded value) and the floating-point single precision value stored

in Rdest. The result is rounded according to the RM field of FPSR.

The result of this operation is stored in Rdest. Exceptions are determined in both Step 1 and

Step 2. The DN bit of FPSR handles the conversion of denormalized numbers. The condition bit

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Overflow (OVF)

• Underflow (UDF)

• Inexact Exception (IXCT)

[Encoding]

1101 src1 0000 src2 0011 dest 0000 0000

FMADD Rdest,Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

FMADD

Floating-point multiply and add

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1, Rsrc2 and Rdest and the operation results when DN

= 0 and DN = 1.

DN=0

Value after Multiplication Operation

Rsrc2

Normalized

Number

Denormalized

Number

-0

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

Multiplication

Infinity

-0

IVLD

+Infinity

-Infinity

+Infinity

-Infinity

+Infinity

Rsrc1

Infinity

IVLD

Denormalized

Number

UIPL

QNaN

SNaN

QNaN

IVLD

Value after Addition Operation

Value after Multiplication Operation

Normalized

Number

-0

+Infinity

-Infinity

QNaN

Normalized

Number

add

(Note)

-0

-Infinity

-0

(Note)

+Infinity

-Infinity

+Infinity

IVLD

Rdest

-Infinity

Denormalized

Number

UIPL

QNaN

SNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

FMADD

Floating-point multiply and add

[M32R-FPU Extended Instruction]

DN=1

Value after Multiplication Operation

Rsrc2

Normalized

Number

Denormalized

Number

Denormalized

Number

+0, +

-0, -

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

Multiplication

Infinity

Denormalized

Number

Denormalized

Number

+0, +

-0, -

-0

IVLD

-Infinity

Rsrc1

+Infinity

-Infinity

QNaN

SNaN

+Infinity

-Infinity

Infinity

IVLD

+Infinity

QNaN

IVLD

Value after Addition Operation

Value after Multiplication Operation

Normalized

Number

-0

+Infinity

-Infinity

QNaN

Normalized

Number

Multiplication

(Note)

-0

-Infinity

-0

(Note)

Rdest

+Infinity

-Infinity

QNaN

SNaN

+Infinity

IVLD

-Infinity

QNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

FMSUB

Floating-point multiply and subtract

[M32R-FPU Extended Instruction]

[Mnemonic]

FMSUB Rdest,Rsrc1,Rsrc2

[Function]

Floating-point multiply and subtract

Rdest = Rdest - Rsrc1 * Rsrc2 ;

[Description]

This instruction is executed in the following 2 steps.

ꢀꢀStep 1

Multiply the floating-point single precision value stored in Rsrc1 by the floating-point single

precision value stored in Rsrc2.

The multiplication result is rounded toward 0 regardless of the value in the RM field of FPSR.

ꢀꢀStep 2

Subtract the result (rounded value) of Step 1 from the floating-point single precision value

stored in Rdest.

The subtraction result is rounded according to the RM field of FPSR.

The result of this operation is stored in Rdest. Exceptions are determined in both Step 1 and

Step 2. The DN bit of FPSR handles the conversion of denormalized numbers. The condition bit

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Overflow (OVF)

• Underflow (UDF)

• Inexact Exception (IXCT)

[Encoding]

1101 src1 0000 src2 0011 dest 0100 0000

FMSUB Rdest,Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

FMSUB

Floating-point multiply and subtract

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1, Rsrc2 and Rdest and the operation results when DN

= 0 and DN = 1.

DN=0

Value after Multiplication Operation

Rsrc2

Normalized

Number

Denormalized

Number

-0

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

Multiplication

Infinity

-0

IVLD

+Infinity

-Infinity

+Infinity

-Infinity

+Infinity

Rsrc1

Infinity

IVLD

Denormalized

Number

UIPL

QNaN

SNaN

QNaN

IVLD

Value after Subtraction Operation

Value after Multiplication Operation

Normalized

Number

-0

+Infinity

-Infinity

QNaN

Normalized

Number

Subtraction

(Note)

-0

-Infinity

-0

(Note)

+Infinity

-Infinity

+Infinity

IVLD

Rdest

-Infinity

Denormalized

Number

UIPL

QNaN

SNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

3-48

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

FMSUB

Floating-point multiply and subtract

[M32R-FPU Extended Instruction]

DN=1

Value after Multiplication Operation

Rsrc2

Normalized

Number

Denormalized

Number

Denormalized

Number

+0, +

-0, -

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

Multiplication

Infinity

Denormalized

+0, +

-0

Number

IVLD

-Infinity

Denormalized

Number

-0, -

Rsrc1

+Infinity

-Infinity

QNaN

SNaN

+Infinity

-Infinity

Infinity

IVLD

+Infinity

QNaN

IVLD

Value after Subtraction Operation

Value after Multiplication Operation

Normalized

Number

-0

+Infinity

-Infinity

QNaN

Normalized

Number

Subtraction

-Infinity

+Infinity

(Note)

-0

(Note)

Rdest

+Infinity

-Infinity

QNaN

SNaN

+Infinity

IVLD

-Infinity

IVLD

QNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Floating-point multiply

FMUL

[M32R-FPU Extended Instruction]

[Mnemonic]

FMUL Rdest,Rsrc1,Rsrc2

[Function]

Floating-point multiply

Rdest = Rsrc1 * Rsrc2 ;

[Description]

Multiply the floating-point single precision value stored in Rsrc1 by the floating-point single

precision value stored in Rsrc2 and store the results in Rdest. The result is rounded according to

the RM field of FPSR. The DN bit of FPSR handles the modification of denormalized numbers.

The condition bit (C) remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Overflow (OVF)

• Underflow (UDF)

• Inexact Exception (IXCT)

[Encoding]

1101 src1 0000 src2 0001 dest 0000 0000

FMUL Rdest,Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point multiply

FMUL

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN=0

Rsrc2

+Infinity -Infinity

Normalized

Number

Denormalized

Number

-0

QNaN

SNaN

Normalized

Number

Multiplication

Infinity

-0

IVLD

+Infinity

-Infinity

+Infinity

-Infinity

+Infinity

Rsrc1

Infinity

IVLD

Denormalized

Number

UIPL

QNaN

SNaN

QNaN

IVLD

DN=1

Rsrc2

Normalized

Number

Denormalized

Number

Denormalized

Number

+0, +

-0, -

+Infinity

-Infinity

QNaN

SNaN

Normalized

Number

Multiplication

Infinity

Denormalized

+0, +

-0

Number

IVLD

Denormalized

Number

-0, -

Rsrc1

+Infinity

-Infinity

QNaN

SNaN

+Infinity

-Infinity

+Infinity

Infinity

IVLD

QNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Floating-point subtract

FSUB

[M32R-FPU Extended Instruction]

[Mnemonic]

FSUB Rdest,Rsrc1,Rsrc2

[Function]

Floating-point subtract

Rdest = Rsrc1 - Rsrc2 ;

[Description]

Subtract the floating-point single precision value stored in Rsrc2 from the floating-point single

precision value stored in Rsrc1 and store the results in Rdest. The result is rounded according to

the RM field of FPSR. The DN bit of FPSR handles the modification of denormalized numbers.

The condition bit (C) remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Overflow (OVF)

• Underflow (UDF)

• Inexact Exception (IXCT)

[Encoding]

1101 src1 0000 src2 0000 dest 0100 0000

FSUB Rdest,Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Floating-point subtract

FSUB

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and

DN = 1.

DN = 0

Rsrc2

-Infinity

Normalized

Number

Denormalized

Number

-0

+Infinity

-Infinity

IVLD

QNaN

SNaN

Normalized

Number

Subtraction

+Infinity

IVLD

-0

(Note)

-0

(Note)

+Infinity

-Infinity

Rsrc1

-Infinity

Denormalized

Number

UIPL

QNaN

SNaN

QNaN

IVLD

DN = 1

Rsrc2

Normalized

Number

Denormalized

Number

Denormalized

Number

-0, -

+0, +

+Infinity

-Infinity

QNaN

SNaN

Normalized Number

Subtraction

Denormalized

+0, +

(Note)

-0

-Infinity

IVLD

Number

+Infinity

IVLD

Denormalized

-0, -

(Note)

Number

Rsrc1

+Infinity

-Infinity

QNaN

SNaN

-Infinity

QNaN

IVLD

IVLD: Invalid Operation Exception

UIPL: Unimplemented Exception

NaN: Not a Number

SNaN: Signaling NaN

QNaN: Quiet NaN

Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding

toward any other direction.

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Float to Integer

FTOI

[M32R-FPU Extended Instruction]

[Mnemonic]

FTOI Rdest,Rsrc

[Function]

Convert the floating-point single precision value to 32-bit integer.

Rdest = (signed int) Rsrc ;

[Description]

Convert the floating-point single precision value stored in Rsrc to a 32-bit integer and store the

result in Rdest.

The result is rounded toward 0 regardless of the value in the RM field of FPSR. The condition

bit (C) remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Inexact Exception (IXCT)

[Encoding]

1101 src 0000 0000 0100 dest 1000 0000

FTOI Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Float to Integer

FTOI

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The results of the FTOI instruction executed based on the Rsrc value, both when DN = 0 and DN = 1,

are shown in below.

DN = 0

Rsrc Value (exponent with no bias)

Rdest

Exception

Rsrc ≥ 0

Rsrc < 0

NaN

+Infinity

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'7FFF FFFF

127 ≥ exp ≥ 31

30 ≥ exp ≥ -126

+Denormalized value

H'0000 0000 to H'7FFF FF80 No change (Note 1)

No change

Unimplemented Exception

No change

H'0000 0000

-0

-Denormalized value

30 ≥ exp ≥ -126

127 ≥ exp ≥ 31

-Infinity

No change

Unimplemented Exception

No change (Note 1)

H'0000 0000 to H'8000 0080

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'8000 0080 (Note 2)

QNaN

When EIT occurs: no change Invalid Operation Exception

Other EIT:

SNaN

Signed bit = 0:H’7FFF FFFF

Signed bit = 1:H’8000 0000

Note 1: Inexact Exception occurs when rounding is performed.

2: Inexact Exception does not occur when Rsrc = H’CF00 0000.

DN = 1

Rsrc Value (exponent with no bias)

Rdest

Exception

Rsrc ≥ 0

Rsrc < 0

NaN

+Infinity

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'7FFF FFFF

127 ≥ exp ≥ 31

30 ≥ exp ≥ -126

+0, +Denormalized value

-0, -Denormalized value

30 ≥ exp ≥ -126

127 ≥ exp ≥ 31

-Infinity

H'0000 0000 to H'7FFF FF80 No change (Note 1)

H'0000 0000

No change

H'0000 0000 to H'8000 0080

No change (Note 1)

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'8000 0000 (Note 2)

QNaN

When EIT occurs: no change Invalid Operation Exception

Other EIT:

SNaN

Signed bit = 0:H’7FFF FFFF

Signed bit = 1:H’8000 0000

Note 1: Inexact Exception occurs when rounding is performed.

2: Inexact Exception does not occur when Rsrc = H’CF00 0000.

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Float to short

FTOS

[M32R-FPU Extended Instruction]

[Mnemonic]

FTOS Rdest,Rsrc

[Function]

Convert the floating-point single precision value to 16-bit integer.

Rdest = (signed int) Rsrc ;

[Description]

Convert the floating-point single precision value stored in Rsrc to a 16-bit integer and store the

result in Rdest.

The result is rounded toward 0 regardless of the value in the RM field of FPSR. The condition

bit (C) remains unchanged.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Unimplemented Operation Exception (UIPL)

• Invalid Operation Exception (IVLD)

• Inexact Exception (IXCT)

[Encoding]

1101 src 0000 0000 0100 dest 1100 0000

FTOS Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

floating point Instructions

Float to short

FTOS

[M32R-FPU Extended Instruction]

[Supplemental Operation Description]

The results of the FTOS instruction executed based on the Rsrc value, both when DN = 0 and DN = 1,

are shown in below.

DN = 0

Rsrc Value (exponent with no bias)

Rdest

Exception

Rsrc ≥ 0

Rsrc < 0

NaN

+Infinity

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'0000 7FFFF

127 ≥ exp ≥ 15

14 ≥ exp ≥ -126

+Denormalized value

H'0000 0000 to H'0000 7FFF No change (Note 1)

No change

Unimplemented Exception

No change

H'0000 0000

-0

-Denormalized value

14 ≥ exp ≥ -126

127 ≥ exp ≥ 15

-Infinity

No change

Unimplemented Exception

H'0000 0000 to H'FFFF 8001 No change (Note 1)

When EIT occurs: no change Invalid Operation Exception

Other EIT: H’FFFF 8000

(Note 2)

QNaN

When EIT occurs: no change Invalid Operation Exception

Other EIT:

SNaN

Signed bit = 0:H’0000 7FFF

Signed bit = 1:H’FFFF 8000

Note 1: Inexact Exception occurs when rounding is performed.

2: Inexact Exception does not occur when Rsrc = H’CF00 0000.

DN = 1

Rsrc Value (exponent with no bias)

Rdest

Exception

Rsrc ≥ 0

Rsrc < 0

NaN

+Infinity

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'0000 7FFF

127 ≥ exp ≥ 15

14 ≥ exp ≥ -126

+0, +Denormalized value

-0, -Denormalized value

14 ≥ exp ≥ -126

127 ≥ exp ≥ 15

-Infinity

H'0000 0000 to H'0000 7FFF No change (Note 1)

H'0000 0000

No change

H'0000 0000 to H'FFFF 8001 No change (Note 1)

When EIT occurs: no change Invalid Operation Exception

Other EIT: H'FFFF 8000

(Note 2)

QNaN

When EIT occurs: no change Invalid Operation Exception

Other EIT:

SNaN

Signed bit = 0:H’0000 7FFF

Signed bit = 1:H’FFFF 8000

Note 1: Inexact Exception occurs when rounding is performed.

2: No Exceptions occur when Rsrc = H’C700 0000. When Rsrc = H’C700 0001 to H’C700 00FF,

the Inexact Exception occurs and the Invalid Operation Exception does not occur.

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INSTRUCTIONS

3.2 Instruction description

floating-point Instructions

Integer to float

ITOF

[M32R-FPU Extended Instruction]

[Mnemonic]

ITOF Rdest,Rsrc

[Function]

Convert the integer to a floating-point single precision value.

Rdes = (float) Rsrc ;

[Description]

Converts the 32-bit integer stored in Rsrc to a floating-point single precision value and stores

the result in Rdest. The result is rounded according to the RM field of FPSR. The condition bit (C)

remains unchanged. H’0000 0000 is handled as “+0” regardless of the Rounding Mode.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Inexact Exception (IXCT)

[Encoding]

1101 src 0000 0000 0100 dest 0000 0000

ITOF Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

branch instruction

Jump and link

[Mnemonic]

JL Rsrc

[Function]

Subroutine call (register direct)

R14 = ( PC & 0xfffffffc ) + 4;

PC = Rsrc & 0xfffffffc;

[Description]

JL causes an unconditional jump to the address specified by Rsrc and puts the return address

in R14.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 1110 1100 src

JL Rsrc

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INSTRUCTIONS

3.2 Instruction description

branch instruction

JMP

Jump

[Mnemonic]

JMP Rsrc

[Function]

Jump

PC = Rsrc & 0xfffffffc;

[Description]

JMP causes an unconditional jump to the address specified by Rsrc.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 1111 1100 src

JMP Rsrc

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

Load

[Mnemonic]

(1) LD Rdest,@Rsrc

(2) LD Rdest,@Rsrc+

(3) LD Rdest,@(disp16,Rsrc)

[Function]

Load to register from the contents of the memory.

(1) Rdest = *( int *) Rsrc;

(2) Rdest = *( int *) Rsrc, Rsrc += 4;

(3) Rdest = *( int *) ( Rsrc + ( signed short ) disp16 );

[Description]

(1) The contents of the memory at the address specified by Rsrc are loaded into Rdest.

(2) The contents of the memory at the address specified by Rsrc are loaded into Rdest.

Rsrc is post incremented by 4.

(3) The contents of the memory at the address specified by Rsrc combined with the 16-

bit displacement are loaded into Rdest.

The displacement value is sign-extended to 32 bits before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

Address exception (AE)

[Encoding]

0010 dest 1100 src

LD Rdest,@Rsrc

LD Rdest,@Rsrc+

disp16

0010 dest

1010 dest

1110 src

1100 src

LD Rdest,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

LD24

Load 24-bit immediate

[Mnemonic]

LD24 Rdest,#imm24

[Function]

Load the 24-bit immediate value into register.

Rdest = imm24 & 0x00ffffff;

[Description]

LD24 loads the 24-bit immediate value into Rdest. The immediate value is zero-extended to 32

bits.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

imm24

1110 dest

LD24 Rdest,#imm24

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

LDB

Load byte

[Mnemonic]

(1) LDB Rdest,@Rsrc

(2) LDB Rdest,@(disp16,Rsrc)

[Function]

Load to register from the contents of the memory.

(1) Rdest = *( signed char *) Rsrc;

(2) Rdest = *( signed char *) ( Rsrc + ( signed short ) disp16 );

[Description]

(1) LDB sign-extends the byte data of the memory at the address specified by Rsrc and loads

it into Rdest.

(2) LDB sign-extends the byte data of the memory at the address specified by Rsrc combined

with the 16-bit displacement, and loads it into Rdest.

The displacement value is sign-extended to 32 bits before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0010 dest

1010 dest

1000 src

LDB Rdest,@Rsrc

disp16

LDB Rdest,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

LDH

Load halfword

[Mnemonic]

(1) LDH Rdest,@Rsrc

(2) LDH Rdest,@(disp16,Rsrc)

[Function]

Load to register from the contents of the memory.

(1) Rdest = *( signed short *) Rsrc;

(2) Rdest = *( signed short *) ( Rsrc + ( signed short ) disp16 );

[Description]

(1) LDH sign-extends the halfword data of the memory at the address specified by Rsrc and

loads it into Rdest.

(2) LDH sign-extends the halfword data of the memory at the address specified by Rsrc

combined with the 16-bit displacement, and loads it into Rdest.

The displacement value is sign-extended to 32 bits before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

Address exception (AE)

[Encoding]

0010 dest

1010 dest

1010 src

LDH Rdest,@Rsrc

disp16

LDH Rdest,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

transfer instruction

LDI

Load immediate

[Mnemonic]

(1) LDI Rdest,#imm8

(2) LDI Rdest,#imm16

[Function]

Load the immediate value into register.

(1) Rdest = ( signed char ) imm8;

(2) Rdest = ( signed short ) imm16;

[Description]

(1) LDI loads the 8-bit immediate value into Rdest.

The immediate value is sign-extended to 32 bits.

(2) LDI loads the 16-bit immediate value into Rdest.

The immediate value is sign-extended to 32 bits.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0110 dest imm8

1001 dest

LDI Rdest,#imm8

imm16

1111 0000

LDI Rdest,#imm16

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

LDUB

Load unsigned byte

[Mnemonic]

(1) LDUB Rdest,@Rsrc

(2) LDUB Rdest,@(disp16,Rsrc)

[Function]

Load to register from the contents of the memory.

(1) Rdest = *( unsigned char *) Rsrc;

(2) Rdest = *( unsigned char *) ( Rsrc + ( signed short ) disp16 );

[Description]

(1) LDUB zero-extends the byte data from the memory at the address specified by Rsrc and

loads it into Rdest.

(2) LDUB zero-extends the byte data of the memory at the address specified by Rsrc com-

bined

with the 16-bit displacement, and loads it into Rdest.

The displacement value is sign-extended to 32 bits before address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0010 dest

1001 src

LDUB Rdest,@Rsrc

disp16

1010 dest

LDUB Rdest,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

LDUH

Load unsigned halfword

[Mnemonic]

(1) LDUH Rdest,@Rsrc

(2) LDUH Rdest,@(disp16,Rsrc)

[Function]

Load to register from the contents of the memory.

(1) Rdest = *( unsigned short *) Rsrc;

(2) Rdest = *( unsigned short *) ( Rsrc + ( signed short ) disp16 );

[Description]

(1) LDUH zero-extends the halfword data from the memory at the address specified by Rsrc

and loads it into Rdest.

(2) LDUH zero-extends the halfword data in memory at the address specified by Rsrc com-

bined

with the 16-bit displacement, and loads it into Rdest.

The displacement value is sign-extended to 32 bits before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

Address exception (AE)

[Encoding]

0010 dest

1010 dest

1011 src

LDUH Rdest,@Rsrc

disp16

LDUH Rdest,@(disp16,Rsrc)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

LOCK

Load locked

[Mnemonic]

LOCK Rdest,@Rsrc

[Function]

Load locked

LOCK = 1, Rdest = *( int *) Rsrc;

[Description]

The contents of the word at the memory location specified by Rsrc are loaded into Rdest. The

condition bit (C) is unchanged.

This instruction sets the LOCK bit in addition to simple loading.

When the LOCK bit is 1, external bus master access is not accepted.

The LOCK bit is cleared by executing the UNLOCK instruction.

The LOCK bit is located in the CPU and operates based on the LOCK and UNLOCK instruc-

tions. The user cannot directly read or write to this bit.

The LOCK bit is internal to the CPU and is the control bit for receiving all bus right requests

from circuits other than the CPU.

Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to

the type of MCU.

[EIT occurrence]

Address exception (AE)

[Encoding]

0010 dest 1101 src

LOCK Rdest,@Rsrc

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

MACHI

Multiply-accumulate high-order halfwords

[Mnemonic]

MACHI Rsrc1,Rsrc2

[Function]

Multiply and add

accumulator += (( signed) (Rsrc1 & 0xffff0000) * (signed short) (Rsrc2 >> 16));

[Description]

MACHI multiplies the high-order 16 bits of Rsrc1 and the high-order 16 bits of Rsrc2, then adds

the result to the low-order 56 bits in the accumulator.

The LSB of the multiplication result is aligned with bit 47 in the accumulator, and the portion

corresponding to bits 8 through 15 of the accumulator is sign-extended before addition. The

result of the addition is stored in the accumulator. The high-order 16 bits of Rsrc1 and Rsrc2 are

treated as signed values.

The condition bit (C) is unchanged.

15 16

high-order 16 bits

Rsrc1

Rsrc2

high-order 16 bits

Sign extension

Result of the multiplication

Value in accumulator before the

execution of the MACHI instruction

Value in accumulator after the

execution of the MACHI instruction

Sign extension

7 8

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0100 src2 MACHI Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

MACLO _{Multiply-accumulate low-order halfwords}MACLO

[Mnemonic]

MACLO Rsrc1,Rsrc2

[Function]

Multiply and add

accumulator += ( ( signed ) ( Rsrc1 << 16 ) * ( signed short ) Rsrc2 ) ;

[Description]

MACLO multiplies the low-order 16 bits of Rsrc1 and the low-order 16 bits of Rsrc2, then adds

the result to the low order 56 bits in the accumulator.

The LSB of the multiplication result is aligned with bit 47 in the accumulator, and the portion

corresponding to bits 8 through 15 of the accumulator is sign-extended before addition. The

result of the addition is stored in the accumulator. The low-order 16 bits of Rsrc1 and Rsrc2 are

treated as signed values.

The condition bit (C) is unchanged.

15 16

low-order 16 bits

Rsrc1

Rsrc2

low-order 16 bits

Sign extension

Result of the multiplication

Value in accumulator before the

execution of the MACLO instruction

Value in accumulator after the

execution of the MACLO instruction

Sign extension

7 8

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0101 src2 MACLO Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Multiply-accumulate

MACWHI

word and high-order halfword

[Mnemonic]

MACWHI Rsrc1,Rsrc2

[Function]

Multiply and add

accumulator += ( ( signed ) Rsrc1 * ( signed short ) ( Rsrc2 >> 16 ) );

[Description]

MACWHI multiplies the 32 bits of Rsrc1 and the high-order 16 bits of Rsrc2, then adds the

result to the low-order 56 bits in the accumulator.

The LSB of the multiplication result is aligned with the LSB of the accumulator, and the portion

corresponding to bits 8 through 15 of the accumulator is sign extended before addition. The

result of addition is stored in the accumulator. The 32 bits of Rsrc1 and the high-order 16 bits of

Rsrc2 are treated as signed values.

The condition bit (C) is unchanged.

15 16

32 bits

Rsrc1

Rsrc2

high-order 16 bits

Sign extension

Result of the multiplication

Value in accumulator before the

execution of the MACWHI instruction

Value in accumulator after the

execution of the MACWHI instruction

Sign extension

7 8

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0110 src2 MACWHI Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Multiply-accumulate

MACWLO

word and low-order halfword

[Mnemonic]

MACWLO Rsrc1,Rsrc2

[Function]

Multiply and add

accumulator += ( ( signed ) Rsrc1 * ( signed short ) Rsrc2 ) ;

[Description]

MACWLO multiplies the 32 bits of Rsrc1 and the low-order 16 bits of Rsrc2, then adds the

result to the low-order 56 bits in the accumulator.

The LSB of the multiplication result is aligned with the LSB of the accumulator, and the portion

corresponding to bits 8 through 15 of the accumulator is sign-extended before the addition. The

result of the addition is stored in the accumulator. The 32 bits Rsrc1 and the low-order 16 bits of

Rsrc2 are treated as signed values.

The condition bit (C) is unchanged.

15 16

32 bits

Rsrc1

low-order 16 bits Rsrc2

Sign extension

Result of the multiplication

Value in accumulator before the

execution of the MACWLO instruction

Value in accumulator after the

execution of the MACWLO instruction

Sign extension

7 8

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0111 src2 MACWLO Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

multiply and divide instruction

MUL

Multiply

[Mnemonic]

MUL Rdest,Rsrc

[Function]

Multiply

{ signed64bit tmp;

tmp = ( signed64bit ) Rdest * ( signed64bit ) Rsrc;

Rdest = ( int ) tmp;}

[Description]

MUL multiplies Rdest by Rsrc and puts the result in Rdest.

The operands are treated as signed values.

The contents of the accumulator are destroyed by this instruction. The condition bit (C) is

unchanged.

[EIT occurrence]

None

[Encoding]

0001 dest 0110 src

MUL Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

MULHI

Multiply high-order halfwords

[Mnemonic]

MULHI Rsrc1,Rsrc2

[Function]

Multiply

accumulator = (( signed) (Rsrc1 & 0xffff000 ) * (signed short) (Rsrc2 >> 16));

[Description]

MULHI multiplies the high-order 16 bits of Rsrc1 and the high-order 16 bits of Rsrc2, and

stores the result in the accumulator.

However, the LSB of the multiplication result is aligned with bit 47 in the accumulator, and the

portion corresponding to bits 0 through 15 of the accumulator is sign-extended. Bits 48 through

63 of the accumulator are cleared to 0. The high-order 16 bits of Rsrc1 and Rsrc2 are treated as

signed values.

The condition bit (C) is unchanged.

15 16

high-order 16 bits

Rsrc1

Rsrc2

high-order 16 bits

Value in accumulator after the

execution of the MALHI instruction

Sign extension

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0000 src2 MULHI Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

MULLO

Multiply low-order halfwords

[Mnemonic]

MULLO Rsrc1,Rsrc2

[Function]

Multiply

accumulator = ( ( signed ) ( Rsrc1 << 16 ) * ( signed short ) Rsrc2 );

[Description]

MULLO multiplies the low-order 16 bits of Rsrc1 and the low-order 16 bits of Rsrc2, and stores

the result in the accumulator.

The LSB of the multiplication result is aligned with bit 47 in the accumulator, and the portion

corresponding to bits 0 through 15 of the accumulator is sign extended. Bits 48 through 63 of the

accumulator are cleared to 0. The low-order 16 bits of Rsrc1 and Rsrc2 are treated as signed

values.

The condition bit (C) is unchanged.

15 16

low-order 16 bits

Rsrc1

Rsrc2

low-order 16 bits

Value in accumulator after the

execution of the MULLO instruction

Sign extension

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0001 src2 MULLO Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Multiply

MULWHI

word and high-order halfword

[Mnemonic]

MULWHI Rsrc1,Rsrc2

[Function]

Multiply

accumulator = ( ( signed ) Rsrc1 * ( signed short ) ( Rsrc2 >> 16 ) );

[Description]

MULWHI multiplies the 32 bits of Rsrc1 and the high-order 16 bits of Rsrc2, and stores the

result in the accumulator.

The LSB of the multiplication result is aligned with the LSB of the accumulator, and the portion

corresponding to bits 0 through 15 of the accumulator is sign-extended. The 32 bits of Rsrc1 and

high-order 16 bits of Rsrc2 are treated as signed values.

The condition bit (C) is unchanged.

15 16

32 bits

Rsrc1

Rsrc2

high-order 16 bits

Value in accumulator after the

execution of the MULWHI instruction

Sign extension

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0010 src2 MULWHI Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

DSP fucntion instruction

Multiply

MULWLO

word and low-order halfword

[Mnemonic]

MULWLO Rsrc1,Rsrc2

[Function]

Multiply

accumulator = ( ( signed ) Rsrc1 * ( signed short ) Rsrc2 );

[Description]

MULWLO multiplies the 32 bits of Rsrc1 and the low-order 16 bits of Rsrc2, and stores the

result in the accumulator.

The LSB of the multiplication result is aligned with the LSB of the accumulator, and the portion

corresponding to bits 0 through 15 of the accumulator is sign extended. The 32 bits of Rsrc1 and

low-order 16 bits of Rsrc2 are treated as signed values.

The condition bit (C) is unchanged.

15 16

32 bits

Rsrc1

Rsrc2

low-order 16 bits

Value in accumulator after the

execution of the MULWLO instruction

Sign extension

15 16

31 32

47 48

[EIT occurrence]

None

[Encoding]

0011 src1 0011 src2 MULWLO Rsrc1,Rsrc2

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INSTRUCTIONS

3.2 Instruction description

transfer instruction

Move register

[Mnemonic]

MV Rdest,Rsrc

[Function]

Transfer

Rdest = Rsrc;

[Description]

MV moves Rsrc to Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 dest 1000 src

MV Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Move high-order word

from accumulator

MVFACHI

[Mnemonic]

MVFACHI Rdest

[Function]

Transfer from accumulator to register

Rdest = ( int ) ( accumulator >> 32 ) ;

[Description]

MVFACHI moves the high-order 32 bits of the accumulator to Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 dest 1111 0000 MVFACHI Rdest

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Move low-order word

from accumulator

MVFACLO

[Mnemonic]

MVFACLO Rdest

[Function]

Transfer from accumulator to register

Rdest = ( int ) accumulator

[Description]

MVFACLO moves the low-order 32 bits of the accumulator to Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 dest 1111 0001 MVFACLO Rdest

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Move middle-order word

from accumulator

MVFACMI

[Mnemonic]

MVFACMI Rdest

[Function]

Transfer from accumulator to register

Rdest = ( int ) ( accumulator >> 16 ) ;

[Description]

MVFACMI moves bits16 through 47 of the accumulator to Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 dest 1111 0010 MVFACMI Rdest

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INSTRUCTIONS

3.2 Instruction description

transfer instruction

MVFC

Move from control register

[Mnemonic]

MVFC Rdest,CRsrc

[Function]

Transfer from control register to register

Rdest = CRsrc ;

[Description]

MVFC moves CRsrc to Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 dest 1001 src

MVFC Rdest,CRsrc

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Move high-order word

to accumulator

MVTACHI

[Mnemonic]

MVTACHI Rsrc

[Function]

Transfer from register to accumulator

accumulator [ 0 : 31 ] = Rsrc ;

[Description]

MVTACHI moves Rsrc to the high-order 32 bits of the accumulator.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 src 0111 0000 MVTACHI Rsrc

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

Move low-order word

to accumulator

MVTACLO

[Mnemonic]

MVTACLO Rsrc

[Function]

Transfer from register to accumulator

accumulator [ 32 : 63 ] = Rsrc ;

[Description]

MVTACLO moves Rsrc to the low-order 32 bits of the accumulator.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 src 0111 0001 MVTACLO Rsrc

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INSTRUCTIONS

3.2 Instruction description

transfer instruction

MVTC

Move to control register

[Mnemonic]

MVTC Rsrc,CRdest

[Function]

Transfer from register to control register

CRdest = Rsrc ;

[Description]

MVTC moves Rsrc to CRdest.

If PSW(CR0) is specified as CRdest, the condition bit (C) is changed; otherwise it is un-

changed.

[EIT occurrence]

None

[Encoding]

0001 dest 1010 src

MVTC Rsrc,CRdest

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

NEG

Negate

[Mnemonic]

NEG Rdest,Rsrc

[Function]

Negate

Rdest = 0 – Rsrc ;

[Description]

NEG negates (changes the sign of) Rsrc treated as a signed 32-bit value, and puts the result

in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest 0011 src

NEG Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

branch instruction

NOP

No operation

[Mnemonic]

NOP

[Function]

No operation

/* */

[Description]

NOP performs no operation. The subsequent instruction then processed.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0111 0000 0000 0000 NOP

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INSTRUCTIONS

3.2 Instruction description

logic operation instruction

NOT

Logical NOT

[Mnemonic]

NOT Rdest,Rsrc

[Function]

Logical NOT

Rdest = ~ Rsrc ;

[Description]

NOT inverts each of the bits of Rsrc and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest 1011 src

NOT Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

logic operation instruction

[Mnemonic]

OR Rdest,Rsrc

[Function]

Logical OR

Rdest = Rdest | Rsrc ;

[Description]

OR computes the logical OR of the corresponding bits of Rdest and Rsrc, and puts the result

in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest 1110 src

OR Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

logic operation instruction

OR3

OR 3-operand

[Mnemonic]

OR3 Rdest,Rsrc,#imm16

[Function]

Logical OR

Rdest = Rsrc | ( unsigned short ) imm16 ;

[Description]

OR3 computes the logical OR of the corresponding bits of Rsrc and the 16-bit immediate

value, which is zero-extended to 32 bits, and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

imm16

1000 dest 1110 src

OR3 Rdest,Rsrc,#imm16

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

RAC

Round accumulator

[Mnemonic]

RAC

[Function]

Saturation Process

{ signed64bit tmp;

tmp = ( signed64bit ) accumulator << 1;

tmp = tmp + 0x0000 0000 0000 8000;

if( 0x0000 7fff ffff 0000 < tmp )

accumulator = 0x0000 7fff ffff 0000;

else if( tmp < 0xffff 8000 0000 0000 )

accumulator = 0xffff 8000 0000 0000;

else

accumulator = tmp & 0xffff ffff ffff 0000; }

[Description]

RAC rounds the contents in the accumulator to word size and stores the result in the accumu-

lator.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 0000 1001 0000 RAC

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

RAC

Round accumulator

[Supplement]

This instruction is executed in two steps as shown below:

1-bit shift to the left

supposed sign

extended bit0-bit7

47 48

The value in the accumulator is altered depending on the supposed bit 80 through 7 after

left-shift operation and bit 8 through bit 63 after shift operation.

Value in Adest after the

execution of the RAC instruction

0000

00 00

7FFF

FFFF

•

47 48

positive

value

0000 7FFF FFFF 8000

0000 7FFF FFFF 7FFF

•

if bit 48 is 0 , there is no carry.

if bit 48 is 1 , the bit is carried.

Bits 48 to 63 are cleared to zero.

0000 0000 0000 0000

•

FFFF 8000 0000 8000

FFFF 8000 0000 7FFF

negative

value

•

FF FF

8000

0000

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

RACH

Round accumulator halfword

[Mnemonic]

RACH

[Function]

Saturation Process

{ signed64bit tmp;

tmp = ( signed64bit ) accumulator << 1;

tmp = tmp + 0x0000 0000 8000 0000;

if( 0x0000 7fff 0000 0000 < tmp )

accumulator = 0x0000 7fff 0000 0000;

else if( tmp < 0xffff 8000 0000 0000 )

accumulator = 0xffff 8000 0000 0000;

else

accumulator = tmp & 0xffff ffff 0000 0000; }

[Description]

RACH rounds the contents in the accumulator to halfword size and stores the result in the

accumulator.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 0000 1000 0000 RACH

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INSTRUCTIONS

3.2 Instruction description

DSP function instruction

RACH

Round accumulator halfword

[Supplement]

This instruction is executed in two steps, as shown below.

1-bit shift to the left

supposed sign

extended bit0-bit7

47 48

The value in the accumulator is altered depending on the supposed bit 80 through 7 after

left-shift operation and bit 8 through bit 63 after shift operation.

Value in Adest after the

execution of the RAC instruction

0000

00 00

7FFF

FFFF

•

31 32

positive

value

0000 7FFE 8000 0000

0000 7FFE 7FFF 7FFF

•

if bit 32 is 0 , there is no carry.

if bit 32 is 1 , the bit is carried.

Bits 32 to 63 are cleared to zero.

0000 0000 0000 0000

•

sign extension

FFFF 8000 8000 0000

FFFF 8000 7FFF FFFF

negative

value

•

FF FF

8000

0000

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INSTRUCTIONS

3.2 Instruction description

multiply and divide instruction

REM

Remainder

[Mnemonic]

REM Rdest,Rsrc

[Function]

Signed remainder

Rdest = ( signed ) Rdest % ( signed ) Rsrc ;

[Description]

REM divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as

signed 32-bit values.

The quotient is rounded toward zero and the quotient takes the same sign as the dividend.

The condition bit (C) is unchanged.

When Rsrc is zero, Rdest is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 0010 src 0000 0000 0000 0000

REM Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

multiply and divide instruction

REMU

Remainder unsigned

[Mnemonic]

REMU Rdest,Rsrc

[Function]

Unsigned remainder

Rdest = ( unsigned ) Rdest % ( unsigned ) Rsrc ;

[Description]

REMU divides Rdest by Rsrc and puts the quotient in Rdest.

The operands are treated as unsigned 32-bit values.

The condition bit (C) is unchanged.

When Rsrc is zero, Rdest is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 0011 src 0000 0000 0000 0000

REMU Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

EIT-related instruction

RTE

Return from EIT

[Mnemonic]

RTE

[Function]

Return from EIT

SM = BSM ;

IE = BIE ;

C = BC ;

PC = BPC & 0xfffffffc ;

[Description]

RTE restores the SM, IE and C bits of the PSW from the BSM, BIE and BC bits, and jumps to

the address specified by BPC.

At this time, because the BSM, BIE, and BC bits in the PSW register are undefined, the BPC is

also undefined.

[EIT occurrence]

None

[Encoding]

0001 0000 1101 0110 RTE

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INSTRUCTIONS

3.2 Instruction description

Transfer instructions

SETH

Set high-order 16-bit

[Mnemonic]

SETH Rdest,#imm16

[Function]

Transfer instructions

Rdest = ( signed short ) imm16 << 16 ;

[Description]

SETH load the immediate value into the 16 most significant bits of Rdest.

The 16 least significant bits become zero.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1101 dest 1100 0000

SETH Rdest,#imm16

imm16

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INSTRUCTIONS

3.2 Instruction description

Bit Operation Instructions

Set PSW

SETPSW

[M32R-FPU Extended Instruction]

[Mnemonic]

SETPSW #imm8

[Function]

Set the undefined SM, IE, anc C bits of PSW to 1.

PSW : = imm8&0x000000ff

[Description]

Set the AND result of the value of b0 (MSB), b1, and b7 (LSB) of the 8-bit immediate value and

bits SM, IE, and C of PSW to the corresponding SM, IE, and C bits. When b7 (LSB) or #imm8 is

1, the condition bit (C) goes to 0. All other bits remain unchanged.

[EIT occurrence]

None

[Encoding]

imm8

0111 0001

SETPSW #imm8

[Note]

Set the 8-bit immediate values of b2 to b6 to “0”.

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SLL

Shift left logical

[Mnemonic]

SLL Rdest,Rsrc

[Function]

Logical left shift

Rdest = Rdest << ( Rsrc & 31 ) ;

[Description]

SLL left logical-shifts the contents of Rdest by the number specified by Rsrc, shifting zeroes

into the least significant bits.

Only the five least significant bits of Rsrc are used.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 dest 0100 src SLL Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SLL3

Shift left logical 3-operand

[Mnemonic]

SLL3 Rdest,Rsrc,#imm16

[Function]

Logical left shift

Rdest = Rsrc << ( imm16 & 31 ) ;

[Description]

SLL3 left logical-shifts the contents of Rsrc into Rdest by the number specified by the 16-bit

immediate value, shifting zeroes into the least significant bits.

Only the five least significant bits of the 16-bit immediate value are used.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 1100 src

imm16

SLL3 Rdest,Rsrc,#imm16

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SLLI

Shift left logical immediate

[Mnemonic]

SLLI Rdest,#imm5

[Function]

Logical left shift

Rdest = Rdest << imm5 ;

[Description]

SLLI left logical-shifts the contents of Rdest by the number specified by the 5-bit immediate

value, shifting zeroes into the least significant bits.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 dest 010 imm5 SLLI Rdest,#imm5

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SRA

Shift right arithmetic

[Mnemonic]

SRA Rdest,Rsrc

[Function]

Arithmetic right shift

Rdest = ( signed ) Rdest >> ( Rsrc & 31 ) ;

[Description]

SRA right arithmetic-shifts the contents of Rdest by the number specified by Rsrc, replicates

the sign bit in the MSB of Rdest and puts the result in Rdest.

Only the five least significant bits are used.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 dest 0010 src SRA Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SRA3

Shift right arithmetic 3-operand

[Mnemonic]

SRA3 Rdest,Rsrc,#imm16

[Function]

Arithmetic right shift

Rdest = ( signed ) Rsrc >> ( imm16 & 31 ) ;

[Description]

SRA3 right arithmetic-shifts the contents of Rsrc into Rdest by the number specified by the 16-

bit immediate value, replicates the sign bit in Rsrc and puts the result in Rdest.

Only the five least significant bits are used.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 1010 src

imm16

SRA3 Rdest,Rsrc,#imm16

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M32R-FPU Software Manual (Rev.1.01)

INSTRUCTIONS

3.2 Instruction description

shift instruction

SRAI

Shift right arithmetic immediate

[Mnemonic]

SRAI Rdest,#imm5

[Function]

Arithmetic right shift

Rdest = ( signed ) Rdest >> imm5 ;

[Description]

SRAI right arithmetic-shifts the contents of Rdest by the number specified by the 5-bit immedi-

ate value, replicates the sign bit in MSB of Rdest and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 dest 001 imm5 SRAI Rdest,#imm5

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SRL

Shift right logical

[Mnemonic]

SRL Rdest,Rsrc

[Function]

Logical right shift

Rdest = ( unsigned ) Rdest >> ( Rsrc & 31 ) ;

[Description]

SRL right logical-shifts the contents of Rdest by the number specified by Rsrc, shifts zeroes

into the most significant bits and puts the result in Rdest.

Only the five least significant bits of Rsrc are used.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0001 dest 0000 src SRL Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SRL3

Shift right logical 3-operand

[Mnemonic]

SRL3 Rdest,Rsrc,#imm16

[Function]

Logical right shift

Rdest = ( unsigned ) Rsrc >> ( imm16 & 31 ) ;

[Description]

SRL3 right logical-shifts the contents of Rsrc into Rdest by the number specified by the 16-bit

immediate value, shifts zeroes into the most significant bits. Only the five least significant bits of

the immediate value are valid.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1001 dest 1000 src

imm16

SRL3 Rdest,Rsrc,#imm16

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INSTRUCTIONS

3.2 Instruction description

shift instruction

SRLI

Shift right logical immediate

[Mnemonic]

SRLI Rdest,#imm5

[Function]

Logical right shift

Rdest = ( unsigned ) Rdest >> ( imm5 & 31 ) ;

[Description]

SRLI right arithmetic-shifts Rdest by the number specified by the 5-bit immediate value, shift-

ing zeroes into the most significant bits.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0101 dest 000 imm5 SRLI Rdest,#imm5

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

Store

[Mnemonic]

(1) ST Rsrc1,@Rsrc2

(2) ST Rsrc1,@+Rsrc2

(3) ST Rsrc1,@-Rsrc2

(4) ST Rsrc1,@(disp16,Rsrc2)

[Function]

Store

(1) * ( int *) Rsrc2 = Rsrc1;

(2) Rsrc2 += 4, * ( int *) Rsrc2 = Rsrc1;

(3) Rsrc2 -= 4, * ( int *) Rsrc2 = Rsrc1;

(4) * ( int *) ( Rsrc2 + ( signed short ) disp16 ) = Rsrc1;

[Description]

(1) ST stores Rsrc1 in the memory at the address specified by Rsrc2.

(2) ST increments Rsrc2 by 4 and stores Rsrc1 in the memory at the address specified by the

resultant Rsrc2.

(3) ST decrements Rsrc2 by 4 and stores the contents of Rsrc1 in the memory at the address

specified by the resultant Rsrc2.

(4) ST stores Rsrc1 in the memory at the address specified by Rsrc combined with the 16-bit

displacement. The displacement value is sign-extended before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

Address exception (AE)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

Store

[Encoding]

0010 src1

1010 src1

ST Rsrc1,@Rsrc2

ST Rsrc1,@+Rsrc2

ST Rsrc1,@-Rsrc2

disp16

0100 src2

0110 src2

0111 src2

0100 src2

ST Rsrc1,@(disp16,Rsrc2)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

STB

Store byte

[Mnemonic]

(1) STB Rsrc1,@Rsrc2

(2) STB Rsrc1,@(disp16,Rsrc2)

[Function]

Store

(1) * ( char *) Rsrc2 = Rsrc1;

(2) * ( char *) ( Rsrc2 + ( signed short ) disp16 ) = Rsrc1;

[Description]

(1) STB stores the least significant byte of Rsrc1 in the memory at the address specified by

Rsrc2.

(2) STB stores the least significant byte of Rsrc1 in the memory at the address specified by

Rsrc

combined with the 16-bit displacement.

The displacement value is sign-extended to 32 bits before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0010 src1

STB Rsrc1,@Rsrc2

disp16

0000 src2

1010 src1

STB Rsrc1,@(disp16,Rsrc2)

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INSTRUCTIONS

3.2 Instruction description

load/store instruction

Store halfword

STH

[M32R-FPU Extended Mnemonic]

[Mnemonic]

(1) STH Rsrc1,@Rsrc2

(2) STH Rsrc1,@Rsrc2+ [M32R-FPU Extended Mnemonic]

(3) STH Rsrc1,@(disp16,Rsrc2)

[Function]

Store

(1) * ( signed short *) Rsrc2 = Rsrc1;

(2) * ( signed short *) Rsrc2 = Rsrc1, Rsrc2 + = 2 ;

(3) * ( signed short *) ( Rsrc2 + ( signed short ) disp16 ) = Rsrc1;

[Description]

(1) STH stores the least significant halfword of Rsrc1 in the memory at the address specified

by Rsrc2.

(2) STH stores the LSB halfword of Rsrc1 to the memory of the address specified by Rsrc2,

and

then increments Rsrc2 by 2.

(3) STH stores the least significant halfword of Rsrc1 in the memory at the address specified

tended to 32

Rsrc combined with the 16-bit displacement. The displacement value is sign-ex-

bits before the address calculation.

The condition bit (C) is unchanged.

[EIT occurrence]

Address exception (AE)

[Encoding]

0010 src1

1010 src1

STH Rsrc1,@Rsrc2

STH Rsrc1,@Rsrc2+

disp16

0010 src2

0011 src2

0010 src2

STH Rsrc1,@(disp16,Rsrc2)

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M32R-FPU Software Manual (Rev.1.01)

INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

SUB

Subtract

[Mnemonic]

SUB Rdest,Rsrc

[Function]

Subtract

Rdest = Rdest - Rsrc;

[Description]

SUB subtracts Rsrc from Rdest and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest

SUB Rdest,Rsrc

0010 src

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

SUBV

Subtract with overflow checking

[Mnemonic]

SUBV Rdest,Rsrc

[Function]

Subtract

Rdest = Rdest - Rsrc;

C = overflow ? 1 : 0;

[Description]

SUBV subtracts Rsrc from Rdest and puts the result in Rdest.

The condition bit (C) is set when the subtraction results in overflow; otherwise, it is cleared.

[EIT occurrence]

None

[Encoding]

0000 dest

SUBV Rdest,Rsrc

0000 src

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INSTRUCTIONS

3.2 Instruction description

arithmetic operation instruction

SUBX

Subtract with borrow

[Mnemonic]

SUBX Rdest,Rsrc

[Function]

Subtract

Rdest = ( unsigned ) Rdest - ( unsigned ) Rsrc - C;

C = borrow ? 1 : 0;

[Description]

SUBX subtracts Rsrc and C from Rdest and puts the result in Rdest.

The condition bit (C) is set when the subtraction result cannot be represented by a 32-bit

unsigned integer; otherwise it is cleared.

[EIT occurrence]

None

[Encoding]

0000 dest

SUBX Rdest,Rsrc

0001 src

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INSTRUCTIONS

3.2 Instruction description

EIT-related instruction

TRAP

Trap

[Mnemonic]

TRAP #imm4

[Function]

Trap occurrence

BPC = PC + 4;

BSM = SM;

BIE = IE;

BC = C ;

IE = 0;

C = 0;

call_trap_handler( imm4 );

[Description]

TRAP generates a trap with the trap number specified by the 4-bit immediate value.

IE and C bits are cleared to "0".

[EIT occurrence]

Trap (TRAP)

[Encoding]

0001 0000 1111 imm4 TRAP #imm4;

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M32R-FPU Software Manual (Rev.1.01)

INSTRUCTIONS

3.2 Instruction description

load/store instruction

UNLOCK

Store unlocked

[Mnemonic]

UNLOCK Rsrc1,@Rsrc2

[Function]

Store unlocked

if ( LOCK == 1 ) { * ( int *) Rsrc2 = Rsrc1; }

LOCK = 0;

[Description]

When the LOCK bit is 1, the contents of Rsrc1 are stored at the memory location specified by

Rsrc2. When the LOCK bit is 0, store operation is not executed. The condition bit (C) is un-

changed.

This instruction clears the LOCK bit to 0 in addition to the simple storage operation.

The LOCK bit is internal to the CPU and cannot be accessed except by using the LOCK and

UNLOCK instructions.

The user cannot directly read or write to this bit.

The LOCK bit is internal to the CPU and is the control bit for receiving all bus right requests

from circuits other than the CPU.

Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to

the type of M

[EIT occurrence]

Address exception (AE)

[Encoding]

0010 src1 0101 src2 UNLOCK Rsrc1,@Rsrc2

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INSTRUCTIONS

3.2 Instruction description

Floating Point Instructions

Unsigned integer to float

UTOF

[M32R-FPU Extended Instruction]

[Mnemonic]

UTOF Rdest,Rsrc

[Function]

Convert from unsigned integer to floating-point single precision value.

Rdest = ( float ) ( unsigned int ) Rsrc ;

[Description]

UTOF converts the 32-bit unsigned integer stored in Rsrc to a floating-point single precision

value, and the result is stored in Rdest. The result is rounded according to the RM field in FPSR.

The condition bit (C) remains unchanged.

H’0000 0000 is treated as “+0” regardless of the Rounding Mode.

[EIT occurrence]

Floating-Point Exceptions (FPE)

• Inexact Exception (IXCT)

[Encoding]

1101 src 0000 0000 0100 dest 0100 0000

UTOF Rdest,Rsrc

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M32R-FPU Software Manual (Rev.1.01)

INSTRUCTIONS

3.2 Instruction description

logic operation instruction

XOR

Exclusive OR

[Mnemonic]

XOR Rdest,Rsrc

[Function]

Exclusive OR

Rdest = ( unsigned ) Rdest ^ ( unsigned ) Rsrc;

[Description]

XOR computes the logical XOR of the corresponding bits of Rdest and Rsrc, and puts the

result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

0000 dest 1101 src

XOR Rdest,Rsrc

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INSTRUCTIONS

3.2 Instruction description

logic operation instruction

XOR3

Exclusive OR 3-operand

[Mnemonic]

XOR3 Rdest,Rsrc,#imm16

[Function]

Exclusive OR

Rdest = ( unsigned ) Rsrc ^ ( unsigned short ) imm16;

[Description]

XOR3 computes the logical XOR of the corresponding bits of Rsrc and the 16-bit immediate

value, which is zero-extended to 32 bits, and puts the result in Rdest.

The condition bit (C) is unchanged.

[EIT occurrence]

None

[Encoding]

1000 dest

imm16

1101 src

XOR3 Rdest,Rsrc,#imm16

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M32R-FPU Software Manual (Rev.1.01)

APPENDICES

APPENDIX 1 Hexadecimal Instraction Code

APPENDIX 2 Instruction List

APPENDIX 3 Pipeline Processing

APPENDIX 4 Instruction Execution Time

APPENDIX 5 IEEE754 Specification Overview

APPENDIX 6 M32R-FPU Specification Supplemental

Explanation

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APPENDIX 1

Appendix 1 Hexadecimal Instraction Code

APPENDICES

Appendix1 Hexadecimal Instraction Code

The bit pattern of each instruction and correspondence of mnemonic are shown below.

The instructions enclosed in the bold lines are M32R-FPU extended instructions.

Appendix Table 1.1.1 Instruction Code Table

8-b11

0000

0001

0010

0011

0100

0101

0110

0111

hexadecimal

numeral

b0-b3

SUBV

Rdest,Rsrc

SUBX

Rdest,Rsrc

SUB

Rdest,Rsrc

NEG

Rdest,Rsrc

CMP

Rsrc1,Rsrc2

CMPU

Rsrc1,Rsrc2

0000

MUL

Rdest,Rsrc

SRL

Rdest,Rsrc

SRA

Rdest,Rsrc

SLL

Rdest,Rsrc

0001

0010

0011

0100

STH

STB

Rsrc1,@Rsrc2

STH

Rsrc1,@Rsrc2

UNLOCK

Rsrc1,@Rsrc2

Rsrc1,@Rsrc2+

Rsrc1,@Rsrc2

Rsrc1,@+Rsrc2

Rsrc1,@-Rsrc2

MULHI

Rsrc1,Rsrc2

MULLO

MULWHI

Rsrc1,Rsrc2

MULWLO

Rsrc1,Rsrc2

MACHI

Rsrc1,Rsrc2

MACLO

Rsrc1,Rsrc2

MACWHI

Rsrc1,Rsrc2

MACWLO

Rsrc1,Rsrc2

ADDI

Rdest,#imm8

MVTACHI,

MVTACLO

SRLI

Rdest,#imm5

SRAI

Rdest,#imm5

SLLI

0101

0110

0111

1000

1001

1010

1011

(

✽2)

Rdest,#imm5

LDI

Rdest,#imm8

NOP ( ✽ 1)

( ✽ 1)

BC, BNC, BL, BRA, SETPSW, CLRPSW

CMPI

Rsrc,#imm16

CMPUI

Rsrc,#imm16

DIV

Rdest,Rsrc

DIVU

Rdest,Rsrc

REM

Rdest,Rsrc

REMU

Rdest,Rsrc

STB

STH

BSET

BCLR

Rsrc1,@(disp16,Rsrc2)

#bitpos,@(disp16,Rsrc)

BEQ

BNE

Rsrc1,Rsrc2,pcdisp16

1100

1101

1110

1111

FPU

externded instruction

LD24

Rdest,#imm24

BC, BNC, BL, BRA

( ✽ 1)

FPU extended instruction (b0-b3 = 1101, b8-b11 = 0000)

0000

0001

0010

0011

0100

0101

0110

0111

b24-b27

hexadecimal

numeral

b16-b19

0000

FADD

FMUL

FDIV

FSUB

0001

0010

0011

0100

0101

0110

0111

FMADO

ITOF

FMSUB

UTOF

11 12

b15

0-b3

8-b

16-bit instruction

11 12

b15 b16

19 20

23 24

27 28

b31

0-b3

8-b11

0000

32-bit instruction

b15 b16

19 20

23 24

b24-b27

1101

b16-b19

32-bit instruction

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M32R-FPU Software Manual (Rev.1.01)

APPENDIX 1

Appendix 1 Hexadecimal Instraction Code

APPENDICES

1101

1110

8-b11

1000

1001

1010

1011

1100

1111

hexadecimal

numeral

0-b

ADDV

ADDX

NOT

AND

XOR

BTST

ADD

0000

0001

0010

0011

0100

Rdest,Rsrc

#bitpos,Rsrc

JL, JMP

( ✽ 1)

Rdest,Rsrc

MVFC

Rdest,CRsrc

MVTC

Rsrc,CRdest

RTE

TRAP

#imm4

LDB

Rdest,@Rsrc

LDUB

Rdest,@Rsrc

LDH

Rdest,@Rsrc

LDUH

Rdest,@Rsrc

LOCK

Rdest,@Rsrc

Rdest,@Rsrc+

ADDI

Rdest,#imm8

MVFACHI,

MVFACLO,

MVFACMI

RACH

RAC

0101

0110

0111

1000

1001

1010

1011

(

✽2)

LDI

Rdest,#imm8

(✽ 1)

BC, BNC, BL, BRA

ADDV3

Rdest,Rsrc,#imm16

ADD3

Rdest,Rsrc,#imm16

AND3

Rdest,Rsrc,#imm16

XOR3

Rdest,Rsrc,#imm16

OR3

Rdest,Rsrc,#imm16

SRL3

Rdest,Rsrc,#imm16

SRA3

Rdest,Rsrc,#imm16

SLL3

Rdest,Rsrc,#imm16

LDI

Rdest,#imm16

LDB

Rdest,@(disp16,Rsrc)

LDUB

Rdest,@(disp16,Rsrc)

LDH

Rdest,@(disp16,Rsrc)

LDUH

Rdest,@(disp16,Rsrc)

BEQZ

Rsrc,pcdisp16

BNEZ

Rsrc,pcdisp16

BLTZ

Rsrc,pcdisp16

BGEZ

Rsrc,pcdisp16

BLEZ

Rsrc,pcdisp16

BGTZ

Rsrc,pcdisp16

1100

1101

1110

1111

SETH

Rdest,#imm16

LD24

Rdest,#imm24

BC, BNC, BL, BRA (✽ 1)

1000

1001

1010

1011

1100

1101

1110

1111

b24-b27

hexadecimal

numeral

b16-b19

0000

FCMP

FCMPE

0001

0010

0011

0100

0101

0110

0111

FTOI

FTOS

Note. In addition to b0-b3, b8-b11, instructions shown the above ✽1, ✽2 in the table are

decided by the following bit patterns.

As for details of bit patterns of each instruction, refer to "3.2 Instruction description."

✽1: b4-b7, ✽2: b12-b15

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APPENDIX 2

Appendix 2 Instruction List

APPENDICES

Appendix 2 Instruction List

The M32R-FPU instruction list is shown below (in alphabetical order).

mnemonic

function

condition bit (C)

ADD

Rdest,Rsrc

Rdest = Rdest + Rsrc

–

ADD3 Rdest,Rsrc,#imm16

ADDI Rdest,#imm8

ADDV Rdest,Rsrc

ADDV3 Rdest,Rsrc,#imm16

ADDX Rdest,Rsrc

Rdest = Rsrc + (sh)imm16

Rdest = Rdest + (sb)imm8

Rdest = Rdest + Rsrc

–

change

–

Rdest = Rsrc + (sh)imm16

Rdest = Rdest + Rsrc + C

Rdest = Rdest & Rsrc

AND

Rdest,Rsrc

AND3 Rdest,Rsrc,#imm16

Rdest = Rsrc & (uh)imm16

–

pcdisp8

if(C) PC=PC+((sb)pcdisp8<<2)

if(C) PC=PC+((s24)pcdisp24<<2)

–

pcdisp24

BCLR #bitpos,@(disp16,Rsrc) *(sb *)(Rsrc + (sh)disp16) & = ~(1<<(7-bitpos))

–

BEQ

Rsrc1,Rsrc2,pcdisp16

if(Rsrc1 == Rsrc2) PC=PC+((sh)pcdisp16<<2)

if(Rsrc == 0) PC=PC+((sh)pcdisp16<<2)

if(Rsrc >= 0) PC=PC+((sh)pcdisp16<<2)

if(Rsrc > 0) PC=PC+((sh)pcdisp16<<2)

R14=PC+4,PC=PC+((sb)pcdisp8<<2)

R14=PC+4,PC=PC+((s24)pcdisp24<<2)

if(Rsrc <= 0) PC=PC+((sh)pcdisp16<<2)

if(Rsrc < 0) PC=PC+((sh)pcdisp16<<2)

if(!C) PC=PC+((sb)pcdisp8<<2)

–

BEQZ Rsrc,pcdisp16

BGEZ Rsrc,pcdisp16

BGTZ Rsrc,pcdisp16

–

pcdisp8

–

pcdisp24

–

BLEZ Rsrc,pcdisp16

BLTZ Rsrc,pcdisp16

–

BNC

BNE

pcdisp8

–

pcdisp24

if(!C) PC=PC+((s24)pcdisp24<<2)

if(Rsrc1 != Rsrc2) PC=PC+((sh)pcdisp16<<2)

if(Rsrc != 0) PC=PC+((sh)pcdisp16<<2)

PC=PC+((sb)pcdisp8<<2)

–

Rsrc1,Rsrc2,pcdisp16

–

BNEZ Rsrc,pcdisp16

–

BRA

pcdisp8

–

pcdisp24

PC=PC+((s24)pcdisp24<<2)

–

BSET #bitpos,@(disp16,Rsrc) *(sb *)(Rsrc + (sh)disp16) | = (1<<(7-bitpos))

BTST #bitpos,Rsrc

(Rsrc>>(7-bitpos))&1

change

CLRPSW#imm8

PSW & = ~imm8 | 0xffffff00

(s)Rsrc1 < (s)Rsrc2

change

CMP

Rsrc1,Rsrc2

CMPI Rsrc,#imm16

CMPU Rsrc1,Rsrc2

CMPUI Rsrc,#imm16

(s)Rsrc < (sh)imm16

(u)Rsrc1 < (u)Rsrc2

(u)Rsrc < (u)((sh)imm16)

DIV

Rdest,Rsrc

Rdest = (s)Rdest / (s)Rsrc

Rdest = (u)Rdest / (u)Rsrc

–

DIVU Rdest,Rsrc

FADD Rdest,Rsrc1,Rsrc2

FCMP Rdest,Rsrc1,Rsrc2

Rdest = Rsrc1 + Rsrc2

–

Rdest = (Rsrc1 == Rsrc2)?32'h00000000:((Rsrc1<

Rsrc2)?{1.31'bx}:{0.31'bx}

FCMPE Rdest,Rsrc1,Rsrc2

FDIV Rdest,Rsrc1,Rsrc2

FCMP with Exception when unordered

Rdest = Rsrc1 / Rsrc2

–

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APPENDIX 2

Appendix 2 Instruction List

APPENDICES

mnemonic

function

condition bit (C)

FMADD Rdest,Rsrc1,Rsrc2

FMSUB Rdest,Rsrc1,Rsrc2

FMUL Rdest,Rsrc1,Rsrc2

FSUB Rdest,Rsrc1,Rsrc2

FTOI Rdest,Rsrc

Rdest = Rdest + Rsrc1 * Rsrc2

Rdest = Rdest - Rsrc1 * Rsrc2

Rdest = Rdest * Rsrc2

Rdest = Rsrc1 - Rsrc2

Rdest = (s)Rsrc2

–

FTOS Rdest,Rsrc

Rdest = (sh)Rsrc

ITOF Rdest,Rsrc

Rdest = (float)Rsrc

–

Rsrc

R14 = PC+4, PC = Rsrc

PC = Rsrc

–

JMP

Rdest,@(disp16,Rsrc)

Rdest,@Rsrc

Rdest = *(s *)(Rsrc+(sh)disp16)

Rdest = *(s *)Rsrc

–

Rdest,@Rsrc+

Rdest = *(s *)Rsrc, Rsrc += 4

LD24

LDB

Rdest,#imm24

Rdest = imm24 & 0x00ffffff

–

Rdest,@(disp16,Rsrc) Rdest = *(sb *)(Rsrc+(sh)disp16)

Rdest,@Rsrc Rdest = *(sb *)Rsrc

Rdest,@(disp16,Rsrc) Rdest = *(sh *)(Rsrc+(sh)disp16)

LDB

LDH

Rdest,@Rsrc

Rdest,#imm16

Rdest,#imm8

Rdest = *(sh *)Rsrc

Rdest = (sh)imm16

Rdest = (sb)imm8

LDI

LDUB

LDUH

LOCK

Rdest,@(disp16,Rsrc) Rdest = *(ub *)(Rsrc+(sh)disp16)

Rdest,@Rsrc Rdest = *(ub *)Rsrc

Rdest,@(disp16,Rsrc) Rdest = *(uh *)(Rsrc+(sh)disp16)

Rdest,@Rsrc

Rdest = *(ub *)Rsrc

LOCK = 1, Rdest = *(s *)Rsrc

MACHI

Rsrc1,Rsrc2

accumulator += (s)(Rsrc1 & 0xffff0000)

* (s)((s)Rsrc2>>16)

–

MACLO

MACWHI

MACWLO

MUL

Rsrc1,Rsrc2

Rdest,Rsrc

Rsrc1,Rsrc2

accumulator += (s)(Rsrc1<<16) * (sh)Rsrc2

accumulator += (s)Rsrc1 * (s)((s)Rsrc2>>16)

accumulator += (s)Rsrc1 * (sh)Rsrc2

Rdest = (s)Rdest * (s)Rsrc

accumulator = (s)(Rsrc1 & 0xffff0000)

* (s)((s)Rsrc2>>16)

–

MULHI

MULLO

MULWHI

MULWLO

Rsrc1,Rsrc2

Rdest,Rsrc

accumulator = (s)(Rsrc1<<16) * (sh)Rsrc2

accumulator = (s)Rsrc1 * (s)((s)Rsrc2>>16)

accumulator = (s)Rsrc1 * (sh)Rsrc2

Rdest = Rsrc

–

MVFACHI Rdest

MVFACLO Rdest

MVFACMI Rdest

Rdest = accumulater >> 32

–

Rdest = accumulator

–

Rdest = accumulator >> 16

–

MVFC

Rdest,CRsrc

Rdest = CRsrc

–

MVTACHI Rsrc

MVTACLO Rsrc

accumulator[0:31] = Rsrc

–

accumulator[32:63] = Rsrc

MVTC

Rsrc,CRdest

CRdest = Rsrc

change

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APPENDIX 2

Appendix 2 Instruction List

APPENDICES

mnemonic

function

condition bit (C)

NEG

NOP

NOT

Rdest,Rsrc

Rdest = 0 - Rsrc

/*no-operation*/

Rdest = ~Rsrc

–

Rdest,Rsrc

Rdest = Rdest | Rsrc

–

OR3

Rdest,Rsrc,#imm16

Rdest = Rsrc | (uh)imm16

RAC

Round the 32-bit value in the accumulator

Round the 16-bit value in the accumulator

Rdest = (s)Rdest % (s)Rsrc

Rdest = (u)Rdest % (u)Rsrc

PC = BPC & 0xfffffffc,

–

RACH

REM

–

Rdest,Rsrc

–

REMU

RTE

change

PSW[SM,IE,C] = PSW[BSM,BIE,BC]

Rdest = imm16 << 16

SETH Rdest,#imm16

SETPSW #imm8

–

PSW | = imm8&0x000000ff

change

SLL

Rdest,Rsrc

Rdest = Rdest << (Rsrc & 31)

Rdest = Rsrc << (imm16 & 31)

Rdest = Rdest << imm5

–

SLL3 Rdest,Rsrc,#imm16

SLLI Rdest,#imm5

–

SRA

Rdest,Rsrc

Rdest = (s)Rdest >> (Rsrc & 31)

Rdest = (s)Rsrc >> (imm16 & 31)

Rdest = (s)Rdest >> imm5

–

SRA3 Rdest,Rsrc,#imm16

SRAI Rdest,#imm5

–

SRL

Rdest,Rsrc

Rdest = (u)Rdest >> (Rsrc & 31)

Rdest = (u)Rsrc >> (imm16 & 31)

Rdest = (u)Rdest >> imm5

–

SRL3 Rdest,Rsrc,#imm16

SRLI Rdest,#imm5

–

Rsrc1,@(disp16,Rsrc2) *(s *)(Rsrc2+(sh)disp16) = Rsrc1

–

Rsrc1,@+Rsrc2

Rsrc1,@-Rsrc2

Rsrc1,@Rsrc2

Rsrc2 += 4, *(s *)Rsrc2 = Rsrc1

Rsrc2 -= 4, *(s *)Rsrc2 = Rsrc1

*(s *)Rsrc2 = Rsrc1

–

STB

STH

SUB

Rsrc1,@(disp16,Rsrc2) *(sb *)(Rsrc2+(sh)disp16) = Rsrc1

Rsrc1,@Rsrc2 *(sb *)Rsrc2 = Rsrc1

Rsrc1,@(disp16,Rsrc2) *(sh *)(Rsrc2+(sh)disp16) = Rsrc1

–

Rsrc1,@Rsrc2

Rsrc1,@Rsrc2+

Rdest,Rsrc

*(sh *)Rsrc2 = Rsrc1

–

*(sh *)Rsrc2 = Rsrc1, Rsrc2 += 2

Rdest = Rdest - Rsrc

–

SUBV Rdest,Rsrc

SUBX Rdest,Rsrc

Rdest = Rdest - Rsrc

change

Rdest = Rdest - Rsrc - C

TRAP #n

PSW[BSM,BIE,BC] = PSW[SM,IE,C]

PSW[SM,IE,C] = PSW[SM,0,0]

Call trap-handler number-n

change

UNLOCK Rsrc1,@Rsrc2

if(LOCK) { *(s *)Rsrc2 = Rsrc1; } LOCK=0

Rdest = (float)(unsigned int) Rsrc;

–

UTOF

Rdest,Rsrc

XOR

Rdest,Rsrc

Rdest = Rdest ^ Rsrc

–

XOR3 Rdest,Rsrc,#imm16

Rdest = Rsrc ^ (uh)imm16

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APPENDIX 2

Appendix 2 Instruction List

APPENDICES

where:

typedef singed int

typedef unsigned int

typedef signed short

s; /* 32 bit signed integer (word)*/

u; /* 32 bit unsigned integer (word)*/

sh; /* 16 bit signed integer (halfword)*/

typedef unsigned short uh; /* 16 bit unsigned integer (halfword)*/

typedef signed char

sb; /* 8 bit signed integer (byte)*/

ub; /* 8 bit unsigned integer (byte)*/

typedef unsigned char

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

Appendix 3 Pipeline Processing

Appendix 3.1 Instructions and Pipeline Processing

Appendix Figure 3.1.1 shows each instruction type and the pipeline process.

I Load/Store instruction

6 stages

MEM1 MEM2

Pipeline Stage

*The number of cycles required by the MEM1 stage varies according to the access,

but the MEM2 stage is normally executed in 1 cycle.

I All other integer instructions

4 stages

Pipeline Stage

*Multi-cycle instructions such as the multiply instruction are executed in multiple

cycles in the E stage.

Pipeline Stage

¥¥¥¥¥¥

II FPU instruction (excluding FMADD, FMSUB)

5 stages

Pipeline Stage

*The E1 and E2 stages cannot be executed at the same time as the E stage.

*The E1 stage of the FDIV instruction requires 14 cycles.

I FPU instruction (FMADD, FMSUB)

6 stages

EM EA

* The EM and EA stages cannot be executed at the same time as the E or E1 stage.

Pipeline Stage

*Operation stages with the same name cannot be executed at the same time. In general, stages with

different names can be executed in parallel, but the following combinations are not acceptable.

¥ E stage executed with E1, E2, EM or EA stage.

¥ E1 stage executed with EM or EA stage.

*Bypass process: When using the result of one instruction in a subsequent instruction, the first result

may bypass the register file and be sent on to the execution stage of the subsequent instruction.

The following is an example of a bypass process:

¥ E stage continuing to WB stage → E, E1, EM stages

¥ MEM2 stage continuing to WB stage → E, E1, EM, EA stages

Appendix Figure 3.1.1 Instructions and Pipeline Process

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

The overview of each pipeline stage is shown below.

✽ IF stage (instruction fetch stage)

The instruction fetch (IF) is processed in this stage. There is an instruction queue

and instructions are fetched until the queue is full regardless of the completion of

decoding in the D stage.

If there is an instruction already in the instruction queue, the instruction read out

of the instruction queue is passed to the instruction decoder.

✽ D stage (decode stage)

Instruction decoding is processed in the first half of the D stage (DEC1).

The subsequent instruction decoding (DEC2) and a register fetch (RF) is

processed in the second half of the stage.

✽ E stage (execution stage)

Operations and address calculations (OP) are processed in the E stage.

If an operation result from the previous instruction is required, bypass process

(BYP) is performed in the first half of the E stage.

✽ E1, EM, EA stage (execution stage)

These are the initial stages for execution of the FPU instructions. The EM and EA

stages only use instructions FMADD and FMSUB. All other instructions are used

in the E1stage

✽ E2 stage (execution stage)

This is the secondary stage for the execution of FPU instructions and mainly

rounding is performed.

✽ MEM stage (memory access stage)

Operand accesses (OA) are processed in the MEM stage. This stage is used only

when the load/store instruction is executed.

✽ WB stage (write back stage)

The operation results and fetched data are written to the registers in the WB

stage.

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

Appendix 3.2 Pipeline Basic Operation

(1) Pipeline Flow with no Stall

The following diagram shows an ideal pipeline flow that has no stall and executes each

instruction in 1 clock cycle. (Since this is just an ideal case, all instructions may not be

piplined in.)

<Case 1> Integer instructions (register-to-register) are executed continuously

LDI R0,#1

ADD R0,R1

OR R0,R2

CMP R0,R3

* A multi-cycle instruction, such as multiply or divide, executes

multiple cycles in the E stage.

<Case 2> Load/store instructions to destination are accessed in 1 cycle continuously

ST R0,@-R15

ST R1,@-R15

LD R2,@R15+

LD R3,@R15+

MEM1 MEM2 WB

<Case 3> Register-register instructions are executed with no register dependency following

a load/store instruction (out-of-order-completion)

LD R0,@R2

LDI R1,#1

ADD R1,R3

OR R1,R4

MEM1 MEM1 MEM2 WB

* A multi-cycle instruction, such as multiply or divide, executes multiple

cycles in the E stage.

Appendix Figure 3.2.1 Pipeline Flow with no Stall (1)

APPENDICES-10

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

<Case 4> Three FPU instructions continue consecutively with no register dependency

FADD R0,R5,R6

FSUB R1,R6,R7

FMUL R2,R7,R8

FCMP R0,R0,R3

* The FDIV instruction takes 14 cycles in E1 stage.

<Case 5> Four FMADD or FMSUB instructions continue consecutively with no register dependency

FMADD R0,R5,R6

FMADD R1,R6,R7

FMADD R2,R7,R8

FMADD R3,R80,R9

Appendix Figure 3.2.2 Pipeline Flow with no Stall (2)

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

(2) Pipeline Flow with Stalls

A pipeline stage may stall due to execution of a process or branch instruction.

The following diagrams show typical stall cases.

<Case 1> An instruction which requires several cycles is executed in E

DIV R1,R2

ADD R3,R4

ADD R5,R6

ADD R7,R8

••••

stall

<Case 2> An instruction which requires more than 1 cycle for its operand access is executed

Other than no-wait

memory access

LD R1,@R2

LD R3,@R4

ADD R5,R6

ADD R7,R8

MEM1 MEM1

MEM1 MEM2 WB

••••

stall

stall MEM1 MEM2 WB

stall

stall: a pipeline stall

Appendix Figure 3.2.3 Pipeline Flow with Stalls (1)

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

<Case 3> A branch instruction is executed (except for the case in which no branch occurs

at a conditional branch instruction)

branch instruction is executed

Branch Instruction

stall

<Case 4> The subsequent instruction uses an operand read from the memory

LD R1,@R2

MEM1 MEM2 WB

Bypass process

stall

ADD R3,R1

LD R1,@R2

MEM1 MEM2 WB

Bypass process

ADD R4,R5

stall

ADD R3,R1

LD R1,@R2

MEM1 MEM2 WB

Bypass process

ADD R4,R5

ADD R6,R7

ADD R3,R1

LD R1,@R2

MEM1 MEM2 WB

Bypass process

ADD R4,R5

FMADD R1,R6,R7

Appendix Figure 3.2.4 Pipeline Flow with Stalls (2)

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

<Case 5> The PSW is written by an MVTC, SETPSW, or CLRPSW instruction and

the subsequent instruction reads R15

MVTC R1,PSW

stall

SUB R3,R15

<Case 6> FPSR is accessed by an MVFC instruction after the FPU instruction is executed

FADD R0,R1,R2

stall

MVFC R3,FPSR

<Case 7> The operation result of the FPU instruction is used by the subsequent instruction

FADD R0,R1,R2

stall

FADD R3,R0,R4

FMADD R0,R1,R2

stall

FMADD R0,R3,R4

FMADD R0,R1,R2

stall

FMADD R3,R0,R4

Appendix Figure 3.2.5 Pipeline Flow with Stalls (3)

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

<Case 8> The FPU and integer instructions run consecutively (with no register dependency)

ADD R0,R1

FADD R2,R3,R4

ADD R5,R6

stall

FADD R7,R8,R9

<Case 9> The FPU and integer instructions run consecutively (with register dependency)

ADD R0,R1

Bypass process

stall

FADD R0,R0,R4

ADD R0,R6

stall

Bypass process

E2 WB

FADD R0,R0,R9

<Case 10> The FMADD/FMSUB instructions run consecutively with the integer instruction

(with no register dependency)

ADD R0,R1

FMADD R2,R3,R4

ADD R5,R6

stall

FMADD R7,R8,R9

<Case 11> The FMADD/FMSUB instructions run consecutively with the integer instruction

(with register dependency)

ADD R0,R1

Bypass process

stall

FMADD R0,R0,R4

ADD R0,R6

stall

FMADD R0,R8,R9

Appendix Figure 3.2.6 Pipeline Flow with Stalls (4)

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APPENDIX 3

Appendix 3 Pipeline Processing

APPENDICES

<Case 12> The FPU and FMADD/FMSUB instructions run consecutively (with no register dependency)

FADD R0,R1,R10

FMADD R2,R3,R4

FADD R5,R6,R11

stall

FMADD R7,R8,R9

<Case 13> The FPU and FMADD/FMSUB instructions run consecutively (with register dependency)

FADD R0,R1,R10

FMADD R0,R0,R4

FADD R0,R0,R11

stall

FMADD R0,R8,R9

Appendix Figure 3.2.7 Pipeline Flow with Stalls (5)

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APPENDIX 4

Appendix 4 Instruction Execution Time

APPENDICES

Appendix 4 Instruction Execution Time

Normally, the E stage is considered as representing as the instruction execution time,

however, because of the pipeline processing the execution time for other stages may

effect the total instruction execution time. In particular, the IF, D, and E stages of the

subsequent instruction must be considered after a branch has occurred.

The following shows the number of the instruction execution cycles for each pipeline

stage.

The execution time of the IF and MEM stages depends on the implementation of each

product of the M32R family.

Refer to the user's manual of each product for the execution time of these stages.

Note 1: FPU instruction uses E1 and EM stages.

Appendix Table 4.1.1 Instruction Execution Cycles per Pipeline Stage [excluding FPU instructions]

the number of execution cycles in each stage

instruction

MEM1 MEM2 WB

load instruction (LD, LDB, LDUB, LDH, LDUH, LOCK)

store instruction (ST, STB, STH, UNLOCK)

BSET, BCLR instructions

R (note 1)

W (note 1)

(1) (note 2)

R (note 1) 1 R (note 1) W (note 1)

multiply instruction (MUL)

R (note 1)

divide/reminder instruction (DIV, DIVU, REM, REMU)

other instructions (DSP function instructions,

including BTST, SETPSW, CLRPSW)

Note 1: R, W: Refer to the user's manual prepared for each product.

Note 2: Within the store instruction, only instructions which include the register indirect and

do not require extra cycles.

Appendix Table 4.1.2 Instruction Execution Cycles per Pipeline Stage [FPU instructions]

the number of execution cycles in each stage

instruction

FMADD, FMSUB instructions

FDIV instruction

R (note 1)

other FPU instructions

Note 1: R, W: Refer to the user's manual prepared for each product.

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APPENDIX 5

Appendix 5 IEEE754 Specification Overview

APPENDICES

Appendix 5 IEEE754 Specification Overview

The following is a basic overview of the IEEE754 specification. M32R-FPU fulfills the

IEEE754 requirements through a combination of software and hardware features.

Appendix 5.1 Floating Point Formats

The following describes the floating-point formats.

8 9

Single Precision

Double Precision

e (8 bit)

s (1 bit)

f (23 bit)

11 12

e (11 bit)

s (1 bit)

f (52 bit)

Appendix Figure 5.1.1 Floating-Point Formats

s: Sign bit. 0 = positive number, 1 = negative numbers

e: Exponent. This represents a value that was made positive by adding 127 to a single

precision value or 1023 to a double precision value (biased exponent).

f : Fraction. Represents the fraction field of the value.

Using these symbols, the floating-point values (normalized numbers) can be described

by the following expressions:

Single-Precision Format: (–1) ^ s ✽ 1.f ✽ 2 ^ (e–127)

Double-Precision Format: (–1) ^ s ✽ 1.f ✽ 2 ^ (e–1023)

• Certain values do not fit into the above expressions, such as ±∞, ±0, NaN (Not a

Number), denormalized numbers, etc.

• Other formats, such as expanded double precision, can also be used.

✽ M32R-FPU only supports the single-precision format. The double precision format is

supported in the software library.

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APPENDIX 5

Appendix 5 IEEE754 Specification Overview

APPENDICES

Appendix Table 5.1.1 Single Precision Floating-Point Bit Values

Exponent

Expressed value

Before adding bias

0111 1111 (+127)

After adding bias

( =0111 1111)

1111 1110

Normalized number

•

(The absolute value can be described for the range

of 1. 0…0 x 2 ^ -126 to 1. 1…1 x 2 ^ 127)

1000 0010 (-126)

0000 0001

0000 0000

(1000 0001 (-127) )

Fraction field = all 0: ±0

Fraction field ≠ all 0: denormalized number

(1000 0000 (-128) )

1111 1111

Fraction field = all 0: ±∞

Fraction field ≠ all 0: NaN (the value is split into SNaN and

QNaN according to the value of high-order bit of the

fraction field)

(1) Denormalized Numbers

Denormalized numbers represent numbers (values??) that have an absolute value

less than 1. 0…0 x 2 ^ -126. Single-precision denormalized numbers are expressed as

follows:

(-1) ^ s x 0.f x 2 ^ -126

(2) NaN (Not a Number)

SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction field is "0".

When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs

are useful in identifying program bugs when used as the initial value in a variable.

However, SNaNs cannot be generated by hardware.

QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction field is "1". Even

when QNaN is used as the source operand in an operation, an IVLD will not occur

(excluding comparison and format conversion). Because a result can be checked by

the arithmetic operations, QNaN allows the user to debug without executing an EIT

processing. QNaNs are created by hardware.

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APPENDIX 5

Appendix 5 IEEE754 Specification Overview

APPENDICES

Appendix 5.2 Rounding

The following 4 rounding modes are specified by IEEE754.

Appendix Table 5.2.1 Four Rounding Modes

Rounding Mode

Round to Nearest (default)

Operation

Assuming an infinite range of precision, round to the best

approximation of the result. Round an interval arithmetic

result to an even number.

Round toward –Infinity

Round toward +Infinity

Round toward 0

Round to the smaller magnitude of the result.

Round to the larger magnitude of the result.

Round to the smaller in magnitude of the absolute value

of the result.

• “Round to Nearest” is the default mode and produces the most accurate value.

• “Round toward –Infinity,” “Round toward +Infinity” and “Round toward Zero” are used

for interval arithmetic to insure precision

Appendix 5.3 Exceptions

IEEE754 allows the following 5 exceptions. The floating-point status register is used to

determine whether the EIT process will be executed when an Exception occurs.

(1) Overflow Exception (OVF)

The exception occurs when the absolute value of the operation result exceeds the

largest describable precision in the floating-point format. Appendix Table 5.3.1 shows

the operation results when an OVF occurs.

Appendix Table 5.3.1 Operation Result due to OVF Exception

Result

Rounding Mode

Sign of Result

when the OVF EIT

processing is masked

processing is executed

–Infinity

–

+MAX

round (x2 ^ -a)

–Infinity

+Infinity

–MAX

a = 192 (single-precision)

a = 1536 (double-precision)

+Infinity

+MAX

–MAX

Nearest

+Infinity

–Infinity

Note : • When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "0"

• When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "1"

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APPENDIX 5

Appendix 5 IEEE754 Specification Overview

APPENDICES

(2) Underflow Exception (UDF)

The exception occurs when the absolute value of the operation result is less then the

largest describable precision in the floating-point format. Appendix Table 5.3.2 shows

the operation results when a UDF occurs.

Appendix Table 5.3.2 Operation Results due to UDF Exception

Result

when the UDF EIT processing is masked

when the UDF EIT processing is executed

Denormalized Numbers

round (x2 ^ a)

(The denomalize flag is set only when

rounding occurs.)

a = 192 (single-precision),

a = 1536 (double-precision)

Note: • When the operation result is rounded, an Inexact Exception is generated simultaneously.

(3) Inexact Exception (IXCT)

The exception occurs when the operation result differs from a result led out with an

infinite range of precision. Appendix Table 5.3.3 shows operation results and the

respective conditions in which each IXCT occurs.

Appendix Table 5.3.3 Operation Results and Respective Conditions for IXCT Exception

Result

Occurrence Condition

when the IXCT EIT

processing is masked

processing is executed

Overflow occurs in OVF Exception

masked condition

Reference OVF Exception

table

Same as left

Rounding occurs

Rounded value

(4) Zero Division Exception (DIV0)

The exception occurs when a finite, nonzero value is divided by zero. Appendix Table

5.3.4 shows the operation result when a DIV0 occurs.

Appendix Table 5.3.4 Operation Results for DIV0 Exception

Result

Dividend

when the DIV0 EIT

when the IXCT EIT

processing is masked

processing is executed

Nonzero finite value

± Infinity (Sign of result is

exclusive-OR (EXOR) of

signs of divider and dividend.)

Destination unchanged

Please note that the DIV0 EIT operation does not occur in the following factors.

Dividend

Operation

Invalid Operation Exception occurs

No Exception occurs (result is “Infinity”)

Infinity

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APPENDIX 5

Appendix 5 IEEE754 Specification Overview

APPENDICES

(5) Invalid Operation Exception (IVLD)

The exception occurs when an invalid operation is executed. Appendix Table 5.3.5

shows operation results and the respective conditions in which each IVLD occurs.

Appendix Table 5.3.5 Operation Results due to IVLD Exception

Result

Occurrence Condition

when the IVLD EIT

processing is masked

processing is executed

Operation for SNaN operand

QNaN

(Destination unchanged)

+Infinity– (+Infinity), –Infinity– (–Infinity)

0 ✽ Infinity

0 ÷ 0, Infinity ÷ Infinity

oute operation for values less then 0

Integer conversion overflow:

Undefined

NaN and ∞ are converted to integers

When < or > comparison was performed on NaN (No change)

Important: The following operations never generate an Exception.

√ (-0): returns –0

∞/ 0: returns ∞ (Sign of result is exclusive-OR (EXOR) of signs of divider and

dividend.)

✽ Definition of Terms

• Exception

Special conditions generated by execution of floating-point instructions. The

corresponding enable bits of the floating-point status register are used to determine

whether the EIT processing will be executed when an Exception occurs. However, the

actual generation of an exception cannot be masked.

• EIT Processing

An operation triggered by the generation of an Exception, in which the flow jumps to a

floating-point Exception vector address, or a string of related Exception operation

sequences is triggered. The corresponding enable bits of the floating-point status

Exception occurs.

• Intermediate Result of Operation

The value resulting from calculations of infinite and unbounded exponent and mantissa

bits. In actual implementation, the number of exponent and mantissa bits is finite and

the intermediate result is rounded so that the final operation result can be determined.

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APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

APPENDICES

Appendix 6 M32R-FPU Specification Supplemental Explanation

Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs. two

instructions (FMUL and FADD)

The following is an explanation of the differences between an operation using just one

instruction (FMADD or FMSUB) and an operation using 2 instructions (FMUL and

FADD).

Appendix 6.1.1 Rounding Mode

The rounding mode for an operation using both FMUL and FADD rounds both FMUL

and FADD according to the setting of the FPSR RM field. However, the result of the

FMADD or FMSUB instruction in Step 1 (multiply stage) is not rounded according to

the setting of FPSR RM field, rather it is rounded toward zero.

Appendix 6.1.2 Exception occurring in Step 1

Two instructions are compared below as examples of Exception occurring in Step 1.

✽✽FMUL + FADD:

FMUL

FADD

R3, R1, R2

R0, R3, R0

(R3 = R1 * R2)

(R0 = R3 + R0)

✽✽FMADD or FMSUB:

FMADD R0, R1, R2

(R0 = R0 +R1 * R2)

Note: If the register supports different operations than those described above, the

operations may differ in some ways to those shown below.

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APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

APPENDICES

(1) Overflow occurs in Step 1

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Normalized

number, 0

–

R0 = OVF immediate

value (Note 1) + R0

R0 = OVF immediate

value (Note 2)

Infinity

when OVF immediate value EV=0

IVLD occurs

same as left

R0=H'7FFF FFFF

is R0 and the opposite sign EV=1

of the infinity sign

IVLD occurs, EIT occurs

R0 = maintained

factors other than above

–

R0 = ∞

(same as original value)

Denormalized DN=0

number

UIPL occurs, EIT occurs

R0 = maintained

DN=1

R0 = OVF immediate value

(Note 1)

QNaN

SNaN

–

R0 = maintained (QNaN)

same as left

EV=0

IVLD occurs

R0 = R0 converted to QNaN

EV=0

IVLD occurs, EIT occurs

R0 = maintained (SNaN)

same as left

Note 1: Refer to [Appendix Table 5.3.1 Operation Result due to OVF Exception] for immediate

values if an overflow occurs due to Overflow Exclusion when the EIT processing is

masked.

Note 2: In Step 1, the rounding mode is set to [Round toward 0]. However, when an overflow

occurs, the immediate value is rounded according to the rounding mode. Refer to

[Appendix Table 5.3.1 Operation Result due to OVF Exception] for these values.

However, when the rounding mode is [round toward nearest], the OVF immediate value =

infinity and the R0 value becomes the same as that of FMUL + FADD.

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Normalized

number, 0,

Infinity

–

EIT occurs when FMUL is

completed

EIT occurs,

R0 = maintained

Denormalized DN=0

number

Same as above

UIPL occurs,

EIT occurs

R0 = maintained

DN=1

Same as above

EIT occurs

R0 = maintained

QNaN

SNaN

–

Same as above

EV=0

IVLD occurs,

EIT occurs

R0 = maintained

EV=1

Same as above

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APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

APPENDICES

(2) When underflow occurs in Step 1

Type of R0

Condition

FMUL + FADD Operation

R0 = R0 + 0

FMADD Operation

Same as left

Normalized

number, 0,

Infinity

–

Denormalized

number

R0 = 0

Same as left

QNaN

SNaN

–

R0 = maintained (QNaN)

EV=0

R0 = R0 converted to QNaN Same as left

IVLD occurs

EV=1

R0 = maintained (SNaN)

IVLD occurs, EIT occurs

Same as left

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Normalized

number, 0,

Infinity

–

EIT occurs when FMUL is

completed

EIT occurs,

R0 = maintained

Denormalized

number

Same as above

QNaN

SNaN

–

Same as above

EV=0

IVLD occurs,

EIT occurs

R0 = maintained

EV=1

Same as above

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Normalized

number, 0,

Infinity

–

EIT occurs when FMUL is

completed

EIT occurs,

R0 = maintained

Denormalized DN=0

number

Same as above

UIPL occurs,

EIT occurs

R0 = maintained

DN=1

Same as above

EIT occurs

R0 = maintained

QNaN

SNaN

–

Same as above

EV=0

IVLD occurs,

EIT occurs

R0 = maintained

EV=1

Same as above

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APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

APPENDICES

(3) When Invalid Operation Exception occurs in Step 1

✽✽If at least one of [R1, R2] is an SNaN

Type of R0

Normalized

Condition

FMUL + FADD Operation

FMADD Operation

Same as left

–

R0 = R3

(SNaN converted to QNaN)

Denormalized DN=0

number

R0 = R3

Same as left

(SNaN converted to QNaN)

DN=1

R0 = R3

(SNaN converted to QNaN)

QNaN

SNaN

–

R0 = maintained (QNaN)

R0 = R0 converted to QNaN Same as left

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Normalized

number, 0,

Infinity

–

EIT occurs when FMUL is

completed

EIT occurs,

R0 = maintained

Denormalized DN=0

number

Same as above

UIPL occurs,

EIT occurs

R0 = maintained

DN=1

Same as above

EIT occurs,

R0 = maintained

QNaN

SNaN

–

Same as above

✽✽If “✽ ∞” occurs in [R1, R2]

Type of R0

Normalized

Condition

FMUL + FADD Operation

R0 = H'7FFF FFFF

FMADD Operation

Same as left

–

Denormalized DN=0

R0 = H'7FFF FFFF

Same as left

number

QNaN

SNaN

DN=1

R0 = H'7FFF FFFF

Same as left

–

R0 = maintained (QNaN)

Same as left

R0 = R0 converted to QNaN Same as left

Same results as when “If at least one of [R1, R2] is an SNaN.”

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APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

APPENDICES

(4) When Inexact Operation Exception occurs in Step 1

✽✽If an Inexact Operation occurs due to rounding:

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Same as left

Normalized

number, 0,

Infinity

–

R0 = rounded value of

R1*R2 + R0

Denormalized DN=0

number

UIPL occurs, EIT occurs

R0 = maintained

Same as left

DN=1

R0 = rounded value of

R1*R2

QNaN

SNaN

–

R0 = maintained (QNaN)

Same as left

EV=0

IVLD occurs

R0 = R0 converted to QNaN

EV=1

IVLD occurs, EIT occurs

R0 = maintained (SNaN)

Same as left

Type of R0

Condition

FMUL + FADD Operation

FMADD Operation

Normalized

number, 0,

Infinity

–

EIT occurs when FMUL is

completed

EIT occurs,

R0 = maintained

Denormalized DN=0

number

Same as above

UIPL occurs,

EIT occurs

R0 = maintained

DN=0

Same as above

EIT occurs

R0 = maintained

QNaN

SNaN

–

Same as above

EV=0

IVLD occurs,

EIT occurs

R0 = maintained

EV=1

Same as above

✽✽When an Inexact Operation occurs due to an OVF at EO = 0:

Refer to “(1) Overflow occurs in Step 1 <When EO = 0, EX = 0: OVF and IXCT occur>”.

Same results as “✽✽If an Inexact Operation occurs due to rounding <when EX = 1: IXCT

occurs>”.

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APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

APPENDICES

Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU

The following are rules concerning generating a QNaN as an operation result.

Instructions that generate NaNs as operation results are FADD, FSUB, FMUL, FDIV,

FMADD, and FMSUB.

[Important Note]

This rule does not apply when the data that is sent to Rdest, the results of the FCMP or

FCMPE comparison, comprise a NaN bit pattern.

<FADD, FSUB, FMUL, FDIV>

Source Operand (Rsrc1, Rsrc2)

SNaN and QNaN

Rdest

SNaN converted to QNaN (Note 1)

Rsrc2 converted to QNaN (Note 1)

Rscr2

Both SNaN

Both QNaN

SNaN and actual number

QNaN and actual number

Neither operand is NaN; IVLD occurs

SNaN converted to QNaN (Note 1)

QNaN

H'7FFF FFFF

Note 1: SNaN b9 is set to “1” and the operand is converted to QNaN.

<FMADD, FMSUB>

Source Operand

Rsrc1, Rsrc2

Rdest

Actual number

SNaN and QNaN

Both SNaN

SNaN converted to QNaN (Note 1)

Rsrc2 converted to QNaN (Note 1)

Rscr2

Both QNaN

SNaN and actual number

QNaN and actual number

SNaN converted to QNaN (Note 1)

QNaN

Neither operand is NaN; IVLD occurs H'7FFF FFFF

QNaN

SNaN

Don't care

Rdest (maintained)

Rdest converted to QNaN (Note 1)

Note 1: SNaN b9 is set to “1” and the operand is converted to QNaN.

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APPENDIX 7

Appendix 7 Precautions

APPENDICES

Appendix 7 Precautions

Appendix 7.1 Precautions to be taken when aligning data

When aligning or allocating the data area following the code area in a program, the

alignment must be done from an address that has an adjusted word alignment.

If the data area is aligned or allocated without adjusting the word alignment, a 16-bit

instruction may exist in the high-order halfword of the word, and data with MSB of “1”

may be aligned to the following halfword. In this case, the M32R family upward-

compatible CPU recognizes the 16-bit instruction and the data as a pair of parallel

executable instructions and executes the instructions as such.

In consideration of the upward compatibility of software when programming, if the high-

order halfword has a 16-bit instruction, make sure that the following data area is aligned

or allocated from an address that has an adjusted word alignment.

1 word

MSB

16-bit instruction

data

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APPENDIX 7

Appendix 7 Precautions

APPENDICES

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INDEX

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INDEX

BNEZ 3-25

BRA 3-26

JL 3-59

Symbol

#imm 1-15, 3-2

@(disp,R) 1-15, 3-2

@+R 1-15, 3-2

@-R 1-15, 3-2

@R 1-15, 3-2

JMP 3-60

NOP 3-87

@R+ 1-15, 3-2

Compare instructions 2-4

CMP 3-30

CMPI 3-31

CMPU 3-32

CMPUI 3-33

Accumulator(ACC) 1-11

Addressing Mode 1-15, 3-2

Arithmetic operation instructions 2-4

ADD 3-6

Condition Bit Register(CBR) 1-5

Control registers 1-3

CPU Programming Model 1-1

CPU Register 1-2

CR 1-3, 1-15

ADD3 3-7

ADDI 3-8

CR0 1-3, 1-4

ADDV 3-9

ADDV3 3-10

CR1 1-3, 1-5

ADDX 3-11

CR2 1-3, 1-5

NEG 3-86

CR3 1-3, 1-5

SUB 3-113

CR6 1-3, 1-5

SUBV 3-114

CR7 1-3, 1-6

SUBX 3-115

Data format 1-13, 1-14

Data format in a register 1-13

Data format in memory 1-14

Data type 1-12, 3-3

DSP function instructions 2-8

MACHI 3-69

Backup PC(BPC) 1-5

Bit operation instructions 2-11

BCLR 3-15

BSET 3-27

BTST 3-28

CLRPSW 3-29

SETPSW 3-99

Branch instructions 2-6

BC 3-14

MACLO 3-70

MACWHI 3-71

MACWLO 3-72

MULHI 3-74

BEQ 3-16

MULLO 3-75

BEQZ 3-17

MULWHI 3-76

BGEZ 3-18

MULWLO 3-77

BGTZ 3-19

MVFACHI 3-79

BL 3-20

MVFACLO 3-80

MVFACMI 3-81

MVTACHI 3-83

BLEZ 3-21

BLTZ 3-22

BNC 3-23

MVTACLO 3-84

RAC 3-91

BNE 3-24

RACH 3-93

INDEX-2

M32R-FPU Software Manual (Rev.1.01)

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INDEX

EIT-related instructions 2-8

Load/store instructions 2-2

LD 3-61

RTE 3-97

TRAP 3-116

LDB 3-63

LDH 3-64

LDUB 3-66

LDUH 3-67

LOCK 3-68

ST 3-109

Floating-point instruction 2-11

FADD 3-36

STB 3-111

STH 3-112

FCMP 3-38

UNLOCK 3-117

Logic operation instructions 2-5

AND 3-12

FCMPE 3-40

FDIV 3-42

FMADD 3-44

FMSUB 3-47

FMUL 3-50

AND3 3-13

NOT 3-88

OR 3-89

FSUB 3-52

OR3 3-90

FTOI 3-54

XOR 3-119

FTOI 3-54

XOR3 3-120

ITOF 3-58

UTOF 3-118

Floating-point Status Register 1-6

Multiply/divide instructions 2-5

DIV 3-34

DIVU 3-35

General-purpose Registers 1-2

MUL 3-73

REM 3-95

REMU 3-96

Hexadecimal Instruction Code APPENDICES-2

Operation expression 3-2, 3-3

Operation instructions 2-4

Operand List 3-2

immediate 1-15, 3-2

Instruction Execution Time APPENDICES-17

Instruction format 2-12

Instruction List APPENDICES-4

Instruction set overview 2-2

PC relative(pcdisp) 1-14, 3-2

Interrupt Stack Pointer(SPI) 1-2, 1-3, 1-5

Processor Status Register(PSW) 1-3, 1-4

Program Counter(PC) 1-11

INDEX-3

M32R-FPU Software Manual (Rev.1.01)

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INDEX

1-15, 3-2

Shift instructions 2-5

SLL 3-100

SLL3 3-101

SLLI 3-102

SRA 3-103

SRA3 3-104

SRAI 3-105

SRL 3-106

SRL3 3-107

SRLI 3-108

Stack pointer 1-2, 1-5

Transfer instructions 2-4

LD24 3-62

LDI 3-65

MV 3-78

MVFC 3-82

MVTC 3-85

SETH 3-98

User Stack Pointer(SPU) 1-2, 1-3, 1-5

INDEX-4

M32R-FPU Software Manual (Rev.1.01)

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RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER

SOFTWARE MANUAL

M32R-FPU

Publication Data : Rev.1.00 Jan 08, 2003

Rev.1.01 Oct 31, 2003

Published by : Sales Strategic Planning Div.

Renesas Technology Corp.

Download from Www.Somanuals.com. All Manuals Search And Download.

M32R Family

Software Manual

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan

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