Philips Stereo Amplifier TDA5360 User Manual

INTEGRATED CIRCUITS  
TDA5360  
Pre–Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
Objective specification, Revision 2.2  
1998 Jul 30  
Philips  
Semiconductors  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
1
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FEATURES  
12 channels design for Single-stripe (SAL and GMR) Read / Thin-film Write heads.  
Design target 350 Mbps, for d=0 (16 / 17) rate code.  
Differential Hybrid sense Reader architecture.  
MR element biased by direct programmable constant Power or constant Current.  
Voltage driven Writer architecture.  
MR read / inductive write heads biased at ground level.  
Short rise and fall time with near rail to rail voltage swing.  
Dual power supplies : +5.0 V and -5.0 V.  
On-chip AC couplings eliminate MR head DC and DC offset voltage.  
Programmable 3-wire Serial Port Interface for programming (3.3 V and 5 V TTL / CMOS compatible).  
Extensive programmability of Write current wave overshoot.  
Programmable voltage / current mode write data input.  
Programmable voltage / current mode read data output.  
Programmable Read gain.  
Programmable Reader input impedance.  
Thermal asperity detection with programmable threshold.  
Thermal asperity compression with extensive programmability.  
High spurious-noise rejections.  
Internal Dummy Head available for MR heads protection during switchings.  
FAST mode available for short Write to Read mode transient.  
Sleep, Standby, Active, Servo Track Write, and Test modes available.  
Support servo writing.  
Write / Read Fault detection with fault code read back register and Fault masking capability.  
Low power-supplies fault protections.  
Short Write to Read Recovery, including DC settling.  
On-chip digitizing of Temperature and MR element Resistance value.  
Vendor ID and chip revision register.  
Illegal Multiple Device Selected detection.  
2 pads CS0 and CS1, hard wired, for separate activation for multiple pre-amplifiers operation.  
Requires one external resistor.  
2
APPLICATIONS  
Hard Disk Drive (HDD).  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
3
QUICK REFERENCE DATA  
SYMBOL  
VCC  
PARAMETER  
CONDITIONS  
MIN.  
+4.5  
TYP.  
+5  
MAX.  
+5.5  
UNIT  
DC Supply voltage  
V
V
VEE  
-4.5  
-5  
-5.5  
NF  
Noise Figure  
Note 3, Section 14  
1.7  
0.8  
1.7  
dB  
IRNV  
Input Referred Noise  
Voltage  
Rmr=66W; Imr=8mA;  
10 MHz<f<100 MHz  
nV/  
sqrtHz  
Avd  
Differential gain  
VIN=1mVpp @ 20 MHz,  
RLoaddif=330W, Imr=8mA,  
Rmr=66W,  
50  
dB  
GAIN0=0, GAIN1=1;  
fHR  
-3dB frequency bandwidth  
Common Mode Rejection  
Rmr=66W, Lmr=30 nH  
-3dB: without Boost SAL  
GMR  
225  
225  
MHz  
MHz  
CMR  
Imr=8 mA, Rmr=66W,  
10MHz<f<200MHz  
20  
40  
60  
dB  
dB  
dB  
1 MHz<f< 10 MHz  
f<100 kHz, 1mV input signal  
PSR  
Power Supply Rejection  
200mVpp on Vcc or Vee,  
Imr=8mA, Rmr=66W,  
10MHz<f<200MHz  
1 MHz<f<10 MHz  
f < 100 kHz  
20  
40  
60  
dB  
dB  
dB  
tr, tf  
Write Current Rise/Fall times Iwr=50 mA; f=20 MHz;  
(-0.8 * Iwr => +0.8 * Iwr)  
LH=75nH, RH=10W  
0.84  
ns  
IMR(PR)  
IWR(b-p)  
fsclk  
Programming MR bias  
current range  
SAL  
4
3
10.2  
6 .1  
mA  
mA  
GMR (see note section 10)  
Programming Write current  
range (base-to-peak)  
Rext = 10 kW  
10  
50.3  
mA  
Serial interface clock rate  
40  
MHz  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
4
DESCRIPTION  
The +/- 5.0 volt pre-amplifier for HDD described here has been designed for 12 terminals, comprised of a SAL or GMR  
magneto-resistive reader and an inductive thin film writer. In read mode, the device operates as a low noise differential  
preamplifier which senses resistance changes in the MR element that correspond to flux changes on the disk. In write  
mode, the circuit operates as a thin film head current switch, driving the inductive element of the head.  
The IC incorporates Read amplifiers with programmable gain and HF boosts, Write amplifiers, 3-wires Serial Interface,  
Digital-to-Analog Converters, Thermal Asperity Detector and Programmable Thermal Asperity Compressor, reference  
and control circuits which operate on a Dual Supply Voltage of +/-5V (+/-10%).  
The Read amplifier has programmable medium input impedance. The DC offset between the two terminals of the MR  
head is eliminated using on chip AC coupling. The bandwidth can be enhanced by using programmable high frequency  
gain-boost. Fast settling features are used to keep the transients short. As an option, the Read amplifier may be left  
biased during writing, so as to reduce the duration of these transients even further.  
The Write amplifier has a programmable current overshoot which may be added to the programmable steady state write  
current.  
Fault protection is provided for a variety of read or write unsafe conditions. For added data protection, internal pull up  
resistors are connected to RWN, CS0, CS1, STWN, WDP and WDN pins and pull down resistors are connected to SEN,  
SDATA, SCLK, DRN and BFAST pins, to prevent accidental writing due to open lines and to ensure the device will power  
up in a non-writing condition.  
On-chip Digital to Analog converters for MR bias current or power and Write current are programmed via a 3 wire Serial  
Interface. Head selection, Mode control, Testing and Servo Writing can also be programmed using the serial interface.  
In Sleep mode, the CMOS serial interface is operationnal. Fig 2 shows the block diagram of the IC. Invalid head select  
codes disable the writer, select the dummy head and trigger the FLT output.  
5
ORDERING INFORMATION  
EXTENDED TYPE NUMBER  
PACKAGE  
bare die  
bumped die  
TDA5360UH  
TDA5360UK  
Fig.1 Type Number  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
6
BLOCK DIAGRAM  
Av  
RDp  
On/Off  
hybrid  
sense  
V / I  
TA handling  
Rin:2bits  
Av  
out  
+
RDn  
d/dt  
RFE  
4 bits  
3bits 1.5 bit  
Read Back End  
hybrid  
sense  
TA handling  
Rin:2bits  
THERMAL  
ASPERITY  
DETECTOR  
FAULT  
DETECTION  
CODING  
FLT  
MR BIAS  
CURRENT  
/ POWER  
RFE  
Rmr measure  
temperatue  
SDATA  
SETTING  
SERIAL  
INTERFACE  
5 bits  
SCLK  
SEN  
DIGITIZER  
voltage  
driven  
WRITE  
CURRENT  
5 bits  
Rext  
BANDGAP  
WDp  
WDn  
WDI  
V/I  
WDI  
MUX  
Interface  
boost:2bits  
1 bit  
voltage  
driven  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
7
PAD ARRANGEMENT  
DRN  
WN7  
WP7  
BFAST  
SDATA  
SCLK  
RP7  
RN7  
RN6  
SEN  
FLT  
WDP  
WDN  
VCC  
VCC  
VCC  
RP6  
RWN  
WP6  
WN6  
SHIELDN  
RDN  
GND  
GND  
RDP  
CS0  
SHIELDP  
WN5  
WP5  
REXT  
CS1  
RP5  
RN5  
VCC  
VCC  
RN4  
RP4  
WP4  
WN4  
Fig.2 TDA5360 pad arrangement pads up.  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
8
PAD DESCRIPTION  
SYMBOL  
Pin  
Description  
VCC  
+5V supply  
Ground  
GND  
VEE  
-5V supply  
RDP,RDN  
RWN  
output  
Read Data, Differential read signal outputs  
Read/Write : read = HIGH, write = LOW  
logic input  
input  
WDP,WDN  
FLT  
Differential PECL or current mode write data input  
output  
In Write mode, a fault is flagged when FLT is high.  
In Read Mode, a fault is flagged when FLT is low.  
a 5kW external resistor must be connected between FLT and VCC.  
This pad is used as an input in MDS mode.  
input  
REXT  
SEN  
a 10kW external resistor must be connected between REXT and GND  
Serial Enable line. Active High  
logic input  
logic input  
SCLK  
SDATA  
Serial Clock line. 40 MHz max.  
logic  
Serial Data line. Bi-directional interface  
input/output  
BFAST  
DRN  
logic input  
logic input  
Controls reader passband or enables the Imr generator depending on the state  
of BFCTL bit from Reg.01  
Selects the dummy head or performs a system reset depending on the state of  
RSTDMY bit from Reg.09  
RP0...RP11  
RN0...RN11  
WP0...WP11  
WN0...WN11  
STWN  
input  
MR head connections, positive end  
MR head connections, negative end  
Write head connections, positive end  
Write head connections, negative end  
Set Low for Servo Track Write mode only  
Code for Chip ID  
input  
output  
output  
logic input  
logic input  
logic input  
CS0  
CS1  
Code for Chip ID  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
9
FUNCTIONAL DESCRIPTION  
9.1  
Active READ mode  
Taking RWN high and programming bits MODE0 and MODE1 (see Reg.09) selects the read mode.  
The Head select inputs, in serial register, select the appropriate head.  
In read mode, the circuit provides either a constant power bias or a constant current bias that flows from the P to the N  
side of the MR section of the head.  
The value of the current/power is programmed in Reg. 02 and is referenced by the external resistor, REXT, which is  
connected between the REXT pin and GND. The reference voltage on REXT pin is stable over the entire operating  
temperature range and process.  
The current or power in the MR element is constant over temperature.  
The resistance of the MR element, R  
head voltage. The circuit acts as a low-noise differential amplifier to sense this voltage change. The read amplifier  
outputs, RDP and RDN, are in phase with the MRP and MRN head ports.  
, changes in the presence of a magnetic field and causes a change in the MR  
MR  
The read data at pins RDP, RDN can output either voltage or current, depending on how the RVORI bit in Reg.01 is set:  
LOW or HIGH respectively.  
The polarity convention for current mode is :  
“positive” => pin with least current flowing  
“negative” => pin with most current flowing  
Write current is not present in read mode under any circumstances; either transient or steady state.  
The read path includes the following programmable features :  
Gain programmation (Reg. 02 and Reg. 03) :  
- gain only,  
- a combination of gain plus differentiator (therefore HF-gain-boost),  
- differentiator only.  
The gain is programmable with step of 3dB between 44dB and 50dB.  
Input impedance :  
With bits RIN1, RIN0 (Reg.01), the input impedance of the readpath can be programmed from 15 to 30W.  
Low Pole Frequency :  
Bits LFP (Reg.03) allow the programmation of the Low Pole Frequency from 1 to 4 MHz.  
Thermal Asperity Detection and Compression :  
Thermal Asperity Detector flags an error on FLT line when a thermal disturbance is detected and load the  
appropriate error code in Reg. 07. The threshold is programmable via Reg. 05.  
Thermal Asperity Compressor extracts the signal from the disturbance. Its thresholds levels and frequency  
response are also programmable with Reg.11.  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
9.2  
Active WRITE mode  
Taking RWN low from an Active READ mode selects the Active WRITE mode. The head select inputs, in a serial register,  
select the appropriate head.  
In write mode the circuit acts as a current switch with write current toggled between the P and N directions of the thin-  
film section of the selected head x. The signal polarity is noninverting from WDP, WDN to WPx, WNx.  
The write data at pins WDP, WDN could be driven by either a voltage or a current, according to the WVORI bit in Reg.01  
(set LOW or HIGH respectively.)  
The polarity convention for current mode is :  
“positive” => input pin with minimum current flowing  
“negative” => input pin with maximum current flowing  
The writer terminal voltages are driven to GND during read mode to avoid accidental discharges to the disc.  
Note that the write mode CAN NOT be selected directly from a sleep or standby condition.  
The steady state value of the write current is programmed in Reg. 04 and is referenced by the external resistor, REXT,  
which is connected between the REXT pin and GND. The reference voltage on REXT pin is stable over the entire  
operating temperature range and process.  
Internal compensation networks are optimized and provided to control the write current shape and settling characteristics  
based on specified head loads. The value can be programmed in Reg. 04.  
9.3  
Active STW mode  
In Active Read or Active Write mode, only one head in one preamp is selected.  
A special programmation of Reg. 09, using (STWN = LOW) AND (CS0 = CS1 = HIGH) allows the user to either :  
- select one head per preamp (if several preamps are adressed at the same time)  
- select one head in one preamp when in read mode but two heads in one preamp when going to write mode.  
In that case Head x and Head (x+6) will be selected, with x=0...5. Head x is selected via Reg. 00  
9.4  
STANDBY mode  
The standby mode is selected by programming bits MODE0 and MODE1. (see Reg.09)  
The internal write current source, and MR bias current source are deactivated while RDP, RDN and FLT outputs are in  
a high-impedance state so that they can be OR’d in multiple preamplifiers applications. The device is specially designed  
for reduced dissipation in this mode. Response time from Standby to Active Read mode is much shorter than from Sleep  
mode to Active Read. The CMM of RDP and RDN is the same as in Sleep or Active mode. (see Note 2)  
Internal fault detectors are powered off.  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
9.5  
SLEEP mode  
The sleep mode is selected by programming bits MODE0 and MODE1. (see Reg.09)  
In Sleep Mode, the IC is accessible via the Serial Interface. All circuits, other than those of the CMOS Serial Interface  
and the circuit which forces the data registers to their default values at power up and which fixes the DC level of RDp-  
RDn (required when operating with more than one amplifier), are inactive. Typical static current consumption is less than  
one mA, depending on the state of the logic pins where internal pull-up or pull-down resistors are connected. Dynamic  
current consumption during operation of the Serial Interface in the Sleep mode and owing to external activity at the inputs  
to the Serial Interface is not included. In all Modes including the Sleep mode, data registers can be  
programmed. Sleep is the default Mode at power-up. Switching to other modes takes less than 0.1 ms.  
The CMM of RDP and RDN is the same as in Standby or Active mode. (see Note)  
Internal fault detectors are powered off.  
Note 1 : At power-up, as long as DRN pin is LOW, a reset of the Serial Interface registers occurs. Before any register  
programmation, the user should first force DRN pin to HIGH in order to exit the reset mode and enable a register  
programmation. See description of DRN function in (10.6).  
Note 2 : As a goal, the CMM of RDP and RDN is identical in all operating modes. The term “high-impedance” here means  
at least 10 to 20 kOhm from RDP or RDN to an internal CMM voltage reference.  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
10 BIASING OF THE MR ELEMENT  
This preamplifier has been designed for SAL and GMR elements. Programming bit GMR in Reg. 01 select either a SAL  
range (LOW) or a GMR range (HIGH).  
By programming bit PORI in Reg. 01, the user can program either a constant current bias (LOW) or a constant power  
bias (HIGH) for the MR element. The value of the current/power is programmed on 5 bits via Reg. 02.  
If bit PORI in Reg. 01 is HIGH, a constant power bias is maintained accross the MR element.  
The power is defined as :  
Pw = R  
* I  
MR MR  
2, where Pw is constant over temperature and process.  
In power bias mode, two power ranges are possible :  
For SAL heads  
For GMR heads  
1.5mW to 9.25 mW in steps of 0.25mW  
375uW to 2.3 mW in steps of 0.0625mW  
Note :  
whatever Power programmation is used, the IMR current flowing into the MR element will be within the min-  
max range given below.  
If bit PORI in Reg.01 is LOW, then the biasing scheme shall revert to constant current instead of constant power.  
is then constant over temperature and process.  
I
MR  
In current bias mode, two current ranges are possible :  
For SAL heads :  
For GMR heads :  
4 to 10.2 mA in steps of 0.2 mA  
3 to 6.1 mA in steps of 0.1 mA  
Note :  
In GMR mode, I  
current is guaranted up to 5.1mA  
MR  
6.1mA can be reached under certain supplies/Rmr conditions.  
10.1 MR Head Resistance and Temperature Measurement  
By programming RANGE0,RANGE1 bits in Reg. 08, the user can select either a Rmr measurement or a Temperature  
measurement (junction temperature).  
Setting DIGON bit HIGH launch a digitazation  
The settling time of the digitization operation is less than TBD ms.  
A 5 bit code is then available in Reg. 08, as long as DIGON stays HIGH,  
Setting DIGON bit LOW, reset the 5 bit code.  
In case of Rmr measurement, the user have access to two Rmr range by programming RANGE0 and RANGE1 bits.  
In case of Temperature too high condition (T > 140oC), during a Temperature measurement, a Fault is triggered on FLT  
line and a error code is available in Reg. 07.  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
10.2 Fault Mode  
Fault conditions are indicated on the FLT pin (HIGH during write mode and LOW during read mode). The fault condition  
is coded and stored in Reg. 07 for monitoring purposes. The fault code is cleared on power up, on system reset and on  
writing to Reg.09  
The FLT output is an open collector to an external resistor of 5Kohms connected to +5V.  
Table 1: Fault Conditions  
Mode  
Both  
Read  
Fault condition  
FCOD3  
FCOD2  
FCOD1  
FCOD0  
No fault  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write current present  
Fault code not used  
Thermal Asperity detected  
Read head open  
Write  
Both  
No write current  
Write Data frequency to low  
Write head open  
Write head shorted to GND  
Rext open or short  
Write to read head short  
Low Vcc or Low Vee  
Fault code not used  
Illegal head address  
Fault code not used  
Temperature too high 140 C  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
The following are valid READ fault conditions which set FLT=LOW  
·
·
·
·
·
·
Rext pin open or shorted to GND or Vcc  
Thermal Asperity detected  
Read Head open  
Power supplies too low (VCC and/or VEE)  
Write current present in read mode  
Illegal head address ( i.e. head 12, 13, 14 or 15)  
In this case, besides asserting the fault flag, the MR bias current is diverted to the dummy head.  
The following are valid WRITE fault conditions which set FLT=HIGH. An action can eventually be taken :  
FAULT  
ACTION  
·
No write current in write mode  
Disable write current  
·
·
·
·
·
Rext pin open or shorted to GND or Vcc  
Open write head or shorted to GND  
Write data frequency too low  
Disable write current  
Do not disable write current  
Do not disable write current  
Disable write current  
Power supplies too low  
lllegal head address (i.e. HD 12, 13, 14, 15)  
Disable write current  
If the write current is disabled, the writer is powered down. The only way to restart a write sequence is to switch R/W  
high and then to switch R/W low again.  
Trying to go in Write mode from a sleep or standby mode condition will disable the write current.  
If two fault conditions occurs nearly at the same time, the first to occur will be loaded in Reg. 07.  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
10.3 Serial Interface Address bit Allocation  
Register  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS1  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
CS0  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
RWN  
1
2
3
4
5
6
7
8
9
10  
11  
10.4 Serial Interface Register bit Allocation  
9
Register  
D7  
HS3  
X
D6  
HS2  
PORI  
PWR4  
HFZ2  
IW3  
TAD  
VEND6  
FLT2  
M3  
D5  
HS1  
GMR  
PWR3  
HFZ1  
IW2  
TAC  
VEND5  
FLT1  
M2  
D4  
D3  
D2  
D1  
D0  
0
HS0  
RIN1  
SELT  
RIN0  
SELF  
RVORI  
PWR0  
X
LCS1  
WVORI  
GAIN1  
LFP1  
LCS0  
1
BFCTL  
GAIN0  
LFP0  
2
DUMMY  
HFZ3  
IW4  
TRANGE  
VEND7  
X
PWR2  
HFZ0  
IW1  
PWR1  
X
3
4
IW0  
WCP2  
TAD2  
VEND2  
FCOD2  
WCP1  
TAD1  
WCP0  
TAD0  
5
TAD4  
VEND4  
FLT0  
M1  
TAD3  
VEND3  
FCOD3  
M0  
6
VEND1  
FCOD1  
VEND0  
FCOD0  
DIGON  
MODE0  
X
7
8
M4  
RANGE1 RANGE0  
9
X
X
X
X
SIOLVL RSTDMY MODE1  
10  
11  
X
X
X
X
X
X
X
X
X
X
ENFST  
TAU  
TACT2  
TACT1  
TACT0  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
10.5 Serial Interface Operations  
The serial interface communication consists of an adress word of 8 bits followed by a data word of 8 bits. See section  
11, page 24 and 25 for timing diagrams.  
10.5.1 SERIAL ADDRESSING  
When SEN goes HIGH, bits are latched-in at rising edges of SCLK. The first eight bits a7-a0 starting with the LSB, are  
shifted serially into an address register.  
If SEN goes LOW before 16 bits have been found, then the operation is ignored.  
When STWn is HIGH; if a1 does not match CS0 or a2 does not match CS1, then the operation is ignored.  
When STWn is LOW; if a1 and a2 are not HIGH, then the operation is ignored.  
Bits a3 to a6 constitute the register address. Bit a7 is an unused one.  
If  
or if  
(a0, a1, a2, STWn) = (0, CS0, CS1, 1)  
(a0, a1, a2, STWn) = (0, 1, 1, 0)  
then a PROGRAMMING sequence starts (see Reg. 09 description for details about preamp addressing)  
If  
or if  
(a0, a1, a2, STWn) = (1, CS0, CS1, 1)  
(a0, a1, a2, STWn) = (1, 1, 1, 0)  
then READING data from the pre-amplifier can start. The data read back can be either 3.3V compatible or 5V  
compatible depending on SIOLV bit in Reg. 09.  
10.5.2 PROGRAMMING DATA  
During a programming sequence, the last eight bits d0-d7, before SEN goes LOW, are shifted into an input register.  
When SEN goes LOW, the communication sequence is ended and the data in the input register are copied in parallel to  
the data register corresponding to the decoded address a6-a3. SEN should go LOW at least 5ns after the last rising  
edge of SCLK.  
10.5.3 READING DATA  
Immediately after the IC detects a reading sequence, data from the data register (address a6-a3) are copied  
in parallel to the input register. The LSB d0 is placed on SDATA line followed by d1 at the  
next falling edge of SCLK, etc...  
If SEN goes LOW before 8 address bits (a7-a0) have been detected, the communication is ignored. If SEN goes LOW  
before the 8 data bits have been sent out of the IC, the reading sequence is immediately interrupted.  
SEN must stay LOW at least 75ns between two adressings.  
See Timing diagramms for Serial Adressing on section 11.  
10.5.4 BROADCAST MODE  
When A1=A2=1 and STWN=LOW, all the preamps will be adressed whatever their CS1/CS0 setup is.  
This mode allows parallel programming of any register of the serial interface, and allows STW mode programming (See  
Reg. 09 description).  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
10.6 Registers description  
Nb  
0
Register Name  
Contents  
Head Select Register  
HS3..HS0 = 0,0,0,0 to 1,0,1,1 = H0 to H11  
SELT : if HIGH, the multiple selection detector is enabled. Inactive in STW mode  
SELF : is set HIGH if illegal MDS is detected (read back only bit)  
( Note 0 )  
LCS1,LCS0 : copy of CS1,CS0 pins state (read back only bits)  
PORI : Select a MR Bias mode.  
1
Control Register  
LOW = Current  
HIGH = Power  
Bias  
Bias  
GMR : select the range to be used in current or power  
LOW = SAL  
HIGH = GMR  
range  
range  
RIN1,0 = define the input impedance of the reader.  
(0,0)  
(0,1)  
(1,0)  
(1,1)  
=
=
=
=
30W  
23W  
18W  
15W  
RVORI = Reader output buffer mode.  
LOW  
HIGH  
=
=
Voltage mode  
Current mode  
WVORI = Writer data inputs mode.  
LOW  
HIGH  
=
=
Voltage mode,  
Current mode  
( Note 1a)  
BFCTL = Control of BFAST pin functionality  
( Note 1b)  
2
Reader Bias Register DUMMY : Dummy head is selected in read mode if LOW  
PWR4...PWR0 = define Imr current/power.  
Range according to GMR bit setting  
Rmr current bias mode :  
SAL : Imr = 4mA+200uA*(pwr0 + 2 * pwr1 + 4 * pwr2 + 8 * pwr3 + 16 * pwr4)  
GMR : Imr = 3mA+100uA*(pwr0 + 2 * pwr1 + 4 * pwr2 + 8 * pwr3 + 16 * pwr4)  
Rmr power bias mode :  
SAL : Pwr = 1.5mW+250uW*(pwr0 + 2 * pwr1 + 4 * pwr2 + 8 * pwr3 + 16 * pwr4)  
GMR : Pwr = 375uW+62.5uW*(pwr0 + 2 * pwr1 + 4 * pwr2 + 8 * pwr3 + 16 * pwr4)  
GAIN1, GAIN0 = read amplifier gain.  
(0,0) = 44 dB  
(0,1) = 47 dB  
(1,0) = 50 dB  
(1,1) = Differentiator only  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
3
Reader Bandwith  
Register  
HFZ3, HFZ2, HFZ1, HFZ0 = high frequency gain boost/ differentiator control  
( Note 3 )  
LFP1, LFP0 = low frequency pole.  
(0,0) =1 MHz  
(0,1) =2 MHz  
(1,0) =3 MHz  
(1,1) =4 MHz  
4
5
Writer Bias Register  
IW4, IW3, IW2, IW1, IW0 = 5 bits to define Iwr current :  
Iwr = 10mA + 1.3mA*(IW0+2*IW1+4*IW2+8*IW3+16*IW4)  
WCP2...WCP1 = 3 bits for the write current overshoot  
(Note 4)  
Thermal Asperity  
Detection  
TRANGE = if HIGH, the TA detector range is shifted up 3.17mV  
TAD = if HIGH, the TA detection circuits are enabled  
TAC = if HIGH, the TA Compression circuits are enabled  
TAD4..TAD0 = 5 bits for TAD threshold programmation (referred to the input)  
Vth(mV) =  
(Note 5)  
0.390  
3.170*TRANGE  
0.177*(TAD0 + 2*TAD1 + 4*TAD2+ 8*TAD3 + 16*TAD4)  
+
+
6
7
Vendor Register  
VEND7...VEND0 = 8 bits for identification (read back only bits)  
7 6 5 4 3 2 1 0  
0 0 1 0 0 0 1 1 = rev1  
0 1 0 0 0 0 1 1 = rev2  
Fault Management  
Register  
FLT2...FLT0 = 3 bits to set the reporting of a fault condition :  
000 = report all fault detected  
001 = Disable low supply fault  
010 = Disable temperature too high fault  
011 = Disable write head open/short fault  
100 = Disable write data frequency too low fault  
101 = disable MR power too high fault  
110 = Disable TA Detected fault  
111 = Disable all faults  
FCOD3...FCOD0 = 4 bits for encoding the fault conditions (read back only bits)  
( Note 7 )  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
8
Measurement Register M4...M0 = 5 bits for Rmr/Temperature digitazation (read back only bits)  
RANGE1,RANGE0 = 2bits to define which measurement to be done  
(0,0) RMR measurement for 15W < Rmr < 46W  
Rmr = 698 / (15.5 + M0 + 2*M1 + 4*M2 + 8*M3 + 16*M4)  
(0,1) and (1,0) : RMR measurement for  
40W < Rmr < 90W  
Rmr = 2094 / ( 21 + M0 + 2*M1 + 4*M2 + 8*M3 + 16*M4 )  
(1,1) = Temperature measurement  
Temp = 473K - 4.6K * (M0 + 2*M1 + 4*M2 + 8*M3 + 16*M4)  
DIGON = is set HIGH to launch a digitazation  
( Note 8 )  
9
Operating mode  
Register  
SIOLVL = level of SDATA when reading back a register  
if LOW,  
if HIGH,  
3.3V compatible.  
5.0V compatible.  
RSTDMY = define functionality of DRN pin  
( Note 9a)  
MODE1,MODE0 = 2 power management control bits.  
(0,0)  
(0,1)  
(1,0)  
(1,1)  
Sleep Mode  
Standby Mode  
Active Mode or STW one head  
Test Mode or STW two heads  
(Note 9b)  
11  
Thermal Asperity  
Compression  
ENFST = when TAC is enable, this bit defines BFAST functionality  
( Note 11a)  
TAU = Low Pole Frequency time constant of the TAC  
LOW  
HIGH  
=
=
700 ns  
70 ns  
TACT2,TACT1,TACT0 = 3 bits to determine the TAC threshold  
(0,0,0)  
(0,0,1)  
(0,1,0)  
(0,1,1)  
(1,0,0)  
(1,0,1)  
(1,1,0)  
(1,1,1)  
=
=
=
=
=
=
=
=
4.00 mV  
2.97 mV  
2.21 mV  
1.64 mV  
1.22 mV  
0.91 mV  
0.67 mV  
0.50 mV  
( Note 11b )  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
Note 0 : MDS (Multiple Device Selected) detector :  
When several preamps are connected in parallel, this function allows the user detection of wrong adressing  
withing the preamps.  
When SELT is high, the selected preamp pull a precise current on FLT pin. If only one preamp has reacted,  
SELF is LOW. If more than one preamp has reacted, the voltage on FLT pin is lower than a reference voltage  
and thus SELF is HIGH.  
Note 1a : The Write path can be controled by either a voltage or a current input signal.  
The signal polarity is non inverted from WDP - WDN input to WPx - WNx output  
Voltage mode :  
Current mode :  
WDP-WDN > 0 => WPx-WNx > 0 (current flowing externally from WPx to WNx)  
current has to be pulled from WDP and WDN pins.  
The positive side for signal, is the one where the least current is pulled  
The negative side for signal, is the one where the most current is pulled  
most current pulled from WDN => current flowing externally from WPx to WNx)  
Note 1b : BFCTL define BFAST functionality :  
BFCTL  
LOW  
BFAST  
Function  
LOW  
HIGH  
LOW  
HIGH  
IMR generator ON (Reader ON) during write  
IMR generator OFF (Reader OFF) during write  
Normal Reader PassBand  
LOW  
HIGH  
HIGH  
Low Frequency corner increased to 8 MHz  
See ENFST bit in Reg. 11 for restrictions of BFAST functionality  
Note 3 : For differentiator only (GAIN0 = GAIN1 = 1),  
the midrange setting ( HFZ3 = 1, HFZ0 = HFZ1 = HFZ2 = 0 ) have a gain of 44dB at 100 Mhz.  
i.e. gain (@100 Mhz)= 80 +10 * (HFZ0 + 2*HFZ1 + 4*HFZ2 + 8*HFZ3)  
For gain plus differentiator (other GAIN0, GAIN1 programmation)  
the midrange setting (HFZ3=1, HFZ0,1,2=0) create a zero at 300 Mhz independent of the gain bits.  
HF Zero @ f = 2400 MHz / (HFZ0 +2*HFZ1 + 4*HFZ2 +8*HFZ3)  
i.e. gain = 150 + 75 * ( GAIN0 + 2*GAIN1 - 5*GAIN0*GAIN1)  
Note 4 : In order to increase performance for high data rate, 3 bits are available to tune the write current waveform.  
WCP2 : this bit is used to add a capacitive boost during a transition of the write current.  
WCP1,WCP0 : these bits are used to increase the internal swing on the write data signal.  
when IW4 is HIGH ( Iwr > 30.8 mA), some capacitive compensation is also activated in the write driver.  
Note 5 : The threshold range of the TAD can be shifted up by 50% by setting TRANGE HIGH.  
In that case the steps are still 177uV,  
but the range is shifted from ( 0.390mV-5.877mV ) to ( 3.560mV-9.047mV )  
The relation between the threshold of the TAD programmed in Reg. 05 and the real threshold is a function of  
the input impedance of the reader and the low corner frequency of the reader.  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
Formula to link real TAD threshold with LF pole of the reader and programmed input impedance :  
0.85  
Vth = Vthprog ´ ---------------------------------------------------------  
2
fLFP  
(K ´ fTA )  
æ
ö
ø
1 + ------------------------  
è
K ´ -------------------------------------------  
2
fLFP  
fTA  
æ
ö
1 + ------------  
è
ø
where :  
and :  
fLFP is the low frequency pole of the read amplifer (1 to 4 MHz, programmable via Reg. 03)  
fTA is the frequency of the principal harmonic of the TA signal.  
RINnom  
K = ----------------------------------------  
RINnom + RMR  
where :  
RINnom is the input impedance of the reader in mid-band (programmable via Reg. 01)  
For RINnom = 18W, RMR = 66W, fTA = 2MHz, Tj = 70oC, we have K = 0.214  
and so,  
Vth( fLFP = 1MHz) = Vthprog * 1.747  
Vth( fLFP = 4MHz) = Vthprog * 0.945  
Note 7: FAULT code protocol.  
When a fault occurs, the FAULT pin is set LOW (if read mode) or HIGH (if write mode) and a 4 bits code is  
available in Reg. 07 (See Section 10.2 for details).  
The FAULT pin is flagged as long as the error remains present. When the error condition is removed, the  
FAULT pin toggles to a non-error state, but the 4 bits code still remains present in Reg. 07  
To Reset the FAULT code, the user should reprogramm Reg. 09.  
Some fault detections can be inhibited via FLT2,1,0 bits. If an action is linked to the inhibited detection (for  
example inhibiting the write current when a low power supply condition occurs), then the action is still taken,  
but no fault code and no FAULT pin toggling occurs.  
Note 8 : RMR and Temperature Digitizer  
- RMR digitizer  
This measurement can only be done in Read mode, with the head to be measured selected.  
the Digitazation is launched when DIGON toggles from LOW to HIGH,  
after a maximum of TBD us, a 5 bits code is available in Reg. 08.  
The 5 bits code will only be reseted by DIGON toggling from HIGH to LOW.  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
- Temperature digitizer  
This measurement can be done either in Active Read mode or in Active Write mode.  
Note 9a : RSTDMY define DRN pin functionality  
RSTDMY  
LOW  
DRN  
LOW  
HIGH  
LOW  
HIGH  
Function  
Serial Interface register reset  
No effect  
LOW  
HIGH  
No effect  
HIGH  
Dummy Head selected in read mode  
Note 9b : MODE1,MODE0 power management control bits  
A2 A1 Mode1 Mode0 STWN  
CS1 CS0  
CS1 CS0  
CS1 CS0  
0
0
1
1
1
1
x
0
1
0
0
1
1
x
x
x
1
0
1
0
1
Sleep  
Standby  
Active Read or Write  
1
1
Active STW with one head  
Test mode  
CS1 CS0  
1
1
1
1
Active STW with 2 heads in write mode  
Forbidden : no change in register  
- Test mode is a state where both Reader and Writer are ON when R/W pin is LOW : in write mode, reader  
signal is present at RDP-RDN output pins.  
- (A2=A1=1 and STWN=0) is a broadcast mode condition, where all the preamps will treat the data arriving on  
SDATA line.  
- In order to get two write head selected, Head Hx should be programmed in Reg. 00 (x = 0 to 5). In that case  
Head Hx and Head H(x+6) will be selected in STW (Servo Track Write) 2 heads.  
Note 11a : ENFST define BFAST pin functionality when Thermal Asperity Compression is ON  
ENFST  
LOW  
BFAST functionality  
inhibit BFAST control of the passband  
enable BFAST control of the passband  
HIGH  
Note 11b : Thermal Asperity Compression ( TAC ) functionality  
When a thermal asperity occurs at the reader input, the reader output signal get superposed with an amplified  
signal corresponding, to a certain extent, to the thermal asperity.  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
The aim of the TAC is to limit the amplitude and the duration of the perturbation seen at the reader output.  
Because thermal asperity amplitude is not constant, the TAC need some threshold programmation to define  
the sharpness of the response.  
note that reducing the TAC threshold also impact the Low corner frequency value of the read amplifier.  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
11 SERIAL INTERFACE TIMING  
READ  
t > 5ns  
t > 5ns  
1.5 Tclk  
SEN  
2 Tclk  
1 Tclk  
SCLK  
SDATA  
d1  
d2  
d3  
Data  
d6  
d7  
d0  
d5  
d4  
a0=1 a1  
a2  
a3  
a4  
a5  
a6  
a7  
Address  
When Fclk > 20 MHz and a register reading is performed, it is necessary to extend the clock period as above  
When Fclk < 20 MHz, this is not necessary  
WRITE  
SEN  
1 Tclk  
0.5 Tclk  
SCLK  
SDATA  
d1  
d2  
d3  
Data  
d5  
d7  
d0  
d5  
d4  
a1  
a2  
a3  
a4  
a5  
a6  
a7  
a0=0  
Address  
0...Reg.00H  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
t_sen_sen  
SEN  
tr  
tf  
tclkperiod  
tf_sclk_sen  
trsen_sclk  
SCLK  
tclkwidth  
thold  
tsetup  
tr  
tclklow  
SDATA  
SEN timing  
Description  
Min  
5
Nom  
2
Max Unit  
tr_sen_sclk  
tf_sclk_sen  
tr,tf  
90% of SEN to 10% of SCLK  
last SCLK to 90% of SEN  
rise/fall time 10%-90%  
delay between 2 SEN  
ns  
ns  
5
Tclk/4 ns  
ns  
t_sen_sen  
SCLK timing  
frequency  
tr , tf  
75  
40  
MHz  
rise/fall time 10%-90%  
2
Tclk/4 ns  
tclklow  
10% of SEN to CLK state change  
5(*)  
ns  
ns  
tclkwidth  
SDATA timing  
tsetup  
TBD  
data setup time before 10% of SCLK  
data hold time after 90% of SCLK  
5
5
Tclk/2 ns  
Tclk/2 ns  
thold  
(*) either positive or negative, but ABS (tclklow) > 5ns  
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
12 ELECTRICAL PARAMETERS  
12.1 DC Characteristics  
Unless otherwise specified, recommended operating conditions apply  
CS0=CS1=LOW, DRN=HIGH, BFAST=LOW, STWn=HIGH, RIN=18 Ohm, LFP = 1MHz, Imr = 8mA, Rmr = 66 Ohm  
Iwr = 30.8mA.  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Read Mode, I  
= 8mA  
65  
75  
85  
mA  
MR  
I
VCC Supply Current  
Write Mode, I  
= 30.8 mA 100  
130  
175  
mA  
CC  
WR  
Standby Mode  
Sleep Mode  
200  
200  
1400  
700  
-12  
2500  
2000  
-8  
uA  
uA  
mA  
Read Mode, I  
= 8mA  
-20  
MR  
I
VEE Supply Current  
Power Dissipation  
Write Mode, I  
= 30.8 mA -150  
-80  
-60  
mA  
EE  
WR  
Standby Mode  
Sleep Mode  
-200  
-200  
-5  
0
uA  
-5  
0
uA  
Read Mode, I  
= 8mA  
365  
435  
525  
mW  
MR  
Pw  
(T =105°C)  
J
Write Mode I  
TTL  
= 30.8 mA 800  
1050  
1625  
0.8  
5
mW  
V
WR  
V
Input Low Voltage  
Input High Voltage  
Input Low Current  
0
IL  
V
TTL  
2.4  
V
IH  
I
PECL  
TTL  
50  
uA  
uA  
IL  
V
= 0.8 V  
-160  
IL  
I
Input High Current  
PECL  
TTL  
50  
80  
uA  
uA  
IH  
V
= 2.4V  
IH  
VOL  
VOH  
Output Low voltage  
Output High voltage  
SDATA  
I
= 4mA  
0.4  
V
OL  
SDATA 5V mode  
SDATA 3.3V mode  
3.6  
2.4  
Vcc  
3.6  
V
V
I
Output High Current  
Output Low Voltage  
FLT  
V
= 5.0V  
50  
uA  
V
OH  
OH  
V
FLT  
I
= 4mA  
0.4  
OL  
OL  
High level WDP and WDN  
PECL  
Current mode (Note2)  
(Note 1)  
Vcc  
0
V
mA  
-0.25  
Low level WDP and WDN  
|WDP-WDN| PECL swing  
PECL (Note 1)  
Current mode (Note 2)  
2.4  
- 4  
V
mA  
-1  
Voltage mode selected  
peak to peak (Note 1)  
0.4  
1.5  
V
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Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
Voltage compliance for WDP  
and WDN in current mode  
CMM of the inputs  
in current mode  
1.5  
Vcc -1.7  
4.20  
V
V
V
V
Fault Threshold  
Fault Threshold  
Hysteresis=100mV +/- 10% 3.80  
Hysteresis=100mV +/- 10% -4.20  
4.00  
V
V
CCTL  
CC  
V
-4.00 -3.80  
EETL  
EE  
12.2 Read Characteristics  
Unless otherwise specified, recommended operating conditions apply.  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP MAX UNIT  
I
MR Current Range  
SAL  
GMR  
4
3
8
10.2  
6
mA  
MR  
Pwr  
MR Power Range  
SAL  
GMR  
(Note 3)  
1.500 4.2  
9.25  
2.30  
mW  
mW  
0.375  
-5  
1
MR Power Tolerance  
3 < I  
< 10mA  
+5  
%
MR  
MR Bias Current Overshoot  
RMR Digitizer Accuracy  
Rext Reference Voltage  
0
%
%
V
5
V
Rext  
1.31  
A
Vd  
Differential Voltage Gain  
V
= 1mV  
@ 20MHz,  
IN  
PP  
48  
50  
52  
dB  
R
dif = 330 Ohm,I  
=8mA,  
Load  
MR  
R
= 66 Ohm,  
MR  
RIN = 18 Ohm,  
GAIN0=0, GAIN1=1,GMR=0  
f
Passband Upper -3dB  
Frequency  
R
= 66W;L  
MR  
MR  
=30nH  
HR  
225  
MHz  
MHz  
- 3dB. Without boost.  
f
Passband Lower -3dB  
Frequency  
R
= 66W; L  
MR  
= 30nH;  
3
LR  
MR  
LPF0=0  
LPF1=1  
IRNV  
Input referenced noise voltage  
(including MR bias current noise,  
excluding Rmr noise)  
R
= 66W; I  
MR  
=8mA  
MR  
0.8  
nV/  
÷sqrt  
Hz  
10 MHz<f<100 MHz, GMR=0  
(Note 4)  
MR bias current noise  
I
I
=8mA 10 MHz<f<100MHz  
=5mA 10 MHz<f<130MHz  
8
5.7  
pA/  
sqrt÷  
Hz  
MR  
MR  
NF  
Noise figure  
(Note 5)  
1.7  
350  
3
dB  
HF noise +3dB frequency  
LF noise +3dB frequency  
Preamp noise=head noise  
Preamp noise=head noise  
MHz  
MHz  
1998 July 30  
27  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
C
R
Differential Input  
Capacitance  
10  
pF  
IN  
IN  
Differential Input  
Resistance  
RIN0=0, RIN1=1  
18  
Ohm  
DR  
Dynamic Range  
AC input where AVd falls to  
90% of its value at@f = 20MHz  
TBD  
mV  
PP  
CMR  
Common Mode Rejection  
I
= 8mA, R  
= 66W,  
MR  
MR  
20  
40  
60  
dB  
dB  
10 Mhz < f < 200 Mhz  
1 Mhz < f < 10 Mhz  
f < 100 KHz, GMR=0,  
1mV input signal  
PSR  
CS  
Power Supply Rejection  
from a signal on VCC, VEE or any  
logic pin, to RDP, RDN  
300mV  
P-P  
on V  
or V  
EE  
,
CC  
= 8mA, R =66W,  
I
MR  
MR  
20  
40  
60  
10 Mhz < f < 200 Mhz  
1 Mhz < f < 10 Mhz  
f < 100 KHz, GMR=0  
Channel Separation  
Unselected Channels:  
V
= 1mV  
50  
dB  
IN  
PP  
1 < f < 200 MHz  
V
Output Offset Voltage  
IMR=8mA, RMR=66W,  
GAIN0=GAIN1=0, GMR=0  
100  
mV  
OS  
V
Common Mode Output Voltage  
2.45  
17.5  
V
OCM  
R
Single-Ended Output  
Resistance  
Ohm  
SEO  
I
Output Current  
AC Coupled Load, RDP to RDN  
RVORI = HIGH  
O
TBD  
4
RVORI = LOW  
mA  
MR head potential  
From any point to GND  
First 10 harmonics  
-500  
+500 mV  
THD  
Total Harmonic Distortion  
0.5  
%
I
MR Head-to-Disc Contact Current  
Extended contact  
Maximum Peak Discharge for  
<20ns  
100  
20  
uA  
DISK  
mA  
C
=300pF,R  
=10MW  
DISK  
DISK  
(READ)  
DV  
Common Mode Output Voltage  
Change  
V
-
V
100  
40  
mV  
nS  
OCM  
OCM  
OCM  
(WRITE)  
TA Detection Response Time  
TA occurred to FLT active  
20  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
12.3 Write Charateristics  
Unless otherwise specified, recommended operating conditions apply,  
I
=50mA, L =75nH, R = 10W, f  
DATA  
=5MHz, Ambient temperature.  
W
H
H
SYMBOL PARAMETERS  
Write Current Range  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
I
10  
30.8  
50.3  
mAPK  
WR  
DIWR / IWR Write Current Tolerance  
-7  
7
1
%
Differential Head Voltage  
Swing  
Iwr = 50mA  
TBD  
16  
30  
V
PP  
I
f
Unselected Head Current  
Glitch  
I
= 50mA  
mA  
UH  
W
PK  
Write Data Frequency for  
Safe Condition  
FLT = Low  
1
MHz  
Ohm  
DATA  
R
Differential Output  
Resistance  
60  
O
O
C
A
Differential Output  
Capacitance  
6
pF  
ns  
Asymmetry  
Write Data has 50% duty cycle &  
0.5ns rise/fall time, load=short  
0.1  
SYM  
(A  
= |tr-tf| )  
SYM  
t , t  
Rise/Fall Time  
(-0.8 * IWR => +0.8 * IWR  
10-90%; I = 50mA  
W
LH=75nH, RH=10W  
0.84  
2.5  
ns  
ns  
%
r
f
)
T
Write Current Settling Time  
Write Current Overshoot  
I
= 50mA,  
WSET  
WR  
LH=75nH, RH=10W  
W
I
= 50mA,  
20  
COV  
W
LH = 75 nH, RH = 10W  
WCP0,1,2 = 000  
1998 July 30  
29  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
12.4 Switching Characteristics  
Unless otherwise specified, recommended operating conditions apply  
PARAMETER  
CONDITIONS  
(Note 6)  
MIN  
TYP  
MAX  
UNIT  
SI  
t
Serial Interface timing  
R/WN to Write Mode  
To 90% of write current  
50  
50  
ns  
RW  
SEN to Write Mode  
R/WN to Read Mode  
To 90% of write current  
ns  
ns  
t
Reader outputs loaded with high-  
pass single ended filters :  
R=165W, C=270pF  
Writer output shorted  
(Note 7)  
175  
WR  
t
t
CS to Read Mode  
Head Switching  
Reader outputs loaded with high-  
pass single ended filters :  
R=165W, C=270pF  
1
1
us  
us  
CS  
Reader outputs loaded with high-  
pass single ended filters :  
R=165W, C=270pF  
HS  
t
t
CS to Unselect  
Safe to Unsafe  
To 10% write current  
50  
1
ns  
us  
RI  
50% WDP to 50% FLT  
when a low frequency condition  
occurs.  
D1  
t
t
Unsafe to Safe  
50% WDP to 50% FLT  
20  
ns  
ns  
D2  
D3  
T
Head Current Propagation  
Delay  
From 50% of WDP to 50% of write  
current, load=short  
5
1
MR Bias Current Settling  
Time  
I
= 8mA, R  
=66W  
MR  
us  
RSET  
MR  
(Note 8)  
Notes:  
1. The differential peak to peak voltage swing could be from 0.4V to 1.5V and the common mode should be such that  
for any of the two states the maximum High shall be less than Vcc and the minimum LOW shall be more than 2.4V.  
2. In current mode, a ratio of at least 5 sould exist between the HIGH and LOW level currents.  
3. Whatever constant power is programmed, the value of the Imr current can not exceed the limits given in the constant  
current mode.  
4. The input referred noise voltage, excluding the noise of the MR resistor iis defined as follows :  
vn = -------------- 2 4 ´ k ´ T ´ RMR  
2
vnout  
Av  
æ
ö
è
ø
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
5. The noise figure is defined as :  
NF[dB] = 10xlog[(Vnout/Av)2 / (4kTxRMR)]  
where Av is the gain and Vnout is the noise voltage at the output of the amplifier  
6. See Section 11 for Serial Interface timing diagrams  
7. This tWR is defined for a specific load on RDP,RDN reader outputs :  
RDP  
RDN  
RDPch  
330 Ohm  
270pF  
270pF  
RMR  
Av  
RDNch  
tWR is the time between R/Wn going HIGH and the time when :  
90% of the signal envelop is present at RDPch-RDNch  
AND  
the differential DC decaying at RDPch-RDNch is below 10mV :  
RDPch-RDNch  
10mV  
R/Wn  
tWR  
Changing the load of the preamp will change tWR according to the new RC time constant.  
8. When changing MR bias current, from SEN to 90% of IMR bias current.  
1998 July 30  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
13 LIMITING VALUES / RECOMMENDED OPERATION CONDITIONS  
In accordance with the Absolute Maximum System (IEC 134)  
SYMBOL  
VCC  
PARAMETER  
CONDITIONS  
MIN.  
4.5  
TYP  
5.0  
MAX.  
5.5  
UNIT  
Positive Supply voltage  
range  
note1  
V
V
V
V
V
VEE  
Negative Supply voltage  
range  
note 2  
-4.5  
2.4  
0
- 5.0  
-5.5  
VCC  
0.8  
VIH  
High level CMOS input  
voltage  
VIL  
Low level CMOS input  
voltage  
Vi(dif)(p-p)  
Differential Peak to Peak  
input voltage  
0.4  
0.7  
3.2  
1.5  
High level PECL input  
voltage  
VCC  
V
V
(Writer input)  
Low level PECL input  
voltage  
2.4  
0.4  
2.8  
0.8  
Imode  
Differential Peak to Peak  
input current  
1.0  
mA  
(Writer input)  
High level input current  
-1.4  
0
-1.2  
mA  
Low level input current  
Ambient temperature  
Junction temperature  
-0.4  
55  
-0.1  
70  
mA  
°C  
°C  
Tamb  
Tj  
when reading  
when writing  
70  
110  
130  
86  
RMR  
Ll(tot)  
MR element resistance  
46  
-
66  
17  
Ohm  
nH  
Total lead inductance to  
the head  
in each lead  
Rl(tot)  
Total lead resistance to the in each lead  
head  
-
1.5  
Ohm  
VMR  
Voltage accross MR  
element (RPx-RNx)  
1
3
V
Vsig(dif)(p-p)  
Lwh  
MR head input signal peak differential  
to peak voltage  
0.4  
1
mVpp  
nH  
Write Head inductance  
Write Head resistance  
Write head capacitance  
Reference resistor  
including lead  
including lead  
including lead  
Iref=Vref/Rext  
75  
Rwh  
Cwh  
Rext  
-
10  
Ohm  
pF  
-
TBD  
10  
9.9  
10.1  
k W  
1998 July 30  
32  
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Philips Semiconductors  
Objective Specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
Notes  
1. A supply by-pass capacitor from VCC to ground or a low pass filter may be used to optimize the PSRR.  
2. A supply by-pass capacitor from VEE to ground or a low pass filter may be used to optimize the PSRR  
14 ABSOLUTE MAXIMUM RATINGS  
SYMBOL  
VCC  
PARAMETER  
MIN.  
-0.5  
MAX.  
UNIT  
Positive supply voltage  
Negative supply voltage  
Digital input voltage  
6.0  
0.5  
V
V
V
V
VEE  
VIN  
Vn1  
-6.0  
-0.5  
-0.5  
VCC+0.3V  
5.5  
Voltage on all pins except VCC, read inputs RPx, RNx, write  
outputs WPx, WNx (x=0 to 11) and the ones mentionned in  
this table  
but not higher than  
VCC+0.5  
VCC  
V
V
Vn2  
Voltage on write driver outputs WPx, WNx  
VEE  
but not larger than  
VEE-0.5 VCC+0.5  
V
V
Vn3  
Tstg  
Tj  
Read inputs RPx, RNx  
IC Storage temperature range  
Junction temperature range  
-1  
1
-65  
150  
150  
°C  
°C  
1998 July 30  
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Objective specification, Revision 2.2  
Pre-Amplifier for Hard Disk Drive with  
MR-Read / Inductive Write Heads  
TDA5360  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Date of release: 09-98  
Document order number:  
9397 750 04468  
Philips  
Semiconductors  
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