TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD
cameras
Rev. 03 — 16 January 2001
Objective specification
1. Description
The TDA9964 is a 12-bit analog-to-digital interface for CCD cameras. The device
includes a correlated double sampling circuit, PGA, clamp loops and a low-power
12-bit ADC together with its reference voltage regulator.
The PGA gain and the ADC input clamp level are controlled via the serial interface.
An additional DAC is provided for additional system controls; its output voltage range
is 1.0 V p-p, which is available at pin OFDOUT.
2. Features
■ Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 12-bit
Analog-to-Digital Converter (ADC) and reference regulator included
■ Fully programmable via a 3-wire serial interface
■ Sampling frequency up to 30 MHz
■ PGA gain range of 24 dB (in steps of 0.1 dB)
■ Low power consumption of only 175 mW at 2.7 V
■ Power consumption in standby mode of 4.5 mW (typ.)
■ 3.0 V operation and 2.5 to 3.6 V operation for the digital outputs
■ All digital inputs accept 5 V signals
c
c
■ Active control pulses polarity selectable via serial interface
■ 8-bit DAC included for analog settings
■ TTL compatible inputs, CMOS compatible outputs.
3. Applications
■ Low-power, low-voltage CCD camera systems.
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BLK
CLK
OE
V
V
SHP
SHD
AGND1
2
AGND6 CLPOB CLPDM
CCA1
1
CCA4
41
45
46
40
44
48
43
47
39
22
21
DGND1
V
CCD1
CDS CLOCK GENERATOR
37
OGND2
38
36
35
34
33
32
31
30
29
28
V
CCO2
8
9
TDA9964
CPCDS1
CPCDS2
D11
D10
CLAMP
D9
D8
D7
D6
D5
D4
D3
D2
7
3
4
V
CCA2
AGND2
IN
PGA
CORRELATED
DOUBLE
SAMPLING
BLACK
LEVEL
SHIFT
DATA
FLIP-
FLOP
OUTPUT
BUFFER
SHIFT
BLANKING
12-bit ADC
CLAMP
27
26
25
D1
D0
V
14
5
ref
V
CCA3
8-BIT
REGISTER
7-BIT
24
23
REGISTER
OGND1
AGND3
OFD DAC
V
CCO1
11
OFDOUT
10
SERIAL
INTERFACE
8-BIT
REGISTER
REGULATOR
DCLPC
13
16
18
17
20
42
12
6
15
19
FCE515
OPGA
OPGAC
SCLK
VSYNC
TEST
SEN
SDATA
STDBY
AGND5
AGND4
Fig 1. Block diagram.
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
7. Pinning information
7.1 Pinning
V
D11
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
CCA1
AGND1
AGND2
IN
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AGND3
AGND4
TDA9964HL
V
CCA2
CPCDS1
CPCDS2
DCLPC 10
OFDOUT 11
12
TEST
FCE516
Fig 2. Pin configuration.
7.2 Pin description
Table 3: Pin description
Symbol
VCCA1
Pin
1
Description
analog supply voltage 1
analog ground 1
AGND1
AGND2
IN
2
3
analog ground 2
4
input signal from CCD
analog ground 3
AGND3
AGND4
VCCA2
5
6
analog ground 4
7
analog supply voltage 2
clamp storage capacitor pin 1
clamp storage capacitor pin 2
regulator decoupling pin
CPCDS1
CPCDS2
DCLPC
OFDOUT
TEST
8
9
10
11
12
13
14
analog output of the additional 8-bit control DAC
test mode input pin (should be connected to AGND5)
analog ground 5
AGND5
VCCA3
analog supply 3
9397 750 07918
© Philips Electronics N.V. 2001. All rights reserved.
Objective specification
Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
Table 3: Pin description…continued
Symbol
OPGA
OPGAC
SDATA
SCLK
SEN
VSYNC
VCCD1
DGND1
VCCO1
OGND1
D0
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
PGA output (test pin)
PGA complementary output (test pin)
serial data input for serial interface control
serial clock input for serial interface
strobe pin for serial interface
vertical sync pulse input
digital supply voltage 1
digital ground 1
output supply voltage 1
digital output ground 1
ADC digital output 0 (LSB)
ADC digital output 1
D1
D2
ADC digital output 2
D3
ADC digital output 3
D4
ADC digital output 4
D5
ADC digital output 5
D6
ADC digital output 6
D7
ADC digital output 7
D8
ADC digital output 8
D9
ADC digital output 9
D10
ADC digital output 10
ADC digital output 11 (MSB)
output digital ground 2
output supply voltage 2
D11
OGND2
VCCO2
OE
output enable control input (LOW: outputs active; HIGH:
outputs are high impedance)
AGND6
VCCA4
40
41
42
analog ground 6
analog supply voltage 4
STDBY
standby mode control input (LOW: TDA9964 active; HIGH:
TDA9964 standby)
BLK
43
44
45
46
47
48
blanking control input
CLPOB
SHP
clamp pulse input at optical black
preset sample-and-hold pulse input
data sample-and-hold pulse input
data clock input
SHD
CLK
CLPDM
clamp pulse input at dummy pixel
9397 750 07918
© Philips Electronics N.V. 2001. All rights reserved.
Objective specification
Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
8. Limiting values
Table 4: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCCA
Parameter
Conditions
Min
−0.3
−0.3
−0.3
Max
+7.0
+7.0
+7.0
Unit
V
[1]
[1]
[1]
analog supply voltage
digital supply voltage
digital outputs supply voltage
supply voltage difference:
between VCCA and VCCD
between VCCA and VCCO
between VCCD and VCCO
input voltage
VCCD
V
VCCO
V
∆VCC
−0.5
−0.5
−0.5
−0.3
−
+0.5
+1.2
+1.2
+7.0
±10
V
V
V
Vi
referenced to AGND
V
Io
data output current
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
−20
−
+150
+75
150
[1] The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage difference
∆VCC remains as indicated.
9. Thermal characteristics
Table 5: Thermal characteristics
Symbol
Parameter
Conditions
Value
Unit
Rth(j-a)
thermal resistance from junction to ambient in free air
76
K/W
10. Characteristics
Table 6: Characteristics
VCCA = VCCD = 3.0 V; VCCO = 2.7 V; fpix = 30 MHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Supplies
VCCA
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
digital supply voltage
digital outputs supply voltage
analog supply current
digital supply current
2.7
2.7
2.5
−
3.0
3.0
2.7
60
3
3.6
3.6
3.6
−
V
VCCD
V
VCCO
ICCA
V
all clamps active
mA
mA
mA
ICCD
−
−
ICCO
digital outputs supply current CL = 10 pF on all data
outputs; input ramp
−
1
−
response time is 800 µs
9397 750 07918
© Philips Electronics N.V. 2001. All rights reserved.
Objective specification
Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
Table 6: Characteristics…continued
VCCA = VCCD = 3.0 V; VCCO = 2.7 V; fpix = 30 MHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Digital inputs
Pins: SHP, SHD and CLK (referenced to DGND)
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
0.6
5.5
+3
−
V
2.2
−3
−
−
V
0 ≤ Vi ≤ 5.5 V
fCLK = 30 MHz
fCLK = 30 MHz
−
µA
kΩ
pF
Zi
input impedance
50
−
Ci
input capacitance
−
2
Pins: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC
VIL
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
0.6
5.5
+2
V
VIH
2.2
−2
V
Ii
0 ≤ Vi ≤ 5.5 V
µA
Clamps
Global characteristics of the clamp loops
tW(clamp)
clamp active pulse width in
number of pixels
PGA code = 255 for
maximum 4 LSB error
12
−
−
−
pixels
mS
Input clamp (driven by CLPDM)
gm(CDS)
CDS input clamp
transconductance
−
20
Correlated Double Sampling (CDS)
Vi(CDS)(p-p) maximum peak-to-peak CDS VCC = 2.85 V
650
800
500
−
−
−
−
−
−
mV
mV
mV
input amplitude (video signal)
VCC ≥ 3.0 V
Vreset(max)
maximum CDS input reset
pulse amplitude
Ii(IN)
input current into pin IN
input capacitance
at floating gate level
tbf
−
−
2
tbf
−
µA
pF
ns
Ci
tCDS(min)
CDS control pulses minimum Vi(CDS)(p-p) = 800 mV
8
−
−
active time
black to white transition in
Vi recovery
th(IN;SHP)
CDS input hold time (pin IN) see Figure 3 and 4
compared to control pulse
SHP
4
4
−
−
−
−
ns
ns
th(IN;SHD)
CDS input hold time (pin IN) see Figure 3 and 4
compared to control pulse
SHD
Amplifier
DRPGA
PGA dynamic range
PGA gain step
−
24
−
dB
dB
∆GPGA
0.08
0.10
0.12
Analog-to-Digital Converter (ADC)
DNL differential non linearity
Total chain characteristics (CDS + PGA + ADC)
fpix = 30 MHz; ramp input
−
±0.5
±0.9
LSB
MHz
fpix(max)
maximum pixel frequency
30
−
−
9397 750 07918
© Philips Electronics N.V. 2001. All rights reserved.
Objective specification
Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
Table 6: Characteristics…continued
VCCA = VCCD = 3.0 V; VCCO = 2.7 V; fpix = 30 MHz; Tamb = 25 °C; unless otherwise specified.
Symbol
fpix(min)
tCLKH
Parameter
Conditions
Min
tbf
Typ
−
Max
−
Unit
MHz
ns
minimum pixel frequency
CLK pulse width HIGH
CLK pulse width LOW
12
−
−
tCLKL
12
−
−
ns
td(SHD;CLK)
time delay between
SHD and CLK
10
−
−
ns
tsu(BLK;SHD)
Vi(IN)
set-up time of BLK compared see Figure 3 and 4
to SHD
5
−
−
ns
video input dynamic signal
for ADC full-scale output
PGA code = 00
PGA code = 255
800
50
−
−
−
−
mV
mV
Ntot(rms)
total noise from CDS input to see Figure 8
ADC output (RMS value)
PGA gain = 0 dB
−
1.5
2.2
70
−
LSB
LSB
µV
PGA gain = 9 dB
PGA gain = 24 dB
PGA gain = 9 dB
−
−
Ein(rms)
equivalent input noise
voltage (RMS value)
−
−
−
140
−
−
µV
OCCD(max)
maximum offset between
CCD floating level and CCD
dark pixel level
−100
+100
mV
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control DAC
(OFD) output voltage
Ri = 1 MΩ
−
1.0
−
V
(peak-to-peak value)
VOFDOUT(0)
DC output voltage for code 0
−
−
AGND
−
−
V
V
VOFDOUT(255) DC output voltage for
code 255
AGND + 1.0
TCDAC
DAC output range
−
250
−
ppm/°C
temperature coefficient
ZOFDOUT
IOFDOUT
DAC output impedance
OFD output current drive
−
−
2000
−
Ω
static
−
100
µA
Digital outputs (fpix = 30 MHz; CL = 10 pF); see Figure 3 and 4
VOH
VOL
IOZ
HIGH-level output voltage
LOW-level output voltage
IOH = −1 mA
VCCO − 0.5 −
VCCO
0.5
V
IOL = 1 mA
0
−
−
V
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
+20
µA
th(o)
td(o)
output hold time
output delay time
5
−
−
ns
ns
ns
pF
CL = 10 pF; VCCO = 3.0 V
CL = 10 pF; VCCO = 2.7 V
−
−
−
12
14
−
tbf
tbf
15
CL
output load capacitance
Serial interface
fSCLK(max)
maximum frequency of serial
interface
10
−
−
MHz
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Objective specification
Rev. 03 — 16 January 2001
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IN
N + 1
N + 2
N + 3
N + 4
N + 5
N
t
CDS(min)
2.2 V
SHP
SHD
0.6 V
t
h(IN;SHP)
t
CDS(min)
2.2 V
2.2 V
0.6 V
0.6 V
t
h(IN;SHD)
t
CLKH
2.2 V
0.6 V
2.2 V
CLK
0.6 V
t
d(SHD;CLK)
ADC CLAMP
CODE
50%
N
DATA
N − 4
N − 3
N − 2
N − 1
t
h(o)
t
d(o)
2.2 V
BLK
FCE517
t
su(BLK;SHD)
Fig 3. Pixel frequency timing diagram; all polarities active HIGH.
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IN
N + 1
N + 2
N + 3
N + 4
N + 5
N
2.2 V
SHP
SHD
0.6 V
t
CDS(min)
2.2 V
t
h(IN;SHP)
2.2 V
0.6 V
0.6 V
t
t
CDS(min)
h(IN;SHD)
2.2 V
2.2 V
0.6 V
CLK
DATA
BLK
0.6 V
CLKL
t
t
d(SHD;CLK)
ADC CLAMP
CODE
50%
N − 4
N − 3
N − 2
N − 1
N
t
h(o)
t
d(o)
0.6 V
FCE518
t
su(BLK;SHD)
Fig 4. Pixel frequency timing diagram; all polarities active LOW.
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
FCE519
1.0
OFDOUT
DAC voltage
output
(V)
0
255
0
OFDOUT control DAC input code
Fig 5. DAC voltage output as a function of DAC input code.
CLPOB
CLPDM
WINDOW
WINDOW
AGCOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
CLPDM
(active HIGH)
BLK
(active HIGH)
BLK window
FCE520
Fig 6. Line frequency timing diagram.
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© Philips Electronics N.V. 2001. All rights reserved.
Objective specification
Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
FCE521
30
24
TOTAL
gain
(dB)
25.9
18
12
6
1.9
0
0
64
128
192
255
PGA input code
Fig 7. Total gain from CDS input to ADC input as a function of PGA input code.
FCE522
6
handbook, halfpage
N
tot(rms)
(LSB)
5
4
3
2
1
0
0
64
128
192
255
PGA code
Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is
evaluated. Front-end works at 30 Mpixels with line of 1024 pixels of which the first 40 lines are used to run CLPOB and the
last 40 lines for CLPDM. Data at the ADC outputs is measured during the other pixels. As a result, the standard deviation of the
codes statistic is computed, resulting in the noise. No quantization noise is taken into account as there is no input.
Fig 8. Typical total noise performance as a function of PGA gain.
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Objective specification
Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
SDATA
SHIFT REGISTER
SD0 SD1 SD2
SD3
A0
SD6
SD4
12
SD9 SD10 SD11
MSB
A1
A2
A3
SD5
SD8
SD7
SCLK
SEN
LSB
LATCH
SELECTION
8
8
7
10
CONTROL PULSE
POLARITY
PGA GAIN
LATCHES
ADC CLAMP
LATCHES
OFDOUT DAC
LATCHES
SCLK
LATCHES
VSYNC
FLIP-FLOP
FLIP-FLOP
FLIP-FLOP
8-bit DAC
ADC clamp
control
control pulses
PGA control
FCE523
polarity settings
Fig 9. Serial interface block diagram.
t
su2
t
hd4
MSB
LSB
A3
SDATA
A2
A1
A0
SD10
SD11 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
SCLK
SEN
t
t
su1
su3
t
hd3
FCE524
tsu1 = tsu2 = tsu3 = 10 ns (min.); thd3 = thd4 = 10 ns (min.)
Fig 10. Loading sequence of control input data via the serial interface.
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Rev. 03 — 16 January 2001
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
Table 7: Serial interface programming
Address bits
A3 A2 A1 A0
Data bits D9 to D0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
PGA gain control (SD7 to SD0)
DAC OFDOUT output control (SD7 to SD0)
ADC clamp reference control (SD6 to SD0); from code 0 to 127
polarity settings; SD2, SD6, SD7 and SD9 should be set to logic 1;
for SD6 and SD7 see Table 9, 10, 11, and 12
0
1
1
1
0
1
0
1
SD7 = 0 by default; SD7 = 1 PGA gain up to 36 dB but noise and
clamp behaviour are not guaranteed
initialization (SD11 to SD0 = 0)
test modes
other addresses
Table 8: Polarity settings
Symbol
SHP and SHD
CLK
Pin
Serial control bit
Active edge or level
1 = HIGH; 0 = LOW
1 = rising; 0 = falling
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
0 = rising; 1 = falling
45 and 46 SD4
47
48
44
43
20
SD5
SD0
SD1
SD3
SD8
CLPDM
CLPOB
BLK
VSYNC
Table 9: Standby control using pin STDBY
Bit SD7 of
register 0011
STDBY
ADC digital outputs
D11 to D0
ICCA + ICCO + ICCD (typ.)
1
1
0
1
0
last logic state
active
1.5 mA
65 mA
65 mA
1.5 mA
0
active
test logic state
Table 10: Output enable selection using output enable pin (OE)
Bit SD6 of register 0011
OE
0
ADC digital outputs D11 to D0
1
active, binary
high impedance
high impedance
active binary
1
0
0
1
Table 11: Standby control by serial interface (register
address A3 = 0, A2 = 0, A1 = 1 and A0 = 1); pin STDBY connected to ground
SD7
0
ADC digital outputs D11 to D0 ICCA + ICCO + ICCD (typ.)
last logic state
active
1.5 mA
65 mA
1
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Objective specification
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TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Philips Semiconductors
Table 12: Output enable control by serial interface (register address A3 = 0, A2 = 0,
A1 = 1 and A0 = 1); output enable pin (OE) connected to ground
SD6
0
ADC digital outputs D11 to D0
high impedance
1
active binary
11. Application information
V
V
CCD
CCD
V
V
CCO
CCA
100 nF
100 nF
(2) (2)
(2)
CCD
1 µF
48 47 46 45 44 43 42 41 40 39 38 37
V
CCA1
D11
D10
D9
V
1
2
3
4
5
6
36
35
34
33
32
31
30
29
28
27
26
25
CCA
AGND1
AGND2
IN
D8
AGND3
AGND4
D7
D6
V
TDA9964
D5
CCA2
V
7
CCA
100
nF
CPCDS1
CPCDS2
D4
8
1
µF
D3
9
1
µF
D2
DCLPC
10
11
12
1
µF
OFDOUT
D1
D0
TEST
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
CCA
100 nF 100 nF
(1)
serial
interface
V
V
CCD
V
CCO
FCE525
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN;SHP) and th(IN;SHD) (see Section 10
“Characteristics”).
Fig 11. Application diagram.
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11.1 Power and grounding recommendations
When designing a printed-circuit board for applications such as PC cameras,
surveillance cameras, camcorders and digital still cameras, care should be taken to
minimize the noise.
For the front-end integrated circuit, the basic rules of printed-circuit board design and
implementation of analog components (such as classical operational amplifiers) must
be respected, particularly with respect to power and ground connections.
The following additional recommendation is given for the CDS input pin(s) which is
(are) internally connected to the programmable gain amplifier:
The connections between CCD interface and CDS input should be as short as
possible and a ground ring protection around these connections can be beneficial.
Separate analog and digital supplies provide the best solution. If it is not possible to
do this on the board, the analog supply pins must be decoupled effectively from the
digital supply pins. If the same power supply and ground are used for all the pins, the
decoupling capacitors must be placed as closely as possible to the IC package.
To minimize the noise caused by package and die parasitics in a two-ground system,
the following recommendation must be implemented:
All analog and digital supply pins must be decoupled to the analog ground plane.
Only the ground pin associated with the digital outputs must be connected to the
digital ground plane. All other ground pins should be connected to the analog ground
plane. The analog and digital ground planes must be connected together at one point
as closely as possible to the ground pin associated with the digital outputs.
The digital output pins and their associated lines should be shielded by the digital
ground plane, which can then be used as return path for digital signals.
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12. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT313-2
136E05
MS-026
Fig 12. SOT313-2.
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13. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe, it is desirable to take normal precautions appropriate
to handling integrated circuits.
14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 220 °C for thick/large
packages, and below 235 °C small/thin packages.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
•
•
For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
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The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
•
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
14.5 Package related soldering information
Table 13: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package
Soldering method
Wave
Reflow[1]
suitable
suitable
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
not suitable[2]
HBCC, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, SMS
PLCC[3], SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
suitable
not recommended[3] [4]
not recommended[5]
[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board
and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top
version).
[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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15. Revision history
Table 14: Revision history
Rev Date
CPCN
Description
03 20010116
02 20000801
01 20000502
-
-
-
Objective specification; third version
Objective specification; second version
Objective specification; initial version
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16. Data sheet status
[1]
Datasheet status
Product status Definition
Development
Objective specification
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
17. Definitions
18. Disclaimers
Short-form specification — The data in
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
a
short-form specification is
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
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Philips Semiconductors - a worldwide company
Argentina: see South America
Netherlands: Tel. +31 40 278 2785, Fax. +31 40 278 8399
Australia: Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
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For all other countries apply to: Philips Semiconductors,
Marketing Communications,
Internet: http://www.semiconductors.philips.com
Building BE, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 272 4825
(SCA71)
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17
18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
© Philips Electronics N.V. 2001.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 16 January 2001
Document order number: 9397 750 07918
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