Important Information
Warranty
The NI PCI-6110 and the NI PCI-6111 are warranted against defects in materials and workmanship for a period of one year from the date of
shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to
be defective during the warranty period. This warranty includes parts and labor.
The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects
in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National
Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives
notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be
uninterrupted or error free.
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before
any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are
covered by warranty.
National Instruments believes that the information in this document is accurate. The document has been carefully reviewed for technical
accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent
editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected.
In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.
EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF
NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER. NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR
DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY
THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action, whether in contract or tort, including
negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments
shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover
damages, defects, malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or
maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire,
flood, accident, actions of third parties, or other events outside reasonable control.
Copyright
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying,
recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National
Instruments Corporation.
Trademarks
CVI™, DAQ-STC™, IMAQ™, IVI™, LabVIEW™, Measurement Studio™, MITE™, National Instruments™, NI™, ni.com™, NI Develper Zone™
NI-DAQ™, and RTSI™ are trademarks of National Instruments Corporation.
,
Product and company names mentioned herein are trademarks or trade names of their respective companies.
Patents
For patents covering National Instruments products, refer to the appropriate location: Help»Patents in your software, the patents.txtfile
on your CD, or ni.com/patents.
WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
(1) NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF
RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN
ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT
INJURY TO A HUMAN.
(2) IN ANY APPLICATION, INCLUDING THE ABOVE, RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE
IMPAIRED BY ADVERSE FACTORS, INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY,
COMPUTER HARDWARE MALFUNCTIONS, COMPUTER OPERATING SYSTEM SOFTWARE FITNESS, FITNESS OF COMPILERS
AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION, INSTALLATION ERRORS, SOFTWARE AND
HARDWARE COMPATIBILITY PROBLEMS, MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL
DEVICES, TRANSIENT FAILURES OF ELECTRONIC SYSTEMS (HARDWARE AND/OR SOFTWARE), UNANTICIPATED USES OR
MISUSES, OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER (ADVERSE FACTORS SUCH AS THESE ARE
HEREAFTER COLLECTIVELY TERMED “SYSTEM FAILURES”). ANY APPLICATION WHERE A SYSTEM FAILURE WOULD
CREATE A RISK OF HARM TO PROPERTY OR PERSONS (INCLUDING THE RISK OF BODILY INJURY AND DEATH) SHOULD
NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE. TO AVOID
DAMAGE, INJURY, OR DEATH, THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO
PROTECT AGAINST SYSTEM FAILURES, INCLUDING BUT NOT LIMITED TO BACK-UP OR SHUT DOWN MECHANISMS.
BECAUSE EACH END-USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS' TESTING
PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN
COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL
INSTRUMENTS, THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING
THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE
INCORPORATED IN A SYSTEM OR APPLICATION, INCLUDING, WITHOUT LIMITATION, THE APPROPRIATE DESIGN,
PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION.
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Compliance
FCC/Canada Radio Frequency Interference Compliance
Determining FCC Class
The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC
places digital electronics into two classes. These classes are known as Class A (for use in industrial-commercial locations only)
or Class B (for use in residential or commercial locations). All National Instruments (NI) products are FCC Class A products.
Depending on where it is operated, this Class A product could be subject to restrictions in the FCC rules. (In Canada, the
Department of Communications (DOC), of Industry Canada, regulates wireless interference in much the same way.) Digital
electronics emit weak signals during normal operation that can affect radio, television, or other wireless products.
All Class A products display a simple warning statement of one paragraph in length regarding interference and undesired
operation. The FCC rules have restrictions regarding the locations where FCC Class A products can be operated.
Consult the FCC Web site at www.fcc.govfor more information.
FCC/DOC Warnings
This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions
in this manual and the CE marking Declaration of Conformity*, may cause interference to radio and television reception.
Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department of
Communications (DOC).
Changes or modifications not expressly approved by NI could void the user’s authority to operate the equipment under the FCC
Rules.
Class A
Federal Communications Commission
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC
Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated
in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and
used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this
equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference
at their own expense.
Canadian Department of Communications
This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations.
Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.
Compliance to EU Directives
Readers in the European Union (EU) must refer to the manufacturer’s Declaration of Conformity (DoC) for information*
pertaining to the CE marking compliance scheme. The manufacturer includes a DoC for most hardware products except for those
bought from OEMs. In addition, DoCs are usually not provided if compliance is not required, for example electrically benign
apparatus or cables.
To obtain the DoC for this product, click Declarations of Conformity Information at ni.com/hardref.nsf/. This Web site
lists the DoCs by product family. Select the appropriate product family, followed by your product, and a link to the DoC appears
in Adobe Acrobat format. Click the Acrobat icon to download or read the DoC.
*
The CE marking Declaration of Conformity contains important supplementary information and instructions for the user or
installer.
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About This Manual
Conventions ...................................................................................................................ix
Chapter 1
Introduction
NI-DAQ...........................................................................................................1-2
National Instruments ADE Software...............................................................1-3
Optional Equipment.......................................................................................................1-4
Custom Cabling .............................................................................................................1-4
Unpacking......................................................................................................................1-5
Chapter 2
Installing and Configuring the NI PCI-6110/6111
Installing the Software...................................................................................................2-1
Chapter 3
Hardware Overview
Analog Trigger...............................................................................................................3-4
Digital I/O......................................................................................................................3-8
Timing Signal Routing...................................................................................................3-8
Programmable Function Inputs .......................................................................3-10
Device and RTSI Clocks .................................................................................3-10
RTSI Triggers..................................................................................................3-11
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Contents
Chapter 4
Connecting Signals
I/O Connector................................................................................................................ 4-1
Connecting Analog Input Signals.................................................................................. 4-8
Types of Signal Sources ................................................................................................ 4-9
Floating Signal Sources .................................................................................. 4-9
Ground-Referenced Signal Sources................................................................ 4-9
Differential Measurements............................................................................................ 4-10
Working Voltage Range................................................................................................ 4-13
Analog Output Signal Connections............................................................................... 4-14
Power Connections........................................................................................................ 4-16
GPCTR0_SOURCE Signal .............................................................. 4-31
GPCTR0_GATE Signal ................................................................... 4-31
GPCTR0_OUT Signal...................................................................... 4-32
GPCTR0_UP_DOWN Signal........................................................... 4-33
GPCTR1_SOURCE Signal .............................................................. 4-33
GPCTR1_GATE Signal ................................................................... 4-34
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GPCTR1_UP_DOWN Signal...........................................................4-35
Field Wiring Considerations..........................................................................................4-37
Chapter 5
Calibration
Loading Calibration Constants ......................................................................................5-1
Self-Calibration..............................................................................................................5-2
External Calibration.......................................................................................................5-2
Appendix A
Specifications
Appendix B
Cable Connector Descriptions
Appendix C
Common Questions
Appendix D
Technical Support and Professional Services
Glossary
Index
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About This Manual
This manual describes the electrical and mechanical aspects of the National
Instruments PCI-6110/6111 data acquisition (DAQ) device and contains
information concerning its operation and programming.
The device is a high-performance multifunction analog, digital, and timing
I/O device for PCI bus computers. Supported functions include analog
input (AI), analog output (AO), digital I/O (DIO), and timing I/O (TIO).
Conventions
The following conventions appear in this manual:
<>
Angle brackets that contain numbers separated by an ellipsis represent a
range of values associated with a bit or signal name—for example,
DIO<3..0>.
»
The » symbol leads you through nested menu items and dialog box options
to a final action. The sequence File»Page Setup»Options directs you to
pull down the File menu, select the Page Setup item, and select Options
from the last dialog box.
This icon denotes a note, which alerts you to important information.
This icon denotes a caution, which advises you of precautions to take to
avoid injury, data loss, or a system crash. When this symbol is marked on
the product, refer to the Unpacking section of Chapter 1, Introduction, for
precautions to take.
bold
Bold text denotes items that you must select or click in the software, such
as menu items and dialog box options. Bold text also denotes parameter
names and hardware labels.
italic
Italic text denotes variables, emphasis, a cross reference, or an introduction
to a key concept. This font also denotes text that is a placeholder for a word
or value that you must supply.
monospace
Text in this font denotes text or characters that you should enter from the
keyboard, sections of code, programming examples, and syntax examples.
This font is also used for the proper names of disk drives, paths, directories,
programs, subprograms, subroutines, device names, functions, operations,
variables, filenames and extensions, and code excerpts.
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About This Manual
NI-DAQ
NI-DAQ refers to the NI-DAQ driver software for Macintosh or
PC compatible computers unless otherwise noted.
NI PCI-6110/6111
PCI
This phrase refers to either the NI PCI-6110 or NI PCI-6111 device.
PCI stands for Peripheral Component Interconnect. PCI is a
high-performance expansion bus architecture originally developed by Intel
to replace ISA and EISA.
Platform
Text in this font denotes a specific platform and indicates that the text
following it applies only to that platform.
National Instruments Documentation
The NI PCI-6110/6111 User Manual is one piece of the documentation set
for the DAQ system. You could have any of several types of documentation
depending on the hardware and software in the system. Refer to
ni.com/manualsto download the following documents:
•
•
Accessory installation guides or manuals—If you use accessory
products, read the terminal block and cable assembly installation
guides. They explain how to physically connect the relevant pieces
of the system. Consult these guides when you make the connections.
DAQ hardware documentation—This documentation has detailed
information about the DAQ hardware that plugs into or is connected to
the computer. Use this documentation for hardware installation and
configuration instructions, specification information about the DAQ
hardware, and application hints.
•
Software documentation—You may have both application software
and NI-DAQ documentation. NI application software includes
LabVIEW, Measurement Studio, and others. After you set up the
hardware system, use either the application software documentation or
the NI-DAQ documentation to help you write your application. If you
have a large, complicated system, it is worthwhile to look through the
software documentation before you configure the hardware.
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Related Documentation
The following documents contain information that you might find helpful:
•
The NI Developer Zone tutorial, Field Wiring and Noise
Considerations for Analog Signals, located at ni.com/zone
•
•
•
•
PCI Local Bus Specification Revision 2.2
DAQ Quick Start Guide, located at ni.com/manuals
DAQ-STC Technical Reference Manual, located at ni.com/manuals
NI-DAQ User Manual for PC Compatibles, located at
ni.com/manuals
•
•
NI-DAQ Function Reference Manual (for NI-DAQ versions 6.6 or
earlier), located at ni.com/manuals
NI-DAQ Function Reference Help (for NI-DAQ versions 6.7 or later),
which is accessible from Start»Programs»National Instruments»
NI-DAQ»NI-DAQ Help
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1
Introduction
This chapter describes the NI PCI-6110/6111, lists what you need to get
started, describes the optional software and optional equipment, and
explains how to unpack the device.
About the NI PCI-6110/6111
Thank you for buying an NI PCI-6110/6111. The NI PCI-6110/6111 is a
Plug and Play, multifunction analog, digital, and timing I/O device for PCI
bus computers. The NI PCI-6110/6111 features a 12-bit A/D converter
(ADC) per channel with four or two simultaneously sampling analog
inputs, 16-bit D/A converters (DACs) with voltage outputs, eight lines of
TTL-compatible DIO, and two 24-bit counter/timers for TIO. Because the
NI PCI-6110/6111 has no DIP switches, jumpers, or potentiometers, it is
easily software-configured and calibrated.
The NI PCI-6110/6111 is a completely switchless and jumperless DAQ
device for the PCI bus. This feature is made possible by the NI MITE bus
interface chip that connects the device to the PCI I/O bus. The MITE
implements the PCI Local Bus Specification so that the interrupts and base
memory addresses are all software configured.
The NI PCI-6110/6111 uses the National Instruments DAQ-STC system
timing controller for time-related functions. The DAQ-STC consists
of three timing groups that control AI, AO, and general-purpose
counter/timer functions. These groups include a total of seven 24-bit and
three 16-bit counters and a maximum timing resolution of 50 ns. The
DAQ-STC makes possible such applications as buffered pulse generation,
equivalent time sampling, and seamless changes to the sampling rate.
The NI PCI-6110/6111 uses the Real-Time System Integration (RTSI) bus
to easily synchronize several measurement functions to a common trigger
or timing event. The RTSI bus consists of the RTSI bus interface and a
ribbon cable to route timing and trigger signals between several functions
on as many as five DAQ devices in the computer.
Detailed specifications of the NI PCI-6110/6111 are in Appendix A,
Specifications.
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Chapter 1
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What You Need to Get Started
To set up and use the NI PCI-6110/6111, you will need the following items:
❑ NI PCI-6110/6111
❑ NI PCI-6110/6111 User Manual
❑ NI-DAQ
❑ The computer
❑ (Optional) One of the following software packages and
documentation:
–
–
–
LabVIEW (Windows or Mac OS)
Measurement Studio (Windows)
VI Logger (Windows)
Software Programming Choices
When programming the National Instruments DAQ hardware, you can use
NI application development environment (ADE) software or other ADEs.
In either case, you use NI-DAQ.
NI-DAQ
NI-DAQ, which ships with the NI PCI-6110/6111, has an extensive library
of functions that you can call from the ADE. These functions allow you to
use all the features of the NI PCI-6110/6111.
NI-DAQ carries out many of the complex interactions, such as
programming interrupts, between the computer and the DAQ hardware.
NI-DAQ maintains a consistent software interface among its different
versions so that you can change platforms with minimal modifications to
the code. Whether you use LabVIEW, Measurement Studio, or other
ADEs, your application uses NI-DAQ, as illustrated in Figure 1-1.
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LabVIEW,
Measurement Studio,
or VI Logger
Conventional
Programming
Environment
NI-DAQ
Personal
Computer or
Workstation
DAQ Hardware
Figure 1-1. The Relationship Between the Programming Environment,
NI-DAQ, and the Hardware
To download a free copy of the most recent version of NI-DAQ, click
Download Software at ni.com.
National Instruments ADE Software
LabVIEW features interactive graphics, a state-of-the-art interface, and
a powerful graphical programming language. The LabVIEW Data
Acquisition VI Library, a series of virtual instruments for using LabVIEW
with National Instruments DAQ hardware, is included with LabVIEW.
Measurement Studio, which includes LabWindows™/CVI™, tools for
Visual C++, and tools for Visual Basic, is a development suite that allows
you to use ANSI C, Visual C++, and Visual Basic to design test and
measurement software. For C developers, Measurement Studio includes
LabWindows/CVI, a fully integrated ANSI C application development
environment that features interactive graphics and the LabWindows/CVI
Data Acquisition and Easy I/O libraries. For Visual Basic developers,
Measurement Studio features a set of ActiveX controls for using National
Instruments DAQ hardware. These ActiveX controls provide a high-level
programming interface for building virtual instruments. For Visual C++
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Chapter 1
Introduction
developers, Measurement Studio offers a set of Visual C++ classes and
tools to integrate those classes into Visual C++ applications. The libraries,
ActiveX controls, and classes are available with Measurement Studio and
NI-DAQ.
VI Logger is an easy-to-use yet flexible tool specifically designed for data
logging applications. Using dialog windows, you can configure data
logging tasks to easily acquire, log, view, and share your data. VI Logger
does not require any programming; it is a stand-alone, configuration-based
software.
Using LabVIEW, Measurement Studio, or VI Logger greatly reduces the
development time for your data acquisition and control application.
Optional Equipment
NI offers a variety of products to use with the NI PCI-6110/6111, including
the following cables, connector blocks, and other accessories:
•
•
•
Shielded cables and cable assemblies
Connector blocks, shielded 50- and 68-pin screw terminals
RTSI bus cables
For more specific information about these products, refer to the NI catalog
at ni.com/catalog.
Custom Cabling
NI offers cables and accessories for you to prototype your application or to
use if you frequently change device interconnections.
When developing custom cabling, refer to the following guidelines:
•
For the AI signals, shielded twisted-pair wires for each AI pair yield
the best results, assuming that you use differential inputs. Tie the shield
for each signal pair to the ground reference at the source.
•
•
Route the analog lines separately from the digital lines.
When using a cable shield, use separate shields for the analog and
digital halves of the cable. Failure to do so results in noise coupling
into the analog signals from transient digital signals.
Mating connectors and a backshell kit for making custom 68-pin cables are
available from NI.
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The following list gives recommended part numbers for connectors that
mate to the I/O connector on the NI PCI-6110/6111:
•
•
Honda 68-position, solder cup, female connector
Honda backshell
Unpacking
The NI PCI-6110/6111 is shipped in an antistatic package to prevent
electrostatic damage to the device. Electrostatic discharge (ESD) can
damage several components on the device.
Caution Never touch the exposed pins of connectors.
To avoid such damage in handling the device, take the following
precautions:
•
Ground yourself using a grounding strap or by holding a grounded
object.
•
Touch the antistatic package to a metal part of the computer chassis
before removing the device from the package.
Remove the device from the package and inspect the device for loose
components or any sign of damage. Notify NI if the device appears
damaged in any way. Do not install a damaged device into the computer.
Store the NI PCI-6110/6111 in the antistatic envelope when not in use.
Safety Information
This section contains important safety information that you must follow
when installing and using the product.
Do not operate the product in a manner not specified in this document.
Misuse of the product can result in a hazard. You can compromise the
safety protection built into the product if the product is damaged in any
way. If the product is damaged, return it to NI for repair.
Do not substitute parts or modify the product except as described in this
document. Use the product only with the chassis, modules, accessories, and
and filler panels installed during operation of the product.
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Do not operate the product in an explosive atmosphere or where there may
be flammable gases or fumes. Operate the product only at or below the
pollution degree stated in the Appendix A, Specifications. Pollution is
foreign matter in a solid, liquid, or gaseous state that can reduce dielectric
strength or surface resistivity. The following is a description of pollution
degrees:
•
Pollution Degree 1 means no pollution or only dry, nonconductive
pollution occurs. The pollution has no influence.
•
Pollution Degree 2 means that only nonconductive pollution occurs in
most cases. Occasionally, however, a temporary conductivity caused
by condensation must be expected.
•
Pollution Degree 3 means that conductive pollution occurs, or dry,
nonconductive pollution occurs that becomes conductive due to
condensation.
Clean the product with a soft nonmetallic brush. Make sure that the product
is completely dry and free from contaminants before returning it to service.
the product is rated. Do not exceed the maximum ratings for the product.
Remove power from signal lines before connecting them to or
disconnecting them from the product.
Operate this product only at or below the installation category stated in
Appendix A, Specifications.
The following is a description of installation categories:
•
Installation Category I is for measurements performed on circuits not
directly connected to MAINS1. This category is a signal level such as
voltages on a printed wire board (PWB) on the secondary of an
isolation transformer.
Examples of Installation Category I are measurements on circuits not
derived from MAINS and specially protected (internal)
MAINS-derived circuits.
•
Installation Category II is for measurements performed on circuits
directly connected to the low-voltage installation. This category refers
to local-level distribution such as that provided by a standard wall
outlet.
1
MAINS is defined as the electricity supply system to which the equipment concerned is designed to be connected either for
powering the equipment or for measurement purposes.
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Examples of Installation Category II are measurements on household
appliances, portable tools, and similar equipment.
•
Installation Category III is for measurements performed in the building
installation. This category is a distribution level referring to hardwired
equipment that does not rely on standard building insulation.
Examples of Installation Category III include measurements on
distribution circuits and circuit breakers. Other examples of
Installation Category III are wiring including cables, bus-bars, junction
boxes, switches, socket outlets in the building/fixed installation, and
equipment for industrial use, such as stationary motors with a
permanent connection to the building/fixed installation.
•
Installation Category IV is for measurements performed at the source
of the low-voltage (<1,000 V) installation.
Examples of Installation Category IV are electric meters, and
measurements on primary overcurrent protection devices and
ripple-control units.
Below is a diagram of a sample installation.
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2
Installing and Configuring the
NI PCI-6110/6111
This chapter explains how to install and configure the NI PCI-6110/6111.
Installing the Software
Note It is important to install the software before installing the NI PCI-6110/6111 to
ensure that the device is properly detected.
1. Install the ADE, such as LabVIEW or Measurement Studio, according
to the instructions on the CD and the release notes.
2. Install NI-DAQ according to the instructions on the CD and in the
DAQ Quick Start Guide included with the device.
Installing the Hardware
The following are general installation instructions. Consult the computer or
chassis user manual or technical reference manual for specific instructions
and warnings about installing new devices.
You can install the NI PCI-6110/6111 in any available expansion slot in the
computer. However, to achieve best noise performance, leave as much room
as possible between the NI PCI-6110/6111 and other devices and hardware.
2. Remove the top cover or access port to the I/O channel.
3. Remove the expansion slot cover on the back panel of the computer.
4. Ground yourself using a grounding strap or by holding a grounded
object. Follow the ESD protection precautions described in the
Unpacking section of Chapter 1, Introduction.
5. Insert the NI PCI-6110/6111 into a PCI system slot. Gently rock the
device to ease it into place. It may be a tight fit, but do not force the
device into place.
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Chapter 2
Installing and Configuring the NI PCI-6110/6111
6. If required, screw the mounting bracket of the NI PCI-6110/6111 to the
back panel rail of the computer.
7. Visually verify the installation by making sure the device is not
touching other devices or components and is fully inserted into the slot.
8. Replace the cover.
9. Plug in and power on the computer.
The NI PCI-6110/6111 is now installed. You are now ready to configure the
device. Refer to the software documentation for configuration instructions.
Configuring the Device
The NI standard architecture for data acquisition and the PCI bus
specification make the NI PCI-6110/6111 completely software
configurable. You must perform two types of configuration on the
NI PCI-6110/6111—bus-related and data acquisition-related
configuration.
The NI PCI-6110/6111 is fully compatible with the industry standard
PCI Local Bus Specification Revision 2.2. This allows the PCI system
to automatically perform all bus-related configurations. Bus-related
configuration includes setting the device base memory address and
interrupt channel.
Data acquisition-related configuration, which you must perform, includes
such settings as AI coupling and range, and others. You can modify these
settings using NI-DAQ or application level software, such as LabVIEW,
Measurement Studio, and VI Logger.
To configure the device using Measurement & Automation Explorer
(MAX), refer to either the DAQ Quick Start Guide or to the NI-DAQ User
Manual for PC Compatibles. For operating system-specific installation and
troubleshooting instructions, refer to ni.com/support/daq.
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This chapter presents an overview of the hardware functions on the
NI PCI-6110/6111. Figures 3-1 and 3-2 show block diagrams for the
NI PCI-6110 and the NI PCI-6111, respectively.
CH0+
+
AI CH0
Mux
12
12
12
12
CH0
Latch
CH0
Amplifier
–
CH0
12-Bit ADC
Data (16)
Data (16)
Data (16)
CH0–
CH1+
+
AI CH1
Mux
CH1
Latch
CH1
Amplifier
–
CH1
12-Bit ADC
CH1–
CH2+
+
AI CH2
Mux
CH2
Latch
CH2
Amplifier
–
CH2
12-Bit ADC
Control
CH2–
CH3+
Generic
Bus
Interface
PCI
Bus
Interface
Mini
MITE
ADC
FIFO
Data (32)
+
Address/Data
AI CH3
Mux
CH3
Latch
CH3
Amplifier
–
CH3
12-Bit ADC
Data (16)
AI Control
CH3–
Calibration
Mux
EEPROM
IRQ
DMA
Analog
Trigger
Circuitry
2
Trigger
Trigger Level
DACs
Analog Input
Timing/Control
DMA/IRQ
Trigger
PFI / Trigger
Analog
EEPROM
DMA
Input
Control Interface
Control
Bus
Interface
Counter/
Timing I/O
DAQ-STC
Bus
Interface
DAQ - STC
Timing
FPGA
I/O
Bus
Interface
Analog
Output
Control
Analog Output
Timing/Control
RTSI Bus
Interface
Digital I/O
Digital I/O (8)
AO Control
Data (32)
DAC
FIFO
DAC0
Data (16)
DAC1
RTSI Bus
Calibration
DACs
4
Figure 3-1. NI PCI-6110 Block Diagram
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CH0+
+
AI CH0
Mux
12
12
CH0
Latch
CH0
Amplifier
–
CH0
12-Bit ADC
Data (16)
Control
CH0-
Generic
Bus
Interface
PCI
Bus
Interface
Mini
MITE
ADC
FIFO
Data (32)
CH1+
+
Address/Data
AI CH1
Mux
CH1
Latch
CH1
Amplifier
–
CH1
12-Bit ADC
Data (16)
AI Control
CH1-
Calibration
Mux
EEPROM
IRQ
DMA
Analog
Trigger
Circuitry
2
Trigger
Trigger Level
DACs
Analog Input
Timing/Control
DMA/IRQ
Trigger
PFI / Trigger
Analog
EEPROM
DMA
Input
Control Interface
Control
Bus
Interface
Counter/
Timing I/O
DAQ-STC
Bus
Interface
DAQ - STC
Timing
FPGA
I/O
Bus
Interface
Analog
Output
Control
Analog Output
Timing/Control
RTSI Bus
Interface
Digital I/O
Digital I/O (8)
AO Control
Data (32)
DAC
FIFO
DAC0
DAC1
RTSI Bus
Calibration
DACs
4
Figure 3-2. NI PCI-6111 Block Diagram
Analog Input
The AI section for the NI PCI-6110/6111 is software configurable. You can
select different AI configurations through application software. The
following sections describe in detail each AI setting.
Input Mode
The NI PCI-6110/6111 supports only differential (DIFF) inputs. DIFF
input mode provides up to four channels on the NI PCI-6110 and up to
two channels on the NI PCI-6111.
Note The inputs are differential only in the sense that the ground loops are broken. The
negative input is not intended to carry signals of interest, rather it provides a DC reference
point for the positive input, which may be different than ground.
A channel configured in DIFF input mode uses two AI channel lines.
One line connects to the positive input of the device programmable gain
instrumentation amplifier (PGIA), and the other connects to the negative
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input of the PGIA. For more information about DIFF input mode, refer to
the Connecting Analog Input Signals section of Chapter 4, Connecting
Signals, which contains diagrams showing the signal paths for DIFF input
mode.
Input Polarity and Input Range
The NI PCI-6110/6111 has bipolar inputs only. Bipolar input means that
the input voltage range is between –Vref /2 and +Vref /2. These devices
have a bipolar input range of 20 V ( 10 V).
You can program range settings on a per channel basis so that you can
uniquely configure each AI channel.
The software-programmable gain on these devices increases flexibility by
matching the input signal ranges to those that the ADC can accommodate.
The NI PCI-6110/6111 has gains of 0.2, 0.5, 1, 2, 5, 10, 20, and 50, and it
is suited for a wide variety of signal levels. With the proper gain setting,
you can use the full resolution of the ADC to measure the input signal.
Table 3-1 shows the overall input range and precision according to the
chosen gain.
Table 3-1. Actual Range and Measurement Precision
Range
Configuration
Gain
Actual Input Range1
Precision2
–10 to +10 V
0.2
0.5
1.0
–50 to +50 V
–20 to +20 V
–10 to +10 V
–5 to +5 V
24.41 mV
9.77 mV
4.88 mV
2.0
2.44 mV
5.0
–2 to +2 V
–1 to +1 V
–500 to +500 mV
–200 to +200 mV
976.56 µV
488.28 µV
244.14 µV
97.66 µV
10.0
20.0
50.0
1 Caution: The NI PCI-6110/6111 is not designed for input voltages greater than 42 V,
device. Input voltages greater than 42 V can damage the NI PCI-6110/6111, any device
connected to it, and the host computer. Overvoltage can also cause an electric shock hazard
for the operator. NI is not liable for damage or injury resulting from such misuse.
2 The value of 1 least significant bit (LSB) of the 12-bit ADC; that is, the voltage increment
corresponding to a change of one count in the ADC 12-bit count.
Note: Refer to Appendix A, Specifications, for absolute maximum ratings.
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Considerations for Selecting Input Ranges
The range you select depends on the expected range of the incoming signal.
A large input range can accommodate a large signal variation but reduces
the voltage resolution. Choosing a smaller input range improves the voltage
resolution but may result in the input signal going out of range. For best
results, match the input range as closely as possible to the expected range
of the input signal.
Input Coupling
You can configure the NI PCI-6110/6111 for either AC or DC input
coupling on a per channel basis. Use AC coupling when the AC signal
contains a large DC component. If you enable AC coupling, you remove
the large DC offset for the input amplifier and amplify only the AC
component. This configuration makes effective use of the ADC dynamic
range.
Analog Output
Analog Trigger
The NI PCI-6110/6111 supplies two channels of AO voltage at the
I/O connector. The range is fixed at bipolar 10 V.
In addition to supporting internal software triggering and external digital
triggering to initiate a DAQ sequence, these devices also support analog
triggering. You can configure the analog trigger circuitry to accept either
a direct analog input from the PFI0/TRIG1 pin on the I/O connector or a
postgain signal from the output of the PGIA on any of the channels, as
shown in Figures 3-3 and 3-4. The trigger-level range for the direct analog
channel is 10 V in 78 mV steps for the NI PCI-6110/6111. The range for
the post-PGIA trigger selection is simply the full-scale range of the selected
channel, and the resolution is that range divided by 256.
Note PFI0/TRIG1 pin is an analog input when configured as an analog trigger. Therefore,
it is susceptible to crosstalk from adjacent pins, which can result in false triggering when
the pin is unconnected. To avoid false triggering, make sure this pin is connected to a
low-impedance signal source (less than 1 kΩ source impedance) if you plan to enable this
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ADC
+
–
+
–
+
–
+
–
Analog
Input
CH0
PGIA
PGIA
PGIA
PGIA
ADC
ADC
Analog
Input
CH1
Analog
Trigger
Circuit
Mux
DAQ-STC
Analog
Input
CH2
ADC
Analog
Input
CH3
PFI0/TRIG1
Figure 3-3. Analog Trigger Block Diagram for the NI PCI-6110
ADC
+
Analog
Input
CH0
PGIA
–
Analog
Mux
Trigger
Circuit
DAQ-STC
ADC
+
Analog
Input
CH1
PGIA
–
PFI0/TRIG1
Figure 3-4. Analog Trigger Block Diagram for the NI PCI-6111
Five analog triggering modes are available, as shown in Figures 3-5
software.
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In below-low-level analog triggering mode, the trigger is generated when
the signal value is less than lowValue, as shown in Figure 3-5. HighValue
is unused.
lowValue
Trigger
Figure 3-5. Below-Low-Level Analog Triggering Mode
In above-high-level analog triggering mode, the trigger is generated when
the signal value is greater than highValue, as shown in Figure 3-6.
LowValue is unused.
highValue
Trigger
Figure 3-6. Above-High-Level Analog Triggering Mode
In inside-region analog triggering mode, the trigger is generated when the
signal value is between the lowValue and the highValue, as shown in
Figure 3-7.
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highValue
lowValue
Trigger
Figure 3-7. Inside-Region Analog Triggering Mode
In high-hysteresis analog triggering mode, the trigger is generated when the
signal value is greater than highValue, with the hysteresis specified by
lowValue, as shown in Figure 3-8.
highValue
lowValue
Trigger
Figure 3-8. High-Hysteresis Analog Triggering Mode
In low-hysteresis analog triggering mode, the trigger is generated when the
signal value is less than lowValue, with the hysteresis specified by
highValue, as shown in Figure 3-9.
highValue
lowValue
Trigger
Figure 3-9. Low-Hysteresis Analog Triggering Mode
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The analog trigger circuit generates an internal digital trigger based on the
AI signal and user-defined trigger levels. This digital trigger can be used by
any DAQ-STC timing section, including the AI, AO, and general-purpose
counter/timer sections. For example, the AI section can be configured to
acquire n scans after the AI signal crosses a specific threshold. As another
example, the AO section can be configured to update its outputs whenever
the AI signal crosses a specific threshold.
Digital I/O
The NI PCI-6110/6111 contains eight lines of DIO for general-purpose use.
You can individually software-configure each line for either input or
output. At system startup and reset, the DIO ports are all high-impedance.
The hardware up/down control for general-purpose counters 0 and 1 are
connected onboard to DIO6 and DIO7, respectively. Thus, you can use
DIO6 and DIO7 to control those counters. The up/down control signals,
GPCTR0_UP_DOWN and GPCTR1_UP_DOWN, are input only and do
not affect the operation of the DIO lines.
Timing Signal Routing
The DAQ-STC provides a flexible interface for connecting timing signals
to other devices or external circuitry. The NI PCI-6110/6111 uses the
RTSI bus to connect timing signals between devices and the Programmable
Function Input (PFI) pins on the I/O connector to external circuitry. These
connections enable the NI PCI-6110/6111 to both control and be controlled
by other devices and circuits.
You can control 13 timing signals internal to the DAQ-STC with an external
source. These timing signals can also be controlled by signals generated
internally to the DAQ-STC, and these selections are fully software
configurable. For example, the signal routing multiplexer for controlling
the STARTSCAN signal is shown in Figure 3-10.
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RTSI Trigger <0..6>
STARTSCAN
PFI<0..9>
Scan Interval Counter TC
GPCTR0_OUT
Figure 3-10. STARTSCAN Signal Routing
sources, including the external signals RTSI<0..6> and PFI<0..9> and the
internal signals Sample Interval Counter TC and GPCTR0_OUT.
Many of these timing signals are also available as outputs on the RTSI pins,
as indicated in the RTSI Triggers section, and on the PFI pins, as indicated
in Chapter 4, Connecting Signals.
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Programmable Function Inputs
The 10 PFIs are connected to the signal routing multiplexer for each timing
signal, and software can select a PFI as the external source for a given
timing signal. Any PFI can be used as an input by any timing signal, and
multiple timing signals can simultaneously use the same PFI. This flexible
routing scheme reduces the need to change physical connections to the
I/O connector for different applications. You can also individually enable
each PFI pin to output a specific internal timing signal. For example, if you
need the UPDATE* signal as an output on the I/O connector, software can
turn on the output driver for the PFI5/UPDATE* pin.
Device and RTSI Clocks
Many functions performed by the NI PCI-6110/6111 require a frequency
timebase to generate the necessary timing signals for controlling A/D
conversions, DAC updates, or general-purpose signals at the I/O connector.
The NI PCI-6110/6111 can use either its internal 20 MHz timebase or a
timebase received over the RTSI bus. In addition, if you configure the
device to use the internal timebase, you can program the device to drive its
internal timebase over the RTSI bus to another device that is programmed
to receive this timebase signal. This clock source, whether local or from the
RTSI bus, is used directly by the device as the primary frequency source.
The default configuration at startup is to use the internal timebase without
driving the RTSI bus timebase signal. This timebase is software-selectable.
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RTSI Triggers
The seven RTSI trigger lines on the RTSI bus provide a flexible
interconnection scheme for the device sharing the RTSI bus. These
bidirectional lines can drive any of eight timing signals onto the RTSI bus
and can receive any of these timing signals. This signal connection scheme
is shown in Figure 3-11.
DAQ-STC
TRIG1
TRIG2
CONVERT*
UPDATE*
WFTRIG
GPCTR0_SOURCE
GPCTR0_GATE
GPCTR0_OUT
STARTSCAN
AIGATE
Trigger
7
SISOURCE
UISOURCE
GPCTR1_SOURCE
GPCTR1_GATE
RTSI_OSC (20 MHz)
Clock
switch
Figure 3-11. RTSI Bus Signal Connection
Refer to the Timing Connections section of Chapter 4, Connecting Signals,
for a description of the signals shown in Figure 3-11.
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4
Connecting Signals
This chapter describes how to make input and output signal connections to
the NI PCI-6110/6111 through the device I/O connector. Table 4-1 shows
the cables that can be used with the I/O connectors to connect to different
accessories.
Table 4-1. I/O Connector Details
Cable for
Connecting
to 100-Pin
Accessories
Cable for
Connecting
to 68-Pin
Cable for
Connecting
to 50-Pin
Device with
I/O Connector
Number
of Pins
Accessories
Accessories
NI PCI-6110,
NI PCI-6111
68
SH68-68EP,
SH68-68R1-EP
SH6850
I/O Connector
Figure 4-1 shows the pin assignments for the 68-pin I/O connector on the
Figure 4-2 shows the pin assignments for the NI PCI-6110/6111 when used
with a 50-pin accessory.
Caution Connections that exceed any of the maximum ratings of input or output signals
on the NI PCI-6110/6111 can damage the device and the computer. Maximum input ratings
for each signal are given in the Protection column of Table 4-3. NI is not liable for
any damage resulting from such signal connections.
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34 68
ACH1+ 33 67
ACH0–
ACH0+
ACH0GND
ACH1–
ACH2+1
ACH2GND1
ACH3–1
NC
32 66
31 65
30 64
29 63
28 62
ACH1GND
ACH2–1
ACH3+1
ACH3GND1
NC
NC 27 61
NC 26 60
NC
NC
NC
NC 24 58
25 59
NC
NC
NC
23 57
22 56
21 55
NC
NC
DAC0OUT
DAC1OUT
AOGND
AOGND
DGND
DIO0
NC 20 54
19 53
18 52
17 51
16 50
15 49
DIO4
DGND
DIO1
DIO5
DIO6
DGND
DIO2
DGND
+5 V 14 48
DGND 13 47
DGND 12 46
DIO7
DIO3
SCANCLK
PFI0/TRIG1
11 45
10 44
EXTSTROBE*
DGND
PFI1/TRIG2
DGND
9
8
7
6
5
4
3
2
1
43
42
41
40
39
38
37
36
35
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
DGND
+5 V
DGND
PFI5/UPDATE*
PFI6/WFTRIG
DGND
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
DGND
PFI9/GPCTR0_GATE
GPCTR0_OUT
FREQ_OUT
DGND
1 NC on NI PCI-6111
NC = No Connect
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DIO0
DGND 24
50
25
FREQ_OUT
GPCTR0_OUT
49
AOGND
23 48
PFI9/GPCTR0_GATE
22
21
47
46
45
PFI8/GPCTR0_SOURCE
PFI7/STARTSCAN
PFI6/WFTRIG
NC
DAC1OUT
DAC0OUT 20
19 44
18 43
17 42
16 41
15 40
NC
NC
NC
NC
NC
PFI5/UPDATE*
GPCTR1_OUT
PFI4/GPCTR1_GATE
PFI3/GPCTR1_SOURCE
PFI2/CONVERT*
NC 14 39
NC 13 38
NC 12 37
PFI1/TRIG2
PFI0/TRIG1
EXTSTROBE*
SCANCLK
+5 V
PFI0/TRIG1
11 36
10 35
ACH3–1
ACH3+1
ACH2–1
9
8
7
6
5
4
3
2
1
34
33
32
31
30
29
28
27
26
+5 V
DGND
DIO7
ACH2+1
ACH1–
DIO6
ACH1+
DIO5
ACH0–
DIO4
ACH0+
DIO3
ACH<0..3>GND
ACH<0..3>GND
DIO2
DIO1
1 NC on NI PCI-6111
Figure 4-2. 50-Pin Connector Pin Assignments for the NI PCI-6110/6111
I/O Connector Signal Descriptions
Table 4-2. Signal Descriptions for I/O Connector Pins
Signal Name
Reference
Direction
Description
ACH<0..3>GND
—
—
Analog Input Channels 0 through 3 ground—These pins
are the bias current return point for differential
measurements. ACH<2..3>GND signals are no connects
on the NI PCI-6111.
ACH<0..3>+
ACH<0..3>GND Input
Analog Input Channels 0 through 3 (+)—These pins are
routed to the (+) terminal of the respective channel
amplifier. ACH<2..3>+ signals are no connects on the
NI PCI-6111.
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Table 4-2. Signal Descriptions for I/O Connector Pins (Continued)
Signal Name
ACH<0..3>–
Reference
Direction
Description
ACH<0..3>GND Input
Analog Input Channels 0 through 3 (–)—These pins are
routed to the (–) terminal of the respective channel
amplifier. ACH<2..3>– signals are no connects on the
NI PCI-6111.
DAC0OUT
DAC1OUT
AOGND
DGND
AOGND
AOGND
—
Output
Output
—
Analog Channel 0 Output—This pin supplies the voltage
output of AO channel 0.
Analog Channel 1 Output—This pin supplies the voltage
output of AO channel 1.
Analog Output Ground—The AO voltages are referenced
to this node.
—
—
Digital Ground—This pin supplies the reference for the
digital signals at the I/O connector as well as the +5 VDC
supply.
DIO<0..7>
+5 V
DGND
DGND
DGND
Input or
Output
Digital I/O signals—DIO6 and 7 can control the up/down
signal of general-purpose counters 0 and 1, respectively.
Output
+5 VDC Source—These pins are fused for up to 1 A of
+5 V supply. The fuse is self-resetting.
SCANCLK
Output
Scan Clock—This pin pulses once for each A/D
conversion when enabled. The low-to-high edge indicates
when the input signal can be removed from the input or
switched to another signal.
EXTSTROBE*
PFI0/TRIG1
DGND
DGND
Output
Input
External Strobe—This output can be toggled under
software control to latch signals or trigger events on
external devices.
PFI0/Trigger 1—As an input, this is either a PFI or the
source for the hardware analog trigger. PFI signals are
explained in the Timing Connections section. Refer to
the Analog Trigger section of Chapter 3, Hardware
Overview, for more information about the hardware
analog trigger.
Output
As an output, this is the TRIG1 signal. In posttrigger
DAQ sequences, a low-to-high transition indicates the
initiation of the DAQ sequence. In pretrigger
applications, a low-to-high transition indicates the
initiation of the pretrigger conversions.
PFI1/TRIG2
DGND
Input
PFI1/Trigger 2—As an input, this is a PFI.
Output
As an output, this is the TRIG2 signal. In pretrigger
applications, a low-to-high transition indicates the
initiation of the posttrigger conversions. TRIG2 is not
used in posttrigger applications.
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Table 4-2. Signal Descriptions for I/O Connector Pins (Continued)
Signal Name
Reference
DGND
Direction
Description
PFI2/CONVERT*
Input
PFI2/Convert—As an input, this is a PFI.
Output
As an output, this is the CONVERT* signal.
A high-to-low edge on CONVERT* indicates that an
A/D conversion is occurring.
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
DGND
DGND
Input
PFI3/Counter 1 Source—As an input, this is a PFI.
Output
As an output, this is the GPCTR1_SOURCE signal. This
signal reflects the actual source connected to the
general-purpose counter 1.
Input
PFI4/Counter 1 Gate—As an input, this is a PFI.
Output
As an output, this is the GPCTR1_GATE signal. This
signal reflects the actual gate signal connected to the
general-purpose counter 1.
GPCTR1_OUT
PFI5/UPDATE*
DGND
DGND
Output
Counter 1 Output—This output is from the
general-purpose counter 1 output.
Input
PFI5/Update—As an input, this is a PFI.
Output
As an output, this is the UPDATE* signal. A high-to-low
edge on UPDATE* indicates that the AO primary group
is being updated.
PFI6/WFTRIG
DGND
DGND
Input
PFI6/Waveform Trigger—As an input, this is a PFI.
Output
As an output, this is the WFTRIG signal. In timed
AO sequences, a low-to-high transition indicates the
initiation of the waveform generation.
PFI7/STARTSCAN
Input
PFI7/Start of Scan—As an input, this is a PFI.
Output
As an output, this is the STARTSCAN signal. This pin
pulses once at the start of each AI scan in the interval
scan. A low-to-high transition indicates the start of the
scan.
PFI8/GPCTR0_SOURCE
PFI9/GPCTR0_GATE
DGND
DGND
Input
PFI8/Counter 0 Source—As an input, this is a PFI.
Output
As an output, this is the GPCTR0_SOURCE signal. This
signal reflects the actual source connected to the
general-purpose counter 0.
Input
PFI9/Counter 0 Gate—As an input, this is a PFI.
Output
As an output, this is the GPCTR0_GATE signal. This
signal reflects the actual gate signal connected to the
general-purpose counter 0.
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Table 4-2. Signal Descriptions for I/O Connector Pins (Continued)
Signal Name
GPCTR0_OUT
Reference
DGND
Direction
Description
Output
Counter 0 Output—This output is from the
general-purpose counter 0 output.
FREQ_OUT
DGND
Output
Frequency Output—This output is from the frequency
generator output.
Table 4-3. I/O Signal Summary for the NI PCI-6110/6111
Signal Impedance
Type and Input/
Direction Output
Protection
(Volts)
On/Off
Rise
Time
(mA at V) (ns)
Source
(mA at V)
Sink
Signal Name
Bias
ACH<0..3>+
AI
1 MΩ
42 V
—
—
—
—
in parallel
with
100 pF1
1 MΩ
in parallel
with
10 pF2
ACH<0..3>–
ACH<0..3>GND
DAC0OUT
AI
10 nF
—
42 V
—
—
—
—
—
—
—
200 pA
—
AI
AO
50 Ω
Short-circuit
to ground
5 at 10
5 at –10 300
—
V/µs
DAC1OUT
AO
50 Ω
Short-circuit
to ground
5 at 10
5 at –10 300
—
V/µs
AOGND
DGND
VCC
AO
DO
DO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.1 Ω
Short-circuit
to ground
1 A
DIO<0..7>
DIO
DO
DO
—
—
—
V
+0.5
—
13 at (V –0.4)
cc
24 at0.4 1.1
50 kΩ pu
50 kΩ pu
50 kΩ pu
cc
SCANCLK
EXTSTROBE*
PFI0/TRIG1
3.5 at (V –0.4) 5 at 0.4
cc
1.5
1.5
1.5
—
3.5 at (V –0.4) 5 at 0.4
cc
AI/DIO 10 kΩ
35 V +0.5 3.5 at (V –0.4) 5 at 0.4
9 kΩ pu
and
cc
cc
10 kΩ pd
PFI1/TRIG2
DIO
DIO
—
—
V
V
+0.5
+0.5
3.5 at (V –0.4) 5 at 0.4
cc
1.5
1.5
50 kΩ pu
cc
cc
PFI2/CONVERT*
3.5 at (V –0.4) 5 at 0.4
cc
50 kΩ pu
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Table 4-3. I/O Signal Summary for the NI PCI-6110/6111 (Continued)
Signal Impedance
Type and Input/
Direction Output
Protection
(Volts)
On/Off
Rise
Time
(mA at V) (ns)
Source
(mA at V)
Sink
Signal Name
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
Bias
DIO
DIO
DO
—
—
—
—
—
—
—
—
—
—
V
V
+0.5
+0.5
—
3.5 at (V –0.4) 5 at 0.4
cc
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
50 kΩ pu
cc
cc
3.5 at (V –0.4) 5 at 0.4
cc
3.5 at (V –0.4) 5 at 0.4
cc
PFI5/UPDATE*
DIO
DIO
DIO
DIO
DIO
DO
V
V
V
V
V
+0.5
+0.5
+0.5
+0.5
+0.5
—
3.5 at (V –0.4) 5 at 0.4
cc
cc
cc
cc
cc
cc
PFI6/WFTRIG
3.5 at (V –0.4) 5 at 0.4
cc
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
PFI9/GPCTR0_GATE
GPCTR0_OUT
3.5 at (V –0.4) 5 at 0.4
cc
3.5 at (V –0.4) 5 at 0.4
cc
3.5 at (V –0.4) 5 at 0.4
cc
3.5 at (V –0.4) 5 at 0.4
cc
FREQ_OUT
DO
—
3.5 at (V –0.4) 5 at 0.4
cc
1 Applies to gain ≤ 1, impedance refers to ACH<0..3>–
2 Applies to gain > 1, impedance refers to ACH<0..3>–
AI/DIO = Analog Input/Digital I/O, DO = Digital Output, pd = pull-down, pu = pull-up
The tolerance on the 50 kΩ pull-up and pull-down resistors is very large. Actual value may range between 17 and 100 kΩ.
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Connecting Analog Input Signals
The NI PCI-6110/6111 channels are configured as pseudodifferential
inputs. The input signal of each channel, ACH<0..3>+, is tied to the
positive input of the PGIA, and each reference signal ACH<0..3>–, is tied
to the negative input of the PGIA. The inputs are differential only in the
sense that ground loops are broken. The reference signal, ACH<0..3>–, is
not intended to carry signals of interest but only to provide a DC reference
point for ACH<0..3>+ that may be different from ground.
Pseudodifferential signal connections reduce noise pickup and increase
common-mode noise rejection. This connection type also allows input
signals to float within the common-mode limits of the PGIA.
signals. Exceeding the maximum input voltage rating can damage the device and the
computer. NI is not liable for any damage resulting from such signal connections.
The maximum input voltage ratings are listed in the Protection column of Table 4-3.
You can use the PGIA in different ways when using different input
configurations. Figure 4-3 shows a diagram of the PGIA.
Instrumentation
Vin+
+
Amplifier
+
PGIA
Measured
Voltage
Vm
Vin–
–
–
Vm = [Vin+ – Vin–] × Gain
Figure 4-3. NI PCI-6110/6111 PGIA
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The PGIA applies gain and common-mode voltage rejection and presents
high input impedance to the AI signals connected to the NI PCI-6110/6111.
Signals are routed to the positive and negative inputs of the PGIA. The
PGIA converts two input signals to a signal that is the difference between
the two input signals multiplied by the gain setting of the amplifier. The
amplifier output voltage is referenced to the device ground. The ADC
measures this output voltage when it performs A/D conversions.
Types of Signal Sources
When making signal connections, first determine whether the signal
sources are floating or ground-referenced. The following sections describe
these two signal types.
Floating Signal Sources
A floating signal source is not connected in any way to the building ground
system but, rather, has an isolated ground-reference point. Some examples
of floating signal sources are outputs of transformers, thermocouples,
battery-powered devices, optical isolator outputs, and isolation amplifiers.
An instrument or device that has an isolated output is a floating signal
source. You must tie the ground reference of a floating signal to the
NI PCI-6110/6111 AI ground to establish a local or onboard reference for
the signal. Otherwise, the measured input signal varies as the source floats
out of the common-mode input range.
Ground-Referenced Signal Sources
A ground-referenced signal source is connected in some way to the
building system ground and is, therefore, already connected to a common
ground point with respect to the NI PCI-6110/6111, assuming that the
computer is plugged into the same power system. Nonisolated outputs of
instruments and devices that plug into the building power system fall into
this category.
The difference in ground potential between two instruments connected to
the same building power system is typically between 1 and 100 mV but can
be much higher if power distribution circuits are not properly connected.
If a grounded signal source is improperly measured, this difference may
appear as a measurement error. The connection instructions for grounded
signal sources are designed to eliminate this ground potential difference
from the measured signal.
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The following sections discuss the use of differential (DIFF) measurements
and considerations for measuring both floating and ground-referenced
signal sources.
Table 4-4 summarizes the recommended DIFF signal connections and
includes input examples for both types of signal sources.
Table 4-4. Signal Source Types
DIFF Input
Examples and
Signal Source
Floating Signal Source
(Not Connected to Building Ground)
Grounded Signal Source
Input Examples
• Ungrounded thermocouples
• Plug-in cards with nonisolated
outputs
• Signal conditioning with isolated
outputs
• Battery devices
Differential
(DIFF)
ACH0(+)
+
ACH0(+)
+
+
–
+
–
V
V
1
ACH0(–)
1
ACH0(–)
–
–
ACH0GND
See text for information on bias resistors.
ACH0GND
Differential Connection Considerations
A differential connection is one in which the NI PCI-6110/6111 AI signal
has its own reference signal or signal return path. The device channels are
always configured in DIFF input mode. The input signal is tied to the
positive input of the PGIA, and its reference signal, or return, is tied to the
negative input of the PGIA.
Each differential signal uses two inputs—one for the signal and one for its
reference signal.
Differential signal connections reduce noise pickup and increase
common-mode noise rejection. Differential signal connections also allow
input signals to float within the common-mode limits of the PGIA.
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Differential Connections for Ground-Referenced
Signal Sources
Figure 4-4 shows how to connect a ground-referenced signal source to a
channel on the NI PCI-6110/6111.
Instrumentation
ACH0+
Amplifier
+
Ground-
Referenced
Signal
+
Vs
PGIA
+
–
Source
–
+
ACH0–
Measured
Voltage
–
Vm
Common-
Mode
Noise and
Ground
Vcm
–
Potential
ACH0GND
I/O Connector
ACH0 Connections Shown
Figure 4-4. Differential Input Connections for Ground-Referenced Signals
With this type of connection, the PGIA rejects both the common-mode
noise in the signal and the ground potential difference between the signal
source and the device ground, shown as Vcm in Figure 4-4.
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Differential Connections for Nonreferenced or
Floating Signal Sources
Figure 4-5 shows how to connect a floating signal source to a channel on
the NI PCI-6110/6111.
ACH0+
Instrumentation
+
Vs
Amplifier
Floating
Signal
+
100pf
1MΩ
Source
–
PGIA
+
–
ACH0–
Measured
Voltage
–
Vm
Bias
Current
Return
Paths
10nf
Bias
Resistor
(see text)
ACH0GND
I/O Connector
ACH0 Connections Shown
Figure 4-5. Differential Input Connections for Nonreferenced Signals
Figure 4-5 shows a bias resistor connected between ACH0– and the
floating signal source ground. If you do not use the resistor and the source
range of the PGIA, and the PGIA saturates, causing erroneous readings.
You must reference the source to the respective channel ground.
Common-Mode Signal Rejection Considerations
Figure 4-4 shows connections for signal sources that are already referenced
to some ground point with respect to the NI PCI-6110/6111. In theory,
the PGIA can reject any voltage caused by ground-potential differences
between the signal source and the device. In addition, with
pseudodifferential input connections, the PGIA can reject common-mode
noise pickup in the leads connecting the signal sources to the device.
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Like any amplifier, the common-mode rejection ratio (CMRR) of the PGIA
is limited at high frequency. This limitation has been compensated for in the
design of the NI PCI-6110/6111 by using a common-mode choke on each
channel. The purpose of the 10 nF capacitance on the ACH<0..3>–
connection is to provide an impedance for this choke to work against at
high frequency, thus improving the high-frequency CMRR.
Depending upon your application and the type of common noise at your
source, further common-noise rejection might be gained by placing a
0.1 µF ceramic bypass capacitor between ACH<0..3> and
ACH<0..3>GND.
Working Voltage Range
The PGIA operates normally by amplifying signals of interest while
rejecting common-mode signals as long as the following three conditions
are met:
1. The common-mode voltage (Vcm), which is equivalent to subtracting
ACH<0..3>GND from ACH<0..3>– and which is shown in Figure 4-5,
must be less than 11 V. This Vcm is a constant for all range selections.
2. The signal voltage (Vs), which is equivalent to subtracting
ACH<0..3>– from ACH<0..3>+ and which is shown in Figure 4-5,
must be less than or equal to the range selection of the given channel.
If Vs is greater than the range selected, the signal clips and information
is lost.
3. The total working voltage of the positive input, which can be thought
of as (Vcm + Vs) or simply as subtracting ACH<0..3>GND from
ACH<0..3>+, must be less than 11 V for ranges ≤ 10 V or less than
42 V for ranges > 10 V.
If any of these conditions are exceeded, current limiters limit the input
current to 20 mA maximum into any input until the fault condition is
removed.
Note All inputs are protected at up to 42 V.
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Analog Output Signal Connections
DAC0OUT is the voltage output signal for AO channel 0, DAC1OUT is the
voltage output signal for AO channel 1, and AOGND is the ground
reference signal for the AO channels.
Figure 4-6 shows how to make AO connections to the NI PCI-6110/6111.
DAC0OUT
Channel 0
+
Load
Load
VOUT 0
–
AOGND
–
VOUT 1
DAC1OUT
+
Channel 1
Analog Output Channels
NI PCI-6110/6111
Figure 4-6. Analog Output Connections
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Digital I/O Signal Connections
The DIO signals are DIO<0..7> and DGND. DIO<0..7> are the signals
making up the DIO port, and DGND is the ground reference signal for the
Caution Exceeding the maximum input voltage ratings, which are listed in Table 4-3, can
damage the NI PCI-6110/6111 and the computer. NI is not liable for any damage resulting
from such signal connections.
Figure 4-7 shows signal connections for three typical DIO applications.
+5 V
LED
DIO<4..7>
TTL Signal
DIO<0..3>
+5 V
Switch
DGND
I/O Connector
NI PCI-6110/6111
Figure 4-7. Digital I/O Connections
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Figure 4-7 shows DIO<0..3> configured for digital input and DIO<4..7>
configured for digital output. Digital input applications include receiving
TTL signals and sensing external device states, such as the switch state
shown in Figure 4-7. Digital output applications include sending TTL
signals and driving external devices, such as the LED shown in Figure 4-7.
Power Connections
Two pins on the I/O connector supply +5 V from the computer power
supply using a self-resetting fuse. The fuse resets automatically within a
few seconds after the overcurrent condition is removed. These pins are
referenced to DGND and can be used to power external digital circuitry.
Power rating+4.65 to +5.25 VDC at 1 A
Caution Under no circumstances should you connect these +5 V power pins directly to
analog or digital ground or to any other voltage source on the NI PCI-6110/6111 or any
other device. Doing so can damage the device and the computer. NI is not liable for damage
resulting from such a connection.
Timing Connections
damage the NI PCI-6110/6111 and the computer. NI is not liable for any damage resulting
from such signal connections.
All external control over the timing of the NI PCI-6110/6111 is routed
through the 10 PFIs, labeled PFI0 through PFI9. These signals are
explained in the next section, Programmable Function Input Connections.
These PFIs are bidirectional; as outputs they are not programmable and
reflect the state of many DAQ, waveform generation, and general-purpose
timing signals. There are five other dedicated outputs for the remainder of
the timing signals. As inputs, the PFI signals are programmable and can
control any DAQ, waveform generation, and general-purpose timing
signals.
The DAQ signals are explained in the DAQ Timing Connections section.
The waveform generation signals are explained in the Waveform
signals are explained in the General-Purpose Timing Signal Connections
section.
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All digital timing connections are referenced to DGND. Figure 4-8
illustrates how to connect an external TRIG1 source and an external
CONVERT* source to two NI PCI-6110/6111 PFI pins.
PFI0/TRIG1
PFI7/STARTSCAN
TRIG1
Source
STARTSCAN
Source
DGND
I/O Connector
NI PCI-6110/6111
Figure 4-8. Timing I/O Connections
Programmable Function Input Connections
There are a total of 13 internal timing signals that you can externally
control from the PFI pins. The source for each signal is software-selectable
from any PFI when you want external control. This flexible routing scheme
reduces the need to change the physical wiring to the device I/O connector
for applications requiring alternative wiring.
You can individually enable each PFI pin to output a specific internal
timing signal. For example, if you need the STARTSCAN* signal as an
output on the I/O connector, software can turn on the output driver for the
PFI2/STARTSCAN* pin.
Caution Be careful not to externally drive a PFI signal when it is configured as an output.
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In edge-detection mode, the minimum pulse width required is 10 ns.
This setting applies for both rising-edge and falling-edge polarity settings.
Edge-detect mode does not have a maximum pulse-width requirement.
In level-detection mode, the PFIs themselves do not impose a minimum or
maximum pulse-width requirement, but the particular timing signal being
controlled can impose limits. These requirements are listed later in this
chapter.
DAQ Timing Connections
The DAQ timing signals are TRIG1, TRIG2, STARTSCAN, CONVERT*,
AIGATE, SISOURCE, SCANCLK, and EXTSTROBE*.
Posttriggered data acquisition allows you to view only data that is acquired
after a trigger event is received. A typical posttriggered DAQ sequence is
shown in Figure 4-9. On the NI PCI-6110/6111, each STARTSCAN pulse
initiates one CONVERT* pulse.
TRIG1
STARTSCAN
CONVERT*
Scan Counter
4
3
2
1
0
Figure 4-9. Typical Posttriggered Acquisition
Pretriggered data acquisition allows you to view data that is acquired before
the trigger of interest in addition to data acquired after the trigger.
Figure 4-10 shows a typical pretriggered DAQ sequence. The description
for each signal shown in these figures appears later in this chapter.
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TRIG1
TRIG2
n/a
STARTSCAN
CONVERT*
Scan Counter
3
2
1
0
2
2
2
1
0
Figure 4-10. Typical Pretriggered Acquisition
TRIG1 Signal
Any PFI pin can receive as an input the TRIG1 signal, which is available
as an output on the PFI0/TRIG1 pin.
Refer to Figures 4-9 and 4-10 for the relationship of TRIG1 to the
DAQ sequence.
As an input, the TRIG1 signal is configured in the edge-detection mode.
You can select any PFI pin as the source for TRIG1 and configure the
polarity selection for either rising or falling edge. The selected edge of the
TRIG1 starts the DAQ sequence for both posttriggered and pretriggered
acquisitions. The NI PCI-6110/6111 supports analog triggering on the
PFI0/TRIG1 pin. Refer to Chapter 3, Hardware Overview, for more
information on analog triggering.
As an output, TRIG1 reflects the action that initiates a DAQ sequence even
if another PFI is externally triggering the acquisition. The output is an
active high pulse with a pulse width of 25 to 50 ns. This output is set to
high-impedance at startup.
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Figures 4-11 and 4-12 show the timing requirements for TRIG1.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-11. TRIG1 Input Signal Timing
tw
tw = 25 to 50 ns
Figure 4-12. TRIG1 Output Signal Timing
The device also uses TRIG1 to initiate pretriggered DAQ operations. In
most pretriggered applications, TRIG1 is generated by a software trigger.
of TRIG1 and TRIG2 in a pretriggered DAQ operation.
TRIG2 Signal
Any PFI pin can receive as an input the TRIG2 signal, which is available
as an output on the PFI1/TRIG2 pin. Refer to Figure 4-10 for the
relationship of TRIG2 to the DAQ sequence.
As an input, TRIG2 is configured in the edge-detection mode. You can
select any PFI pin as the source for TRIG2 and configure the polarity
selection for either rising or falling edge. The selected edge of TRIG2
initiates the posttriggered phase of a pretriggered DAQ sequence. In
pretriggered mode, the TRIG1 signal initiates the data acquisition. The scan
counter (SC) indicates the minimum number of scans before TRIG2 can be
recognized. After the SC decrements to zero, it is loaded with the number
of posttrigger scans to acquire while the acquisition continues. The device
ignores TRIG2 if it is asserted prior to the SC decrementing to zero. After
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the selected edge of TRIG2 is received, the device acquires a fixed number
of scans and the acquisition stops. This mode acquires data both before and
after receiving TRIG2.
sequence even if another PFI is externally triggering the acquisition.
TRIG2 is not used in posttriggered data acquisition. The output is an active
high pulse with a pulse width of 25 to 50 ns. This output is set to high
impedance at startup.
Figures 4-13 and 4-14 show the timing requirements for TRIG2.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-13. TRIG2 Input Signal Timing
tw
tw = 25 to 50 ns
Figure 4-14. TRIG2 Output Signal Timing
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STARTSCAN Signal
Any PFI pin can receive as an input the STARTSCAN signal, which is
available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-9
and 4-10 for the relationship of STARTSCAN to the DAQ sequence.
As an input, STARTSCAN is configured in the edge-detection mode.
You can select any PFI pin as the source for STARTSCAN and configure
the polarity selection for either rising or falling edge. The selected edge of
STARTSCAN initiates a scan. The sample interval counter (SI2) starts if
you select internally triggered CONVERT*.
As an output, STARTSCAN reflects the actual start pulse that initiates a
scan even if another PFI is externally triggering the starts. You have two
output options. The first is an active high pulse with a pulse width of 25 to
high pulse that terminates at the start of the last conversion in the scan,
which indicates a scan in progress. STARTSCAN is deasserted toff after the
last conversion in the scan is initiated. This output is set to high-impedance
at startup.
Figures 4-15 and 4-16 show the input and output timing requirements for
STARTSCAN.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-15. STARTSCAN Input Signal Timing
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tw
tw = 25 to 50 ns
a. Star of Scan
Start Pulse
CONVERT*
STARTSCAN
t
off = 10 ns minimum
toff
b. Scan in Progress, Two Conversions per Scan
Figure 4-16. STARTSCAN Output Signal Timing
The CONVERT* pulses are masked off until the device generates the
STARTSCAN signal. If you are using internally generated conversions,
the first CONVERT* appears when SI2 reaches zero. If you select an
external CONVERT*, the first external pulse after STARTSCAN generates
a conversion. The STARTSCAN pulses should be separated by at least one
scan period.
A counter on the NI PCI-6110/6111 device internally generates
STARTSCAN unless you select some external source. This counter is
started by the TRIG1 signal and is stopped by either software or the SC.
Scans generated by either an internal or external STARTSCAN signal are
inhibited unless they occur within a DAQ sequence. Scans occurring within
a DAQ sequence may be gated by either the hardware (AIGATE) signal or
software command register gate.
The NI PCI-6110/6111 uses a three-point analog FIFO to digitize the input.
(internally supplied unless you pass 0 for the scanTimebase), it is not sent
to NI-DAQ until three additional edges of STARTSCAN clock the point.
Consequently, you may not see the last three points of the acquisition.
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If you are performing an internally timed acquisition, NI-DAQ generates
three extra points to clock the data for you. However, if you perform an
externally clocked acquisition, NI-DAQ does not know when the last point
is taken, so you must provide the three extra pulses.
CONVERT* Signal
Any PFI pin can receive as an input the CONVERT* signal, which is
available as an output on the PFI2/CONVERT* pin.
Refer to Figures 4-9 and 4-10 for the relationship of CONVERT* to the
DAQ sequence.
As an input, CONVERT* is configured in the edge-detection mode.
You can select any PFI pin as the source for CONVERT* and configure
the polarity selection for either rising or falling edge. The selected edge
of CONVERT* initiates an A/D conversion.
As an output, CONVERT* reflects the actual convert pulse that is
connected to the ADC, even if another PFI is externally generating the
conversions. The output is an active low pulse with a pulse width of 50 to
100 ns. This output is set to high-impedance at startup.
Figures 4-17 and 4-18 show the timing requirements for CONVERT*.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-17. CONVERT* Input Signal Timing
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tw
tw = 50 to 100 ns
Figure 4-18. CONVERT* Output Signal Timing
The ADC switches to hold mode within 20 ns of the selected edge. This
hold-mode delay time is a function of temperature and does not vary from
one conversion to the next.
The SI2 on the NI PCI-6110/6111 normally generates CONVERT* unless
you select some external source. The counter is started by the
STARTSCAN signal and continues to count down and reload itself until the
scan is finished. It then reloads itself in preparation for the next
STARTSCAN pulse.
A/D conversions generated by either an internal or external CONVERT*
signal are inhibited unless they occur within a DAQ sequence. Scans
occurring within a DAQ sequence may be gated by either the hardware
(AIGATE) signal or software command register gate.
AIGATE Signal
Any PFI pin can receive as an input the AIGATE signal, which is not
available as an output on the I/O connector. The AIGATE signal can mask
off scans in a DAQ sequence. You can configure the PFI pin you select as
the source for the AIGATE signal in either the level-detection or
edge-detection mode. You can configure the polarity selection for the
PFI pin for either active high or active low.
In the level-detection mode if AIGATE is active, the STARTSCAN signal
is masked off and no scans can occur. In the edge-detection mode, the first
active edge disables the STARTSCAN signal, and the second active edge
enables STARTSCAN.
AIGATE can neither stop a scan in progress nor continue a previously
conversions until the beginning of the next scan and, conversely, if
conversions are being gated off, AIGATE does not gate them back on until
the beginning of the next scan.
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SISOURCE Signal
Any PFI pin can receive as an input the SISOURCE signal, which is not
available as an output on the I/O connector. The SI2 uses SISOURCE as
a clock to time the generation of the STARTSCAN signal. You must
configure the PFI pin you select as the source for SISOURCE in the
level-detection mode. You can configure the polarity selection for the
PFI pin for either active high or active low.
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 23 ns high or low. There is no minimum frequency limitation.
Either the 20 MHz or 100 kHz internal timebase generates SISOURCE
unless you select some external source. Figure 4-19 shows the timing
requirements for SISOURCE.
tp
tw
tw
tp = 50 ns minimum
tw = 23 ns minimum
Figure 4-19. SISOURCE Signal Timing
SCANCLK Signal
SCANCLK is an output-only signal that generates a pulse with the leading
edge occurring approximately 50 to 100 ns after an A/D conversion begins.
The polarity of this output is software-selectable, but it is typically
configured so that a low-to-high leading edge can clock external AI
multiplexers indicating when the input signal has been sampled and can be
removed. This signal has a 450 ns pulse width and is software enabled.
Note SCANCLK polarity is low-to-high and cannot be changed programmatically using
NI-DAQ.
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Figure 4-20 shows the timing for SCANCLK.
CONVERT*
td
tw
SCANCLK
td = 50 to 100 ns
tw = 450 ns
Figure 4-20. SCANCLK Signal Timing
EXTSTROBE* Signal
EXTSTROBE* is an output-only signal that generates either a single pulse
or a sequence of eight pulses in the hardware-strobe mode. An external
device can use this signal to latch signals or to trigger events. In the
and a 1.2 µs clock are available for generating a sequence of eight pulses in
the hardware-strobe mode.
Note EXTSTROBE* cannot be enabled through NI-DAQ.
Figure 4-21 shows the timing for the hardware-strobe mode
EXTSTROBE* signal.
VOH
VOL
tw
tw
tw = 600 ns or 5 µs
Figure 4-21. EXTSTROBE* Signal Timing
Waveform Generation Timing Connections
The analog group defined for the NI PCI-6110/6111 is controlled by
WFTRIG, UPDATE*, and UISOURCE.
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WFTRIG Signal
Any PFI pin can externally input the WFTRIG signal, which is available as
an output on the PFI6/WFTRIG pin.
As an input, WFTRIG is configured in the edge-detection mode. You can
select any PFI pin as the source for WFTRIG and configure the polarity
selection for either rising or falling edge. The selected edge of WFTRIG
starts the waveform generation for the DACs. The update interval counter
(UI) is started if you select internally generated UPDATE*.
As an output, WFTRIG reflects the trigger that initiates waveform
generation, even if the waveform generation is being externally triggered
by another PFI. The output is an active high pulse with a pulse width of
25 to 50 ns. This output is set to high-impedance at startup.
Figures 4-22 and 4-23 show the timing requirements for WFTRIG.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-22. WFTRIG Input Signal Timing
tw
tw = 25 to 50 ns
Figure 4-23. WFTRIG Output Signal Timing
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UPDATE* Signal
Any PFI pin can externally input the UPDATE* signal, which is available
as an output on the PFI5/UPDATE* pin.
As an input, UPDATE* is configured in the edge-detection mode. You can
select any PFI pin as the source for UPDATE* and configure the polarity
selection for either rising or falling edge. The selected edge of UPDATE*
updates the outputs of the DACs. In order to use UPDATE*, you must set
the DACs to posted-update mode.
As an output, UPDATE* reflects the actual update pulse that is connected
to the DACs, even if the updates are being externally generated by another
PFI. The output is an active low pulse with a pulse width of 50 to 75 ns.
This output is set to high-impedance at startup.
Figures 4-24 and 4-25 show the timing requirements for UPDATE*.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-24. UPDATE* Input Signal Timing
tw
tw = 50 to 75 ns
Figure 4-25. UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the
DAC latches.
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The NI PCI-6110/6111UI normally generates UPDATE* unless you select
some external source. The WFTRIG signal starts the UI, and the UI can be
stopped by software or the internal Buffer Counter.
D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.
UISOURCE Signal
Any PFI pin can externally input the UISOURCE signal, which is not
clock to time the generation of the UPDATE* signal. You must configure
the PFI pin you select as the source for UISOURCE in the level-detection
mode. You can configure the polarity selection for the PFI pin for either
active high or active low.
Figure 4-26 shows the timing requirements for the UISOURCE signal.
tp
tw
tw
tp = 50 ns minimum
tw = 10 ns minimum
Figure 4-26. UISOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 10 ns high or low. There is no minimum frequency limitation.
Either the 20 MHz or 100 kHz internal timebase normally generates the
UISOURCE signal unless you select some external source.
General-Purpose Timing Signal Connections
The general-purpose timing signals are GPCTR0_SOURCE,
GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN,
GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT,
GPCTR1_UP_DOWN, and FREQ_OUT.
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GPCTR0_SOURCE Signal
Any PFI pin can externally input the GPCTR0_SOURCE signal, which is
available as an output on the PFI8/GPCTR0_SOURCE pin.
As an input, GPCTR0_SOURCE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR0_SOURCE and
As an output, GPCTR0_SOURCE reflects the actual clock connected to
general-purpose counter 0, even if another PFI is externally inputting the
source clock. This output is set to high-impedance at startup.
Figure 4-27 shows the timing requirements for GPCTR0_SOURCE.
tp
tw
tw
tp = 50 ns minimum
tw = 10 ns minimum
Figure 4-27. GPCTR0_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 10 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the
GPCTR0_SOURCE signal unless you select some external source.
GPCTR0_GATE Signal
Any PFI pin can externally input the GPCTR0_GATE signal, which is
available as an output on the PFI9/GPCTR0_GATE pin.
As an input, GPCTR0_GATE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR0_GATE and configure
the polarity selection for either rising or falling edge. You can use the gate
signal in a variety of different applications to perform actions such as
starting and stopping the counter, generating interrupts, and saving the
counter contents.
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As an output, GPCTR0_GATE reflects the actual gate signal connected to
general-purpose counter 0, even if the gate is being externally generated by
another PFI. This output is set to high-impedance at startup.
Figure 4-28 shows the timing requirements for the GPCTR0_GATE signal.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-28. GPCTR0_GATE Signal Timing
GPCTR0_OUT Signal
This signal is available only as an output on the GPCTR0_OUT pin.
The GPCTR0_OUT signal reflects the terminal count (TC) of
general-purpose counter 0. You have two software-selectable output
options—pulse on TC and toggle output polarity on TC. The output
polarity is software-selectable for both options. This output is set to
high-impedance at startup. Figure 4-29 shows the timing of
GPCTR0_OUT.
TC
GPCTR0_SOURCE
GPCTR0_OUT
(Pulse on TC)
GPCTR0_OUT
(Toggle Output on TC)
Figure 4-29. GPCTR0_OUT Signal Timing
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GPCTR0_UP_DOWN Signal
This signal can be externally input on the DIO6 pin and is not available as
an output on the I/O connector. The general-purpose counter 0 counts down
when this pin is at a logic low and counts up when it is at a logic high. You
can disable this input so that software controls the up-down functionality
and leaves the DIO6 pin free for general use.
GPCTR1_SOURCE Signal
Any PFI pin can externally input the GPCTR1_SOURCE signal, which is
available as an output on the PFI3/GPCTR1_SOURCE pin.
As an input, GPCTR1_SOURCE is configured in the edge-detection mode.
You can select any PFI pin as the source for GPCTR1_SOURCE and
As an output, GPCTR1_SOURCE monitors the actual clock connected to
general-purpose counter 1, even if the source clock is being externally
generated by another PFI. This output is set to tri-state at startup.
Figure 4-30 shows the timing requirements for GPCTR1_SOURCE.
tp
tw
tw
tp = 50 ns minimum
tw = 10 ns minimum
Figure 4-30. GPCTR1_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width
of 10 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the
GPCTR1_SOURCE unless you select some external source.
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GPCTR1_GATE Signal
Any PFI pin can externally input the GPCTR1_GATE signal, which is
available as an output on the PFI4/GPCTR1_GATE pin.
As an input, GPCTR1_GATE is configured in edge-detection mode. You
can select any PFI pin as the source for GPCTR1_GATE and configure the
polarity selection for either rising or falling edge. You can use the gate
signal in a variety of different applications to perform such actions as
starting and stopping the counter, generating interrupts, saving the counter
contents, and so on.
As an output, GPCTR1_GATE monitors the actual gate signal connected to
general-purpose counter 1, even if the gate is being externally generated by
another PFI. This output is set to high-impedance at startup.
Figure 4-31 shows the timing requirements for the GPCTR1_GATE signal.
tw
Rising-Edge
Polarity
Falling-Edge
Polarity
tw = 10 ns minimum
Figure 4-31. GPCTR1_GATE Signal Timing
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GPCTR1_OUT Signal
This signal is available only as an output on the GPCTR1_OUT pin.
The GPCTR1_OUT signal monitors the TC of general-purpose counter 1.
You have two software-selectable output options—pulse on TC and toggle
output polarity on TC. The output polarity is software-selectable for both
options. This output is set to high-impedance at startup. Figure 4-32 shows
the timing requirements for GPCTR1_OUT.
TC
GPCTR1_SOURCE
GPCTR1_OUT
(Pulse on TC)
GPCTR1_OUT
(Toggle Output on TC)
Figure 4-32. GPCTR1_OUT Signal Timing
GPCTR1_UP_DOWN Signal
an output on the I/O connector. General-purpose counter 1 counts down
when this pin is at a logic low and counts up at a logic high. This input can
be disabled so that software can control the up-down functionality and
leave the DIO7 pin free for general use.
Figure 4-33 shows the timing requirements for the GATE and SOURCE
input signals and the timing specifications for the NI PCI-6110/6111 OUT
output signals.
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tsc
tsp
tsp
VIH
SOURCE
VIL
tgsu
tgh
VIH
VIL
GATE
OUT
tgw
tout
VOH
VOL
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
tsc
tsp
tgsu
tgh
tgw
tout
50 ns minimum
23 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
Figure 4-33. GPCTR Timing Summary
The GATE and OUT signal transitions shown in Figure 4-33 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
edge of the source signal, applies when the counter is programmed to count
falling edges.
SOURCE input or to one of the internally generated signals on the
NI PCI-6110/6111. Figure 4-33 shows the GATE signal referenced to the
rising edge of a source signal. The gate must be valid (either high or low)
for at least 10 ns before the rising or falling edge of a source signal for the
gate to take effect at that source edge, as shown by tgsu and tgh in
Figure 4-33. The gate signal is not required to be held after the active edge
of the source signal.
If you use an internal timebase clock, the gate signal cannot be
synchronized with the clock. In this case, gates applied close to a source
edge take effect either on that source edge or on the next one. This
arrangement results in an uncertainty of one source clock period with
respect to unsynchronized gating sources.
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The OUT output timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated clock signals on the
NI PCI-6110/6111. Figure 4-33 shows the OUT signal referenced to the
rising edge of a source signal. Any OUT signal state changes occur within
80 ns after the rising or falling edge of the source signal.
FREQ_OUT Signal
This signal is available only as an output on the FREQ_OUT pin.
The frequency generator for the NI PCI-6110/6111 outputs the
FREQ_OUT pin. The frequency generator is a 4-bit counter that can divide
its input clock by the numbers 1 through 16. The input clock of the
frequency generator is software-selectable from the internal 10 MHz and
100 kHz timebases. The output polarity is software-selectable. This output
is set to high-impedance at startup.
Field Wiring Considerations
Environmental noise can seriously affect the measurement accuracy of the
NI PCI-6110/6111 if you do not take proper care when running signal wires
between signal sources and the device. The following recommendations
apply mainly to AI signal routing to the device, although they also apply to
signal routing in general.
Minimize noise pickup and maximize measurement accuracy by taking the
following precautions:
•
•
Use differential AI connections to reject common-mode noise.
Use individually shielded, twisted-pair wires to connect AI signals to
the device. With this type of wire, the signals attached to the ACH+ and
ACH– inputs are twisted together and then covered with a shield. You
then connect this shield only at one point to the signal source ground.
This kind of connection is required for signals traveling through areas
with large magnetic fields or high electromagnetic interference.
•
•
Route signals to the device carefully. Keep cabling away from noise
sources. The most common noise source in a PCI DAQ system is the
video monitor. Separate the monitor from the analog signals as far as
possible.
Separate the NI PCI-6110/6111 signal lines from high-current or
high-voltage lines. These lines can induce currents in or voltages on
the NI PCI-6110/6111 signal lines if they run in parallel paths at a
close distance. To reduce the magnetic coupling between lines,
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separate them by a reasonable distance if they run in parallel, or run the
lines at right angles to each other.
•
•
Do not run signal lines through conduits that also contain power lines.
Protect signal lines from magnetic fields caused by electric motors,
welding equipment, breakers, or transformers by running them through
special metal conduits.
For more information, refer to the NI Developer Zone tutorial, Field Wiring
and Noise Consideration for Analog Signals, available at ni.com/zone.
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5
Calibration
This chapter discusses the calibration procedures for the
NI PCI-6110/6111. NI-DAQ includes calibration functions for performing
all of the steps in the calibration process.
Calibration refers to the process of minimizing measurement and
output voltage errors by making small circuit adjustments. On the
NI PCI-6110/6111, these adjustments take the form of writing values
to onboard calibration DACs (CalDACs).
Most applications require some form of device calibration. If you do not
calibrate the device, the signals and measurements could have very large
offset, gain, and linearity errors.
Three levels of calibration are available to you and described in this chapter.
The first level is the fastest, easiest, and least accurate; whereas, the last
level is the slowest, most difficult, and most accurate.
Loading Calibration Constants
The NI PCI-6110/6111 is factory calibrated before shipment at
approximately 25 °C to the levels indicated in Appendix A, Specifications.
The associated calibration constants—the values that were written to the
CalDACs to achieve calibration in the factory—are stored in the onboard
nonvolatile memory (EEPROM). Because the CalDACs have no memory
capability, they do not retain calibration information when the device is
unpowered. Loading calibration constants refers to the process of loading
the CalDACs with the values stored in the EEPROM. NI-DAQ determines
when this is necessary and does it automatically. If you are not using
NI-DAQ, you must load these values yourself.
In the EEPROM there is a user-modifiable calibration area in addition to
the permanent factory calibration area. This means that you can load the
CalDACs with values either from the original factory calibration or from a
calibration that you subsequently performed.
This method of calibration is not very accurate because it does not take into
account the fact that the device measurement and output voltage errors can
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Calibration
vary with time and temperature. It is better to self-calibrate when the device
is installed in the environment in which it is used.
Self-Calibration
The NI PCI-6110/6111 can measure and correct for almost all of its
calibration-related errors without any external signal connections. NI-DAQ
provides a self-calibration method. This self-calibration process, which
generally takes less than a minute, is the preferred method of assuring
accuracy in your application. Initiate self-calibration to minimize the
effects of offset, gain, and linearity drifts, particularly those due to warmup.
Immediately after self-calibration, the only significant residual calibration
error could be gain error due to time or temperature drift of the onboard
voltage reference. This error is addressed by external calibration, which is
discussed in the following section. If you are interested primarily in relative
measurements, you can ignore a small amount of gain error, and
self-calibration should be sufficient.
External Calibration
The NI PCI-6110/6111 has an onboard calibration reference to ensure the
accuracy of self-calibration. The specifications are listed in Appendix A,
Specifications. The reference voltage is measured at the factory and stored
in the EEPROM for subsequent self-calibrations. This voltage is stable
enough for most applications, but if you are using the device at an extreme
temperature or if the onboard reference has not been measured for a year or
more, you may wish to externally calibrate the device.
An external calibration refers to calibrating the device with a known
external reference rather than relying on the onboard reference.
Redetermining the value of the onboard reference is part of this process and
the results can be saved in the EEPROM, so you should not have to perform
an external calibration very often. You can externally calibrate the device
by calling the NI-DAQ calibration function.
To externally calibrate the device, be sure to use a very accurate external
reference. The reference should be several times more accurate than the
device itself. For example, to calibrate a 16-bit device, the external
For a detailed calibration procedure for the NI PCI-6110/6111, click
Manual Calibration Procedures at ni.com/calibration.
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A
Specifications
This appendix lists the specifications of the NI PCI-6110/6111.
These specifications are typical at 25 °C unless otherwise noted.
Analog Input
Input Characteristics
Number of channels
NI PCI-6110.................................... 4 pseudodifferential
NI PCI-6111.................................... 2 pseudodifferential
Type of ADC
Resolution ....................................... 12 bits, 1 in 4,096
Pipeline ........................................... 3
Sampling rate
Maximum........................................ 5 MS/s
Minimum ........................................ 1 kS/s
Input coupling ........................................ DC or AC
Max working voltage for all AI channels
Maximum Working Voltage
Input Channels
Range
20 mV to 10 V
20 to 42 V
All
(Signal + Common Mode)
Should remain within 11 V of ground
Should remain within 42 V of ground
Should remain within 11 V of ground
ACH<0..3>+
ACH<0..3>–
Overvoltage protection........................... 42 V
Inputs protected
Positive input .................................. All channels
Negative input................................. All channels
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Appendix A
Specifications
FIFO buffer size......................................8,192 samples
Data transfers..........................................DMA, interrupts,
programmed I/O
DMA modes ...........................................Scatter-gather (single transfer,
demand transfer)
Accuracy Information
Table A-1. NI PCI-6110/6111 Accuracy Information
Absolute Accuracy
Relative Accuracy
Resolution (mV)
Nominal
Range
(V)
Noise + Quantization
(mV)
Temp
Drift
% of Reading
Offset
(mV)
Full
Scale
24 Hours
0.51
90 Days
0.51
1 Year
0.51
Single Pt.
Averaged
4.4
(%/°C)
0.0005
0.0005
0.0005
0.0005
0.0005
0.0005
0.0005
0.0005
Theoretical
24
Averaged
5.8
42
20
10
5
35
20
51
20
0.51
0.51
0.51
1.8
9.8
4.9
2.3
1.2
0.11
0.11
0.11
5.7
3
10
0.88
0.057
0.057
0.057
0.057
0.057
0.058
0.058
0.058
0.058
0.058
0.059
0.059
0.059
0.059
0.059
5.1
2
0.44
2.4
0.58
0.23
0.12
0.077
0.046
2
1.3
0.7
0.4
0.2
0.18
0.98
0.49
0.24
0.098
1
1
0.088
0.059
0.035
0.5
0.2
0.67
0.39
Note: Accuracies are valid for measurements following an internal calibration. Averaged numbers assume dithering and averaging of
100 single-channel readings.
Measurement accuracies are listed for operational temperatures within 1 °C of internal calibration temperature and 10 °C of external or
factory calibration temperature. A one-year calibration interval is recommended.
Transfer Characteristics
INL.......................................................... 0.5 LSB typ, 1 LSB max
DNL........................................................ 0.3 LSB typ, 0.75 LSB max
Spurious free dynamic range (SFDR) ....Refer to Table A-2
Effective number of bits (ENOB)...........11.0 bits, DC to 100 kHz
Offset and gain error...............................Refer to Table A-1
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Appendix A
Specifications
Amplifier Characteristics
Input impedance
ACH<0..3>+ to ACH<0..3>–
Normal powered on ................. 1 MΩ in parallel with 100 pF
Powered off.............................. 1 MΩ minimum
Overload .................................. 1 MΩ
Impedance to ground
ACH<0..3>– to ground............ 10 nF
Input bias current ................................... 300 pA
Input offset current................................. 200 pA
CMRR .................................................... Refer to Table A-2
Dynamic Characteristics
Interchannel skew .................................. 1 ns typ
fin = 100 kHz
input range = 10 V
Bandwidth
Range
200 mV
Small Signal (–3 dB)
4 MHz
500 mV to 50 V
5 MHz
Note Bandwidth specifications are for signals on the (+) input with the (–) input at
DC ground. The (–) input is slew rate limited to 24 V/µsec and has an additional 10 nF
capacitance to ground.
System noise .......................................... Refer to Table A-2
Crosstalk................................................. –80 dB, DC to 100 kHz
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Appendix A
Specifications
Table A-2. Analog Input Characteristics
System
Noise4
Bandwidth1
(MHz)
SFDR Typ2
(dB)
SFDR Max
(dB)
CMRR3
(dB)
Input Range
42 V
(LSBrms
)
5.5
4.4
7.2
4.8
4.8
4.4
4.4
4.1
78
78
81
81
85
85
85
81
70
70
75
75
75
75
75
70
34
40
46
52
60
66
70
72
0.5
20 V
0.5
10 V
0.5
5 V
0.5
2 V
0.5
1 V
0.5
500 mV
200 mV
0.6
1.0
1 –3 dB frequency for input amplitude at 96% of the input range (–0.3 dB)
2 Measured at 100 kHz
3 DC to 60 Hz
4 LSBrms, not including quantization
Stability
Recommended warm-up time.................15 minutes
Offset temperature coefficient
Pregain............................................. 5 µV/°C
Postgain ........................................... 50 µV/°C
Gain temperature coefficient .................. 20 ppm/°C
Onboard calibration reference
Level................................................5.000 V ( 2.5 mV)
(actual value stored in EEPROM)
Temperature coefficient................... 2.0 ppm/°C max
Long-term stability.......................... 6 ppm/ 1,000 h
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Appendix A
Specifications
Analog Output
Output Characteristics
Number of channels ............................... 2 voltage
Resolution .............................................. 16 bits, 1 in 65,536
Max update rate
1 channel......................................... 4 MS/s, system dependent
2 channel......................................... 2.5 MS/s, system dependent
FIFO buffer size..................................... 2,048 samples
Data transfers ......................................... DMA, interrupts,
programmed I/O
DMA modes........................................... Scatter gather (single transfer,
demand transfer)
Transfer Characteristics
Relative accuracy (INL)......................... 4 LSB typ, 8 LSB max
DNL ....................................................... 2 LSB typ, 8 LSB max
Table A-3. NI PCI-6110/6111 Analog Output DC Accuracy Information
Absolute Accuracy
% of Reading
Nominal
Range (V)
Offset
(mV)
Temp Drift
(%/°C)
Absolute Accuracy
at Full Scale ( mV)
24 Hrs
0.018
1 Year
10
0.022
5.933
0.0005
8.133
Note: Temp Drift applies only if ambient is greater than 10 °C of previous external calibration.
Voltage Output
Ranges.................................................... 10 V
Output coupling...................................... DC
Output impedance .................................. 50 Ω, 5%
Short circuit current ............................... 27 mA typ
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Appendix A
Specifications
Current drive........................................... 5 mA min
Output stability .......................................Any passive load
Protection................................................Short-circuit to ground
Power-on output voltage.........................0, 400 mV (before software
loads calibration values)
Dynamic Characteristics
Settling time and slew rate
Settling Time for Full-Scale Step
Slew Rate
300 ns to 0.01%
300 V/µs
Noise.......................................................1 mVrms, DC to 5 MHz
Spurious free dynamic range ..................75 dB, DC to 10 kHz
Glitch energy .......................................... 30 mV for 1 µs
Stability
Offset temperature coefficient................ 500 µV/°C
Gain temperature coefficient
Internal reference............................. 50 ppm/°C
External reference............................ 25 ppm/°C
Onboard calibration reference
Level................................................5.000 V ( 2.5 mV)
(actual value stored in EEPROM)
Temperature coefficient................... 2.0 ppm/°C max
Long-term stability.......................... 6 ppm/ 1,000 h
Digital I/O
Number of channels................................8 input/output
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Appendix A
Specifications
Digital logic levels
Level
Min
Max
0.8 V
5.0 V
–320 µA
10 µA
0.4 V
—
Input low voltage
0.0 V
2.0 V
—
Input high voltage
Input low current (Vin = 0 V)
Input high current (Vin = 5 V)
Output low voltage (IOL = 24 mA)
Output high voltage (IOH = 13 mA)
—
—
4.35 V
Power-on state........................................ Input (high-impedance)
Data transfers ......................................... Programmed I/O
Timing I/O
General-Purpose Up/Down Counter/Timers
Number of channels ............................... 2
Resolution .............................................. 24 bits
Compatibility ......................................... TTL/CMOS
Digital logic levels
Level
Input low voltage
Minimum
Maximum
0 V
2 V
0.8 V
5 V
Input high voltage
Input low current (Vin= 0 V)
Input high current (Vin = 5 V)
—
—
–320 µΑ
10 µΑ
Output low voltage (IOL = 24 mA)
Output high voltage (IOH = 13 mA)
—
4.35 V
0.4 V
—
Base clocks available ............................. 20 MHz, 100 kHz
Base clock accuracy............................... 0.01%
Max source frequency............................ 20 MHz
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Appendix A
Specifications
Min source pulse duration .....................10 ns, edge-detect mode
Min gate pulse duration .........................10 ns, edge-detect mode
Data transfers..........................................DMA, interrupts,
programmed I/O
DMA modes ...........................................Scatter-gather (single transfer,
demand transfer)
Frequency Scaler
Number of channels................................1
Resolution...............................................4 bits, 1 in 16
Compatibility..........................................TTL/CMOS
Digital logic levels
Level
Input low voltage
Minimum
Maximum
0 V
2 V
0.8 V
5 V
Input high voltage
Output low voltage (Iout= 5 mA)
Output low voltage (Iout = 3.5 mA)
—
4.35 V
0.4 V
—
Base clocks available..............................10 MHz, 100 kHz
Base clock accuracy................................ 0.01%
Data transfers..........................................DMA, interrupts,
programmed I/O
Triggers
Analog Trigger
Number of triggers..................................1
Purpose
Analog input....................................Start and stop trigger, gate, clock
Analog output..................................Start trigger, gate, clock
General-purpose counter/timers ......Source, gate
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Appendix A
Specifications
Source..................................................... All analog input channels,
external trigger (PFI0/TRIG1)
Level
Internal source, ACH<0..3>............ Full-scale
External source, PFI0/TRIG1 ......... 10 V, external
Slope....................................................... Positive or negative
(software-selectable)
Resolution .............................................. 8 bits, 1 in 256
Hysteresis............................................... Programmable
Bandwidth (–3 dB)
Internal source, ACH<0..3>............ 5 MHz
External source, PFI0/TRIG1 ......... 5 MHz
Digital Trigger
Purpose
Analog input ................................... Start and stop trigger, gate, clock
Analog output ................................. Start trigger, gate, clock
General-purpose counter/timers...... Source, gate
External sources ..................................... PFI<0..9>, RTSI<0..6>
Slope....................................................... Positive or negative
(software-selectable)
Compatibility ......................................... 5 V/TTL
Response ................................................ Rising or falling edge
Pulse width............................................. 10 ns min
External Input for Digital or Analog Trigger
(PFI0/TRIG1)
Output impedance .................................. 10 kΩ
Source impedance (recommended)........ 1 kΩ
Coupling................................................. DC or AC
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Appendix A
Specifications
Protection
Digital trigger ..................................–0.5 V to (Vcc + 0.5) V
Analog trigger
On/disabled............................... 35 V
Powered off .............................. 35 V
RTSI
Trigger Lines ..........................................7
Bus Interface
Type........................................................Master, slave
Power Requirement
+5 VDC ( 5%)
NI PCI-6110 ....................................2.5 A
NI PCI-6111 ....................................2.0 A
Power available at I/O connector............+4.65 to +5.25 VDC at 1 A
Physical
Dimensions
(not including connectors).....................31.2 by 10.6 cm
(12.3 by 4.2 in.)
I/O connector ..........................................68-pin male SCSI-II type
Maximum Working Voltage
Maximum working voltage refers to the signal voltage plus the
common-mode voltage.
Channel-to-earth .....................................42 V, Installation Category I
Channel-to-channel.................................42 V, Installation Category I
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Appendix A
Specifications
Environmental
Operating temperature............................ 0 to 45 °C
Storage temperature ............................... –20 to 70 °C
Humidity ................................................ 5 to 90% RH, noncondensing
Maximum altitude.................................. 2000 m
Pollution Degree (indoor use only)........ 2
Safety
This product is designed to meet the requirements of the following
standards of safety for electrical equipment for measurement, control,
and laboratory use:
•
•
•
IEC 61010-1, EN 61010-1
UL 3111-1, UL 61010B-1
CAN/CSA C22.2 No. 1010.1
Note For UL and other safety certifications, refer the the product label or to ni.com.
Electromagnetic Compatibility
Emissions ............................................... EN 55011 Class A at 10 m
FCC Part 15A above 1 GHz
Immunity................................................ EN 61326:1997 + A2:2001,
Table 1
EMC/EMI............................................... CE, C-Tick, and FCC Part 15
(Class A) Compliant
Note For EMC compliance, you must operate this device with shielded cabling.
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Appendix A
Specifications
CE Compliance
This product meets the essential requirements of applicable European
Directives, as amended for CE marking, as follows:
Low-Voltage Directive (safety)..............73/23/EEC
Electromagnetic Compatibility
Directive (EMC).....................................89/336/EEC
Note Refer to the Declaration of Conformity (DoC) for this product for any additional
regulatory compliance information. To obtain the DoC for this product, click Declarations
of Conformity Information at ni.com/hardref.nsf/. This Web site lists the DoCs by
product family. Select the appropriate product family, followed by your product, and a link
to the DoC appears in Adobe Acrobat format. Click the Acrobat icon to download or read
the DoC.
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B
Figure B-1 shows the pin assignments for the 68-pin NI PCI-6110/6111
connector. This connector is available when you use the SH6868EP cable
assemblies with the NI PCI-6110/6111.
Figure B-2 shows the pin assignments for the NI PCI-6110/6111 when used
with 50-pin accessories.
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Appendix B
Cable Connector Descriptions
34 68
ACH1+ 33 67
ACH0–
ACH0+
ACH0GND
ACH1–
ACH2+1
ACH2GND1
ACH3–1
NC
32 66
31 65
30 64
29 63
28 62
ACH1GND
ACH2–1
ACH3+1
ACH3GND1
NC
NC 27 61
NC 26 60
NC
NC
NC
NC 24 58
25 59
NC
NC
NC
23 57
22 56
21 55
NC
NC
DAC0OUT
DAC1OUT
AOGND
AOGND
DGND
DIO0
NC 20 54
19 53
18 52
17 51
16 50
15 49
DIO4
DGND
DIO1
DIO5
DIO6
DGND
DIO2
DGND
+5 V 14 48
DGND 13 47
DGND 12 46
DIO7
DIO3
SCANCLK
PFI0/TRIG1
11 45
10 44
EXTSTROBE*
DGND
PFI1/TRIG2
DGND
9
8
7
6
5
4
3
2
1
43
42
41
40
39
38
37
36
35
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
GPCTR1_OUT
DGND
+5 V
DGND
PFI5/UPDATE*
PFI6/WFTRIG
DGND
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
DGND
PFI9/GPCTR0_GATE
GPCTR0_OUT
FREQ_OUT
DGND
1 NC on NI PCI-6111
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Appendix B
Cable Connector Descriptions
DIO0
DGND 24
50
25
FREQ_OUT
GPCTR0_OUT
49
AOGND
23 48
PFI9/GPCTR0_GATE
PFI8/GPCTR0_SOURCE
PFI7/STARTSCAN
PFI6/WFTRIG
22
21
47
46
45
NC
DAC1OUT
DAC0OUT 20
19 44
18 43
17 42
16 41
15 40
NC
NC
NC
NC
NC
PFI5/UPDATE*
GPCTR1_OUT
PFI4/GPCTR1_GATE
PFI3/GPCTR1_SOURCE
PFI2/CONVERT*
NC 14 39
NC 13 38
NC 12 37
PFI1/TRIG2
PFI0/TRIG1
EXTSTROBE*
SCANCLK
+5 V
PFI0/TRIG1
11 36
10 35
ACH3–1
ACH3+1
ACH2–1
9
8
7
6
5
4
3
2
1
34
33
32
31
30
29
28
27
26
+5 V
DGND
DIO7
ACH2+1
ACH1–
DIO6
ACH1+
DIO5
ACH0–
DIO4
ACH0+
DIO3
ACH<0..3>GND
ACH<0..3>GND
DIO2
DIO1
1 NC on NI PCI-6111
Figure B-2. 50-Pin Connector Pin Assignment for the NI PCI-6110/6111
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C
Common Questions
This appendix contains a list of commonly asked questions and answers
relating to usage and special features of the NI PCI-6110/6111.
General Information
What is the NI PCI-6110/6111?
The NI PCI-6110/6111 is a switchless and jumperless enhanced
Multifunction DAQ device that uses the DAQ-STC for timing.
What is the DAQ-STC?
The DAQ-STC is the system timing control application-specific integrated
circuit (ASIC) designed by NI and is the backbone of the
NI PCI-6110/6111. The DAQ-STC contains seven 24-bit counters and
three 16-bit counters. The counters are divided into the following three
groups:
•
•
•
AI—two 24-bit, two 16-bit counters
AO—three 24-bit, one 16-bit counters
General-purpose counter/timer functions—two 24-bit counters
The groups can be configured independently with timing resolutions of
50 ns or 10 µs. With the DAQ-STC, you can interconnect a wide variety of
internal timing signals to other internal blocks. The interconnection scheme
is quite flexible and completely software configurable. New capabilities
such as buffered pulse generation, equivalent time sampling, and seamless
changes to the sampling rate are possible.
What does the maximum sampling rate mean to me?
Sampling rate is the fastest you can acquire data on the device and still
achieve accurate results. The NI PCI-6110/6111 has a sampling rate of
5 MS/s. This sampling rate is at 5 MS/s regardless if 1 or 4 channels are
acquiring data.
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Appendix C
Common Questions
What type of 5 V protection does the NI PCI-6110/6111 have?
The NI PCI-6110/6111 has 5 V lines equipped with a self-resetting
1 A fuse.
How do I use the NI PCI-6110/6111 with the NI-DAQ C API?
The NI-DAQ User Manual for PC Compatibles describes the general
programming flow and provides example code for using the NI-DAQ API.
For a list of functions that support the NI PCI-6110/6111, you can refer to
the NI-DAQ Function Reference Help (for NI-DAQ version 6.7 or later)
or the NI-DAQ Function Reference Manual (for NI-DAQ version 6.6 or
earlier).
Installing and Configuring
How do you set the base address for the NI PCI-6110/6111?
The base address of the NI PCI-6110/6111 is assigned automatically
through the PCI bus protocol. This assignment is completely transparent
to you.
What jumpers should I be aware of when configuring the
NI PCI-6110/6111?
The NI PCI-6110/6111 is jumperless and switchless.
Which NI document should I read first to get started using DAQ
software?
The DAQ Quick Start Guide and the NI-DAQ or application software
release notes documentation are good places to start. Refer to
ni.com/manualsto download these documents.
What is the best way to test the NI PCI-6110/6111 without
programming the device?
If you are using Windows, Measurement & Automation Explorer (MAX)
has a test panel option that is available by selecting Devices and Interfaces
in the left-hand panel and then selecting the NI PCI-6110/6111. The test
panels are excellent tools for performing simple functional tests of the
device, such as AI, DIO, and counter/timer tests. If you are using Mac OS,
the NI-DAQ Configuration Utility provides the same functionality
as MAX.
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Appendix C
Common Questions
Analog Input and Output
Why is there a minimum sampling rate on the NI PCI-6110/6111?
The NI PCI-6110/6111 makes use of a pipelined ADC in order to achieve
its high sampling rates. Sampling at rates below 20 kS/s can result in
improper digitalization, which would appear as noise in the acquired data.
I connected a DIFF input signal, but the readings are random and drift
rapidly. What’s wrong?
Check the ground reference connections. The signal may be referenced to
a level that is considered floating with reference to the device ground
reference. Even if you are in differential mode, the signal must still be
referenced to the same ground level as the device reference. There are
various methods of achieving this while maintaining a high common-mode
rejection ratio (CMRR). These methods are outlined in Chapter 4,
Connecting Signals.
I’m using the DACs to generate a waveform, but I discovered with a
digital oscilloscope that there are glitches on the output signal. Is this
normal?
When it switches from one voltage to another, any DAC produces glitches
due to released charges. The largest glitches occur when the most
significant bit (MSB) of the D/A code switches. You can build a low-pass
deglitching filter to remove some of these glitches, depending on the
frequency and nature of the output signal.
Can I synchronize a one-channel AI data acquisition with a
one-channel AO waveform generation on the NI PCI-6110/6111?
Yes. One way to accomplish this is to use the waveform generation timing
pulses to control the analog input data acquisition. To do this, follow steps 1
through 4 below, in addition to the usual steps for data acquisition and
waveform generation configuration.
1. Enable the PFI5 line for output, as follows:
•
If you are using NI-DAQ, call
Select_Signal(deviceNumber, ND_PFI_5,
ND_OUT_UPDATE, ND_HIGH_TO_LOW).
•
If you are using LabVIEW, invoke Route Signal.vi with signal
name set to PFI5 and signal source set to AO Update.
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Appendix C
Common Questions
2. Set up acquisition timing so that the timing signal for A/D conversion
comes from PFI5, as follows:
•
If you are using NI-DAQ, call
Select_Signal(deviceNumber, ND_IN_SCAN_START,
ND_PFI_5, ND_HIGH_TO_LOW).
•
If you are using LabVIEW, invoke AI Clock Config.vi with clock
source code set to PFI pin, high to low, and clock source string set
to 5.
3. Initiate AI data acquisition, which starts only when the AO waveform
generation starts.
4. Initiate AO waveform generation.
Timing and Digital I/O
What types of triggering can be hardware-implemented on the
NI PCI-6110/6111?
Hardware digital and analog triggering are both supported on the
NI PCI-6110/6111.
What added functionality does the DAQ-STC make possible in
contrast to the Am9513?
The DAQ-STC incorporates much more than just 10 Am9513-style
counters within one chip. In fact, the DAQ-STC has the complexity of more
than 24 chips. The DAQ-STC makes possible PFI lines, analog triggering,
selectable logic level, and frequency shift keying. The DAQ-STC also
makes buffered operations possible, such as direct up/down control, single
or pulse train generation, equivalent time sampling, buffered period, and
buffered semiperiod measurement.
What is the difference in timebases between the Am9513 counter/timer
and the DAQ-STC?
The DAQ-STC-based MIO devices have a 20 MHz timebase. The
Am9513-based MIO devices have a 1 MHz or 5 MHz timebase.
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Appendix C
Common Questions
Do the counter/timer applications that I wrote previously work with
the DAQ-STC?
If you are using NI-DAQ with LabVIEW, some applications that were built
using the CTR VIs still run. However, there are many differences between
the counters of the NI PCI-6110/6111 and those of other devices: the
counter numbers are different, timebase selections are different, and the
DAQ-STC counters are 24-bit counters (unlike the 16-bit counters on
devices without the DAQ-STC).
If you are using NI-DAQ or Measurement Studio, the counter/timer
applications that you wrote previously do not work with the DAQ-STC.
You must use the GPCTR functions because ICTR and CTR functions do
not work with the DAQ-STC. The GPCTR functions have the same
capabilities as the ICTR and CTR functions, plus more, but you must first
rewrite the application using GPCTR function calls.
I’m using one of the general-purpose counter/timers on the
NI PCI-6110/6111, but I do not see the counter/timer output on
the I/O connector. What am I doing wrong?
If you are using NI-DAQ or LabWindows/CVI, you must configure the
output line to output the signal to the I/O connector. Use the
Select_Signalcall in NI-DAQ to configure the output line. By default,
all timing I/O lines except EXTSTROBE* are high-impedance.
What are the PFIs and how do I configure these lines?
PFIs are Programmable Function Inputs. These lines serve as connections
to almost all internal timing signals.
If you are using NI-DAQ or LabWindows/CVI, use the Select_Signal
function to route internal signals to the I/O connector, route external signals
to internal timing sources, or tie internal timing signals together.
If you are using NI-DAQ with LabVIEW and you want to connect external
signal sources to the PFI lines, you can use AI Clock Config, AI Trigger
Config, AO Clock Config, AO Trigger and Gate Config, and Counter Set
Attribute advanced-level VIs to indicate which function the connected
signal serves. Use the Route Signal VI to enable the PFI lines to output
internal signals.
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Appendix C
Common Questions
Table C-1. Signal Name Equivalencies
Hardware
Signal Name
LabVIEW
Route Signal
NI-DAQ Select_Signal
AIGATE
—
ND_IN_EXTERNAL_GATE
ND_OUT_EXTERNAL_GATE
ND_IN_CONVERT
AOGATE
CONVERT*
SISOURCE
STARTSCAN
TRIG1
—
AI Convert
—
ND_IN_SCAN_CLOCK_TIMEBASE
ND_IN_SCAN_START
AI Scan Start
AI Start Trigger
AI Stop Trigger
—
ND_IN_START_TRIGGER
ND_IN_STOP_TRIGGER
TRIG2
UISOURCE
UPDATE*
WFTRIG
ND_OUT_UPDATE_CLOCK_TIMEBASE
ND_OUT_UPDATE
AO Update
AO Start Trigger
ND_OUT_START_TRIGGER
Caution If you enable a PFI line for output, do not connect any external signal source to
it. Connecting external signals to enabled PFI lines can damage the device, the computer,
and the connected equipment.
What are the power-on states of the PFI and DIO lines on the I/O
connector?
At system power-on and reset, both the PFI and DIO lines are set to
high-impedance by the hardware. This means that the device circuitry is not
actively driving the output either high or low. However, these lines may
have pull-up or pull-down resistors connected to them as shown in
Table 4-3, I/O Signal Summary for the NI PCI-6110/6111. These resistors
weakly pull the output to either a logic high or logic low state. For example,
DIO(0) is in the high impedance state after power-on, and Table 4-3 shows
that there is a 50 kΩ pull-up resistor. This pull-up resistor sets the DIO(0)
pin to a logic high when the output is in a high-impedance state.
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D
Technical Support and
Professional Services
Visit the following sections of the National Instruments Web site at
ni.comfor technical support and professional services:
•
Support—Online technical support resources include the following:
–
Self-Help Resources—For immediate answers and solutions,
visit our extensive library of technical support resources available
in English, Japanese, and Spanish at ni.com/support. These
resources are available for most products at no cost to registered
users and include software drivers and updates, a KnowledgeBase,
product manuals, step-by-step troubleshooting wizards,
conformity documentation, example code, tutorials and
application notes, instrument drivers, discussion forums,
a measurement glossary, and so on.
–
Assisted Support Options—Contact NI engineers and other
measurement and automation professionals by visiting
ni.com/support. Our online system helps you define your
question and connects you to the experts by phone, discussion
forum, or email.
•
•
Training—Visit ni.com/trainingfor self-paced tutorials, videos,
and interactive CDs. You also can register for instructor-led, hands-on
courses at locations around the world.
System Integration—If you have time constraints, limited in-house
technical resources, or other project challenges, NI Alliance Program
members can help. To learn more, call your local NI office or visit
ni.com/alliance.
•
Declaration of Conformity (DoC)—A DoC is our claim of
compliance with the Council of the European Communities using
the manufacturer’s declaration of conformity. This system affords
the user protection for electronic compatibility (EMC) and product
safety. You can obtain the DoC for your product by visiting
ni.com/hardref.nsf.
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Appendix D
Technical Support and Professional Services
If you searched ni.comand could not find the answers you need, contact
your local office or NI corporate headquarters. Phone numbers for our
worldwide offices are listed at the front of this manual. You also can visit
the Worldwide Offices section of ni.com/niglobalto access the branch
office Web sites, which provide up-to-date contact information, support
phone numbers, email addresses, and current events.
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Glossary
l
Symbol
Prefix
pico
Value
10–12
10–9
10– 6
10–3
103
p
n
nano
micro
milli
kilo
µ
m
k
M
G
T
mega
giga
106
109
tera
1012
Numbers/Symbols
°
degrees
greater than
>
≥
<
≤
/
greater than or equal to
less than
less than or equal to
per
%
percent
plus or minus
positive of, or plus
negative of, or minus
ohms
+
–
Ω
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Glossary
square root of
+5 V
+5 VDC source signal
A
A
amperes
A/D
analog-to-digital
AC
alternating current
ACH
ACH0GND
ADC
analog input channel signal
analog input channel ground signal
analog-to-digital converter—an electronic device, often an integrated
circuit, that converts an analog voltage to a digital number
ADE
application development environment
analog input
AI
AIGATE
AIGND
ANSI
AO
analog input gate signal
analog input ground signal
American National Standards Institute
analog output
AOGND
ASIC
analog output ground signal
Application-Specific Integrated Circuit—a proprietary semiconductor
component designed and manufactured to perform a set of specific
functions
B
bipolar
a signal range that includes both positive and negative values
(for example, –5 V to +5 V)
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Glossary
C
C
Celsius
CalDAC
CH
calibration DAC
channel—pin or wire lead to which you apply or from which you read
the analog or digital signal. Analog signals can be single-ended or
differential. For digital signals, you group channels to form ports. Ports
usually consist of either four or eight digital channels.
channel rate
cm
reciprocal of the interchannel delay
centimeter
CMOS
CMRR
complementary metal-oxide semiconductor
common-mode rejection ratio—a measure of an instrument’s ability to
reject interference from a common-mode signal, usually expressed in
decibels (dB)
common-mode noise
unwanted signals that appear in equal phase and amplitude on both the
inverting and noninverting input in a differential measurement system.
Ideally, but not completely in practice, the measurement device ignores
this noise, because the measurement device is designed to respond to
the difference between the inverting and noninverting inputs.
common-mode range
common-mode signal
the input range over which a circuit can handle a common-mode signal
the mathematical average voltage, relative to the ground of the
computer, of the signals from a differential input
common-mode voltage
any voltage present at both instrumentation amplifier inputs with
respect to amplifier ground
CONVERT*
counter/timer
CTR
convert signal
a circuit that counts external pulses or clock pulses (timing)
counter
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Glossary
D
D/A
digital-to-analog
DAC
digital-to-analog converter—an electronic device, often an integrated
circuit, that converts a digital number into a corresponding analog
voltage or current
DAC0OUT
DAC1OUT
DAQ
analog channel 0 voltage output signal
analog channel 1 voltage output signal
data acquisition—a system that uses the computer to collect, receive,
and generate electrical signals
DAQ-STC
dB
data acquisition system timing controller—an application-specific
integrated circuit (ASIC) for the system timing requirements of a
general A/D and D/A system
decibel—the unit for expressing a logarithmic measure of the ratio of
two signal levels: dB = 20log10 V1/V2, for signals in volts
DC
direct current
DGND
DI
digital ground signal
digital input
DIFF
DIO
differential mode
digital input/output
DIP
dual inline package
dithering
DMA
the addition of Gaussian noise to an analog input signal
direct memory access—a method by which data can be transferred
to/from computer memory from/to a device or memory on the bus while
the processor does something else. DMA is the fastest method of
transferring data to/from computer memory.
DNL
DO
differential nonlinearity—a measure in least significant bit of the
worst-case deviation of code widths from their ideal value of 1 LSB
digital output
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Glossary
DOC
DoC
the Canadian Department of Communications
Declaration of Conformity
E
edge detection
a technique that locates an edge of an analog signal, such as the edge of
a square wave
EEPROM
electrically erasable programmable read-only memory—ROM that can
be erased with an electrical signal and reprogrammed
EMC
electromechanical compliance
ENOB
effective number of bits—a measure of the actual performance of an
A/D converter after its various noise sources and nonlinearities are
included. The ENOB is computed as the signal-to-noise ratio of the
A/D converter (in dB) minus 1.76, divided by 6.02. Also called
effective bits.
ESD
electrostatic discharge—a high-voltage, low-current discharge of static
electricity that can damage sensitive electronic components.
Electrostatic discharge voltage can easily range from 1,000 to 10,000 V.
EXTSTROBE
external strobe signal
F
F
farads
FCC
Federal Communications Commission
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Glossary
FIFO
first-in first-out memory buffer—FIFOs are often used on DAQ devices
to temporarily store incoming or outgoing data until that data can be
read or written. For example, an analog input FIFO stores the results of
A/D conversions until the data can be read into system memory.
Programming the DMA controller and servicing interrupts can take
several milliseconds in some cases. During this time, data accumulates
in the FIFO for future retrieval. With a larger FIFO, longer latencies can
be tolerated. In the case of analog output, a FIFO permits faster update
rates, because the waveform data can be stored in the FIFO ahead of
time. This again reduces the effect of latencies associated with getting
the data from system memory to the DAQ device.
floating signal sources
signal sources with voltage signals that are not connected to an absolute
reference or system ground. Also called nonreferenced signal sources.
Some common example of floating signal sources are batteries,
transformers, or thermocouples.
FREQ_OUT
ft
frequency output signal
feet
G
gain
the factor by which a signal is amplified, sometimes expressed in
decibels
GATE
gate signal
GPCTR
general-purpose counter signal
GPCTR0_GATE
GPCTR0_OUT
GPCTR0_SOURCE
GPCTR0_UP_DOWN
GPCTR1_GATE
GPCTR1_OUT
GPCTR1_SOURCE
general-purpose counter 0 gate signal
general-purpose counter 0 output signal
general-purpose counter 0 clock source signal
general-purpose counter 0 up down signal
general-purpose counter 1 gate signal
general-purpose counter 1 output signal
general-purpose counter 1 clock source signal
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Glossary
GPCTR1_UP_DOWN
ground
general-purpose counter 1 up down signal
an electrically neutral wire that has the same potential as the
surrounding earth; a common reference point for an electrical system
H
h
hour
hex
Hz
hexadecimal
hertz
I
ICTR
8253 Programmable Interval Timer—applies to legacy DAQ products,
such as the 1200 series
INL
integral nonlinearity—for an ADC, deviation of codes of the actual
transfer function from a straight line
interchannel delay
amount of time that passes between sampling consecutive channels.
The interchannel delay must be short enough to allow sampling of all
the channels in the channel list, within the scan interval. The greater the
interchannel delay, the more time the PGIA is allowed to settle before
the next channel is sampled. The interchannel delay is regulated by
CONVERT*.
I/O
input/output—the transfer of data to/from a computer system involving
communications channels, operator interface devices, and/or data
acquisition and control interfaces
IOH
current, output high
current, output low
current out
IOL
IOUT
IRQ
interrupt request
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Glossary
K
kHz
kilohertz
L
LabVIEW
a graphical programming language
light emitting diode
LED
library
a file containing compiled object modules, each comprised of one of
more functions, that can be linked to other object modules that make use
of these functions. NIDAQ32.LIB is a library that contains NI-DAQ
functions. The NI-DAQ function set is broken down into object
modules so that only the object modules that are relevant to your
application are linked in, while those object modules that are not
relevant are not linked.
linearity
LSB
the adherence of device response to the equation R = KS, where
R = response, S = stimulus, and K = a constant
least significant bit
M
m
meter
MB
megabytes of memory
Measurement & Automation a controlled centralized configuration environment that allows you to
Explorer (MAX)
configure all of your National Instruments DAQ, GPIB, IMAQ, IVI,
Motion, VISA, and VXI devices
MHz
MIO
MITE
MSB
megahertz
multifunction I/O
MXI Interface to Everything
most significant bit
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Glossary
mux
mV
multiplexer—a switching device with multiple inputs that sequentially
connects each of its inputs to its output, typically at high speeds, in
order to measure several signals with a single analog input channel
millivolts
N
NC
not connected
NI
National Instruments
NI-DAQ
noise
National Instruments driver software for DAQ hardware
an undesirable electrical signal—Noise comes from external sources
such as the AC power line, motors, generators, transformers,
fluorescent lights, CRT displays, computers, electrical storms, welders,
radio transmitters, and internal sources such as semiconductors,
resistors, and capacitors. Noise corrupts signals you are trying to send
or receive.
O
OUT
output pin—a counter output pin where the counter can generate
various TTL pulse waveforms
P
PCI
Peripheral Component Interconnect—a high-performance expansion
bus architecture originally developed by Intel to replace ISA and EISA.
It is achieving widespread acceptance as a standard for PCs and
work-stations; it offers a theoretical maximum transfer rate of
132 MB/s.
pd
pull-down
PFI
Programmable Function Input
PFI0/trigger 1
PFI0/TRIG1
PFI1/TRIG2
PFI1/trigger 2
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Glossary
PFI2/CONVERT*
PFI3/GPCTR1_SOURCE
PFI4/GPCTR1_GATE
PFI5/UPDATE*
PFI2/convert
PFI3/general-purpose counter 1 source
PFI4/general-purpose counter 1 gate
PFI5/update
PFI6/WFTRIG
PFI6/waveform trigger
PFI7/STARTSCAN
PFI8/GPCTR0_SOURCE
PFI9/GPCTR0_GATE
PGIA
PFI7/start of scan
PFI8/general-purpose counter 0 source
PFI9/general-purpose counter 0 gate
Programmable Gain Instrumentation Amplifier
Plug and Play devices
devices that do not require DIP switches or jumpers to configure
resources on the devices—also called switchless devices
port
(1) a communications connection on a computer or a remote controller
(2) a digital port, consisting of four or eight lines of digital input and/or
output
posttriggering
potentiometer
the technique used on a DAQ device to acquire a programmed number
of samples after trigger conditions are met
an electrical device the resistance of which can be manually adjusted;
used for manual adjustment of electrical circuits and as a transducer for
linear or rotary position
ppm
parts per million
precision
the measure of the stability of an instrument and its capability to give
the same measurement over and over again for the same input signal
pretriggering
the technique used on a DAQ device to keep a continuous buffer filled
with data, so that when the trigger conditions are met, the sample
includes the data leading up to the trigger condition
pseudodifferential input
pu
pseudodifferential input channels are all referred to a common ground,
but this ground is not directly connected to the computer ground
pull up
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Glossary
R
RAM
random access memory
range
the maximum and minimum parameters between which a sensor,
instrument, or device operates with a specified set of characteristics
referenced signal sources
resolution
signal sources with voltage signals that are referenced to a system
ground, such as the earth or a building ground. Also called grounded
signal sources.
the smallest signal increment that can be detected by a measurement
system. Resolution can be expressed in bits, in proportions, or in
percent of full scale. For example, a system has 12-bit resolution,
one part in 4,096 resolution, and 0.0244% of full scale.
RH
relative humidity
root mean square
rms
RTD
resistive temperature detector—a metallic probe that measures
temperature based upon its coefficient of resistivity
RTSI bus
real-time system integration bus—the National Instruments timing bus
that connects DAQ devices directly, by means of connectors on top of
the devices, for precise timing synchronization between multiple
devices
RTSI_OSC
RTSI Oscillator—RTSI bus master clock
S
s
seconds
samples
S
S/s
samples per second—used to express the rate at which a DAQ device
samples an analog signal
SC
scan counter
scan interval
controls how often a scan is initialized; the scan interval is regulated by
STARTSCAN
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Glossary
scan rate
SCANCLK
SCSI
reciprocal of the scan interval
scan clock signal
small computer system interface—a high-speed, peripheral-connect
interface primarily used for hard disks, CD-ROM drives, tape drives,
and other mass-storage devices to PCs
settling time
SFDR
the amount of time required for a voltage to reach its final value within
specified limits
spurious-free dynamic range—the dynamic range from full-scale
deflection to the highest spurious signal in the frequency domain
SI2
sample interval counter
signal conditioning
SISOURCE
SOURCE
the manipulation of signals to prepare them for digitizing
SI counter clock signal
source signal
STARTSCAN
system noise
start scan signal
a measure of the amount of noise seen by an analog circuit or an ADC
when the analog inputs are grounded
T
TC
terminal count—the ending value of a counter
delay time
td
tgh
gate hold time
tgsu
tgw
tout
THD
gate setup time
gate pulse width
output delay time
total harmonic distortion—the ratio of the total rms signal due to
harmonic distortion to the overall rms signal, in decibel or a percentage
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Glossary
thermocouple
a temperature sensor created by joining two dissimilar metals; the
junction produces a small voltage as a function of the temperature
TIO
toff
timing I/O
an offset (delayed) pulse; the offset is t nanoseconds from the falling
edge of the CONVERT* signal
tout
output delay time
tP
pulse period
TRIG
trigger
tsc
trigger signal
any event that causes or starts some form of data capture
source clock period
tsp
source pulse width
TTL
tw
transistor-transistor logic
pulse width
U
UI
update interval counter
UISOURCE
unipolar
UPDATE
update interval counter clock signal
a signal range that is always positive (for example, 0 to +10 V)
update signal
V
V
volts
VDC
VI
volts direct current
virtual instrument—(1) a combination of hardware and/or software
elements, typically used with a PC, that has the functionality of a classic
stand-alone instrument (2) a LabVIEW software module (VI), which
consists of a front panel user interface and a block diagram program
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Glossary
VIH
VIL
Vin
volts, input high
volts, input low
volts in
Vm
measured voltage
volts, output high
volts, output low
reference voltage
volts, root mean square
ground-referenced signal source
VOH
VOL
Vref
Vrms
Vs
W
WFTRIG
waveform generation trigger signal
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Index
differential connections
(figure), 4-11
sources (figure), 4-12
signal summary (table), 4-6
specifications, A-1
Symbols
+5 V signal
description (table), 4-4
power connections, 4-16
self-resetting fuse, 4-16, C-2
working voltage range, 4-13
ACH<0..3>GND signal
description (table), 4-3
differential connections
(figure), 4-11
Numerics
50-pin connector pin assignment
(figure), 4-3, B-3
68-pin connector pin assignment
(figure), 4-2, B-2
A
sources (figure), 4-12
power connections (caution), 4-16
signal summary (table), 4-6
working voltage range, 4-13
AIGATE signal
above-high-level analog triggering mode, 3-6
AC input coupling, 3-4
ACH<0..3>– signal
analog input connections, 4-8
description (table), 4-4
gating DAQ sequences, 4-23
overview, 4-25
differential connections
amplifier characteristic specifications, A-3
analog input
(figure), 4-11
input coupling, 3-4
input mode, 3-2
sources (figure), 4-12
input polarity and input range, 3-3
questions about, C-3
signal summary (table), 4-6
specifications, A-1
signal connections, 4-8
specifications
working voltage range, 4-13
ACH<0..3>+ signal
amplifier characteristics, A-3
dynamic characteristics, A-3
input characteristics, A-1
stability, A-4
analog input connections, 4-8
common-mode signal rejection, 4-12
description (table), 4-3
transfer characteristics, A-2
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Index
analog output
NI PCI-6111, 3-2
analog trigger, 3-5
number of channels, 3-4
output range, 3-4
bus
questions about, C-3
signal connections, 4-14
specifications
PCI
overview, 1-1
dynamic characteristics, A-6
stability, A-6
Revision 2.0, 2-2
RTSI
device and RTSI clocks, 3-10
overview, 1-1
transfer characteristics, A-5
voltage output, A-5
analog trigger
(figure), 3-6
avoiding false triggering (note), 3-4
below-low-level analog triggering mode
(figure), 3-6
cables
See also I/O connectors
block diagrams
custom cabling, 1-4
NI PCI-6110, 3-5
field wiring considerations, 4-37
optional equipment, 1-4
calibration
high-hysteresis analog triggering mode
(figure), 3-7
inside-region analog triggering mode
(figure), 3-7
(figure), 3-7
external calibration, 5-2
loading calibration constants, 5-1
self-calibration, 5-2
clocks, device and RTSI, 3-10
answers
common-mode signal rejection, 4-12
configuring
specifications, A-8
AOGND signal
analog output signal connections, 4-14
description (table), 4-4
signal summary (table), 4-6
avoiding false triggering (note), 3-4
NI PCI-6110/6111, 2-2
questions about, C-2
contacting National Instruments, D-2
conventions used in the manual, ix
CONVERT* signal
B
below-low-level analog triggering mode, 3-6
bipolar input, 3-3
block diagrams
See also PFI2/CONVERT* signal
input timing (figure), 4-24
output timing (figure), 4-25
NI PCI-6110, 3-1
analog trigger, 3-5
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Index
typical posttriggered acquisition
(figure), 4-18
controller
(figure), 4-19
timing connections
counter/timer applications, C-5
custom cabling, 1-4
customer
DC input coupling, 3-4
Declaration of Conformity, D-1
device clocks, 3-10
education, D-1
professional services, D-1
technical support, D-1
device configuration, 2-2
DGND signal
description (signal), 4-4
digital I/O connections, 4-15
power connections, 4-16
signal summary (table), 4-6
timing connections, 4-15
diagnostic resources, D-1
differential measurements
common-mode signal rejection, 4-12
connection considerations, 4-10
ground-referenced signal sources, 4-11
nonreferenced signal sources, 4-12
recommended configuration (table), 4-10
D
DAC0OUT signal
analog output signal connections, 4-14
description (table), 4-4
signal summary (table), 4-6
DAC1OUT signal
analog output signal connections, 4-14
description (table), 4-4
signal summary (table), 4-6
DAQ timing connections
AIGATE signal, 4-25
See also DGND signal; DIO<0..7> signal
overview, 3-8
questions about, C-4
signal connections, 4-15
specifications, A-6
CONVERT* signal, 4-24
EXTSTROBE* signal, 4-27
SCANCLK signal, 4-26
SISOURCE signal, 4-26
TRIG1 signal, 4-19
digital trigger
overview, 3-8
TRIG2 signal, 4-20
specifications, A-9
typical posttriggered acquisition
(figure), 4-18
DIO<0..7> signal
description (table), 4-4
typical pretriggered acquisition
(figure), 4-19
DAQ-STC system timing controller
overview, 1-1
digital I/O connections, 4-15
signal summary (table), 4-6
documentation
conventions used in the manual, ix
National Instruments documentation, x
online library, D-1
questions about, C-4
related documentation, xi
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Index
drivers
instrument, D-1
general-purpose timing signal connections
FREQ_OUT signal, 4-37
software, D-1
analog input, A-3
GPCTR0_GATE signal, 4-31
GPCTR0_OUT signal, 4-32
GPCTR0_SOURCE signal, 4-31
GPCTR0_UP_DOWN signal, 4-33
GPCTR1_GATE signal, 4-34
GPCTR1_OUT signal, 4-35
GPCTR1_SOURCE signal, 4-33
GPCTR1_UP_DOWN signal, 4-35
overview, 4-30
analog output, A-6
E
EEPROM storage of calibration constants, 5-1
electromagnetic compatibility
specifications, A-11
environmental noise, avoiding, 4-37
environmental specifications, A-11
equipment, optional, 1-4
example code, D-1
external calibration, 5-2
EXTSTROBE* signal
GPCTR0_GATE signal
See also PFI9/GPCTR0_GATE signal
general-purpose counter timing summary
(figure), 4-36
general-purpose timing connections, 4-31
timing diagram, 4-32
description (table), 4-4
signal summary (table), 4-6
timing connections, 4-27
GPCTR0_OUT signal
description (table), 4-6
general-purpose counter timing summary
(figure), 4-36
general-purpose timing connections, 4-32
signal summary (table), 4-7
F
field wiring considerations, 4-37
FIFO, analog
See also PFI8/GPCTR0_SOURCE
general-purpose counter timing summary
(figure), 4-36
general-purpose timing connections, 4-31
relation to GPCTR0_OUT signal, 4-32
timing diagram, 4-31
DAQ sequences, 4-23
specifications, A-2
floating signal sources
description, 4-9
differential connections, 4-10
recommended configuration (table), 4-10
FREQ_OUT signal
GPCTR0_UP_DOWN signal
digital I/O lines, 3-8
general-purpose timing connections, 4-33
GPCTR1_GATE signal
description (table), 4-6
general-purpose timing connections, 4-37
signal summary (table), 4-7
answers
general-purpose counter timing summary
(figure), 4-36
general-purpose signal connections, 4-34
timing diagram, 4-34
fuse, self-resetting, 4-16, C-2
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GPCTR1_OUT signal
timing signal routing
device and RTSI clocks, 3-10
overview, 3-8
description (table), 4-5
general-purpose counter timing summary
(figure), 4-36
(figure), 3-9
general-purpose timing connections, 4-35
signal summary (table), 4-7
GPCTR1_SOURCE signal
general-purpose counter timing summary
(figure), 4-36
professional services, D-1
technical support, D-1
high-hysteresis analog triggering mode, 3-7
general-purpose timing connections, 4-33
relation to GPCTR1_OUT signal, 4-35
timing diagram, 4-33
GPCTR1_UP_DOWN signal
digital I/O lines, 3-8
general-purpose timing connections, 4-35
ground-referenced signal sources
description, 4-9
I
I/O connectors
cable options for the NI PCI-6110/6111,
1-4
connector details (table), 4-1
exceeding maximum ratings
(caution), 4-1
differential connections, 4-11
H
pin assignments
50-pin connector (figure), 4-3, B-3
68-pin connector (figure), 4-2, B-2
signal descriptions (table), 4-3
signal summary (table), 4-6
input coupling, 3-4
hardware installation
procedure, 2-1
unpacking the NI PCI-6110/6111, 1-5
hardware overview
analog input
input polarity, 3-3
input coupling, 3-4
input mode, 3-2
input range, 3-3
input polarity and input range, 3-3
overview, 3-2
selection considerations, 3-4
analog output, 3-4
analog trigger
(table), 3-3
considerations for selecting input
ranges, 3-4
inside-region analog triggering mode, 3-7
installation
block diagram, 3-5
overview, 3-4
block diagrams
NI PCI-6110, 3-1
NI PCI-6111, 3-2
digital I/O, 3-8
hardware, 2-1
questions about, C-2
software, 2-1
unpacking the NI PCI-6110/6111, 1-5
instrument drivers, D-1
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Index
questions about
analog input and output, C-3
K
KnowledgeBase, D-1
general information, C-1
installing and configuring, C-2
timing and digital I/O, C-4
requirements for getting started, 1-2
software programming choices, 1-2
unpacking, 1-5
L
loading calibration constants, 5-1
lowValue, 3-5, 3-6, 3-7
NI-DAQ
overview, 1-2
M
questions about, C-2
noise
MAX
avoiding, 4-37
rejecting common-mode, 4-12
configuration instructions, 2-2
questions about, C-2
Measurement & Automation Explorer. See
MAX
O
online technical support, D-1
optional equipment, 1-4
output characteristics specifications, A-5
output, analog. See analog output
See also voltage output specifications
N
National Instruments
customer education, D-1
Declaration of Conformity, D-1
professional services, D-1
system integration services, D-1
technical support, D-1
worldwide offices, D-2
National Instruments ADE software
LabVIEW, 1-3
PCI bus
overview, 1-1
2.0, 2-2
PFI0/TRIG1 pin, analog triggering, 3-4
PFI0/TRIG1 signal
Measurement Studio, 1-4
VI Logger, 1-4
NI PCI-6110/6111
See also TRIG1 signal
analog triggering, 3-4
description (table), 4-4
signal summary (table), 4-6
PFI1/TRIG2 signal
See also hardware overview
block diagram
NI PCI-6110, 3-1
NI PCI-6111, 3-2
custom cabling, 1-4
See also TRIG2 signal
description (table), 4-4
signal summary (table), 4-6
optional equipment, 1-4
overview, 1-1
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PFI2/CONVERT* signal
See also CONVERT* signal
description (table), 4-5
signal summary (table), 4-6
PFI3/GPCTR1_SOURCE signal
See also GPCTR1_SOURCE signal
description (table), 4-5
signal summary (table), 4-7
PFI4/GPCTR1_GATE signal
See also GPCTR1_GATE signal
description (table), 4-5
signal summary (table), 4-7
PFI5/UPDATE* signal
See also UPDATE* signal
description (table), 4-5
signal summary (table), 4-7
PFI6/WFTRIG signal
See also WFTRIG signal
description (table), 4-5
signal summary (table), 4-7
PFI7/STARTSCAN signal
See also STARTSCAN signal
description (table), 4-5
signal summary (table), 4-7
PFI8/GPCTR0_SOURCE signal
See also GPCTR0_SOURCE signal
description (table), 4-5
signal summary (table), 4-7
PFI9/GPCTR0_GATE signal
See also GPCTR0_GATE signal
description (table), 4-5
signal summary (table), 4-7
PFIs (programmable function inputs)
connecting to external signal source
(caution), C-6
PGIA
analog input connections
common-mode signal rejection
sources, 4-12
overview, 4-8
definition, 3-2
working voltage range, 4-13
phone technical support, D-2
physical specifications, A-10
pin assignments
50-pin connector (figure), 4-3, B-3
68-pin connector (figure), 4-2, B-2
polarity selection, analog input, 3-3
power connections
+5 V power pins, 4-16
self-resetting fuse, 4-16
professional services, D-1
programmable function inputs (PFIs). See
PFIs (programmable function inputs)
programmable gain instrumentation amplifier.
See PGIA
questions and answers
analog input and output, C-3
general information, C-1
installing and configuring, C-2
timing and digital I/O, C-4
overview, 4-16
questions about, C-5
signal routing, 3-10
timing input connections, 4-17
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digital I/O, 4-15
field wiring considerations, 4-37
I/O connector
R
Real-Time System Integration. See RTSI
related documentation, xi
requirements for getting started, 1-2
RTSI
(caution), 4-1
bus
pin assignments
overview, 1-1
50-pin connector (figure), 4-3
68-pin connector (figure), 4-2
signal descriptions (table), 4-3
signal summary (table), 4-6
power connections, 4-16
timing connections
signal connection (figure), 3-11
timing signal routing, 3-8
device and RTSI clocks, 3-10
trigger lines, 3-11
DAQ timing connections
AIGATE signal, 4-25
CONVERT* signal, 4-24
EXTSTROBE* signal, 4-27
overview, 4-18
S
safety
overview, 1-5
SCANCLK signal, 4-26
safety information, 1-5
safety specifications, A-11
SCANCLK signal
description (table), 4-4
signal summary (table), 4-6
timing connections, 4-26
timing diagram, 4-27
self-calibration, 5-2
general-purpose timing signal
GPCTR0_SOURCE signal, 4-31
GPCTR1_GATE signal, 4-34
GPCTR1_SOURCE signal, 4-33
GPCTR1_UP_DOWN
signal, 4-35
self-resetting fuse, 4-16, C-2
signal connections
analog input, 4-8
analog output, 4-14
differential measurements
common-mode signal rejection, 4-12
floating signal sources, 4-12
ground-referenced signal
sources, 4-11
overview, 4-30
overview, 4-10
(table), 4-10
programmable function input
connections, 4-17
signal overview, 4-16
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waveform generation timing
connections
digital I/O, A-6
electromagnetic compatibility, A-11
environmental, A-11
physical, A-10
power requirements, A-10
RTSI, A-10
overview, 4-27
UISOURCE signal, 4-30
UPDATE* signal, 4-29
WFTRIG signal, 4-28
types of signal sources
floating, 4-9
safety, A-11
stability
ground-referenced, 4-9
SISOURCE signal
analog input, A-4
analog output, A-6
timing I/O
frequency scaler, A-8
counter/timers, A-7
triggers
timing connections, 4-26
timing diagram, 4-26
software drivers, D-1
software installation, 2-1
software programming choices
LabVIEW, 1-3
analog trigger, A-8
trigger (PFI0/TRIG1), A-9
National Instruments application
software, 1-3
NI-DAQ, 1-2
STARTSCAN signal
overview, 1-2
VI Logger, 1-4
software-programmable gain, 3-3
(table), 3-3
See also PFI7/STARTSCAN signal
FIFO considerations, 4-24
input timing (figure), 4-22
signal routing (figure), 3-9
typical posttriggered acquisition
(figure), 4-18
specifications
analog input
accuracy information (table), A-2
amplifier characteristics, A-3
dynamic characteristics, A-3
input characteristics, A-1
stability, A-4
typical pretriggered acquisition
(figure), 4-19
using the SISOURCE signal, 4-26
support, technical, D-1
system integration services, D-1
transfer characteristics, A-2
analog output
dynamic characteristics, A-6
output characteristics, A-5
stability, A-6
technical support, D-1
telephone technical support, D-2
timing connections
transfer characteristics, A-5
voltage output, A-5
bus interface, A-10
DAQ timing connections
AIGATE signal, 4-25
CONVERT* signal, 4-24
CE compliance, A-12
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Index
EXTSTROBE* signal, 4-27
overview, 4-18
SISOURCE signal, 4-26
TRIG1 signal, 4-19
TRIG2 signal, 4-20
(figure), 4-18
training, customer, D-1
transfer characteristics specifications
analog input, A-2
analog output, A-5
TRIG1 signal
See also PFI0/TRIG1 signal
input timing (figure), 4-20
output timing, 4-20
typical posttriggered acquisition
(figure), 4-18
(figure), 4-19
general-purpose timing signal
connections
typical pretriggered acquisition
(figure), 4-19
FREQ_OUT signal, 4-37
GPCTR0_GATE signal, 4-31
GPCTR0_OUT signal, 4-32
GPCTR0_SOURCE signal, 4-31
GPCTR0_UP_DOWN signal, 4-33
GPCTR1_UP_DOWN signal, 4-35
overview, 4-30
TRIG2 signal
See also PFI1/TRIG2 signal
input timing (figure), 4-21
output timing (figure), 4-21
timing connections, 4-20
programmable function input
connections, 4-17
UISOURCE signal
questions about, C-4
timing connections, 4-30
timing I/O connections (figure), 4-17
waveform generation timing connections
overview, 4-27
timing diagram, 4-30
unpacking the NI PCI-6110/6111, 1-5
UPDATE* signal
UISOURCE signal, 4-30
UPDATE* signal, 4-29
WFTRIG signal, 4-28
See also PFI5/UPDATE* signal
timing connections, 4-29
using with UISOURCE signal, 4-30
using with WFTRIG signal, 4-28
timing I/O
questions about, C-4
specifications, A-7
timing signal routing, 3-8
V
VCC signal summary (table), 4-6
VI Logger application software, 1-4
voltage output specifications, A-5
voltage, working range, 4-13
device and RTSI clocks, 3-10
RTSI triggers, 3-11
STARTSCAN signal routing (figure), 3-9
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WFTRIG signal
See also PFI6/WFTRIG signal
timing connections, 4-28
using with UPDATE* signal, 4-30
wiring considerations, 4-37
W
waveform generation timing connections
overview, 4-27
questions about, C-3
UISOURCE signal, 4-30
UPDATE* signal, 4-29
WFTRIG signal, 4-28
Web
working voltage range, 4-13
worldwide technical support, D-2
professional services, D-1
technical support, D-1
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