NXP Semiconductors Stereo Amplifier TFA9812 User Manual

supply current

soft mute mode, with load,

ﬁlter and snubbers

connected

sleep mode

160

270

µA

I_DDA(3V3)

analog supply

current (3.3 V)

operating mode

I²S slave mode

I²S master mode

sleep mode

V_DDA= V_DDP= 12 V

V_DDA= V_DDP= 1 V

operating mode

I²S slave mode

I²S master mode

120

µA

I_DDD(3V3)

digital supply

current (3.3 V)

µA

sleep mode;

DATA = WS = BCK =

MCLK = 0 V

P_o(RMS)

RMS output power Continuous time output power per channel; THD = 10 %;

R_L= 8 Ω

V_DDA= V_DDP= 12 V

V_DDA= V_DDP= 13.5 V

V_DDA= V_DDP= 15 V

8.3

Short time (≤ 10 s) output power per channel; THD = 10 %;

R_L= 8 Ω

V_DDA= V_DDP= 17 V

η_po

output power

efﬁciency

R_L= 8 Ω; P_o(RMS)= 8.3 W

[1] I_Pis the current through the analog supply voltage (V_DDA) pin added to the current through the power supply

voltage (V_DDP) pin.

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5. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

TFA9812HN

HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads;

SOT619-8

48 terminals; body 7 × 7 × 0.85 mm

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6. Block diagram

TEST1 TEST2

AVOL

DDD(3V3)

DDA(3V3)

DDA

15 BOOT1P

18, 19

DDP

PHASED

LOCKED

LOOP

ADDRESS

HEX 01

DRIVER

HIGH

ADC

TFA9812

16, 17 OUT1P

CONTROL

LOGIC

XTALIN

DRIVER

LOW

CLOCK

PROTECTION

10, 11

SSP2

OSCILLATOR

XTALOUT

CSEL

PWM

CONTROLLER

STAB1

UFP

OFP

25 BOOT1N

DDP

MCLK 47

IBP

THERMAL

FOLDBACK

DRIVER

HIGH

23, 24 OUT1N

CONTROL

LOGIC

DRIVER

LOW

SSP1

26, 27

BCK 46

WS 45

VOLUME

CONTROL

AND SOFT

MUTE

INTER-

POLATION

FILTER AND

DE-EMPHASIS

SERIAL

AUDIO

INTERFACE

10-BAND

PARAMETRIC

EQUALIZER

28 STAB1

POWER

LIMITER

GAIN

22 BOOT2P

DATA 44

DDP

DRIVER

HIGH

20, 21 OUT2P

CONTROL

LOGIC

DRIVER

LOW

SSP2

PWM

CONTROLLER

STAB2

POWERUP 31

ENABLE 33

12 BOOT2N

DDP

GAIN 34

PROTECTION

DRIVER

HIGH

CSEL 35

OVP

UVP

OCP

OTP

ODP

OUT2N

ADSEL2/PLIM2 36

ADSEL1/PLIM1 37

SCL/SFOR 38

SDA/MS 39

13, 14

CONTROL

INTERFACE

CONTROL

LOGIC

REFERENCES

DRIVER

LOW

SSP2

STAB2

DIAG

010aaa217

CDELAY STABD REFD STABA REFA

EXPOSED DIE PADDLE

SS2

SS1

Fig 1. TFA9812 block diagram

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BTL stereo Class-D audio ampliﬁer with I²S input

Figure 1 shows the block diagram of the TFA9812. For a detailed description of the audio

signal path see Section 8.1.

7. Pinning information

7.1 Pinning

terminal 1

index area

XTALIN

ADSEL2/PLIM2

CSEL

XTALOUT

GAIN

DDA(3V3)

STABA

ENABLE

AVOL

REFA

DDA

POWERUP

CDELAY

DIAG

TFA9812HN

TEST1

SS1

STAB2

STAB1

SSP2

SSP1

BOOT2N

BOOT1N

010aaa218

Transparent top view

Fig 2. Pin conﬁguration, transparent top view

Table 3.

Pinning description TFA9812

Symbol

XTALIN

XTALOUT

V_DDA(3V3)

STABA

REFA

Type Description

Crystal oscillator input

Crystal oscillator output

Analog supply voltage (3.3 V)

1.8 V analog stabilizer output

Analog reference voltage

V_DDA

Analog supply voltage (8 V to 20 V)

TEST1

V_SS1

Test signal input 1. For test purposes only (connect to V_SS

PCB ground reference

)

STAB2

V_SSP2

Decoupling of internal 11 V regulator for channel 2 drivers

Negative power supply voltage for channel 1 and channel 2

Bootstrap high-side driver negative PWM output channel 2

Negative PWM output channel 2

V_SSP2

BOOT2N

OUT2N

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Table 3.

Pinning description TFA9812 …continued

Symbol

OUT2N

BOOT1P

OUT1P

V_DDP

Type Description

Negative PWM output channel 2

Bootstrap high-side driver positive PWM output channel 1

Positive PWM output channel 1

Positive power supply voltage (8 V to 20 V)

Positive PWM output channel 2

V_DDP

OUT2P

BOOT2P

OUT1N

BOOT1N

V_SSP1

Positive PWM output channel 2

Bootstrap high-side driver positive PWM output channel 2

Negative PWM output channel 1

Bootstrap high-side driver negative PWM output channel 1

Negative power supply voltage for channel 1 and channel 2

Decoupling of internal 11 V regulator for channel 1 drivers

Fault mode indication output (open-drain pin)

Timing reference

V_SSP1

STAB1

DIAG

CDELAY

POWERUP

Power-up pin to switch between Sleep and other operational

modes

AVOL

Analog volume control (Legacy mode)

ENABLE

Enable input to switch between 3-state and other

operational modes

GAIN

Gain selection input to select between 0 dB and +24 dB

gain (Legacy mode)

CSEL

Control selection input to select between Legacy mode

(no I²C bus control) and I²C bus control

Address selection in I²C mode input 2, power limiter

selection input 2 in Legacy mode

Address selection in I²C mode input 1, power limiter

selection input 1 in Legacy mode

I²C bus clock input in I²C mode, I²S serial data format

selection input in Legacy mode

ADSEL2/PLIM2

ADSEL1/PLIM1

SCL/SFOR

SDA/MS

I/O

I²C bus data input and output in I²C mode, master/slave

selection input in Legacy mode

V_DDD(3V3)

STABD

REFD

TEST2

DATA

Digital supply voltage (3.3 V)

1.8 V digital stabilizer output

Digital reference voltage

Test signal input 2; for test purposes only (connect to V_SS

I²S bus data input

I²S bus word select input (I²S slave mode) or output (I²S

master mode)

)

I/O

BCK

I/O

I²S bus bit clock input (I²S slave mode) or output (I²S

master mode)

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Table 3.

Pinning description TFA9812 …continued

Symbol

Type Description

MCLK

I/O

Master clock input (I²S slave mode) or output (I²S master

mode)

V_SS2

PCB ground reference

Exposed

die-paddle

8. Functional description

8.1 General

The TFA9812 is a high-efﬁciency stereo BTL Class-D ampliﬁer with a digital I²S audio

input. It supports all commonly used I²S formats.

Figure 1 shows the functional block diagram, which includes the key function blocks of the

TFA9812. In the digital domain the audio signal is processed and converted to a pulse

width modulated signal using BD modulation. A BTL conﬁgured power comparator carries

out power ampliﬁcation.

The audio signal processing path is as follows:

1. The Digital Audio Input (DAI) block translates the I²S (-like) input signal into a

standard internal stereo audio stream.

2. The 10-band parametric equalizer can optionally equalize the stereo audio stream.

Both channels have separate equalization streams. It can be used for speaker transfer

curve compensation to optimize the audio performance of applied speakers.

3. Volume control in the TFA9812 is done by attenuation. The attenuation depends on

the volume control settings and the thermal foldback value. Soft mute is also arranged

at this part. In Legacy mode the volume control is done by an on-board

Analog-to-Digital Converter (ADC) which measures the analog voltage on pin 32.

4. The interpolation ﬁlter interpolates from 1 fs to the PWM controller sample rate

(2048 fs at 44.1 kHz) by cascading FIR ﬁlters.

5. The gain block can boost the signal with 0 dB or +24 dB. Four speciﬁc gain settings

are also provided in this block. These speciﬁc gain settings are related to maximum

clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These

maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input

signal.

6. The power limiter limits the maximum output signal of the TFA9812. The power limiter

settings are 0 dB, −1.5 dB, −3 dB, and −4.5 dB. This function can be used to reduce

the maximum output power delivered to the speakers at a ﬁxed supply voltage and

speaker impedance.

7. The PWM controller block transforms the audio signal into a BD-modulated PWM

signal. The BD-modulation provides a high signal-to-noise performance and

eliminates clock jitter noise.

8. Via four differential comparators the PWM signals are ampliﬁed by two BTL power

output stages. By default the left audio signal is connected to channel 1 and the right

audio signal to channel 2.

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The block control deﬁnes the operational control settings of the TFA9812 in line with the

actual I²C settings and the pin-controlled settings.

The PLL block creates the system clock and can take the I²S BCK, the MCLK or an

external crystal as reference source.

The following protections are built into the TFA9812:

• Thermal Foldback (TF)

• OverTemperature Protection (OTP)

• OverCurrent Protection (OCP)

• OverVoltage Protection (OVP)

• UnderVoltage Protection (UVP)

• Window Protection (WP)

• Lock Protection (LP)

• UnderFrequency Protection (UFP)

• OverFrequency Protection (OFP)

• Invalid BCK Protection (IBP)

• DC-blocking

• ElectroStatic Discharge (ESD)

8.2 Functional modes

8.2.1 Control modes

The two control modes of the TFA9812 are I²C and legacy.

• In I²C mode the I²C format control is enabled.

• In Legacy mode a pin-based subset of the control options is available. The control

settings for features which are not available in Legacy mode are set to the default I²C

The control mode is selected via pin CSEL as shown in T a ble 4.

Table 4.

Control mode selection

CSEL Pin value Control mode

Legacy (no I²C)

I²C

In the functional descriptions below the control for the various functions will be described

for each control mode. Section 9.6 summarizes the support given by each control mode

for the various TFA9812 functions.

8.2.2 Key operating modes

There are six key operating modes:

• In Sleep mode the voltage supplies are present, but power consumption for the whole

device is reduced to the minimum level. The output stages in Sleep mode are 3-state

and I²C communication is disabled.

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• In Soft mute mode the I²S input signal is overruled with a soft mute.

– In Legacy control mode the analog input pin AVOL controls Soft mute mode.

– In I²C control mode I²C control can be used to enable an automatic soft mute

function. See also Section 8.5.3.

• In Hard mute mode the PWM controller is overruled with a 50 % duty cycle square

pulse. The Hard mute mode is only available in I²C control mode.

• In Operating mode the TFA9812 ampliﬁes the I²S audio input signal in line with the

actual control setting.

• In 3-state mode the output stages are switched off.

• Fault mode is entered when a fault condition is detected by one or more of the

protection mechanisms implemented in the TFA9812. In Fault mode the actual device

conﬁguration depends on the fault detected: see Section 8.7 for more information.

Fault mode is for a subset of the faults ﬂagged on the DIAG output pin. When the

DIAG pin is ﬂagged the output stages will be forced to enter 3-state mode. In Sleep

mode the DIAG pin will not ﬂag fault modes.

Table 5.

Pin:

Operational mode selection

DIAG Output

Operational mode

selected:

POWERUP ENABLE

CSEL

AVOL

ﬂoating

Sleep mode

0 / ﬂoating

Fault mode (enabled by

system)^[1]

ﬂoating

Soft mute mode (in I²C

control mode)^[2]

< 0.8 V

Soft mute (in Legacy control

mode)

ﬂoating

3-state mode

Operational mode

[1] Clocking faults do not trigger DIAG output.

[2] Under these conditions soft mute still has to be enabled by the appropriate I²C setting.

8.2.3 I²S master/slave modes and MCLK/BCK clock modes

The I²S interface can be set in master or in slave.

• In I²S master mode the PLL locks to the output signal of the internal crystal oscillator

circuit which uses an external crystal. The BCK, WS and MCLK signals are generated

by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the

crystal frequency.

• In I²S slave mode the PLL can lock to:

– The external MCLK signal on the MCLK pin called MCLK clock mode.

– The I²S input BCK signal on the BCK pin called BCK clock mode.

The I²S master or slave mode can be selected:

• In I²C control mode by selecting the right I²C setting.

• In legacy control mode by selecting the right setting on the SDA/MS pin.

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Table 6.

I²S master/slave mode selection

Pin value

Clock mode

I²S mode

CSEL

SDA/MS

legacy

I²C

slave

master

slave or master^[1]

[1] Under these conditions the mode is enabled by the appropriate I²C setting.

In I²S slave mode selection between BCK and MCLK clock modes is automatic.

MCLK clock mode is given higher priority than BCK. If the MCLK clock is judged valid by

the protection circuit then MCLK clock mode is enabled. BCK clock mode is enabled when

the MCLK clock is invalid (e.g. not available) and the BCK clock is judged valid by the

protection circuit (see Section 8.7.11).

T a ble 7 shows the supported crystal frequencies in I²S master mode.

T a ble 8 shows the supported MCLK frequencies in MCLK mode (I²S slave mode).

T a ble 9 shows the supported BCK frequencies in BCK mode (I²S slave mode).

Table 7.

Valid crystal frequencies in I²S master mode

Control mode

f_s(kHz)

Crystal frequency (MHz)

I²C

8, 16, 32, 64, 128

8.192

11.025, 22.05, 44.1, 88.2,

176.4

11.2896

12, 24, 48, 96, 192

12.288

8.192

Legacy

44.1

11.2896

12.288

Table 8.

Valid MCLK frequencies in I²S slave mode

Control mode

I²C

f_s(kHz)

MLCK frequency (MHz)

8.192

8, 16, 32, 64, 128

12.288

18.432 (576 f_s)

11.2896

11.025, 22.05, 44.1, 88.2,

176.4

16.9344

44.1

25.4016 (576 f_s)

12.288

12, 24, 48, 96, 192

18.432

27.648 (576 f_s)

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Table 8.

Valid MCLK frequencies in I²S slave mode

Control mode

f_s(kHz)

MLCK frequency (MHz)

8.192

Legacy

12.288

18.432 (576 f_s)

11.2896

44.1

16.9344

25.4016 (576 f_s)

12.288

18.432

27.648 (576 f_s)

Table 9.

Valid BCK frequencies in I²S slave mode

Control mode

f_s(kHz)

BCK (x f_sinput)

I²C

8 to 192^[1]

32, 44.1, 48

32 f_s

48 f_s

64 f_s

32 f_s

48 f_s

64 f_s

Legacy

[1] The valid sample frequencies are shown in Section 9.5.7.

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8.3 Power-up/power-down

external

voltage

supplies

POWERUP

ENABLE

I C

available

soft mute

setting in

I C mode

AVOL pin

in Legacy

mode

PWM

outputs

Operating

mode active

d(soft_mute)

wake

d(on)

d(mute_off)

010aaa219

Fig 3. Power-up/power-down timing

8.3.1 Power-up

Figure 3 and T a ble 10 describe the power-up timing while T a ble 11 shows the pin control

for initiating a power-up reset.

Table 10. Power-up/power-down timing

Symbol

Parameter Conditions Min

Typ

Max

Unit

t_wake

wake-up

time

I²C control

t_d(on)

turn-on

delay time

135

t_{d(mute_off)}

t_{d(soft_mute)}

mute off

delay time

128/f_s

Soft mute

delay time

I²C control

128/f_s

legacy

control^[1]

[1] Mute in Legacy mode is controlled by AVOL pin.

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In I²C control mode communication is enabled after 4 ms. The preferred I²C settings can

be made within 66 ms before the PLL starts running. Finally, the output stages are

enabled and the audio level is increased via a demute sequence if mute has previously

been disabled.

Remark: In I²C mode soft mute is enabled by default. It can be disabled at any time while

I²C communication is valid. In order to prevent audio clicks volume control (default setting

is 0 dB) should be set before soft mute is disabled.

Remark: For a proper start-up in I²S master mode and I²C mode the following sequence

should be followed:

1. The I²S master setting should be set and keep the default sample rate setting active.

2. Next, another sample rate setting than the default one should be selected.

3. Finally, when the default sample rate is used the default sample rate setting should be

selected again.

8.3.2 Power-down

Figure 3 includes the power-down timing while T a ble 11 shows the pin control for enabling

power-down.

Table 11. Power-up/power-down selection

Power-up pin

value

Description

Power-down (Sleep mode)

Power-up

Putting the TFA9812 into power-down is equivalent to enabling Sleep mode

(see Section 8.2.2). This mode is entered immediately and no additional clock cycles are

required.

In order to prevent audible clicks, soft mute should be enabled at least T_{d(soft_mute)}

seconds before enabling Sleep mode.

The speciﬁed low current and power conditions in T a ble 1 are valid within 10 µs after

enabling Sleep mode.

8.4 Digital audio data input

8.4.1 Digital audio data format support

The TFA9812 supports a commonly used range of I²S and I²S-like digital audio data input

formats. These are listed in T a ble 12.

Table 12. Supported digital audio data formats

BCK frequency Interface format (MSB ﬁrst)

Supported in I²C Supported in Legacy

control mode

32 f_s

48 f_s

I²S up to 16-bit data

yes

MSB-justiﬁed 16-bit data

LSB-justiﬁed 16-bit data

I²S up to 24-bit data

MSB-justiﬁed up to 24-bit data yes

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Table 12. Supported digital audio data formats

BCK frequency Interface format (MSB ﬁrst)

Supported in I²C Supported in Legacy

control mode

48 f_s

64 f_s

LSB-justiﬁed 16-bit data

LSB-justiﬁed 18-bit data

LSB-justiﬁed 20-bit data

LSB-justiﬁed 24-bit data

I²S up to 24-bit data

yes

MSB-justiﬁed up to 24-bit data yes

LSB-justiﬁed 16-bit data

LSB-justiﬁed 18-bit data

LSB-justiﬁed 20-bit data

LSB-justiﬁed 24-bit data

yes

Remark: Only MSB-ﬁrst formats are supported.

RIGHT

LEFT

BCK

DATA

MSB B2

S-BUS FORMAT

MSB

LEFT

RIGHT

BCK

DATA

MSB B2

LSB MSB

LSB MSB B2

MSB-JUSTIFIED FORMAT

LEFT

RIGHT

BCK

DATA

MSB B2

B15

LSB

MSB B2

B15 LSB

LSB-JUSTIFIED FORMAT 16 BITS

LEFT

RIGHT

BCK

DATA

MSB B2

B17

LSB

MSB B2

B17 LSB

LSB-JUSTIFIED FORMAT 18 BITS

LEFT

RIGHT

BCK

DATA

MSB B2

B19

LSB

MSB B2

B19 LSB

LSB-JUSTIFIED FORMAT 20 BITS

LEFT

RIGHT

BCK

DATA

MSB B2

B9 B10

B23

LSB

MSB B2

B9 B10

B23 LSB

010aaa458

LSB-JUSTIFIED FORMAT 24 BITS

Fig 4. Serial interface input and output formats

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In I²C control mode the following sample frequency f_scan be used: 8 kHz, 11.025 kHz,

12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz,

128 kHz, 176.4 kHz or 192 kHz. The I²C control for f_sselection can be found in

Section 9.5.7.

In Legacy control mode the following sample frequencies (f_s) can be used: 32 kHz,

44.1 kHz or 48 kHz.

8.4.2 Digital audio data format control

The BCK-to-WS and MCLK-to-WS frequency ratios are automatically detected, so no

control settings need to be conﬁgured for these.

In I²C control mode all the formats listed in T a ble 12 are supported. The appropriate I²C

controls for selecting the supported formats can be found in Section 9. In the Legacy

control mode only a subset of the supported formats can be used. These are shown in

T a ble 12 and the required pin control is given in T a ble 13.

See Section 8.2.1 for details of how to enable Legacy control mode.

Table 13. Digital audio data format selection in Legacy control mode

SCL/SFOR pin value

Interface formats (MSB-ﬁrst)

I²S

MSB-justiﬁed

8.5 Digital signal-processing features

8.5.1 Equalizer

8.5.1.1 Equalizer options

The equalizer function can be bypassed and the equalizer can be conﬁgured to either a

5-band or 10-band function. These settings are for both audio channels simultaneously.

There are 20 bands in the equalizer. These are distributed as follows:

• Bands A1 to A5 are bands 1 to 5 of output 1 (used in 5-band and 10-band

conﬁguration).

• Bands B1 to B5 are bands 1 to 5 of output 2 (used in 5-band and 10-band

conﬁguration).

• Bands C1 to C5 are bands 6 to 10 of output 1 (used in 10-band conﬁguration only).

• Bands D1 to D5 are bands 6 to 10 of output 2 (used in 10-band conﬁguration only).

In I²C control mode each band can be conﬁgured separately using I²C register settings.

In Legacy control mode the equalizer is bypassed.

8.5.1.2 Equalizer band function

The shape of each parametric equalizer band is determined by the three ﬁlter parameters:

• (Relative) center frequency ω = 2π( f _c⁄ f _s) .

• Quality factor Q.

• Gain factor G.

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In the above equation f_cis the center frequency and f_sis the sample frequency.

The deﬁnition of the quality factor is the center frequency divided by the 3 dB bandwidth,

see Equation 1. In parametric equalizers this is only valid when the gain is set very small

(−30 dB).

A_f

--------

A_f

f ₁:

20¹⁰log

= 3dB f _c> f ₁

f _c

Q =

;

(1)

-----------------

f ₂– f ₁

A_f

--------

A_f

f ₂:

= 3dB , f ₂> f _c

Each band ﬁlter can be programmed to perform a band-suppression (G < 1) or a

band-ampliﬁcation (G > 1) function around the center frequency.

Each band of the TFA9812 equalizer has a second-order Regalia-Mitra all-pass ﬁlter

structure. The structure is shown in Figure 5.

Y(z)

X(z)

−

K /2

A(z)

010aaa406

Fig 5. Regalia ﬁlter ﬂow-diagram

The transfer function of this all-pass ﬁlter is shown in Equation 2:

H(z) = 1 ⁄ 2 ⋅ (1 + A(z)) + K₀⁄ 2 ⋅ (1 – A(z))

(2)

(3)

A(z) is the second-order ﬁlter structure. The transfer function of A(z) is shown in

Equation 3:

K₁+ K₂⋅ (1 + K₁) ⋅ Z^–1+ Z^–2

1 + K₂⋅ (1 + K₁) ⋅ Z^–1+ K₁⋅ Z^–2

A(z) =

--------------------------------------------------------------------------------

The relationship between the programmable parameters K₀, K₁, and K₂and the ﬁlter

parameters G, ω, Q is shown in Equation 4 and Equation 5.

Use Equation 4 to calculate band suppression (G < 1) functions.

K₀= G

K₁= –cosω

(4)

K₂= (2Q ⋅ G – sinω) ⁄ (2Q ⋅ G + sinω)

G < 1

Use Equation 5 to calculate band ampliﬁcation (G ≥ 1) functions.

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K₀= G

K₁= –cosω

(5)

K₂= (2Q – sinω) ⁄ (2Q + sinω)

G ≥ 1

The ranges of the TFA9812 parametric equalizer settings for each band are:

• The Gain, G is from −30 dB to +12 dB.

• The center frequency, f_cis from 0.0004 * f_sto 0.49 * f_s.

• The quality factor Q is from 0.001 to 8.

Using I²C control, ﬁlter coefﬁcients need to be entered for each ﬁlter stage to conﬁgure it

as desired.

Figure 6, Figure 7 and Figure 8 show some of the possible transfer functions of the

equalizer bands. The relations are symmetrical for the suppression and ampliﬁcation

functions. A skewing effect can be observed for the higher frequencies.

Different conﬁgurations are available for the same ﬁlter transfer function, thus allowing

optimum numerical noise performance. The binary ﬁlter conﬁguration parameters t₁and t₂

control the actual conﬁguration and should be chosen according to Equation 6.

ω<=π ⁄ 2

t₁

ω>π ⁄ 2

(6)

k₂>=0

k₂<0

t₂

A maximum of 12 dB ampliﬁcation per equalizer stage can be achieved with respect to the

input signal. Each band of the equalizer is provided with a −6 dB ampliﬁcation, so in order

to prevent numerical clipping for some ﬁlter settings with over 6 dB of ampliﬁcation, band

ﬁlters can be scaled by 0 dB or −6 dB. For optimum numerical noise performance steps of

−6 dB ampliﬁcation should be applied to the highest possible sections that are still within

scale signal processing safeguards. Band ﬁlters can be scaled with the binary parameters

listed in T a ble 14.

Table 14. Equalizer scale factor coding

scale factor (dB)

−6

8.5.1.3 Equalizer band control

For compact representation with positive signed parameters, parameters k₁’ and k₂’ are

introduced in Equation 7.

The parameters k₀, k₁', k₂', t₁, t₂and s must be combined in two 16-bit control words,

word1 and word2, and must ﬁt within the representation given in T a ble 15. Parameters k₁'

and k₂' are unsigned ﬂoating-point representations in Equation 8.

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1 – k₁

t₁= 1

k₁′ =

1 + k₁

t₁= 0

(7)

(8)

1 – k₂

t₂= 0

k₂′ =

1 + k₂

t₂= 1

k_x= M ⋅ 2^–E

M < 1

In Equation 8, M is the unsigned mantissa and E the negative signed exponent. For

−1

example, in word2 bits [14:8] = [0111 010] represent k₂' = (7/2⁴) × 2⁻²= 1.09375 10 .

Table 15. Equalizer control word construction

Word

word1

word2

Section

Data

t₁

[14:4]

[3:0]

11 mantissa bits of k₁’

Four exponent bits of k₁’

t₂

[14:11]

[10:8]

[7:1]

Four mantissa bits of k₂’

Three exponents bits of k₂’

k₀

Section 9.5.4 shows the I²C address locations of the controls for various bands of the

equalizer.

010aaa222

Q1 = 0.27

Gain

(dB)

Q2 = 0.61

Q3 = 1.65

Frequency (Hz)

Fig 6. Transfer functions for several quality factors Q

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010aaa223

Gain

(dB)

Frequency (Hz)

Fig 7. Transfer functions for several center frequencies f_c

010aaa224

Gain

(dB)

-6

-12

Frequency (Hz)

Fig 8. Transfer functions for several gain factors G

8.5.2 Digital volume control

In I²C control mode both audio channels have separate digital volume control. In Legacy

control mode the volume control of both channels is common and the volume control

setting depends on the supply voltage on the pin AVOL (32).

8-bit volume control is available per channel. This is dB-linear down to −124 dB in steps of

0.5 dB. The last step of the volume control is mute.

T a ble 16 shows the various settings and their related channel suppression:

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Table 16. Volume control channel suppression table

[7:0] control value (hexadecimal)

Gain (dB)

...

−0.5

steps of 0.5 dB

−123.5

−124

mute

Section 9 shows the I²C address locations for the digital gain control for both channels.

In Legacy mode the pin AVOL (32) can be used to control the volume.

Voltage levels of 0.8 V to 2.8 V correspond linearly to control values of 00h (0 dB) to F9h

(mute). See T a ble 16.

An external pull-up resistor connected to the V_DDD(3V3)can be applied to provide a default

volume of 0 dB. Pin AVOL has no function in I²C mode.

8.5.3 Soft mute and mute

Soft mute is available in I²C and in Legacy control modes: hard mute can be enabled only

in I²C control mode.

In I²C control mode the soft mute function smoothly reduces the gain setting for both

channels to mute level over a duration of 128/f_sseconds. The smooth shape is

implemented as a raised cosine function. Soft demute results in a similar gain increase.

This implementation avoids audible plops.

A different soft mute and soft demute function is implemented in Legacy mode. This works

via the analog gain control under the control of pin AVOL. The analog volume control input

signal is ﬁrst-order low-pass ﬁltered with a time constant of 10 ms in the digital domain.

Suddenly switching on or switching off volume by setting the control voltage to

> 2.8 V or < 0.8 V respectively will result in a fading which lasts approximately 15 ms

(switching between 0 V and 3.3 V at AVOL).

In Legacy mode the soft demute function that is part of the automatic power-up sequence

is similar to the I²C mode soft demute function described above. The I²C control for the

soft and hard mute functions can be found In Section 9.

8.5.4 Output signal and word-select polarity control

In I²C control mode the TFA9812 can switch the polarity of the stereo output signal. The

effect is a 180 degree phase shift of both output signals.

The TFA9812 also has the option of switching the polarity of the WS signal. Without

polarity inversion the left audio signal is connected to channel 1 and the right audio signal

is connected to channel 2.

The I²C control for the polarity switch can be found in Section 9.5.1.

8.5.5 Gain boost and clip level control

An additional gain boost of +24 dB can be selected in the TFA9812. In Legacy mode this

feature can be selected with the GAIN pin, see T a ble 17.

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Table 17. GAIN pin functionality

GAIN pin value

Function

0 dB gain

+24 dB gain

The I²C controls for selecting the +24 dB gain can be found in Section 9.5.6. The GAIN

pin has no function In I²C mode.

The TFA9812 features also speciﬁc gain settings which are related to < 0.5 %, 10 %, 20 %

or 30 % clipping at the output of the TFA9812. These clipping values are only valid under

the following conditions:

• The volume control is set to 0 dB.

• The gain boost is set to 0 dB.

• A 0 dBFs I²S input signal is obtained.

The I²C controls for selecting a speciﬁc clip level can be found in Section 9.5.6. In Legacy

mode the clip level is set to 10 %.

8.5.6 Output power limiter

Output power can be limited to three discrete levels with respect to the maximum power.

The maximum power output value is determined by the value of the high voltage supply.

Clipping levels (see Section 8.5.5) still apply to the maximum levels of reduced output

voltage swings.

In I²C control mode the same output power limiting levels can be selected, see

Section 9.5.6. In Legacy control mode two pins can be used to select the output power

limit level as shown in T a ble 18.

Table 18. Legacy mode output power limiter control

Pin value

Function

ADSEL2/PLIM2

ADSEL1/PLIM1

Maximum power

Maximum power − 1.5 dB

Maximum power − 3.0 dB

Maximum power − 4.5 dB

8.5.7 PWM control for performance improvement

The PWM switching frequency of the TFA9812 is dependent on:

• The sampling frequency, f_s.

• The sampling frequency setting, f_s(selected) (see Section 9.5.7).

• The PWM switching frequency setting, f_sw(selected) (see Section 9.5.6).

Equation 9 shows the relationship between these settings and the PWM carrier

frequency:

f _s

f _sw

⋅ f

(9)

---------------------------

sw(selected)

f _{s(selected ))}

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The selected PWM switching frequency is 400 kHz by default and can be set to 350 kHz,

700 kHz and 750 kHz in I²C control mode. In Legacy mode 400 kHz is the only option and

this scales linearly if 32 kHz or 48 kHz is used as f_s.

Remark: The selected sample frequency, f_s(selected) must be equal to the sample

frequency (f_s) in I²C control mode.

Remark: The performance of AM radio reception can sometimes be improved by

selecting non-interfering frequencies for the PWM signal.

8.6 Class-D ampliﬁcation

The Class-D power ampliﬁcation of the PWM signal is carried out in two BTL power

stages. The output signal voltage level is determined by the values on the V_DDPpins.

The power ampliﬁers can be explicitly put into 3-state mode by using the pin ENABLE as

shown in T a ble 19. The ENABLE pin is functional in Legacy mode and in I²C mode.

Table 19. ENABLE pin functionality

ENABLE pin value

Function

Output stages in 3-state mode.

Switching enabled ^[1]

[1] Can be overruled by a forced 3-state in Sleep or Fault mode.

8.7 Protection mechanisms

The TFA9812 has a wide range of protection mechanisms to facilitate optimal and safe

application. All of these are active in both I²C and Legacy control modes.

The following protections are included in the TFA9812:

• Thermal Foldback (TF)

• OverTemperature Protection (OTP)

• OverCurrent Protection (OCP)

• OverVoltage Protection (OVP)

• UnderVoltage Protection (UVP)

• Window Protection (WP)

• Lock Protection (LP)

• UnderFrequency Protection (UFP)

• OverFrequency Protection (OFP)

• Invalid BCK Protection (IBP)

• DC-blocking

• ESD

The reaction of the device to the different fault conditions differs per protection.

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8.7.1 Thermal foldback

If the junction temperature of the TFA9812 exceeds the programmable Thermal foldback

threshold temperature the gain of the ampliﬁer is decreased gradually to a level where the

combination of dissipation (P) and the thermal resistance from junction to ambient (R_th(j-a)

)

results in a junction temperature around the threshold temperature.

This means that the device will not completely switch off, but remains operational at lower

output power levels. Especially with music output signals this feature enables high peak

output power while still operating without any external heat sink other than the

printed-circuit board area. If the junction temperature still increases due to external

causes, the OTP switches the ampliﬁer to 3-state mode.

Under I²C control the Thermal foldback threshold temperature value can be lowered

(see Section 9.5.8): In Legacy control mode the default threshold value of 125 °C is ﬁxed.

8.7.2 Overtemperature protection

This is a ‘hard’ protection to prevent heat damage to the TFA9812. The overtemperature

threshold level is the 160 °C junction temperature.

When the threshold temperature is exceeded the output stages are set to 3-state mode.

The temperature is then checked at 1 µs intervals and the output stages will operate

normally again once the temperature has dropped below the threshold level.

OTP is ﬂagged by a low DIAG pin. The TFA9812 temperature is an I²C reading, see

Section 9.5.9.

Under normal conditions thermal foldback prevents the overtemperature protection from

being triggered.

8.7.3 Overcurrent protection

The output current of the power ampliﬁers is current-limited. When an output stage

exceeds a current of 3 A typical, the output stages are set to 3-state mode and after 1 µs

the stages will start operating normally again. These interruptions are not audible.

OCP is ﬂagged by a low DIAG pin and by a high DIAG I²C status bit, see Section 9.5.10.

I²C settings remain valid.

8.7.4 Overvoltage protection

The supply for the power stages (V_DDA, V_DDP) is protected against overvoltage. When a

supply voltage exceeds 20 V the device will enter Sleep mode. When the supply voltage

has fallen below 20 V again the power-up sequence is started.

OVP is ﬂagged by a low DIAG pin and by a high DIAG I²C status bit, see Section 9.5.10.

I²C settings remain valid.

8.7.5 Undervoltage protections

The supplies are protected against undervoltage. When this is detected the device will

enter Sleep mode. When the supply voltage has risen to a sufﬁcient level again the

power-up sequence is started.

T a ble 20 shows the UVP trigger levels for the V_DDAand V_DDA(3V3)supplies:

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Table 20. Undervoltage trigger levels

Pin name

UVP level

Min

DIAG pin (protection active)

Max

V_DDA

≥ 7 V

< 8 V

< 3 V

LOW

V_DDA(3V3)

≥ 1.6 V

8.7.6 Overdissipation protection

When the output current of the power ampliﬁers exceeds a current value of 3 A and the

temperature is above 140 °C, overdissipation protection is activated and the device enters

Sleep mode. A restart will be initiated automatically when the two overdissipation

conditions are both changed to ‘false’.

Overdissipation is ﬂagged by a low DIAG pin and by a high DIAG I²C status bit, see

Section 9.5.10.

Under normal conditions thermal foldback prevents overdissipation protection from being

triggered. I²C settings remain valid.

8.7.7 Window protection

Window protection is a feature for protecting the device against shorts from the outputs to

the ground or supply lines. If during power-up one of the outputs is shorted to V_SSPxor

V_DDP, power-up does not proceed any further. The trigger levels for these conditions are:

• OUTxx > V_DDA− 1 V, or

• OUTxx < REFA + 1 V.

The WP alarm is ﬂagged by a low DIAG pin and by a high DIAG I²C status bit, see

Section 9.5.10.

8.7.8 Lock protection

When the selected clock input source (MCLK, BCK or crystal) stops running, the TFA9812

is able to detect this and set the output stages to 3-state mode. Without this protection

peripheral devices in an application might be damaged.

The PLL lock indication is an I²C reading and will be ‘false’ in the event of a clock

interruption, see Section 9.5.10.

8.7.9 Underfrequency protection

UFP sets the output stages to 3-state mode when the clock input source is too low. The

PWM switching frequency can becomes critically low when the clock input source is lower

than speciﬁed. Without UFP peripheral devices in an application might be damaged.

The status of the UFP is shown in I²C reading register, see Section 9.5.10.

8.7.10 Overfrequency protection

OFP sets the output stages to 3-state mode when the clock input source is too high. The

PWM controller can become unstable when the clock input source is higher than

speciﬁed. Without OFP peripheral devices in an application might be damaged.

The status of the OFP is shown in I²C reading register, see Section 9.5.10.

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8.7.11 Invalid BCK protection

The BCK clock signal is veriﬁed as being at one of the allowed relative frequencies: 32 f_s,

48 f_sor 64 f_s. If it is not at one of these frequencies the TFA9812 will set the output stages

to 3-state mode to prevent audible effects.

The MCLK clock signal is also veriﬁed as being valid, see Section 8.2.3.

Detection of violation results in an automatic internal overruling of the MCLK assignment

to BCK.

8.7.12 DC blocking

The TFA9812 features a high pass ﬁlter after the I²S input to block DC signals. DC values

at the output can damage the peripheral devices. The high pass ﬁlter is always enabled.

8.7.13 Overview protections

T a ble 21 shows the overview of the protections.

Table 21. Overview protections

Protections

Symbol Conditions

DIAG

I²C

ﬂag^[1]

Output

Recovering

programmable

max. T_j> 125 °C

Floating

Switching Automatic, increasing

volume control back to

volume setting

OTP

OCP

OVP

T_j> 160 °C

I_O> I_ORM

LOW

DIAG Floating

Automatic, after 1 µs and

T_j< 160 °C

Automatic, after 1 µs and

I_O< I_ORM

V_DDA> 20 V

Restart (fault to operating

when V_DDA> 8 V and

V_DDA(3V3)> 3 V)

UVP

ODP

WP^[2]

V_DDA< 8 V or

LOW

DIAG Floating

Restart (fault to operating

when V_DDA> 8 V and

_DDA(3V3)< 3 V

V_DDA(3V3)> 3 V)

T_j> 140 °C and I_O> I_ORMLOW

Restart (fault to operating

when T_j< 140 °C or

IO < I_ORM

)

OUTX > V_DDA− 1 V or

OUTX < REFA + 1 V

LOW

Restart (fault to operating

when OUTX < V_DDA− 1 V

and OUTX > V_SSA+ 1 V)

PLL out of lock

Floating LP

Floating

Restart (fault to operating

when PLL is in lock)

UFP

PLL frequency < 45 MHz

Floating UFP

Restart (fault to operating

when

PLL frequency > 45 MHz)

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Table 21. Overview protections …continued

Protections

Symbol Conditions

DIAG

I²C

ﬂag^[1]

Output

Recovering

OFP

IBP

PLL frequency > 140 MHz Floating OFP

Floating

Restart (fault to operating

when

PLL frequency < 140 MHz)

BCK/WS is not 32 ± 2,

Floating

Restart (fault to operating

when BCK/WS is 32 ± 2,

48 2 or 64 2)

48 2 or 64 2

[1] See, Section 9.5.10.

[2] Window Protection is only checked at power-up.

9. I²C bus interface and register settings

9.1 I²C bus interface

The TFA9812 supports the 400 kHz I²C bus microcontroller interface mode standard. This

can be used to control the TFA9812 and to exchange data with it when in I²C control

mode, see Section 8.2.1.

The TFA9812 can operate in I²C slave mode only as slave receiver or a slave transmitter.

The serial hardware interface involves the pins of the TFA9812 as described in T a ble 22.

Table 22. I²C pins in I²C control mode

Pin name

Description

SCL/SFOR

SDA/MS

I²C bus clock input

I²C bus data input and output

I²C bus device address bit A2

I²C bus device address bit A1

ADSEL2/PLIM2

ADSEL1/PLIM1

Voltage values applied to the I²C bus device address pins are interpreted as described in

T a ble 23.

Table 23. I²C pin voltages in I²C control mode

Logic value

Voltage A2/A1

< V_IL

> V_IH

9.2 I²C bus TFA9812 device addresses

T a ble 24 shows the register address options for the TFA9812 as part of the 8-bit byte that

contains the device address as well as the bit indicator read/write_not R/!W. The TFA9812

supports four different addresses, each of which can be conﬁgured using the pins

ADSEL1/PLIM1 and ADSEL2/PLIM2, see T a ble 22.

Table 24. I²C bus device address

(MSB)

Bit

(LSB)

R/!W

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9.3 I²C write cycle description

T a ble 25 shows the cycle required for writing data to the I²C registers of the TFA9812. The

byte size is 8 bits. The I²C registers of the TFA9812 store two data bytes. Data is always

written in pairs of two bytes. Data transfer is always MSB ﬁrst.

The cycle format for writing to the TFA9812 using SDA is as follows:

1. The microcontroller asserts a start condition (S).

2. The microcontroller sends the device address (7 bits) of the TFA9812 followed by the

R/!W bit set to 0.

3. The TFA9812 asserts an acknowledge (A).

4. The microcontroller writes the 8-bit TFA9812 register address to which the ﬁrst data

byte will be written.

5. The TFA9812 asserts an acknowledge.

6. The microcontroller sends the ﬁrst byte. This is the most signiﬁcant byte of the

7. The TFA9812 asserts an acknowledge.

8. The microcontroller sends the second byte.

9. The TFA9812 asserts an acknowledgement.

10. The microcontroller can either assert the stop condition (P) or continue with a further

pair of data bytes, repeating step 6. In the latter case the targeted register address will

have been auto-increased by the TFA9812.

Table 25. I²C write cycle

Start TFA9812

Address

R/!W

TFA9812 ﬁrst

databyte

More Stop

databyte data...

11010A₂A₁

ADDR

MS1

LS1 <....>

9.4 I²C read cycle description

T a ble 26 shows the cycle required for reading data from the I²C registers of the TFA9812.

The byte size is 8 bits. The I²C registers of the TFA9812 store two data bytes. Data is

always read in pairs of two bytes. Data transfer is always MSB-ﬁrst.

The read cycle format for writing to the TFA9812 using SDA is as follows:

1. The microcontroller asserts a start condition (S).

2. The microcontroller sends the device address (7 bits) of the TFA9812 followed by the

R/!W bit set to 0.

3. The TFA9812 asserts an acknowledge (A).

4. The microcontroller writes the 8-bit TFA9812 register address from which the ﬁrst data

byte will be read.

5. The TFA9812 asserts an acknowledge.

6. The microcontroller asserts a repeated start (Sr).

7. The microcontroller resends the device address (7 bits) of the TFA9812 followed by

the R/!W bit set to 1.

8. The TFA9812 asserts an acknowledge.

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9. The TFA9812 sends the ﬁrst byte. This is the most signiﬁcant byte of the register.

10. The microcontroller asserts an acknowledge.

11. The TFA9812 sends the second byte.

12. The microcontroller asserts either an acknowledge or a negative acknowledge (NA).

– If the microcontroller has asserted an acknowledge, the targeted register address

is auto-increased by the TFA9812 and steps 9 to 12 are repeated.

– If the microcontroller has asserted a negative acknowledge, the TFA9812 frees the

I²C bus and the microcontroller generates a stop condition (P).

Table 26. I²C read cycle

Start TFA9812

address

R/!W

First

address

TFA9812

address

R/!W

data

byte

LS More More

data data... data...

byte

Stop

11010A₂A₁

ADDR

Sr 11010A₂A₁

MS1

LS1 <A>

<....>

9.5 Top-level register map

T a ble 27 describes the assignments of the various register addresses to the functional

control or status areas at top level. There are 47 control registers and 2 status registers.

The following subsections give the individual register interpretations and bit level details.

Table 27. Top-level register map

Access See:

Description

address

(hex)

0x00

0x0020;

R/W

Section 9.5.1

Interpolator settings and soft mute

Legacy_mode

0x0021; I²C_mode

0x01

0x02

0x03

0x04

0x0000

R/W

Volume control

0x0006

Format digital in

0x0002

Equalizer conﬁguration

0x0058

Equalizer_A1 word_1; word_1 for

equalizer band A1, see Section 8.5.1.2

0x05

0x4F40

R/W

Section 9.5.5

Equalizer_A1 word_2; see

Section 8.5.1.2

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x0058

0x4F40

0x0A63

0x4240

0x0A63

0x4240

0x00B7

0x4E40

0x00B7

0x4E40

0x14A2

R/W

Section 9.5.5

Equalizer_B1 word_1

Equalizer_B1 word_2

Equalizer_C1 word_1

Equalizer_C1 word_2

Equalizer_D1 word_1

Equalizer_D1 word_2

Equalizer_A2 word_1

Equalizer_A2 word_2

Equalizer_B2 word_1

Equalizer_B2 word_2

Equalizer_C2 word_1

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Table 27. Top-level register map …continued

Description

address

(hex)

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x7A40

0x14A2

0x7A40

0x0156

0x4D40

0x0156

0x4D40

0x2871

0x7140

0x2871

0x7140

0x02A5

0x4C40

0x02A5

0x4C40

0x4A80

0x5040

0x4A80

0x5040

0x0534

0x4B40

0x0534

0x4B40

0xD961

0x4840

0xD961

0x4840

0x0005

0x000E

0x0000

R/W

Section 9.5.5

Equalizer_C2 word_2

Equalizer_D2 word_1

Equalizer_D2 word_2

Equalizer_A3 word_1

Equalizer_A3 word_2

Equalizer_B3 word_1

Equalizer_B3 word_2

Equalizer_C3 word_1

Equalizer_C3 word_2

Equalizer_D3 word_1

Equalizer_D3 word_2

Equalizer_A4 word_1

Equalizer_A4 word_2

Equalizer_B4 word_1

Equalizer_B4 word_2

Equalizer_C4 word_1

Equalizer_C4 word_2

Equalizer_D4 word_1

Equalizer_D4 word_2

Equalizer_A5 word_1

Equalizer_A5 word_2

Equalizer_B5 word_1

Equalizer_B5 word_2

Equalizer_C5 word_1

Equalizer_C5 word_2

Equalizer_D5 word_1

Equalizer_D5 word_2

PWM signal control

Digital-in clock conﬁguration

Thermal foldback control

TFA9812 temperature

Section 9.5.10 Miscellaneous status

Reserved registers or bits will be indicated by RSD.

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9.5.1 Interpolator settings and soft mute

Table 28. Register address 00h: miscellaneous I²C interpolator settings

Bit

RSD

Symbol

Default

Bit

RSD

INV_POL

ROFF1

ROFF0

FDEMP2

FDEMP1

FDEMP0

Symbol

Default

RSD

S_MUTE

1/0

Table 29. Bit description of register 00h: miscellaneous I²C interpolator settings

Bit

Symbol

Description

INV_POL

Enable polarity inversion:

0 = No polarity inversion (left audio signal connected to

channel 1; right signal to channel 2)

1 = Polarity inversion enabled

5 to 4

ROFF[1:0]

Filter roll-off sharpness:

0 = Slow ﬁlter roll-off (2 to 8 f_s) ≥ stop band > 0.7619 f_s

1 = Slow ﬁlter roll-off (2 to 8 f_s) ≥ stop band > 0.7619 f_s

2 = Fast ﬁlter roll-off (2 to 8 f_s) ≥ stop band > 0.6094 f_s

3 = Fast ﬁlter roll-off (2 to 8 f_s) ≥ stop band > 0.6094 f_s

Digital de-emphasis setting:

3 to 1

FDEMP[2:0]

0 = No digital de-emphasis

1 = Digital de-emphasis for f_s= 32 kHz

2 = Digital de-emphasis for f_s= 44.1 kHz

3 = Digital de-emphasis for f_s= 48 kHz

4 = Digital de-emphasis for f_s= 96 kHz

5 to 8 = No digital de-emphasis

S_MUTE

Soft mute:

0 = Soft mute disabled using raised cosine (default in

Legacy control mode)

1 = Soft mute enabled using raised cosine (default in

I²C control mode)

9.5.2 Volume control

Table 30. Register address 01h: volume control

Bit

Symbol

Default

Bit

VOL_L7

VOL_L6

VOL_L5

VOL_L4

VOL_L3

VOL_L2

VOL_L1

VOL_L0

VOL_R7

VOL_R6

VOL_R5

VOL_R4

VOL_R3

VOL_R2

VOL_R1

VOL_R0

Symbol

Default

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Table 31. Bit description of register 00h: miscellaneous I²C interpolator settings

Bit

Symbol

Description

15 to 8

VOL_L[15:8]

See T a ble 16 for suppression levels on left channel as

function of data byte setting.

7 to 0

VOL_R[7:0]

See T a ble 16 for suppression levels on right channel as

function of data byte setting.

9.5.3 Digital input format

Table 32. Register address 02h: digital input format

Bit

RSD

Symbol

Default

Bit

RSD

DI_FOR2

DI_FOR1

DI_FOR0

WS_POL

Symbol

Default

RSD

Table 33. Bit description of register 02h: digital input format

Bit

Symbol

Description

3 to 1

DI_FOR[2:0]

Digital audio input format:

0 = RSD

1 = RSD

2 = MSB-justiﬁed data up to 24 bits

3 = I²S data up to 24 bits

4 = LSB-justiﬁed 16-bit data

5 = LSB-justiﬁed 18-bit data

6 = LSB-justiﬁed 20-bit data

7 = LSB-justiﬁed 24-bit data

WS_POL

Enable WS signal polarity inversion:

0 = No WS signal polarity inversion

1 = WS signal polarity inversion enabled

9.5.4 Equalizer conﬁguration

Table 34. Register address 03h: equalizer conﬁguration

Bit

RSD

Symbol

Default

Bit

RSD

EQ_BP

EQ_BND

Symbol

Default

RSD

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Table 35. Bit description of register 03h: equalizer conﬁguration

Bit

Symbol

Description

EQ_BP

Equalizer bypass enable:

0 = Equalizer not bypassed

1 = Equalizer bypassed

EQ_BND

Equalizer 10-band or 5-band conﬁguration selection:

0 = 10-band equalizer conﬁguration enabled

1 = 5-band equalizer conﬁguration enabled

9.5.5 Equalizer settings

Table 36. Register addresses xxh = 04, 06...2A

For word1 for equalizer 'yy' see Figure 9

Bit

Symbol

Default^[1]

Bit

Eyy_t₁

Eyy_k_1m10

Eyy_k_1m

Eyy_k_1m4

Eyy_k_1m

Symbol

Default^[1]

Eyy_k_1m

Eyy_k_1e3

Eyy_k_1e2

Eyy_k_1e1

Eyy_k_1e0

[1] Default settings are shown in T a ble 27. The corresponding equalizer conﬁguration is shown in T a ble 40.

Table 37. Register addresses xxh = 05, 07...2B

For word2 for equalizer 'yy' see Figure 9

Bit

Symbol

Default

Bit

Eyy_t₂

Eyy_k_2m

Eyy_k_2e2

Eyy_k_2e1

Eyy_k_2e0

Eyy_s

Symbol

Default

Eyy_k₀6

Eyy_k₀5

Eyy_k₀4

Eyy_k₀3

Eyy_k₀2

Eyy_k₀1

Eyy_k₀0

[1] Default settings are shown in T a ble 27. The corresponding equalizer conﬁguration is shown in T a ble 40.

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Left in

Left out

2 × 5 or 2 × 10

Right in

Right out

2 × 5 or 2 × 10

010aaa404

Fig 9. Equalizer conﬁguration and register location mapping

Table 38. Bit description of registers xxh = 04, 06...2A

Bit

Symbol

Description

Eyy_t₁

The ﬁlter conﬁguration bit t_1,see Section 8.5.1.2.

14 to 4

Eyy_k1_m[10:0]

The 11 mantissa bits of the ﬁlter parameter k_1,see

3 to 0

Eyy_k1_e[3:0]

The four exponent bits of the ﬁlter parameter k₁, see

Table 39. Bit description of registers xxh = 05, 07...2B

Bit

Symbol

Description

Eyy_t₂

The ﬁlter conﬁguration bit t₂, see Section 8.5.1.2.

14 to 11

Eyy_k_2m[3:0]

The four mantissa bits of the ﬁlter parameter k₂, see

10 to 8

7 to 1

Eyy_k_2e[2:0]

Eyy_k₀[6:0]

Eyy_s

The three exponent bits of the ﬁlter parameter k₂, see

The seven bits of the ﬁlter gain parameter k₀, see

The ﬁlter scale-factor bits, see Section 8.5.1.2:

0 = No scaling applied

1 = −6 dB ampliﬁcation enabled

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Table 40. Default conﬁguration equalizer for f_s= 44.1 kHz

Band

A1/B1

A2/B2

A3/B3

A4/B4

A5/B5

C1/D1

C2/D2

C3/D3

C4/D4

C5/D5

Frequency

(Hz)

125

250

500

1000

2000

4000

8000

16000

Q-factor

Gain (dB)

9.5.6 PWM signal control

Table 41. Register 2Ch: PWM signal control

Bit

RSD

Symbol

Default

Bit

RSD

PW_OFF

PW_SF1

PW_CL1

PW_CL0

Symbol

Default

RSD

PLIM1

PLIM0

PW_SF0

Table 42. Bit description address 2Ch

Bit

Symbol

Description

+24 dB gain boost:

GAIN

0 = Gain boost 0 dB

1 = Gain boost +24 dB

Output power limitation:

0 = Maximum power

6 to 5

PLIM[1:0]

1 = Maximum power − 1.5 dB

2 = Maximum power − 3.0 dB

3 = Maximum power − 4.5 dB

Hard mute control:

PW_OFF

0 = No hard mute

1 = Hard mute enabled, implemented by PWM signal

with 50 % duty cycle

3 to 2

PW_SF[1:0]

PWM switching frequency:

0 = 350 kHz

1 = 400 kHz

2 = 700 kHz

3 = 750 kHz

1 to 0

PW_CL[1:0]

PWM clip level:

0 = < 0.5 % THD

1 = 10 % THD

2 = 20 % THD

3 = 30 % THD

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9.5.7 Digital-in clock conﬁguration

Table 43. Register 2Dh: digital-in clock conﬁguration

Bit

RSD

Symbol

Default

Bit

RSD

FSUB3

FSUB2

FSUB1

FSUB0

DI_MS

Symbol

Default

RSD

Table 44. Bit description of register 2Dh:digital-in clock conﬁguration

Bit

Symbol

Description

4 to 1

FSUB[3:0]

Sample frequency f_sof digital-in signal:

0 = 8 kHz

1 = 11.025 kHz

2 = 12 kHz

3 = 16 kHz

4 = 22.05 kHz

5 = 24 kHz

6 = 32 kHz

7 = 44.1 kHz

8 = 48 kHz

9 = 64 kHz

10 = 88.2 kHz

11 = 96 kHz

12 = 128 kHz

13 = 176.4 kHz

14 = 192 kHz

15 = RSD

DI_MS

TFA9812 digital-in Master/Slave mode selection:

0 = Slave mode

1 = Master mode

9.5.8 Thermal foldback control

Table 45. Register 2Eh: thermal foldback control

Bit

Symbol

Default

Bit

RSD

TP_THR9

TP_THR8

TP_THR7

TP_THR6

TP_THR5

TP_THR4

TP_THR3

TP_THR2

TP_THR1

TP_THR0

Symbol

Default

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Table 46. Bit description of register 2Dh: digital-in clock conﬁguration

Bit

Symbol

Description

9 to 0

TP_THR[9:0]

Reduction on the maximum temperature of 125 °C.

The reduction can be calculated by:

(TP_THR[9:0]

reduction = INTEGER

in °C

-----------------------------------

2.4552

9.5.9 TFA9812 temperature

Table 47. Register 2Fh: TFA9812 temperature

Bit

RSD

Symbol

Default

Bit

RSD

TEMP9

TEMP8

Symbol

Default

TEMP7

TEMP6

TEMP5

TEMP4

TEMP3

TEMP2

TEMP1

TEMP0

Table 48. Bit description of register 2Dh: digital-in clock conﬁguration

Bit

Symbol

Description

9 to 0

TEMP[9:0]

Temperature of the TFA9812, which can be calculated in

°C using: Temp TFA9812 = (1023 − TEMP[9:0]) / 2.4552

9.5.10 Miscellaneous status

Table 49. Register 30h: miscellaneous status

Bit

Symbol

Default

Bit

RSD

DIAG

MUTE

Symbol

Default

OFP

UFP

UVP1V8

UVP3V3

Table 50. Bit description of register 30h: miscellaneous status

Bit

Symbol

Description

OFP

PLL frequency-over-range indicator:

0 = PLL frequency in supported range

1 = PLL frequency exceeds highest supported

frequency value

UFP

PLL frequency under-range indicator:

0 = PLL frequency in supported range

1 = PLL frequency below lowest supported frequency

value

UVP1V8

Undervoltage detector for pins 4 and 41:

0 = No UVP has been detected

1 = A UVP has been detected since the last read-out of

the register

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Table 50. Bit description of register 30h: miscellaneous status …continued

Bit

Symbol

Description

UVP3V3

Undervoltage detector for pins 3 and 40:

0 = No UVP has been detected

1 = A UVP has been detected since the last read-out of

the register

DIAG

Diagnostic pin ﬂagging status^[1]:

0 = Diagnostic pin has not been ﬂagged low

1 = Diagnostic pin has been ﬂagged low since the last

read-out of the register

PLL lock protection indicator:

0 = PLL is in locked status

1 = PLL is not in locked status

Soft mute status:

MUTE

0 = No soft-mute or soft mute/demute in progress

1 = Audio signal muted as result of a soft mute

[1] The diagnostic pin 30 DIAG is ﬂagged when several protection mechanisms have been active, see

Section 8.7.

9.6 Overview of functional control in each control mode

T a ble 51 shows the control level supported by either I²C or Legacy control mode for all

functions described in Section 9. It summarizes the information provided in the detailed

description of each function.

Table 51. Functional control support in I²C and Legacy control modes

D = ﬁxed control setting, determined by default I²C register setting; N = not supported; Y = fully

supported (i.e. all options implemented in the TFA9812).

Control function

Reference

I²C mode

Legacy mode

I²C register content

Section 9

N/D

Sleep mode enable

Section 8.2.2

Section 8.2.3

Section 8.4

Operating mode enable

3-state mode enable

Master/Slave I²S

MCLK/BCK master input clock selection

Digital audio input format selection

Selection f_s= 8 kHz to192 kHz

Equalizer enable and conﬁguration

Detailed equalizer settings

Digital volume control per channel

Auto

Subset

D^[1]

D^[2]

Section 8.4.1

Section 8.5.1

Section 8.5.2

Analog volume control (shared for two channels) Section 8.5.3

De-emphasis for subset of allowed f_s

Soft mute

Section 8.5.3

Section 8.5.4

Section 8.5.6

Y^[3]

Hard mute

Polarity switch enable

+24 dB gain boost

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Table 51. Functional control support in I²C and Legacy control modes …continued

D = ﬁxed control setting, determined by default I²C register setting; N = not supported; Y = fully

supported (i.e. all options implemented in the TFA9812).

Control function

Reference

I²C mode

Legacy mode

Clip level control

Section 8.5.5

Section 8.5.6

Section 8.5.7

D^[4]

Output power limit level control

PWM signal frequency selection

D^[5]

Thermal foldback threshold temperature control Section 8.7.1

[1] 32 kHz, 44.1 kHz and 48 kHz supported

[2] Bypass.

[3] Special Legacy mode implementation.

[4] 10 % clip level.

[5] 400 kHz.

10. Internal circuitry

Table 52. Internal circuitry

Symbol

XTALIN

AVOL

Equivalent circuitry

1, 32

ESD

, V , REFA, REFD

SS1 SS2

Exposed die paddle

010aaa459

XTALOUT

STABA

ESD

, V

SS1 SS2

, REFA, REFD,

Exposed die-paddle

010aaa460

V_DDA(3V3)

V_DDD(3V3)

3, 40

ESD

, V

SS1 SS2

, REFA, REFD,

Exposed die-paddle

010aaa461

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Table 52. Internal circuitry …continued

Symbol

STABA

STABD

Equivalent circuitry

DDA(3V3), DDD(3V3)

4, 41

ESD

, V

SS1 SS2

, REFA, REFD,

Exposed die-paddle

010aaa462

REFA

V_DDA

24 V

, REFD, V

SS2

SS1

Exposed die-paddle

010aaa463

TEST1

DDA

13 kΩ

SS1

010aaa464

STAB2

STAB1

DDA

9, 28

12 V

SS1

010aaa465

10/11

18/19

26/27

V_SSP2

V_DDP

V_SSP1

18/19

24 V

10/11, 26/27

010aaa466

BOOT2N

BOOT1P

BOOT2P

BOOT1N

12, 15, 22, 25

12 V

OUT2N, OUT1P, OUT2P, OUT1N

010aaa467

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Table 52. Internal circuitry …continued

Symbol

OUT2N

OUT1P

OUT2P

OUT1N

Equivalent circuitry

13/14

16/17

20/21

23/24

DDP

13/14, 16/17, 20/21, 23/24

, V

SSP1 SSP2

010aaa468

DIAG

DDA

SS1

010aaa469

CDELAY

DDA

2 µA

200 nA

5 kΩ

DISCHARGE

SS1

010aaa470

POWERUP

DDA

3 kΩ

250 nA

SS1

010aaa471

ENABLE

33, 34, 35, 36, 37, 43

GAIN

Pull-down

ESD

CSEL

50 µA

ADSEL2/PLIM2

ADSEL1/PLIM1

TEST2

, V

, REFA, REFD,

SS1 SS2

Exposed die-paddle

010aaa472

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Table 52. Internal circuitry …continued

Symbol

Equivalent circuitry

SCL/SFOR

38, 44

ESD

, V , REFA, REFD,

SS1 SS2

Exposed die-paddle

010aaa473

SDA/MS

ESD

, V , REFA, REFD,

SS1 SS2

Exposed die-paddle

010aaa474

DDD(3V3)

BCK

MCLK

45, 46, 47

ESD

VSS1, VSS2, REFA, REFD,

Exposed die-paddle

010aaa475

11. Limiting values

Table 53. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DDA

V_DDP

V_DDA(3V3)

V_DDD(3V3)

T_j

Parameter

Conditions

−V_SS

Min

Max

+24

+4.6

150

+150

+85

Unit

analog supply voltage

power supply voltage

analog supply voltage (3.3 V)

digital supply voltage (3.3 V)

junction temperature

storage temperature

ambient temperature

power dissipation

−0.3

−V_SSPx; x = 1.2

−V_SS

−0.3

−0.3

−V_SS

−0.3

°C

T_stg

−55

−40

T_amb

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Table 53. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

DIAG

Min

Max

Unit

V_x

voltage on pin x

V_SS− 0.3

V_SS− 0.5

V_SS+ 12

V_DDA+ 0.3

V_SS+ 5.5

POWERUP

ENABLE, GAIN, CSEL,

ADSEL2/PLIM2,

ADSEL2/PLIM1, SCL/SFOR,

SDA/MS, DATA, WS, BCK,

MCLK

AVOL

V_SS− 0.5

V_SS+ 4.6

+1750

V_esd

electrostatic discharge voltage

according to the human body model

STAB1 and STAB2 with

respect to other pins

−1750

all other pins

−2

according to the charge

device model

−500

+500

[1] V_ss= V_SS1= V_SS2= REFA = REFD

12. Thermal characteristics

Table 54. Thermal Characteristics

Symbol

Parameter

Condition

Min Typ Max Unit

[1][2]

R_th(j-a)

thermal resistance

from junction to

ambient

No air ﬂow, JEDEC board

42 K/W

36 K/W

No air ﬂow; typical 4L board in

the NXP 4L reference

application

[3]

No air ﬂow; typical 2L board in

the NXP 2L reference

application

K/W

R_th(j-c)

thermal resistance

from junction to case

K/W

R_th(j-lead)

thermal resistance

from junction to lead

Worst-case pin

[1] Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7).

[2] Measured in free air with natural convection.

[3] Strongly depends on where measurement is made on the case: worst-case value stated.

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TFA9812

NXP Semiconductors

BTL stereo Class-D audio ampliﬁer with I²S input

13. Characteristics

13.1 DC Characteristics

Table 55. DC characteristics

Unless speciﬁed otherwise, V_DDA= V_DDP= 12 V, V_SSP1= V_SSP2= 0 V, V_DDA(3V3)= V_DDD(3V3)= 3.3 V,

_SS1= V_SS2= REFD = REFA = 0 V, T_amb= 25 °C, R_L= 8 Ω, f_i= 1 kHz, f_s= 44.1 kHz, f_sw= 400 kHz, 24-bit I²S input data,

MCLK clock mode, typical application diagram (Figure 13).

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Supply voltage

V_DDA

analog supply

voltage

V_DDP

power supply voltage

V_DDA(3V3)

analog supply

voltage (3.3 V)

3.0

3.3

3.6

V_DDD(3V3)

I_P

digital supply voltage

(3.3 V)

3.0

3.3

3.6

supply current

soft mute mode, with

load, ﬁlter and snubbers

connected

sleep mode

160

270

µA

I_DDA(3V3)

analog supply

current (3.3 V)

operating mode

I²S slave mode

I²S master mode

sleep mode

V_DDA= V_DDP= 12 V

V_DDA= V_DDP= 1 V

120

µA

I_DDD(3V3)

digital supply current operating mode

(3.3 V)

I²S slave mode

I²S master mode

µA

sleep mode;

DATA = WS = BCK =

MLCK = 0 V

Ampliﬁer output pins; pins OUT1P, OUT1N, OUT2P and OUT2N

|V_O(offset)

output offset voltage soft mute mode

Power-up pin

V_IH

HIGH-level input

voltage

With respect to V_SS1

2.1

−0.3

V_DDD(3V3)

+0.8

V_IL

LOW-level input

voltage

I_I

input current

0.1

µA

MCLK, BCK, WS, DATA pin

V_IH

HIGH-level input

voltage

With respect to V_SS2

0.7 × V_DDD(3V3)

V_IL

LOW-level input

voltage

0.3 × V_DDD(3V3)

C_i

input capacitance

TFA9812_2

Preliminary data sheet

Rev. 02 — 22 January 2009

44 of 66

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TFA9812

NXP Semiconductors

BTL stereo Class-D audio ampliﬁer with I²S input

Table 55. DC characteristics …continued

Unless speciﬁed otherwise, V_DDA= V_DDP= 12 V, V_SSP1= V_SSP2= 0 V, V_DDA(3V3)= V_DDD(3V3)= 3.3 V,

_SS1= V_SS2= REFD = REFA = 0 V, T_amb= 25 °C, R_L= 8 Ω, f_i= 1 kHz, f_s= 44.1 kHz, f_sw= 400 kHz, 24-bit I²S input data,

MCLK clock mode, typical application diagram (Figure 13).

Symbol

Parameter

Condition

Min

Typ

Max

Unit

V_OH

HIGH-level output

voltage

At I_OH= −0.4 mA

V_DDD(3V3)− 0.4 V -

V_OL

C_L

LOW-level output

voltage

At I_OL= 4 mA

400

load capacitance

SDA/MS, SCL/SFOR pin

V_IH

HIGH-level input

voltage

With respect to V_SS2

0.7 × V_DDD(3V3)

−0.3

5.5

V_IL

LOW-level input

voltage

0.3 × V_DDD(3V3)

V_hys(i)

input hysteresis

voltage

0.1 × V_DDD(3V3)

C_i

input capacitance

2.5

V_OL

LOW-level output

voltage

At I_OL= 3 mA

400

ENABLE, GAIN, CSEL, ADSEL2/PLIM2, ASEL1/PLIM1 pin

V_IH

HIGH-level input

voltage

With respect to V_SS2

0.7 × V_DDD(3V3)

V_IL

LOW-level input

voltage

0.3 × V_DDD(3V3)

V_hys(i)

input hysteresis

voltage

0.1 × V_DDD(3V3)

I_I

input current

µA

Regulators

V_o

output voltage

STAB1 − V_SS1

STAB2 − V_SS1

STABA − REFA

STABD − REFD

1.65

1.8

1.95

CDELAY pin

V_CDELAY

voltage on pin

CDELAY

Relative to positive

analog power supply

V_DDA−1

Crystal pins

V_o(xtal)(p-p)

peak-to-peak crystal With respect to V_SS2

1.8

oscillator output

voltage

AVOL pin

V_i

input voltage

Mute level, with respect

to V_SS2

0.77

2.74

0.8

2.8

0.83

2.86

0 dB level with respect

to V_SS2

I_I

input current

µA

TFA9812_2

Preliminary data sheet

Rev. 02 — 22 January 2009

45 of 66

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TFA9812

NXP Semiconductors

BTL stereo Class-D audio ampliﬁer with I²S input

Table 55. DC characteristics …continued

Unless speciﬁed otherwise, V_DDA= V_DDP= 12 V, V_SSP1= V_SSP2= 0 V, V_DDA(3V3)= V_DDD(3V3)= 3.3 V,

_SS1= V_SS2= REFD = REFA = 0 V, T_amb= 25 °C, R_L= 8 Ω, f_i= 1 kHz, f_s= 44.1 kHz, f_sw= 400 kHz, 24-bit I²S input data,

MCLK clock mode, typical application diagram (Figure 13).

Symbol

Thermal Foldback (TF)

T_{act(th_fold)}thermal foldback

Parameter

Condition

Min

Typ

Max

Unit

118

125

132

°C

activation

temperature

OverTemperature Protection (OTP)

T_{act(th_prot)}

thermal protection

activation

temperature

160

°C

OverVoltage Protection (OVP)

V_P(ovp)

overvoltage

protection supply

voltage

22.3

UnderVoltage Protections (UVP)

V_P(uvp)

undervoltage

protection supply

voltage

UVP on V_DDA

7.5

2.2

UVP on V_DDA(3V3)

1.6

3.0

OverCurrent Protection (OCP)

[3]

I_O(ocp)

overcurrent

protection output

current

3.0

3.3

3.6

Window Protection (WP)

V_ooutput voltage

high level

low level

V_DDA− 1

REFA + 1

OverFrequency Protection (OFP)

[4]

f_OFP

Overfrequency

protection frequency

At PLL output frequency

100

140

185

MHz

UnderFrequency Protection (OFP)

f_UFP

Underfrequency

protection frequency

[1] I_Pis the current through the analog supply voltage (V_DDA) pin added to the current through the power supply voltage (V_DDP) pin.

[2] Thermal foldback temperature sensor is not located at hottest spot. Hottest spot is 12 °C higher.

[3] Current limiting concept: in overcurrent condition no interruption of the audio signal in case of impedance drop.

[4] PLL output frequency not external available.

TFA9812_2

Preliminary data sheet

Rev. 02 — 22 January 2009

46 of 66

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TFA9812

NXP Semiconductors

BTL stereo Class-D audio ampliﬁer with I²S input

13.2 AC characteristics

Table 56. AC characteristics

Unless speciﬁed otherwise, V_DDA= V_DDP= 12 V, V_DDA(3V3)= V_DDD(3V3)= 3.3 V, T_amb= 25 °C, R_s< 0.1 Ω^[1], R_L= 8 Ω,

f_i= 1 kHz, f_s= 44.1 kHz, f_sw= 400 kHz, 24-bit I²S input data, MCLK clock mode, typical application diagram (Figure 13).

Symbol Parameter

Condition

Min. Typ. Max. Unit

Output power per channel

P_o(RMS)

RMS output power

Continuous time output power per channel; THD = 1 %, R_L= 6 Ω

V_DDA= V_DDP= 12 V

V_DDA= V_DDP= 15 V

7.9

Continuous time output power per channel; THD = 10 %, R_L= 6 Ω

V_DDA= V_DDP= 12 V 9.7

Short time (≤ 10 s) output power per channel; THD = 10 %, R_L= 6 Ω

V_DDA= V_DDP= 15 V

Continuous time output power per channel; THD = 1 %, R_L= 8 Ω

V_DDA= V_DDP= 12 V

V_DDA= V_DDP= 15 V

6.6

Continuous time output power per channel; THD = 10 %, R_L= 8 Ω

V_DDA= V_DDP= 12 V

V_DDA= V_DDP= 13.5 V

V_DDA= V_DDP= 15 V

8.3

Short time (≤ 10 s) output power per channel; THD = 10 %, R_L= 8 Ω

V_DDA= V_DDP= 17 V

Performance

THD+N

total harmonic

P_O= 1 W; AES17 brick wall ﬁlter

V_O= 10 V; A-weighted

0.07 0.1

distortion-plus-noise

signal-to-noise ratio

output noise voltage

S/N

103

V_n(o)

MCLK clock jitter < 200 ps; AES17 brick-wall ﬁlter

operating mode

soft mute mode

hard mute mode

µV

α_cs

channel separation

P_o(RMS)= 1 W; aggressor channel:

f_i= 1 kHz

SVRR

supply voltage ripple rejection

output power efﬁciency

V_ripple= 2 V_pp; f_ripple= 100 Hz

R_L= 8 Ω; P_o(RMS)= 8.3 W

R_L= 6 Ω; P_o(RMS)= 9.7 W

η_po

Power-up times and delay times

t_d(on)

turn-on delay time

155 ms

TFA9812_2

Preliminary data sheet

Rev. 02 — 22 January 2009

47 of 66

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TFA9812

NXP Semiconductors

BTL stereo Class-D audio ampliﬁer with I²S input

Table 56. AC characteristics …continued

Unless speciﬁed otherwise, V_DDA= V_DDP= 12 V, V_DDA(3V3)= V_DDD(3V3)= 3.3 V, T_amb= 25 °C, R_s< 0.1 Ω^[1], R_L= 8 Ω,

f_i= 1 kHz, f_s= 44.1 kHz, f_sw= 400 kHz, 24-bit I²S input data, MCLK clock mode, typical application diagram (Figure 13).

Symbol Parameter

Condition

f_s=

Min. Typ. Max. Unit

t_PD

propagation delay

8 kHz

3.6

µs

11.025 kHz

12 kHz

2.58

2.39

1.78

1.3

16 kHz

22.05 kHz

24 kHz

1.18

892

664

600

458

320

306

67.2

32 kHz

44.1 kHz

48 kHz

64 kHz

88.2 kHz

96 kHz

128 kHz

176.4 kHz

192 kHz

40.8

PWM output

t_r

rise time

I_O= 0 A

Ω

t_f

fall time

t_w(min)

R_DSon

minimum pulse width

drain-source on-state resistance

per output MOSFET, for low and high

side

0.28 0.35

δ_max

maximum duty factor

0.96

[1] R_sis the series resistance of inductor of low-pass LC ﬁlter in the application.

[2] Output power measured across the loudspeaker load. This is based on indirect measurement of R_DSon

13.3 Timing

Table 57. Characteristics I²C bus interface; see Figure 10

V_DDD(3V3)= V_DDA(3V3)= 2.7 V to 3.6 V; V_DDA= V_DDP= 8 V to 20 V;T_amb= −20 °C to +85 °C; all voltages referenced to ground;

unless otherwise speciﬁed.

Symbol

f_SCL

Parameter

Conditions

Min

Typ

Max

Unit

kHz

µs

SCL clock frequency

LOW period of the SCL clock

HIGH period of the SCL clock

rise time

400

t_LOW

t_HIGH

t_r

1.3

0.6

µs