NEC Network Card PD78052 User Manual

User’s Manual  
µPD78054, 78054Y SUBSERIES  
8-BIT SINGLE-CHIP MICROCONTROLLERS  
µPD78052  
µPD78052Y  
µPD78053Y  
µPD78054Y  
µPD78055Y  
µPD78056Y  
µPD78058Y  
µPD78P058Y  
µPD78053  
µPD78054  
µPD78P054  
µPD78055  
µPD78056  
µPD78058  
µPD78P058  
µPD78052(A)  
µPD78053(A)  
µPD78054(A)  
Document No. U11747EJ5V0UM00 (5th edition)  
Date Published April 1998 N CP (K)  
©
1992  
Printed in Japan  
Download from Www.Somanuals.com. All Manuals Search And Download.  
NOTES FOR CMOS DEVICES  
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS  
Note:  
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and  
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity  
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control  
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using  
insulators that easily build static electricity. Semiconductor devices must be stored and transported  
in an anti-static container, static shielding bag or conductive material. All test and measurement  
tools including work bench and floor should be grounded. The operator should be grounded using  
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need  
to be taken for PW boards with semiconductor devices on it.  
2
HANDLING OF UNUSED INPUT PINS FOR CMOS  
Note:  
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided  
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence  
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels  
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused  
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of  
being an output pin. All handling related to the unused pins must be judged device by device and  
related specifications governing the devices.  
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Note:  
Power-on does not necessarily define initial status of MOS device. Production process of MOS  
does not define the initial operation status of the device. Immediately after the power source is  
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does  
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the  
reset signal is received. Reset operation must be executed immediately after power-on for devices  
having reset function.  
3
Download from Www.Somanuals.com. All Manuals Search And Download.  
FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation.  
MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft  
Corporation in the United States and/or other countries.  
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.  
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.  
SPARCstation is a trademark of SPARC International, Inc.  
Sun OS is a trademark of Sun Microsystems, Inc.  
Ethernet is a trademark of XEROX Corporation.  
NEWS and NEWS-OS are trademarks of SONY Corporation.  
OSF/Motif is a trademark of Open Software Foundation, Inc.  
TRON is an abbreviation of The Realtime Operating system Nucleus.  
ITRON is an abbreviation of Industrial TRON.  
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these  
products may be prohibited without governmental license. To export or re-export some or all of these products from a  
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales  
representative.  
License not needed: µPD78P054KK-T, 78P058KK-T, 78P058YKK-T  
The customer must judge the need for license:  
µPD78052GC-×××-8BT, 78052GK-×××-BE9, 78052YGC-×××-8BT  
µPD78053GC-×××-8BT, 78053GK-×××-BE9, 78053YGC-×××-8BT  
µPD78054GC-×××-8BT, 78054GK-×××-BE9, 78054YGC-×××-8BT  
µPD78P054GC-3B9, 78P054GC-8BT, 78P054GK-BE9  
µPD78055GC-×××-8BT, 78055GK-×××-BE9, 78055YGC-×××-8BT  
µPD78056GC-×××-8BT, 78056GK-×××-BE9, 78056YGC-×××-8BT  
µPD78058GC-×××-8BT, 78058GK-×××-BE9, 78058YGC-×××-8BT  
µPD78P058GC-8BT, 78P058YGC-8BT  
µPD78052GC(A)-×××-3B9, 78053GC(A)-×××-3B9, 78054GC(A)-×××-3B9  
4
Download from Www.Somanuals.com. All Manuals Search And Download.  
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.  
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these  
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined  
by Philips.  
The information in this document is subject to change without notice.  
No part of this document may be copied or reproduced in any form or by any means without the prior written  
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in  
this document.  
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property  
rights of third parties by or arising from use of a device described herein or any other liability arising from use  
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other  
intellectual property rights of NEC Corporation or others.  
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,  
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or  
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety  
measures in its design, such as redundancy, fire-containment, and anti-failure features.  
NEC devices are classified into the following three quality grades:  
“Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a  
customer designated “quality assurance program” for a specific application. The recommended applications of  
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device  
before using it in a particular application.  
Standard: Computers, office equipment, communications equipment, test and measurement equipment,  
audio and visual equipment, home electronic appliances, machine tools, personal electronic  
equipment and industrial robots  
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster  
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed  
for life support)  
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life  
support systems or medical equipment for life support, etc.  
The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books.  
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,  
they should contact an NEC sales representative in advance.  
Anti-radioactive design is not implemented in this product.  
M7 96.5  
5
Download from Www.Somanuals.com. All Manuals Search And Download.  
Regional Information  
Some information contained in this document may vary from country to country. Before using any NEC  
product in your application, pIease contact the NEC office in your country to obtain a list of authorized  
representatives and distributors. They will verify:  
Device availability  
Ordering information  
Product release schedule  
Availability of related technical literature  
Development environment specifications (for example, specifications for third-party tools and  
components, host computers, power plugs, AC supply voltages, and so forth)  
Network requirements  
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary  
from country to country.  
NEC Electronics Inc. (U.S.)  
Santa Clara, California  
Tel: 408-588-6000  
800-366-9782  
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.  
Benelux Office  
Hong Kong  
Eindhoven, The Netherlands  
Tel: 040-2445845  
Tel: 2886-9318  
Fax: 2886-9022/9044  
Fax: 408-588-6130  
800-729-9288  
Fax: 040-2444580  
NEC Electronics Hong Kong Ltd.  
Seoul Branch  
Seoul, Korea  
Tel: 02-528-0303  
Fax: 02-528-4411  
NEC Electronics (France) S.A.  
Velizy-Villacoublay, France  
Tel: 01-30-67 58 00  
NEC Electronics (Germany) GmbH  
Duesseldorf, Germany  
Tel: 0211-65 03 02  
Fax: 01-30-67 58 99  
Fax: 0211-65 03 490  
NEC Electronics Singapore Pte. Ltd.  
United Square, Singapore 1130  
Tel: 65-253-8311  
NEC Electronics (France) S.A.  
Spain Office  
Madrid, Spain  
NEC Electronics (UK) Ltd.  
Milton Keynes, UK  
Tel: 01908-691-133  
Fax: 65-250-3583  
Tel: 01-504-2787  
Fax: 01908-670-290  
Fax: 01-504-2860  
NEC Electronics Taiwan Ltd.  
Taipei, Taiwan  
Tel: 02-719-2377  
NEC Electronics Italiana s.r.1.  
Milano, Italy  
Tel: 02-66 75 41  
NEC Electronics (Germany) GmbH  
Scandinavia Office  
Taeby, Sweden  
Fax: 02-719-5951  
Fax: 02-66 75 42 99  
Tel: 08-63 80 820  
NEC do Brasil S.A.  
Cumbica-Guarulhos-SP, Brasil  
Tel: 011-6465-6810  
Fax: 08-63 80 388  
Fax: 011-6465-6829  
J98. 2  
6
Download from Www.Somanuals.com. All Manuals Search And Download.  
Major Revisions in This Edition  
Page  
Description  
Throughout  
Addition of µPD78052(A),78053(A), 78054(A) to the applicable types  
Deletion of µPD78P054Y from the applicable types  
Deletion of the following package from the µPD78052, 78053, 78054, 78055, 78056, 78058, 78P058, 78054Y  
Subseries:  
• 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)  
p. 233  
Addition of Figure 9-10. Square-Wave Output Operation Timing  
Addition of Figure 9-13. Square-Wave Output Operation Timing  
Addition of Note to Figure 16-4. Serial Operating Mode Register 0 Format  
p. 238  
p. 296  
p. 430, 435  
Addition of (4) Synchronization control and (5) Automatic transmit/receive Interval time to 18.4.3 3-wire  
serial I/O mode operation with automatic transmit/receive function  
p. 439  
Addition of precaution to 19.1 (3) 3-wire serial I/O mode (MSB-/LSB-first switchable)  
Change of Figure 19-3. Serial Operating Mode Register 2 Format  
Change of Table 19-2. Serial Interface Channel 2 Operating Mode Settings  
Correction of Figure 19-10. Receive Error Timing  
p. 444  
p. 446  
p. 465  
p. 474  
Addition of 19.4.4 Limitations when UART mode is used  
p. 577, 578  
Addition of APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND µPD78058F,  
78058FY SUBSERIES  
p. 579 to  
592  
APPENDIX B DEVELOPMENT TOOL  
Entire revision: Support for in-circuit emulator IE-78K0-NS  
p. 593, 594  
APPENDIX C EMBEDDED SOFTWARE  
Entire revision: Deletion of fuzzy inference development support system  
The mark shows major revised points.  
7
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
8
Download from Www.Somanuals.com. All Manuals Search And Download.  
PREFACE  
Readers  
This manual has been prepared for user engineers who want to understand the  
functions of the µPD78054 and 78054Y Subseries and design and develop its  
application systems and programs.  
The target products are the products of the following subseries.  
µPD78054 Subseries : µPD78052, 78053, 78054, 78P054, 78055, 78056,  
µPD78058, 78P058, 78052(A), 78053(A), 78054(A)  
µPD78054Y Subseries : µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y,  
µPD78058Y, 78P058Y  
Caution  
Of the above members, the following devices with the suffix KK-T should be  
usedonlyforexperimentorfunctionevaluation, becausetheyarenotintended  
for use in equipment that will be mass-produced and require high reliability.  
µPD78P054KK-T, 78P058KK-T, 78P058YKK-T  
Purpose  
This manual is intended for users to understand the functions described in the  
Organization below.  
Organization  
The µPD78054, 78054Y Subseries manual is separated into two parts: this manual  
and the instruction edition (common to the 78K/0 Series).  
µPD78054, 78054Y  
Subseries  
78K/0 Series  
User’s Manual  
Instruction  
User’s Manual  
(This manual)  
Pin functions  
CPU functions  
Internal block functions  
Interrupt  
Instruction set  
Explanation of each instruction  
Other on-chip peripheral functions  
9
Download from Www.Somanuals.com. All Manuals Search And Download.  
How to Read This Manual  
Before reading this manual, you should have general knowledge of electric and logic  
circuits and microcontrollers.  
For users who use this document as the manual for the µPD78052(A), 78053(A),  
and 78054(A):  
The only differences between the µPD78052, 78053, and 78054 and the  
µPD78052(A), 78053(A), 78054(A) are the quality grades and packages. (refer  
to 1.9 Differences between Standard Quality Grade Products and (A) Products).  
For the (A) products, read the part numbers in the following manner.  
µPD78052 µPD78052(A)  
µPD78053 µPD78053(A)  
µPD78054 µPD78054(A)  
When you want to understand the functions in general:  
Read this manual in the order of the contents.  
To know the µPD78054 and 78054Y Subseries instruction function in detail:  
Refer to the 78K/0 Series User's Manual: Instructions (U12326E)  
How to interpret the register format:  
For the circled bit number, the bit name is defined as a reserved word in  
RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h.  
To learn the function of a register whose register name is known:  
Refer to Appendix D Register Index.  
To know the electrical specifications of the µPD78054 and 78054Y Subseries:  
Refer to separately available Data Sheet.  
To know application examples of the functions provided in the µPD78054 and  
78054Y Subseries:  
Refer to Application Note separately provided.  
Caution  
The application examples in this manual are created for “Standard” quality  
grade products for general electric equipment. When using the application  
examples in this manual for purposes which require “Special” quality grades,  
thoroughly examine the quality grade of each part and circuit actually used.  
10  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Chapter Organization: This manual divides the descriptions for the µPD78054 and 78054Y Subseries into different  
chapters as shown below. Read only the chapters related to the device you use.  
µPD78054  
µPD78054Y  
Chapter  
Subseries  
Subseries  
Chapter 1  
Chapter 2  
Chapter 3  
Chapter 4  
Chapter 5  
Chapter 6  
Outline (µPD78054 Subseries)  
Outline (µPD78054Y Subseries)  
Pin Function (µPD78054 Subseries)  
Pin Function (µPD78054Y Subseries)  
CPU Architecture  
Port Functions  
Chapter 7  
Chapter 8  
Chapter 9  
Clock Generator  
16-Bit Timer/Event Counter  
8-Bit Timer/Event Counters 1 and 2  
Chapter 10 Watch Timer  
Chapter 11 Watchdog Timer  
Chapter 12 Clock Output Control Circuit  
Chapter 13 Buzzer Output Control Circuit  
Chapter 14 A/D Converter  
Chapter 15 D/A Converter  
Chapter 16 Serial Interface Channel 0 (µPD78054 Subseries)  
Chapter 17 Serial Interface Channel 0 (µPD78054Y Subseries)  
Chapter 18 Serial Interface Channel 1  
Chapter 19 Serial Interface Channel 2  
Chapter 20 Real-Time Output Port  
Chapter 21 Interrupt and Test Functions  
Chapter 22 External Device Expansion Function  
Chapter 23 Standby Function  
Chapter 24 Reset Function  
Chapter 25 ROM Correction  
Chapter 26 µPD78P054, µPD78P058  
Chapter 27 Instruction Set  
11  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Differences between µPD78054 and µPD78054Y Subseries:  
The µPD78054 and µPD78054Y Subseries are different in the following functions  
of the serial interface channel 0.  
Modes of serial interface channel 0  
µPD78054  
µPD78054Y  
Subseries  
Subseries  
3-wire serial I/O mode  
2-wire serial I/O mode  
SBI (serial bus interface) mode  
I2C (Inter IC) bus mode  
: Supported  
— : Not supported  
Legend  
Data significant  
:
:
:
:
:
:
Left: higher digit, right: lower digit  
××× (top bar over pin or signal name)  
Footnote  
Active low  
Note  
Caution  
Important information  
Supplement  
Remark  
Numerical notation  
Binary ... ×××× or ××××B  
Decimal ... ××××  
Hexadecimal ... ××××H  
12  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Related Documents  
The related documents indicated in this publication may include preliminary  
versions. However, preliminary versions are not marked as such.  
Related documents for µPD78054 Subseries  
Document No.  
Japanese English  
U12327J  
Document name  
µPD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet  
µPD78052(A), 78053(A), 78054(A) Data Sheet  
µPD78P054, 78P058 Data Sheet  
U12327E  
U12171E  
U10417E  
This manual  
U12326E  
U12171J  
U10417J  
U11747J  
U12326J  
U10903J  
U10904J  
U10102J  
U10182J  
IEA-718  
µPD78054, 78054Y Subseries User’s Manual  
78K/0 Series User’s Manual, Instruction  
78K/0 Series Instruction Table  
78K/0 Series Instruction Set  
µPD78054 Subseries Special Function Register Table  
78K/0 Series Application Note  
Basics (III)  
Floating-point operation program  
U10182E  
IEA-1289  
Related documents for µPD78054Y Subseries  
Document No.  
Document name  
Japanese  
English  
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y Data Sheet  
U10906J  
U10906E  
µPD78P058Y Data Sheet  
U10907J  
U11747J  
U12326J  
U10907E  
µPD78054, 78054Y Subseries User’s Manual  
78K/0 Series User’s Manual, Instruction  
This manual  
U12326E  
78K/0 Series Instruction Table  
U10903J  
U10904J  
U10087J  
U10182J  
78K/0 Series Instruction Set  
µPD78054Y Subseries Special Function Register Table  
78K/0 Series Application Note  
Basics (III)  
U10182E  
Caution The above documents are subject to change without prior notice. Be sure to use the latest version  
document when starting design.  
13  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Development Tool Documents (User’s Manuals)  
Document No.  
Japanese English  
Document name  
RA78K0 Assembler Package  
Operation  
U11802J  
U11802E  
U11801E  
U11789E  
EEU-1402  
U11517E  
U11518E  
EEA-1208  
Assembly Language  
Structured Assembly  
U11801J  
U11789J  
U12323J  
U11517J  
U11518J  
U13034J  
U12322J  
U11940J  
EEU-704  
RA78K Series Structured Assembler Preprocessor  
CC78K0 C Compiler  
Operation  
Language  
CC78K0 C Compiler Application Note  
CC78K Series Library Source File  
PG-1500 PROM Programmer  
Programming know-how  
U11940E  
EEU-1291  
PG-1500 Controller PC-9800 Series (MS-DOS™) Base  
PG-1500 Controller IBM PC Series (PC DOS™) Base  
IE-78K0-NS  
EEU-5008  
U10540E  
To be prepared  
To be prepared  
IE-78001-R-A  
To be prepared  
To be prepared  
To be prepared  
To be prepared  
IE-780308-NS-EM1  
IE-780308-R-EM  
U11362J  
EEU-985  
EEU-932  
U10181J  
U10092J  
U11362E  
EEU-1515  
EEU-1468  
U10181E  
U10092E  
EP-78230  
EP-78054GK-R  
SM78K0 System Simulator Windows™ Base  
SM78K Series System Simulator  
Reference  
External component user  
open interface specifications  
ID78K0-NS Integrated Debugger  
Reference  
U12900J  
To be prepared  
ID78K0 Integrated Debugger EWS Base  
ID78K0 Integrated Debugger PC Base  
ID78K0 Integrated Debugger Windows Base  
Reference  
Reference  
Guide  
U11151J  
U11539J  
U11649J  
U11539E  
U11649E  
Caution The above documents are subject to change without prior notice. Be sure to use the latest version  
document when starting design.  
14  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Documents for Embedded Software  
(User’s Manual)  
Document No.  
Japanese English  
Document name  
78K/0 Series Real-Time OS  
OS for 78K/0 Series MX78K0  
Basics  
U11537J  
U11537E  
U11536E  
U12257E  
Installation  
Basics  
U11536J  
U12257J  
Other Documents  
Document No.  
Document name  
Japanese  
English  
IC PACKAGE MANUAL  
C10943X  
C10535J  
Semiconductor Device Mounting Technology Manual  
Quality Grade on NEC Semiconductor Devices  
C10535E  
C11531J  
C10983J  
C11892J  
C11531E  
C10983E  
C11892E  
MEI-1202  
NEC Semiconductor Device Reliability/Quality Control System  
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)  
Guide to Quality Assurance for Semiconductor Devices  
Microcontroller Related Product Guide—Third Party Manufacturers  
U11416J  
Caution The above documents are subject to change without prior notice. Be sure to use the latest version  
document when starting design.  
15  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
16  
Download from Www.Somanuals.com. All Manuals Search And Download.  
TABLE OF CONTENTS  
CHAPTER 1 GENERAL (µPD78054 Subseries) ............................................................................  
1.1 Features .............................................................................................................................  
1.2 Applications ......................................................................................................................  
1.3 Ordering Information ........................................................................................................  
1.4 Quality Grade ....................................................................................................................  
1.5 Pin Configuration (Top View) ...........................................................................................  
1.6 78K/0 Series Expansion ...................................................................................................  
1.7 Block Diagram ...................................................................................................................  
1.8 Outline of Function ...........................................................................................................  
1.9 Differences between Standard Quality Grade Products and (A) Products .................  
1.10 Mask Options ....................................................................................................................  
37  
37  
38  
38  
39  
40  
43  
45  
46  
48  
48  
CHAPTER 2 GENERAL (µPD78054Y Subseries) ..........................................................................  
2.1 Features .............................................................................................................................  
2.2 Applications ......................................................................................................................  
2.3 Ordering Information ........................................................................................................  
2.4 Quality Grade ....................................................................................................................  
2.5 Pin Configuration (Top View) ...........................................................................................  
2.6 78K/0 Series Expansion ...................................................................................................  
2.7 Block Diagram ...................................................................................................................  
2.8 Outline of Function ...........................................................................................................  
2.9 Mask Options ....................................................................................................................  
49  
49  
50  
50  
50  
51  
54  
56  
57  
58  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries) ....................................................................  
59  
59  
59  
63  
64  
64  
65  
65  
66  
67  
67  
67  
68  
69  
69  
69  
69  
70  
70  
70  
70  
70  
3.1 Pin Function List ...............................................................................................................  
3.1.1  
3.1.2  
Normal operating mode pins ...............................................................................................  
PROM programming mode pins (PROM versions only) ......................................................  
3.2 Description of Pin Functions ...........................................................................................  
3.2.1  
3.2.2  
3.2.3  
3.2.4  
3.2.5  
3.2.6  
3.2.7  
3.2.8  
3.2.9  
P00 to P07 (Port 0) ..............................................................................................................  
P10 to P17 (Port 1) ..............................................................................................................  
P20 to P27 (Port 2) ..............................................................................................................  
P30 to P37 (Port 3) ..............................................................................................................  
P40 to P47 (Port 4) ..............................................................................................................  
P50 to P57 (Port 5) ..............................................................................................................  
P60 to P67 (Port 6) ..............................................................................................................  
P70 to P72 (Port 7) ..............................................................................................................  
P120 to P127 (Port 12) ........................................................................................................  
3.2.10 P130 and P131 (Port 13) .....................................................................................................  
3.2.11 AVREF0 ..................................................................................................................................  
3.2.12 AVREF1 ..................................................................................................................................  
3.2.13 AVDD .....................................................................................................................................  
3.2.14 AVSS .....................................................................................................................................  
3.2.15 RESET .................................................................................................................................  
3.2.16 X1 and X2 ............................................................................................................................  
3.2.17 XT1 and XT2 .......................................................................................................................  
17  
Download from Www.Somanuals.com. All Manuals Search And Download.  
3.2.18 VDD .......................................................................................................................................  
3.2.19 VSS .......................................................................................................................................  
3.2.20 VPP (PROM versions only) ...................................................................................................  
3.2.21 IC (Mask ROM version only)................................................................................................  
3.3 Input/output Circuits and Recommended Connection of Unused Pins ......................  
70  
70  
70  
70  
71  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries) ..................................................................  
75  
75  
75  
79  
80  
80  
81  
81  
82  
82  
83  
83  
84  
84  
85  
85  
85  
85  
85  
85  
86  
86  
86  
86  
86  
86  
87  
4.1 Pin Function List ...............................................................................................................  
4.1.1  
4.1.2  
Normal operating mode pins ...............................................................................................  
PROM programming mode pins (PROM versions only) ......................................................  
4.2 Description of Pin Functions ...........................................................................................  
4.2.1  
4.2.2  
4.2.3  
4.2.4  
4.2.5  
4.2.6  
4.2.7  
4.2.8  
4.2.9  
P00 to P07 (Port 0) ..............................................................................................................  
P10 to P17 (Port 1) ..............................................................................................................  
P20 to P27 (Port 2) ..............................................................................................................  
P30 to P37 (Port 3) ..............................................................................................................  
P40 to P47 (Port 4) ..............................................................................................................  
P50 to P57 (Port 5) ..............................................................................................................  
P60 to P67 (Port 6) ..............................................................................................................  
P70 to P72 (Port 7) ..............................................................................................................  
P120 to P127 (Port 12) ........................................................................................................  
4.2.10 P130 and P131 (Port 13) .....................................................................................................  
4.2.11 AVREF0 ..................................................................................................................................  
4.2.12 AVREF1 ..................................................................................................................................  
4.2.13 AVDD .....................................................................................................................................  
4.2.14 AVSS .....................................................................................................................................  
4.2.15 RESET .................................................................................................................................  
4.2.16 X1 and X2 ............................................................................................................................  
4.2.17 XT1 and XT2 .......................................................................................................................  
4.2.18 VDD .......................................................................................................................................  
4.2.19 VSS .......................................................................................................................................  
4.2.20 VPP (PROM versions only) ...................................................................................................  
4.2.21 IC (Mask ROM version only)................................................................................................  
4.3 Input/output Circuits and Recommended Connection of Unused Pins ......................  
CHAPTER 5 CPU ARCHITECTURE................................................................................................  
5.1 Memory Spaces.................................................................................................................  
91  
91  
5.1.1  
5.1.2  
5.1.3  
5.1.4  
5.1.5  
Internal program memory space..........................................................................................  
Internal data memory space ................................................................................................  
Special Function Register (SFR) area .................................................................................  
External memory space .......................................................................................................  
Data memory addressing ....................................................................................................  
99  
100  
100  
100  
101  
5.2 Processor Registers ......................................................................................................... 109  
5.2.1  
5.2.2  
5.2.3  
Control registers ..................................................................................................................  
General registers .................................................................................................................  
Special Function Register (SFR) .........................................................................................  
109  
112  
114  
118  
118  
119  
5.3 Instruction Address Addressing .....................................................................................  
5.3.1  
5.3.2  
Relative addressing .............................................................................................................  
Immediate addressing .........................................................................................................  
18  
Download from Www.Somanuals.com. All Manuals Search And Download.  
5.3.3  
5.3.4  
Table indirect addressing .....................................................................................................  
Register addressing .............................................................................................................  
120  
120  
5.4 Operand Address Addressing ......................................................................................... 121  
5.4.1  
5.4.2  
5.4.3  
5.4.4  
5.4.5  
5.4.6  
5.4.7  
5.4.8  
5.4.9  
Implied addressing ..............................................................................................................  
Register addressing .............................................................................................................  
Direct addressing.................................................................................................................  
Short direct addressing ........................................................................................................  
Special-Function Register (SFR) addressing ......................................................................  
Register indirect addressing ................................................................................................  
Based addressing ................................................................................................................  
Based indexed addressing ..................................................................................................  
Stack addressing .................................................................................................................  
121  
122  
123  
124  
125  
126  
127  
128  
128  
CHAPTER 6 PORT FUNCTIONS .................................................................................................... 129  
6.1 Port Functions................................................................................................................... 129  
6.2 Port Configuration ............................................................................................................ 134  
6.2.1  
6.2.2  
6.2.3  
6.2.4  
6.2.5  
6.2.6  
6.2.7  
6.2.8  
6.2.9  
Port 0 ...................................................................................................................................  
Port 1 ...................................................................................................................................  
Port 2 (µPD78054 Subseries)..............................................................................................  
Port 2 (µPD78054Y Subseries) ...........................................................................................  
Port 3 ...................................................................................................................................  
Port 4 ...................................................................................................................................  
Port 5 ...................................................................................................................................  
Port 6 ...................................................................................................................................  
Port 7 ...................................................................................................................................  
134  
136  
137  
139  
141  
142  
143  
144  
146  
148  
149  
6.2.10 Port 12 .................................................................................................................................  
6.2.11 Port 13 .................................................................................................................................  
6.3 Port Function Control Registers ..................................................................................... 150  
6.4 Port Function Operations.................................................................................................  
156  
156  
156  
157  
157  
6.4.1  
6.4.2  
6.4.3  
Writing to input/output port...................................................................................................  
Reading from input/output port ............................................................................................  
Operations on input/output port ...........................................................................................  
6.5 Selection of Mask Option .................................................................................................  
CHAPTER 7 CLOCK GENERATOR ................................................................................................ 159  
7.1 Clock Generator Functions .............................................................................................. 159  
7.2 Clock Generator Configuration ....................................................................................... 159  
7.3 Clock Generator Control Register ...................................................................................  
161  
7.4 System Clock Oscillator ................................................................................................... 165  
7.4.1  
7.4.2  
7.4.3  
7.4.4  
Main system clock oscillator ................................................................................................  
Subsystem clock oscillator ..................................................................................................  
Scaler...................................................................................................................................  
When no subsystem clocks are used ..................................................................................  
165  
166  
168  
168  
7.5 Clock Generator Operations ............................................................................................ 169  
7.5.1  
7.5.2  
Main system clock operations .............................................................................................  
Subsystem clock operations ................................................................................................  
170  
171  
171  
171  
173  
7.6 Changing System Clock and CPU Clock Settings.........................................................  
7.6.1  
7.6.2  
Time required for switchover between system clock and CPU clock ..................................  
System clock and CPU clock switching procedure ..............................................................  
19  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER .............................................................................  
8.1 Outline of Timers Incorporated in the µPD78054, 78054Y Subseries ..........................  
8.2 16-Bit Timer/Event Counter Functions ...........................................................................  
175  
175  
177  
8.3 16-Bit Timer/Event Counter Configuration ..................................................................... 179  
8.4 16-Bit Timer/Event Counter Control Registers .............................................................. 182  
8.5 16-Bit Timer/Event Counter Operations.......................................................................... 191  
8.5.1  
8.5.2  
8.5.3  
8.5.4  
8.5.5  
8.5.6  
8.5.7  
Interval timer operations ......................................................................................................  
PWM output operations .......................................................................................................  
PPG output operations ........................................................................................................  
Pulse width measurement operations .................................................................................  
External event counter operation.........................................................................................  
Square-wave output operation ............................................................................................  
One-shot pulse output operation .........................................................................................  
191  
193  
196  
197  
204  
206  
208  
212  
8.6 16-Bit Timer/Event Counter Operating Precautions ......................................................  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 .............................................................. 215  
9.1 8-Bit Timer/Event Counters 1 and 2 Functions .............................................................. 215  
9.1.1  
9.1.2  
8-bit timer/event counter mode ............................................................................................  
16-bit timer/event counter mode ..........................................................................................  
215  
218  
220  
223  
228  
228  
234  
238  
9.2 8-Bit Timer/Event Counters 1 and 2 Configurations......................................................  
9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers .................................................  
9.4 8-Bit Timer/Event Counters 1 and 2 Operations ............................................................  
9.4.1  
9.4.2  
8-bit timer/event counter mode ............................................................................................  
16-bit timer/event counter mode ..........................................................................................  
9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2 ..........................................................  
CHAPTER 10 WATCH TIMER ........................................................................................................... 241  
10.1 Watch Timer Functions .................................................................................................... 241  
10.2 Watch Timer Configuration .............................................................................................. 242  
10.3 Watch Timer Control Registers ....................................................................................... 242  
10.4 Watch Timer Operations................................................................................................... 246  
10.4.1 Watch timer operation..........................................................................................................  
10.4.2 Interval timer operation ........................................................................................................  
246  
246  
CHAPTER 11 WATCHDOG TIMER ................................................................................................... 247  
11.1 Watchdog Timer Functions .............................................................................................. 247  
11.2 Watchdog Timer Configuration ....................................................................................... 249  
11.3 Watchdog Timer Control Registers ................................................................................. 250  
11.4 Watchdog Timer Operations ............................................................................................ 253  
11.4.1 Watchdog timer operation....................................................................................................  
11.4.2 Interval timer operation ........................................................................................................  
253  
254  
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT ..................................................................... 255  
12.1 Clock Output Control Circuit Functions ......................................................................... 255  
12.2 Clock Output Control Circuit Configuration................................................................... 256  
12.3 Clock Output Function Control Registers ......................................................................  
257  
20  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT....................................................................  
261  
261  
261  
262  
13.1  
13.2  
13.3  
Buzzer Output Control Circuit Functions .............................................................................  
Buzzer Output Control Circuit Configuration .......................................................................  
Buzzer Output Function Control Registers ..........................................................................  
CHAPTER 14 A/D CONVERTER.......................................................................................................  
265  
14.1 A/D Converter Functions.................................................................................................. 265  
14.2 A/D Converter Configuration ........................................................................................... 265  
14.3 A/D Converter Control Registers..................................................................................... 269  
14.4 A/D Converter Operations ................................................................................................ 273  
14.4.1 Basic operations of A/D converter .......................................................................................  
14.4.2 Input voltage and conversion results ...................................................................................  
14.4.3 A/D converter operating mode .............................................................................................  
273  
275  
276  
14.5 A/D Converter Cautions ................................................................................................... 278  
CHAPTER 15 D/A CONVERTER.......................................................................................................  
15.1 D/A Converter Functions.................................................................................................. 281  
15.2 D/A Converter Configuration ........................................................................................... 282  
15.3 D/A Converter Control Registers..................................................................................... 284  
15.4 Operations of D/A Converter ........................................................................................... 285  
15.5 Cautions Related to D/A Converter ................................................................................. 286  
281  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)......................................  
16.1 Serial Interface Channel 0 Functions ..............................................................................  
16.2 Serial Interface Channel 0 Configuration .......................................................................  
16.3 Serial Interface Channel 0 Control Registers.................................................................  
16.4 Serial Interface Channel 0 Operations ............................................................................  
16.4.1 Operation stop mode ...........................................................................................................  
16.4.2 3-wire serial I/O mode operation .........................................................................................  
16.4.3 SBI mode operation .............................................................................................................  
16.4.4 2-wire serial I/O mode operation .........................................................................................  
16.4.5 SCK0/P27 pin output manipulation ......................................................................................  
287  
288  
290  
294  
301  
301  
302  
307  
333  
339  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries) ...................................  
17.1 Serial Interface Channel 0 Functions ..............................................................................  
17.2 Serial Interface Channel 0 Configuration .......................................................................  
17.3 Serial Interface Channel 0 Control Registers.................................................................  
17.4 Serial Interface Channel 0 Operations ............................................................................  
17.4.1 Operation stop mode ...........................................................................................................  
17.4.2 3-wire serial I/O mode operation .........................................................................................  
17.4.3 2-wire serial I/O mode operation .........................................................................................  
17.4.4 I2C bus mode operation .......................................................................................................  
17.4.5 Cautions on use of I2C bus mode ........................................................................................  
17.4.6 Restrictions in I2C bus mode ...............................................................................................  
17.4.7 SCK0/SCL/P27 pin output manipulation..............................................................................  
341  
342  
344  
348  
356  
356  
357  
361  
367  
385  
388  
390  
21  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ............................................................................  
18.1 Serial Interface Channel 1 Functions ..............................................................................  
18.2 Serial Interface Channel 1 Configuration .......................................................................  
18.3 Serial Interface Channel 1 Control Registers.................................................................  
18.4 Serial Interface Channel 1 Operations ............................................................................  
18.4.1 Operation stop mode ...........................................................................................................  
18.4.2 3-wire serial I/O mode operation .........................................................................................  
18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function .........................  
393  
393  
394  
397  
405  
405  
406  
409  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ............................................................................  
19.1 Serial Interface Channel 2 Functions ..............................................................................  
19.2 Serial Interface Channel 2 Configuration .......................................................................  
19.3 Serial Interface Channel 2 Control Registers.................................................................  
19.4 Serial Interface Channel 2 Operation ..............................................................................  
19.4.1 Operation stop mode ...........................................................................................................  
19.4.2 Asynchronous serial interface (UART) mode ......................................................................  
19.4.3 3-wire serial I/O mode .........................................................................................................  
19.4.4 Limitations when UART mode is used .................................................................................  
439  
439  
440  
444  
452  
452  
454  
467  
474  
CHAPTER 20 REAL-TIME OUTPUT PORT ...................................................................................... 477  
20.1 Real-Time Output Port Functions....................................................................................  
20.2 Real-Time Output Port Configuration .............................................................................  
20.3 Real-Time Output Port Control Registers.......................................................................  
477  
478  
480  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS .......................................................................  
483  
21.1 Interrupt Function Types .................................................................................................. 483  
21.2 Interrupt Sources and Configuration ..............................................................................  
21.3 Interrupt Function Control Registers ..............................................................................  
484  
488  
21.4 Interrupt Servicing Operations ........................................................................................ 497  
21.4.1 Non-maskable interrupt request acknowledge operation ....................................................  
21.4.2 Maskable interrupt request acknowledge operation ............................................................  
21.4.3 Software interrupt request acknowledge operation .............................................................  
21.4.4 Multiple interrupt servicing ...................................................................................................  
21.4.5 Interrupt request reserve .....................................................................................................  
497  
500  
503  
503  
506  
21.5 Test Functions................................................................................................................... 507  
21.5.1 Registers controlling the test function..................................................................................  
21.5.2 Test input signal acknowledge operation .............................................................................  
507  
509  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION .........................................................  
22.1 External Device Expansion Functions............................................................................  
22.2 External Device Expansion Function Control Register.................................................  
22.3 External Device Expansion Function Timing .................................................................  
22.4 Example of Connection with Memory .............................................................................  
511  
511  
516  
518  
523  
CHAPTER 23 STANDBY FUNCTION ................................................................................................ 525  
23.1 Standby Function and Configuration..............................................................................  
23.1.1 Standby function ..................................................................................................................  
23.1.2 Standby function control register .........................................................................................  
525  
525  
526  
22  
Download from Www.Somanuals.com. All Manuals Search And Download.  
23.2 Standby Function Operations..........................................................................................  
23.2.1 HALT mode ..........................................................................................................................  
23.2.2 STOP mode .........................................................................................................................  
527  
527  
530  
CHAPTER 24 RESET FUNCTION ..................................................................................................... 533  
24.1 Reset Function .................................................................................................................. 533  
CHAPTER 25 ROM CORRECTION ................................................................................................... 537  
25.1 ROM Correction Functions .............................................................................................. 537  
25.2 ROM Correction Configuration ........................................................................................ 537  
25.3 ROM Correction Control Registers ................................................................................. 539  
25.4 ROM Correction Application ............................................................................................ 540  
25.5 ROM Correction Example.................................................................................................  
25.6 Program Execution Flow .................................................................................................. 544  
25.7 Cautions on ROM Correction........................................................................................... 546  
543  
CHAPTER 26 µPD78P054, 78P058 .................................................................................................. 547  
26.1 Memory Size Switching Register (µPD78P054).............................................................. 549  
26.2 Memory Size Switching Register (µPD78P058).............................................................. 550  
26.3 Internal Expansion RAM Size Switching Register .........................................................  
551  
26.4 PROM Programming ......................................................................................................... 552  
26.4.1 Operating modes .................................................................................................................  
26.4.2 PROM write procedure ........................................................................................................  
26.4.3 PROM reading procedure ....................................................................................................  
26.5 Erasure Procedure (µPD78P054KK-T and 78P058KK-T Only) ......................................  
26.6 Opaque Film Masking the Window (µPD78P054KK-T and 78P058KK-T Only)............  
552  
554  
558  
559  
559  
26.7 Screening of One-Time PROM Versions ......................................................................... 559  
CHAPTER 27 INSTRUCTION SET .................................................................................................... 561  
27.1 Legends Used in Operation List ...................................................................................... 562  
27.1.1 Operand identifiers and description methods ......................................................................  
27.1.2 Description of “operation” column ........................................................................................  
27.1.3 Description of “flag operation” column .................................................................................  
562  
563  
563  
27.2 Operation List.................................................................................................................... 564  
27.3 Instructions Listed by Addressing Type ......................................................................... 572  
APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND  
µPD78058F, 78058FY SUBSERIES ...........................................................................  
577  
APPENDIX B DEVELOPMENT TOOLS............................................................................................ 579  
B.1 Language Processing Software ...................................................................................... 582  
B.2 PROM Writing Tools ......................................................................................................... 584  
B.2.1  
B.2.2  
Hardware .............................................................................................................................  
Software...............................................................................................................................  
584  
584  
B.3 Debugging Tools ............................................................................................................... 585  
B.3.1  
B.3.2  
Hardware .............................................................................................................................  
Software...............................................................................................................................  
585  
587  
23  
Download from Www.Somanuals.com. All Manuals Search And Download.  
B.4 OS for IBM PC ................................................................................................................... 589  
B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A ..................  
APPENDIX C EMBEDDED SOFTWARE ..........................................................................................  
APPENDIX D REGISTER INDEX ......................................................................................................  
589  
593  
595  
D.1 Register Index ................................................................................................................... 595  
APPENDIX E REVISION HISTORY .................................................................................................. 599  
24  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (1/8)  
Figure No.  
3-1.  
Title  
Page  
73  
Pin Input/Output Circuit of List.......................................................................................................  
4-1.  
Pin Input/Output Circuit of List.......................................................................................................  
89  
5-1.  
Memory Map (µPD78052, 78052Y)...............................................................................................  
Memory Map (µPD78053, 78053Y)...............................................................................................  
Memory Map (µPD78054, 78054Y)...............................................................................................  
Memory Map (µPD78P054)...........................................................................................................  
Memory Map (µPD78055, 78055Y)...............................................................................................  
Memory Map (µPD78056, 78056Y)...............................................................................................  
Memory Map (µPD78058, 78058Y)...............................................................................................  
Memory Map (µPD78P058, µPD78P058Y)...................................................................................  
91  
92  
93  
94  
95  
96  
97  
98  
5-2.  
5-3.  
5-4.  
5-5.  
5-6.  
5-7.  
5-8.  
5-9.  
Data Memory Addressing (µPD78052, 78052Y) ........................................................................... 101  
Data Memory Addressing (µPD78053, 78053Y) ........................................................................... 102  
Data Memory Addressing (µPD78054, 78054Y) ........................................................................... 103  
Data Memory Addressing (µPD78P054) ....................................................................................... 104  
Data Memory Addressing (µPD78055, 78055Y) ........................................................................... 105  
Data Memory Addressing (µPD78056, 78056Y) ........................................................................... 106  
Data Memory Addressing (µPD78058, 78058Y) ........................................................................... 107  
Data Memory Addressing (µPD78P058, 78P058Y) ...................................................................... 108  
Program Counter Configuration .................................................................................................... 109  
Program Status Word Configuration ............................................................................................. 109  
Stack Pointer Configuration........................................................................................................... 111  
Data to be Saved to Stack Memory............................................................................................... 111  
Data to be Reset from Stack Memory ........................................................................................... 111  
General Register Configuration ..................................................................................................... 113  
5-10.  
5-11.  
5-12.  
5-13.  
5-14.  
5-15.  
5-16.  
5-17.  
5-18.  
5-19.  
5-20.  
5-21.  
5-22.  
6-1.  
Port Types ..................................................................................................................................... 129  
P00 and P07 Block Diagram ......................................................................................................... 135  
P01 to P06 Block Diagram ............................................................................................................ 135  
P10 to P17 Block Diagram ............................................................................................................ 136  
P20, P21, P23 to P26 Block Diagram ........................................................................................... 137  
P22 and P27 Block Diagram ......................................................................................................... 138  
P20, P21, P23 to P26 Block Diagram ........................................................................................... 139  
P22 and P27 Block Diagram ......................................................................................................... 140  
P30 to P37 Block Diagram ............................................................................................................ 141  
P40 to P47 Block Diagram ............................................................................................................ 142  
Block Diagram of Falling Edge Detection Circuit........................................................................... 142  
P50 to P57 Block Diagram ............................................................................................................ 143  
P60 to P63 Block Diagram ............................................................................................................ 145  
P64 to P67 Block Diagram ............................................................................................................ 145  
P70 Block Diagram........................................................................................................................ 146  
P71 and P72 Block Diagram ......................................................................................................... 147  
P120 to P127 Block Diagram ........................................................................................................ 148  
6-2.  
6-3.  
6-4.  
6-5.  
6-6.  
6-7.  
6-8.  
6-9.  
6-10.  
6-11.  
6-12.  
6-13.  
6-14.  
6-15.  
6-16.  
6-17.  
25  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (2/8)  
Figure No.  
Title  
Page  
6-18.  
6-19.  
6-20.  
6-21.  
6-22.  
P130 and P131 Block Diagram ..................................................................................................... 149  
Port Mode Register Format ........................................................................................................... 152  
Pull-Up Resistor Option Register Format ...................................................................................... 153  
Memory Expansion Mode Register Format ................................................................................... 154  
Key Return Mode Register Format................................................................................................ 155  
7-1.  
7-2.  
7-3.  
7-4.  
7-5.  
7-6.  
7-7.  
7-8.  
7-9.  
7-10.  
Block Diagram of Clock Generator ................................................................................................ 160  
Subsystem Clock Feedback Resistor............................................................................................ 161  
Processor Clock Control Register Format ..................................................................................... 162  
Oscillation Mode Selection Register Format ................................................................................. 164  
Main System Clock when Writing to OSMS .................................................................................. 164  
External Circuit of Main System Clock Oscillator .......................................................................... 165  
External Circuit of Subsystem Clock Oscillator ............................................................................. 166  
Examples of Incorrect Oscillator Connection ................................................................................ 166  
Main System Clock Stop Function ................................................................................................ 170  
System Clock and CPU Clock Switching ...................................................................................... 173  
8-1.  
16-Bit Timer/Event Counter Block Diagram................................................................................... 179  
16-Bit Timer/Event Counter Output Control Circuit Block Diagram ............................................... 180  
Timer Clock Selection Register 0 Format ...................................................................................... 183  
16-Bit Timer Mode Control Register Format.................................................................................. 185  
Capture/Compare Control Register 0 Format ............................................................................... 186  
16-Bit Timer Output Control Register Format ................................................................................ 187  
Port Mode Register 3 Format ........................................................................................................ 188  
External Interrupt Mode Register 0 Format ................................................................................... 189  
Sampling Clock Select Register Format........................................................................................ 190  
Control Register Settings for Interval Timer Operation.................................................................. 191  
Interval Timer Configuration Diagram............................................................................................ 192  
Interval Timer Operation Timings .................................................................................................. 192  
Control Register Settings for PWM Output Operation ................................................................... 194  
Example of D/A Converter Configuration with PWM Output ......................................................... 195  
TV Tuner Application Circuit Example ........................................................................................... 195  
Control Register Settings for PPG Output Operation .................................................................... 196  
Control Register Settings for Pulse Width Measurement with Free-Running Counter and  
8-2.  
8-3.  
8-4.  
8-5.  
8-6.  
8-7.  
8-8.  
8-9.  
8-10.  
8-11.  
8-12.  
8-13.  
8-14.  
8-15.  
8-16.  
8-17.  
One Capture Register ................................................................................................................... 197  
Configuration Diagram for Pulse Width Measurement by Free-Running Counter ........................ 198  
Timing of Pulse Width Measurement Operation by Free-Running Counter and  
8-18.  
8-19.  
One Capture Register (with Both Edges Specified) ...................................................................... 198  
Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ........ 199  
Timing of Pulse Width Measurement Operation with Free-Running Counter  
8-20.  
8-21.  
(with Both Edges Specified) .......................................................................................................... 200  
Control Register Settings for Pulse Width Measurement with Free-Running Counter and  
8-22.  
Two Capture Registers .................................................................................................................. 201  
26  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (3/8)  
Figure No.  
8-23.  
Title  
Page  
Timing of Pulse Width Measurement Operation by Free-Running Counter and  
Two Capture Registers (with Rising Edge Specified) .................................................................... 202  
Control Register Settings for Pulse Width Measurement by Means of Restart ............................. 203  
Timing of Pulse Width Measurement Operation by Means of Restart  
8-24.  
8-25.  
(with Rising Edge Specified) ......................................................................................................... 203  
Control Register Settings in External Event Counter Mode .......................................................... 204  
External Event Counter Configuration Diagram ............................................................................ 205  
External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 205  
Control Register Settings in Square-Wave Output Mode .............................................................. 206  
Square-Wave Output Operation Timing ........................................................................................ 207  
Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger............. 208  
Timing of One-Shot Pulse Output Operation Using Software Trigger ........................................... 209  
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger.............. 210  
Timing of One-Shot Pulse Output Operation Using External Trigger  
8-26.  
8-27.  
8-28.  
8-29.  
8-30.  
8-31.  
8-32.  
8-33.  
8-34.  
(With Rising Edge Specified)......................................................................................................... 211  
16-Bit Timer Register Start Timing ................................................................................................ 212  
Timings After Change of Compare Register During Timer Count Operation ................................. 212  
Capture Register Data Retention Timing....................................................................................... 213  
Operation Timing of OVF0 Flag..................................................................................................... 214  
8-35.  
8-36.  
8-37.  
8-38.  
9-1.  
8-Bit Timer/Event Counters 1 and 2 Block Diagram ...................................................................... 221  
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 .......................................... 222  
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 .......................................... 222  
Timer Clock Select Register 1 Format........................................................................................... 224  
8-Bit Timer Mode Control Register 1 Format................................................................................. 225  
8-Bit Timer Output Control Register Format .................................................................................. 226  
Port Mode Register 3 Format ........................................................................................................ 227  
Interval Timer Operation Timings .................................................................................................. 228  
External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 231  
Square-Wave Output Operation Timing ........................................................................................ 233  
Interval Timer Operation Timing .................................................................................................... 234  
External Event Counter Operation Timings (with Rising Edge Specified) ..................................... 236  
Square-Wave Output Operation Timing ........................................................................................ 238  
8-Bit Timer Registers 1 and 2 Start Timing.................................................................................... 238  
Event Counter Operation Timing ................................................................................................... 239  
Timing after Compare Register Change during Timer Count Operation ....................................... 239  
9-2.  
9-3.  
9-4.  
9-5.  
9-6.  
9-7.  
9-8.  
9-9.  
9-10.  
9-11.  
9-12.  
9-13.  
9-14.  
9-15.  
9-16.  
10-1.  
10-2.  
10-3.  
Watch Timer Block Diagram .......................................................................................................... 243  
Timer Clock Select Register 2 Format........................................................................................... 244  
Watch Timer Mode Control Register Format ................................................................................. 245  
11-1.  
11-2.  
11-3.  
Watchdog Timer Block Diagram .................................................................................................... 249  
Timer Clock Select Register 2 Format........................................................................................... 251  
Watchdog Timer Mode Register Format........................................................................................ 252  
27  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (4/8)  
Figure No.  
Title  
Page  
12-1.  
12-2.  
12-3.  
12-4.  
Remote Controlled Output Application Example ........................................................................... 255  
Clock Output Control Circuit Block Diagram ................................................................................. 256  
Timer Clock Select Register 0 Format........................................................................................... 258  
Port Mode Register 3 Format ........................................................................................................ 259  
13-1.  
13-2.  
13-3.  
Buzzer Output Control Circuit Block Diagram ............................................................................... 261  
Timer Clock Select Register 2 Format........................................................................................... 263  
Port Mode Register 3 Format ........................................................................................................ 264  
14-1.  
14-2.  
14-3.  
14-4.  
14-5.  
14-6.  
14-7.  
14-8.  
14-9.  
A/D Converter Block Diagram ....................................................................................................... 266  
Handling of AVDD Pin ..................................................................................................................... 268  
A/D Converter Mode Register Format ........................................................................................... 270  
A/D Converter Input Select Register Format ................................................................................. 271  
External Interrupt Mode Register 1 Format ................................................................................... 272  
A/D Converter Basic Operation ..................................................................................................... 274  
Relations between Analog Input Voltage and A/D Conversion Result........................................... 275  
A/D Conversion by Hardware Start ............................................................................................... 276  
A/D Conversion by Software Start................................................................................................. 277  
14-10. Example of Method of Reducing Current Dissipation in Standby Mode........................................ 278  
14-11. Analog Input Pin Disposition ......................................................................................................... 279  
14-12. A/D Conversion End Interrupt Request Generation Timing........................................................... 280  
14-13. Handling of AVDD Pin ..................................................................................................................... 280  
15-1.  
15-2.  
15-3.  
D/A Converter Block Diagram ....................................................................................................... 282  
D/A Converter Mode Register Format ........................................................................................... 284  
Use Example of Buffer Amplifier.................................................................................................... 286  
16-1.  
16-2.  
16-3.  
16-4.  
16-5.  
16-6.  
16-7.  
16-8.  
16-9.  
Serial Bus Interface (SBI) System Configuration Example ........................................................... 289  
Serial Interface Channel 0 Block Diagram .................................................................................... 291  
Timer Clock Select Register 3 Format........................................................................................... 295  
Serial Operating Mode Register 0 Format..................................................................................... 296  
Serial Bus Interface Control Register Format................................................................................ 298  
Interrupt Timing Specify Register Format ...................................................................................... 300  
3-Wire Serial I/O Mode Timings .................................................................................................... 305  
RELT and CMDT Operations......................................................................................................... 305  
Circuit of Switching in Transfer Bit Order ...................................................................................... 306  
16-10. Example of Serial Bus Configuration with SBI .............................................................................. 307  
16-11. SBI Transfer Timings ..................................................................................................................... 309  
16-12. Bus Release Signal ....................................................................................................................... 310  
16-13. Command Signal ........................................................................................................................... 310  
16-14. Addresses ..................................................................................................................................... 311  
16-15. Slave Selection with Address ........................................................................................................ 311  
16-16. Commands .................................................................................................................................... 312  
28  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (5/8)  
Figure No.  
Title  
Page  
16-17. Data ............................................................................................................................................... 312  
16-18. Acknowledge Signal ...................................................................................................................... 313  
16-19. BUSY and READY Signals............................................................................................................ 314  
16-20. RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................. 319  
16-21. RELT and CMDD Operations (Slave) ............................................................................................ 319  
16-22. ACKT Operation ............................................................................................................................ 320  
16-23. ACKE Operations .......................................................................................................................... 321  
16-24. ACKD Operations .......................................................................................................................... 322  
16-25. BSYE Operation ............................................................................................................................ 322  
16-26. Pin Configuration ........................................................................................................................... 325  
16-27. Address Transmission from Master Device to Slave Device (WUP = 1) ....................................... 327  
16-28. Command Transmission from Master Device to Slave Device ..................................................... 328  
16-29. Data Transmission from Master Device to Slave Device .............................................................. 329  
16-30. Data Transmission from Slave Device to Master Device .............................................................. 330  
16-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................. 333  
16-32. 2-Wire Serial I/O Mode Timings .................................................................................................... 337  
16-33. RELT and CMDT Operations......................................................................................................... 338  
16-34. SCK0/P27 Pin Configuration ......................................................................................................... 339  
17-1.  
17-2.  
17-3.  
17-4.  
17-5.  
17-6.  
17-7.  
17-8.  
17-9.  
Serial Bus Configuration Example Using I2C Bus ......................................................................... 343  
Serial Interface Channel 0 Block Diagram .................................................................................... 345  
Timer Clock Select Register 3 Format........................................................................................... 349  
Serial Operating Mode Register 0 Format..................................................................................... 351  
Serial Bus Interface Control Register Format................................................................................ 352  
Interrupt Timing Specify Register Format ...................................................................................... 354  
3-Wire Serial I/O Mode Timings .................................................................................................... 359  
RELT and CMDT Operations......................................................................................................... 359  
Circuit of Switching in Transfer Bit Order ...................................................................................... 360  
17-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................. 361  
17-11. 2-Wire Serial I/O Mode Timings .................................................................................................... 365  
17-12. RELT and CMDT Operations......................................................................................................... 366  
17-13. Example of Serial Bus Configuration Using I2C Bus ..................................................................... 367  
17-14. I2C Bus Serial Data Transfer Timing.............................................................................................. 368  
17-15. Start Condition............................................................................................................................... 369  
17-16. Address ......................................................................................................................................... 369  
17-17. Transfer Direction Specification..................................................................................................... 369  
17-18. Acknowledge Signal ...................................................................................................................... 370  
17-19. Stop Condition ............................................................................................................................... 370  
17-20. Wait Signal .................................................................................................................................... 371  
17-21. Pin Configuration ........................................................................................................................... 377  
17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) .......... 379  
17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) .......... 382  
17-24. Start Condition Output ................................................................................................................... 385  
17-25. Slave Wait Release (Transmission) .............................................................................................. 386  
29  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (6/8)  
Figure No.  
Title  
Page  
17-26. Slave Wait Release (Reception).................................................................................................... 387  
17-27. SCK0/SCL/P27 Pin Configuration ................................................................................................. 390  
17-28. SCK0/SCL/P27 Pin Configuration ................................................................................................. 390  
17-29. Logic Circuit of SCL Signal ............................................................................................................ 391  
18-1.  
18-2.  
18-3.  
18-4.  
18-5.  
18-6.  
18-7.  
18-8.  
18-9.  
Serial Interface Channel 1 Block Diagram .................................................................................... 395  
Timer Clock Select Register 3 Format........................................................................................... 398  
Serial Operation Mode Register 1 Format..................................................................................... 399  
Automatic Data Transmit/Receive Control Register Format.......................................................... 400  
Automatic Data Transmit/Receive Interval Specify Register Format............................................. 401  
3-Wire Serial I/O Mode Timings .................................................................................................... 407  
Circuit of Switching in Transfer Bit Order ...................................................................................... 408  
Basic Transmission/Reception Mode Operation Timings .............................................................. 417  
Basic Transmission/Reception Mode Flowchart............................................................................ 418  
18-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode)...... 419  
18-11. Basic Transmission Mode Operation Timings ............................................................................... 421  
18-12. Basic Transmission Mode Flowchart ............................................................................................. 422  
18-13. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ..................................... 423  
18-14. Repeat Transmission Mode Operation Timing .............................................................................. 425  
18-15. Repeat Transmission Mode Flowchart .......................................................................................... 426  
18-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) .................................. 427  
18-17. Automatic Transmission/Reception Suspension and Restart........................................................ 429  
18-18. System Configuration When the Busy Control Option is Used ..................................................... 430  
18-19. Operation Timings when Using Busy Control Option (BUSY0 = 0) ............................................... 431  
18-20. Busy Signal and Wait Cancel (when BUSY0 = 0) ......................................................................... 432  
18-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) ................................ 433  
18-22. Operation Timing of the Bit Slippage Detection Function Through the Busy SIgnal  
(when BUSY0 = 1)......................................................................................................................... 434  
18-23. Automatic Data Transmit/Receive Interval .................................................................................... 435  
18-24. Operation Timing with Automatic Data Transmit/Receive Function Performed by  
Internal Clock ................................................................................................................................ 436  
19-1.  
19-2.  
19-3.  
19-4.  
19-5.  
19-6.  
19-7.  
19-8.  
19-9.  
Serial Interface Channel 2 Block Diagram .................................................................................... 441  
Baud Rate Generator Block Diagram ............................................................................................ 442  
Serial Operating Mode Register 2 Format..................................................................................... 444  
Asynchronous Serial Interface Mode Register Format.................................................................. 445  
Asynchronous Serial Interface Status Register Format ................................................................ 447  
Baud Rate Generator Control Register Format ............................................................................. 448  
Asynchronous Serial Interface Transmit/Receive Data Format..................................................... 461  
Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing .. 463  
Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing ....... 464  
19-10. Receive Error Timing ..................................................................................................................... 465  
19-11.  
The State of Receive Buffer Register (RXB) and Whether the Receive Completion  
Interrupt Request (INTSR) is Generated ....................................................................................... 466  
30  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (7/8)  
Figure No.  
Title  
Page  
19-12. 3-Wire Serial I/O Mode Timing ...................................................................................................... 472  
19-13. Circuit of Switching in Transfer Bit Order ...................................................................................... 473  
19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1)............................ 474  
19-15. Receive Buffer Register Read Disable Period .............................................................................. 475  
20-1.  
20-2.  
20-3.  
20-4.  
20-5.  
Real-time Output Port Block Diagram ........................................................................................... 478  
Real-time Output Buffer Register Configuration ............................................................................ 479  
Port Mode Register 12 Format ...................................................................................................... 480  
Real-time Output Port Mode Register Format ............................................................................... 480  
Real-time Output Port Control Register Format ............................................................................ 481  
21-1.  
21-2.  
21-3.  
21-4.  
21-5.  
21-6.  
21-7.  
21-8.  
21-9.  
Basic Configuration of Interrupt Function ...................................................................................... 486  
Interrupt Request Flag Register Format ........................................................................................ 489  
Interrupt Mask Flag Register Format............................................................................................. 490  
Priority Specify Flag Register Format............................................................................................ 491  
External Interrupt Mode Register 0 Format ................................................................................... 492  
External Interrupt Mode Register 1 Format ................................................................................... 493  
Sampling Clock Select Register Format........................................................................................ 494  
Noise Eliminator Input/Output Timing (during rising edge detection) ............................................ 495  
Program Status Word Configuration ............................................................................................. 496  
21-10. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment................... 498  
21-11. Non-Maskable Interrupt Request Acknowledge Timing................................................................. 498  
21-12. Non-Maskable Interrupt Request Acknowledge Operation ........................................................... 499  
21-13. Interrupt Request Acknowledge Processing Algorithm.................................................................. 501  
21-14. Interrupt Request Acknowledge Timing (Minimum Time) .............................................................. 502  
21-15. Interrupt Request Acknowledge Timing (Maximum Time) ............................................................. 502  
21-16. Multiple Interrupt Example............................................................................................................. 504  
21-17. Interrupt Request Hold .................................................................................................................. 506  
21-18. Basic Configuration of Test Function ............................................................................................. 507  
21-19. Format of Interrupt Request Flag Register 1L ............................................................................... 508  
21-20. Format of Interrupt Mask Flag Register 1L.................................................................................... 508  
21-21. Key Return Mode Register Format................................................................................................ 509  
22-1.  
22-2.  
22-3.  
22-4.  
22-5.  
22-6.  
22-7.  
22-8.  
Memory Map when Using External Device Expansion Function ................................................... 512  
Memory Expansion Mode Register Format ................................................................................... 516  
Memory Size Switching Register Format ...................................................................................... 517  
Instruction Fetch from External Memory ....................................................................................... 519  
External Memory Read Timing ...................................................................................................... 520  
External Memory Write Timing ...................................................................................................... 521  
External Memory Read Modify Write Timing ................................................................................. 522  
Connection Example of µPD78054 and Memory .......................................................................... 523  
23-1.  
23-2.  
Oscillation Stabilization Time Select Register Format ................................................................... 526  
HALT Mode Clear upon Interrupt Request Generation ................................................................. 528  
31  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF FIGURES (8/8)  
Figure No.  
Title  
Page  
23-3.  
23-4.  
23-5.  
HALT Mode Release by RESET Input........................................................................................... 529  
STOP Mode Release by Interrupt Request Generation ................................................................ 531  
Release by STOP Mode RESET Input .......................................................................................... 532  
24-1.  
24-2.  
24-3.  
24-4.  
Block Diagram of Reset Function .................................................................................................. 533  
Timing of Reset Input by RESET Input.......................................................................................... 534  
Timing of Reset due to Watchdog Timer Overflow ........................................................................ 534  
Timing of Reset Input in STOP Mode by RESET Input ................................................................. 534  
25-1.  
25-2.  
25-3.  
25-4.  
25-5.  
25-6.  
25-7.  
25-8.  
25-9.  
Block Diagram of ROM Correction ................................................................................................ 537  
Correction Address Registers 0 and 1 Format .............................................................................. 538  
Correction Control Register Format .............................................................................................. 539  
Storing Example to EEPROM (when one place is corrected) ....................................................... 540  
Connecting Example with EEPROM (using 2-wire serial I/O mode) ............................................. 540  
Initialization Routine ...................................................................................................................... 541  
ROM Correction Operation............................................................................................................ 542  
ROM Correction Example ............................................................................................................. 543  
Program Transition Diagram (when one place is corrected) ......................................................... 544  
25-10. Program Transition Diagram (when two places are corrected) ..................................................... 545  
26-1.  
26-2.  
26-3.  
26-4.  
26-5.  
26-6.  
26-7.  
26-8.  
Memory Size Switching Register Format (µPD78P054) ............................................................... 549  
Memory Size Switching Register Format (µPD78P058) ............................................................... 550  
Internal Expansion RAM Size Switching Register Format ............................................................ 551  
Page Program Mode Flowchart..................................................................................................... 554  
Page Program Mode Timing.......................................................................................................... 555  
Byte Program Mode Flowchart ...................................................................................................... 556  
Byte Program Mode Timing ........................................................................................................... 557  
PROM Read Timing ...................................................................................................................... 558  
B-1.  
B-2.  
B-3.  
B-4.  
Development Tool Configuration ................................................................................................... 580  
EV-9200GC-80 Drawing (For Reference Only) ............................................................................. 590  
EV-9200GC-80 Footprint (For Reference Only) ............................................................................ 591  
TGK-080SDW Drawing (For Reference) (unit: mm)...................................................................... 592  
32  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF TABLES (1/3)  
Table No.  
Title  
Page  
1-1.  
1-2.  
Differences between Standard Quality Grade Products and (A) Products....................................  
Mask Options of Mask ROM Versions...........................................................................................  
48  
48  
2-1.  
3-1.  
4-1.  
Mask Options of Mask ROM Versions...........................................................................................  
Pin Input/Output Circuit Types .......................................................................................................  
Pin Input/Output Circuit Types .......................................................................................................  
58  
71  
87  
5-1.  
5-2.  
5-3.  
5-4.  
5-5.  
5-6.  
Internal ROM Capacity ..................................................................................................................  
Vector Table...................................................................................................................................  
99  
99  
Internal High-Speed RAM Capacity .............................................................................................. 100  
Internal High-Speed RAM Area ..................................................................................................... 110  
Correspondent Table of Absolute Addresses in the General Registers......................................... 112  
Special-Function Register List....................................................................................................... 115  
6-1.  
6-2.  
6-3.  
6-4.  
6-5.  
6-6.  
Port Functions (µPD78054 subseries) .......................................................................................... 130  
Port Functions (µPD78054Y subseries) ........................................................................................ 132  
Port Configuration ......................................................................................................................... 134  
Pull-up Resistor of Port 6 .............................................................................................................. 144  
Port Mode Register and Output Latch Settings when Using Dual-Functions ................................ 151  
Comparison between Mask ROM Version and PROM Version..................................................... 157  
7-1.  
7-2.  
7-3.  
Clock Generator Configuration ...................................................................................................... 159  
Relationship between CPU Clock and Minimum Instruction Execution Time................................ 163  
Maximum Time Required for CPU Clock Switchover .................................................................... 172  
8-1.  
8-2.  
8-3.  
8-4.  
8-5.  
8-6.  
8-7.  
Timer/Event Counter Operations ................................................................................................... 176  
16-Bit Timer/Event Counter Interval Times.................................................................................... 177  
16-Bit Timer/Event Counter Square-Wave Output Ranges ........................................................... 178  
16-Bit Timer/Event Counter Configuration..................................................................................... 179  
INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge .............................................. 181  
16-Bit Timer/Event Counter Interval Times.................................................................................... 193  
16-Bit Timer/Event Count Square-Wave Output Ranges .............................................................. 207  
9-1.  
9-2.  
9-3.  
8-Bit Timer/Event Counters 1 and 2 Interval Times ....................................................................... 216  
8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges .............................................. 217  
Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as  
16-Bit Timer/Event Counters ......................................................................................................... 218  
Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as  
9-4.  
16-Bit Timer/Event Counters ......................................................................................................... 219  
8-Bit Timer/Event Counters 1 and 2 Configurations ...................................................................... 220  
8-Bit Timer/Event Counter 1 Interval Time .................................................................................... 229  
8-Bit Timer/Event Counter 2 Interval Time .................................................................................... 230  
9-5.  
9-6.  
9-7.  
33  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF TABLES (2/3)  
Table No.  
Title  
Page  
9-8.  
9-9.  
8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges .............................................. 232  
Interval Times when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2) are Used  
as 16-Bit Timer/Event Counter ...................................................................................................... 235  
Square-Wave Output Ranges when 2-Channel 8-Bit Timer/ Event Counters (TM1 and TM2)  
are Used as 16-Bit Timer/Event Counter....................................................................................... 237  
9-10.  
10-1.  
10-2.  
10-3.  
Interval Timer Interval Time ........................................................................................................... 241  
Watch Timer Configuration ............................................................................................................ 242  
Interval Timer Interval Time ........................................................................................................... 246  
11-1.  
11-2.  
11-3.  
11-4.  
11-5.  
Watchdog Timer Runaway Detection Times.................................................................................. 247  
Interval Times ................................................................................................................................ 248  
Watchdog Timer Configuration ...................................................................................................... 249  
Watchdog Timer Runaway Detection Times.................................................................................. 253  
Interval Timer Interval Time ........................................................................................................... 254  
12-1.  
13-1.  
14-1.  
15-1.  
Clock Output Control Circuit Configuration ................................................................................... 256  
Buzzer Output Control Circuit Configuration ................................................................................. 261  
A/D Converter Configuration ......................................................................................................... 265  
D/A Converter Configuration ......................................................................................................... 282  
16-1.  
16-2.  
16-3.  
Differences between Channels 0, 1, and 2 ................................................................................... 287  
Serial Interface Channel 0 Configuration ...................................................................................... 290  
Various Signals in SBI Mode ......................................................................................................... 323  
17-1.  
17-2.  
17-3.  
17-4.  
Differences between Channels 0, 1, and 2 ................................................................................... 341  
Serial Interface Channel 0 Configuration ...................................................................................... 344  
Serial Interface Channel 0 Interrupt Request Signal Generation .................................................. 347  
Signals in I2C Bus Mode ................................................................................................................ 376  
18-1.  
18-2.  
18-3.  
Serial Interface Channel 1 Configuration ...................................................................................... 394  
Interval Timing Through CPU Processing (when the internal clock is operating).......................... 436  
Interval Timing Through CPU Processing (when the external clock is operating)......................... 437  
19-1.  
19-2.  
19-3.  
19-4.  
Serial Interface Channel 2 Configuration ...................................................................................... 440  
Serial Interface Channel 2 Operating Mode Settings .................................................................... 446  
Relation between Main System Clock and Baud Rate .................................................................. 450  
Relation between ASCK Pin Input Frequency and Baud Rate  
(When BRGC is set to 00H) .......................................................................................................... 451  
Relation between Main System Clock and Baud Rate .................................................................. 459  
Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)......... 460  
19-5.  
19-6.  
34  
Download from Www.Somanuals.com. All Manuals Search And Download.  
LIST OF TABLES (3/3)  
Table No.  
19-7.  
Title  
Page  
Receive Error Causes ................................................................................................................... 465  
20-1.  
20-2.  
20-3.  
Real-time Output Port Configuration ............................................................................................. 478  
Operation in Real-time Output Buffer Register Manipulation ........................................................ 479  
Real-time Output Port Operating Mode and Output Trigger .......................................................... 481  
21-1.  
21-2.  
21-3.  
21-4.  
21-5.  
21-6.  
Interrupt Source List ...................................................................................................................... 484  
Various Flags Corresponding to Interrupt Request Sources ......................................................... 488  
Times from Maskable Interrupt Request Generation to Interrupt Service ..................................... 500  
Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing .................................. 503  
Test Input Factors .......................................................................................................................... 507  
Flags Corresponding to Test Input Signals.................................................................................... 507  
22-1.  
22-2.  
22-3.  
Pin Functions in External Memory Expansion Mode ..................................................................... 511  
State of Ports 4 to 6 Pins in External Memory Expansion Mode ................................................... 511  
Values when the Memory Size Switching Register is Reset ......................................................... 517  
23-1.  
23-2.  
23-3.  
23-4.  
HALT Mode Operating Status........................................................................................................ 527  
Operation after HALT Mode Release ............................................................................................ 529  
STOP Mode Operating Status ....................................................................................................... 530  
Operation after STOP Mode Release............................................................................................ 532  
24-1.  
25-1.  
Hardware Status after Reset ......................................................................................................... 535  
ROM Correction Configuration ...................................................................................................... 537  
26-1.  
26-2.  
26-3.  
26-4.  
26-5.  
26-6.  
Differences between µPD78P054, 78P058 and Mask ROM Versions .......................................... 547  
Differences between µPD78P054 and 78P058 ............................................................................. 548  
Examples of Memory Size Switching Register Settings (µPD78P054) ......................................... 549  
Examples of Memory Size Switching Register Settings (µPD78P058) ......................................... 550  
Value Set to the Internal Expansion RAM Size Switching Register .............................................. 551  
PROM Programming Operating Modes ........................................................................................ 552  
27-1.  
A-1.  
Operand Identifiers and Description Methods ............................................................................... 562  
Major differences between µPD78054, 78054Y Subseries and  
µPD78058F, 78058FY Subseries .................................................................................................. 578  
B-1.  
B-2.  
OS for IBM PC............................................................................................................................... 589  
Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A.................................... 589  
35  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
36  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 GENERAL (µPD78054 Subseries)  
1.1 Features  
On-chip high-capacity ROM and RAM  
Type  
Part Number  
Data Memory  
Program Memory  
(ROM)  
Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM  
32 bytes  
None  
512 bytes  
µPD78052  
µPD78053  
µPD78054  
µPD78P054  
µPD78055  
µPD78056  
µPD78058  
µPD78P058  
16 Kbytes  
1024 bytes  
24 Kbytes  
32 Kbytes  
1024 bytesNote1  
1024 bytes  
32 KbytesNote1  
40 Kbytes  
48 Kbytes  
1024 bytes  
60 Kbytes  
1024 bytesNote1  
1024 bytesNote2  
60 KbytesNote1  
Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the  
memory size switching register (IMS).  
2. The capacity of internal high-speed RAM can be changed by means of the internal expansion RAM  
size switching register (IXS).  
External Memory Expansion Space: 64 Kbytes  
Minimum instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation)  
to ultra-low speed (122 µs: In subsystem clock 32.768 kHz operation)  
Instruction set suited to system control  
• Bit manipulation possible in all address spaces  
• Multiply and divide instructions  
69 I/O ports: (4 N-ch open-drain ports)  
8-bit resolution A/D converter: 8 channels  
8-bit resolution D/A converter: 2 channels  
Serial interface: 3 channels  
• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel  
• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel  
• 3-wire serial I/O/UART mode: 1 channel  
Timer: 5 channels  
• 16-bit timer/event counter : 1 channel  
• 8-bit timer/event counter : 2 channels  
• Watch timer : 1 channel  
• Watchdog timer : 1 channel  
22 vectored interrupt sources  
2 test inputs  
Two types of on-chip clock oscillators (main system clock and subsystem clock)  
Supply voltage: VDD = 2.0 to 6.0 V  
37  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.2 Applications  
µPD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058:  
Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending  
machines, etc.  
µPD78052(A), 78053(A), 78054(A):  
Control unit for automobile electronics, gas detector/breaker, various safety unit, etc.  
1.3 Ordering Information  
Part number  
Package  
Internal ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
One-time PROM  
One-time PROM  
One-time PROM  
EPROM  
µPD78052GC-×××-8BT  
µPD78052GK-×××-BE9  
µPD78053GC-×××-8BT  
µPD78053GK-×××-BE9  
µPD78054GC-×××-8BT  
µPD78054GK-×××-BE9  
µPD78P054GC-3B9  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
Note  
µPD78P054GC-8BT  
µPD78P054GK-BE9  
µPD78P054KK-T  
80-pin ceramic WQFN (14 × 14 mm)  
µPD78055GC-×××-8BT  
µPD78055GK-×××-BE9  
µPD78056GC-×××-8BT  
µPD78056GK-×××-BE9  
µPD78058GC-×××-8BT  
µPD78058GK-×××-BE9  
µPD78P058GC-8BT  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
One-time PROM  
EPROM  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin ceramic WQFN (14 × 14 mm)  
µPD78P058KK-T  
µPD78052GC(A)-×××-3B9  
µPD78053GC(A)-×××-3B9  
µPD78054GC(A)-×××-3B9  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
Mask ROM  
Mask ROM  
Mask ROM  
Note Under development  
Caution The µPD78P054GC is available in two packages. For the package that can be supplied, consult  
NEC.  
Remark ××× indicates ROM code suffix.  
38  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.4 Quality Grade  
Part number  
Package  
Quality grade  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
µPD78052GC-×××-8BT  
µPD78052GK-×××-BE9  
µPD78053GC-×××-8BT  
µPD78053GK-×××-BE9  
µPD78054GC-×××-8BT  
µPD78054GK-×××-BE9  
µPD78P054GC-3B9  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin ceramic WQFN (14 × 14 mm)  
Note  
µPD78P054GC-8BT  
µPD78P054GK-BE9  
µPD78P054KK-T  
Not applicable  
(for function evalution)  
µPD78055GC-×××-8BT  
µPD78055GK-×××-BE9  
µPD78056GC-×××-8BT  
µPD78056GK-×××-BE9  
µPD78058GC-×××-8BT  
µPD78058GK-×××-BE9  
µPD78P058GC-8BT  
µPD78P058KK-T  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin ceramic WQFN (14 × 14 mm)  
Not applicable  
(for function evalution)  
µPD78052GC(A)-×××-3B9  
µPD78053GC(A)-×××-3B9  
µPD78054GC(A)-×××-3B9  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
Special  
Special  
Special  
Note Under development  
Cautions 1. The µPD78P054GC is available in two packages. For the package that can be supplied,  
consult NEC.  
2. The µPD78054KK-T and 78P058KK-T should be used only for experiment or function  
evaluation, because they are not intended for use in equipment that will be mass-produced  
and require high reliability.  
Remark ××× indicates ROM code suffix.  
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC  
Corporation to know the specification of quality grade on the devices and its recommended applications.  
39  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.5 Pin Configuration (Top View)  
(1) Normal operating mode  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
µPD78P054GC-3B9  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
µPD78052GC-×××-8BT, 78053GC-×××-8BT, 78054GC-×××-8BT, 78P054GC-8BT  
µPD78055GC-×××-8BT, 78056GC-×××-8BT, 78058GC-×××-8BT, 78P058GC-8BT  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
Note  
µPD78052GK-×××-BE9, 78053GK-×××-BE9, 78054GK-×××-BE9, 78P054GK-BE9  
µPD78055GK-×××-BE9, 78056GK-×××-BE9, 78058GK-×××-BE9  
80-pin ceramic WQFN (14 × 14 mm)  
µPD78P054KK-T, 78P058KK-T  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
P15/ANI5  
P16/ANI6  
P17/ANI7  
1
2
3
4
5
6
7
8
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
RESET  
P127/RTP7  
P126/RTP6  
P125/RTP5  
P124/RTP4  
P123/RTP3  
P122/RTP2  
P121/RTP1  
P120/RTP0  
P37  
AVSS  
P130/ANO0  
P131/ANO1  
AVREF1  
P70/SI2/RxD  
P71/SO2/TxD  
P72/SCK2/ASCK  
P20/SI1  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
P36/BUZ  
P35/PCL  
P34/TI2  
P21/SO1  
P22/SCK1  
P23/STB  
P33/TI1  
P24/BUSY  
P25/SI0/SB0  
P26/SO0/SB1  
P27/SCK0  
P40/AD0  
P32/TO2  
P31/TO1  
P30/TO0  
P67/ASTB  
P66/WAIT  
P65/WR  
P41/AD1  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Note Under development  
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.  
2. Connect AVDD pin to VDD.  
3. Connect AVSS pin to VSS.  
Remark Pin connection in parentheses is intended for the µPD78P054, 78P058.  
40  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
Pin Identifications  
A8 to A15  
AD0 to AD7  
ANI0 to ANI7  
ANO0, ANO1  
ASCK  
:
:
:
:
:
:
:
:
:
:
:
:
Address Bus  
P130, P131  
PCL  
:
:
:
:
:
:
:
Port13  
Address/Data Bus  
Analog Input  
Programmable Clock  
Read Strobe  
Reset  
RD  
Analog Output  
RESET  
RTP0 to RTP7  
RxD  
Asynchronous Serial Clock  
Address Strobe  
Analog Power Supply  
Analog Reference Voltage  
Analog Ground  
Real-Time Output Port  
Receive Data  
Serial Bus  
ASTB  
AVDD  
SB0, SB1  
AVREF0, AVREF1  
AVSS  
SCK0 to SCK2 : Serial Clock  
S10 to S12  
SO0 to SO2  
STB  
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Serial Input  
BUSY  
Busy  
Serial Output  
Strobe  
BUZ  
Buzzer Clock  
IC  
Internally Connected  
TI00, TI01  
TI1, TI2  
TO0 to TO2  
TxD  
Timer Input  
INTP0 to INTP6 : Interrupt from Peripherals  
Timer Input  
P00 to P07  
P10 to P17  
P20 to P27  
P30 to P37  
P40 to P47  
P50 to P57  
P60 to P67  
P70 to P72  
P120 to P127  
:
:
:
:
:
:
:
:
:
Port0  
Port1  
Port2  
Port3  
Port4  
Port5  
Port6  
Port7  
Port12  
Timer Output  
Transmit Data  
Power Supply  
Programming Power Supply  
Ground  
VDD  
VPP  
VSS  
WAIT  
Wait  
WR  
Write Strobe  
X1, X2  
XT1, XT2  
Crystal (Main System Clock)  
Crystal (Subsystem Clock)  
41  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
(2) PROM programming mode  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
µPD78P054GC-3B9  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
Note  
µPD78P054GC-8BT  
, 78P058GC-8BT  
80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
µPD78P054GK-BE9  
80-pin ceramic WQFN (14 × 14 mm)  
µPD78P054KK-T, 78P058KK-T  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
1
2
3
4
5
6
7
8
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
RESET  
(L)  
(L)  
VSS  
(L)  
VDD  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
(L)  
(L)  
A0  
A1  
CE  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Note Under development  
Cautions 1. (L)  
2. VSS  
: Connect individually to VSS via a pull-down resistor.  
: Connect to the ground.  
3. RESET : Set to the low level.  
4. Open : Leave this pin unconnected.  
A0 to A16  
CE  
: Address Bus  
: Chip Enable  
: Data Bus  
RESET  
: Reset  
VDD  
VPP  
VSS  
: Power Supply  
: Programming Power Supply  
: Ground  
D0 to D7  
OE  
: Output Enable  
: Program  
PGM  
42  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.6 78K/0 Series Expansion  
The products in the 78K/0 Series are listed below. The names in boxes are subseries names.  
Mass-produced products  
Products under development  
The subseries whose name ends with Y support  
the I2C bus specifications.  
Control  
100-pin  
100-pin  
100-pin  
100-pin  
80-pin  
80-pin  
80-pin  
64-pin  
64-pin  
64-pin  
64-pin  
64-pin  
64-pin  
64-pin  
42-/44-pin  
µPD78075B  
µPD78078  
µPD78070A  
Reduced EMI noise version of µPD78078  
Added timers to µPD78054 and enhanced external interface  
µPD78070AY ROM-less version of µPD78078  
µPD78078Y  
Enhanced serial I/O of µPD78078Y and functions are defined.  
µ
PD780018AY  
Note  
Enhanced serial I/O of µPD78054, reduced EMI noise version  
µPD780058  
µPD78058F  
µPD78054  
µPD780034  
µPD780024  
µPD78014H  
µPD78018F  
µPD78014  
µPD780001  
µPD78002  
µPD78083  
µPD780058Y  
µPD78058FY Reduced EMI noise version of µPD78054  
µPD78054Y  
Added UART and D/A to µPD78014 and enhanced I/Os  
µPD780034Y Enhanced A/D of µPD780024  
µPD780024Y Enhanced serial I/O of µPD78018F  
Reduced EMI noise version of µPD78018F  
µPD78018FY Low-voltage (1.8 V) version of µPD78014 and enhanced ROM/RAM size options  
µPD78014Y  
Added A/D and 16-bit timer to µPD78002  
Added A/D to µPD78002  
µPD78002Y  
Basic subseries for control applications  
Equipped with UART and operates at low-voltage (1.8 V)  
Inverter control  
µPD780988  
µPD780964  
µPD780924  
Enhanced inverter control, timer, and SIO of µPD780964, expanded ROM and RAM  
Enhanced A/D of µPD780924  
64-pin  
64-pin  
64-pin  
Equipped with inverter control circuit and UART, reduced EMI noise version  
78K/0  
Series  
FIPTM driving  
µPD780208  
µPD780228  
µPD78044H  
µPD78044F  
100-pin  
100-pin  
80-pin  
Enhanced I/O and FIP C/D of µPD78044F, 53 display outputs  
Enhanced I/O and FIP C/D of µPD78044H, 48 display outputs  
Added N-ch open-drain I/O to µPD78044F, 34 display outputs  
Basic subseries for driving FIPs, 34 display outputs  
80-pin  
LCD driving  
µPD780308  
µPD78064B  
µPD78064  
100-pin  
100-pin  
100-pin  
µPD780308Y Enhanced SIO of µPD78064, expanded ROM and RAM  
Reduced EMI noise version of µPD78064  
µPD78064Y  
Basic subseries for driving LCDs, equipped with UART  
IEBusTM supported  
µPD78098B  
µPD78098  
80-pin  
80-pin  
Reduced EMI noise version of µPD78098  
Added IEBus controller to µPD78054  
Meter control  
Equipped with controller/driver for driving automobile meters  
80-pin  
µPD780973  
Note Planned  
43  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
The following shows the major differences between subseries products.  
Function  
Subseries Name  
ROM  
Timer  
8-bit 10-bit 8-bit  
VDD  
External  
Serial Interface  
I/O  
Capacity  
8-bit 16-bit Watch WDT A/D A/D D/A  
MIN. Value Expansion  
Control µPD78075B  
µPD78078  
32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch  
2 ch 3 ch (UART: 1 ch) 88  
1.8 V  
48 K to 60 K  
µPD78070A  
61  
2.7 V  
1.8 V  
µPD780058  
24 K to 60 K 2 ch  
3 ch (Time division 68  
UART: 1 ch)  
µPD78058F  
µPD78054  
48 K to 60 K  
16 K to 60 K  
3 ch (UART: 1 ch) 69  
2.7 V  
2.0 V  
1.8 V  
µPD780034  
8 K to 32 K  
8 ch  
3 ch (UART: 1 ch, Time 51  
division 3-wire: 1 ch)  
µPD780024  
8 ch  
µPD78014H  
µPD78018F  
2 ch  
53  
8 K to 60 K  
8 K to 32 K  
8 K  
µPD78014  
2.7 V  
µPD780001  
1 ch  
1 ch  
39  
53  
µPD78002  
8 K to 16 K  
8 ch  
µPD78083  
1 ch (UART: 1 ch) 33  
3 ch (UART: 2 ch) 47  
2 ch (UART: 2 ch)  
1.8 V  
4.0 V  
2.7 V  
Inverter µPD780988  
32 K to 60 K 3 ch Note 1  
8 K to 32 K  
1 ch  
8 ch  
control  
µPD780964  
Note 2  
µPD780924  
8 ch  
FIP  
µPD780208  
µPD780228  
µPD78044H  
µPD78044F  
µPD780308  
32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch  
48 K to 60 K 3 ch  
2 ch  
1 ch  
74  
72  
68  
2.7 V  
4.5 V  
2.7 V  
driving  
32 K to 48 K 2 ch 1 ch 1 ch  
16 K to 40 K  
2 ch  
LCD  
48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch  
3 ch (Time division 57  
UART: 1 ch)  
2.0 V  
driving  
µPD78064B  
µPD78064  
µPD78098B  
µPD78098  
µPD780973  
32 K  
2 ch (UART: 1 ch)  
16 K to 32 K  
IEBus  
40 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch  
32 K to 60 K  
2 ch 3 ch (UART: 1 ch) 69  
2.7 V  
4.5 V  
supported  
Meter  
control  
24 K to 32 K 3 ch 1 ch 1 ch 1 ch 5 ch  
2 ch (UART: 1 ch) 56  
Notes 1. 16-bit timer: 2 channels  
10-bit timer: 1 channel  
2. 10-bit timer: 1 channel  
44  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.7 Block Diagram  
P00  
TO0/P30  
P01-P06  
P07  
PORT 0  
PORT 1  
PORT 2  
PORT 3  
PORT 4  
PORT 5  
PORT 6  
PORT 7  
PORT 12  
PORT 13  
16-bit TIMER/  
EVENT COUNTER  
TI00/INTP0/P00  
TI01/INTP1/P01  
P10-P17  
P20-P27  
P30-P37  
P40-P47  
P50-P57  
P60-P67  
P70-P72  
P120-P127  
P130, P131  
TO1/P31  
TI1/P33  
8-bit TIMER/  
EVENT COUNTER 1  
TO2/P32  
TI2/P34  
8-bit TIMER/  
EVENT COUNTER 2  
WATCHDOG TIMER  
WATCH TIMER  
SI0/SB0/P25  
SO0/SB1/P26  
SCK0/P27  
SERIAL  
INTERFACE 0  
78K/0  
CPU CORE  
ROM  
SI1/P20  
SO1/P21  
SCK1/P22  
STB/P23  
SERIAL  
INTERFACE 1  
BUSY/P24  
SI2/RxD/P70  
SO2/TxD/P71  
SCK2/ASCK/P72  
SERIAL  
INTERFACE 2  
RAM  
ANI0/P10-  
ANI7/P17  
RTP0/P120-  
RTP7/P127  
REAL-TIME  
OUTPUT PORT  
AVDD  
AVSS  
A/D CONVERTER  
D/A CONVERTER  
AVREF0  
AD0/P40-  
AD7/P47  
ANO0/P130,  
ANO1/P131  
A8/P50-  
A15/P57  
EXTERNAL  
ACCESS  
AVSS  
RD/P64  
AVREF1  
WR/P65  
WAIT/P66  
ASTB/P67  
INTP0/P00-  
INTP6/P06  
INTERRUPT  
CONTROL  
RESET  
X1  
BUZ/P36  
PCL/P35  
BUZZER OUTPUT  
SYSTEM  
CONTROL  
X2  
XT1/P07  
XT2  
CLOCK OUTPUT  
CONTROL  
VDD  
VSS  
IC  
(VPP)  
Remarks 1. The internal ROM and RAM capacities depend on the product.  
2. Pin connection in parentheses is intended for the µPD78P054, 78P058.  
45  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.8 Outline of Function  
Part Number  
µPD78052 µPD78053 µPD78054 µPD78P054 µPD78055 µPD78056 µPD78058 µPD78P058  
Note 1 Note 2  
Item  
ROM  
Mask ROM  
PROM  
Mask ROM  
PROM  
Internal  
memory  
16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes  
Note 3  
Note 3  
High-speed RAM  
512 bytes 1024 bytes  
1024 bytes 1024 bytes  
1024 bytes  
Note 3  
Note 3  
Buffer RAM  
32 bytes  
None  
Expansion RAM  
1024 bytes 1024 bytes  
Note 4  
Memory space  
64 Kbytes  
General register  
Minimum  
8 bits × 8 × 4 banks  
With main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz)  
instruction  
With subsystem clock selected  
122 µs (@ 32.768 kHz)  
execution time  
Instruction set  
• 16-bit operation  
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)  
• Bit manipulate (set, reset, test, and Boolean operation)  
• BCD adjust, etc.  
I/O port  
• Total  
: 69  
: 2  
• CMOS input  
• CMOS I/O  
: 63  
• N-ch open-drain I/O : 4  
8-bit resolution × 8 channels  
8-bit resolution × 2 channels  
A/D converter  
D/A converter  
Serial interface  
• 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible : 1 channel  
• 3-wire serial I/O mode (Max. 32-byte on-chip auto-transmit/receive) : 1 channel  
• 3-wire serial I/O/UART mode selectable : 1 channel  
Timer  
• 16-bit timer/event counter : 1 channel  
• 8-bit timer/event counter  
• Watch timer  
: 2 channels  
: 1 channel  
: 1 channel  
• Watchdog timer  
Timer output  
Clock output  
Three outputs: (14-bit PWM output enable: 1)  
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,  
2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)  
32.768 kHz (@ 32.768 kHz with subsystem clock)  
Buzzer output  
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)  
Notes 1. The µPD78P054 is the PROM version for the µPD78052, 78053, and 78054.  
2. The µPD78P058 is the PROM version for the µPD78055, 78056, and 78058.  
3. The capacities of the internal PROM and the internal high-speed RAM can be changed using the  
memory switching register (IMS).  
4. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size  
switching register (IXS).  
46  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
Part Number µPD78052 µPD78053 µPD78054 µPD78P054 µPD78055 µPD78056 µPD78058 µPD78P058  
Item  
Note 1  
Note2  
Vectored Maskable  
Internal: 13 External: 7  
interrupt Non-maskable  
Internal: 1  
1
source  
Software  
Test input  
Internal: 1 External: 1  
VDD = 2.0 to 6.0 V  
TA = –40 to +85°C  
Supply voltage  
Operating ambient temperature  
Package  
• 80-pin plastic QFP (14 × 14 mm, Resin thickness : 2.7 mm) (µPD78P054 only)  
Note 3  
• 80-pin plastic QFP  
(14 × 14 mm, Resin thickness : 1.4 mm)  
• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) (except µPD78P058)  
• 80-pin ceramic WQFN (14 × 14 mm) (µPD78P054, 78P058 only)  
Notes 1. The µPD78P054 is the PROM version for the µPD78052, 78053, 78054.  
2. The µPD78P058 is the PROM version for the µPD78055, 78056, 78058.  
3. The µPD78P054 is under development.  
47  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 1 OUTLINE (µPD78054 Subseries)  
1.9 Differences between Standard Quality Grade Products and (A) Products  
Table 1-1 shows the differences between the standard quality grade products (µPD78052, 78053, 78054) and (A)  
products (µPD78052(A), 78053(A), 78054(A)).  
Table 1-1. Differences between Standard Quality Grade Products and (A) Products  
Part Number  
Standard Quality Grade Products  
Standard  
(A) Products  
Special  
Item  
Quality grade  
Note 3  
Package  
• 80-pin plastic QFP  
80-pin plastic QFP  
(14 × 14 mm, Resin thickness : 1.4 mm)  
(14 × 14 mm, Resin thickness : 2.7 mm)  
• 80-pin plastic TQFP (Fine pitch) (12 × 12 mm)  
Recommended  
soldering conditions  
Refer to separate Data Sheets  
1.10 Mask Options  
The mask ROM versions (µPD78052, 78053, 78054, 78055, 78056, 78058) provide pull-up resistor mask options  
which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order  
for the device production. Using this mask option when pull-up resistors are required reduces the number of  
components to add to the device, resulting in board space saving.  
The mask options provided in the µPD78054 subseries are shown in Table 1-2.  
Table 1-2. Mask Options of Mask ROM Versions  
Pin names  
P60 to P63  
Mask options  
Pull-up resistor connection can be specified in 1-bit units.  
48  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 GENERAL (µPD78054Y Subseries)  
2.1 Features  
On-chip high-capacity ROM and RAM  
Type  
Data Memory  
Program Memory  
(ROM)  
Internal High-Speed RAM Internal Buffer RAM Internal Expansion RAM  
Part Number  
16 Kbytes  
24 Kbytes  
32 Kbytes  
40 Kbytes  
48 Kbytes  
60 Kbytes  
60 KbytesNote 1  
32 bytes  
None  
µPD78052Y  
µPD78053Y  
µPD78054Y  
µPD78055Y  
µPD78056Y  
µPD78058Y  
µPD78P058Y  
512 bytes  
1024 bytes  
1024 bytes  
1024 bytesNote 2  
1024 bytesNote 1  
Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the  
memory size switching register (IMS).  
2. The capacity of internal high-speed RAM can be changed by means of the internal expansion RAM  
size switching register (IXS).  
External Memory Expansion Space: 64 Kbytes  
Minimum instruction execution time changeable from high speed (0.4 µs: In main system clock 5.0 MHz operation)  
to ultra-low speed (122 µs: In subsystem clock 32.768 kHz operation)  
Instruction set suited to system control  
• Bit manipulation possible in all address spaces  
• Multiply and divide instructions  
I/O ports: 69 (N-ch open-drain ports: 4)  
8-bit resolution A/D converter: 8 channels  
8-bit resolution D/A converter: 2 channels  
Serial interface: 3 channels  
2
• 3-wire serial I/O/2-wire serial I/O/I C bus mode: 1 channel  
• 3-wire serial I/O mode (Automatic transmit/receive function): 1 channel  
• 3-wire serial I/O/UART mode: 1 channel  
Timer: Five channels  
• 16-bit timer/event counter : 1 channel  
• 8-bit timer/event counter : 2 channels  
• Watch timer : 1 channel  
• Watchdog timer : 1 channel  
22 vectored interrupt sources  
2 test inputs  
Two types of on-chip clock oscillators (main system clock and subsystem clock)  
Supply voltage: VDD = 2.0 to 6.0 V  
49  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
2.2 Applications  
Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending  
machines, etc.  
2.3 Ordering Information  
Part number  
Package  
Internal ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
Mask ROM  
One-time PROM  
EPROM  
µPD78052YGC-×××-8BT  
µPD78053YGC-×××-8BT  
µPD78054YGC-×××-8BT  
µPD78055YGC-×××-8BT  
µPD78056YGC-×××-8BT  
µPD78058YGC-×××-8BT  
µPD78P058YGC-8BT  
µPD78P058YKK-T  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin ceramic WQFN (14 × 14 mm)  
Remark ××× indicates ROM code suffix.  
2.4 Quality Grade  
Part number  
Package  
Quality grade  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
Standard  
µPD78052YGC-×××-8BT  
µPD78053YGC-×××-8BT  
µPD78054YGC-×××-8BT  
µPD78055YGC-×××-8BT  
µPD78056YGC-×××-8BT  
µPD78058YGC-×××-8BT  
µPD78P058YGC-8BT  
µPD78P058YKK-T  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin ceramic WQFN (14 × 14 mm)  
Not applicable  
(for function evaluation)  
Remark ××× indicates ROM code suffix.  
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number C11531E) published by NEC  
Corporation to know the specification of quality grade on the devices and its recommended applications.  
50  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
2.5 Pin Configuration (Top View)  
(1) Normal operating mode  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
µPD78052YGC-×××-8BT, 78053YGC-×××-8BT, 78054YGC-×××-8BT  
µPD78055YGC-×××-8BT, 78056YGC-×××-8BT, 78058YGC-×××-8BT, 78P058YGC-8BT  
80-pin ceramic WQFN (14 × 14 mm)  
µPD78P058YKK-T  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
P15/ANI5  
P16/ANI6  
P17/ANI7  
1
2
3
4
5
6
7
8
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
RESET  
P127/RTP7  
P126/RTP6  
P125/RTP5  
P124/RTP4  
P123/RTP3  
P122/RTP2  
P121/RTP1  
P120/RTP0  
P37  
AVSS  
P130/ANO0  
P131/ANO1  
AVREF1  
P70/SI2/RxD  
P71/SO2/TxD  
P72/SCK2/ASCK  
P20/SI1  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
P36/BUZ  
P35/PCL  
P34/TI2  
P21/SO1  
P22/SCK1  
P23/STB  
P24/BUSY  
P33/TI1  
P32/TO2  
P31/TO1  
P30/TO0  
P67/ASTB  
P66/WAIT  
P65/WR  
P25/SI0/SB0/SDA0  
P26/SO0/SB1/SDA1  
P27/SCK0/SCL  
P40/AD0  
P41/AD1  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.  
2. Connect AVDD pin to VDD.  
3. Connect AVSS pin to VSS.  
Remark Pin connection in parentheses is intended for the µPD78P058Y.  
51  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
Pin Identifications  
A8 to A15  
AD0 to AD7  
ANI0 to ANI7  
ANO0 to ANO7  
ASCK  
:
:
:
:
:
:
:
:
:
:
:
:
Address Bus  
PCL  
:
:
:
Programmable Clock  
Reset  
Address/Data Bus  
Analog Input  
RESET  
RD  
Read Strobe  
Analog Output  
RTP0 to RTP7 : Real-Time Output Port  
Asynchronous Serial Clock  
Address Strobe  
Analog Power Supply  
Analog Reference Voltage  
Analog Ground  
RxD  
:
:
Receive Data  
Serial Bus  
ASTB  
SB0, SB1  
AVDD  
SCK0 to SCK1 : Serial Clock  
AVREF0, AVREF1  
AVSS  
SCL  
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Serial Clock  
SDA0, SDA1  
SI0, SI1  
SO0, SO1  
STB  
Serial Data  
BUSY  
Busy  
Serial Input  
BUZ  
Buzzer Clock  
Serial Output  
Strobe  
IC  
Internally Connected  
INTP0 to INTP6 : Interrupt from Peripherals  
TI1, TI2  
TI00 to TI01  
TO0 to TO2  
TxD  
Timer Input  
P00 to P07  
P10 to P17  
P20 to P27  
P30 to P37  
P40 to P47  
P50 to P57  
P60 to P67  
P70 to P72  
P120 to P127  
P130, P131  
:
:
:
:
:
:
:
:
:
:
Port0  
Port1  
Port2  
Port3  
Port4  
Port5  
Port6  
Port7  
Port12  
Port13  
Timer Input  
Timer Output  
Transmit Data  
Power Supply  
Programming Power Supply  
Ground  
VDD  
VPP  
VSS  
WAIT  
Wait  
WR  
Write Strobe  
X1, X2  
XT1, XT2  
Crystal (Main System Clock)  
Crystal (Subsystem Clock)  
52  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
(2) PROM programming mode  
80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
µPD78P058YGC-8BT  
80-pin ceramic WQFN (14 × 14 mm)  
µPD78P058YKK-T  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
1
2
3
4
5
6
7
8
60  
RESET  
(L)  
(L)  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
VSS  
(L)  
VDD  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
(L)  
(L)  
A0  
A1  
CE  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Cautions 1. (L)  
2. VSS  
: Connect individually to VSS via a pull-down resistor.  
: Connect to the ground.  
3. RESET : Set to the low level.  
4. Open : Leave this pin unconnected.  
A0 to A16  
CE  
: Address Bus  
: Chip Enable  
: Data Bus  
RESET  
: Reset  
VDD  
VPP  
VSS  
: Power Supply  
D0 to D7  
OE  
: Programming Power Supply  
: Ground  
: Output Enable  
: Program  
PGM  
53  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
2.6 78K/0 Series Expansion  
The products in the 78K/0 Series are listed below. The names in boxes are subseries names.  
Mass-produced products  
Products under development  
The subseries whose name ends with Y support  
the I2C bus specifications.  
Control  
100-pin  
100-pin  
100-pin  
100-pin  
80-pin  
80-pin  
80-pin  
64-pin  
64-pin  
64-pin  
64-pin  
64-pin  
64-pin  
64-pin  
42-/44-pin  
µPD78075B  
µPD78078  
µPD78070A  
Reduced EMI noise version of µPD78078  
Added timers to µPD78054 and enhanced external interface  
µPD78070AY ROM-less version of µPD78078  
µPD78078Y  
Enhanced serial I/O of µPD78078Y and functions are defined.  
µ
PD780018AY  
Note  
Enhanced serial I/O of µPD78054, reduced EMI noise version  
µPD780058  
µPD78058F  
µPD78054  
µPD780034  
µPD780024  
µPD78014H  
µPD78018F  
µPD78014  
µPD780001  
µPD78002  
µPD78083  
µPD780058Y  
µPD78058FY Reduced EMI noise version of µPD78054  
µPD78054Y  
Added UART and D/A to µPD78014 and enhanced I/Os  
µPD780034Y Enhanced A/D of µPD780024  
µPD780024Y Enhanced serial I/O of µPD78018F  
Reduced EMI noise version of µPD78018F  
µPD78018FY Low-voltage (1.8 V) version of µPD78014 and enhanced ROM/RAM size options  
µPD78014Y  
Added A/D and 16-bit timer to µPD78002  
Added A/D to µPD78002  
µPD78002Y  
Basic subseries for control applications  
Equipped with UART and operates at low-voltage (1.8 V)  
Inverter control  
µPD780988  
µPD780964  
µPD780924  
Enhanced inverter control, timer, and SIO of µPD780964, expanded ROM and RAM  
64-pin  
64-pin  
64-pin  
Enhanced A/D of µPD780924  
Equipped with inverter control circuit and UART, reduced EMI noise version  
78K/0  
Series  
FIP driving  
µPD780208  
µPD780228  
µPD78044H  
µPD78044F  
100-pin  
100-pin  
80-pin  
Enhanced I/O and FIP C/D of µPD78044F, 53 display outputs  
Enhanced I/O and FIP C/D of µPD78044H, 48 display outputs  
Added N-ch open-drain I/O to µPD78044F, 34 display outputs  
Basic subseries for driving FIPs, 34 display outputs  
80-pin  
LCD driving  
µPD780308  
µPD78064B  
µPD78064  
100-pin  
100-pin  
100-pin  
µPD780308Y Enhanced SIO of µPD78064, expanded ROM and RAM  
Reduced EMI noise version of µPD78064  
µPD78064Y  
Basic subseries for driving LCDs, equipped with UART  
IEBus supported  
µPD78098B  
µPD78098  
80-pin  
80-pin  
Reduced EMI noise version of µPD78098  
Added IEBus controller to µPD78054  
Meter control  
Equipped with controller/driver for driving automobile meters  
80-pin  
µPD780973  
Note Planned  
54  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
Major differences among Y subseries are tabulated below.  
Function  
ROM  
VDD  
Configuration of Serial Interface  
I
/O  
Subseries  
Control  
Capacity  
MIN.  
2
µPD78078Y  
48K to 60K  
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
: 1 ch  
88  
61  
1.8 V  
3-wire with automatic transmit/receive function  
3-wire/UART  
µPD78070AY  
2.7 V  
µPD780018AY 48K to 60K  
µPD780058Y 24K to 60K  
µPD78058FY 48K to 60K  
3-wire with automatic transmit/receive function  
Time division 3-wire  
: 1 ch  
: 1 ch  
: 1 ch  
88  
68  
69  
2
I C bus (supports multi-master)  
2
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
: 1 ch  
1.8 V  
3-wire with automatic transmit/receive function  
3-wire/time division UART  
2
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
: 1 ch  
2.7 V  
2.0 V  
3-wire with automatic transmit/receive function  
3-wire/UART  
µPD78054Y  
16K to 60K  
µPD780034Y 8K to 32K  
UART  
3-wire  
: 1 ch  
: 1 ch  
: 1 ch  
51  
53  
1.8 V  
µPD780024Y  
2
I C bus (supports multi-master)  
2
µPD78018FY 8K to 60K  
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
3-wire with automatic transmit/receive function  
2
µPD78014Y  
8K to 32K  
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
2.7 V  
2.0 V  
3-wire with automatic transmit/receive function  
2
µPD78002Y  
8K to 16K  
3-wire/2-wire/SBI/I C  
: 1 ch  
2
LCD  
drive  
µPD780308Y 48K to 60K  
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
: 1 ch  
57  
3-wire/time division UART  
3-wire  
2
µPD78064Y  
16K to 32K  
3-wire/2-wire/I C  
: 1 ch  
: 1 ch  
3-wire/UART  
Remark The functions except serial interface are common with subseries without Y.  
55  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
2.7 Block Diagram  
P00  
TO0/P30  
P01-P06  
P07  
PORT 0  
PORT 1  
PORT 2  
PORT 3  
PORT 4  
PORT 5  
PORT 6  
PORT 7  
PORT 12  
PORT 13  
16-bit TIMER/  
EVENT COUNTER  
TI00/INTP0/P00  
TI01/INTP1/P01  
P10-P17  
P20-P27  
P30-P37  
P40-P47  
P50-P57  
P60-P67  
P70-P72  
P120-P127  
P130, P131  
TO1/P31  
TI1/P33  
8-bit TIMER/  
EVENT COUNTER 1  
TO2/P32  
TI2/P34  
8-bit TIMER/  
EVENT COUNTER 2  
WATCHDOG TIMER  
WATCH TIMER  
SI0/SB0/SDA0/P25  
SO0/SB1/SDA1/P26  
SCK0/SCL/P27  
SERIAL  
INTERFACE 0  
78K/0  
CPU CORE  
ROM  
SI1/P20  
SO1/P21  
SCK1/P22  
STB/P23  
SERIAL  
INTERFACE 1  
BUSY/P24  
SI2/RxD/P70  
SO2/TxD/P71  
SCK2/ASCK/P72  
SERIAL  
INTERFACE 2  
RAM  
ANI0/P10-  
ANI7/P17  
RTP0/P120-  
RTP7/P127  
REAL-TIME  
OUTPUT PORT  
AVDD  
AVSS  
A/D CONVERTER  
D/A CONVERTER  
AVREF0  
AD0/P40-  
AD7/P47  
ANO0/P130,  
ANO1/P131  
A8/P50-  
A15/P57  
EXTERNAL  
ACCESS  
AVSS  
RD/P64  
AVREF1  
WR/P65  
WAIT/P66  
ASTB/P67  
INTP0/P00-  
INTP6/P06  
INTERRUPT  
CONTROL  
RESET  
X1  
BUZ/P36  
PCL/P35  
BUZZER OUTPUT  
SYSTEM  
CONTROL  
X2  
XT1/P07  
XT2  
CLOCK OUTPUT  
CONTROL  
VDD  
VSS  
IC  
(VPP)  
Remarks 1. The internal ROM and RAM capacities depend on the product.  
2. Pin connection in parentheses is intended for the µPD78P058.  
56  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
2.8 Outline of Function  
Part Number  
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y µPD78P058Y  
Item  
ROM  
Mask ROM  
16 Kbytes  
PROM  
Internal  
memory  
24 Kbytes  
1024 bytes  
32 Kbytes  
40 Kbytes  
48 Kbytes  
60 Kbytes  
60 Kbytes  
Note 1  
High-speed RAM  
512 bytes  
1024 bytes  
Note 1  
Buffer RAM  
32 bytes  
None  
Expansion RAM  
1024 bytes  
1024 bytes  
Note 2  
Memory space  
64 Kbytes  
General register  
Minimum  
8 bits × 8 × 4 banks  
With main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz)  
instruction  
With subsystem clock selected  
122 µs (@ 32.768 kHz)  
execution time  
Instruction set  
• 16-bit operation  
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)  
• Bit manipulate (set, reset, test, and Boolean operation)  
• BCD adjust, etc.  
I/O port  
• Total  
: 69  
: 2  
• CMOS input  
• CMOS I/O  
: 63  
• N-ch open-drain I/O : 4  
8-bit resolution × 8 channels  
8-bit resolution × 2 channels  
A/D converter  
D/A converter  
2
Serial interface  
• 3-wire serial I/O/2-wire serial I/O/I C bus mode selection possible : 1 channel  
• 3-wire serial I/O mode (Max. 32-byte on-chip auto-transmit/receive) : 1 channel  
• 3-wire serial I/O/UART mode selectable : 1 channel  
Timer  
• 16-bit timer/event counter : 1 channel  
• 8-bit timer/event counter  
• Watch timer  
: 2 channels  
: 1 channel  
: 1 channel  
• Watchdog timer  
Timer output  
Clock output  
Three outputs: (14-bit PWM output enable: 1)  
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz,  
2.5 MHz, 5.0 MHz (@ 5.0 MHz with main system clock)  
32.768 kHz (@ 32.768 kHz with subsystem clock)  
Buzzer output  
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz with main system clock)  
Notes 1. The capacities of the internal PROM and the internal high-speed RAM can be changed using the  
memory switching register (IMS).  
2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size  
switching register (IXS).  
57  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 2 OUTLINE (µPD78054Y Subseries)  
Part Number  
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y µPD78P058Y  
Item  
Maskable  
Internal: 13  
External: 7  
Internal: 1  
1
Vectored  
interrupt  
source  
Non-maskable  
Software  
Test input  
Internal: 1  
External: 1  
Supply voltage  
VDD = 2.0 to 6.0 V  
Operating ambient temperature  
Package  
TA = –40 to +85 °C  
• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm)  
• 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm)  
• 80-pin ceramic WQFN (14 × 14 mm) (µPD78P058 only)  
2.9 Mask Options  
The mask ROM versions (µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y) provide pull-up resistor mask  
options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places  
an order for the device production. Using this mask option when pull-up resistors are required reduces the number  
of components to add to the device, resulting in board space saving.  
The mask options provided in the µPD78054Y subseries are shown in Table 2-1.  
Table 2-1. Mask Options of Mask ROM Versions  
Pin names  
P60 to P63  
Mask options  
Pull-up resistor connection can be specified in 1-bit units.  
58  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.1 Pin Function List  
3.1.1 Normal operating mode pins  
(1) Port pins (1/3)  
Pin Name Input/Output  
Function  
Input only  
After Reset Alternate Function  
P00  
P01  
P02  
P03  
P04  
P05  
P06  
Input  
Input  
INTP0/TI00  
INTP1/TI01  
INTP2  
Input/output mode can be specified  
in 1-bit units.  
Input/  
Port 0.  
When used as an input port, an  
on-chip pull-up resistor can be used  
by software.  
INTP3  
Input  
output  
8-bit input/output port.  
INTP4  
INTP5  
INTP6  
Note1  
P07  
Input  
Input only  
Input  
Input  
XT1  
P10 to P17  
Port 1.  
8-bit input/output port.  
Input/  
Input/output mode can be specified in 1-bit units.  
ANI0 to ANI7  
output  
When used as input port, an on-chip pull-up resistor can be used by  
Note2  
software  
.
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
SI1  
SO1  
Port 2.  
SCK1  
STB  
Input/  
8-bit input/output port.  
Input  
output  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
BUSY  
SI0/SB0  
SO0/SB1  
SCK0  
Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register  
(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).  
2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, set port 1 to input  
mode. The on-chip pull-up resistor will automatically be disabled.  
59  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
(1) Port pins (2/3)  
Pin Name Input/Output  
Function  
After Reset Alternate Function  
P30  
P31  
TO0  
TO1  
TO2  
P32  
P33  
P34  
P35  
P36  
P37  
Port 3.  
8-bit input/output port.  
Input/  
TI1  
Input  
output  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
TI2  
PCL  
BUZ  
Port 4.  
8-bit input/output port.  
Input/  
Input/output mode can be specified in 8-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
P40 to P47  
Input  
AD0 to AD7  
output  
Test input flag (KRIF) is set to 1 by falling edge detection.  
Port 5.  
8-bit input/output port.  
Input/  
LED can be driven directly.  
P50 to P57  
Input  
A8 to A15  
output  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
P60  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
N-ch open-drain input/output port.  
On-chip pull-up resistor can be  
specified by mask option.  
(Mask ROM version only).  
LEDs can be driven directly.  
Port 6.  
Input/  
8-bit input/output port.  
Input/output mode can be  
specified in 1-bit units.  
output  
When used as an input port, an  
on-chip pull-up resistor can be used  
by software.  
Input  
RD  
WR  
WAIT  
ASTB  
Port 7.  
P70  
P71  
P72  
SI2/RxD  
SO2/TxD  
3-bit input/output port.  
Input/  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
Input  
output  
SCK2/ASCK  
60  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
(1) Port pins (3/3)  
Pin Name Input/Output  
Function  
After Reset Alternate Function  
P120 to P127 Input/  
output  
Port 12.  
8-bit input/output port.  
Input  
RTP0 to RTP7  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
P130 to P131  
Input  
ANO0 to ANO1  
Input/  
Port 13.  
output  
2-bit input/output port.  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
61  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
(2) Pins other than port pins (1/2)  
Pin Name Input/Output  
INTP0  
Function  
After Reset Alternate Function  
P00/TI00  
P01/TI01  
P02  
INTP1  
INTP2  
External interrupt request inputs with specifiable valid edges (rising  
edge, falling edge, both rising and falling edges).  
INTP3  
INTP4  
INTP5  
INTP6  
SI0  
Input  
Input  
P03  
P04  
P05  
P06  
P25/SB0  
P20  
SI1  
Input  
Serial interface serial data input  
Input  
SI2  
P70/RxD  
P26/SB1  
P21  
SO0  
SO1  
SO2  
SB0  
Output Serial interface serial data output  
Input  
Input  
Input  
P71/TxD  
P25/SI0  
P26/SO0  
P27  
Input/  
Serial interface serial data input/output  
output  
SB1  
SCK0  
SCK1  
SCK2  
STB  
BUSY  
RxD  
TxD  
Input/  
Serial interface serial clock input/output  
output  
P22  
P72/ASCK  
P23  
Output Serial interface automatic transmit/receive strobe output  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Serial interface automatic transmit/receive busy input  
Asynchronous serial interface serial data input  
P24  
P70/SI2  
P71/SO2  
P72/SCK2  
P00/INTP0  
P01/INTP1  
P33  
Output Asynchronous serial interface serial data output  
ASCK  
TI00  
TI01  
TI1  
Input  
Asynchronous serial interface serial clock input  
External count clock input to 16-bit timer (TM0)  
Capture trigger signal input to capture register (CR00)  
External count clock input to 8-bit timer (TM1)  
External count clock input to 8-bit timer (TM2)  
16-bit timer (TM0) output (also used for 14-bit PWM output)  
8-bit timer (TM1) output  
Input  
Input  
TI2  
P34  
TO0  
TO1  
TO2  
PCL  
BUZ  
P30  
Input  
Output  
P31  
8-bit timer (TM2) output  
P32  
Output Clock output (for main system clock and subsystem clock trimming)  
Output Buzzer output  
Input  
Input  
Input  
P35  
P36  
RTP0 to RTP7 Output Real-time output port outputting data in synchronization with trigger  
P120 to P127  
62  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
(2) Pins other than port pins (2/2)  
Pin Name Input/Output  
Function  
After Reset Alternate Function  
AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory  
A8 to A15 Output High-order address bus when expanding external memory  
Input  
Input  
P40 to P47  
P50 to P57  
P64  
RD  
WR  
Strobe signal output for read operation from external memory  
Strobe signal output for write operation to external memory  
Wait insertion when accessing external memory  
Strobe output externally latching address information output to ports 4,  
5 to access external memory  
Output  
Input  
P65  
WAIT  
ASTB  
Input  
Input  
Input  
P66  
Output  
P67  
ANI0 to ANI7 Input  
A/D converter analog input  
Input  
Input  
P10 to P17  
ANO0, ANO1 Output D/A converter analog output  
P130, P131  
AVREF0  
AVREF1  
AVDD  
AVSS  
RESET  
X1  
Input  
Input  
A/D converter reference voltage input  
D/A converter reference voltage input  
A/D converter analog power supply. Connect to VDD.  
A/D and D/A converter ground potential. Connect to VSS.  
System reset input  
Input  
Input  
Crystal connection for main system clock oscillation  
X2  
XT1  
Input  
Crystal connection for subsystem clock oscillation  
Input  
P07  
XT2  
VDD  
Positive power supply  
High-voltage application for program write/verify. Directly connect to  
VSS in normal operating mode.  
VPP  
VSS  
Ground potential  
IC  
Internally connected. Directly connect to the VSS pin.  
3.1.2 PROM programming mode pins (PROM versions only)  
Pin Name Input/Output  
Function  
PROM programming mode setting.  
RESET  
Input  
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,  
the PROM programming mode is set.  
VPP  
Input  
Input  
High-voltage application for PROM programming mode setting and program write/verify.  
Address bus  
A0 to A16  
D0 to D7 Input/output Data bus  
CE  
OE  
Input  
Input  
Input  
PROM enable input/program pulse input  
Read strobe input to PROM  
PGM  
VDD  
Program/program inhibit input in PROM programming mode  
Positive power supply  
VSS  
Ground potential  
63  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.2 Description of Pin Functions  
3.2.1 P00 to P07 (Port 0)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt  
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for  
subsystem oscillation.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
P00 and P07 function as input-only ports and P01 to P06 function as input/output ports.  
P01 to P06 can be specified for input or output ports in 1-bit units with a port mode register 0 (PM0). When  
they are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor  
option register L (PUOL).  
(2) Control mode  
In this mode, these ports function as an external interrupt request input, an external count clock input to the  
timer, and crystal connection for subsystem clock oscillation.  
(a) INTP0 to INTP6  
INTP0 to INTP6 are external interrupt request input pins which can specify valid edges (rising edge, falling  
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture  
trigger signal input pin with a valid edge input.  
(b) TI00  
Pin for external count clock input to 16-bit timer/event counter  
(c) TI01  
Pin for capture trigger signal to capture register (CR00) of 16-bit timer/event counter  
(d) XT1  
Crystal connect pin for subsystem clock oscillation  
64  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.2.2 P10 to P17 (Port 1)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog  
input.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports.  
They can be specified in 1-bit units as input or output ports with a port mode register 1 (PM1). If used as input  
ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L  
(PUOL).  
(2) Control mode  
These ports function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistor is  
automatically disabled when the pins specified for analog input.  
3.2.3 P20 to P27 (Port 2)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/  
from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be used  
to them by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy  
input, and strobe output functions.  
(a) SI0, SI1, SO0, SO1  
Serial interface serial data input/output pins  
(b) SCK0 and SCK1  
Serial interface serial clock input/output pins  
(c) SB0 and SB1  
NEC standard serial bus interface input/output pins  
65  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
(d) BUSY  
Serial interface automatic transmit/receive busy input pins  
(e) STB  
Serial interface automatic transmit/receive strobe output pins  
Caution  
When this port is used as a serial interface, the I/O and output latches must be set  
according to the function the user requires. For the setting, refer to Figure 16-4 “Serial  
Operation Mode Register 0 Format” and Figure 18-3 “Serial Operation Mode Register  
1 Format.”  
3.2.4 P30 to P37 (Port 3)  
These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock  
output and buzzer output.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as timer input/output, clock output, and buzzer output.  
(a) TI1 and TI2  
Pin for external count clock input to the 8-bit timer/event counter.  
(b) TO0 to TO2  
Timer output pins.  
(c) PCL  
Clock output pin.  
(d) BUZ  
Buzzer output pin.  
66  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.2.5 P40 to P47 (Port 4)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus.  
The test input flag (KRIF) can be set to 1 by detecting a falling edge.  
The following operating mode can be specified in 8-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports  
by using the memory expansion mode register (MM). When they are used as input ports, on-chip pull-up  
resistors can be used by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as low-order address/data bus pins (AD0 to AD7) in external memory expansion mode.  
When pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled.  
3.2.6 P50 to P57 (Port 5)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus.  
Port 5 can drive LEDs directly.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input/output ports with  
port mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by  
defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as high-order address bus pins (A8 to A15) in external memory expansion mode. When  
pins are used as an address bus, the on-chip pull-up resistor is automatically disabled.  
3.2.7 P60 to P67 (Port 6)  
These are 8-bit input/output ports. Besides serving as input/output ports, they are used for control in external  
memory expansion mode. P60 to P63 can drive LEDs directly.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 6 (PM6).  
P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.  
When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor  
option register L (PUOL).  
(2) Control mode  
These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.  
When a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled.  
Caution When external wait is not used in external memory expansion mode, P66 can be used as an  
input/output port.  
67  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.2.8 P70 to P72 (Port 7)  
This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/  
output and clock input/output functions.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
Port 7 functions as a 3-bit input/output port. 1-bit-units specification as an input port or output port is possible  
by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
Port 7 functions as serial interface data input/output and clock input/output.  
(a) SI2, SO2  
Serial interface serial data input/output pins  
(b) SCK2  
Serial interface serial clock input/output pin.  
(c) RxD, TxD  
Asynchronous serial interface serial data input/output pins.  
(d) ASCK  
Asynchronous serial interface serial clock input/output pin.  
Caution When this port is used as a serial interface, the I/O and output latches must be set according  
to the function the user requires.  
For the setting, see the operation mode setting list in Table 19-2 “Serial Interface Channel  
2”.  
68  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.2.9 P120 to P127 (Port 12)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 12 (PM12). When they are used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register H (PUOH).  
(2) Control mode  
These ports function as real-time output ports (RTP0 to RTP7) outputting data in synchronization with a trigger.  
3.2.10 P130 and P131 (Port 13)  
These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog  
output.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 2-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 13 (PM13). When they are used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register H (PUOH).  
(2) Control mode  
These ports allow D/A converter analog output (ANO0 and ANO1).  
Caution When only either one of the D/A converter channels is used with AVREF1< VDD, the other pins  
that are not used as analog outputs must be set as follows:  
• Set PM13x bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin  
to VSS.  
• Set PM13x bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch  
to 0, to output low level from the pin.  
3.2.11 AVREF0  
A/D converter reference voltage input pin.  
When A/D converter is not used, connect this pin to VSS.  
3.2.12 AVREF1  
D/A converter reference voltage input pin.  
When D/A converter is not used, connect this pin to VDD.  
69  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.2.13 AVDD  
Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D  
converter is not used.  
3.2.14 AVSS  
This is a ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the VSS  
pin even when neither A/D nor D/A converter is used.  
3.2.15 RESET  
This is a low-level active system reset input pin.  
3.2.16 X1 and X2  
Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its  
inverted signal to X2.  
3.2.17 XT1 and XT2  
Crystal resonator connect pins for subsystem clock oscillation.  
For external clock supply, input it to XT1 and its inverted signal to XT2.  
3.2.18 VDD  
Positive power supply pin  
3.2.19 VSS  
Ground potential pin  
3.2.20 VPP (PROM versions only)  
High-voltage apply pin for PROM programming mode setting and program write/verify. Directly connect to VSS  
in the normal operating mode.  
3.2.21 IC (Mask ROM version only)  
The IC (Internally Connected) pin is provided to set the test mode to check the µPD78054 Subseries before  
shipment. Directly connect this pin to the VSS with the shortest possible wire in the normal operating mode.  
When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins  
is too long or an external noise is input to the IC pin, the user's program may not run normally.  
Directly connect IC pins to VSS pins.  
VSS IC  
As short as possible  
70  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
3.3 Input/output Circuits and Recommended Connection of Unused Pins  
Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.  
Refer to Figure 3-1 for the configuration of the input/output circuit of each type.  
Table 3-1. Pin Input/Output Circuit Types (1/2)  
Input/Output  
Circuit Type  
Pin Name  
P00/INTP0/TI00  
Input/Output  
Input  
Recommended Connection of Unused Pins  
Connect to VSS.  
2
P01/INTP1/TI01  
P02/INTP2  
P03/INTP3  
P04/INTP4  
P05/INTP5  
P06/INTP6  
P07/XT1  
Individually connect to VSS via a resistor.  
8-A  
Input/Output  
16  
11  
Input  
Connect to VDD.  
P10/ANI0 to P17/ANI7  
P20/SI1  
8-A  
5-A  
8-A  
5-A  
8-A  
P21/SO1  
P22/SCK1  
P23/STB  
P24/BUSY  
P25/SI0/SB0  
P26/SO0/SB1  
P27/SCK0  
P30/TO0  
10-A  
Individually connect to VDD or VSS via a  
resistor.  
Input/Output  
P31/TO1  
5-A  
8-A  
P32/TO2  
P33/TI1  
P34/TI2  
P35/PCL  
P36/BUZ  
5-A  
P37  
P40/AD0 to P47/AD7  
5-E  
5-A  
Input/Output  
Input/output  
Individually connect to VDD via a resistor.  
Individually connect to VDD or VSS via a  
resistor.  
P50/A8 to P57/A15  
71  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
Table 3-1. Pin Input/Output Circuit Types (2/2)  
Input/Output  
Circuit Type  
Pin Name  
Input/Output  
Input/output  
Recommended Connection of Unused Pins  
P60 to P63 (Mask ROM version)  
13-B  
Individually connect to VDD via a resistor.  
P60 to P63 (PROM version)  
P64/RD  
13-D  
5-A  
Input/output  
Individually connect to VDD or VSS via a resistor.  
P65/WR  
P66/WAIT  
P67/ASTB  
P70/SI2/RxD  
P71/SO2/TxD  
P72/SCK2/ASCK  
P120/RTP0 to P127/RTP7  
P130/ANO0, P131/ANO1  
RESET  
8-A  
5-A  
8-A  
5-A  
12-A  
2
Input/output  
Input  
Individually connect to VSS via a resistor.  
Leave open.  
XT2  
16  
AVREF0  
Connect to VSS.  
Connect to VDD.  
AVREF1  
AVDD  
AVSS  
Connect to VSS.  
IC (Mask ROM version)  
VPP (PROM version)  
Directly connect to VSS.  
72  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
Figure 3-1. Pin Input/Output Circuit of List (1/2)  
Type 2  
Type 8-A  
VDD  
pullup  
enable  
P-ch  
IN  
VDD  
data  
P-ch  
IN/OUT  
Schmitt-Triggered Input with  
Hysteresis Characteristics  
output  
disable  
N-ch  
Type 10-A  
Type 5-A  
VDD  
VDD  
pullup  
enable  
pullup  
enable  
P-ch  
P-ch  
VDD  
VDD  
data  
P-ch  
data  
P-ch  
IN/OUT  
IN/OUT  
output  
disable  
open-drain  
output disable  
N-ch  
N-ch  
input  
enable  
VDD  
Type 5-E  
Type 11  
VDD  
pullup  
enable  
P-ch  
pullup  
enable  
P-ch  
VDD  
data  
VDD  
P-ch  
IN/OUT  
data  
P-ch  
output  
disable  
N-ch  
P-ch  
N-ch  
IN/OUT  
comparator  
+
output  
disable  
N-ch  
VREF (Threshold voltage)  
input  
enable  
73  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 3 PIN FUNCTION (µPD78054 Subseries)  
Figure 3-1. Pin Input/Output Circuit of List (2/2)  
Type 12-A  
Type 13-D  
VDD  
IN/OUT  
pullup  
enable  
P-ch  
data  
output disable  
N-ch  
VDD  
VDD  
data  
P-ch  
IN/OUT  
output  
disable  
N-ch  
P-ch  
RD  
input  
enable  
P-ch  
N-ch  
medium breakdown  
input buffer  
analog output  
voltage  
Type 13-B  
Type 16  
VDD  
Mask  
Option  
feedback  
cut-off  
IN/OUT  
P-ch  
data  
output disable  
N-ch  
VDD  
P-ch  
RD  
XT1  
XT2  
medium breakdown  
input buffer  
74  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.1 Pin Function List  
4.1.1 Normal operating mode pins  
(1) Port pins (1/3)  
Pin Name Input/Output  
Function  
Input only  
After Reset Alternate Function  
P00  
P01  
P02  
P03  
P04  
P05  
P06  
Input  
Input  
INTP0/TI00  
INTP1/TI01  
INTP2  
Input/output mode can be specified  
in 1-bit units.  
Input/  
Port 0.  
When used as an input port, an  
on-chip pull-up resistor can be used  
by software.  
INTP3  
Input  
output  
8-bit input/output port.  
INTP4  
INTP5  
INTP6  
Note1  
P07  
Input  
Input only  
Input  
Input  
XT1  
P10 to P17  
Port 1.  
8-bit input/output port.  
Input/  
Input/output mode can be specified in 1-bit units.  
ANI0 to ANI7  
output  
When used as input port, an on-chip pull-up resistor can be used by  
Note2  
software  
.
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
SI1  
SO1  
Port 2.  
SCK1  
Input/  
8-bit input/output port.  
STB  
Input  
output  
Input/output mode can be specified in1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
BUSY  
SI0/SB0/SDA0  
SO0/SB1/SDA1  
SCK0/SCL  
Notes 1. When the P07/XT1 pin is used as an input port, set the bit 6 (FRC) of the processor clock control register  
(PCC) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator).  
2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, set port 1 to input  
mode. The on-chip pull-up resistor will automatically be disabled.  
75  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
(1) Port pins (2/3)  
Pin Name Input/Output  
Function  
After Reset Alternate Function  
P30  
P31  
TO0  
TO1  
TO2  
P32  
P33  
P34  
P35  
P36  
P37  
Port 3.  
8-bit input/output port.  
Input/  
TI1  
Input  
output  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
TI2  
PCL  
BUZ  
Port 4.  
8-bit input/output port.  
Input/  
Input/output mode can be specified in 8-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
P40 to P47  
Input  
AD0 to AD7  
output  
Test input flag (KRIF) is set to 1 by falling edge detection.  
Port 5.  
8-bit input/output port.  
Input/  
LED can be driven directly.  
P50 to P57  
Input  
A8 to A15  
output  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
P60  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
N-ch open drain input/output port.  
On-chip pull-up resistor can be  
specified by mask option.  
(Mask ROM version only).  
LEDs can be driven directly.  
Port 6.  
Input/  
8-bit input/output port.  
Input/output mode can be  
specified in 1-bit units.  
output  
When used as an input port, an  
on-chip pull-up resistor can be used  
by software.  
Input  
RD  
WR  
WAIT  
ASTB  
Port 7.  
P70  
P71  
P72  
SI2/RxD  
SO2/TxD  
3-bit input/output port.  
Input/  
Input  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
output  
SCK2/ASCK  
76  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
(1) Port pins (3/3)  
Pin Name Input/Output  
Function  
After Reset Alternate Function  
P120 to P127 Input/  
output  
Port 12.  
8-bit input/output port.  
Input  
RTP0 to RTP7  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
P130 to P131  
Input/  
Port 13.  
Input  
ANO0 to ANO1  
output  
2-bit input/output port.  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by  
software.  
77  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
(2) Pins other than port pins (1/2)  
Pin Name Input/Output  
INTP0  
Function  
After Reset Alternate Function  
P00/TI00  
P01/TI01  
P02  
INTP1  
INTP2  
External interrupt request inputs with specifiable valid edges (rising  
edge, falling edge, both rising and falling edges).  
INTP3  
INTP4  
INTP5  
INTP6  
SI0  
Input  
Input  
P03  
P04  
P05  
P06  
P25/SB0/SDA0  
P20  
SI1  
Input  
Serial interface serial data input  
Input  
SI2  
P70/RxD  
P26/SB1/SDA1  
P21  
SO0  
SO1  
SO2  
SB0  
Output Serial interface serial data output  
Input  
Input  
P71/TxD  
P25/SI0/SDA0  
P26/SO0/SDA1  
P25/SI0/SB0  
P26/SO0/SB1  
P27/SCL  
P22  
Input/  
Serial interface serial data input/output  
output  
SB1  
SDA0  
SDA1  
SCK0  
SCK1  
SCK2  
SCL  
Input/  
output Serial interface serial clock input/output  
Input  
P72/ASCK  
P27/SCK0  
P23  
STB  
Output Serial interface automatic transmit/receive strobe output  
Input  
Input  
Input  
Input  
Input  
Input  
BUSY  
RxD  
Input  
Input  
Serial interface automatic transmit/receive busy input  
Asynchronous serial interface serial data input  
P24  
P70/SI2  
P71/SO2  
P72/SCK2  
P00/INTP0  
P01/INTP1  
P33  
TxD  
Output Asynchronous serial interface serial data output  
ASCK  
TI00  
TI01  
TI1  
Input  
Input  
Asynchronous serial interface serial clock input  
External count clock input to 16-bit timer (TM0)  
Capture trigger signal input to capture register (CR00)  
External count clock input to 8-bit timer (TM1)  
External count clock input to 8-bit timer (TM2)  
TI2  
P34  
TO0  
Output 16-bit timer (TM0) output (also used for 14-bit PWM output)  
8-bit timer (TM1) output  
Input  
P30  
TO1  
P31  
8-bit timer (TM2) output  
TO2  
P32  
PCL  
Output Clock output (for main system clock and subsystem clock trimming)  
Output Buzzer output  
Input  
Input  
Input  
P35  
BUZ  
P36  
RTP0 to RTP7 Output Real-time output port outputting data in synchronization with trigger  
P120 to P127  
78  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
(2) Pins other than port pins (2/2)  
Pin Name Input/Output  
Function  
After Reset Alternate Function  
AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory  
A8 to A15 Output High-order address bus when expanding external memory  
Input  
Input  
Input  
P40 to P47  
P50 to P57  
P64  
Output  
RD  
WR  
Strobe signal output for read operation from external memory  
Strobe signal output for write operation to external memory  
Wait insertion when accessing external memory  
Strobe output externally latching address information output to ports 4,  
5 to access external memory  
P65  
WAIT  
ASTB  
Input  
Input  
Input  
P66  
Output  
P67  
ANI0 to ANI7 Input  
A/D converter analog input  
Input  
Input  
P10 to P17  
ANO0, ANO1 Output D/A converter analog output  
P130, P131  
AVREF0  
AVREF1  
AVDD  
AVSS  
RESET  
X1  
Input  
Input  
A/D converter reference voltage input  
D/A converter reference voltage input  
A/D converter analog power supply. Connect to VDD.  
A/D and D/A converter ground potential. Connect to VSS.  
System reset input  
Input  
Input  
Crystal connection for main system clock oscillation  
X2  
Crystal connection for subsystem clock oscillation  
XT1  
Input  
Input  
P07  
XT2  
VDD  
Positive power supply  
High-voltage application for program write/verify. Directly connect to  
VSS in normal operating mode.  
VPP  
VSS  
Ground potential  
IC  
Internally connected. Connect directly to VSS.  
4.1.2 PROM programming mode pins (PROM versions only)  
Pin Name Input/Output  
Function  
PROM programming mode setting.  
RESET  
Input  
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,  
the PROM programming mode is set.  
VPP  
Input  
Input  
High-voltage application for PROM programming mode setting and program write/verify.  
Address bus  
A0 to A16  
D0 to D7 Input/output Data bus  
CE  
OE  
Input  
Input  
Input  
PROM enable input/program pulse input  
Read strobe input to PROM  
PGM  
VDD  
Program/program inhibit input in PROM programming mode  
Positive power supply  
VSS  
Ground potential  
79  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2 Description of Pin Functions  
4.2.1 P00 to P07 (Port 0)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt  
request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for  
subsystem oscillation.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
P00 and P07 function as input-only ports and P01 to P06 function as input/output ports.  
P01 to P06 can be specified for input or output ports in 1-bit units with a port mode register 0 (PM0). When  
they are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor  
option register L (PUOL).  
(2) Control mode  
In this mode, these ports function as an external interrupt request input, an external count clock input to the  
timer, and crystal connection for subsystem clock oscillation.  
(a) INTP0 to INTP6  
INTP0 to INTP6 are external interrupt request input pins which can specify valid edges (rising edge, falling  
edge, and both rising and falling edges). INTP0 or INTP1 becomes a 16-bit timer/event counter capture  
trigger signal input pin with a valid edge input.  
(b) TI00  
Pin for external count clock input to 16-bit timer/event counter  
(c) TI01  
Pin for capture trigger signal to capture register (CR00) of 16-bit timer/event counter  
(d) XT1  
Crystal connect pin for subsystem clock oscillation  
80  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2.2 P10 to P17 (Port 1)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog  
input.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports.  
They can be specified in 1-bit units as input or output ports with a port mode register 1 (PM1). If used as input  
ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L  
(PUOL).  
(2) Control mode  
These ports function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistor is  
automatically disabled when the pins specified for analog input.  
4.2.3 P20 to P27 (Port 2)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/  
from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be used  
to them by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy  
input, and strobe output functions.  
(a) SI0, SI1, SO0, SO1, SB0, SB1, SDA0, SDA1  
Serial interface serial data input/output pins  
(b) SCK0, SCK1, SCL  
Serial interface serial clock input/output pins  
(c) BUSY  
Serial interface automatic transmit/receive busy input pins  
(d) STB  
Serial interface automatic transmit/receive strobe output pins  
Caution  
When this port is used as a serial interface, the I/O and output latches must be set  
according to the function the user requires. For the setting, refer to Figure 17-4 “Serial  
Operation Mode Register 0 Format” and Figure 18-3 “Serial Operation Mode Register  
1 Format.”  
81  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2.4 P30 to P37 (Port 3)  
These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock  
output, and buzzer output.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as timer input/output, clock output, and buzzer output.  
(a) TI1 and TI2  
Pin for external count clock input to the 8-bit timer/event counter.  
(b) TO0 to TO2  
Timer output pins.  
(c) PCL  
Clock output pin.  
(d) BUZ  
Buzzer output pin.  
4.2.5 P40 to P47 (Port 4)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus.  
The test input flag (KRIF) can be set to 1 by detecting a falling edge.  
The following operating mode can be specified in 8-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 8-bit units for input or output ports  
by using the memory expansion mode register (MM). When they are used as input ports, on-chip pull-up  
resistors can be used by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as low-order address/data bus pins (AD0 to AD7) in external memory expansion mode.  
When pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled.  
82  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2.6 P50 to P57 (Port 5)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus.  
Port 5 can drive LEDs directly.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input/output ports with  
port mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by  
defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
These ports function as high-order address bus pins (A8 to A15) in external memory expansion mode. When  
pins are used as an address bus, the on-chip pull-up resistor is automatically disabled.  
4.2.7 P60 to P67 (Port 6)  
These are 8-bit input/output ports. Besides serving as input/output ports, they are used for control in external  
memory expansion mode. P60 to P63 can drive LEDs directly.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 6 (PM6).  
P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the mask option.  
When P64 to P67 are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor  
option register L (PUOL).  
(2) Control mode  
These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.  
When a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled.  
Caution When external wait is not used in external memory expansion mode, P66 can be used as an  
input/output port.  
83  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2.8 P70 to P72 (Port 7)  
This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/  
output and clock input/output functions.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
Port 7 functions as a 3-bit input/output port. 1-bit-units specification as an input port or output port is possible  
by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register L (PUOL).  
(2) Control mode  
Port 7 functions as serial interface data input/output and clock input/output.  
(a) SI2, SO2  
Serial interface serial data input/output pins  
(b) SCK2  
Serial interface serial clock input/output pin.  
(c) RxD, TxD  
Asynchronous serial interface serial data input/output pins.  
(d) ASCK  
Asynchronous serial interface serial clock input/output pin.  
Caution When this port is used as a serial interface, the I/O and output latches must be set according  
to the function the user requires.  
For the setting, see to the operation mode setting list in Table 19-2 “Serial Interface Channel  
2”.  
4.2.9 P120 to P127 (Port 12)  
These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 8-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 12 (PM12). When they are used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register H (PUOH).  
(2) Control mode  
These ports function as real-time output ports (RTP0 to RTP7) outputting data in synchronization with a trigger.  
84  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2.10 P130 and P131 (Port 13)  
These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog  
output.  
The following operating modes can be specified in 1-bit units.  
(1) Port mode  
These ports function as 2-bit input/output ports. They can be specified in 1-bit units as input or output ports  
with port mode register 13 (PM13). When they are used as input ports, on-chip pull-up resistors can be used  
by defining the pull-up resistor option register H (PUOH).  
(2) Control mode  
These ports allow D/A converter analog output (ANO0 and ANO1).  
Caution When only either one of the D/A converter channels is used with AVREF1< VDD, the other pins  
that are not used as analog outputs must be set as follows:  
Set PM13x bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin  
to VSS.  
Set PM13x bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch  
to 0, to output low level from the pin.  
4.2.11 AVREF0  
A/D converter reference voltage input pin.  
When A/D converter is not used, connect this pin to VSS.  
4.2.12 AVREF1  
D/A converter reference voltage input pin.  
When D/A converter is not used, connect this pin to VDD.  
4.2.13 AVDD  
Analog power supply pin of A/D converter. Always use the same voltage as that of the VDD pin even when A/D  
converter is not used.  
4.2.14 AVSS  
This is a ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the VSS  
pin even when neither A/D nor D/A converter is used.  
4.2.15 RESET  
This is a low-level active system reset input pin.  
85  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.2.16 X1 and X2  
Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its  
inverted signal to X2.  
4.2.17 XT1 and XT2  
Crystal resonator connect pins for subsystem clock oscillation.  
For external clock supply, input it to XT1 and its inverted signal to XT2.  
4.2.18 VDD  
Positive power supply pin  
4.2.19 VSS  
Ground potential pin  
4.2.20 VPP (PROM versions only)  
High-voltage apply pin for PROM programming mode setting and program write/verify. Directly connect to VSS  
in the normal operating mode.  
4.2.21 IC (Mask ROM version only)  
The IC (Internally Connected) pin is provided to set the test mode to check the µPD78054Y Subseries before  
shipment. Directly connect the pin to the VSS with the shortest possible wire in the normal operating mode.  
When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins  
is too long or an external noise is input to the IC pin, the user's program may not run normally.  
Directly connect IC pins to VSS pins.  
VSS IC  
As short as possible  
86  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
4.3 Input/output Circuits and Recommended Connection of Unused Pins  
Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.  
Refer to Figure 4-1 for the configuration of the input/output circuit of each type.  
Table 4-1. Pin Input/Output Circuit Types (1/2)  
Input/Output  
Circuit Type  
Pin Name  
P00/INTP0/TI00  
Input/Output  
Input  
Recommended Connection of Unused Pins  
Connect to VSS.  
2
P01/INTP1/TI01  
P02/INTP2  
P03/INTP3  
P04/INTP4  
P05/INTP5  
P06/INTP6  
P07/XT1  
8-A  
Individually connect to VSS via a resistor.  
Input/Output  
16  
11  
Input  
Connect to VDD.  
P10/ANI0 to P17/ANI7  
P20/SI1  
8-A  
5-A  
8-A  
5-A  
8-A  
10-A  
P21/SO1  
P22/SCK1  
P23/STB  
P24/BUSY  
P25/SI0/SB0/SDA0  
P26/SO0/SB1/SDA1  
P27/SCK0/SCL  
P30/TO0  
Individually connect to VDD or VSS via a  
resistor.  
Input/Output  
5-A  
P31/TO1  
P32/TO2  
8-A  
5-A  
P33/TI1  
P34/TI2  
P35/PCL  
P36/BUZ  
P37  
P40/AD0 to P47/AD7  
5-E  
5-A  
Input/Output  
Input/output  
Individually connect to VDD via a resistor.  
Individually connect to VDD or VSS via a  
resistor.  
P50/A8 to P57/A15  
87  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
Table 4-1. Pin Input/Output Circuit Types (2/2)  
Input/Output  
Circuit Type  
Pin Name  
Input/Output  
Input/output  
Recommended Connection of Unused Pins  
P60 to P63 (Mask ROM version)  
P60 to P63 (PROM version)  
P64/RD  
13-B  
Individually connect to VDD via a resistor.  
13-D  
5-A  
Input/output  
Individually connect to VDD or VSS via a resistor.  
P65/WR  
P66/WAIT  
P67/ASTB  
P70/SI2/RxD  
8-A  
5-A  
8-A  
5-A  
12-A  
2
P71/SO2/TxD  
P72/SCK2/ASCK  
P120/RTP0 to P127/RTP7  
P130/ANO0 to P131/ANO1  
RESET  
Input/output  
Input  
Individually connect to VSS via a resistor.  
Leave open.  
XT2  
16  
AVREF0  
Connect to VSS.  
Connect to VDD.  
AVREF1  
AVDD  
AVSS  
Connect to VSS.  
IC (Mask ROM version)  
VPP (PROM version)  
Directly connect to VSS.  
88  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
Figure 4-1. Pin Input/Output Circuit of List (1/2)  
Type 2  
Type 8-A  
VDD  
pullup  
enable  
P-ch  
IN  
VDD  
data  
P-ch  
IN/OUT  
Schmitt-Triggered Input with  
Hysteresis Characteristics  
output  
disable  
N-ch  
Type 10-A  
Type 5-A  
VDD  
VDD  
pullup  
enable  
pullup  
enable  
P-ch  
P-ch  
VDD  
VDD  
data  
P-ch  
data  
P-ch  
IN/OUT  
IN/OUT  
output  
disable  
open-drain  
output disable  
N-ch  
N-ch  
input  
enable  
VDD  
Type 5-E  
Type 11  
VDD  
pullup  
enable  
P-ch  
pullup  
enable  
P-ch  
VDD  
data  
VDD  
P-ch  
IN/OUT  
data  
P-ch  
output  
disable  
N-ch  
P-ch  
N-ch  
IN/OUT  
comparator  
+
output  
disable  
N-ch  
VREF (Threshold voltage)  
input  
enable  
89  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 4 PIN FUNCTION (µPD78054Y Subseries)  
Figure 4-1. Pin Input/Output Circuit of List (2/2)  
Type 12-A  
Type 13-D  
VDD  
IN/OUT  
pullup  
enable  
P-ch  
data  
output disable  
N-ch  
VDD  
VDD  
data  
P-ch  
IN/OUT  
output  
disable  
N-ch  
P-ch  
RD  
input  
enable  
P-ch  
N-ch  
medium breakdown  
input buffer  
analog output  
voltage  
Type 13-B  
Type 16  
VDD  
Mask  
Option  
feedback  
cut-off  
IN/OUT  
P-ch  
data  
output disable  
N-ch  
VDD  
P-ch  
RD  
XT1  
XT2  
medium breakdown  
input buffer  
90  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.1 Memory Spaces  
Each product of the µPD78054 and 78054Y Subseries can access the memory space of 64 Kbytes. Figures 5-1  
to 5-8 show memory maps.  
Figure 5-1. Memory Map (µPD78052, 78052Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
512 × 8 bits  
FD00H  
FCFFH  
Reserved  
FAE0H  
FADFH  
3FFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
0FFFH  
Reserved  
FA80H  
FA7FH  
0800H  
07FFH  
External Memory  
47744 × 8 bits  
Program  
memory  
space  
0080H  
007FH  
4000H  
3FFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Internal ROM  
16384 × 8 bits  
0000H  
0000H  
91  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-2. Memory Map (µPD78053, 78053Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
5FFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
Reserved  
0FFFH  
FA80H  
FA7FH  
0800H  
07FFH  
External Memory  
39552 × 8 bits  
Program  
memory  
space  
0080H  
007FH  
6000H  
5FFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Internal ROM  
24576 × 8 bits  
0000H  
0000H  
92  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-3. Memory Map (µPD78054, 78054Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
7FFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
Reserved  
0FFFH  
FA80H  
FA7FH  
0800H  
07FFH  
External Memory  
31360 × 8 bits  
Program  
memory  
space  
0080H  
007FH  
8000H  
7FFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Internal ROM  
32768 × 8 bits  
0000H  
0000H  
93  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-4. Memory Map (µPD78P054)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
7FFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
0FFFH  
Reserved  
FA80H  
FA7FH  
0800H  
07FFH  
External Memory  
31360 × 8 bits  
Program  
memory  
space  
0080H  
007FH  
8000H  
7FFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Internal PROM  
32768 × 8 bits  
0000H  
0000H  
94  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-5. Memory Map (µPD78055, 78055Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
9FFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
Reserved  
0FFFH  
FA80H  
FA7FH  
0800H  
07FFH  
External Memory  
23168 × 8 bits  
Program  
memory  
space  
0080H  
007FH  
A000H  
9FFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Internal ROM  
40960 × 8 bits  
0000H  
0000H  
95  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-6. Memory Map (µPD78056, 78056Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
BFFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
Reserved  
0FFFH  
FA80H  
FA7FH  
0800H  
07FFH  
External Memory  
14976 × 8 bits  
Program  
memory  
space  
0080H  
007FH  
C000H  
BFFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Internal ROM  
49152 × 8 bits  
0000H  
0000H  
96  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-7. Memory Map (µPD78058, 78058Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
EFFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
0FFFH  
Reserved  
F800H  
F7FFH  
Internal  
Expansion RAM  
1024 × 8 bits  
0800H  
07FFH  
F400H  
F3FFH  
ReservedNote  
0080H  
007FH  
F000H  
EFFFH  
CALLT Table Area  
Vector Table Area  
0040H  
003FH  
Program  
memory  
space  
Internal ROM  
61440 × 8 bits  
0000H  
0000H  
Note When internal ROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH  
can be used as external memory by setting the internal ROM size to less than 56K bytes by the  
memory size switching register (IMS).  
97  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-8. Memory Map (µPD78P058, µPD78P058Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
FF00H  
FEFFH  
General Registers  
32 × 8 bits  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
EFFFH  
Internal Buffer RAM  
Program Area  
CALLF Entry Area  
Program Area  
32 × 8 bits  
FAC0H  
FABFH  
Data memory  
space  
1000H  
0FFFH  
Reserved  
F800H  
F7FFH  
Internal  
Expansion RAM  
1024 × 8 bits  
0800H  
07FFH  
F400H  
F3FFH  
ReservedNote  
0080H  
007FH  
F000H  
EFFFH  
CALLT Table Area  
Vector Table Area  
Program  
memory  
space  
0040H  
003FH  
Internal PROM  
61440 × 8 bits  
0000H  
0000H  
Note When internal PROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH  
can be used as external memory by setting the internal PROM size to less than 56K bytes by the  
memory size switching register (IMS).  
98  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.1.1 Internal program memory space  
The internal program memory space stores programs and table data. Normally, they are addressed with a program  
counter (PC).  
Each product of the µPD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below.  
Table 5-1. Internal ROM Capacity  
Internal ROM  
Part number  
Type  
Capacity  
µPD78052, 78052Y  
µPD78053, 78053Y  
µPD78054, 78054Y  
µPD78055, 78055Y  
µPD78056, 78056Y  
µPD78058, 78058Y  
µPD78P054  
Mask ROM  
16384 x 8 bits (0000H to 3FFFH)  
24576 x 8 bits (0000H to 5FFFH)  
32768 x 8 bits (0000H to 7FFFH)  
40960 x 8 bits (0000H to 9FFFH)  
49152 x 8 bits (0000H to BFFFH)  
61440 x 8 bits (0000H to EFFFH)  
32768 x 8 bits (0000H to 7FFFH)  
61440 x 8 bits (0000H to EFFFH)  
PROM  
µPD78P058, 78P058Y  
The following areas are allocated to the internal program memory space.  
(1) Vector table area  
The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start  
addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the  
16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.  
Table 5-2. Vector Table  
Vector Table Address  
0000H  
Interrupt Source  
RESET input  
INTWDT  
INTP0  
Vector Table Address  
0018H  
Interrupt Source  
INTSER  
0004H  
0006H  
0008H  
000AH  
000CH  
000EH  
0010H  
0012H  
0014H  
0016H  
001AH  
001CH  
001EH  
0020H  
0022H  
0024H  
0026H  
0028H  
003EH  
INTSR/INTCSI2  
INTST  
INTP1  
INTTM3  
INTP2  
INTTM00  
INTTM01  
INTTM1  
INTP3  
INTP4  
INTP5  
INTTM2  
INTP6  
INTAD  
INTCSI0  
INTCSI1  
BRK  
(2) CALLT instruction table area  
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).  
(3) CALLF instruction entry area  
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).  
99  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.1.2 Internal data memory space  
The µPD78054 and 78054Y subseries units incorporate the following RAMs.  
(1) Internal high-speed RAM  
The µPD78054 and 78054Y Subseries are provided with the internal high-speed RAM as shown below.  
Table 5-3. Internal High-Speed RAM Capacity  
Part Number  
µPD78052, 78052Y  
µPD78053, 78053Y  
µPD78054, 78054Y  
µPD78P054  
Internal High-Speed RAM  
512 × 8 bits (FD00H to FEFFH)  
1024 × 8 bits (FB00H to FEFFH)  
µPD78055, 78055Y  
µPD78056, 78056Y  
µPD78058, 78058Y  
µPD78P058, 78P058Y  
In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the  
32-byte area FEE0H to FEFFH.  
The internal high-speed RAM can also be used as a stack memory.  
(2) Buffer RAM  
Buffer RAM is allocated to the 32-byte area from FAC0H to FADFH. The buffer RAM is used to store transmit/  
receive data of serial interface channel 1 (in three-wire serial I/O mode with automatic transfer/receive  
function). If the three-wire serial I/O mode with automatic transfer/receive function is not used, the buffer RAM  
can also be used as normal RAM. Buffer RAM can also be used as normal RAM.  
(3) Internal expansion RAM (µPD78058, 78058Y, 78P058, 78P058Y only)  
Internal expansion RAM is allocated to the 1024-byte area from F400H to F7FFH.  
5.1.3 Special Function Register (SFR) area  
An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH. (Refer  
to Table 5-6. Special-Function Register List in 5.2.3 Special Function Register (SFR)).  
Caution Do not access addresses where the SFR is not assigned.  
5.1.4 External memory space  
The external memory space is accessible by setting the memory expansion mode register (MM). External memory  
space can store program, table data, etc. and allocate peripheral devices.  
100  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.1.5 Data memory addressing  
The method to specify the address of the instruction to be executed next, or the address of a register or memory  
to be manipulated when an instruction is executed is called addressing.  
The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to  
5.3 Instruction Address Addressing).  
To address the memory that is manipulated when an instruction is executed, the µPD78054, 78054Y Subseries  
is provided with many addressing modes with a high operability. Especially at addresses corresponding to data  
memory area, particular addressing modes are possible to meet the functions of the special function registers (SFRs)  
and general registers. This area is between FD00H and FFFFH for the µPD78052 and 78052Y, and between FB00H  
and FFFFH for the µPD78053, 78053Y, 78054, 78054Y, 78P054, 78055, 78055Y, 78056, 78056Y, 78058, 78058Y,  
78P058, and 78P058Y. The data memory space is the entire 64K-byte space (0000H to FFFFH). Figure 5-9 to 5-16  
show the data memory addressing modes. For details of each addressing, refer to 5.4 Operand Address  
Addressing.  
Figure 5-9. Data Memory Addressing (µPD78052, 78052Y)  
FFFFH  
Special Function  
Registers (SFRs)  
SFR Addressing  
256 × 8 bits  
FF20H  
FF1FH  
FF00H  
FEFFH  
General Registers  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
512 × 8 bits  
FE20H  
FE1FH  
FD00H  
FCFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
FA80H  
FA7FH  
Based Indexed  
Addressing  
External Memory  
47744 × 8 bits  
4000H  
3FFFH  
Internal ROM  
16384 × 8 bits  
0000H  
101  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-10. Data Memory Addressing (µPD78053, 78053Y)  
FFFFH  
Special Function  
Registers (SFRs)  
SFR Addressing  
256 × 8 bits  
FF20H  
FF1FH  
FF00H  
FEFFH  
General Registers  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
FA80H  
FA7FH  
Based Indexed  
Addressing  
External Memory  
39552 × 8 bits  
6000H  
5FFFH  
Internal ROM  
24576 × 8 bits  
0000H  
102  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-11. Data Memory Addressing (µPD78054, 78054Y)  
FFFFH  
Special Function  
Registers (SFRs)  
SFR Addressing  
256 × 8 bits  
FF20H  
FF1FH  
FF00H  
FEFFH  
General Registers  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
FA80H  
FA7FH  
Based Indexed  
Addressing  
External Memory  
31360 × 8 bits  
8000H  
7FFFH  
Internal ROM  
32768 × 8 bits  
0000H  
103  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-12. Data Memory Addressing (µPD78P054)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
SFR Addressing  
FF20H  
FF1FH  
FF00H  
FEFFH  
GeneralRegisters  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
FA80H  
FA7FH  
Based Indexed  
Addressing  
External Memory  
31360 × 8 bits  
8000H  
7FFFH  
Internal PROM  
32768 × 8 bits  
0000H  
104  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-13. Data Memory Addressing (µPD78055, 78055Y)  
FFFFH  
Special Function  
Registers (SFRs)  
SFR Addressing  
256 × 8 bits  
FF20H  
FF1FH  
FF00H  
FEFFH  
General Registers  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
FA80H  
FA7FH  
Based Indexed  
Addressing  
External Memory  
23168 × 8 bits  
A000H  
9FFFH  
Internal ROM  
40960 × 8 bits  
0000H  
105  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-14. Data Memory Addressing (µPD78056, 78056Y)  
FFFFH  
Special Function  
Registers (SFRs)  
SFR Addressing  
256 × 8 bits  
FF20H  
FF1FH  
FF00H  
FEFFH  
General Registers  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
FA80H  
FA7FH  
Based Indexed  
Addressing  
External Memory  
14976 × 8 bits  
C000H  
BFFFH  
Internal ROM  
49152 × 8 bits  
0000H  
106  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-15. Data Memory Addressing (µPD78058, 78058Y)  
FFFFH  
Special Function  
Registers (SFRs)  
SFR Addressing  
256 × 8 bits  
FF20H  
FF1FH  
FF00H  
FEFFH  
General Registers  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
F800H  
F7FFH  
Based Indexed  
Addressing  
Internal Expansion RAM  
1024 × 8 bits  
F400H  
F3FFH  
ReservedNote  
F000H  
EFFFH  
Internal ROM  
61440 × 8 bits  
0000H  
Note When internal ROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH  
can be used as external memory by setting the internal ROM size to less than 56K bytes by the  
memory size switching register.  
107  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-16. Data Memory Addressing (µPD78P058, 78P058Y)  
FFFFH  
Special Function  
Registers (SFRs)  
256 × 8 bits  
SFR Addressing  
FF20H  
FF1FH  
FF00H  
FEFFH  
GeneralRegisters  
Register Addressing  
32 × 8 bits  
Short Direct  
Addressing  
FEE0H  
FEDFH  
Internal High-speed RAM  
1024 × 8 bits  
FE20H  
FE1FH  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Direct Addressing  
Internal Buffer RAM  
32 × 8 bits  
Register Indirect  
Addressing  
FAC0H  
FABFH  
Based Addressing  
Reserved  
F800H  
F7FFH  
Based Indexed  
Addressing  
Internal Expansion RAM  
1024 × 8 bits  
F400H  
F3FFH  
ReservedNote  
F000H  
EFFFH  
Internal PROM  
61440 × 8 bits  
0000H  
Note When internal PROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH  
can be used as external memory by setting the internal PROM size to less than 56K bytes by the  
memory size switching register (IMS).  
108  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.2 Processor Registers  
The µPD78054 and 78054Y subseries units incorporate the following processor registers.  
5.2.1 Control registers  
The control registers control the program sequence, statuses and stack memory. The control registers consist  
of a program counter (PC), a program status word (PSW) and a stack pointer (SP).  
(1) Program counter (PC)  
The program counter is a 16-bit register which holds the address information of the next program to be  
executed.  
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction  
to be fetched. When a branch instruction is executed, immediate data and register contents are set.  
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.  
Figure 5-17. Program Counter Configuration  
15  
0
PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6  
PC PC15  
PC5 PC4 PC3  
PC2 PC1 PC0  
(2) Program status word (PSW)  
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.  
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW  
instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.  
RESET input sets the PSW to 02H.  
Figure 5-18. Program Status Word Configuration  
7
0
PSW  
IE  
Z
RBS1  
AC  
RBS0  
0
ISP  
CY  
(a) Interrupt enable flag (IE)  
This flag controls the interrupt request acknowledge operations of the CPU.  
When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status).  
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled  
with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority  
specify flag.  
The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt is  
acknowledged, and set to 1 when the EI instruction is executed.  
(b) Zero flag (Z)  
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.  
(c) Register bank select flags (RBS0 and RBS1)  
These are 2-bit flags to select one of the four register banks.  
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction  
execution is stored.  
109  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
(d) Auxiliary carry flag (AC)  
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all  
other cases.  
(e) In-service priority flag (ISP)  
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the  
vectored interrupt whose priority is specified by the priority specify flag registers (PR0L, PR0H, and PR1L)  
(Refer to 21.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) to be low is disabled.  
Whether the interrupt is actually acknowledged is controlled by the status of the interrupt enable flag (IE).  
(f) Carry flag (CY)  
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out  
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation  
instruction execution.  
(3) Stack pointer (SP)  
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM  
area can be set as the stack area. The following shows the internal high-speed RAM area of each product.  
Table 5-4. Internal High-Speed RAM Area  
Part Number  
µPD78052, 78052Y  
µPD78053, 78053Y  
µPD78054, 78054Y  
µPD78P054  
Internal High-Speed RAM Area  
FD00H to FEFFH  
FB00H to FEFFH  
µPD78055, 78055Y  
µPD78056, 78056Y  
µPD78058, 78058Y  
µPD78P058, 78P058Y  
110  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-19. Stack Pointer Configuration  
15  
0
SP  
PC15  
PC12 PC11  
PC14 PC13  
PC10 PC9  
PC5  
PC3  
PC0  
PC8 PC7 PC6  
PC4  
PC2 PC1  
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from  
the stack memory.  
Each stack operation saves/resets data as shown in Figures 5-20 and 5-21.  
Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before  
instruction execution.  
Figure 5-20. Data to be Saved to Stack Memory  
Interrupt and  
BRK Instruction  
PUSH rp Instruction  
CALL, CALLF, and  
CALLT Instruction  
_
_
_
_
SP SP  
SP  
3
3
2
1
_
_
_
_
_
_
SP SP  
SP  
2
2
1
SP SP  
SP  
2
2
1
PC7-PC0  
PC15-PC8  
PSW  
Register Pair Lower  
Register Pair Upper  
SP  
PC7-PC0  
SP  
SP  
SP  
PC15-PC8  
SP  
SP  
SP  
Figure 5-21. Data to be Reset from Stack Memory  
RETI and RETB  
Instruction  
POP rp Instruction  
RET Instruction  
SP  
SP + 1  
Register Pair Lower  
Register Pair Upper  
SP  
SP + 1  
SP  
PC7-PC0  
PC7-PC0  
PC15-PC8  
PSW  
SP + 1  
SP + 2  
PC15-PC8  
SP SP + 2  
SP SP + 2  
SP SP + 3  
111  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.2.2 General registers  
A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks,  
each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H).  
Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register  
(AX, BC, DE and HL).  
They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names  
(R0 to R7 and RP0 to RP3).  
Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because  
of the 4-register bank configuration, an efficient program can be created by switching between a register for normal  
processing and a register for interruption for each bank.  
Table 5-5. Correspondent Table of Absolute Addresses in the General Registers  
Bank  
Register  
Absolute  
Address  
Bank  
Register  
Absolute  
Address  
Functional Name Absolute Name  
Functional Name Absolute Name  
BANK0  
H
L
R7  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
R7  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
FEFFH  
BANK2  
H
L
R7  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
R7  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
FEEFH  
FEFEH  
FEFDH  
FEFCH  
FEFBH  
FEFAH  
FEF9H  
FEF8H  
FEF7H  
FEF6H  
FEF5H  
FEF4H  
FEF3H  
FEF2H  
FEF1H  
FEF0H  
FEEEH  
FEEDH  
FEECH  
FEEBH  
FEEAH  
FEE9H  
FEE8H  
FEE7H  
FEE6H  
FEE5H  
FEE4H  
FEE3H  
FEE2H  
FEE1H  
FEE0H  
D
E
B
C
A
X
H
L
D
E
B
C
A
X
H
L
BANK1  
BANK3  
D
E
B
C
A
X
D
E
B
C
A
X
112  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Figure 5-22. General Register Configuration  
(a) Absolute Name  
16-Bit Processing  
8-Bit Processing  
R7  
FEFFH  
BANK0  
BANK1  
BANK2  
BANK3  
RP3  
RP2  
RP1  
RP0  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
FEF8H  
FEF7H  
FEF0H  
FEEFH  
FEE8H  
FEE7H  
FEE0H  
15  
0
7
0
(b) Function Name  
16-Bit Processing  
8-Bit Processing  
H
FEFFH  
BANK0  
BANK1  
BANK2  
BANK3  
HL  
DE  
BC  
L
D
E
B
C
A
X
FEF8H  
FEF7H  
FEF0H  
FEEFH  
FEE8H  
FEE7H  
AX  
FEE0H  
15  
0
7
0
113  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.2.3 Special Function Register (SFR)  
Unlike a general register, each special-function register has special functions.  
It is allocated in the FF00H to FFFFH area.  
The special-function register can be manipulated like the general register, with the operation, transfer and bit  
manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type.  
Each manipulation bit unit can be specified as follows.  
• 1-bit manipulation  
Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).  
This manipulation can also be specified with an address.  
• 8-bit manipulation  
Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).  
This manipulation can also be specified with an address.  
• 16-bit manipulation  
Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).  
When addressing an address, describe an even address.  
Table 5-6 gives a list of special-function registers. The meaning of items in the table is as follows.  
• Symbol  
Symbols indicating the addresses of special function register. These symbols are reserved words for the RA78K/  
0 and defined by header file sfrbit.h for the CC78K/0, and can be used as the operands of instructions when  
the RA78K/0, ID78K0-NS, ID78K0, and SM78K0 are used.  
• R/W  
Indicates whether the corresponding special-function register can be read or written.  
R/W : Read/write enable  
R
: Read only  
: Write only  
W
• Manipulatable bit units  
indicates bit units (1, 8 or 16 bits) in which the register can be manipulated. — indicates that the register cannot  
be manipulated in the indicated bit units.  
• After reset  
Indicates each register status upon RESET input.  
114  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Table 5-6. Special-Function Register List (1/3)  
Manipulatable Bit Unit  
Address  
Special-Function Register (SFR) Name  
Symbol  
R/W  
After Reset  
8 bits  
16 bits  
1 bit  
FF00H  
FF01H  
FF02H  
FF03H  
FF04H  
FF05H  
FF06H  
FF07H  
FF0CH  
FF0DH  
FF10H  
FF11H  
FF12H  
FF13H  
FF14H  
FF15H  
FF16H  
FF17H  
FF18H  
FF19H  
FF1AH  
FF1BH  
FF1FH  
FF20H  
FF21H  
FF22H  
FF23H  
FF25H  
FF26H  
FF27H  
FF2CH  
FF2DH  
FF30H  
FF31H  
FF34H  
FF36H  
Port0  
Port1  
Port2  
Port3  
Port4  
Port5  
Port6  
Port7  
Port12  
Port13  
P0  
P1  
00H  
P2  
P3  
P4  
R/W  
P5  
Undefined  
00H  
P6  
P7  
P12  
P13  
Capture/compare register 00  
Capture/compare register 01  
CR00  
CR01  
Undefined  
16-bit timer register  
TM0  
R
0000H  
Compare register 10  
CR10  
CR20  
R/W  
R
Undefined  
00H  
Compare register 20  
8-bit timer register 1  
TM1  
TM2  
SIO0  
TMS  
8-bit timer register 2  
Serial I/O shift register 0  
Serial I/O shift register 1  
A/D conversion result register  
Port mode register 0  
R/W  
R
SIO1  
ADCR  
PM0  
Undefined  
Port mode register 1  
PM1  
Port mode register 2  
PM2  
Port mode register 3  
PM3  
R/W  
FFH  
Port mode register 5  
PM5  
Port mode register 6  
PM6  
Port mode register 7  
PM7  
Port mode register 12  
PM12  
PM13  
RTBL  
RTBH  
RTPM  
RTPC  
Port mode register 13  
Real-time output buffer register L  
Real-time output buffer register H  
Real-time output port mode register  
Real-time output port control register  
00H  
115  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Table 5-6. Special-Function Register List (2/3)  
Manipulatable Bit Unit  
Address  
Special-Function Register (SFR) Name  
Symbol  
R/W  
After Reset  
0000H  
8 bits  
16 bits  
1 bit  
FF38H  
FF39H  
(Note)  
Correction address register 0  
CORAD0  
CORAD1  
(Note)  
FF3AH  
FF3BH  
Correction address register 1  
00H  
FF40H  
FF41H  
FF42H  
FF43H  
FF47H  
FF48H  
FF49H  
FF4AH  
FF4CH  
FF4EH  
FF4FH  
FF60H  
Timer clock select register 0  
TCL0  
TCL1  
TCL2  
TCL3  
SCS  
Timer clock select register 1  
Timer clock select register 2  
Timer clock select register 3  
R/W  
88H  
00H  
Sampling clock select register  
16-bit timer mode control register  
8-bit timer mode control register 1  
Watch timer mode control register  
Capture/compare control register 0  
16-bit timer output control register  
8-bit timer output control register  
Serial operating mode register 0  
TMC0  
TMC1  
TMC2  
CRC0  
TOC0  
TOC1  
CSIM0  
04H  
00H  
FF61H  
FF62H  
FF63H  
FF68H  
FF69H  
FF6AH  
FF6BH  
FF70H  
FF71H  
FF72H  
FF73H  
Serial bus interface control register  
Slave address register  
SBIC  
SVA  
Undefined  
00H  
Interrupt timing specify register  
SINT  
Serial operating mode register 1  
Automatic data transmit/receive control register  
Automatic data transmit/receive address pointer  
Automatic data transmit/receive interval specify register  
Asynchronous serial interface mode register  
Asynchronous serial interface status register  
Serial operating mode register 2  
Baud rate generator control register  
Transmit shift register  
CSIM1  
ADTC  
ADTP  
ADTI  
ASIM  
ASIS  
R
CSIM2  
BRGC  
RW  
TXS  
RXB  
W
R
SIO2  
FFH  
FF74H  
Receive buffer register  
R/W  
FF80H  
FF84H  
FF8AH  
FF90H  
FF91H  
FF98H  
A/D converter mode register  
A/D converter input select register  
ADM  
01H  
00H  
ADIS  
CORCN  
DACS0  
DACS1  
DAM  
(Note)  
Correction control register  
D/A conversion value set register 0  
D/A conversion value set register 1  
D/A converter mode register  
Note This register is provided only in the µPD78058, 78P058, 78058Y and 78P058Y.  
116  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
Table 5-6. Special-Function Register List (3/3)  
Manipulatable Bit Unit  
Address  
Special-Function Register (SFR) Name  
Symbol  
R/W  
R/W  
After Reset  
Undefined  
00H  
8 bits  
16 bits  
1 bit  
Note1  
FFD0H to  
FFDFH  
External access area  
IF0L  
IF0H  
IF0  
FFE0H  
FFE1H  
FFE2H  
FFE4H  
FFE5H  
FFE6H  
Interrupt request flag register 0L  
Interrupt request flag register 0H  
Interrupt request flag register 1L  
Interrupt mask flag register 0L  
Interrupt mask flag register 0H  
Interrupt mask flag register 1L  
IF1L  
MK0L  
MK0H  
MK0  
FFH  
MK1L  
PR0  
PR0L  
PR0H  
FFE8H  
FFE9H  
FFEAH  
FFECH  
FFEDH  
FFF0H  
FFF2H  
FFF3H  
FFF4H  
Priority order specify flag register 0L  
Priority order specify flag register 0H  
Priority order specify flag register 1L  
External interrupt mode register 0  
External interrupt mode register 1  
Memory size switching register  
Oscillation mode selection register  
Pull-up resistor option register H  
Internal expansion RAM size  
PR1L  
00H  
INTM0  
INTM1  
IMS  
Note2  
OSMS  
PUOH  
IXS  
W
R/W  
W
00H  
0AH  
(Note3)  
switching register  
R/W  
FFF6H  
FFF7H  
FFF8H  
FFF9H  
FFFAH  
FFFBH  
Key return mode register  
KRM  
PUOL  
MM  
02H  
00H  
10H  
00H  
Pull-up resistor option register L  
Memory expansion mode register  
Watchdog timer mode register  
Oscillation stabilization time select register  
Processor clock control register  
WDTM  
OSTS  
PCC  
04H  
Notes 1. The external access area cannot be accessed in SFR addressing. Access the area with direct  
addressing.  
2. The value after reset depends on products.  
µPD78052, 78052Y: 44H, µPD78053, 78053Y: C6H, µPD78054, 78054Y: C8H, µPD78P054: C8H,  
µPD78055, 78055Y: CAH, µPD78056, 78056Y: CCH, µPD78058, 78058Y: CFH, µPD78P058,  
78P058Y: CFH  
3. This register is provided only in the µPD78058, 78058Y, 78P058, and 78P058Y.  
117  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.3 Instruction Address Addressing  
An instruction address is determined by program counter (PC) contents. The contents of PC are normally  
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each  
time another instruction is executed. When a branch instruction is executed, the branch destination information is  
set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 Series User’s  
Manual, Instruction (U12326E).  
5.3.1 Relative addressing  
[Function]  
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the  
start address of the following instruction is transferred to the program counter (PC) and branched. The  
displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit.  
In the relative addressing modes, execution branches in a relative range of –128 to +127 from the first address  
of the next instruction.  
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.  
[Illustration]  
15  
0
0
PC indicates the start address  
of the instruction  
...  
PC  
+
after the BR instruction.  
15  
8
7
6
S
α
jdisp8  
15  
0
PC  
When S = 0, all bits of α are 0.  
When S = 1, all bits of α are 1.  
118  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.3.2 Immediate addressing  
[Function]  
Immediate data in the instruction word is transferred to the program counter (PC) and branched.  
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.  
The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11  
instruction branches to an area of addresses 0800H through 0FFFH.  
[Illustration]  
In the case of CALL !addr16 and BR !addr16 instructions  
7
0
CALL or BR  
Low Addr.  
High Addr.  
15  
8 7  
0
PC  
In the case of CALLF !addr11 instruction  
7
6
4
3
0
fa10–8  
CALLF  
fa7–0  
15  
11 10  
1
8 7  
0
PC  
0
0
0
0
119  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.3.3 Table indirect addressing  
[Function]  
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the  
immediate data of an operation code are transferred to the program counter (PC) and branched.  
Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction  
references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire  
memory space.  
[Illustration]  
7
6
1
5
1
0
1
Operation Code  
1
ta4–0  
15  
8
0
7
0
6
1
5
1
0
0
Effective Address  
0
0
0
0
0
0
0
7
Memory (Table)  
Low Addr.  
0
High Addr.  
Effective Address+1  
15  
8
7
0
PC  
5.3.4 Register addressing  
[Function]  
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)  
and branched.  
This function is carried out when the BR AX instruction is executed.  
[Illustration]  
7
0
8
7
7
0
0
rp  
A
X
15  
PC  
120  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4 Operand Address Addressing  
The following various methods are available to specify the register and memory (addressing) which undergo  
manipulation during instruction execution.  
5.4.1 Implied addressing  
[Function]  
The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly)  
addressed.  
Of the µPD78054 and 78054Y subseries instruction words, the following instructions employ implied addressing.  
Instruction  
MULU  
Register to be Specified by Implied Addressing  
A register for multiplicand and AX register for product storage  
AX register for dividend and quotient storage  
DIVUW  
ADJBA/ADJBS  
ROR4/ROL4  
A register for storage of numeric values which become decimal correction targets  
A register for storage of digit data which undergoes digit rotation  
[Operand format]  
Because implied addressing can be automatically employed with an instruction, no particular operand format is  
necessary.  
[Description example]  
In the case of MULU X  
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,  
the A and AX registers are specified by implied addressing.  
121  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.2 Register addressing  
[Function]  
This addressing accesses a general register as an operand. The general register accessed is specified by the  
register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code.  
Register addressing is carried out when an instruction with the following operand format is executed. When an  
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.  
[Operand format]  
Identifier  
Description  
X, A, C, B, E, D, L, H  
AX, BC, DE, HL  
r
rp  
'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute  
names (R0 to R7 and RP0 to RP3).  
[Description example]  
MOV A, C; when selecting C register as r  
Operation code  
0 1 1 0 0 0 1 0  
Register specify code  
INCW DE; when selecting DE register pair as rp  
Operation code 1 0 0 0 0 1 0 0  
Register specify code  
122  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.3 Direct addressing  
[Function]  
This addressing directly addresses the memory indicated by the immediate data in an instruction word.  
[Operand format]  
Identifier  
addr16  
Description  
Label or 16-bit immediate data  
[Description example]  
MOV A, !0FE00H; when setting !addr16 to FE00H  
Operation code  
1 0 0 0 1 1 1 0  
OP code  
00H  
0 0 0 0 0 0 0 0  
1 1 1 1 1 1 1 0  
FEH  
[Illustration]  
7
0
OP code  
saddr16 (low)  
saddr16 (high)  
Memory  
123  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.4 Short direct addressing  
[Function]  
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.  
The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An  
internal high-speed RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to  
FF1FH, respectively.  
The SFR area (FF00H through FF1FH) to which short direct addressing is applied is a part of the entire SFR  
area. To this area, ports frequently accessed by the program, and the compare registers and capture registers  
of timer/event counters are mapped. These SFRs can be manipulated with a short byte length and a few clocks.  
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,  
bit 8 is set to 1. Refer to [Illustration] on next page.  
[Operand format]  
Identifier  
saddr  
Description  
Label of FE20H to FF1FH immediate data  
saddrp  
Label of FE20H to FF1FH immediate data (even address only)  
[Description example]  
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H  
Operation code  
0 0 0 1 0 0 0 1  
0 0 1 1 0 0 0 0  
0 1 0 1 0 0 0 0  
OP code  
30H (saddr-offset)  
50H (immediate data)  
[Illustration]  
7
0
OP code  
saddr-offset  
Short Direct Memory  
15  
1
8
7
0
Effective Address  
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0  
When 8-bit immediate data is 00H to 1FH, α = 1  
124  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.5 Special-Function Register (SFR) addressing  
[Function]  
The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction  
word.  
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR  
mapped at FF00H to FF1FH can be accessed with short direct addressing.  
[Operand format]  
Identifier  
sfr  
Description  
Special-function register name  
16-bit manipulatable special-function register name (even address only)  
sfrp  
[Description example]  
MOV PM0, A; when selecting PM0 (FF20H) as sfr  
Operation code 1 1 1 1 0 1 1 0  
OP code  
0 0 1 0 0 0 0 0  
20H (sfr-offset)  
[Illustration]  
7
0
OP code  
sfr-offset  
SFR  
15  
1
8
7
0
Effective Address  
1
1
1
1
1
1
1
125  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.6 Register indirect addressing  
[Function]  
This addressing addresses the memory with the contents of a register pair specified as an operand. The register  
pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code  
in an instruction code. This addressing can be carried out for all the memory spaces.  
[Operand format]  
Identifier  
Description  
[DE], [HL]  
[Description example]  
MOV A, [DE]; when selecting [DE] as register pair  
Operation code  
1 0 0 0 0 1 0 1  
[Illustration]  
15  
8
7
7
0
0
DE  
D
E
Memory address specified  
by register pair DE  
Memory  
Contents of addressed  
memory are transferred.  
7
0
A
126  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.7 Based addressing  
[Function]  
This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair  
which is used as a base register and by using the result of the addition. The HL register pair to be accessed  
is in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by  
expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing  
can be carried out for all the memory spaces.  
[Operand format]  
Identifier  
Description  
[HL + byte]  
[Description example]  
MOV A, [HL + 10H]; when setting byte to 10H  
Operation code  
1 0 1 0 1 1 1 0  
0 0 0 1 0 0 0 0  
127  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 5 CPU ARCHITECTURE  
5.4.8 Based indexed addressing  
[Function]  
This addressing addresses the memory by adding the contents of the HL register, which is used as a base register,  
to the contents of the B or C register specified in the instruction word, and by using the result of the addition.  
The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select  
flags (RBS0 and RBS1). The addition is performed by extending the contents of the B or C register to 16 bits  
as a positive number. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory  
spaces.  
[Operand format]  
Identifier  
Description  
[HL + B], [HL + C]  
[Description example]  
In the case of MOV A, [HL + B]  
Operation code  
1 0 1 0 1 0 1 1  
5.4.9 Stack addressing  
[Function]  
The stack area is indirectly addressed with the stack pointer (SP) contents.  
This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN  
instructions are executed or the register is saved/reset upon generation of an interrupt request.  
Stack addressing enables to address the internal high-speed RAM area only.  
[Description example]  
In the case of PUSH DE  
Operation code  
1 0 1 1 0 1 0 1  
128  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.1 Port Functions  
The µPD78054 and 78054Y subseries units incorporate two input ports and sixty-seven input/output ports. Figure  
6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably  
varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins.  
Figure 6-1. Port Types  
P50  
P00  
Port 0  
Port 1  
Port 2  
Port 5  
P57  
P60  
P07  
P10  
Port 6  
Port 7  
P67  
P70  
P17  
P20  
P72  
P120  
P27  
P30  
Port 12  
Port 13  
P127  
P130  
Port 3  
Port 4  
P131  
P37  
P40-P47  
8
129  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Table 6-1. Port Functions (µPD78054 subseries) (1/2)  
Pin Name  
P00  
Function  
Alternate Function  
INTP0/TI00  
INTP1/TI01  
Input/output mode can be specified in 1-bit INTP2  
Input only  
P01  
P02  
P03  
Port 0.  
units.  
INTP3  
P04  
8-bit input/output port.  
When used as an input port, an on-chip  
pull-up resistor can be used by software.  
INTP4  
P05  
INTP5  
P06  
INTP6  
P07  
Input only  
XT1  
Port 1.  
8-bit input/output port.  
P10 to P17  
ANI0 to ANI7  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
P30  
P31  
P32  
P33  
P34  
P35  
P36  
P37  
SI1  
SO1  
Port 2.  
SCK1  
STB  
8-bit input/output port.  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
BUSY  
SI0/SB0  
SO0/SB1  
SCK0  
TO0  
TO1  
Port 3.  
TO2  
8-bit input/output port.  
TI1  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
TI2  
PCL  
BUZ  
Port 4.  
8-bit input/output port.  
P40 to P47  
Input/output mode can be specified in 8-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
Test input flag (KRIF) is set to 1 by falling edge detection.  
Port 5.  
AD0 to AD7  
8-bit input/output port.  
P50 to P57  
LED can be driven directly.  
A8 to A15  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
130  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Table 6-1. Port Functions (µPD78054 subseries) (2/2)  
Pin Name  
P60  
Function  
Alternate Function  
N-ch open-drain input/output port.  
On-chip pull-up resistor can be specified by  
mask option. (Mask ROM version only).  
P61  
P62  
Port 6.  
8-bit input/output port.  
Input/output mode can be specified in 1-bit When used as an input port, an on-chip  
P63  
LEDs can be driven directly.  
P64  
RD  
WR  
P65  
units.  
pull-up resistor can be used by software.  
P66  
WAIT  
ASTB  
P67  
Port 7.  
P70  
P71  
P72  
SI2/RxD  
SO2/TxD  
3-bit input/output port.  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
Port 12.  
SCK2/ASCK  
8-bit input/output port.  
P120 to P127  
RTP0 to RTP7  
ANO0, ANO1  
Input/output mode can be specified in 1-bit units.  
When used as an input port, on-chip pull-up resistor can be used by software.  
Port 13.  
2-bit input/output port.  
P130 and P131  
Input/output mode can be specified in 1-bit units.  
When used as an input port, on-chip pull-up resistor can be used by software.  
131  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Table 6-2. Port Functions (µPD78054Y subseries) (1/2)  
Pin Name  
P00  
Function  
Alternate Function  
INTP0/TI00  
INTP1/TI01  
INTP2  
Input only  
P01  
P02  
Input/output mode can be specified in 1-bit  
units.  
P03  
Port 0.  
INTP3  
P04  
8-bit input/output port.  
When used as an input port, an on-chip  
pull-up resistor can be used by software.  
INTP4  
P05  
INTP5  
P06  
INTP6  
P07  
Input only  
XT1  
Port 1.  
P10 to P17  
8-bit input/output port.  
ANI0 to ANI7  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
P30  
P31  
P32  
P33  
P34  
P35  
P36  
P37  
SI1  
SO1  
Port 2.  
SCK1  
STB  
8-bit input/output port.  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
BUSY  
SI0/SB0/SDA0  
SO0/SB1/SDA1  
SCK0/SCL  
TO0  
TO1  
Port 3.  
TO2  
8-bit input/output port.  
TI1  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
TI2  
PCL  
BUZ  
Port 4.  
8-bit input/output port.  
P40 to P47  
Input/output mode can be specified in 8-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
Test input flag (KRIF) is set to 1 by falling edge detection.  
Port 5.  
AD0 to AD7  
8-bit input/output port.  
P50 to P57  
LED can be driven directly.  
A8 to A15  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
132  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Table 6-2. Port Functions (µPD78054Y subseries) (2/2)  
Pin Name  
P60  
Function  
Alternate Function  
N-ch open drain input/output port.  
On-chip pull-up resistor can be specified by  
mask option. (Mask ROM version only).  
P61  
P62  
Port 6.  
8-bit input/output port.  
Input/output mode can be specified in 1-bit When used as an input port, an on-chip  
P63  
LEDs can be driven directly.  
P64  
RD  
WR  
P65  
units.  
pull-up resistor can be used by software.  
P66  
WAIT  
ASTB  
P67  
Port 7.  
P70  
P71  
P72  
SI2/RxD  
SO2/TxD  
3-bit input/output port.  
Input/output mode can be specified in 1-bit units.  
When used as an input port, an on-chip pull-up resistor can be used by software.  
Port 12.  
SCK2/ASCK  
8-bit input/output port.  
P120 to P127  
RTP0 to RTP7  
ANO0, ANO1  
Input/output mode can be specified in 1-bit units.  
When used as an input port, on-chip pull-up resistor can be used by software.  
Port 13.  
2-bit input/output port.  
P130 and P131  
Input/output mode can be specified in 1-bit units.  
When used as an input port, on-chip pull-up resistor can be used by software.  
133  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2 Port Configuration  
A port consists of the following hardware:  
Table 6-3. Port Configuration  
Item  
Configuration  
Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13)  
Pull-up resistor option register (PUOH, PUOL)  
Control register  
Note  
Memory expansion mode register (MM)  
Key return mode register (KRM)  
Total: 69 ports (2 inputs, 67 inputs/outputs)  
• Mask ROM version  
Port  
Pull-up resistor  
Total: 67 (software specifiable: 63, mask option: 4)  
• PROM version Total: 63  
Note MM specifies port 4 input/output.  
6.2.1 Port 0  
Port 0 is an 8-bit input/output port with output latch. P01 to P06 pins can specify the input mode/output mode in  
1-bit units with the port mode register 0 (PM0). P00 and P07 pins are input-only ports. When P01 to P06 pins are  
used as input ports, an on-chip pull-up resistor can be used to them in 6-bit units with a pull-up resistor option register  
L (PUOL).  
Alternate functions include external interrupt request input, external count clock input to the timer and crystal  
connection for subsystem clock oscillation.  
RESET input sets port 0 to input mode.  
Figures 6-2 and 6-3 show block diagrams of port 0.  
Caution Because port 0 also serves for external interrupt request input, when the port function output  
mode is specified and the output level is changed, the interrupt request flag is set. Thus, when  
the output mode is used, set the interrupt mask flag to 1.  
134  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Figure 6-2. P00 and P07 Block Diagram  
RD  
P00/INTP0/TI00,  
P07/XT1  
Figure 6-3. P01 to P06 Block Diagram  
VDD  
WRPUO  
PUO0  
P-ch  
RD  
Selector  
WRPORT  
P01/INTP1/TI01.  
P02/INTP2  
Output Latch  
(P01 to P06)  
P06/INTP6  
WRPM  
PM01-PM06  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 0 read signal  
WR : Port 0 write signal  
135  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.2 Port 1  
Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with  
a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used  
to them in 8-bit units with a pull-up resistor option register L (PUOL).  
Alternate functions include an A/D converter analog input.  
RESET input sets port 1 to input mode.  
Figure 6-4 shows a block diagram of port 1.  
Caution A pull-up resistor cannot be used for pins used as A/D converter analog input.  
Figure 6-4. P10 to P17 Block Diagram  
VDD  
WRPUO  
PUO1  
P-ch  
RD  
Selector  
WRPORT  
P10/ANI0,  
Output Latch  
(P10 to P17)  
P17/ANI7  
WRPM  
PM10-PM17  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 1 read signal  
WR : Port 1 write signal  
136  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.3 Port 2 (µPD78054 Subseries)  
Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in  
1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up  
resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).  
Alternate functions include serial interface data input/output, clock input/output, automatic transmit/receive busy  
input, and strobe output.  
RESET input sets port 2 to input mode.  
Figures 6-5 and 6-6 show block diagrams of port 2.  
Cautions 1. When used as a serial interface, set the input/output and output latch according to its  
functions. For the setting method, refer to Figure 16-4 Serial Operating Mode Register 0  
Format and Figure 18-3 Serial Operating Mode Register 1 Format.  
2. When reading the pin state in SBI mode, set PM2n bit of PM2 to 1 (n = 5, 6) (Refer to the  
description of (10) Discrimination of slave busy state in section 16.4.3 “SBI Mode  
Operation”).  
Figure 6-5. P20, P21, P23 to P26 Block Diagram  
VDD  
WRPUO  
PUO2  
P-ch  
RD  
Selector  
WRPORT  
P20/SI1,  
P21/SO1,  
P23/STB,  
P24/BUSY,  
Output Latch  
(P20, P21, P23-P26)  
P25/SI0/SB0,  
P26/SO0/SB1  
WRPM  
PM20, PM21  
PM23-PM26  
Alternate Function  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 2 read signal  
WR : Port 2 write signal  
137  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Figure 6-6. P22 and P27 Block Diagram  
VDD  
WRPUO  
PUO2  
P-ch  
RD  
Selector  
WRPORT  
Output Latch  
(P22, P27)  
P22/SCK1,  
P27/SCK0  
WRPM  
PM22, PM27  
Alternate Function  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 2 read signal  
WR : Port 2 write signal  
138  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.4 Port 2 (µPD78054Y Subseries)  
Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in  
1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up  
resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).  
Alternate functions include serial interface data input/output, clock input/output, automatic transmit/receive busy  
input, and strobe output.  
RESET input sets port 2 to input mode.  
Figures 6-7 and 6-8 show block diagrams of port 2.  
Caution When used as a serial interface, set the input/output and output latch according to its functions.  
For the setting method, refer to Figure 17-4 Serial Operating Mode Register 0 Format and Figure  
18-3 Serial Operating Mode Register 1 Format.  
Figure 6-7. P20, P21, P23 to P26 Block Diagram  
VDD  
WRPUO  
PUO2  
P-ch  
RD  
Selector  
WRPORT  
Output Latch  
(P20, P21, P23 to P26)  
P20/SI1,  
P21/SO1,  
P23/STB,  
P24/BUSY,  
P25/SI0/SB0/SDA0,  
P26/SO0/SB1/SDA1  
WRPM  
PM20, PM21  
PM23 to PM26  
Alternate Function  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 2 read signal  
WR : Port 2 write signal  
139  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Figure 6-8. P22 and P27 Block Diagram  
VDD  
WRPUO  
PUO2  
P-ch  
RD  
Selector  
WRPORT  
Output Latch  
(P22 and P27)  
P22/SCK1,  
P27/SCK0/SCL  
WRPM  
PM22, PM27  
Alternate Function  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 2 read signal  
WR : Port 2 write signal  
140  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.5 Port 3  
Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in  
1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up  
resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).  
Alternate functions include timer input/output, clock output and buzzer output.  
RESET input sets port 3 to input mode.  
Figure 6-9 shows a block diagram of port 3.  
Figure 6-9. P30 to P37 Block Diagram  
VDD  
WRPUO  
PUO3  
P-ch  
RD  
Selector  
WRPORT  
P30/TO0  
Output Latch  
(P30 to P37)  
P32/TO2,  
P33/TI1,  
P34/TI2,  
P35/PCL,  
P36/BUZ,  
P37  
WRPM  
PM30-PM37  
Alternate Function  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 3 read signal  
WR : Port 3 write signal  
141  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.6 Port 4  
Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in  
8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on-  
chip pull-up resistor can be used to them in 8-bit units with pull-up resistor option register L (PUOL).  
The test input flag (KRIF) can be set to 1 by detecting falling edges.  
Alternate function includes address/data bus function in external memory expansion mode.  
RESET input sets port 4 to input mode.  
Figures 6-10 and 6-11 show a block diagram of port 4 and block diagram of falling edge detection circuit,  
respectively.  
Figure 6-10. P40 to P47 Block Diagram  
VDD  
WRPUO  
PUO4  
P-ch  
RD  
Selector  
WRPORT  
P40/AD0  
Output Latch  
(P40 to P47)  
P47/AD7  
WRMM  
MM  
PUO : Pull-up resistor option register  
MM : Memory expansion mode register  
RD : Port 4 read signal  
WR : Port 4 write signal  
Figure 6-11. Block Diagram of Falling Edge Detection Circuit  
P40  
P41  
P42  
Falling Edge  
Detection Circuit  
P43  
P44  
P45  
P46  
P47  
KRIF Set Signal  
Standby Release  
Signal  
KRMK  
142  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.7 Port 5  
Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in  
1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up  
resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).  
Port 5 can drive LEDs directly.  
Alternate function includes address bus function in external memory expansion mode.  
RESET input sets port 5 to input mode.  
Figure 6-12 shows a block diagram of port 5.  
Figure 6-12. P50 to P57 Block Diagram  
VDD  
WRPUO  
PUO5  
P-ch  
RD  
Selector  
WRPORT  
P50/A8  
Output Latch  
(P50 to P57)  
P57/A15  
WRPM  
PM50-PM57  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 5 read signal  
WR : Port 5 write signal  
143  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.8 Port 6  
Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in  
1-bit units with the port mode register 6 (PM6).  
This port has functions related to pull-up resistors as shown below. These functions depending on whether the  
higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or PROM model is used.  
Table 6-4. Pull-up Resistor of Port 6  
Higher 4 Bits (P64 through P67 pins)  
Lower 4 bits (P60 through P63 pins)  
Mask ROM  
version  
On-chip pull-up resistor can be connected in 4-bit Pull-up resistor can be connected in 1-bit units by  
units by PUO6  
mask option  
PROM version  
Pull-up resistor is not connected  
PUO6: Bit 6 of pull-up resistor option register L (PUOL)  
Pins P60 to P63 can drive LEDs directly.  
Pins P64 to P67 also serve as control signal output in external memory expansion mode.  
RESET input sets port 6 to input mode.  
Figures 6-13 and 6-14 show block diagrams of port 6.  
Cautions 1. When external wait is not used in external memory expansion mode, P66 can be used as an  
input/output port.  
2. The value of the low-level input leakage current flowing to the P60 through P63 pins differ  
depending on the following conditions:  
[Mask ROM version]  
When pull-up resistor is connected: always –3 µA (MAX.)  
When pull-up resistor is not connected  
For duration of 1.5 clock (no wait) when instruction to read port 6 (P6) and port mode  
register 6 (PM6) is executed: –200 µA (MAX.)  
Other than above:  
–3 µA (MAX.)  
[PROM version]  
For duration of 1.5 clock (no wait) when instruction to read port 6 (P6) and port mode  
register 6 (PM6) is executed: –200 µA (MAX.)  
Other than above:  
–3 µA (MAX.)  
144  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Figure 6-13. P60 to P63 Block Diagram  
VDD  
RD  
Mask Option Resistor  
Mask ROM products  
only. PROM versions  
have no pull-up resistor.  
Selector  
WRPORT  
Output Latch  
(P60 to P63)  
P60-P63  
WRPM  
PM60-PM63  
PM : Port mode register  
RD : Port 6 read signal  
WR : Port 6 write signal  
Figure 6-14. P64 to P67 Block Diagram  
VDD  
WRPUO  
PUO6  
P-ch  
RD  
Selector  
WRPORT  
P64/RD,  
P65/WR,  
P66/WAIT,  
P67/ASTB  
Output Latch  
(P64 to P67)  
WRPM  
PM64-PM67  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 6 read signal  
WR : Port 6 write signal  
145  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.9 Port 7  
This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means  
of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can  
be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).  
Alternate functions include serial interface channel 2 data input/output and clock input/output.  
RESET input sets the input mode.  
Figures 6-15 and 6-16 show block diagrams of port 7.  
Caution When used as a serial interface, set the input/output and output latch according to its functions.  
For the setting method, refer to Table 19-2 Serial Interface Channel 2 Operating Mode Setting.  
Figure 6-15. P70 Block Diagram  
VDD  
WRPUO  
PUO7  
P-ch  
RD  
Selector  
WRPORT  
Output Latch  
P70/SI2/RxD  
(P70)  
WRPM  
PM70  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 7 read signal  
WR : Port 7 write signal  
146  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Figure 6-16. P71 and P72 Block Diagram  
VDD  
WRPUO  
PUO7  
P-ch  
RD  
Selector  
WRPORT  
Output Latch  
(P71 and P72)  
P71/SO2/TxD,  
P72/SCK2/ASCK  
WRPM  
PM71, PM72  
Alternate Function  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 7 read signal  
WR : Port 7 write signal  
147  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.10 Port 12  
This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means  
of port mode register 12 (PM12). When pins P120 to P127 are used as input port pins, an on-chip pull-up resistor  
can be used as an 8-bit unit by means of pull-up resistor option register H (PUOH).  
Alternate function includes real-time output.  
RESET input sets the input mode.  
Figure 6-17 shows a block diagram of port 12.  
Figure 6-17. P120 to P127 Block Diagram  
VDD  
WRPUO  
PUO12  
P-ch  
RD  
Selector  
WRPORT  
P120/RTP0  
Output Latch  
(P120 to P127)  
P127/RTP7  
WRPM  
PM120-PM127  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 12 read signal  
WR : Port 12 write signal  
148  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.2.11 Port 13  
This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means  
of port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor  
can be used as a 2-bit unit by means of pull-up resistor option register H (PUOH).  
Alternate function includes D/A converter analog output.  
RESET input sets the input mode.  
Figure 6-18 shows a block diagram of port 13.  
Caution When only either one of the D/A converter channels is used with AVREF1< VDD, the other pins  
that are not used as analog outputs must be set as follows:  
Set PM13. bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin  
to VSS.  
Set PM13x bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch  
to 0, to output low level from the pin.  
Figure 6-18. P130 and P131 Block Diagram  
VDD  
WRPUO  
PUO13  
P-ch  
RD  
Selector  
WRPORT  
P130/ANO0,  
P131/ANO1  
Output Latch  
(P130 and P131)  
WRPM  
PM130, PM131  
PUO : Pull-up resistor option register  
PM : Port mode register  
RD : Port 13 read signal  
WR : Port 13 write signal  
149  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.3 Port Function Control Registers  
The following four types of registers control the ports.  
• Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13)  
• Pull-up resistor option register (PUOH, PUOL)  
• Memory expansion mode register (MM)  
• Key return mode register (KRM)  
(1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13)  
These registers are used to set port input/output in 1-bit units.  
PM0 to PM3, PM5 to PM7, PM12, and PM13 are independently set with a 1-bit or 8-bit memory manipulation  
instruction  
RESET input sets registers to FFH.  
When port pins are used as the dual-function pins, set the port mode register and output latch according to  
Table 6-5.  
Cautions 1. Pins P00 and P07 are input-only pins.  
2. As port 0 has a dual function as external interrupt request input, when the port function  
output mode is specified and the output level is changed, the interrupt request flag is  
set. When the output mode is used, therefore, the interrupt mask flag should be set to  
1 beforehand.  
3. The memory expansion mode register (MM) specifies P40 to P47 as input/output pins.  
150  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Table 6-5. Port Mode Register and Output Latch Settings when Using Dual-Functions  
Dual-functions  
PM××  
P××  
Pin Name  
Name  
Input/Output  
P00  
P01  
INTP0  
TI00  
Input  
1 (Fixed)  
None  
Input  
1 (Fixed)  
None  
INTP1  
TI01  
Input  
1
×
Input  
1
×
P02 to P06  
INTP2 to INTP6  
XT1  
Input  
1
×
Note1  
P07  
Input  
1 (Fixed)  
None  
Note1  
P10 to P17  
P30 to P32  
P33, P34  
P35  
ANI0 to ANI7  
TO0 to TO2  
TI1, TI2  
PCL  
Input  
1
0
1
0
0
×
0
×
0
0
Output  
Input  
Output  
Output  
Input/Output  
Output  
Output  
Output  
Input  
P36  
BUZ  
Note2  
P40 to P47  
P50 to P57  
P64  
AD0 to AD7  
A8 to A15  
RD  
×
Note2  
×
Note2  
×
Note2  
P65  
WR  
×
Note2  
P66  
WAIT  
×
Note2  
P67  
ASTB  
Output  
Output  
Output  
×
P120 to P127  
RTP0 to RTP7  
ANO0, ANO1  
0
1
desired value  
(Note1)  
P130, P131  
×
Notes 1. If these ports are read out when these pins are used in the alternative function mode, undefined values  
are read.  
2. When the P40 to P47 pins P50 to P57 pins, and P64 to P67 pins are used for dual-functions, set the  
function by the memory extension mode register (MM).  
Cautions 1. When not using external wait in the external memory extension mode, the P66 pin can be used  
as an I/O port.  
2. When port 2 and port 7 are used for serial interface, the I/O latch or output latch must be  
set according to its function. For the setting methods, see Figure 16-4 “Serial Operation  
Mode Register 0 Format”, Figure 17-4 “Serial Operation Mode Register 0 Format”, Figure  
18-3 “Serial Operation Mode Register 1 Format”, and Table 19-2 “Serial Interface Channel  
2 Operating Mode Settings”.  
Remarks  
×
: don’t care  
PM×× : port mode register  
P×× : port output latch  
151  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
Figure 6-19. Port Mode Register Format  
After  
Reset  
Symbol  
PM0  
7
1
6
5
4
3
2
1
0
1
Address  
FF20H  
R/W  
R/W  
PM06 PM05 PM04 PM03 PM02 PM01  
FFH  
FFH  
FFH  
FFH  
FFH  
FFH  
FFH  
FFH  
FFH  
PM1  
PM2  
FF21H  
FF22H  
FF23H  
FF25H  
FF26H  
FF27H  
FF2CH  
FF2DH  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10  
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20  
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30  
PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50  
PM6  
PM7  
PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60  
1
1
1
1
1
PM72 PM71 PM70  
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121PM120  
PM13  
1
1
1
1
1
1
PM131 PM130  
Pmn Pin Input/Output Mode Selection  
(m=0-3, 5-7, 12, 13 : n=0-7)  
PMmn  
0
1
Output mode (output buffer ON)  
Input mode (output buffer OFF)  
152  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
(2) Pull-up resistor option register (PUOH, PUOL)  
This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor  
is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been  
specified with PUOH, PUOL. No on-chip pull-up resistors can be used to the bits set to the output mode or  
to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.  
PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets this register to 00H.  
Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.  
2. When ports 1, 4, 5, and P64 to P67 pins are used as dual-function pins, an on-chip pull-  
up resistor cannot be used even if 1 is set in PUOm bit of PUOH, PUOL (m = 1, 4 to 6).  
3. Pins P60 to P63 can be connected with pull-up resistor by mask option only for mask  
ROM version.  
Figure 6-20. Pull-Up Resistor Option Register Format  
After  
Reset  
Symbol  
PUOH  
7
0
6
0
<5>  
PUO13PUO12  
<5> <4>  
<4>  
3
0
2
0
1
0
Address  
FFF3H  
R/W  
R/W  
0
0
00H  
<7>  
<6>  
<3>  
<2>  
<1>  
<0>  
PUOL PUO7 PUO6 PUO5 PUO4 PUO3 PUO2 PUO1 PUO0  
FFF7H  
00H  
R/W  
Pm Internal Pull-up Resistor Selection  
(m=0 to 7, 12, 13)  
PUOm  
0
1
Internal pull-up resistor not used  
Internal pull-up resistor used  
Caution Bits 0 to 3, 6, and 7 of PUOH should be set to 0.  
153  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
(3) Memory expansion mode register (MM)  
This register is used to set input/output of port 4.  
MM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets this register to 10H.  
Figure 6-21. Memory Expansion Mode Register Format  
After  
Symbol  
MM  
7
0
6
0
5
4
3
0
2
1
0
Address  
FFF8H  
Reset  
R/W  
R/W  
PW1 PW0  
MM2 MM1 MM0  
10H  
Single-chip/Memory  
Expansion Mode  
Selection  
P40-P47, P50-P57, P64-P67 Pin State  
MM2 MM1 MM0  
P40-P47  
Input  
P50-P53  
P54, P55  
P56, P57  
P64-P67  
0
0
0
0
0
1
Port  
Port mode  
Single-chip mode  
Out-  
put  
mode  
256-byte  
mode  
Port mode  
0
1
1
1
1
0
0
1
1
0
1
1
P64=RD  
4-Kbyte  
mode  
Port mode  
Memory  
expansion  
mode  
P65=WR  
P66=WAIT  
P67=ASTB  
AD0-AD7  
16-Kbyte  
mode  
Port mode  
A14, A15  
A8-A11  
A12, A13  
Full Note  
address  
mode  
Setting prohibited  
Other than above  
PW0 Wait Control  
PW1  
0
0
1
1
0
1
0
1
No wait  
Wait (one wait state insertion)  
Setting prohibited  
Wait control by external wait pin  
Note  
The full address mode allows external expansion for all areas of the 64-Kbyte address space,  
except the internal ROM, RAM, SFR, and use-prohibited areas.  
Remarks 1. P60 to P63 pins enter the port mode in both the single-chip and memory expansion mode.  
2. Besides setting port 4 input/output, MM also sets the wait count and external expansion area.  
154  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
(4) Key return mode register (KRM)  
This register sets enabling/disabling of standby function release by a key return signal (falling edge detection  
of port 4).  
KRM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets KRM to 02H.  
Figure 6-22. Key Return Mode Register Format  
After  
Symbol  
KRM  
7
0
6
0
5
0
4
0
3
0
2
0
<1>  
<0>  
Reset  
Address  
FFF6H  
R/W  
R/W  
KRMK KRIF  
02H  
Key Return Signal Detection Flag  
Not Detected  
KRIF  
0
1
Detected (Falling edge detection of port 4)  
Standby Mode Control by Key Return Signal  
Standby mode release enabled  
KRMK  
0
1
Standby mode release disabled  
Caution When falling edge detection of port4 is used, KRIF should be cleared to 0 (not cleared to 0  
automatically).  
155  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.4 Port Function Operations  
Port operations differ depending on whether the input or output mode is set, as shown below.  
6.4.1 Writing to input/output port  
(1) Output mode  
A value is written to the output latch by a transfer instruction, and the output latch contents are output from  
the pin.  
Once data is written to the output latch, it is retained until data is written to the output latch again.  
(2) Input mode  
A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status  
does not change.  
Once data is written to the output latch, it is retained until data is written to the output latch again.  
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated  
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output  
pins, the output latch contents for pins specified as input are undefined except for the  
manipulated bit.  
6.4.2 Reading from input/output port  
(1) Output mode  
The output latch contents are read by a transfer instruction. The output latch contents do not change.  
(2) Input mode  
The pin status is read by a transfer instruction. The output latch contents do not change.  
156  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 6 PORT FUNCTIONS  
6.4.3 Operations on input/output port  
(1) Output mode  
An operation is performed on the output latch contents, and the result is written to the output latch. The output  
latch contents are output from the pins.  
Once data is written to the output latch, it is retained until data is written to the output latch again.  
(2) Input mode  
The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.  
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated  
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output  
pins, the output latch contents for pins specified as input are undefined, even for bits other  
than the manipulated bit.  
6.5 Selection of Mask Option  
The following mask option is provided in mask ROM version. The PROM versions have no mask options.  
Table 6-6. Comparison between Mask ROM Version and PROM Version  
Pin Name  
Mask ROM Version  
PROM Version  
Mask option for pins P60 to P63  
Bit-wise-selectable on-chip pull-up resistors  
No on-chip pull-up resistor  
157  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
158  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.1 Clock Generator Functions  
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two  
types of system clock oscillators are available.  
(1) Main system clock oscillator  
This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP  
instruction or setting the processor clock control register (PCC).  
(2) Subsystem clock oscillator  
The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock  
oscillator is not used, not using the internal feedback resistance can be set by the processor clock control  
register (PCC). This enables to decrease power consumption in the STOP mode.  
7.2 Clock Generator Configuration  
The clock generator consists of the following hardware.  
Table 7-1. Clock Generator Configuration  
Item  
Configuration  
Processor clock control register (PCC)  
Oscillation mode selection register (OSMS)  
Main system clock oscillator  
Control register  
Oscillator  
Subsystem clock oscillator  
159  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
Figure 7-1. Block Diagram of Clock Generator  
FRC  
XT1/P07  
XT2  
Watch Timer,  
Clock Output  
Function  
fXT  
Subsystem  
Clock  
Oscillator  
Prescaler  
Clock to  
Peripheral  
Hardware  
1/2  
X1  
X2  
Main  
System  
Clock  
f
f
X
X
fXT  
2
Prescaler  
Scaler  
Oscillator  
fXX  
fXX  
24  
2
Standby  
Control  
Circuit  
Wait  
Control  
Circuit  
23  
fXX  
CPU Clock  
(fCPU)  
22  
fXX  
2
fXX  
To INTP0  
Sampling Clock  
3
STOP  
MCS  
Oscillation Mode  
MCC  
FRC  
CLS CSS  
PCC2  
PCC0  
PCC1  
Processor Clock Control Register  
Selection Register  
Internal Bus  
160  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.3 Clock Generator Control Register  
The clock generator is controlled by the following two registers:  
• Processor clock control register (PCC)  
• Oscillation mode selection register (OSMS)  
(1) Processor clock control register (PCC)  
The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/  
stop and subsystem clock oscillator internal feedback resistor.  
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets the PCC to 04H.  
Figure 7-2. Subsystem Clock Feedback Resistor  
FRC  
P-ch  
Feedback resistor  
XT1  
XT2  
161  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
Figure 7-3. Processor Clock Control Register Format  
After  
Symbol <7>  
<6>  
<5>  
<4>  
3
0
2
1
0
Address  
FFFBH  
Reset  
R/W  
PCC MCC FRC CLS CSS  
PCC2 PCC1 PCC0  
04H  
R/W Note 1  
CPU CIock (fCPU) Selection  
MCS = 1  
R/W  
CSS PCC2 PCC1 PCC0  
MCS = 0  
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
1
0
0
fXX  
f
f
f
f
f
x
f
x
x
x
x
x
/2  
fXX/2  
fXX/22  
fXX/23  
fXX/24  
x/2  
f
f
f
f
/22  
/23  
/24  
/25  
0
1
x
x
x
/22  
/23  
/24  
0
0
0
1
0
1
1
0
1
0
1
0
fXT/2  
Other than above  
Setting prohibited  
CPU Clock Status  
Main system clock  
Subsystem clock  
CLS  
0
R
R/W  
R/W  
1
Subsystem Clock Feedback Resistor Selection  
Internal feedback resistor used  
FRC  
0
1
Internal feedback resistor not used  
Main System Clock Oscillation ControlNote 2  
Oscillation possible  
MCC  
0
1
Oscillation stopped  
Notes 1. Bit 5 is Read Only.  
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main  
system clock oscillation. A STOP instruction should not be used.  
Caution Bit 3 must be set to 0.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillator frequency  
: Subsystem clock oscillator frequency  
3. fXT  
4. MCS : Bit 0 of oscillation mode selection register (OSMS)  
162  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
The fastest instruction of the µPD78054 and 78054Y Subseries is executed with two clocks of the CPU clock.  
Therefore, relationships between the CPU clock (fCPU) and the minimum instruction execution time are as shown in  
Table 7-2.  
Table 7-2. Relationship between CPU Clock and Minimum Instruction Execution Time  
CPU Clock (fCPU)  
Minimum Instruction Execution Time: 2/fCPU  
fX  
0.4 µs  
0.8 µs  
1.6 µs  
3.2 µs  
6.4 µs  
12.8 µs  
122 µs  
fX/2  
fX/2  
fX/2  
fX/2  
fX/2  
2
3
4
5
fXT/2  
Remarks 1. fX = 5.0 MHz, fXT = 32.768 kHz  
2. fX : Main system clock oscillation frequency  
3. fXT : Subsystem clock oscillation frequency  
163  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
(2) Oscillation mode selection register (OSMS)  
This register specifies whether the clock output from the main system clock oscillator without passing through  
the scaler is used as the main system clock, or the clock output via the scaler is used as the main system  
clock.  
OSMS is set with 8-bit memory manipulation instruction.  
RESET input sets OSMS to 00H.  
Figure 7-4. Oscillation Mode Selection Register Format  
After  
Symbol  
OSMS  
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reset  
Address  
FFF2H  
R/W  
W
MCS  
00H  
Main System Clock Scaler Control  
Scaler used  
MCS  
0
1
Scaler not used  
Cautions 1. The main system clock cycle is longer by up to 2/fx only when writing data to OSMS (including  
when writing the same data that was written previously) as shown in Figure 7-5. This causes  
a temporary error in the count clock cycle of timers in the peripheral hardware that operates  
with the main system clock.  
In addition, when the oscillation mode is changed, the clocks provided for the peripheral  
hardware as well as those for the CPU are switched. Therefore, it is recommended that only  
one-time writing to OSMS be performed between the reset release and the peripheral  
hardware operation.  
Figure 7-5. Main System Clock when Writing to OSMS  
Write to OSMS  
(MCS  
0)  
Max. 2/fX  
fXX  
Operating at fXX = fX/2 (MCS = 0)  
Operating at fXX = fX/2 (MCS = 0)  
2. Setting 1 to MCS should be performed after VDD 2.7 V.  
Remarks fxx : Main system clock frequency (fx or fx/2)  
fx : Main system clock oscillation frequency  
164  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.4 System Clock Oscillator  
7.4.1 Main system clock oscillator  
The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz)  
connected to the X1 and X2 pins.  
External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin  
and an antiphase clock signal to the X2 pin.  
Figure 7-6 shows an external circuit of the main system clock oscillator.  
Figure 7-6. External Circuit of Main System Clock Oscillator  
(a) Crystal and ceramic oscillation  
(b) External clock  
X2  
X2  
External  
X1  
X1  
IC  
Clock  
PD74HCU04  
µ
Crystal  
or  
Ceramic Resonator  
Caution Do not execute the STOP instruction or do not set MCC (bit 7 of processor clock control register  
(PCC)) to 1 if an external clock is used. This is because if STOP instruction is executed or MCC  
is set to 1, the operation of the main system clock is stopped and the X2 pin is pulled up to VDD.  
165  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.4.2 Subsystem clock oscillator  
The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1  
and XT2 pins.  
External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin  
and an antiphase clock signal to the XT2 pin.  
Figure 7-7 shows an external circuit of the subsystem clock oscillator.  
Figure 7-7. External Circuit of Subsystem Clock Oscillator  
(a) Crystal oscillation  
(b) External clock  
IC  
XT2  
XT2  
32.768  
kHz  
External  
Clock  
XT1  
XT1  
PD74HCU04  
µ
Cautions 1. When using a main system clock oscillator and a subsystem clock oscillator, carry out wiring  
in the broken line area in Figures 7-6 and 7-7 to prevent any effects from wiring capacities.  
Minimize the wiring length.  
Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come  
near changing high current.  
Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do  
not ground to any ground pattern where high current is present.  
Do not fetch signals from the oscillator.  
Take special note of the fact that the subsystem clock oscillator is a circuit with low-level  
amplification so that current consumption is maintained at low levels.  
Figure 7-8 shows examples of incorrect oscillator connection.  
Figure 7-8. Examples of Incorrect Oscillator Connection (1/2)  
(a) Wiring of connection  
circuits is too long  
(b) Signal lines intersect  
each other  
PORTn  
(n=0-7, 12, 13)  
IC  
X2  
X1  
IC  
X2  
X1  
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert  
resistors in series on the side of XT2.  
166  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
Figure 7-8. Examples of Incorrect Oscillator Connection (2/2)  
(c) Changing high current is too near a  
(d) Current flows through the grounding line  
of the oscillator (potential at points A, B,  
and C fluctuate)  
signal conductor  
VDD  
Pnm  
IC  
X2  
X1  
IC  
X2  
X1  
High  
Current  
A
B
C
High  
Current  
(e) Signals are fetched  
IC  
X1  
X2  
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors  
in series on the XT2 side.  
Cautions 2. In Figure 7-8 (f), XT2 and X1 are wired in parallel. Thus, the cross-talk noise of X1 may  
increase with XT2, resulting in malfunctioning. To prevent that from occurring, it is  
recommended to wire XT2 and X1 so that they are not in parallel, and to correct the IC pin  
between XT2 and X1 directly to VSS.  
167  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.4.3 Scaler  
The scaler divides the main system clock oscillator output (fXX) and generates various clocks.  
7.4.4 When no subsystem clocks are used  
If it is not necessary to use subsystem clocks for low power consumption operations and clock operations,  
connect the XT1 and XT2 pins as follows.  
XT1: Connect to VDD.  
XT2: Leave open.  
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator  
when the main system clock stops. To suppress the leakage current, disconnect the above internal feedback resistor  
by using the bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2  
pins as described above.  
168  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.5 Clock Generator Operations  
The clock generator generates the following various types of clocks and controls the CPU operating mode  
including the standby mode.  
• Main system clock  
• Subsystem clock  
fXX  
fXT  
• CPU clock  
fCPU  
• Clock to peripheral hardware  
The following clock generator functions and operations are determined with the processor clock control register  
(PCC) and the oscillation mode selection register (OSMS).  
(a) Upon generation of RESET signal, the lowest speed mode of the main system clock (12.8 µs when operated  
at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while low level is  
applied to RESET pin.  
(b) With the main system clock selected, one of the six CPU clock types (0.4 µs. 0.8 µs, 1.6 µs, 3.2 µs, 6.4 µs,  
12.8 µs @ 5.0 MHz) can be selected by setting the PCC and OSMS.  
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. In a  
system where the subsystem clock is not used, the current consumption in the STOP mode can be further  
reduced by specifying with bit 6 (FRC) of the PCC not to use the feedback resistor.  
(d) The PCC can be used to select the subsystem clock and to operate the system with low current consumption  
(122 µs when operated at 32.768 kHz).  
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT  
mode can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be  
stopped.)  
(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied  
to 16-bit timer/event counter, the watch timer, and clock output functions only. Thus, 16-bit timer/event counter  
(when selecting watch timer output for count clock operating with subsystem clock), the watch function, and  
the clock output function can also be continued in the standby state. However, since all other peripheral  
hardware operate with the main system clock, the peripheral hardware also stops if the main system clock  
is stopped. (Except external input clock operation)  
169  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.5.1 Main system clock operations  
When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to  
0), the following operations are carried out by PCC setting.  
(a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the  
minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.  
(b) If bit 7 (MCC) of the PCC is set to 1 when operated with the main system clock, the main system clock oscillation  
does not stop. When bit 4 (CSS) of the PCC is set to 1 and the operation is switched to subsystem clock  
operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 7-9).  
Figure 7-9. Main System Clock Stop Function (1/2)  
(a) Operation when MCC is set after setting CSS with main system clock operation  
MCC  
CSS  
CLS  
Main System Clock Oscillation  
Subsystem Clock Oscillation  
CPU Clock  
(b) Operation when MCC is set in case of main system clock operation  
MCC  
L
CSS  
L
CLS  
Oscillation does not stop.  
Main System Clock Oscillation  
Subsystem Clock Oscillation  
CPU Clock  
170  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
Figure 7-9. Main System Clock Stop Function (2/2)  
(c) Operation when CSS is set after setting MCC with main system clock operation  
MCC  
CSS  
CLS  
Main System Clock Oscillation  
Subsystem Clock Oscillation  
CPU Clock  
7.5.2 Subsystem clock operations  
When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1),  
the following operations are carried out.  
(a) The minimum instruction execution time remains constant (122 µs when operated at 32.768 kHz) irrespective  
of bits 0 to 2 (PCC0 to PCC2) of the PCC.  
(b) Watchdog timer counting stops.  
Caution Do not execute the STOP instruction while the subsystem clock is in operation.  
7.6 Changing System Clock and CPU Clock Settings  
7.6.1 Time required for switchover between system clock and CPU clock  
The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS)  
of the processor clock control register (PCC).  
The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the  
pre-switchover clock for several instructions (see Table 7-3).  
Whether the system is operating on the main system clock or the subsystem clock can be discriminated by bit 5  
(CLS) of the PCC register.  
171  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Set Values before  
Switchover  
Set Values After Switchover  
MSC = 1  
MSC = 0  
CSS  
0
CSS  
CSS  
0
CSS  
0
CSS  
1
CSS  
1
PCC2  
PCC0  
CSS PCC2  
PCC0  
0
PCC2  
0
PCC0  
1
PCC2  
0
PCC0  
0
PCC2  
0
PCC0  
1
PCC2  
1
PCC0  
0
PCC2  
PCC0  
PCC1  
PCC1  
0
PCC1  
0
PCC1  
1
PCC1  
1
PCC1  
0
PCC1  
PCC2 PCC1  
CSS  
PCC0  
×
×
×
×
×
×
0
0
0
fX/2fXT instruction  
(77 instructions)  
fX/4fXT instruction  
(39 instructions)  
16 instructions  
16 instructions  
16 instructions  
8 instructions  
4 instructions  
0
16 instructions  
8 instructions  
0
0
0
0
0
0
1
1
fX/4fXT instruction  
(39 instructions)  
fX/8fXT instruction  
(20 instructions)  
8 instructions  
4 instructions  
2 instructions  
1
0
1
8 instructions  
4 instructions  
2 instructions  
fX/16fXT instruction  
(10 instructions)  
fX/8fXT instruction  
(20 instructions)  
4 instructions  
2 instructions  
0
fX/32fXT instruction  
(5 instructions)  
fX/16fXT instruction  
(10 instructions)  
2 instructions  
1 instruction  
1 instruction  
fX/32fXT instruction fX/64fXT instruction  
(5 instructions)  
(3 instructions)  
1 instruction  
1 instruction  
1 instruction  
1 instruction  
1 instruction  
1 instruction  
1
0
0
1 instruction  
×
×
×
1
Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock.  
2. MCS: Oscillation mode selection register bit 0  
3. Figures in parentheses apply to operation with fX = 5.0 MHz and fXT = 32.768 kHz.  
Caution Selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the main system  
clock to the subsystem clock (changing CSS from 0 to 1) should not be performed simultaneously.  
Simultaneous setting is possible, however, for selection of the CPU clock cycle scaling factor (PCC0 to  
PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0).  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 7 CLOCK GENERATOR  
7.6.2 System clock and CPU clock switching procedure  
This section describes switching procedure between system clock and CPU clock.  
Figure 7-10. System Clock and CPU Clock Switching  
VDD  
RESET  
Interrupt  
Request  
Signal  
fXX  
fXX  
fXT  
fXX  
System Clock  
CPU Clock  
Minimum Maximum Speed  
Speed  
Subsystem Clock  
Operation  
High-Speed  
Operation  
Operation  
Operation  
Wait (26.2 ms : 5.0 MHz)  
Internal Reset Operation  
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released  
by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation  
17  
stabilization time (2 /fX) is secured automatically.  
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 µs when  
operated at 5.0 MHz).  
(2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds,  
the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and  
the maximum-speed operation is carried out.  
(3) Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock  
is switched to the subsystem clock (which must be in an oscillation stable state).  
(4) Upon detection of VDD voltage reset due to an interrupt request signal, 0 is set to the bit 7 (MCC) of PCC and  
oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation,  
the PCC and OSMS are rewritten and the maximum-speed operation is resumed.  
Caution When subsystem clock is being operated while main system clock was stopped, if switching to  
the main system clock is made again, be sure to switch after securing oscillation stable time by  
software.  
173  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
174  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.1 Outline of Timers Incorporated in the µPD78054, 78054Y Subseries  
This chapter explains 16-bit timer/event counter. Before that, the timers incorporated into the µPD78054, 78054Y  
Subseries and related circuits are outlined below.  
(1) 16-bit timer/event counter (TM0)  
The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control  
receive function), external event counter, square wave output of any frequency or one-shot pulse output.  
(2) 8-bit timers/event counters 1 and 2 (TM1 and TM2)  
TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square  
waves with any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/event  
counter (See CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2).  
(3) Watch timer (TM3)  
This timer can set a flag every 0.5 sec. and simultaneously generates interrupt requests at the preset time  
intervals (See CHAPTER 10 WATCH TIMER).  
(4) Watchdog timer (WDTM)  
WDTM can perform the watchdog timer function or generate non-maskable interrupt requests, maskable  
interrupt requests and RESET at the preset time intervals (See CHAPTER 11 WATCHDOG TIMER).  
(5) Clock output control circuit  
This circuit supplies other devices with the divided main system clock and the subsystem clock (See CHAPTER  
12 CLOCK OUTPUT CONTROL CIRCUIT).  
(6) Buzzer output control circuit  
This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 13  
BUZZER OUTPUT CONTROL CIRCUIT).  
175  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Table 8-1. Timer/Event Counter Operations  
16-bit Timer/  
8-bit Timer/event  
Counters 1 and 2  
Watch Timer  
Watchdog Timer  
event Counter  
Note 3  
Note 1  
Note 2  
Operating  
mode  
Interval timer  
2 channels  
2 channels  
1 channel  
1 channel  
External event counter  
Timer output  
PWM output  
Pulse width measurement  
Square-wave output  
One-shot pulse output  
Interrupt source  
Test input  
Function  
Notes 1. Watch timer can perform both watch timer and interval timer functions at the same time.  
2. Watchdog timer can perform either the watchdog timer function or the interval timer function.  
3. When capture/compare registers (CR00, CR01) are specified as compare registers.  
176  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.2 16-Bit Timer/Event Counter Functions  
The 16-bit timer/event counter (TM0) has the following functions.  
• Interval timer  
• PWM output  
• Pulse width measurement  
• External event counter  
• Square-wave output  
• One-shot pulse output  
PWM output and pulse width measurement can be used at the same time.  
(1) Interval timer  
TM0 generates interrupt requests at the preset time interval.  
Table 8-2. 16-Bit Timer/Event Counter Interval Times  
Minimum Interval Time  
MCS = 1 MCS = 0  
2 × TI00 input cycle  
Maximum Interval Time  
MCS = 1 MCS = 0  
Resolution  
MCS = 1  
MCS = 0  
16  
2
× TI00 input cycle  
TI00 input edge cycle  
16  
2 × 1/fX  
2
× 1/fX  
1/fX  
(400 ns)  
(13.1 ms)  
(200 ns)  
2
16  
17  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(13.1 ms)  
(26.2 ms)  
(200 ns)  
2 × 1/fX  
(400 ns)  
2
3
17  
18  
2
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(800 ns)  
(1.6 µs)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
3
4
18  
19  
2
3
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(1.6 µs)  
(3.2 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
16  
2 × watch timer output cycle  
2
× watch timer output cycle  
Watch timer output edge cycle  
Remarks 1. fX: Main system clock oscillation frequency  
2. MCS: Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz  
(2) PWM output  
TM0 can generate 14-bit resolution PWM output.  
(3) Pulse width measurement  
TM0 can measure the pulse width of an externally input signal.  
(4) External event counter  
TM0 can measure the number of pulses of an externally input signal.  
177  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(5) Square-wave output  
TM0 can output a square wave with any selected frequency.  
Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges  
Minimum Pulse Width  
MCS = 1 MCS = 0  
2 × TI00 input cycle  
2 × 1/fX  
Maximum Pulse Width  
MCS = 1 MCS = 0  
Resolution  
MCS = 1  
TI00 input edge cycle  
1/fX  
MCS = 0  
16  
2
× TI00 input cycle  
16  
2
× 1/fX  
(400 ns)  
(13.1 ms)  
(200 ns)  
2
16  
17  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(13.1 ms)  
(26.2 ms)  
(200 ns)  
2 × 1/fX  
(400 ns)  
2
3
17  
18  
2
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(800 ns)  
(1.6 µs)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
3
4
18  
19  
2
3
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(1.6 µs)  
(3.2 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
16  
2 × watch timer output cycle  
2
× watch timer output cycle  
Watch timer output edge cycle  
Remarks 1. fX: Main system clock oscillation frequency  
2. MCS: Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz  
(6) One-shot pulse output  
TM0 is able to output one-shot pulse which can set any width of output pulse.  
178  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.3 16-Bit Timer/Event Counter Configuration  
The 16-bit timer/event counter consists of the following hardware.  
Table 8-4. 16-Bit Timer/Event Counter Configuration  
Item  
Configuration  
Timer register  
Register  
16 bits × 1 (TM0)  
Capture/compare register: 16 bits × 2 (CR00, CR01)  
1 (TO0)  
Timer output  
Timer clock select register 0 (TCL0)  
16-bit timer mode control register (TMC0)  
Capture/compare control register 0 (CRC0)  
16-bit timer output control register (TOC0)  
Port mode register 3 (PM3)  
Control register  
External interrupt mode register 0 (INTM0)  
Note  
Sampling clock select register (SCS)  
Note Refer to Figure 21-1. Basic Configuration of Interrupt Function.  
Figure 8-1. 16-Bit Timer/Event Counter Block Diagram  
Internal bus  
Capture/Compare  
Control Register 0  
CRC00  
CRC02 CRC01  
INTP1  
16-Bit Capture/Compare  
Control Register (CR00)  
TI01/  
P01/INTP1  
INTTM00  
PWM Pulse  
Output  
Match  
Note 2  
INTTM3  
2f  
Controller  
fXX  
XX  
16-Bit Timer/Event  
Counter Output  
Control Circuit  
TO0/P30  
TMC01-TMC03  
fXX/2  
fXX/22  
16-Bit Timer Register (TM0)  
Clear  
2
TI00/P00/  
INTP0  
Clear Circuit  
3
Note 1  
TMC01-TMC03  
Match  
INTTM01  
INTP0  
3
16-Bit Capture/Compare  
Control Register (CR01)  
TCL04  
TMC03 TMC02 TMC01  
OSPTOSPETOC04  
LVS0  
LVR0TOC01 TOE0  
TCL06 TCL05  
OVF0  
Timer Clock  
16-Bit Timer Mode  
Control Register  
16-Bit Timer Output  
Control Register  
Selection  
CRC02  
Register 0  
Internal Bus  
Notes 1. Edge detection circuit  
2. The configuration of the 16-bit timer/event counter output control circuit is shown in Figure 8-2.  
179  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram  
PWM Pulse  
Output Control  
Circuit  
Level  
Inversion  
CRC02  
INTTM01  
CRC00  
INV  
INTTM00  
TO0/P30  
Q
S
R
Edge  
Detection  
Circuit  
TI00/P00/  
INTP0  
One-Shot Pulse  
Output Control  
Circuit  
3
2
P30 Output  
Latch  
PM30  
ES11 ES10  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
TMC03 TMC02 TMC01  
External Interrupt  
Mode Register 0  
16-Bit Timer Output  
Control Register  
16-Bit Timer Mode  
Control Register  
Port Mode  
Register 3  
Internal Bus  
Remark The circuitry enclosed by the dotted line is the output control circuit.  
180  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(1) Capture/compare register 00 (CR00)  
CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether  
it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control  
register 0 (CRC0).  
When CR00 is used as a compare register, the value set in the CR00 is constantly compared with the 16-  
bit timer register (TM0) count value, and an interrupt request (INTTM00) is generated if they match. It can  
also be used as the register which holds the interval time when TM0 is set to interval timer operation, and  
it can be used as the register which sets the pulse width when TM0 is set to PWM output operation.  
When CR00 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin or the  
INTP1/TI01 pin as the capture trigger. The INTP0/TI00 or INTP1/TI01 valid edge is set by means of external  
interrupt mode register 0 (INTM0).  
If CR00 is specified as a capture register and capture trigger is specified to be the valid edge of the INTP0/  
TI00 pin, the situation is as shown in the following table.  
Table 8-5. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge  
ES11  
ES10  
INTP0/TI00 Pin Valid Edge  
Falling edge  
CR00 Capture Trigger Valid Edge  
Rising edge  
0
0
1
1
0
1
0
1
Rising edge  
Falling edge  
Setting prohibited  
Both rising and falling edges  
No capture operation  
CR00 is set by a 16-bit memory manipulation instruction.  
After RESET input, the value of CR00 is undefined.  
Cautions 1. Set the data of PWM (14 bits) to the higher 14 bits of CR00. At this time, clear the lower  
2 bits to 00.  
2. Set a value other than 0000H to CR00. When the event counter function is used, therefore,  
one pulse cannot be counted.  
3. If the new value of CR00 is less than the value of the 16-bit timer register (TM0), TM0  
continues counting, overflows, and then starts counting again from 0. If the new value  
of CR00 is less than the old value, the timer must be restarted after changing the value  
of CR00.  
(2) Capture/compare register 01 (CR01)  
CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether  
it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register  
0.  
When CR01 is used as a compare register, the value set in the CR01 is constantly compared with the 16-  
bit timer register (TM0) count value, and an interrupt request (INTTM01) is generated if they match.  
When CR01 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin as the  
capture trigger. The INTP0/TI00 valid edge is set by means of external interrupt mode register 0 (INTM0).  
CR01 is set with a 16-bit memory manipulation instruction.  
After RESET input, the value of CR01 is undefined.  
181  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the  
capture operation and retains the current data. However, the interrupt request flag (PIF0)  
is set.  
(3) 16-bit timer register (TM0)  
TM0 is a 16-bit register which counts the count pulses.  
TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register 01  
(CR01) should first be set as a capture register.  
RESET input sets TM0 to 0000H.  
Caution As the value of TM0 is read via CR01, the value of CR01 previously set is lost.  
8.4 16-Bit Timer/Event Counter Control Registers  
The following seven types of registers are used to control the 16-bit timer/event counter.  
• Timer clock select register 0 (TCL0)  
• 16-bit timer mode control register (TMC0)  
• Capture/compare control register 0 (CRC0)  
• 16-bit timer output control register (TOC0)  
• Port mode register 3 (PM3)  
• External interrupt mode register 0 (INTM0)  
• Sampling clock select register (SCS)  
(1) Timer clock select register 0 (TCL0)  
This register is used to set the count clock of the 16-bit timer register.  
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets TCL0 value to 00H.  
Remark TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock  
of the 16-bit timer register.  
182  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-3. Timer Clock Selection Register 0 Format  
Address  
FF40H  
After Reset  
00H  
R/W  
R/W  
Symbol <7>  
6
5
4
3
2
1
0
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00  
TCL0  
PCL Output Clock Selection  
TCL03 TCL02 TCL01 TCL00  
MCS = 1  
MCS = 0  
0
0
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fXT (32.768 kHz)  
fXX  
f
f
f
f
f
f
f
f
X
(5.0 MHz)  
f
f
f
f
f
f
f
f
X/2  
(2.5 MHz)  
fXX/2  
X/2 (2.5 MHz)  
X
X
X
X
X
/22  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
fXX/22  
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
/23  
/24  
/25  
/26  
/27  
/28  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
X
X
fXX/27  
Other than above  
Setting prohibited  
16-Bit Timer Register Count Clock Selection  
MCS = 1  
TCL06 TCL05 TCL04  
MCS = 0  
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TI00 (Valid edge specifiable)  
2fXX  
fXX  
Setting prohibited  
f
f
f
f
X
(5.0 MHz)  
(2.5 MHz)  
f
f
f
X
(5.0 MHz)  
X/2  
fXX/2  
fXX/22  
X/2 (2.5 MHz)  
X/22 (1.25 MHz)  
X/22 (1.25 MHz)  
X/23 (625 kHz)  
Watch timer output (INTTM 3)  
Setting prohibited  
Other than above  
PCL Output Control  
Output disabled  
CLOE  
0
1
Output enabled  
Cautions 1. The TI00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and  
the sampling clock frequency is selected by the sampling clock selection register  
(SCS).  
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory  
manipulation instruction.  
3. To read the count value when TI00 has been specified as the TM0 count clock, the value  
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).  
4. When rewriting TCL0 to other data, stop the timer operation beforehand.  
183  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
: Subsystem clock oscillation frequency  
3. fXT  
4. TI00 : 16-bit timer/event counter input pin  
5. TM0 : 16-bit timer register  
6. MCS : Bit 0 of oscillation mode selection register (OSMS)  
7. Figures in parentheses apply to operation with fX = 5.0 MHz of fXT = 32.768 kHz.  
(2) 16-bit timer mode control register (TMC0)  
This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and  
detects an overflow.  
TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets TMC0 value to 00H.  
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation  
stop mode) is set in TMC01 to TMC03, respectively. Set 0, 0, 0 in TMC01 to TMC03 to stop  
the operation.  
184  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-4. 16-Bit Timer Mode Control Register Format  
Address  
FF48H  
After Reset  
00H  
R/W  
R/W  
Symbol  
TMC0  
7
0
6
0
5
0
4
0
3
2
1
<0>  
TMC03 TMC02 TMC01 OVF0  
OVF0 16-Bit Timer Register Overflow Detection  
0
1
Overflow not detected  
Overflow detected  
Operating Mode  
Clear Mode Selection  
TO0 Output Timing Selection  
Interrupt Generation  
TMC03 TMC02 TMC01  
Operation stop  
(TM0 cleared to 0)  
0
0
0
0
0
1
0
1
0
No change  
Not Generated  
PWM mode  
(free running)  
PWM pulse output  
Match between TM0 and  
CR00 or match between  
TM0 and CR01  
Free running mode  
Match between TM0 and  
CR00, match between  
TM0 and CR01 or TI00  
valid edge  
0
1
1
1
0
0
1
0
1
Generated on match  
between TM0 and CR00,  
or match between TM0  
and CR01  
Match between TM0 and  
CR00 or match between  
TM0 and CR01  
Clear & start on TI00  
valid edge  
Match between TM0 and  
CR00, match between  
TM0 and CR01 or TI00  
valid edge  
Match between TM0 and  
CR00 or match between  
TM0 and CR01  
1
1
1
1
0
1
Clear & start on match  
between TM0 and CR00  
Match between TM0 and  
CR00, match between  
TM0 and CR01 or TI00  
valid edge  
Remarks 1. TO0 : 16-bit timer/event counter output pin  
2. TI00 : 16-bit timer/event counter input pin  
3. TM0 : 16-bit timer register  
4. CR00 : Compare register 00  
5. CR01 : Compare register 01  
Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation  
(by setting TMC01 to TMC03 to 0, 0, 0).  
2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0  
(INTM0) and select the sampling clock frequency with a sampling clock select register  
(SCS).  
3. When using the PWM mode, set the PWM mode and then set data to CR00.  
4. If clear & start mode on match between TM0 and CR00 is selected, when the set value  
of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, OVF0 flag is set  
to 1.  
185  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(3) Capture/compare control register 0 (CRC0)  
This register controls the operation of the capture/compare registers (CR00, CR01).  
CRC0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CRC0 value to 04H.  
Figure 8-5. Capture/Compare Control Register 0 Format  
Address  
FF4CH  
After Reset  
04H  
R/W  
R/W  
Symbol  
CRC0  
7
0
6
0
5
0
4
0
3
0
2
1
0
CRC02 CRC01 CRC00  
CRC00 CR00 Operating Mode Selection  
0
1
Operates as compare register  
Operates as capture register  
CRC01 CR00 Capture Trigger Selection  
Captures on valid edge of TI01  
Captures on valid edge of TI00  
0
1
CRC02 CR01 Operating Mode Selection  
Operates as compare register  
Operates as capture register  
0
1
Cautions 1. Timer operation must be stopped before setting CRC0.  
2. When clear & start mode on a match between TM0 and CR00 is selected with the 16-  
bit timer mode control register, CR00 should not be specified as a capture register.  
(4) 16-bit timer output control register (TOC0)  
This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type  
flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other  
than PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation  
enabling/disabling, and output trigger for a one-shop pulse by software.  
TOC0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets TOC0 value to 00H.  
186  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-6. 16-Bit Timer Output Control Register Format  
Address  
FF4EH  
After Reset  
00H  
R/W  
R/W  
Symbol  
TOC0  
7
0
<6>  
<5>  
4
<3> <2>  
1
<0>  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
TOE0 16-Bit Timer/Event Counter Output Control  
0
1
Output disabled (Port mode)  
Output enabled  
In PWM Mode  
In Other Modes  
Timer output F/F control  
by match of CR00 and  
TM0  
TOC01  
Active level selection  
Inversion operation disabled  
Inversion operation enabled  
Active high  
Active low  
0
1
16-Bit Timer/Event Counter Timer  
Output F/F Status Setting  
LVS0 LVR0  
0
0
1
1
0
1
0
1
No change  
Timer output F/F reset (0)  
Timer output F/F set (1)  
Setting prohibited  
TOC04 Timer output F/F control by match of CR01 and TM0  
0
1
Inversion operation disabled  
Inversion operation enabled  
OSPE One-Shot Pulse Output Control  
0
1
Continuous pulse output  
One-shot pulse output  
OSPT Control of One-Shot Pulse Output Trigger by Software  
0
1
One-shot pulse trigger not used  
One -shot pulse trigger used  
Cautions 1. Timer operation must be stopped before setting TOC0 (however, except OSPT).  
2. If LVS0 and LVR0 are read after data is set, they will be 0.  
3. OSPT is cleared automatically after data setting, and will therefore be 0 if read.  
187  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(5) Port mode register 3 (PM3)  
This register sets port 3 input/output in 1-bit units.  
When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0.  
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets PM3 value to FFH.  
Figure 8-7. Port Mode Register 3 Format  
Address  
FF23H  
After Reset  
FFH  
R/W  
R/W  
Symbol  
PM3  
7
6
5
4
3
2
1
0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30  
PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7)  
0
1
Output mode (output buffer ON)  
Input mode (output buffer OFF)  
188  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(6) External interrupt mode register 0 (INTM0)  
This register is used to set INTP0 to INTP2 valid edges.  
INTM0 is set with an 8-bit memory manipulation instruction.  
RESET input sets INTM0 value to 00H.  
Figure 8-8. External Interrupt Mode Register 0 Format  
Address  
FFECH  
After Reset  
00H  
R/W  
R/W  
Symbol  
INTM0  
7
6
5
4
3
2
1
0
0
0
ES31 ES30 ES21 ES20 ES11 ES10  
ES11 ES10 INTP0 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES21 ES20 INTP1 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES31 ES30 INTP2 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
Caution Befoer setting the valid edge of the INTP0/TI00/P00 pin, stop the timer operation by clearing  
the bits 1 through 3 (TMC01 through TMC03) of the 16-bit timer mode control register (TMC0)  
to 0, 0, 0.  
189  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(7) Sampling clock select registers (SCS)  
This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote  
controlled reception is carried out using INTP0, digital noise is removed with sampling clock.  
SCS is set with an 8-bit memory manipulation instruction.  
RESET input sets SCS value to 00H.  
Figure 8-9. Sampling Clock Select Register Format  
Address  
FF47H  
After Reset  
00H  
R/W  
R/W  
Symbol  
SCS  
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SCS1 SCS0  
INTP0 Sampling Clock Selection  
SCS1 SCS0  
MCS = 1  
MCS = 0  
0
0
1
1
0
1
0
1
fXX/2N  
fXX/27  
fXX/25  
fXX/26  
f
f
f
X/27 (39.1 kHz)  
X/25 (156.3 kHz)  
X/26 (78.1 kHz)  
f
f
f
X/28 (19.5 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
N
5
6
7
Caution fXX/2 is the clock supplied to the CPU, and fXX/2 , fXX/2 , and fXX/2 are clocks supplied to  
N
peripheral hardware. fXX/2 is stopped in HALT mode.  
Remarks 1. N  
: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)  
(N = 0 to 4)  
2. fXX  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
3. fX  
4. MCS : Bit 0 of oscillation mode selection register (OSMS)  
5. Figures in parentheses apply to operation with fX = 5.0 MHz.  
190  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.5 16-Bit Timer/Event Counter Operations  
8.5.1 Interval timer operations  
Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown  
in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value  
set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.  
When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with  
the TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated.  
Count clock of the 16-bit timer/event counter can be selected with bits 4 to 6 (TCL04 to TCL06) of the timer clock  
select register 0 (TCL0).  
For the operation when the value of the compare register is changed during the timer count operation, refer to  
8.6 16-Bit Timer/Event Counter Precautions (3).  
Figure 8-10. Control Register Settings for Interval Timer Operation  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
0
0
0
0
1
1
0/1  
0
TMC0  
Clear & start on match TM0 and CR00  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
0
0
0
0
0
0/1  
0/1  
0
CRC0  
CR00 set as compare register  
Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See  
the description of the respective control registers for details.  
191  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-11. Interval Timer Configuration Diagram  
16-Bit Capture/Compare Register 00 (CR00)  
INTTM00  
INTTM3  
2fXX  
fXX  
fXX/2  
fXX/22  
OVF0  
16-Bit Timer Register (TM0)  
TI00/P00/INTP0  
Clear Circuit  
Figure 8-12. Interval Timer Operation Timings  
t
Count Clock  
TM0 Count Value  
0000 0001  
Count Start  
N
0000 0001  
Clear  
N
0000 0001  
Clear  
N
CR00  
N
N
N
N
INTTM00  
Interrupt Request Acknowledge Interrupt Request Acknowledge  
TO0  
Interval Time  
Interval Time  
Interval Time  
Remark Interval time = (N + 1) × t : N = 0001H to FFFFH.  
192  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Table 8-6. 16-Bit Timer/Event Counter Interval Times  
Minimum Interval Time  
Maximum Interval Time  
Resolution  
MCS = 1 MCS = 0  
TI00 input edge cycle  
TCL06 TCL05 TCL04  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
16  
0
0
0
0
0
1
2 × TI00 input cycle  
2
× TI00 input cycle  
16  
Setting  
2 × 1/fX  
Setting  
2
× 1/fX  
Setting  
1/fX  
prohibited  
(400 ns)  
prohibited  
(13.1 ms)  
prohibited  
(200 ns)  
2
16  
17  
0
0
1
1
1
1
0
0
1
0
1
2 × 1/fX  
(400 ns)  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(13.1 ms)  
(26.2 ms)  
(200 ns)  
2
3
17  
18  
2
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
(400 ns)  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(26.2 ms)  
(52.4 ms)  
(800 ns)  
3
4
18  
19  
2
3
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(800 ns)  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(52.4 ms)  
(104.9 ms)  
(1.6 µs)  
16  
1
2 × watch timer output cycle  
2
× watch timer output cycle Watch timer output edge cycle  
Other than above  
Setting prohibited  
Remarks 1. fX  
2. MCS  
: Main system clock oscillation frequency  
: Bit 0 of oscillation mode selection register (OSMS)  
3. TCL04 to TCL06 : Bits 4 to 6 of timer clock select register 0 (TCL0)  
4. Figures in parentheses apply to operation with fX = 5.0 MHz  
8.5.2 PWM output operations  
Setting the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit  
timer output control register (TOC0) as shown in Figure 8-13 allows operation as PWM output. Pulses with the duty  
rate determined by the value set in 16-bit capture/compare register 00 (CR00) beforehand are output from the TO0/  
P30 pin.  
Set the active level width of the PWM pulse to the high-order 14 bits of CR00. Select the active level with bit 1  
(TOC01) of the 16- bit timer output control register (TOC0).  
This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with  
8
an external low-pass filter (LPF). The PWM pulse is formed by a combination of the basic cycle determined by 2 /  
14  
Φ and the sub-cycle determined by 2 /Φ so that the time constant of the external LPF can be shortened. Count clock  
Φ can be selected with bits 4 to 6 (TCL04 to TCL06) of the timer clock select register 0 (TCL0).  
PWM output enable/disable can be selected with bit 0 (TOE0) of TOC0.  
Cautions 1. PWM operation mode should be selected before setting CR00.  
2. Be sure to write 0 to bits 0 and 1 of CR00.  
3. Do not select PWM operation mode for external clock input from the TI00/P00/INTP0 pin.  
193  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-13. Control Register Settings for PWM Output Operation  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
0
0
1
0
PWM mode  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
0/1  
0/1  
0
CR00 set as compare register  
(c) 16-bit timer output control register (TOC0)  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
0/1  
TOC0  
0
×
×
×
×
×
1
TO0 Output Enabled  
Specifies Active Level  
Remark 0/1 : Setting 0 or 1 allows another function to be used simultaneously with PWM output.  
See the description of the respective control registers for details.  
×
: Don't care  
194  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog  
voltage and used for electronic tuning and D/A converter applications, etc.  
The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows.  
capture/compare register 00 (CR00) value  
VAN = VREF ×  
16  
2
VREF: External switching circuit reference voltage  
Figure 8-14. Example of D/A Converter Configuration with PWM Output  
µ
PD78054, 78054Y  
VREF  
PWM  
signal  
Analog Output (VAN)  
Switching Circuit  
TO0/P30  
Low-Pass Filter  
Figure 8-15 shows an example in which PWM output is converted to an analog voltage and used in a voltage  
synthesizer type TV tuner.  
Figure 8-15. TV Tuner Application Circuit Example  
+110 V  
µ
PD78054, 78054Y  
22 kΩ  
47 k  
47 k  
47 kΩ  
100 pF  
Electronic  
Tuner  
2SC  
2352  
0.22  
µ
F
0.22  
µ
F
0.22  
µF  
TO0/P30  
8.2 kΩ  
µ
PC574J  
8.2 kΩ  
VSS  
GND  
195  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.5.3 PPG output operations  
Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown  
in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output.  
In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle  
that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/  
compare register 00 (CR00), respectively.  
Figure 8-16. Control Register Settings for PPG Output Operation  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
1
1
0
0
Clear & start on match of TM0 and CR00  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
0
x
0
CR00 set as compare register  
CR01 set as compare register  
(c) 16-bit timer output control register (TOC0)  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
0/1 0/1  
TOC0  
0
0
0
1
1
1
TO0 Output Enabled  
Inversion of output on match of TM0 and CR00  
Specified TO0 output F/F initial value  
Inversion of output on match of TM0 and CR01  
One-shot pulse output disabled  
Caution Values in the following range should be set in CR00 and CR01:  
0000H CR01 < CR00 FFFFH  
Remark × : Don't care  
196  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.5.4 Pulse width measurement operations  
It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the  
16-bit timer register (TM0).  
There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by  
restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.  
(1) Pulse width measurement with free-running counter and one capture register  
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-17),  
and the edge specified by external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value  
of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0)  
is set.  
Any of three edge specifications can be selected—rising, falling, or both edges—by means of bits 2 and 3  
(ES10 and ES11) of INTM0.  
For valid edge detection, sampling is performed at the interval selected by means of the sampling clock  
selection register (SCS), and a capture operation is only performed when a valid level is detected twice, thus  
eliminating noise with a short pulse width.  
Figure 8-17. Control Register Settings for Pulse Width Measurement with  
Free-Running Counter and One Capture Register  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
0
1
0/1  
0
Free-Running Mode  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
1
0/1  
0
CR00 set as compare register  
CR01 set as capture register  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width  
measurement. See the description of the respective control registers for details.  
197  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter  
INTTM3  
2fXX  
fXX  
16-Bit Timer Register (TM0)  
OVF0  
fXX/2  
fXX/22  
16-Bit Capture/Compare  
Register 01 (CR01)  
TI00/P00/INTP00  
INTP0  
Internal Bus  
Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter  
and One Capture Register (with Both Edges Specified)  
t
Count Clock  
TM0 Count Value  
TI00 Pin Input  
0000 0001  
D0  
D1  
FFFF 0000  
D2  
D3  
CR01 Captured Value  
INTP0  
D0  
D1  
D2  
D3  
OVF0  
(D1 – D0) × t  
(10000H – D1 + D2) × t  
(D3 – D2) × t  
198  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(2) Measurement of two pulse widths with free-running counter  
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20),  
it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the  
TI01/P01 pin.  
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is  
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an  
external interrupt request signal (INTP0) is set.  
Also, when the edge specified by bits 4 and 5 (ES20 and ES21) of INTM0 is input to the TI01/P01 pin, the  
value of TM0 is taken into 16-bit capture/compare register 00 (CR00) and an external interrupt request signal  
(INTP1) is set.  
Any of three edge specifications can be selected—rising, falling, or both edges—as the valid edges for the  
TI00/P00 pin and the TI01/P01 pin by means of bits 2 and 3 (ES10 and ES11) and bits 4 and 5 (ES20 and  
ES21) of INTM0, respectively.  
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling  
clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice,  
thus eliminating noise with a short pulse width.  
Figure 8-20. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
0
1
0/1  
0
Free-Running Mode  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
1
1
1
CR00 set as capture register  
Captured in CR00 on invalid edge of  
TI00/P00 Pin  
CR01 set as capture register  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width  
measurement. See the description of the respective control registers for details.  
199  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-21. Timing of Pulse Width Measurement Operation with  
Free-Running Counter (with Both Edges Specified)  
t
Count Clock  
TM0 Count Value  
TI00 Pin Input  
0000 0001  
D0  
D1  
FFFF 0000  
D2  
D3  
D0  
D1  
D2  
D3  
CR01 Captured Value  
INTP0  
TI01 Pin Input  
CR00 Captured Value  
D1  
INTP1  
OVF0  
(10000H – D1 + D2) × t  
(D1 – D0) × t  
(D3 – D2) × t  
(10000H – D1 + (D2 + 1)) × t  
200  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(3) Pulse width measurement with free-running counter and two capture registers  
When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22),  
it is possible to measure the pulse width of the signal input to the TI00/P00 pin.  
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is  
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an  
external interrupt request signal (INTP0) is set.  
Also, on the inverse edge input of that of the capture operation into CR01, the value of TM0 is taken into 16-  
bit capture/compare register 00 (CR00).  
Either of two edge specifications can be selected—rising or falling—as the valid edges for the TI00/P00 pin  
by means of bits 2 and 3 (ES10 and ES11) of INTM0.  
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling  
clock selection register (SCS), and a capture operation is only performed when a valid level is detected twice,  
thus eliminating noise with a short pulse width.  
Caution If the valid edge of TI00/P00 is specified to be both rising and falling edge, capture/compare  
register 00 (CR00) cannot perform the capture operation.  
Figure 8-22. Control Register Settings for Pulse Width Measurement with  
Free-Running Counter and Two Capture Registers  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
0
1
0/1  
0
Free-Running Mode  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
1
1
1
CR00 set as capture register  
Captured in CR00 on invalid edge of  
TI00/P00 Pin  
CR01 set as capture register  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width  
measurement. See the description of the respective control registers for details.  
201  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running  
Counter and Two Capture Registers (with Rising Edge Specified)  
t
Count Clock  
TM0 Count Value  
TI00 Pin Input  
0000 0001  
D0  
D1  
FFFF 0000  
D2  
D3  
CR01 Captured Value  
CR00 Captured Value  
INTP0  
D0  
D2  
D1  
D3  
OVF0  
(D1-D0) × t  
(10000H-D1 + D2) × t  
(D3-D2) × t  
202  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(4) Pulse width measurement by means of restart  
When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0)  
is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the  
TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).  
The edge specification can be selected from two types, rising and falling edges by external interrupt mode  
register 0 (INTM0) bits 2 and 3 (ES10 and ES11).  
In a valid edge detection, the sampling is performed by a cycle selected by the sampling clock selection register  
(SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise  
with a short pulse width.  
Caution If the valid edge of TI00/P00 is specified to be both rising and falling edge, the 16-bit capture/  
compare register 00 (CR00) cannot perform the capture operation.  
Figure 8-24. Control Register Settings for Pulse Width Measurement by Means of Restart  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
1
0
0/1  
0
Clear & start with valid edge of TI00/P00 pin  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
1
1
1
CR00 set as capture register  
Captured in CR00 on invalid  
edge of TI00/P00 Pin  
CR01 set as capture register  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width  
measurement. See the description of the respective control registers for details.  
Figure 8-25. Timing of Pulse Width Measurement Operation by  
Means of Restart (with Rising Edge Specified)  
t
Count Clock  
TM0 Count Value  
TI00 Pin Input  
0000  
0001  
D0  
0000 0001 D1  
D2  
0000 0001  
CR01 Captured Value  
CR00 Captured Value  
D0  
D2  
D1  
INTP0  
D1 × t  
D2 × t  
203  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.5.5 External event counter operation  
The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the  
16-bit timer register (TM0).  
TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input.  
When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to  
0 and the interrupt request signal (INTTM00) is generated.  
Set the value other than 0000H to CR00 (1-pulse count operation cannot be performed).  
The rising edge, the falling edge or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0.  
Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected  
with the sampling clock select register (SCS), noise with short pulse widths can be removed.  
Figure 8-26. Control Register Settings in External Event Counter Mode  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
1
1
0/1  
0
Clear & start with match of TM0 and CR00  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
0/1  
0/1  
0
CR00 set as compare register  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event  
counter. See the description of the respective control registers for details.  
204  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-27. External Event Counter Configuration Diagram  
16-Bit Capture/Compare  
Register 00 (CR00)  
INTTM00  
Clear  
OVF0  
16-Bit Timer Register (TM0)  
TI00 Valid Edge  
INTP0  
16-Bit Capture/Compare  
Register 01 (CR01)  
Internal Bus  
Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified)  
TI00 Pin Input  
TM0 Count Value  
CR00  
0000 0001 0002 0003 0004 0005  
N-1  
N
0000 0001 0002 0003  
N
INTTM0  
Caution When reading the external event counter count value, TM0 should be read.  
205  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.5.6 Square-wave output operation  
Operates as square wave output with any selected frequency at intervals of the count value preset to the 16-bit  
capture/compare register 00 (CR00).  
The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0)  
and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected  
frequency to be output.  
Figure 8-29. Control Register Settings in Square-Wave Output Mode  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
1
1
0/1  
0
Clear & start on match of TM0 and CR00  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
0/1  
0/1  
0
CR00 set as compare register  
(c) 16-bit timer output control register (TOC0)  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
0/1 0/1  
TOC0  
0
0
0
0
1
1
TO0 Output Enabled  
Inversion of output on match of TM0 and CR00  
Specified TO0 output F/F initial value  
No inversion of output on match of TM0 and CR01  
One-shot pulse output disabled  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output.  
See the description of the respective control registers for details.  
206  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-30. Square-Wave Output Operation Timing  
Count Clock  
TM0 Count Value  
CR00  
0000 0001 0002  
N
N-1  
N
0000 0001  
0002  
N-1  
N
0000  
INTTM0  
TO0 Pin Output  
Table 8-7. 16-Bit Timer/Event Count Square-Wave Output Ranges  
Minimum Pulse Width  
Maximum Pulse Width  
MCS = 1 MCS = 0  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
16  
2 × TI00 input cycle  
2
× TI00 input cycle  
TI00 input edge cycle  
16  
2 × 1/fX  
2
× 1/fX  
1/fX  
(400 ns)  
(13.1 ms)  
(200 ns)  
2
16  
17  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(13.1 ms)  
(26.2 ms)  
(200 ns)  
2 × 1/fX  
(400 ns)  
2
3
17  
18  
2
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(800 ns)  
(1.6 µs)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
3
4
18  
19  
2
3
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(1.6 µs)  
(3.2 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
16  
2 × watch timer output cycle  
2
× watch timer output cycle  
Watch timer output edge cycle  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz  
207  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.5.7 One-shot pulse output operation  
It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin  
input).  
(1) One-shot pulse output using software trigger  
If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit  
timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0  
by software, a one-shot pulse is output from the TO0/P30 pin.  
By setting 1 in OSPT, the 16-bit timer/event counter is cleared and started, and output is activated by the count  
value set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivated by the  
count value set beforehand in 16-bit capture/compare register 00 (CR00).  
TM0 continues to operate after one-shot pulse is output. To stop TM0, 00H must be set to TMC0.  
Caution When outputting one-shot pulse, do not set 1 in OSPT. When outputting one-shot pulse  
again, set OSPT to 1 after the INTTM00, or interrupt match signal with CR00, is generated.  
Figure 8-31. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
1
1
0
0
Clear & start with match of TM0 and CR00  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
0
0/1  
0
CR00 set as compare register  
CR01 set as compare register  
(c) 16-bit timer output control register (TOC0)  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
0/1 0/1  
TOC0  
0
0
1
1
1
1
TO0 Output Enabled  
Inversion of output on match of TM0 and CR00  
Specified TO0 output F/F initial value  
Inversion of output on match of TM0 and CR01  
One-shot pulse output mode  
Set 1 in case of output  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.  
See the description of the respective control registers for details.  
Caution Values in the following range should be set in CR00 and CR01.  
0000H CR01 < CR00 FFFFH  
208  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-32. Timing of One-Shot Pulse Output Operation Using Software Trigger  
Set 0CH to TMC0  
(TM0 count start)  
Count Clock  
TM0 Count Value  
0000  
0001  
N
N+1  
0000  
N-1  
N
M-1  
M
0000 0001 0002  
CR01 Set Value  
CR00 Set Value  
OSPT  
N
N
N
N
M
M
M
M
INTTM01  
INTTM00  
TO0 Pin Output  
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation  
stop mode) is set to TMC01 to TMC03, respectively.  
209  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(2) One-shot pulse output using external trigger  
If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit  
timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/  
P30 pin with a TI00/P00 valid edge as an external trigger.  
Any of three edge specifications can be selected—rising, falling, or both edges — as the valid edges for the  
TI00/P00 pin by means of bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0).  
When a valid edge is input to the TI00/P00 pin, the 16-bit timer/event counter is cleared and started, and output  
is activated by the count values set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter,  
output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (CR00).  
Caution When outputting one-shot pulses, external trigger is ignored if generated again.  
Figure 8-33. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger  
(a) 16-bit timer mode control register (TMC0)  
TMC03 TMC02 TMC01 OVF0  
TMC0  
0
0
0
0
1
0
0
0
Clear & start with valid edge of TI00/P00 pin  
(b) Capture/compare control register 0 (CRC0)  
CRC02 CRC01 CRC00  
CRC0  
0
0
0
0
0
0
0/1  
0
CR00 set as compare register  
CR01 set as compare register  
(c) 16-bit timer output control register (TOC0)  
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0  
0/1 0/1  
TOC0  
0
0
1
1
1
1
TO0 Output Enabled  
Inversion of output on match of TM0 and CR00  
Specified TO0 output F/F initial value  
Inversion of output on match of TM0 and CR01  
One-shot pulse output mode  
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.  
See the description of the respective control registers for details.  
Caution Values in the following range should be set in CR00 and CR01.  
0000H CR01 < CR00 FFFFH  
210  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Figure 8-34. Timing of One-Shot Pulse Output Operation Using  
External Trigger (With Rising Edge Specified)  
Set 08H to TMC0  
(TM0 count start)  
Count Clock  
TM0 Count Value  
0000  
0000  
0001  
N
N+1 N+2  
M–2 M–1  
M
M+1 M+2 M+3  
CR01 Set Value  
CR00 Set Value  
TI00 Pin Input  
INTTM01  
N
N
N
N
M
M
M
M
INTTM00  
TO0 Pin Output  
Caution The 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation  
stop mode) is set to TMC01 to TMC03, respectively.  
211  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
8.6 16-Bit Timer/Event Counter Operating Precautions  
(1) Timer start errors  
An error with a maximum of one clock may occur concerning the time required for a match signal to be  
generated after timer start. This is because the 16-bit timer register (TM0) starts asynchronously with the count  
pulse.  
Figure 8-35. 16-Bit Timer Register Start Timing  
Count Pulse  
TM0 Count Value  
0000H  
0001H  
0002H  
0003H  
0004H  
Timer Start  
(2) 16-bit compare register setting  
Set a value other than 0000H to the 16-bit capture/compare register 00 (CR00).  
Thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot  
be carried out.  
(3) Operation after compare register change during timer count operation  
If the value after the 16-bit capture/compare register (CR00) is changed is smaller than that of the 16-bit timer  
register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M)  
after CR00 change is smaller than that (N) before change, it is necessary to restart the timer after changing  
CR00.  
Figure 8-36. Timings After Change of Compare Register During Timer Count Operation  
Count Pulse  
CR00  
M
N
TM0 Count Value  
X-1  
X
FFFFH  
0000H  
0001H  
0002H  
Remark N > X > M  
212  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(4) Capture register data retention timings  
If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01  
holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon  
detection of the valid edge.  
Figure 8-37. Capture Register Data Retention Timing  
Count Pulse  
TM0 Count Value  
Edge Input  
N
N+1  
N+2  
M
M+1  
M+2  
Interrupt  
Request Flag  
Capture Read Signal  
CR01 Captured Value  
X
N+1  
Capture Operation  
Ignored  
(5) Valid edge setting  
Set the valid edge of the TI00/P00/INTP0 pin after setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer  
mode control register (TMC0) to 0, 0 and 0, respectively, and then stopping timer operation. Valid edge is  
set with bits 2 and 3 (ES10 and ES11) of the external interrupt mode register 0 (INTM0).  
(6) Re-trigger of one-shot pulse  
(a) One-shot pulse output using software  
When outputting one-shot pulse, do not set 1 in OSPT. When outputting one-shot pulse again, set OSPT  
to 1 after the INTTM00, or interrupt match signal with CR00, is generated.  
(b) One-shot pulse output using external trigger  
When outputting one-shot pulses, external trigger is ignored if generated again.  
213  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
(7) Operation of OVF0 flag  
OFV0 flag is set to 1 in the following case.  
The clear & start mode on match between TM0 and CR00 is selected.  
CR00 is set to FFFFH.  
When TM0 is counted up from FFFFH to 0000H.  
Figure 8-38. Operation Timing of OVF0 Flag  
Count Pulse  
CR00  
TM0  
FFFFH  
FFFEH  
FFFFH  
0000H  
0001H  
OVF0  
INTTM00  
214  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
9.1 8-Bit Timer/Event Counters 1 and 2 Functions  
For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/  
event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/  
event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode).  
9.1.1 8-bit timer/event counter mode  
The 8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions.  
• Interval timer  
• External event counter  
• Square-wave output  
215  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(1) 8-bit interval timer  
Interrupt requests are generated at the preset time intervals.  
Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times  
Minimum Interval Time  
Maximum Interval Time  
MCS = 1 MCS = 0  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
2
9
10  
2
2 × 1/fX  
(400 ns)  
2 × 1/fX  
2 × 1/fX  
(102.4 µs)  
10  
2
× 1/fX  
2 × 1/fX  
(400 ns)  
2 × 1/fX  
(800 ns)  
(204.8 µs)  
(800 ns)  
2
3
11  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(204.8 µs)  
(409.6 µs)  
(800 ns)  
(1.6 µs)  
3
4
11  
12  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(409.6 µs)  
(819.2 µs)  
(1.6 µs)  
(3.2 µs)  
4
5
12  
13  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(819.2 µs)  
(1.64 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
13  
14  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(1.64 ms)  
(3.28 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
14  
15  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(3.28 ms)  
(6.55 ms)  
(12.8 µs)  
(25.6 µs)  
7
8
15  
16  
7
8
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(6.55 ms)  
(13.1 ms)  
(25.6 µs)  
(51.2 µs)  
8
9
16  
17  
8
9
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(13.1 ms)  
(26.2 ms)  
(51.2 µs)  
(102.4 µs)  
9
10  
17  
18  
9
10  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(26.2 ms)  
(52.4 ms)  
(102.4 µs)  
(204.8 µs)  
11  
12  
19  
20  
11  
12  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(104.9 ms)  
(209.7 ms)  
(409.6 µs)  
(819.2 µs)  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz.  
216  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(2) External event counter  
The number of pulses of an externally input signal can be measured.  
(3) Square-wave output  
A square wave with any selected frequency can be output.  
Table 9-2. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges  
Minimum Pulse Width  
MCS = 1 MCS = 0  
Maximum Pulse Width  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
2
9
10  
2
2 × 1/fX  
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(102.4 µs)  
(204.8 µs)  
(400 ns)  
(800 ns)  
2
3
10  
11  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(204.8 µs)  
(409.6 µs)  
(800 ns)  
(1.6 µs)  
3
4
11  
12  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(409.6 µs)  
(819.2 µs)  
(1.6 µs)  
(3.2 µs)  
4
5
12  
13  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(819.2 µs)  
(1.64 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
13  
14  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(1.64 ms)  
(3.28 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
14  
15  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(3.28 ms)  
(6.55 ms)  
(12.8 µs)  
(25.6 µs)  
7
8
15  
16  
7
8
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(6.55 ms)  
(13.1 ms)  
(25.6 µs)  
(51.2 µs)  
8
9
16  
17  
8
9
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(13.1 ms)  
(26.2 ms)  
(51.2 µs)  
(102.4 µs)  
9
10  
17  
18  
9
10  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(26.2 ms)  
(52.4 ms)  
(102.4 µs)  
(204.8 µs)  
11  
12  
19  
20  
11  
12  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(104.9 ms)  
(209.7 ms)  
(409.6 µs)  
(819.2 µs)  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz.  
217  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
9.1.2 16-bit timer/event counter mode  
(1) 16-bit interval timer  
Interrupt requests can be generated at the preset time intervals.  
Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2  
are Used as 16-Bit Timer/Event Counters  
Minimum Interval Time  
Maximum Interval Time  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
2
17  
18  
2
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
2
3
18  
19  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
3
4
19  
20  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(104.9 ms)  
(209.7 ms)  
(1.6 µs)  
(3.2 µs)  
4
5
20  
21  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(209.7 ms)  
(419.4 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
21  
22  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(419.4 ms)  
(838.9 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
22  
23  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
2
2
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(838.9 ms)  
(1.7 s)  
(12.8 µs)  
(25.6 µs)  
7
8
23  
24  
7
8
2 × 1/fX  
2 × 1/fX  
2
2
2
2
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(1.7 s)  
(3.4 s)  
(25.6 µs)  
(51.2 µs)  
8
9
24  
25  
8
9
2 × 1/fX  
2 × 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(3.4 s)  
(6.7 s)  
(51.2 µs)  
(102.4 µs)  
9
10  
25  
26  
9
10  
2 × 1/fX  
2
× 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(6.7 s)  
(13.4 s)  
(102.4 µs)  
(204.8 µs)  
11  
12  
27  
28  
11  
12  
2
× 1/fX  
2
× 1/fX  
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(26.8 s)  
(53.7 s)  
(409.6 µs)  
(819.2 µs)  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz.  
218  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(2) External event counter  
The number of pulses of an externally input signal can be measured.  
(3) Square-wave output  
A square wave with any selected frequency can be output.  
Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event  
Counters 1 and 2 are Used as 16-Bit Timer/Event Counters  
Minimum Pulse Width  
MCS = 1 MCS = 0  
Maximum Pulse Width  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
2
17  
18  
2
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
2
3
18  
19  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
3
4
19  
20  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(104.9 ms)  
(209.7 ms)  
(1.6 µs)  
(3.2 µs)  
4
5
20  
21  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(209.7 ms)  
(419.4 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
21  
22  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(419.4 ms)  
(838.9 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
22  
23  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
2
2
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(838.9 ms)  
(1.7 s)  
(12.8 µs)  
(25.6 µs)  
7
8
23  
24  
7
8
2 × 1/fX  
2 × 1/fX  
2
2
2
2
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(1.7 s)  
(3.4 s)  
(25.6 µs)  
(51.2 µs)  
8
9
24  
25  
8
9
2 × 1/fX  
2 × 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(3.4 s)  
(6.7 s)  
(51.2 µs)  
(102.4 µs)  
9
10  
25  
26  
9
10  
2 × 1/fX  
2
× 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(6.7 s)  
(13.4 s)  
(102.4 µs)  
(204.8 µs)  
11  
12  
27  
28  
11  
12  
2
× 1/fX  
2
× 1/fX  
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(26.8 s)  
(53.7 s)  
(409.6 µs)  
(819.2 µs)  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz.  
219  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
9.2 8-Bit Timer/Event Counters 1 and 2 Configurations  
The 8-bit timer/event counters 1 and 2 consist of the following hardware.  
Table 9-5. 8-Bit Timer/Event Counters 1 and 2 Configurations  
Item  
Timer register  
Register  
Configuration  
8 bits × 2 (TM1, TM2)  
Compare register: 8 bits × 2 (CR10, CR20)  
Timer output  
2 (TO1, TO2)  
Timer clock select register 1 (TCL1)  
8-bit timer mode control register 1 (TMC1)  
Control register  
8-bit timer output control register (TOC1)  
Note  
Port mode register 3 (PM3)  
Note Refer to Figure 6-9. Block Diagram of P30 to P37.  
220  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Figure 9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram  
Internal Bus  
INTTM1  
8-Bit Compare  
Register (CR20)  
8-Bit Compare  
Register (CR10)  
Note  
8-Bit Timer/  
Event Counter  
Output Control  
Circuit 2  
Match  
TO2/P32  
INTTM2  
Match  
fXX/2-fXX/29  
8-Bit Timer  
Register 1 (TM1)  
4
fXX/211  
8-Bit Timer  
Register 2 (TM2)  
TI1/P33  
Clear  
4
Clear  
Selector  
fXX/2-fXX/29  
fXX/211  
TI2/P34  
Note  
8-Bit Timer/  
Event Counter  
Output Control  
Circuit  
4
TO1/P31  
4
TCL TCL TCL TCL TCL TCL TCL TCL  
17 16 15 14 13 12 11 10  
TOC  
15  
TOC  
11  
TMC12 TCE2 TCE1  
LVS2 LVR2  
TOE2LVS1 LVR1  
TOE1  
Timer Clock  
Select Register 1  
8-Bit Timer Mode  
Control Register  
8-Bit Timer Output  
Control Register  
Internal Bus  
Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counters 1 and 2 output control circuits 1 and  
2, respectively.  
221  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1  
Level F/F  
(LV1)  
LVR1  
R
Q
TO1/P31  
S
LVS1  
P31  
Output Latch  
PM31  
TOC11  
INV  
INTTM1  
TOE1  
Remark The section in the broken line is an output control circuit.  
Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2  
Level F/F  
(LV2)  
fSCK  
LVR2  
R
Q
TO2/P32  
LVS2  
S
P32  
Output Latch  
PM32  
TOC15  
INV  
INTTM2  
TOE2  
Remarks 1. The section in the broken line is an output control circuit.  
2. fSCK : Serial clock frequency  
222  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(1) Compare registers 10 and 20 (CR10, CR20)  
These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value,  
and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an  
interrupt request (INTTM1 and INTTM2, respectively).  
This register can also be used as the register which holds the interval time when setting TM1 and TM2 to interval  
timer operation.  
CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit  
memory manipulation instruction. When the compare register is used as 8-bit timer/event counter, the 00H  
to FFH values can be set. When the compare register is used as 16-bit timer/event counter, the 0000H to  
FFFFH values can be set.  
RESET input makes CR10 and CR20 undefined.  
Caution When using the compare register as 16-bit timer/event counter, be sure to set data after  
stopping timer operation.  
(2) 8-bit timer registers 1, 2 (TM1, TM2)  
These are 8-bit registers to count count pulses.  
When TM1 and TM2 are used in the 8-bit timer × 2-channel mode, they are read with an 8-bit memory  
manipulation instruction. When TM1 and TM2 are used as 16-bit timer × 1-channel mode, 16-bit timer (TMS)  
is read with a 16-bit memory manipulation instruction.  
RESET input sets TM1 and TM2 to 00H.  
9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers  
The following four types of registers are used to control the 8-bit timer/event counter.  
• Timer clock select register 1 (TCL1)  
• 8-bit timer mode control register 1 (TMC1)  
• 8-bit timer output control register (TOC1)  
• Port mode register 3 (PM3)  
(1) Timer clock select register 1 (TCL1)  
This register sets count clocks of 8-bit timer registers 1 and 2.  
TCL1 is set with an 8-bit memory manipulation instruction.  
RESET input sets TCL1 to 00H.  
223  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Figure 9-4. Timer Clock Select Register 1 Format  
Address  
FF41H  
After Reset  
00H  
R/W  
R/W  
Symbol  
TCL1  
7
6
5
4
3
2
1
0
TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10  
8-Bit Timer Register 1 Count Clock Selection  
TCL13 TCL12 TCL11 TCL10  
MCS = 1  
TI1 falling edge  
MCS = 0  
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
TI1 rising edge  
fXX/2  
f
f
f
f
f
f
f
f
f
f
X/2 (2.5 MHz)  
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
X/29 (9.8 kHz)  
X/211 (2.4 kHz)  
f
f
f
f
f
f
f
f
f
f
X
/22  
/23  
/24  
/25  
/26  
/27  
/28  
/29  
/210  
/212  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
(4.9 kHz)  
(1.2 kHz)  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
fXX/29  
fXX/211  
X
X
X
X
X
X
X
X
X
Other than above  
Setting prohibited  
8-Bit Timer Register 2 Count Clock Selection  
TCL17 TCL16 TCL15 TCL14  
MCS = 1  
TI2 falling edge  
MCS = 0  
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
TI2 rising edge  
fXX/2  
f
f
f
f
f
f
f
f
f
f
X/2 (2.5 MHz)  
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
X/29 (9.8 kHz)  
X/211 (2.4 kHz)  
f
f
f
f
f
f
f
f
f
f
X
/22  
/23  
/24  
/25  
/26  
/27  
/28  
/29  
/210  
/212  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
(4.9 kHz)  
(1.2 kHz)  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
fXX/29  
fXX/211  
X
X
X
X
X
X
X
X
X
Other than above  
Setting prohibited  
Caution When rewriting TCL1 to other data, stop the timer operation beforehand.  
Remarks 1. fXX  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
2. fX  
3. TI1 : 8-bit timer register 1 input pin  
4. TI2 : 8-bit timer register 2 input pin  
5. MCS : Oscillation mode selection register (OSMS) bit 0  
6. Figures in parentheses apply to operation with fX = 5.0 MHz  
224  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(2) 8-bit timer mode control register (TMC1)  
This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer  
register 1 and 2.  
TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets TMC1 to 00H.  
Figure 9-5. 8-Bit Timer Mode Control Register 1 Format  
Address  
FF49H  
After Reset  
00H  
R/W  
R/W  
Symbol  
TMC1  
7
0
6
0
5
0
4
0
3
0
2
<1> <0>  
TMC12 TCE2 TCE1  
TCE1 8-Bit Timer Register 1 Operation Control  
0
1
Operation stop (TM1 clear to 0)  
Operation enable  
TCE2 8-Bit Timer Register 2 Operation Control  
0
1
Operation stop (TM2 clear to 0)  
Operation enable  
TMC12 Operating Mode Selection  
0
1
8-Bit timer register × 2 channel mode (TM1, TM2)  
16-Bit timer register × 1 channel mode (TMS)  
Cautions 1. Switch the operating mode after stopping timer operation.  
2. When used as 16-bit timer register, TCE1 should be used for control enable/stop.  
225  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(3) 8-bit timer output control register (TOC1)  
This register controls operation of 8-bit timer/event counter output control circuits 1 and 2.  
It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit  
timer registers 1 and 2.  
TOC1 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets TOC1 to 00H.  
Figure 9-6. 8-Bit Timer Output Control Register Format  
Symbol <7> <6>  
5
<4>  
<3> <2>  
1
<0>  
Address  
FF4FH  
After Reset  
00H  
R/W  
R/W  
TOC1 LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1  
TOE1 8-Bit Timer/Event Counter 1 Outptut Control  
0
1
Output disable (port mode)  
Output enable  
TOC11 8-Bit Timer/Event Counter 1 Timer Output F/F Control  
0
1
Inverted operation disable  
Inverted operation enable  
8-Bit Timer/Event Counter 1 Timer Output F/F Status Set  
Unchanged  
LVS1 LVR1  
0
0
1
0
1
0
Timer output F/F reset (0)  
Timer output F/F set (1)  
1
1
Setting prohibited  
TOE2 8-Bit Timer/Event Counter 2 Output Control  
0
1
Output disable (port mode)  
Output enable  
TOC15 8-Bit Timer/Event Counter 2 Timer Output F/F Control  
0
1
Inverted operation disable  
Inverted operation enable  
8-Bit Timer/Event Counter 2 Timer Output F/F Status Set  
Unchanged  
LVS2 LVR2  
0
0
1
0
1
0
Timer output F/F reset (0)  
Timer output F/F set (1)  
1
1
Setting prohibited  
Cautions 1. Be sure to set TOC1 after stopping timer operation.  
2. After data setting, 0 can be read from LVS1, LVS2, LVR1 and LVR2.  
226  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(4) Port mode register 3 (PM3)  
This register sets port 3 input/output in 1-bit units.  
When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and  
P32 to 0.  
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets PM3 to FFH.  
Figure 9-7. Port Mode Register 3 Format  
Address  
FF23H  
After Reset  
FFH  
R/W  
R/W  
Symbol  
7
6
5
4
3
2
1
0
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30  
PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7)  
0
1
Output mode (output buffer ON)  
Input mode (output buffer OFF)  
227  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
9.4 8-Bit Timer/Event Counters 1 and 2 Operations  
9.4.1 8-bit timer/event counter mode  
(1) Interval timer operations  
The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly  
at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).  
When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and  
CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1  
and INTTM2) are generated.  
Count clock of TM1 can be selected with bits 0 to 3 (TCL10 to TCL13) of the timer clock select register 1 (TCL1).  
Count clock of TM2 can be selected with bits 4 to 7 (TCL14 to TCL17) of the timer clock select register 1 (TCL1).  
For the operation when the value of the compare register is changed during the timer count operation, refer  
to 9.5 8-Bit Timer/Event Counter Precautions (3).  
Figure 9-8. Interval Timer Operation Timings  
t
Count Clock  
TM1 Count Value  
00  
01  
N
00  
Clear  
01  
N
00  
Clear  
01  
N
Count Start  
N
CR10  
N
N
N
INTTM1  
Interrupt Request Acknowledge Interrupt Request Acknowledge  
TO1  
Interval Time  
Interval Time  
Interval Time  
Remark Interval time = (N + 1) × t : N = 00H to FFH  
228  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time  
Minimum Interval Time  
MCS = 1 MCS = 0  
TI1 input cycle  
Maximum Interval Time  
Resolution  
MCS = 1 MCS = 0  
TCL13 TCL12 TCL11 TCL10  
MCS = 1  
MCS = 0  
8
0
0
0
0
0
0
0
1
2 × TI1 input cycle  
TI1 input edge cycle  
8
TI1 input cycle  
2 × TI1 input cycle  
TI1 input edge cycle  
2
9
10  
2
2 × 1/fX  
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
(400 ns)  
(800 ns)  
(102.4 µs)  
(204.8 µs)  
(400 ns)  
(800 ns)  
2
3
10  
11  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(204.8 µs)  
(409.6 µs)  
(800 ns)  
(1.6 µs)  
3
4
11  
12  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(409.6 µs)  
(819.2 µs)  
(1.6 µs)  
(3.2 µs)  
4
5
12  
13  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(819.2 µs)  
(1.64 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
13  
14  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(1.64 ms)  
(3.28 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
14  
15  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(3.28 ms)  
(6.55 ms)  
(12.8 µs)  
(25.6 µs)  
7
8
15  
16  
7
8
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(6.55 ms)  
(13.1 ms)  
(25.6 µs)  
(51.2 µs)  
8
9
16  
17  
8
9
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(13.1 ms)  
(26.2 ms)  
(51.2 µs)  
(102.4 µs)  
9
10  
17  
18  
9
10  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(26.2 ms)  
(52.4 ms)  
(102.4 µs)  
(204.8 µs)  
11  
12  
19  
20  
11  
12  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(104.9 ms) (209.7 ms)  
(409.6 µs)  
(819.2 µs)  
Other than above  
Setting prohibited  
Remarks 1. fX  
: Main system clock oscillation frequency  
: Oscillation mode selection register (OSMS) bit 0  
2. MCS  
3. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register 1 (TCL1)  
4. Values in parentheses when operated at fX = 5.0 MHz.  
229  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time  
Minimum Interval Time  
MCS = 1 MCS = 0  
TI2 input cycle  
Maximum Interval Time  
Resolution  
MCS = 1 MCS = 0  
TCL17 TCL16 TCL15 TCL14  
MCS = 1  
MCS = 0  
8
0
0
0
0
0
0
0
1
2 × TI2 input cycle  
TI2 input edge cycle  
8
TI2 input cycle  
2 × TI2 input cycle  
TI2 input edge cycle  
2
9
10  
2
2 × 1/fX  
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
(400 ns)  
(800 ns)  
(102.4 µs)  
(204.8 µs)  
(400 ns)  
(800 ns)  
2
3
10  
11  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(204.8 µs)  
(409.6 µs)  
(800 ns)  
(1.6 µs)  
3
4
11  
12  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(409.6 µs)  
(819.2 µs)  
(1.6 µs)  
(3.2 µs)  
4
5
12  
13  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(819.2 µs)  
(1.64 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
13  
14  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(1.64 ms)  
(3.28 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
14  
15  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(3.28 ms)  
(6.55 ms)  
(12.8 µs)  
(25.6 µs)  
7
8
15  
16  
7
8
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(6.55 ms)  
(13.1 ms)  
(25.6 µs)  
(51.2 µs)  
8
9
16  
17  
8
9
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(13.1 ms)  
(26.2 ms)  
(51.2 µs)  
(102.4 µs)  
9
10  
17  
18  
9
10  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(26.2 ms)  
(52.4 ms)  
(102.4 µs)  
(204.8 µs)  
11  
12  
19  
20  
11  
12  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(104.9 ms) (209.7 ms)  
(409.6 µs)  
(819.2 µs)  
Other than above  
Setting prohibited  
Remarks 1. fX  
: Main system clock oscillation frequency  
: Bit 0 of oscillation mode selection register (OSMS)  
2. MCS  
3. TCL14 to TCL17 : Bits 4 to 7 of timer clock select register 1 (TCL1)  
4. Values in parentheses when operated at fX = 5.0 MHz  
230  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(2) External event counter operation  
The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/  
P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2).  
TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1)  
is input. Either the rising or falling edge can be selected.  
When the TM1 and TM2 counted values match the values of 8-bit compare registers (CR10 and CR20), TM1  
and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.  
Figure 9-9. External Event Counter Operation Timings (with Rising Edge Specified)  
TI1 Pin Input  
TM1 Count Value  
CR10  
00  
01  
02  
03  
04  
05  
N
N-1  
N
00  
01  
02  
03  
INTTM1  
Remark N = 00H to FFH  
231  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(3) Square-wave output operation  
Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit  
compare register 10 and 20 (CR10, CR20).  
The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20  
by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables  
a square wave with any selected frequency to be output.  
Table 9-8. 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges  
Minimum Pulse Width  
MCS = 1 MCS = 0  
Maximum Pulse Width  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
2
9
10  
2
2 × 1/fX  
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(102.4 µs)  
(204.8 µs)  
(400 ns)  
(800 ns)  
2
3
10  
11  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(204.8 µs)  
(409.6 µs)  
(800 ns)  
(1.6 µs)  
3
4
11  
12  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(409.6 µs)  
(819.2 µs)  
(1.6 µs)  
(3.2 µs)  
4
5
12  
13  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(819.2 µs)  
(1.64 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
13  
14  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(1.64 ms)  
(3.28 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
14  
15  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(3.28 ms)  
(6.55 ms)  
(12.8 µs)  
(25.6 µs)  
7
8
15  
16  
7
8
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(6.55 ms)  
(13.1 ms)  
(25.6 µs)  
(51.2 µs)  
8
9
16  
17  
8
9
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(13.1 ms)  
(26.2 ms)  
(51.2 µs)  
(102.4 µs)  
9
10  
17  
18  
9
10  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(26.2 ms)  
(52.4 ms)  
(102.4 µs)  
(204.8 µs)  
11  
12  
19  
20  
11  
12  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(104.9 ms)  
(209.7 ms)  
(409.6 µs)  
(819.2 µs)  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz.  
232  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Figure 9-10. Square-Wave Output Operation Timing  
Count Clock  
TM1 Count Value  
CR10  
00  
01  
02  
N
N-1  
N
00  
01  
02  
N-1  
N
00  
INTTM1  
TO1 Pin OutputNote  
Note The initial value of TO1 pin output can be set with the bits 2 and 3 (LVR1, LVS1) of 8-bit timer output control  
register (TOC1).  
233  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
9.4.2 16-bit timer/event counter mode  
When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode  
is set.  
In this mode, the count clock is set with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1), and  
the overflow signal of 8-bit timer register 1 (TM1) becomes the count clock of 8-bit timer register 2 (TM2).  
In this mode, enable/disable of the count operation is selected with bit 0 (TCE1) of TMC1.  
(1) Operation as interval timer  
The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at  
intervals of the count value preset to 2-channel 8-bit compare registers (CR10 and CR20). When setting the  
count value, set the value of the higher 8 bits to CR20 and the value of the lower 8 bits to CR10. For the count  
value that can be set, refer to Table 9-9.  
When 8-bit timer register 1 (TM1) and CR10 values match and 8-bit timer register 2 (TM2) and CR20 values  
match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal (INTTM2)  
is generated. For the timing of interval timer operation, refer to Figure 9-11.  
The count clock is selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1), and  
the overflow signal of TM1 becomes the count clock of TM2.  
Figure 9-11. Interval Timer Operation Timing  
t
Count Clock  
TMS (TM1, TM2) Count Value  
0000 0001  
Count Start  
N
0000 0001  
Clear  
N
0000 0001  
Clear  
N
CR10, CR20  
INTTM2  
N
N
N
N
Interrupt Request Acknowledge Interrupt Request Acknowledge  
TO2  
Interval Time  
Interval Time  
Interval Time  
Remark Interval time = (N + 1) × t : N = 0000H to FFFFH  
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the  
CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter  
output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit  
interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.  
Whenreadingthe16-bittimerregister(TMS)countvalue, usethe16-bitmemorymanipulation  
instruction.  
234  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2)  
are Used as 16-Bit Timer/Event Counter  
Minimum Interval Time  
MCS = 1 MCS = 0  
TI1 input cycle  
Maximum Interval Time  
Resolution  
MCS = 1 MCS = 0  
TCL13 TCL12 TCL11 TCL10  
MCS = 1  
MCS = 0  
8
0
0
0
0
0
0
0
1
2 × TI1 input cycle  
TI1 input edge cycle  
8
TI1 input cycle  
2 × TI1 input cycle  
TI1 input edge cycle  
2
17  
18  
2
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
(400 ns)  
(800 ns)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
2
3
18  
19  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
3
4
19  
20  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(104.9 ms) (209.7 ms)  
(1.6 µs)  
(3.2 µs)  
4
5
20  
21  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(209.7 ms) (419.4 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
21  
22  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(419.4 ms) (838.9 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
22  
23  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
2
2
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(838.9 ms)  
(1.7 s)  
(12.8 µs)  
(25.6 µs)  
7
8
23  
24  
7
8
2 × 1/fX  
2 × 1/fX  
2
2
2
2
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(1.7 s)  
(3.4 s)  
(25.6 µs)  
(51.2 µs)  
8
9
24  
25  
8
9
2 × 1/fX  
2 × 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(3.4 s)  
(6.7 s)  
(51.2 µs)  
(102.4 µs)  
9
10  
25  
26  
9
10  
2 × 1/fX  
2
× 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(6.7 s)  
(13.4 s)  
(102.4 µs)  
(204.8 µs)  
11  
12  
27  
28  
11  
12  
2
× 1/fX  
2
× 1/fX  
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(26.8 s)  
(53.7 s)  
(409.6 µs)  
(819.2 µs)  
Other than above  
Setting prohibited  
Remarks 1. fX  
: Main system clock oscillation frequency  
: Oscillation mode selection register (OSMS) bit 0  
2. MCS  
3. TCL10 to TCL13 : Bits 0 to 3 of timer clock select register (TCL1)  
4. Values in parentheses when operated at fX = 5.0 MHz.  
235  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(2) External event counter operations  
The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2-  
channel 8-bit timer registers 1 and 2 (TM1 and TM2).  
TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input.  
When TM1 overflows, TM2 is incremented with the overflow signal as the count clock. Either the rising or  
falling edge can be selected.  
When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and  
CR20), TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated.  
Figure 9-12. External Event Counter Operation Timings (with Rising Edge Specified)  
TI1 Pin Input  
TM1, TM2 Count Value  
0000 0001 0002 0003 0004 0005  
N-1  
N
0000 0001 0002 0003  
N
CR10, CR20  
INTTM2  
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the  
CR10 value, interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter  
output control circuit 1 is inverted. Thus, when using 8-bit timer/event counter as 16-bit  
interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.  
Whenreadingthe16-bittimerregister(TMS)countvalue, usethe16-bitmemorymanipulation  
instruction.  
236  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(3) Square-wave output operation  
Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit  
compare registers 10 and 20 (CR10, CR20). When setting the count value, set the value of higher 8 bits to  
CR20 and the value of lower 8 bits to CR10.  
The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting  
bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected  
frequency to be output.  
Table 9-10. Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters  
(TM1 and TM2) are Used as 16-Bit Timer/Event Counter  
Minimum Pulse Width  
MCS = 1 MCS = 0  
Maximum Pulse Width  
Resolution  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
2
17  
18  
2
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(400 ns)  
(800 ns)  
(26.2 ms)  
(52.4 ms)  
(400 ns)  
(800 ns)  
2
3
18  
19  
2
3
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(800 ns)  
(1.6 µs)  
(52.4 ms)  
(104.9 ms)  
(800 ns)  
(1.6 µs)  
3
4
19  
20  
3
4
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(1.6 µs)  
(3.2 µs)  
(104.9 ms)  
(209.7 ms)  
(1.6 µs)  
(3.2 µs)  
4
5
20  
21  
4
5
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(3.2 µs)  
(6.4 µs)  
(209.7 ms)  
(419.4 ms)  
(3.2 µs)  
(6.4 µs)  
5
6
21  
22  
5
6
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(6.4 µs)  
(12.8 µs)  
(419.4 ms)  
(838.9 ms)  
(6.4 µs)  
(12.8 µs)  
6
7
22  
23  
6
7
2 × 1/fX  
2 × 1/fX  
2
× 1/fX  
2
2
2
2
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(12.8 µs)  
(25.6 µs)  
(838.9 ms)  
(1.7 s)  
(12.8 µs)  
(25.6 µs)  
7
8
23  
24  
7
8
2 × 1/fX  
2 × 1/fX  
2
2
2
2
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(25.6 µs)  
(51.2 µs)  
(1.7 s)  
(3.4 s)  
(25.6 µs)  
(51.2 µs)  
8
9
24  
25  
8
9
2 × 1/fX  
2 × 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2 × 1/fX  
(51.2 µs)  
(102.4 µs)  
(3.4 s)  
(6.7 s)  
(51.2 µs)  
(102.4 µs)  
9
10  
25  
26  
9
10  
2 × 1/fX  
2
× 1/fX  
× 1/fX  
× 1/fX  
2 × 1/fX  
2
× 1/fX  
(102.4 µs)  
(204.8 µs)  
(6.7 s)  
(13.4 s)  
(102.4 µs)  
(204.8 µs)  
11  
12  
27  
28  
11  
12  
2
× 1/fX  
2
× 1/fX  
× 1/fX  
2
× 1/fX  
2
× 1/fX  
2
× 1/fX  
(409.6 µs)  
(819.2 µs)  
(26.8 s)  
(53.7 s)  
(409.6 µs)  
(819.2 µs)  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Oscillation mode selection register (OSMS) bit 0  
3. Values in parentheses when operated at fX = 5.0 MHz.  
237  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
Figure 9-13. Square-Wave Output Operation Timing  
Count Clock  
TM1, TM2 Count Value  
CR10, CR20  
0000 0001 0002  
N
N-1  
N
0000 0001  
0002  
N-1  
N
0000  
INTTM2  
TO2 Pin OutputNote  
Note The initial value of TO2 pin output can be set with the bits 6 and 7 (LVR2, LVS2) of 8-bit timer output control  
register (TOC1).  
9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2  
(1) Timer start errors  
An error with a maximum of one clock may occur concerning the time required for a match signal to be  
generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) starts asynchronously  
with the count pulse.  
Figure 9-14. 8-Bit Timer Registers 1 and 2 Start Timing  
Count Pulse  
TM1, TM2 Count Value  
00H  
01H  
02H  
03H  
04H  
Timer Start  
238  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2  
(2) 8-bit compare register 10 and 20 setting  
The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H.  
Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be  
carried out.  
When the 8-bit compare register is used as 16-bit timer/event counter, write data to CR10 and CR20 after  
setting bit 0 (TCE1) of the 8-bit timer mode control register 1 to 0 and stopping timer operation.  
Figure 9-15. Event Counter Operation Timing  
TI1, TI2, Input  
CR10, CR20  
00H  
TM1, TM2 Count Value  
TO1, TO2  
00H  
00H  
00H  
00H  
Interrupt Request Flag  
(3) Operation after compare register change during timer count operation  
If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those  
of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting  
from 0. Thus, if the value (M) after CR10 and CR20 change is smaller than value (N) before the change, it  
is necessary to restart the timer after changing CR10 and CR20.  
Figure 9-16. Timing after Compare Register Change during Timer Count Operation  
Count Pulse  
CR10, CR20  
N
M
TM1, TM2 Count Value  
X-1  
X
FFH  
00H  
01H  
02H  
Remark N > X > M  
239  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
240  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 10 WATCH TIMER  
10.1 Watch Timer Functions  
The watch timer has the following functions.  
• Watch timer  
• Interval timer  
The watch timer and the interval timer can be used simultaneously.  
(1) Watch timer  
When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.  
When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second  
or 0.25 second intervals.  
Caution 0.5-second intervals cannot be generated with the 5.0-MHz main system clock. You should  
switch to the 32.768 kHz subsystem clock to generate 0.5-second intervals.  
(2) Interval timer  
Interrupt requests (INTTM3) are generated at the preset time interval.  
Table 10-1. Interval Timer Interval Time  
When operated at  
fXX = 5.0 MHz  
When operated at  
fXX = 4.19 MHz  
When operated at  
fXT = 32.768 kHz  
Interval Time  
4
2 × 1/fW  
410 µs  
819 µs  
488 µs  
977 µs  
488 µs  
977 µs  
5
2 × 1/fW  
6
2 × 1/fW  
1.64 ms  
3.28 ms  
6.55 ms  
13.1 ms  
1.95 ms  
3.91 ms  
7.81 ms  
15.6 ms  
1.95 ms  
3.91 ms  
7.81 ms  
15.6 ms  
7
2 × 1/fW  
8
2 × 1/fW  
9
2 × 1/fW  
Remark fXX : Main system clock frequency (fX or fX/2)  
fX : Main system clock oscillation frequency  
fXT : Subsystem clock oscillation frequency  
7
fW : Watch timer clock frequency (fXX/2 or fXT)  
241  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 10 WATCH TIMER  
10.2 Watch Timer Configuration  
The watch timer consists of the following hardware.  
Table 10-2. Watch Timer Configuration  
Configuration  
Item  
Counter  
5 bits × 1  
Timer clock select register 2 (TCL2)  
Control register  
Watch timer mode control register (TMC2)  
10.3 Watch Timer Control Registers  
The following two types of registers are used to control the watch timer.  
• Timer clock select register 2 (TCL2)  
• Watch timer mode control register (TMC2)  
(1) Timer clock select register 2 (TCL2) (Refer to Figure 10-2.)  
This register sets the watch timer count clock.  
TCL2 is set with an 8-bit memory manipulation instruction.  
RESET input sets TCL2 to 00H.  
Remark Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer  
output frequency.  
242  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 10 WATCH TIMER  
Figure 10-1. Watch Timer Block Diagram  
TMC21  
f
W
214  
Clear  
Prescaler  
f
XX/27  
5-Bit Counter  
f
W
INTWT  
Clear  
f
XT  
f
W
27  
f
W
f
W
f
W
f
W
f
W
f
W
213  
24 25 26  
28 29  
INTTM3  
To 16-Bit Timer/  
Event Counter  
3
TMC26 TMC25  
TCL24  
TMC24 TMC23 TMC22 TMC21 TMC20  
Watch Timer Mode  
Control Register  
Timer Clock  
Select Register 2  
Internal Bus  
243  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 10 WATCH TIMER  
Figure 10-2. Timer Clock Select Register 2 Format  
After  
Reset  
7
6
5
4
3
0
2
1
0
Address  
FF42H  
R/W  
R/W  
Symbol  
TCL2  
TCL27 TCL26 TCL25 TCL24  
TCL22 TCL21 TCL20  
00H  
Watchdog Timer Count Clock Selection  
MCS = 1  
TCL22 TCL21 TCL20  
MCS = 0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
fXX/29  
fXX/211  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/23 (625 kHz)  
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
/29 (9.8 kHz)  
/211 (2.4 kHz)  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
/29 (9.8 kHz)  
/210 (4.9 kHz)  
/212 (1.2 kHz)  
Watchdog Timer Count Clock Selection  
MCS = 1  
TCL24  
MCS = 0  
/28 (19.5 kHz)  
0
1
fXX/27  
f
X
/27 (39.1 kHz)  
f
X
fXT (32.768 kHz)  
Buzzer Output Frequency Selection  
MCS = 1  
TCL27 TCL26 TCL25  
MCS = 0  
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
Buzzer output disable  
fXX/29  
f
f
f
X
X
X
/29 (9.8 kHz)  
/210 (4.9 kHz)  
/211 (2.4 kHz)  
f
f
f
X
X
X
/210 (4.9 kHz)  
/211 (2.4 kHz)  
/212 (1.2 kHz)  
fXX/210  
fXX/211  
Setting prohibited  
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
3. fXT  
4. ×  
: Main system clock oscillation frequency  
: Subsystem clock oscillation frequency  
: Don't care  
5. MCS : Bit 0 of oscillation mode selection register (OSMS)  
6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.  
244  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 10 WATCH TIMER  
(2) Watch timer mode control register (TMC2)  
This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/  
disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation  
instruction.  
RESET input sets TMC2 to 00H.  
Figure 10-3. Watch Timer Mode Control Register Format  
After  
Reset  
7
0
6
5
4
3
2
1
0
Address  
FF4AH  
R/W  
R/W  
Symbol  
TMC2  
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20  
00H  
TMC20 Watch Operating Mode Selection  
0
1
Normal operating mode (flag set at fW/214)  
Fast feed operating mode (flag set at fW/25)  
TMC21 Prescaler Operation Control  
0
1
Clear after operation stop  
Operation enable  
TMC22 5-Bit Counter Operation Control  
0
1
Clear after operation stop  
Operation enable  
Watch Flag Set Time Selection  
fXX = 5.0 MHz Operation  
214/fW (0.4 sec)  
TMC23  
fXX = 4.19 MHz Operation  
214/fW (0.5 sec)  
fXT = 32.768 kHz Operation  
214/fW (0.5 sec)  
0
1
213/fW (0.2 sec)  
213/fW (0.25 sec)  
213/fW (0.25 sec)  
Prescaler Interval Time Selection  
TMC26 TMC25 TMC24  
fXX = 5.0 MHz Operation  
24/fW (410 µs)  
fXX = 4.19 MHz Operation  
24/fW (488 µs)  
fXT = 32.768 kHz Operation  
24/fW (488 µs)  
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
25/fW (819 µs)  
25/fW (977 µs)  
25/fW (977 µs)  
26/fW (1.64 ms)  
27/fW (3.28 ms)  
28/fW (6.55 ms)  
29/fW (13.1 ms)  
Setting prohibited  
26/fW (1.95 ms)  
27/fW (3.91 ms)  
28/fW (7.81 ms)  
29/fW (15.6 ms)  
26/fW (1.95 ms)  
27/fW (3.91 ms)  
28/fW (7.81 ms)  
29/fW (15.6 ms)  
Other than above  
Caution When the watch timer is used, the prescaler should not be cleared frequently.  
7
Remarks 1. fW  
2. fXX  
: Watch timer clock frequency (fXX/2 or fXT)  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
: Subsystem clock oscillation frequency  
3. fX  
4. fXT  
245  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 10 WATCH TIMER  
10.4 Watch Timer Operations  
10.4.1 Watch timer operation  
When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch  
timer with a 0.5-second or 0.25-second interval.  
The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/  
HALT mode) can be cleared by setting WTIF to 1.  
When bit 2 (TMC22) of the watch timer mode control register (TMC2) is set to 0, the 5-bit counter is cleared and  
the count operation stops.  
For simultaneous operation of the interval timer, zero-second start can be achieved by setting TMC22 to 0  
(maximum error: 26.2 ms when operated at fXX = 5.0 MHz).  
10.4.2 Interval timer operation  
The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset  
count value.  
The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register.  
Table 10-3. Interval Timer Interval Time  
When operated at  
fXX = 5.0 MHz  
When operated at  
fXX = 4.19 MHz  
When operated at  
fXT = 32.768 kHz  
TMC26 TMC25 TMC24  
Interval Time  
4
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
2 × 1/fW  
410 µs  
819 µs  
488 µs  
977 µs  
488 µs  
977 µs  
5
2 × 1/fW  
6
2 × 1/fW  
1.64 ms  
3.28 ms  
6.55 ms  
13.1 ms  
1.95 ms  
3.91 ms  
7.81 ms  
15.6 ms  
1.95 ms  
3.91 ms  
7.81 ms  
15.6 ms  
7
2 × 1/fW  
8
2 × 1/fW  
9
2 × 1/fW  
Other than above  
Setting prohibited  
Remark fXX : Main system clock frequency (fX or fX/2)  
fX Main system clock oscillation frequency  
:
fXT : Subsystem clock oscillation frequency  
7
fW : Watch timer clock frequency (fXX/2 or fXT)  
246  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
11.1 Watchdog Timer Functions  
The watchdog timer has the following functions.  
• Watchdog timer  
• Interval timer  
Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register  
(WDTM) (The watchdog timer and interval timer cannot be used at the same time).  
(1) Watchdog timer mode  
An inadvertent program loop (runaway) is detected. Upon detection of the runaway, a non-maskable interrupt  
request or RESET can be generated.  
Table 11-1. Watchdog Timer Runaway Detection Times  
Runaway Detection Time  
MCS = 1  
MCS = 0  
11  
11  
12  
13  
14  
15  
16  
17  
19  
12  
13  
14  
15  
16  
17  
18  
20  
2
2
2
2
2
2
2
2
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
2
2
2
2
2
2
2
2
× 1/fX (410 µs)  
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (104.9 ms)  
2
2
2
2
2
2
2
2
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (52.4 ms)  
× 1/fX (209.7 ms)  
12  
13  
14  
15  
16  
17  
19  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX : Main system clock oscillation frequency  
3. MCS : Bit 0 of oscillation mode selection register (OSMS)  
4. Figures in parentheses apply to operation with fX = 5.0 MHz.  
247  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
(2) Interval timer mode  
Interrupt requests are generated at the preset time intervals.  
Table 11-2. Interval Times  
Interval Time  
MCS = 1  
CS = 0  
11  
11  
12  
13  
14  
15  
16  
17  
19  
12  
13  
14  
15  
16  
17  
18  
20  
2
2
2
2
2
2
2
2
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
2
2
2
2
2
2
2
2
× 1/fX (410 µs)  
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (104.9 ms)  
2
2
2
2
2
2
2
2
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (52.4 ms)  
× 1/fX (209.7 ms)  
12  
13  
14  
15  
16  
17  
19  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX : Main system clock oscillation frequency  
3. MCS : Oscillation mode selection register bit 0  
4. Figures in parentheses apply to operation with fX = 5.0 MHz.  
248  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
11.2 Watchdog Timer Configuration  
The watchdog timer consists of the following hardware.  
Table 11-3. Watchdog Timer Configuration  
Item  
Configuration  
Timer clock select register 2 (TCL2)  
Control register  
Watchdog timer mode control register (WDTM)  
Figure 11-1. Watchdog Timer Block Diagram  
Internal Bus  
f
XX/23  
Prescaler  
TMMK4  
fXX fXX fXX fXX fXX fXX  
f
XX  
RUN  
24 25 26 27 28 29 211  
INTWDT  
Maskable  
Interrupt  
Request  
TMIF4  
8-Bit Counter  
Control  
Circuit  
RESET  
INTWDT  
Non-Maskable  
Interrupt  
3
Request  
TCL22 TCL21  
WDTM3  
RUN WDTM4  
TCL20  
Timer Clock Select Register 2  
Watchdog Timer Mode Register  
Internal Bus  
249  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
11.3 Watchdog Timer Control Registers  
The following two types of registers are used to control the watchdog timer.  
• Timer clock select register 2 (TCL2)  
• Watchdog timer mode register (WDTM)  
(1) Timer clock select register 2 (TCL2)  
This register sets the watchdog timer count clock.  
TCL2 is set with 8-bit memory manipulation instruction.  
RESET input sets TCL2 to 00H.  
Remark Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer  
output frequency.  
250  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
Figure 11-2. Timer Clock Select Register 2 Format  
After  
Reset  
7
6
5
4
3
0
2
1
0
Address  
FF42H  
R/W  
R/W  
Symbol  
TCL2  
TCL27 TCL26 TCL25 TCL24  
TCL22 TCL21 TCL20  
00H  
Watchdog Timer Count Clock Selection  
MCS = 1  
TCL22 TCL21 TCL20  
MCS = 0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
fXX/29  
fXX/211  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/23 (625 kHz)  
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
/29 (9.8 kHz)  
/211 (2.4 kHz)  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
/29 (9.8 kHz)  
/210 (4.9 kHz)  
/212 (1.2 kHz)  
Watchdog Timer Count Clock Selection  
MCS = 1  
TCL24  
MCS = 0  
/28 (19.5 kHz)  
0
1
fXX/27  
f
X
/27 (39.1 kHz)  
f
X
fXT (32.768 kHz)  
Buzzer Output Frequency Selection  
MCS = 1  
TCL27 TCL26 TCL25  
MCS = 0  
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
Buzzer output disable  
fXX/29  
f
f
f
X
X
X
/29 (9.8 kHz)  
/210 (4.9 kHz)  
/211 (2.4 kHz)  
f
f
f
X
X
X
/210 (4.9 kHz)  
/211 (2.4 kHz)  
/212 (1.2 kHz)  
fXX/210  
fXX/211  
Setting prohibited  
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
3. fXT  
4. ×  
: Main system clock oscillation frequency  
: Subsystem clock oscillation frequency  
: Don't care  
5. MCS : Bit 0 of oscillation mode selection register (OSMS)  
6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.  
251  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
(2) Watchdog timer mode register (WDTM)  
This register sets the watchdog timer operating mode and enables/disables counting.  
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets WDTM to 00H.  
Figure 11-3. Watchdog Timer Mode Register Format  
After  
Reset  
<7>  
6
0
5
0
4
3
2
0
1
0
0
0
Address  
FFF9H  
R/W  
R/W  
Symbol  
WDTM  
RUM  
WDTM4 WDTM3  
00H  
Watchdog Timer Operation Mode  
SelectionNote 1  
WDTM4 WDTM3  
Interval timer modeNote 2  
(Maskable interrupt request occurs upon  
generation of an overflow.)  
0
1
1
×
0
1
Watchdog timer mode 1  
(Non-maskable interrupt request occurs  
upon generation of an overflow.)  
Watchdog timer mode 2  
(Reset operation is activated upon  
generation of an overflow.)  
RUN Watchdog Timer Operation Mode SelectionNote 3  
0
1
Count stop  
Counter is cleared and counting starts.  
Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.  
2. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1.  
3. Once set to 1, RUN cannot be cleared to 0 by software.  
Thus, once counting starts, counting can only be stopped by RESET input.  
Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is  
up to 0.5 % shorter than the time set by timer clock select register 2 (TCL2).  
2. To use watchdog timer modes 1 and 2, make sure that the interrupt request flag (TMIF4)  
is 0, and then set WDTM4 to 1.  
If WDTM4 is set to 1 when TMIF4 is 1, the non-maskable interrupt request occurs,  
regardless of the contents of WDTM3.  
Remark ×: Don’t care  
252  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
11.4 Watchdog Timer Operations  
11.4.1 Watchdog timer operation  
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated  
to detect any runaway.  
The watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22)  
of the timer clock select register 2 (TCL2).  
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1  
within the set runaway detection time interval. The watchdog timer can be cleared and counting is started by setting  
RUN to 1. If RUN is not set to 1 and the runaway detection time is past, system reset or a non-maskable interrupt  
request is generated according to the WDTM bit 3 (WDTM3) value.  
By setting RUN to 1, the watchdog timer can be cleared.  
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1  
before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.  
Cautions 1. The actual runaway detection time may be shorter than the set time by a maximum of  
0.5 %.  
2. When the subsystem clock is selected for CPU clock, watchdog timer count operation is  
stopped.  
Table 11-4. Watchdog Timer Runaway Detection Times  
TCL22 TCL21 TCL20 Runaway Detection Time  
MCS = 1  
MCS = 0  
11  
11  
12  
13  
14  
15  
16  
17  
19  
12  
13  
14  
15  
16  
17  
18  
20  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
2
2
2
2
2
2
2
2
× 1/fX (410 µs)  
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (104.9 ms)  
2
2
2
2
2
2
2
2
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (52.4 ms)  
× 1/fX (209.7 ms)  
12  
13  
14  
15  
16  
17  
19  
Remarks 1. fXX  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
2. fX  
3. MCS  
: Bit 0 of oscillation mode selection register (OSMS)  
4. TCL20 to TCL22 : Bits 0 to 2 of timer clock select register 2 (TCL2)  
5. Figures in parentheses apply to operation with fX = 5.0 MHz.  
253  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 11 WATCHDOG TIMER  
11.4.2 Interval timer operation  
The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of  
the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.  
A count clock (interval time) can be selected by the bits 0 through 2 (TCL20 through TCL22) of the timer clock  
select register 2 (TCL2). By setting the bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval  
timer.  
When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag  
(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt  
requests, the INTWDT default has the highest priority.  
The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit 7 (RUN) of  
WDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.  
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval  
timer mode is not set unless RESET input is applied.  
2. The interval time just after setting with WDTM may be shorter than the set time by a maximum  
of 0.5 %.  
3. When the subsystem clock is selected for CPU clock, watchdog timer count operation is  
stopped.  
Table 11-5. Interval Timer Interval Time  
TCL22 TCL21 TCL20  
Interval Time  
MCS = 1  
MCS = 0  
11  
11  
12  
13  
14  
15  
16  
17  
19  
12  
13  
14  
15  
16  
17  
18  
20  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
× 1/fXX  
2
2
2
2
2
2
2
2
× 1/fX (410 µs)  
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (104.9 ms)  
2
2
2
2
2
2
2
2
× 1/fX (819 µs)  
× 1/fX (1.64 ms)  
× 1/fX (3.28 ms)  
× 1/fX (6.55 ms)  
× 1/fX (13.1 ms)  
× 1/fX (26.2 ms)  
× 1/fX (52.4 ms)  
× 1/fX (209.7 ms)  
12  
13  
14  
15  
16  
17  
19  
Remarks 1. fXX  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
2. fX  
3. MCS  
: Bit 0 of oscillation mode selection register (OSMS)  
4. TCL20 to TCL22 : Bits 0 to 2 of timer clock select register 2 (TCL2)  
5. Figures in parentheses apply to operation with fX = 5.0 MHz.  
254  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT  
12.1 Clock Output Control Circuit Functions  
The clock output control circuit is intended for carrier output during remote controlled transmission and clock output  
for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/  
P35 pin.  
Follow the procedure below to output clock pulses.  
(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03)  
of TCL0.  
(2) Set the P35 output latch to 0.  
(3) Set bit 5 (PM35) of port mode register 3 (PM3) to 0 (set to output mode).  
(4) Set bit 7 (CLOE) of timer clock select register 0 (TCL0) to 1.  
Caution Clock output cannot be used when setting P35 output latch to 1.  
Remark When clock output enable/disable is switched, the clock output control circuit does not output pulses  
with small widths (See the portions marked with * in Figure 12-1).  
Figure 12-1. Remote Controlled Output Application Example  
CLOE  
*
*
PCL/P35 Pin Output  
255  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT  
12.2 Clock Output Control Circuit Configuration  
The clock output control circuit consists of the following hardware.  
Table 12-1. Clock Output Control Circuit Configuration  
Item  
Configuration  
Timer clock select register 0 (TCL0)  
Port mode register 3 (PM3)  
Control register  
Figure 12-2. Clock Output Control Circuit Block Diagram  
fXX  
fXX /2  
fXX /22  
fXX /23  
fXX /24  
fXX /25  
fXX /26  
fXX /27  
fXT  
Synchronizing  
Circuit  
PCL/P35  
4
P35  
Output Latch  
CLOE TCL03 TCL02 TCL01 TCL00  
PM35  
Port Mode Register 3  
Timer Clock Select Register 0  
Internal Bus  
256  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT  
12.3 Clock Output Function Control Registers  
The following two types of registers are used to control the clock output function.  
• Timer clock select register 0 (TCL0)  
• Port mode register 3 (PM3)  
(1) Timer clock select register 0 (TCL0)  
This register sets PCL output clock.  
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets TCL0 to 00H.  
Remark Besides setting PCL output clock, TCL0 sets the 16-bit timer register count clock.  
257  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT  
Figure 12-3. Timer Clock Select Register 0 Format  
After  
Reset  
<7>  
6
5
4
3
2
1
0
Address  
FF40H  
R/W  
R/W  
Symbol  
TCL0  
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00  
00H  
PCL Output Clock Selection  
TCL03 TCL02 TCL01 TCL00  
MCS = 1  
MCS = 0  
0
0
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fXT (32.768 kHz)  
fXX  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
(5.0 MHz)  
/2 (2.5 MHz)  
/22 (1.25 MHz)  
/23 (625 kHz)  
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2 (2.5 MHz)  
/22 (1.25 MHz)  
/23 (625 kHz)  
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
fXX/2  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
Other than above  
Setting prohibited  
16-Bit Timer Register Count Clock Selection  
MCS = 1  
TCL06 TCL05 TCL04  
MCS = 0  
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TI00 (Valid edge specifiable)  
2fXX  
fXX  
Setting prohibited  
f
f
f
f
X
X
X
X
(5.0 MHz)  
/2 (2.5 MHz)  
/22 (1.25 MHz)  
/23 (625 kHz)  
f
f
f
X
X
X
(5.0 MHz)  
/2 (2.5 MHz)  
/22 (1.25 MHz)  
fXX/2  
fXX/22  
Watch Timer Output (INTTM3)  
Setting prohibited  
Other than above  
CLOE PCL Output Control  
0
1
Output disable  
Output enable  
Cautions 1. Set the TI00/P00/INTP0 pin valid edge by external interrupt mode register 0 (INTM0), and  
select the sampling clock frequency by the sampling clock selection register (SCS).  
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory  
manipulation instruction.  
3. To read the count value when TI00 has been specified as the TM0 count clock, the value  
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).  
4. When rewriting TCL0 to other data, stop the clock operation beforehand.  
258  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
: Subsystem clock oscillation frequency  
3. fXT  
4. TI00 : 16-bit timer/event counter input pin  
5. TM0 : 16-bit timer register  
6. MCS : Oscillation mode selection register (OSMS) bit 0  
7. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.  
(2) Port mode register 3 (PM3)  
This register set port 3 input/output in 1-bit units.  
When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0.  
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets PM3 to FFH.  
Figure 12-4. Port Mode Register 3 Format  
After  
Reset  
7
6
5
4
3
2
1
0
Address  
FF23H  
R/W  
R/W  
Symbol  
PM3  
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30  
FFH  
PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7)  
0
1
Output mode (output buffer ON)  
Input mode (output buffer OFF)  
259  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
260  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT  
13.1 Buzzer Output Control Circuit Functions  
The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer  
frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin.  
Follow the procedure below to output the buzzer frequency.  
(1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2.  
(2) Set the P36 output latch to 0.  
(3) Set bit 6 (PM36) of port mode register 3 (PM3) to 0 (Set to output mode).  
Caution Buzzer output cannot be used when setting P36 output latch to 1.  
13.2 Buzzer Output Control Circuit Configuration  
The buzzer output control circuit consists of the following hardware.  
Table 13-1. Buzzer Output Control Circuit Configuration  
Item  
Configuration  
Timer clock select register 2 (TCL2)  
Port mode register 3 (PM3)  
Control register  
Figure 13-1. Buzzer Output Control Circuit Block Diagram  
fXX /29  
fXX /210  
fXX /211  
BUZ/P36  
3
P36  
Output Latch  
TCL27 TCL26 TCL25  
PM36  
Port Mode Register 3  
Timer Clock Select Register 2  
Internal Bus  
261  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT  
13.3 Buzzer Output Function Control Registers  
The following two types of registers are used to control the buzzer output function.  
• Timer clock select register 2 (TCL2)  
• Port mode register 3 (PM3)  
(1) Timer clock select register 2 (TCL2)  
This register sets the buzzer output frequency.  
TCL2 is set with an 8-bit memory manipulation instruction.  
RESET input sets TCL2 to 00H.  
Remark Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the  
watchdog timer count clock.  
262  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT  
Figure 13-2. Timer Clock Select Register 2 Format  
After  
Reset  
7
6
5
4
3
0
2
1
0
Address  
FF42H  
R/W  
R/W  
Symbol  
TCL2  
TCL27 TCL26 TCL25 TCL24  
TCL22 TCL21 TCL20  
00H  
Watchdog Timer Count Clock Selection  
MCS = 1  
TCL22 TCL21 TCL20  
MCS = 0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
fXX/29  
fXX/211  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/23 (625 kHz)  
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
/29 (9.8 kHz)  
/211 (2.4 kHz)  
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/24 (313 kHz)  
/25 (156 kHz)  
/26 (78.1 kHz)  
/27 (39.1 kHz)  
/28 (19.5 kHz)  
/29 (9.8 kHz)  
/210 (4.9 kHz)  
/212 (1.2 kHz)  
Watchdog Timer Count Clock Selection  
MCS = 1  
TCL24  
MCS = 0  
/28 (19.5 kHz)  
0
1
fXX/27  
f
X
/27 (39.1 kHz)  
f
X
fXT (32.768 kHz)  
Buzzer Output Frequency Selection  
MCS = 1  
TCL27 TCL26 TCL25  
MCS = 0  
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
Buzzer output disable  
fXX/29  
f
f
f
X
X
X
/29 (9.8 kHz)  
/210 (4.9 kHz)  
/211 (2.4 kHz)  
f
f
f
X
X
X
/210 (4.9 kHz)  
/211 (2.4 kHz)  
/212 (1.2 kHz)  
fXX/210  
fXX/211  
Setting prohibited  
Caution When rewriting TCL2 to other data, stop the timer operation beforehand.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
3. fXT  
4. ×  
: Main system clock oscillation frequency  
: Subsystem clock oscillation frequency  
: don't care  
5. MCS : Bit 0 of oscillation mode selection register (OSMS)  
6. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.  
263  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT  
(2) Port mode register 3 (PM3)  
This register sets port 3 input/output in 1-bit units.  
When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0.  
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets PM3 to FFH.  
Figure 13-3. Port Mode Register 3 Format  
After  
Reset  
7
6
5
4
3
2
1
0
Address  
FF23H  
R/W  
R/W  
Symbol  
PM3  
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30  
FFH  
PM3n P3n Pin Input/Output Mode Selection (n=0 to 7)  
0
1
Output mode (output buffer ON)  
Input mode (output buffer OFF)  
264  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
14.1 A/D Converter Functions  
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an  
8-bit resolution.  
The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D  
conversion result register (ADCR).  
The following two ways are available to start A/D conversion.  
(1) Hardware start  
Conversion is started by trigger input (INTP3).  
(2) Software start  
Conversion is started by setting the A/D converter mode register (ADM).  
Select one channel of analog input from ANI0 to ANI7 and perform A/D conversion. In the case of hardware start,  
A/D conversion operation stops when an A/D conversion ends, and an interrupt request (INTAD) is generated. In  
the case of software start, the A/D conversion operation is repeated. Each time an A/D conversion operation ends,  
an interrupt request (INTAD) is generated.  
14.2 A/D Converter Configuration  
The A/D converter consists of the following hardware.  
Table 14-1. A/D Converter Configuration  
Item  
Configuration  
Analog input  
8 Channels (ANI0 to ANI7)  
A/D converter mode register (ADM)  
Control register  
Register  
A/D converter input select register (ADIS)  
External interrupt mode register 1 (INTM1)  
Successive approximation register (SAR)  
A/D conversion result register (ADCR)  
265  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
Figure 14-1. A/D Converter Block Diagram  
Internal Bus  
A/D Converter Input Select Register  
ADIS3  
ADIS2  
ADIS0  
ADIS1  
4
Series Resistor String  
ANI0/P10  
ANI1/P11  
ANI2/P12  
ANI3/P13  
ANI4/P14  
ANI5/P15  
ANI6/P16  
ANI7/P17  
AVDD  
Sample & Hold Circuit  
Note 1  
Note 2  
Voltage  
Comparator  
AVREF0  
Successive  
Approximation  
Register (SAR)  
AVSS  
3
ADM1-ADM3  
Edge  
Detector  
Control  
Circuit  
INTP3/P03  
INTAD  
INTP3  
ES40, ES41Note 3  
Trigger Enable  
3
A/D Conversion  
Result Register  
(ADCR)  
CS TRG FR1  
ADM3 ADM2 ADM1 HSC  
FR0  
A/D Converter Mode Register  
Internal Bus  
Notes 1. Selector to select the number of channels to be used for analog input.  
2. Selector to select the channel for A/D conversion.  
3. Bits 0 and 1 of external interrupt mode register 1 (INTM1)  
266  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(1) Successive approximation register (SAR)  
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from  
the series resistor string and holds the result from the most significant bit (MSB).  
When up to the least significant bit (LSB) is held (termination of A/D conversion), the SAR contents are  
transferred to the A/D conversion result register (ADCR).  
(2) A/D conversion result register (ADCR)  
This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result  
is loaded from the successive approximation register (SAR).  
ADCR is read with an 8-bit memory manipulation instruction.  
RESET input makes ADCR undefined.  
(3) Sample & hold circuit  
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and  
sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D  
conversion.  
(4) Voltage comparator  
The voltage comparator compares the analog input to the series resistor string output voltage.  
(5) Series resistor string  
The series resistor string is connected between AVREF0 and AVSS and generates a voltage to be compared  
to the analog input.  
(6) ANI0 to ANI7 pins  
These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter.  
Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used  
as input/output ports.  
Cautions 1. Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AVREF0  
or lower than AVSS is applied (even if within the absolute maximum ratings), the converted  
value of the corresponding channel becomes indeterminate and may adversely affect the  
converted values of other channels.  
2. Analog input (ANI0 to ANI7) pins are multiplexed with the input/output port (port 1). When  
performing A/D conversion with one of ANI0 to ANI7 selected, do not execute an input  
instruction to port 1 during conversion. Otherwise, the conversion resolution may be  
deteriorated. In addition, if a digital pulse is applied to a pin adjacent to the pin performing  
A/D conversion, the desired A/D conversion value may not be obtained due to coupling  
noise. Therefore, do not apply a pulse to a pin adjacent to the pin performing A/D  
conversion.  
267  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(7) AVREF0 pin  
This pin inputs the A/D converter reference voltage.  
It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF0  
and AVSS.  
The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF0  
pin to AVSS level in standby mode.  
Caution A serial resistor string of approximately 10 kis connected between the AVREF0 pin and the  
AVSS pin. Therefore, when the output impedance of the reference voltage is high, it is  
connected in parallel to the serial resistor string between the AVREF0 pin and the AVSS pin  
so that the reference voltage error increases.  
(8) AVSS pin  
This is a GND potential pin of the A/D converter. Keep it at the same potential as the VSS pin when not using  
the A/D converter.  
(9) AVDD pin  
This is an A/D converter analog power supply pin. Keep it at the same potential as the VSS pin when not using  
the A/D converter.  
Caution AVDD pin is the power supply pin of the analog circuit, and it supplies power also to the input  
circuit of ANI0/P10 to ANI7/P17. Therefore, always supply the voltage of the same level as  
VDD as shown in Figure 14-2 also in applications which switch to backup power supply.  
Figure 14-2. Handling of AVDD Pin  
AVREF0  
VDD  
AVDD  
Main  
power  
supply  
Capacitor  
for back-up  
AVSS  
VSS  
268  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
14.3 A/D Converter Control Registers  
The following three types of registers are used to control the A/D converter.  
• A/D converter mode register (ADM)  
• A/D converter input select register (ADIS)  
• External interrupt mode register 1 (INTM1)  
(1) A/D converter mode register (ADM)  
This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and  
external trigger.  
ADM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ADM to 01H.  
269  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
Figure 14-3. A/D Converter Mode Register Format  
After  
Reset  
<7> <6>  
5
4
3
2
1
0
Address  
FF80H  
R/W  
R/W  
Symbol  
ADM  
CS TRG FR1 FR0 ADM3 ADM2 ADM1 HSC  
01H  
ADM3 ADM2 ADM1 Analog Input Channel Selection  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ANI0  
ANI1  
ANI2  
ANI3  
ANI4  
ANI5  
ANI6  
ANI7  
A/D Conversion Time SelectionNote 1  
FR1 FR0 HSC  
f
X
= 5.0 MHz Operation  
fX  
= 4.19 MHz Operation  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
Setting prohibitedNote 2  
Setting prohibitedNote 2  
Setting prohibitedNote 2  
µ
)
)
)
160/fX (32.0 s)  
80/fX  
80/fX (19.1 s)  
160/fX (38.1 s)  
µ
µ
µ
0
0
1
0
1
0
0
1
1
0
1
80/fX  
40/fX  
50/fX  
(
(
(
Note 2  
Note 2  
Note 2  
µ
(
Setting prohibited  
)
40/fX  
50/fX  
(
Setting prohibited  
Setting prohibited  
µ
)
)
80/fX (19.1 s)  
µ
µ
100/fX (20.0 s)  
(
100/fX (23.8 s)  
µ
µ
1
100/fX (20.0 s)  
200/fX (40.0 s)  
100/fX (23.8 s)  
200/fX (47.7 s)  
Other than above Setting prohibited  
TRG External Trigger Selection  
0
1
No external trigger (software starts)  
Conversion started by external trigger (hardware starts)  
CS  
0
A/D Conversion Operation Control  
Operation stop  
1
Operation start  
Notes 1. Set so that the A/D conversion time is 19.1 µs or more.  
2. Setting prohibited because A/D conversion time is less than 19.1 µs.  
Cautions 1. The following sequence is recommended for power consumption reduction of A/D  
converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the  
A/D conversion operation, and then execute the HALT or STOP instruction.  
2. When restarting the stopped A/D conversion operation, start the A/D conversion  
operation after clearing the interrupt request flag (ADIF) to 0.  
Remarks 1. fX  
: Main system clock oscillation frequency  
2. MCS : Bit 0 of oscillation mode selection register (OSMS)  
270  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(2) A/D converter input select register (ADIS)  
This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels  
or ports. Pins other than those selected as analog input can be used as input/output ports.  
ADIS is set with an 8-bit memory manipulation instruction.  
RESET input sets ADIS to 00H.  
Cautions 1. Set the analog input channel in the following order.  
(1) Set the number of analog input channels with ADIS.  
(2) Using A/D converter mode register (ADM), select one channel to undergo A/D  
conversion from among the channels set for analog input with ADIS.  
2. No internal pull-up resistor can be used to the channels set for analog input with ADIS,  
irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register L (PUOL).  
Figure 14-4. A/D Converter Input Select Register Format  
After  
Reset  
7
0
6
0
5
0
4
0
3
2
1
0
Address  
FF84H  
R/W  
R/W  
Symbol  
ADIS  
ADIS3 ADIS2 ADIS1 ADIS0  
00H  
ADIS3 ADIS2 ADIS1 ADIS0 Number of Analog Input Channel Selection  
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No analog input channel (P10-P17)  
1 channel (ANI0, P11-P17)  
2 channel (ANI0, ANI1, P12-P17)  
3 channel (ANI0-ANI2, P13-P17)  
4 channel (ANI0-ANI3, P14-P17)  
5 channel (ANI0-ANI4, P15-P17)  
6 channel (ANI0-ANI5, P16, P17)  
7 channel (ANI0-ANI6, P17)  
8 channel (ANI0-ANI7)  
Other than above  
Setting prohibited  
271  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(3) External interrupt mode register 1 (INTM1)  
This register sets the valid edge for INTP3 to INTP6.  
INTM1 is set with an 8-bit memory manipulation instruction.  
RESET input sets INTM1 to 00H.  
Figure 14-5. External Interrupt Mode Register 1 Format  
After  
Reset  
7
6
5
4
3
2
1
0
Address  
FFEDH  
R/W  
R/W  
Symbol  
INTM1  
ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40  
00H  
ES41 ES40 INTP3 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES51 ES50 INTP4 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES61 ES60 INTP5 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES71 ES70 INTP6 Valid Edge Selection  
0
0
1
1
0
1
0
1
Falling edge  
Rising edge  
Setting prohibited  
Both falling and rising edges  
272  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
14.4 A/D Converter Operations  
14.4.1 Basic operations of A/D converter  
(1) Set the number of analog input channels with A/D converter input select register (ADIS).  
(2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter  
mode register (ADM).  
(3) Sample & hold circuit samples the voltage input to the selected analog input channel.  
(4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit  
holds the input analog voltage until termination of A/D conversion.  
(5) Bit 7 of the successive approximation register (SAR) is set and the tap selector sets the series resistor string  
voltage tap to (1/2) AVREF0.  
(6) The voltage difference between the series resistor string voltage tap and analog input is compared with a  
voltage comparator. If the analog input is greater than (1/2) AVREF0, the MSB of SAR remains set. If the input  
is smaller than (1/2) AVREF0, the MSB is reset.  
(7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the  
series resistor string voltage tap is selected according to the preset value of bit 7 as described below.  
• Bit 7 = 1 : (3/4) AVREF0  
• Bit 7 = 0 : (1/4) AVREF0  
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as  
follows.  
• Analog input voltage Voltage tap : Bit 6 = 1  
• Analog input voltage < Voltage tap : Bit 6 = 0  
(8) Comparison of this sort continues up to bit 0 of SAR.  
(9) Upon completion of the comparison of 8 bits, any effective digital resultant value remains in SAR and the  
resultant value is transferred to and latched in the A/D conversion result register (ADCR).  
At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.  
273  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
Figure 14-6. A/D Converter Basic Operation  
Conversion  
Time  
Sampling Time  
Sampling  
A/D Converter  
Operation  
A/D Conversion  
C0H  
or  
40H  
Conversion  
Result  
Undefined  
80H  
SAR  
Conversion  
Result  
ADCR  
INTAD  
A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software.  
If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and  
if the CS bit is set (1), conversion starts again from the beginning.  
After RESET input, the value of ADCR is undefined.  
274  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
14.4.2 Input voltage and conversion results  
The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion  
result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression.  
VIN  
AVREF0  
ADCR = INT (  
× 256 + 0.5)  
or  
AVREF0  
256  
AVREF0  
256  
(ADCR – 0.5) ×  
VIN < (ADCR + 0.5) ×  
Where, INT( ) : Function which returns integer parts of value in parentheses.  
VIN : Analog input voltage  
AVREF0 : AVREF0 pin voltage  
ADCR : Value of A/D conversion result register (ADCR)  
Figure 14-7 shows the relation between the analog input voltage and the A/D conversion result.  
Figure 14-7. Relations between Analog Input Voltage and A/D Conversion Result  
255  
254  
A/D Conversion  
Results  
(ADCR)  
253  
3
2
1
0
1
1
3
2
5
3
507 254 509 255 511  
512 256 512 256 512  
1
512 256 512 256 512 256  
Input Voltage/AVREF0  
275  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
14.4.3 A/D converter operating mode  
Select one analog input channel from ANI0 to ANI7 with A/D converter input select register (ADIS) and A/D  
converter mode register (ADM), and start A/D conversion.  
The following two ways are available to start A/D conversion.  
• Hardware start: Conversion is started by trigger input (INTP3).  
• Software start: Conversion is started by setting ADM.  
The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal  
(INTAD) is simultaneously generated.  
(1) A/D conversion by hardware start  
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 1, the A/D conversion standby  
state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied  
to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.  
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register  
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started  
and terminated, another operation is not started until a new external trigger signal is input.  
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D  
conversion operation and waits for a new external trigger signal to be input. When the external trigger input  
signal is reinput, A/D conversion is carried out from the beginning.  
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops  
immediately.  
Figure 14-8. A/D Conversion by Hardware Start  
INTP3  
ADM Rewrite  
CS=1, TRG=1  
ADM Rewrite  
CS=1, TRG=1  
Standby  
State  
Standby  
State  
Standby  
State  
A/D Conversion  
ANIn  
ANIn  
ANIn  
ANIn  
ANIm  
ANIm  
ANIm  
ANIm  
ANIm  
ADCR  
INTAD  
ANIn  
ANIn  
Remarks 1. n = 0, 1, ... , 7  
2. m = 0, 1, ... , 7  
276  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(2) A/D conversion operation in software start  
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the  
A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to  
ADM3) of ADM.  
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register  
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started  
and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation  
continues repeatedly until new data is written to ADM.  
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D  
conversion operation and starts A/D conversion on the newly written data.  
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops  
immediately.  
Figure 14-9. A/D Conversion by Software Start  
Conversion Start  
CS=1, TRG=0  
ADM Rewrite  
CS=1, TRG=0  
ADM Rewrite  
CS=0, TRG=0  
A/D Conversion  
ANIn  
ANIn  
ANIn  
ANIm  
ANIm  
Conversion suspended  
Conversion results are  
not stored  
Stop  
ADCR  
INTAD  
ANIn  
ANIn  
ANIm  
Remarks 1. n = 0, 1, ... , 7  
2. m = 0, 1, ... , 7  
277  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
14.5 A/D Converter Cautions  
(1) Power consumption in standby mode  
The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in  
HALT mode with the subsystem clock. As a current still flows in the AVREF0 pin at this time, this current must  
be cut in order to minimize the overall system power dissipation. In Figure 14-10, the power dissipation can  
be reduced by outputting a low-level signal to the output port in standby mode. However, there is no precision  
to the actual AVREF0 voltage, and therefore the conversion values themselves lack precision and can only be  
used for relative comparison.  
Figure 14-10. Example of Method of Reducing Current Dissipation in Standby Mode  
VDD  
Output Port  
µ PD78054, 78054Y  
AVREF0  
.
AVREF0 = VDD  
.
Series Resistor String  
AVSS  
(2) Input range of ANI0 to ANI7  
The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above  
AVREF0 or below AVSS is input (even if within the absolute maximum rating range), the conversion value for  
that channel will be indeterminate. The conversion values of the other channels may also be affected.  
278  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(3) Noise countermeasures  
In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF0 and ANI0 to ANI7. Since  
the effect increases in proportion to the output impedance of the analog input source, it is recommended that  
a capacitor be connected externally as shown in Figure 14-11 in order to reduce noise.  
Figure 14-11. Analog Input Pin Disposition  
If there is possibility that noise whose  
level is AVREF0 or higher or AVSS or lower may enter,  
clamp with a diode with a small VF (0.3 V or less).  
Reference  
AVREF0  
Voltage Input  
ANI0-ANI7  
VDD  
C=100-1000 pF  
VDD  
AVDD  
AVSS  
VSS  
(4) Pins ANI0/P10 to ANI7/P17  
The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins.  
When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute an input  
instruction to PORT1 while conversion is in progress, as this may reduce the conversion resolution.  
Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected  
A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins  
adjacent to the pin undergoing A/D conversion.  
(5) AVREF0 pin input impedance  
A series resistor string of approximately 10 kis connected between the AVREF0 pin and the AVSS pin.  
Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection  
to the series resistor string between the AVREF0 pin and the AVSS pin, and there will be a large reference voltage  
error.  
279  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 14 A/D CONVERTER  
(6) Interrupt request flag (ADIF)  
The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed.  
If an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change  
analog input may have been set immediately before the ADM rewrite. In this case, if ADIF is read immediately  
after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog  
input has not ended.  
When the A/D conversion is stopped and then resumed, clear the ADIF before it is resumed.  
Figure 14-12. A/D Conversion End Interrupt Request Generation Timing  
ADM Rewrite  
ADIF is set but ANIm  
(Start of ANIm Conversion)  
conversion has not ended  
ADM Rewrite  
(Start of ANIn Conversion)  
A/D Conversion  
ANIn  
ANIn  
ANIm  
ANIn  
ANIm  
ADCR  
INTAD  
ANIn  
ANIm  
ANIm  
(7) AVDD pin  
The AVDD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to  
ANI7/P17.  
Therefore, be sure to apply the same voltage as VDD to this pin even when the application circuit is designed  
so as to switch to a backup battery as shown in Figure 14-13.  
Figure 14-13. Handling of AVDD Pin  
AVREF0  
VDD  
AVDD  
Main  
power  
supply  
Capacitor  
for back-up  
AVSS  
VSS  
280  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 15 D/A CONVERTER  
15.1 D/A Converter Functions  
The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage  
output type D/A converter.  
The conversion method used is the R-2R resistor ladder method.  
Start the A/D conversion by setting the DACE0 and DACE1 of the D/A converter mode register (DAM).  
There are two types of modes for the D/A converter, as follows.  
(1) Normal mode  
Outputs an analog voltage signal immediately after the D/A conversion.  
(2) Real-time output mode  
Outputs an analog voltage signal synchronously with the output trigger after the D/A conversion.  
Since a sine wave can be generated in the mode, it is useful for an MSK modem for cordless telephone sets.  
281  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 15 D/A CONVERTER  
15.2 D/A Converter Configuration  
The D/A converter consists of the following hardware.  
Table 15-1. D/A Converter Configuration  
Item  
Register  
Control register  
Configuration  
D/A conversion value set register 0 (DACS0)  
D/A conversion value set register 1 (DACS1)  
D/A converter mode register (DAM)  
Figure 15-1. D/A Converter Block Diagram  
Internal Bus  
D/A Conversion Value  
Set Register 1  
(DACS1)  
DACS1 Write  
INTTM2  
D/A Conversion Value  
DACS0 Write  
Set Register 0  
(DACS0)  
INTTM1  
AVREF1  
2R  
2R  
ANO1/P131  
ANO0/P130  
R
R
Selector  
AVSS  
2R  
2R  
2R  
2R  
R
R
Selector  
2R  
2R  
DAM5 DAM4 DACE1 DACE0  
D/A Converter Mode Register  
Internal Bus  
282  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 15 D/A CONVERTER  
(1) D/A conversion value set register 0, 1 (DACS0, DACS1)  
DACS0 and DACS1 are registers that set the values to determine analog voltage output to the ANO0 and ANO1  
pins, respectively.  
DACS0 and DACS1 are set with 8-bit memory manipulation instructions.  
RESET input sets these registers to 00H.  
Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression.  
DACSn  
256  
ANOn output voltage = AVREF1 ×  
where,  
n = 0, 1  
Cautions 1. In the real-time output mode, when data that are set in DACS0 and DACS1 are read before  
an output trigger is generated, the previous data are read rather than the set data.  
2. In the real-time output mode, data should be set to DACS0 and DACS1 after an output  
trigger and before the next output trigger.  
283  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 15 D/A CONVERTER  
15.3 D/A Converter Control Registers  
The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation  
enable/stop.  
The DAM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets this register to 00H.  
Figure 15-2. D/A Converter Mode Register Format  
After  
Reset  
7
0
6
0
5
4
3
0
2
0
<1> <0>  
Address  
FF98H  
R/W  
R/W  
Symbol  
DAM  
DAM5 DAM4  
DACE1 DACE0  
00H  
DACE0 D/A Converter Channel 0 Control  
0
1
D/A conversion stop  
D/A conversion enable  
DACE1 D/A Converter Channel 1 Control  
0
1
D/A conversion stop  
D/A conversion enable  
DAM4 D/A Converter Channel 0 Operating Mode  
0
1
Normal mode  
Real-time output mode  
DAM5 D/A Converter Channel 1 Operating Mode  
0
1
Normal mode  
Real-time output mode  
Cautions 1. When using the D/A converter, a dual-function port pin should be set to the input mode, and  
a pull-up resistor should be disconnected.  
2. Always set bits 2, 3, 6, and 7 to 0.  
3. When D/A conversion is stopped, the output state is high-impedance.  
4. The output triggers are INTTM1 and INTTM2 for channel 0 and channel 1, respectively, in the  
real-time output mode.  
284  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 15 D/A CONVERTER  
15.4 Operations of D/A Converter  
(1) Select the channel 0 operating mode and channel 1 operating mode by DAM4 and DAM5 of D/A converter  
mode register (DAM), respectively.  
(2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to the  
D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively.  
(3) The channel 0 and channel 1 D/A conversion operations can be started by setting DACE0 and DACE1 of the  
DAM, respectively.  
(4) In the normal mode, the analog voltage signals are output to the ANO0/P130 and ANO1/P131 pins immediately  
after the D/A conversion. In the real-time output mode, the analog voltage signals are output synchronously  
with the output triggers.  
(5) In the normal mode, the analog voltage signals to be output are held until new data are set in DACS0 and  
DACS1. In the realtime output mode, new data are set in DACS0 and DACS1 and then they are held until  
the next trigger is generated.  
Caution Set DACE0 and DACE1 after setting data in DACS0 and DACS1.  
285  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 15 D/A CONVERTER  
15.5 Cautions Related to D/A Converter  
(1) Output impedance of D/A converter  
Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n =  
0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between  
the load and the ANOn pins. In addition, wiring from the ANOn pins to the buffer amplifier or the load should  
be as short as possible (because of high output impedance). If the wiring may be long, design the ground  
pattern so as to be close to those lines or use some other expedient to achieve shorter wiring.  
Figure 15-3. Use Example of Buffer Amplifier  
(a) Inverting amplifier  
C
µPD78054, 78054Y  
R
2
R1  
ANOn  
• The input impedance of the buffer amplifier is R1  
.
(b) Voltage-follower  
µPD78054, 78054Y  
R
ANOn  
R1  
C
• The input impedance of the buffer amplifier is R1  
• If R1 is not connected, the output becomes  
undefined when RESET is low.  
.
(2) Output voltage of D/A converter  
Because the output voltage of the converter changes in steps, use the D/A converter output signals in general  
by connecting a low-pass filter.  
(3) AVREF1 pin  
When only either one of the D/A converter channels is used with AVREF1< VDD, the other pins that are not used  
as analog outputs must be set as follows:  
Set PM13x bit of the port mode register 13 (PM13) to 1 (input mode) and connect the pin to VSS.  
Set PM13x bit of the port mode register 13 (PM13) to 0 (output mode) and the output latch to 0, to output  
low level from the pin.  
286  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
The µPD78054 subseries incorporates three channels of serial interfaces. Differences between channels 0, 1,  
and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface  
channel 1. Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel  
2).  
Table 16-1. Differences between Channels 0, 1, and 2  
Serial Transfer Mode  
Channel 0  
Channel 1  
Channel 2  
2
3
2
3
fXX/2, fXX/2 , fXX/2 ,  
fXX/2, fXX/2 , fXX/2 ,  
4
5
6
4
5
6
fXX/2 , fXX/2 , fXX/2 ,  
fXX/2 , fXX/2 , fXX/2 ,  
Baud rate generator  
Clock selection  
7
8
7
8
fXX/2 , fXX/2 , external fXX/2 , fXX/2 , external output  
clock, TO2 output  
clock, TO2 output  
MSB/LSB switchable  
as the start bit  
MSB/LSB switchable  
as the start bit  
MSB/LSB switchable  
as the start bit  
3-wire serial I/O  
Transfer method  
Automatic transmit/  
receive function  
Serial transfer end  
Serial transfer end  
interrupt request flag  
(CSIIF1)  
Serial transfer end  
interrupt request flag  
(SRIF)  
Transfer end flag interrupt request flag  
(CSIIF0)  
SBI (serial bus interface)  
2-wire serial I/O  
Use possible  
None  
None  
None  
UART  
Use possible  
(Asynchronous serial interface)  
287  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.1 Serial Interface Channel 0 Functions  
Serial interface channel 0 employs the following four modes.  
• Operation stop mode  
• 3-wire serial I/O mode  
• SBI (serial bus interface) mode  
• 2-wire serial I/O mode  
Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, SBI) of serial interface  
channel 0. Switch the operation mode after stopping the serial operation.  
(1) Operation stop mode  
This mode is used when serial transfer is not carried out. Power consumption can be reduced.  
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)  
This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0)  
and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data  
transfer processing time.  
The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected  
regardless of their start bit recognition.  
This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate  
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.  
(3) SBI (serial bus interface) mode (MSB-first)  
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and  
serial data bus (SB0 or SB1).  
The SBI mode conforms to the NEC serial bus format and transmits/receives transfer data discriminating it  
as three types: “address”, “command”, and “data”.  
• Address  
• Command : Data that gives instruction to the target device  
• Data : Data that is actually transmitted  
: Data that selects the target device of the serial communication  
For the actual transmission, the master device outputs “address” on the serial bus and selects the slave device  
to be the target of communication from multiple devices. Then, the serial transmission is realized by  
transmitting/receiving “command” and “data” between the master device and the slave device. The receive  
side automatically discriminates the received data as “address”, “command”, or “data”, by hardware.  
This function enables the input/output ports to be used effectively and simplifies the application program to  
control serial interface channel 0.  
In this mode, the wake-up function for handshake and the output function of acknowledge and busy signals  
can also be used.  
288  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(4) 2-wire serial I/O mode (MSB-first)  
This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or  
SB1).  
This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level  
and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or  
more devices can be used as input/output ports.  
Figure 16-1. Serial Bus Interface (SBI) System Configuration Example  
VDD  
Master CPU  
Slave CPU1  
SCK0  
SB0  
SCK0  
SB0  
Slave CPU2  
SCK0  
SB0  
Slave CPUn  
SCK0  
SB0  
289  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.2 Serial Interface Channel 0 Configuration  
Serial interface channel 0 consists of the following hardware.  
Table 16-2. Serial Interface Channel 0 Configuration  
Item  
Register  
Configuration  
Serial I/O shift register 0 (SIO0)  
Slave address register (SVA)  
Timer clock select register 3 (TCL3)  
Serial operating mode register 0 (CSIM0)  
Serial bus interface control register (SBIC)  
Interrupt timing specify register (SINT)  
Control register  
Note  
Port mode register 2 (PM2)  
Note Refer to Figure 6-5. Block Diagram of P20, P21, P23 to P26 and Figure 6-6. Block Diagram of P22, P27.  
290  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-2. Serial Interface Channel 0 Block Diagram  
Internal Bus  
Serial Bus Interface  
Control Register  
Serial Operating Mode Register 0  
Slave Address  
Register (SVA)  
CSIM CSIM CSIM CSIM CSIM  
CSIE0 COI WUP  
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
04  
03  
02  
01  
00  
SVAM  
Match  
Control  
Circuit  
CLRSET  
SI0/SB0/  
P25  
Serial I/O Shift  
Register 0 (SIO0)  
D
Q
Selector  
P25  
PM25  
Output Latch  
Output  
Control  
Busy/  
Acknowledge  
Output Circuit  
Selector  
SO0/SB1/  
P26  
PM26  
Bus Release/  
Command/  
Acknowledge  
Detector  
ACKD  
CMDD  
RELD  
WUP  
Output  
Control  
Interrupt  
Request  
Signal  
P26 Output Latch  
CLD  
INTCSI0  
fxx/2-fxx/28  
Serial Clock  
Counter  
SCK0/  
P27  
Generator  
TO2  
PM27  
Output  
Control  
Serial Clock  
Control Circuit  
Selector  
Selector  
CSIM00  
CSIM01  
CSIM00  
4
CSIM01  
P27  
Output Latch  
CLD  
SIC SVAM  
TCL33 TCL32 TCL31 TCL30  
Interrupt Timing  
Specify Register  
Timer Clock  
Select  
Register 3  
Internal Bus  
Remark Output Control performs selection between CMOS output and N-ch open-drain output.  
291  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(1) Serial I/O shift register 0 (SIO0)  
This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception  
(shift operation) in synchronization with the serial clock.  
SIO0 is set with an 8-bit memory manipulation instruction.  
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.  
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In  
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.  
Note that, if a bus is driven in the SBI mode or 2-wire serial I/O mode, the bus pin must serve for both input  
and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address  
reception is carried out by setting bit 5 (WUP) of CSIM0 to 1).  
In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial  
bus interface control register (SBIC) is not cleared to 0.  
RESET input makes SIO0 undefined.  
(2) Slave address register (SVA)  
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.  
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O mode.  
The master device outputs a slave address for selection of a particular slave device to the connected slave  
device. These two data (the slave address output from the master device and the SVA value) are compared  
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of  
serial operating mode register 0 (CSIM0) becomes 1.  
The address can also be compared on the data of LSB-masked high-order 7 bits by setting bit 4 (SVAM) of  
the interrupt timing specify register (SINT) to (1).  
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)  
is cleared to 0. In the SBI mode, the wake-up function can be used by setting the bit 5 (WUP) of CSIM0. In  
this case, the interrupt request signal (INTCSI0) is generated only when the slave address output by the master  
coincides with the value of SVA, and it can be learned by this interrupt request that the master requests for  
communication. If the bit 5 (SIC) of the interrupt timing specify register (SINT) is set to 1, the wake-up function  
cannot be used even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected).  
To use the wake-up function, clear SIC to 0.  
Further, when SVA transmits data as master or slave device in the SBI or 2-wire serial I/O mode, errors can  
be detected if any using SVA.  
RESET input makes SVA undefined.  
292  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(3) SO0 latch  
This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled also by software. In  
the SBI mode, this latch is set upon termination of the 8th serial clock.  
(4) Serial clock counter  
This counter counts the serial clocks to be output and input during transmission/reception and to check whether  
8-bit data has been transmitted/received.  
(5) Serial clock control circuit  
This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock  
is used, the circuit also controls clock output to the SCK0/P27 pin.  
(6) Interrupt request signal generator  
This circuit controls interrupt request signal generation. It generates the interrupt request signal in the following  
cases.  
• In the 3-wire serial I/O mode and 2-wire serial I/O mode  
This circuit generates an interrupt request signal every eight serial clocks.  
• In the SBI mode  
When WUP is 0 ........... Generates an interrupt request signal every eight serial clocks.  
When WUP is 1 ........... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0)  
value matches the slave address register (SVA) value after address reception.  
Remark WUP is wake-up function specify bit. It is bit 5 of serial operating mode register 0 (CSIM0). To  
use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify register  
(SINT) to 0.  
(7) Busy/acknowledge output circuit and bus release/command/acknowledge detector  
These two circuits output and detect various control signals in the SBI mode.  
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.  
293  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.3 Serial Interface Channel 0 Control Registers  
The following four types of registers are used to control serial interface channel 0.  
• Timer clock select register 3 (TCL3)  
• Serial operating mode register 0 (CSIM0)  
• Serial bus interface control register (SBIC)  
• Interrupt timing specify register (SINT)  
(1) Timer clock select register 3 (TCL3)  
This register sets the serial clock of serial interface channel 0.  
TCL3 is set with an 8-bit memory manipulation instruction.  
RESET input sets TCL3 to 88H.  
294  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-3. Timer Clock Select Register 3 Format  
Symbol  
7
6
5
4
3
2
1
0
Address After Reset R/W  
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H  
88H  
R/W  
Serial Interface Channel 0 Serial Clock Selection  
MCS = 1  
TCL33 TCL32 TCL31 TCL30  
MCS = 0  
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
fXX/2  
Setting prohibited  
f
f
f
f
f
f
f
f
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
X/29 (9.8 kHz)  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
f
f
f
f
f
f
f
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
Other than above  
Setting prohibited  
Serial Interface Channel 1 Serial Clock Selection  
MCS = 1  
TCL37 TCL36 TCL35 TCL34  
MCS = 0  
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
fXX/2  
Setting prohibited  
f
f
f
f
f
f
f
f
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
X/29 (9.8 kHz)  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
f
f
f
f
f
f
f
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
Other than above  
Setting prohibited  
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
3. MCS : Bit 0 of oscillation mode selection register (OSMS)  
4. Figures in parentheses apply to operation with fX = 5.0 MHz.  
295  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(2) Serial operating mode register 0 (CSIM0)  
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up  
function and displays the address comparator match signal.  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, SBI) of serial interface  
channel 0. Switch the operation mode after stopping the serial operation.  
Figure 16-4. Serial Operating Mode Register 0 Format (1/2)  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
R/WNote 1  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0 pin from off-chip  
8-bit timer register 2 (TM2) output  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SIO/SB0/P25 SO0/SB1/P26  
SCK0/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
02  
Pin Function  
Pin Function  
Pin Function  
Note 2 Note 2  
SI0Note 2  
(Input)  
SO0  
SCK0 (CMOS  
0
1
MSB  
LSB  
3-wire serial  
l/O mode  
0
×
1
×
0
0
0
0
0
0
1
1
(CMOS output) input/output)  
Note 3 Note 3  
SB1 (N-ch  
open-drain  
input/output)  
SCK0 (CMOS  
input/output)  
P25 (CMOS  
input/output)  
0
1
0
1
×
×
1
0
SBI mode  
MSB  
Note 3 Note 3  
SB0 (N-ch  
open-drain  
input/output)  
P26 (CMOS  
input/output)  
0
0
×
×
0
0
0
1
1
1
Note 3 Note 3  
SB1 (N-ch  
open-drain  
input/output)  
P25 (CMOS  
input/output)  
×
×
0
0
SCK0 (N-ch  
open-drain  
input/output)  
2-wire serial  
l/O mode  
1
1
MSB  
Note 3 Note 3  
SB0 (N-ch  
open-drain  
input/output)  
P26 (CMOS  
input/output)  
0
0
×
×
(Continued)  
Notes 1. Bit 6 (COI) is a read-only bit.  
2. Can be used as P25 (CMOS input/output) when used only for transmission.  
3. Can be used freely as port function.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
296  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-4. Serial Operating Mode Register 0 Format (2/2)  
R/W WUP Wake-up Function ControlNote 1  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)  
matches the slave address register (SVA) data in SBI mode  
R
COI  
0
Slave Address Comparison Result FlagNote 2  
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data  
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data  
1
R/W CSIE0 Serial Interface Channel 0 Operation ControlNote 3  
0
1
Operation stopped  
Operation enable  
Notes 1. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify register  
(SINT) to 0.  
2. When CSIE0 = 0, COI becomes 0.  
3. In the SBI mode, clear WUP to 0 before stopping(CSIE0)the operation of serial interface channel  
0, otherwise, P25 is fixed to high level and may not be able to be used as a normal port.  
297  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(3) Serial bus interface control register (SBIC)  
This register sets serial bus interface operation and displays statuses.  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Figure 16-5. Serial Bus Interface Control Register Format (1/2)  
Symbol  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
R/WNote  
FF61H  
00H  
R/W  
R/W  
R
Used for bus release signal output.  
When RELT = 1, SO0 Iatch is set to 1. After SO0 latch setting, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
RELT  
Used for command signal output.  
When CMDT = 1, SO0 Iatch is cleared to (0). After SO0 latch clearance, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
RELD Bus Release Detection  
Clear Conditions (RELD = 0)  
Set Conditions (RELD =1)  
• When transfer start instruction is executed  
• If SIO0 and SVA values do not match in  
address reception  
• When bus release signal (REL) is detected  
• When CSIE0 = 0  
• When RESET input is applied  
R
CMDD Command Detection  
Clear Conditions (CMDD = 0)  
Set Conditions (CMDD = 1)  
• When transfer start instruction is executed  
• When bus release signal (REL) is detected  
• When CSIE0 = 0  
• When command signal (CMD) is detected  
• When RESET input is applied  
R/W  
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution  
of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0.  
Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.  
ACKT  
Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.  
Remarks 1. Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are 0 when read after data setting.  
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
298  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-5. Serial Bus Interface Control Register Format (2/2)  
R/W  
ACKE Acknowledge Signal Automatic Output Control  
0
Acknowledge signal automatic output disable (output with ACKT enable)  
Acknowledge signal is output in synchronization with the 9th clock  
Before completion of  
transfer  
falling edge of SCK0 (automatically output when ACKE = 1).  
Acknowledge signal is output in synchronization with the falling edge of  
1
After completion of  
transfer  
SCK0 just after execution of the instruction to be set to 1  
(automatically output when ACKE = 1).  
However, not automatically cleared to 0 after acknowledge signal output.  
R
ACKD Acknowledge Detection  
Clear Conditions (ACKD = 0)  
Set Conditions (ACKD = 1)  
• Falling edge of the SCK0 immediately after the busy  
mode is released while executing the transfer  
start instruction  
• When acknowledge signal (ACK) is detected at the  
rising edge of SCK0 clock after completion of  
transfer  
• When CSIE0 = 0  
• When RESET input is applied  
Note  
R/W  
BSYE Synchronizing Busy Signal Output Control  
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after  
execution of the instruction to be cleared to 0.  
0
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.  
Note The busy mode can be canceled by start of serial interface transfer. However, the BSYE flag is  
not cleared to 0.  
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
299  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(4) Interrupt timing specify register (SINT)  
This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level  
status.  
SINT is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SINT to 00H.  
Figure 16-6. Interrupt Timing Specify Register Format  
Symbol  
SINT  
7
0
<6>  
<5>  
<4>  
3
0
2
0
1
0
0
0
Address After Reset R/W  
R/WNote 1  
CLD SIC SVAM  
FF63H  
00H  
R/W  
SVAM SVA Bit to be Used as Slave Address  
0
1
Bits 0 to 7  
Bits 1 to 7  
R/W  
SIC  
0
INTCSI0 Interrupt Cause SelectionNote 2  
CSIIF0 is set upon termination of serial interface  
channel 0 transfer  
CSIIF0 is set upon bus release detection or  
termination of serial interface channel 0 transfer  
1
R
CLD SCK0/P27 Pin LevelNote 3  
0
1
Low level  
High level  
Notes 1. Bit 6 (CLD) is a read-only bit.  
2. When using wake-up function in the SBI mode, set SIC to 0.  
3. When CSIE0 = 0, CLD becomes 0.  
Caution Be sure to set bits 0 to 3 to 0.  
Remark SVA  
: Slave address register  
CSIIF0 : Interrupt request flag corresponding to INTCSI0  
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
300  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.4 Serial Interface Channel 0 Operations  
The following four operating modes are available to the serial interface channel 0.  
• Operation stop mode  
• 3-wire serial I/O mode  
• SBI mode  
• 2-wire serial I/O mode  
16.4.1 Operation stop mode  
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial  
I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register.  
In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1 and P27/SCK0 pins can be used as ordinary input/  
output ports.  
(1) Register setting  
The operation stop mode is set with the serial operating mode register 0 (CSIM0).  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
FF60H 00H R/W  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
301  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.4.2 3-wire serial I/O mode operation  
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate  
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.  
Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).  
(1) Register setting  
The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface  
control register (SBIC).  
(a) Serial operating mode register 0 (CSIM0)  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
302  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
R/WNote 1  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0 pin from off-chip  
8-bit timer register 2 (TM2) output  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SIO/SB0/P25 SO0/SB1/P26  
SCK0/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
02  
Pin Function  
Pin Function  
Pin Function  
Note 2  
Note 2  
0
1
MSB  
LSB  
3-wire serial  
l/O mode  
SI0Note 2  
(Input)  
SO0  
SCK0 (CMOS  
0
×
1
×
0
0
0
1
(CMOS output) input/output)  
1
1
0
1
SBI mode (See section 16.4.3, “SBI mode operation”.)  
2-wire serial I/O mode (See section 16.4.4, “2-wire serial I/O mode operation”.)  
R/W WUP Wake-up Function ControlNote 3  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after bus release  
(when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode  
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
Notes 1. Bit 6 (COI) is a read-only bit.  
2. Can be used as P25 (CMOS input/output) when used only for transmission.  
3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
303  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(b) Serial bus interface control register (SBIC)  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Symbol  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
FF61H 00H R/W  
R/W  
R/W  
When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
RELT  
When CMDT = 1, SO0 Iatch is cleared to 0. After SO0 latch clearance, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
304  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(2) Communication operation  
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/  
reception is carried out in synchronization with the serial clock.  
Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).  
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the  
SI0 pin is latched in SIO0 at the rising edge of SCK0.  
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)  
is set.  
Figure 16-7. 3-Wire Serial I/O Mode Timings  
SCK0  
SI0  
1
2
3
4
5
6
7
8
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SO0  
DO7  
DO6  
DO5  
DO4  
DO3  
DO2  
DO1  
DO0  
CSIIF0  
End of Transfer  
Transfer Start at the Falling Edge of SCK0  
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status  
can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC).  
However, do not carry out this manipulation during serial transfer.  
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27  
output latch (refer to 16.4.5 SCK0/P27 pin output manipulation).  
(3) Other signals  
Figure 16-8 shows RELT and CMDT operations.  
Figure 16-8. RELT and CMDT Operations  
SO0 latch  
RELT  
CMDT  
305  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(4) MSB/LSB switching as the start bit  
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.  
Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the  
figure, MSB/LSB can be read/written in reverse form.  
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register  
0 (CSIM0).  
Figure 16-9. Circuit of Switching in Transfer Bit Order  
7
6
Internal Bus  
1
0
LSB-first  
MSB-first  
Read/Write Gate  
Read/Write Gate  
SO0 Latch  
SI0  
Serial I/O Shift Register 0 (SIO0)  
D
Q
SO0  
SCK0  
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains  
unchanged.  
Thus, switching between MSB-first and LSB-first must be performed before writing data to SIO0.  
(5) Transfer start  
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two  
conditions are satisfied.  
• Serial interface channel 0 operation control bit (CSIE0) = 1.  
• Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer.  
Caution If CSIE0 is set to “1” after data write to SIO0, transfer does not start.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)  
is set.  
306  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.4.3 SBI mode operation  
SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format.  
SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration  
function. This function enables devices to communicate using only two lines. Thus, when making up a serial bus  
with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on  
the board can be decreased.  
The master device outputs three kinds of data to slave devices on the serial data bus: “addresses” to select a device  
to be communicated with, “commands” to instruct the selected device, and “data” which is actually required.  
The slave device can identify the received data into “address”, “command”, or “data”, by hardware. This function  
simplifies the application program to control serial interface channel 0.  
The SBI function is incorporated into various devices including 75X/XL Series and 78K Series.  
Figure 16-10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI  
and peripheral ICs are used.  
In SBI, the SB0 (SB1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves  
in the same way as the wired-OR configuration. In addition, a pull-up resistor must be connected to the serial data  
bus line.  
When the SBI mode is used, refer to (11) SBI mode precautions (d) described later.  
Figure 16-10. Example of Serial Bus Configuration with SBI  
VDD  
Serial Clock  
SCK0  
SCK0  
Slave CPU  
Address 1  
Master CPU  
Serial Data Bus  
SB0 (SB1)  
SB0 (SB1)  
SCK0  
Slave CPU  
Address 2  
SB0 (SB1)  
SCK0  
Slave IC  
SB0 (SB1)  
Address N  
Caution When exchanging the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock  
line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out  
asynchronously between the master and slave CPUs.  
307  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(1) SBI functions  
In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many  
ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the  
busy state, because only the data transfer function is available. If these operations are to be controlled by  
software, the software must be heavily loaded.  
In SBI, a serial bus can be configured with two signal lines of serial clock SCK0 and serial data bus SB0 (SB1).  
Thus, use of SBI leads to reduction in the number of microcontroller ports and that of wirings and routings  
on the board.  
The SBI functions are described below.  
(a) Address/command/data identify function  
Serial data is distinguished into addresses, commands, and data.  
(b) Chip select function by address transmission  
The master executes slave chip selection by address transmission.  
(c) Wake-up function  
The slave can easily discriminate address reception (chip select) with the wake-up function (which can  
be set/reset by software).  
When the wake-up function is set, the interrupt request signal (INTCSI0) is generated upon reception of  
a match address.  
Thus, when communication is executed with two or more devices, the CPU except the selected slave  
devices can operate regardless of underway serial communications.  
(d) Acknowledge signal (ACK) control function  
The acknowledge signal to check serial data reception is controlled.  
(e) Busy signal (BUSY) control function  
The busy signal to report the slave busy state is controlled.  
308  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(2) SBI definition  
The SBI serial data format and the signals to be used are defined as follows.  
Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”.  
Figure 16-11 shows the address, command, and data transfer timings.  
Figure 16-11. SBI Transfer Timings  
Address Transfer  
SCK0  
8
9
SB0 (SB1)  
A7  
A0  
ACK  
BUSY  
Bus Release  
Signal  
Address  
Command Transfer  
Command Signal  
SCK0  
9
SB0 (SB1)  
C7  
C0 ACK  
BUSY  
READY  
Command  
Data Transfer  
SCK0  
8
9
SB0 (SB1)  
D7  
D0 ACK  
BUSY  
READY  
Data  
Remark The dotted line indicates READY status.  
The bus release signal and the command signal are output by the master device. BUSY is output by the slave  
signal. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs).  
Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.  
309  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(a) Bus release signal (REL)  
The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the  
high level when the SCK0 line is at the high level (without serial clock output).  
This signal is output by the master device.  
Figure 16-12. Bus Release Signal  
"H"  
SCK0  
SB0 (SB1)  
Caution A transition of the SB0 (SB1) pin from low to high while the SCK0 line is high is  
interpreted as a bus release signal. Therefore, a shift in the change timing of the bus  
due to the influence of the board capacitance, etc., may be incorrectly identified as a  
bus release signal, regardless of whether data is being transmitted. For this reason,  
special care must be taken regarding wiring.  
The bus release signal indicates that the master device is going to transmit an address to the slave device.  
The slave device incorporates hardware to detect the bus release signal.  
(b) Command signal (CMD)  
The command signal is a signal with the SB0 (SB1) line which has changed from the high level to the  
low level when the SCK0 line is at the high level (without serial clock output). This signal is output by  
the master device.  
Figure 16-13. Command Signal  
"H"  
SCK0  
SB0 (SB1)  
A command signal indicates that the master is to transmit a command to a slave (however, the command  
signal following a bus release signal indicates that the master is to transmit an address).  
The slave device incorporates hardware to detect the command signal.  
Caution A transition of the SB0 (SB1) pin from low to high while the SCK0 line is high is  
interpreted as a command signal. Therefore, a shift in the change timing of the bus due  
to the influence of the board capacitance, etc., may be incorrectly identified as a  
command signal, regardless of whether data is being transmitted. For this reason,  
special care must be taken regarding wiring.  
310  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(c) Address  
An address is 8-bit data which the master device outputs to the slave device connected to the bus line  
in order to select a particular slave device.  
Figure 16-14. Addresses  
1
2
3
4
5
6
7
8
SCK0  
A7 A6 A5 A4 A3 A2 A1 A0  
SB0 (SB1)  
Address  
Bus Release  
Signal  
Command Signal  
8-bit data following bus release and command signals is defined as an “address”. In the slave device,  
this condition is detected by hardware and whether or not 8-bit data matches the own specification number  
(slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device  
has been selected. After that, communication with the master device continues until a release instruction  
is received from the master device.  
Figure 16-15. Slave Selection with Address  
Master  
Slave 1  
Slave 2  
Slave 3  
Slave 4  
Not selected  
Selected  
Slave 2  
address transmission  
Not selected  
Not selected  
311  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(d) Command and data  
The master device transmits commands to, and transmits/receives data to/from the slave device selected  
by address transmission.  
Figure 16-16. Commands  
SCK0  
1
2
3
4
5
6
7
8
SB0 (SB1)  
C7 C6 C5 C4 C3 C2 C1 C0  
Command  
Command Signal  
Figure 16-17. Data  
SCK0  
1
2
3
4
5
6
7
8
SB0 (SB1)  
D7 D6 D5 D4 D3 D2 D1 D0  
Data  
8-bit data following a command signal is defined as “command” data. 8-bit data without command signal  
is defined as “data”. Command and data operation procedures are allowed to determine by user according  
to communications specifications.  
312  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(e) Acknowledge signal (ACK)  
The acknowledge signal is used to check serial data reception between transmitter and receiver.  
Figure 16-18. Acknowledge Signal  
[When output in synchronization with 11th clock SCK0]  
SCK0  
8
9
10  
11  
ACK  
SB0 (SB1)  
[When output in synchronization with 9th clock SCK0]  
SCK0  
8
9
ACK  
SB0 (SB1)  
Remark The dotted line indicates READY status.  
The acknowledge signal is one-shot pulse to be generated at the falling edge of SCK0 after 8-bit data  
transfer. It can be positioned anywhere and can be synchronized with any clock SCK0.  
After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge  
signal. If the acknowledge signal is not returned for the preset period of time after data transmission,  
it can be judged that data reception has not been carried out correctly.  
313  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(f) Busy signal (BUSY) and ready signal (READY)  
The BUSY signal is intended to report to the master device that the slave device is preparing for data  
transmission/reception.  
The READY signal is intended to report to the master device that the slave device is ready for data  
transmission/reception.  
Figure 16-19. BUSY and READY Signals  
SCK0  
8
9
ACK  
BUSY  
READY  
SB0 (SB1)  
In SBI, the slave device notifies the master device of the busy state by setting SB0 (SB1) line to the low  
level.  
The BUSY signal output follows the acknowledge signal output from the master or slave device. It is set/  
reset at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically  
terminates the output of SCK0 serial clock.  
When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer.  
Caution SBI outputs the BUSY signal after BUSY has been cleared until the next falling edge of  
the serial clock. If WUP is set to 1 by mistake during this time, BUSY will not be cleared.  
Therefore, when setting WUP to 1, do so after clearing BUSY and then making sure that  
the SB0 (SB1) pin has gone high.  
314  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(3) Register setting  
The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register  
(SBIC), and the interrupt timing specify register (SINT).  
(a) Serial operating mode register 0 (CSIM0)  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/WNote 1  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0 pin from off-chip  
8-bit timer register 2 (TM2) output  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SI0/SB0/P25  
Pin Function  
SO0/SB1/P26  
Pin Function  
SCK0/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
02  
Pin Function  
0
×
3-wire serial I/O mode (16.4.2, “3-wire serial I/O mode operation.”)  
Note 2 Note 2  
SB1 (N-ch  
open-drain  
input/output)  
P25 (CMOS  
input/output)  
0
1
×
×
0
0
0
0
1
1
SCK0 (CMOS  
input/output)  
1
1
0
SBI mode  
MSB  
Note 2 Note 2  
SB0 (N-ch  
open-drain  
input/output)  
P26 (CMOS  
input/output)  
0
0
×
×
1
2-wire serial I/O mode (see section 16.4.4, “2-wire serial I/O mode operation.”)  
R/W WUP Wake-up Function ControlNote 3  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after bus release  
(when CMDD=RELD=1) matches the slave address register (SVA) data in SBI mode  
R
COI  
0
Slave Address Comparison Result FlagNote 4  
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data  
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data  
1
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
Notes 1. Bit 6 (COI) is a read-only bit.  
2. Can be used as a port.  
3. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify  
register (SINT) to 0.  
4. When CSIE0=0, COI becomes 0.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
315  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(b) Serial bus interface control register (SBIC)  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
The shaded area is used in the SBI mode.  
Symbol  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
R/WNote  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
FF61H  
00H  
R/W  
Used for bus release signal output.  
When RELT = 1, SO0 Iatch is set to (1). After SO0 latch setting, automatically cleared to (0).  
Also cleared to 0 when CSIE0 = 0.  
RELT  
R/W  
R
Used for command signal output.  
When CMDT = 1, SO0 Iatch is cleared to (0). After SO0 latch clearance, automatically cleared to (0).  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
RELD Bus Release Detection  
Clear Conditions (RELD = 0)  
Set Conditions (RELD = 1)  
• When transfer start instruction is executed  
• If SIO0 and SVA values do not match in address  
reception (only when WUP = 1)  
• When bus release signal (REL) is detected  
• When CSIE0 = 0  
• When RESET input is applied  
R
CMDD Command Detection  
Clear Conditions (CMDD = 0)  
Set Conditions (CMDD = 1)  
• When transfer start instruction is executed  
• When bus release signal (REL) is detected  
• When CSIE0 = 0  
• When command signal (CMD) is detected  
• When RESET input is applied  
R/W  
R/W  
Acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution  
of the instruction to be set to (1) and, after acknowledge signal output, automatically cleared to (0).  
Used as ACKE=0. Also cleared to (0) upon start of serial interface transfer or when CSIE0 = 0.  
ACKT  
ACKE Acknowledge Signal Automatic Output Control  
0
Acknowledge signal automatic output disable (output with ACKT enable)  
Acknowledge signal is output in synchronization with the 9th clock falling edge of  
Before completion of  
transfer  
SCK0 (automatically output when ACKE = 1).  
1
Acknowledge signal is output in synchronization with falling edge clock  
After completion of  
transfer  
of SCK0 just after execution of the instruction to be set to 1  
(automatically output when ACKE = 1).  
However, not automatically cleared to 0 after acknowledge signal output.  
(Continued)  
Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.  
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.  
2. CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
316  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
R
ACKD Acknowledge Detection  
Clear Conditions (ACKD = 0)  
Set Conditions (ACKD = 1)  
• SCK0 fall immediately after the busy mode is  
released during the transfer start instruction execution.  
• When CSIE0 = 0  
• When acknowledge signal (ACK) is detected at the  
rising edge of SCK0 clock after completion of  
transfer  
• When RESET input is applied  
Note  
R/W  
BSYE Synchronizing Busy Signal Output Control  
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after  
execution of the instruction to be cleared to (0) (sets READY status).  
0
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.  
Note Busy mode can be cleared by start of serial interface transfer. However, BSYE flag is not cleared  
to 0.  
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
317  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(c) Interrupt timing specify register (SINT)  
SINT is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SINT to 00H.  
Symbol  
SINT  
7
0
<6>  
<5>  
<4>  
3
0
2
0
1
0
0
0
Address After Reset R/W  
R/WNote 1  
CLD SIC SVAM  
FF63H  
00H  
R/W  
SVAM SVA Bit to be Used as Slave Address  
0
1
Bits 0 to 7  
Bits 1 to 7  
R/W  
SIC  
0
INTCSI0 Interrupt Factor SelectionNote 2  
CSIIF0 is set upon termination of serial interface  
channel 0 transfer  
CSIIF0 is set upon bus release detection or  
termination of serial interface channel 0 transfer  
1
R
CLD SCK0/P27 Pin LevelNote 3  
0
1
Low level  
High level  
Notes 1. Bit 6 (CLD) is a read-only bit.  
2. When using wake-up function in the SBI mode, set SIC to 0.  
3. When CSIE0 = 0, CLD becomes 0.  
Caution Be sure to set bits 0 to 3 to 0.  
Remark SVA  
: Slave address register  
CSIIF0 : Interrupt request flag corresponding to INTCSI0  
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
318  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(4) Various signals  
Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in  
SBI.  
Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master)  
Slave address write to SIO0  
(Transfer Start Instruction)  
SIO0  
SCK0  
SB0 (SB1)  
RELT  
CMDT  
RELD  
CMDD  
Figure 16-21. RELT and CMDD Operations (Slave)  
Write FFH to SIO0  
(Transfer start instruction)  
Transfer start instruction  
SIO0  
SCK0  
A7  
A6  
A1  
A0  
1
2
7
8
9
READY  
A7  
A6  
A1  
A0  
ACK  
SB0 (SB1)  
Slave address  
When addresses match  
RELD  
When addresses do not match  
CMDD  
319  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-22. ACKT Operation  
6
7
8
9
SCK0  
SB0 (SB1)  
ACKT  
ACK signal is output for  
a period of one clock  
just after setting  
D2  
D1  
D0  
ACK  
When set during  
this period  
Caution Do not set ACKT before termination of transfer.  
320  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-23. ACKE Operations  
(a) When ACKE = 1 upon completion of transfer  
1
2
7
8
9
SCK0  
ACK signal is output  
at 9th clock  
D7  
D6  
D2  
D1  
D0  
ACK  
SB0 (SB1)  
ACKE  
When ACKE = 1 at this point  
(b) When set after completion of transfer  
6
7
8
9
SCK0  
SB0 (SB1)  
ACKE  
D2  
D1  
D0  
ACK  
ACK signal is output for  
a period of one clock  
just after setting  
If set during this period and ACKE = 1  
at the falling edge of the next SCK0  
(c) When ACKE = 0 upon completion of transfer  
1
2
7
8
9
SCK0  
ACK signal is not output  
D7  
D6  
D2  
D1  
D0  
SB0 (SB1)  
ACKE  
When ACKE = 0 at this point  
(d) When “ACKE = 1” period is short  
SCK0  
ACK signal is not output  
SB0 (SB1)  
D2  
D1  
D0  
ACKE  
If set and cleared during this period  
and ACKE = 0 at the falling edge of SCK0  
321  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
Figure 16-24. ACKD Operations  
(a) When ACK signal is output at 9th clock of SCK0  
Transfer Start  
Instruction  
SIO0  
SCK0  
Transfer Start  
6
7
8
9
D2  
D1  
D0  
ACK  
SB0 (SB1)  
ACKD  
(b) When ACK signal is output after 9th clock of SCK0  
Transfer Start  
Instruction  
SIO0  
SCK0  
Transfer Start  
6
7
8
9
D2  
D1  
D0  
ACK  
SB0 (SB1)  
ACKD  
(c) Clear timing when transfer start is instructed in BUSY  
Transfer Start  
Instruction  
SIO0  
SCK0  
6
7
8
9
D2  
D1  
D0  
ACK  
BUSY  
D7  
D6  
SB0 (SB1)  
ACKD  
Figure 16-25. BSYE Operation  
SCK0  
SB0 (SB1)  
BSYE  
6
7
8
9
ACK  
BUSY  
D2  
D1  
D0  
If reset during this period and  
BSYE = 0 at the falling edge of SCK0  
When BSYE = 1 at this point  
322  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Table 16-3. Various Signals in SBI Mode (1/2)  
Output  
Output  
Device  
Signal Name  
Definition  
Timing Chart  
Effects on Flag  
Meaning of Signal  
Condition  
CMD signal is output  
to indicate that  
transmit data is an  
address.  
SCK0  
"H"  
Bus release  
signal  
SB0 (SB1) rising edge  
when SCK0 = 1  
• RELD set  
Master  
• RELT set  
• CMDD clear  
SB0 (SB1)  
(REL)  
i) Transmit data is an  
address after REL  
signal output.  
Command  
signal  
SCK0  
"H"  
SB0 (SB1) falling edge  
when SCK0 = 1  
ii) REL signal is not  
output and trans-  
mit data is an  
Master  
• CMDT set  
• CMDD set  
SB0 (SB1)  
(CMD)  
command.  
Low-level signal to be  
output to SB0 (SB1) during  
one-clock period of SCK0  
after completion of serial  
reception  
Acknowledge  
signal  
Master/  
slave  
<1> ACKE = 1  
<2>ACKT set  
Completion of  
reception  
• ACKD set  
[Synchronous BUSY output]  
(ACK)  
[Synchronous BUSY signal]  
Low-level signal to be  
output to SB0 (SB1)  
following Acknowledge  
signal  
SCK0  
9
Serial receive disable  
because of  
Busy signal  
(BUSY)  
ACK  
BUSY  
Slave  
Slave  
• BSYE = 1  
µ
SB0 (SB1)  
D0  
D0  
READY  
READY  
processing  
ACK  
BUSY  
SB0 (SB1)  
<1> BSYE = 0  
<2>Execution of  
instruction for  
data write to  
SIO0  
High-level signal to be  
output to SB0 (SB1) before  
serial transfer start and  
after completion of serial  
transfer  
Ready signal  
(READY)  
Serial receive enable  
(transfer start  
instruction)  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Table 16-3. Various Signals in SBI Mode (2/2)  
Output  
Output  
Device  
Signal Name  
Definition  
Timing Chart  
Effects on Flag  
Meaning of Signal  
Condition  
Synchronous clock to  
output address/command/  
data, ACK signal,  
1
2
7
8
9
10  
SCK0  
Timing of signal  
output to serial data  
bus  
Serial clock  
(SCK0)  
synchronous BUSY signal,  
etc. Address/command/  
data are transferred with  
the first eight synchronous  
clocks.  
Master  
SB0 (SB1)  
8-bit data to be transferred  
in synchronization with  
SCK0 after output of REL  
and CMD signals  
1
1
1
2
2
2
7
7
7
8
8
8
SCK0  
When CSIE0 = 1,  
execution of  
Address value of  
slave device on the  
serial bus  
Address  
Master  
Master  
(A7 to A0)  
SB0 (SB1)  
instruction for  
data write to  
SIO0 (serial  
CSIIF0 set (rising  
edge of 9th clock  
REL CMD  
Note 1  
of SCK0)  
transfer start  
8-bit data to be transferred  
in synchronization with  
SCK0 after output of only  
CMD signal without REL  
signal output  
Note 2  
instruction)  
SCK0  
Instructions and  
messages to the  
slave device  
Commands  
(C7 to C0)  
SB0 (SB1)  
µ
CMD  
8-bit data to be transferred  
in synchronization with  
SCK0 without output of  
REL and CMD signals  
Numeric values to be  
processed with slave  
or master device  
SCK0  
Master/  
slave  
Data  
(D7 to D0)  
SB0 (SB1)  
Notes 1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0.  
When WUP = 1, an address is received. Only when the address matches the slave address register (SVA) value, CSIIF0 is set. (if the address does  
not coincide with the value of SVA, RELD is cleared).  
2. In BUSY state, transfer starts after the READY state is set.  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(5) Pin configuration  
The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations.  
(a) SCK0 ............ Serial clock input/output pin  
<1> Master... CMOS and push-pull output  
<2> Slave..... Schmitt input  
(b) SB0 (SB1) .... Serial data input/output dual-function pin  
Both master and slave devices have an N-ch open drain output and a Schmitt input.  
Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary.  
Figure 16-26. Pin Configuration  
Slave Device  
Master Device  
(Clock Output)  
Clock Input  
SCK0  
SCK0  
Clock Output  
(Clock Input)  
Serial Clock  
RL  
N-ch Open-Drain  
N-ch Open-Drain  
SB0 (SB1)  
SB0 (SB1)  
Serial Data Bus  
SO0  
SI0  
SO0  
SI0  
Caution Because the N-ch open-drain output must be high-impedance state at time of data reception,  
write FFH to serial I/O shift register 0 (SIO0) in advance. The N-ch open-drain can be high-  
impedance state at any time of transfer. However, when the wake-up function specify bit  
(WUP) = 1, the N-ch open-drain output always becomes high-impedance state. Thus, it is  
not necessary to write FFH to SIO0 before reception.  
325  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(6) Address match detection method  
In the SBI mode, the master transmits a slave address to select a specific slave device.  
Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave  
address transmitted by the master coincides with the address set to SVA when the wake-up function specify  
bit (WUP) = 1.  
If the bit 5 (SIC) of the interrupt timing specify register (SINT) is set, the wake-up function cannot be used  
even if WUP is set (an interrupt request signal is generated when bus release is detected). To use the wake-  
up function, clear SIC to 0.  
Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after  
bus release (RELD = 1).  
For this match detection, match interrupt request (INTCSI0) of the address to be  
generated with WUP = 1 is normally used. Thus, execute selection/non-selection  
detection by slave address when WUP = 1.  
2. When detecting selection/non-selection without the use of interrupt request with WUP  
= 0, do so by means of transmission/reception of the command preset by program instead  
of using the address match detection method.  
(7) Error detection  
In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that  
is, the serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following way.  
(a) Method of comparing SIO0 data before transmission to that after transmission  
In this case, if two data differ from each other, a transmit error is judged to have occurred.  
(b) Method of using the slave address register (SVA)  
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit  
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is  
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged  
to have occurred.  
(8) Communication operation  
In the SBI mode, the master device selects normally one slave device as communication target from among  
two or more devices by outputting an “address” to the serial bus.  
After the communication target device has been determined, commands and data are transmitted/received  
and serial communication is realized between the master and slave devices.  
Figures 16-27 to 16-30 show data communication timing charts.  
Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of serial clock (SCK0).  
Transmit data is latched into the SO0 latch and is output with MSB set as the first bit from the SB0/P25 or  
SB1/P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into the SIO0.  
326  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1)  
Master Device Processing (Transmitter)  
Program Processing  
CMDT RELT CMDT  
Set Set Set  
Write  
to SIO0  
Interrupt Servicing  
(Preparation for the Next Serial Transfer)  
INTCSI0  
ACKD  
SCK0  
Hardware Operation  
Serial Transmission  
Generation  
Set  
Stop  
Transfer Line  
SCK0 Pin  
1
2
3
4
5
6
7
8
9
SB0 (SB1) Pin  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
ACK  
BUSY  
READY  
Address  
Slave Device Processing (Receiver)  
Program Processing  
µ
ACKT  
Set  
BUSY  
WUP0  
Clear  
CMDD CMDD CMDD  
INTCSI0  
ACK BUSY  
BUSY  
Hardware Operation  
Serial Reception  
Set  
Clear  
Set  
Generation  
Output Output  
Clear  
RELD  
Set  
(When SVA = SIO0)  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Figure 16-28. Command Transmission from Master Device to Slave Device  
Master Device Processing (Transmitter)  
Program Processing  
CMDT  
Set  
Write  
to SIO0  
Interrupt Servicing  
(Preparation for the Next Serial Transfer)  
INTCSI0  
ACKD  
SCK0  
Hardware Operation  
Serial Transmission  
Generation  
Set  
Stop  
Transfer Line  
SCK0 Pin  
1
2
3
4
5
6
7
8
9
SB0 (SB1) Pin  
C7  
C6  
C5  
C4  
C3  
C2  
C1  
C0  
ACK  
BUSY  
READY  
Command  
Slave Device Processing (Receiver)  
Program Processing  
µ
SIO0 Command ACKT  
BUSY  
analysis  
Clear  
Read  
Set  
CMDD  
Set  
INTCSI0  
ACK BUSY  
BUSY  
Hardware Operation  
Serial Reception  
Generation  
Output Output  
Clear  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Figure 16-29. Data Transmission from Master Device to Slave Device  
Master Device Processing (Transmitter)  
Program Processing  
Write  
to SIO0  
Interrupt Servicing  
(Preparation for the Next Serial Transfer)  
INTCSI0  
ACKD  
SCK0  
Hardware Operation  
Serial Transmission  
Generation  
Set  
Stop  
Transfer Line  
SCK0 Pin  
1
2
3
4
5
6
7
8
9
SB0 (SB1) Pin  
D7  
D6  
D5  
D4  
D3  
Data  
D2  
D1  
D0  
ACK  
BUSY  
READY  
Slave Device Processing (Receiver)  
Program Processing  
µ
SIO0  
Read  
ACKT  
Set  
BUSY  
Clear  
INTCSI0  
ACK BUSY  
BUSY  
Hardware Operation  
Serial Reception  
Generation  
Output Output  
Clear  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Figure 16-30. Data Transmission from Slave Device to Master Device  
Master Device Processing (Receiver)  
Program Processing  
FFH Write  
to SIO0  
FFH Write  
to SIO0  
SIO0  
Read  
ACKT  
Receive data processing  
Set  
Serial  
Reception  
INTCSI0  
SCK0  
ACK  
Hardware Operation  
Serial Reception  
Generation  
Stop  
Output  
Transfer Line  
SCK0 Pin  
1
2
3
4
5
6
7
8
9
1
2
SB0 (SB1) Pin  
BUSY READY  
D7  
D6  
D5  
D4  
D3  
Data  
D2  
D1  
D0  
ACK  
BUSY  
D7  
D6  
READY  
Slave Device processing (Transmitter)  
Program Processing  
µ
Write  
to SIO0  
Write  
to SIO0  
INTCSI0  
BUSY  
Output  
BUSY  
ACKD  
BUSY  
Hardware Operation  
Serial Transmission  
Generation  
Clear  
Set  
Clear  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(9) Transfer start  
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two  
conditions are satisfied.  
• Serial interface channel 0 operation control bit (CSIE0) = 1  
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.  
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.  
2. Because the N-ch open-drain output must be high-impedance state for data reception,  
write FFH to SIO0 in advance.  
However, when the wake-up function specify bit (WUP) = 1, the N-ch open-drain output  
is always high-impedance state. Thus, it is not necessary to write FFH to SIO0.  
3. If data is written to SIO0 when the slave is busy, the data is not lost.  
When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY)  
state, transfer starts.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)  
is set.  
Perform the following settings to the pins used for input/output of data (SB0 or SB1) after inputting RESET  
before the first byte of serial transmission.  
<1> Set the P25 and P26 output latches to 1.  
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.  
<3> Reset the P25 and P26 output latches from 1 to 0.  
331  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(10) Discrimination of slave busy state  
When device is in the master mode, follow the procedure below to judge whether slave device is in the busy  
state or not.  
<1> Detect acknowledge signal (ACK) or interrupt request signal generation.  
<2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin into the input mode.  
<3> Read out the pin state (when the pin level is high, the READY state is set).  
After the detection of the READY state, set the port mode register to 0 and return to the output mode.  
(11) SBI mode precautions  
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus  
release (RELD = 1).  
For this match detection, match interrupt (INTCSI0) of the address to be generated with WUP = 1 is  
normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.  
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of  
transmission/reception of the command preset by program instead of using the address match detection  
method.  
(c) A transition of the SB0 (SB1) pin from low to high or high to low while the SCK0 line is high is interpreted  
as a bus release or command signal. Therefore, a shift in the change timing of the bus due to the influence  
of the board capacitance, etc., may be incorrectly identified as a bus release signal (or command signal),  
regardless of whether data is being transmitted. For this reason, special care must be taken regarding  
wiring.  
(d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial  
transfer of the 1st byte after RESET input.  
<1> Set the P25 and P26 output latches to 1.  
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.  
<3> Reset the P25 and P26 output latches from 1 to 0.  
(e) If SB0 (SB1) line changes from low level to high level or from high level to low level while SCK0 line is  
high level, it is recognized as a bus release signal or a command signal. Therefore, if a lag of changing  
timing occurs on the bus because of the substrate capacity, etc., it may be judged as a bus release signal  
(command signal) despite that data is being transmitted. Exercise care for wiring.  
332  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.4.4 2-wire serial I/O mode operation  
The 2-wire serial I/O mode can cope with any communication format by program.  
Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or  
SB1).  
Figure 16-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode  
VDD  
VDD  
Master  
Slave  
SCK0  
SCK0  
SB0 (SB1)  
SB0 (SB1)  
333  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(1) Register setting  
The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface  
control register (SBIC), and the interrupt timing specify register (SINT).  
(a) Serial operating mode register 0 (CSIM0)  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
R/WNote 1  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0 pin from off-chip  
8-bit timer register 2 (TM2) output  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SIO/SB0/P25 SO0/SB1/P26  
Pin Function Pin Function  
SCK0/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
×
0
02  
Pin Function  
0
3-wire Serial I/O mode (See Section 16.4.2, “3-wire serial I/O mode operation”  
SBI mode (See section 16.4.3, “SBI mode operation”  
1
Note 2 Note 2  
SB1 (N-ch  
open-drain  
input/output)  
P25 (CMOS  
input/output  
0
×
×
0
0
0
1
SCK0 (N-ch  
open-drain  
2-wire serial  
l/O mode  
1
1
MSB  
Note 2 Note 2  
SB0 (N-ch  
open-drain  
input/output)  
input/output)  
P26 (CMOS  
input/output)  
1
0
0
×
×
0
1
R/W WUP Wake-up Function ControlNote 3  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after bus release  
(when CMDD=RELD=1) matches the slave address register (SVA) data in SBI mode  
R
COI  
0
Slave Address Comparison Result FlagNote 4  
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data  
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data  
1
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
Notes 1. Bit 6 (COI) is a read-only bit.  
2. Can be used freely as port function.  
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.  
4. When CSIE0=0, COI becomes 0.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
334  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(b) Serial bus interface control register (SBIC)  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Symbol  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
FF61H 00H R/W  
R/W  
R/W  
When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
RELT  
When CMDT = 1, SO0 Iatch is cleared to 0. After SO0 latch clearance, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
Remark CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
335  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(c) Interrupt timing specify register (SINT)  
SINT is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SINT to 00H.  
Symbol  
SINT  
7
0
<6>  
<5>  
<4>  
3
0
2
0
1
0
0
0
Address After Reset R/W  
R/WNote 1  
CLD SIC SVAM  
FF63H  
00H  
R/W  
SIC  
0
INTCSI0 Interrupt Factor Selection  
CSIIF0 is set upon termination of serial interface  
channel 0 transfer  
CSIIF0 is set upon bus release detection or  
termination of serial interface channel 0 transfer  
1
R
CLD SCK0/P27 Pin LevelNote 2  
0
1
Low level  
High level  
Notes 1. Bit 6 (CLD) is a read-only bit.  
2. When CSIE0 = 0, CLD becomes 0.  
Caution Be sure to set bits 0 to 3 to 0.  
Remark CSIIF0 : Interrupt request flag corresponding to INTCSI0  
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
336  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(2) Communication operation  
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception  
is carried out bit-wise in synchronization with the serial clock.  
Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge  
of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/  
P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the shift register  
at the rising edge of SCK0.  
Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request  
flag (CSIIF0) is set.  
Figure 16-32. 2-Wire Serial I/O Mode Timings  
1
2
3
4
5
6
7
8
SCK0  
SB0 (SB1)  
CSIIF0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
End of Transfer  
Transfer Start at the Falling Edge of SCK0  
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be  
externally connected to a pull-up resistor. Because it is necessary to set N-ch open-drain output to high-  
impedance state for data reception, write FFH to SIO0 in advance.  
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be  
manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC). However,  
do not carry out this manipulation during serial transfer.  
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27  
output latch (refer to 16.4.5 SCK0/P27 pin output manipulation).  
337  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
(3) Other signals  
Figure 16-33 shows RELT and CMDT operations.  
Figure 16-33. RELT and CMDT Operations  
SO0 Latch  
RELT  
CMDT  
(4) Transfer start  
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two  
conditions are satisfied.  
• Serial interface channel 0 operation control bit (CSIE0) = 1  
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.  
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.  
2. Because it is necessary to set N-ch open-drain output to high-impedance state for data  
reception, write FFH to SIO0 in advance.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)  
is set.  
(5) Error detection  
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination  
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.  
(a) Method of comparing SIO0 data before transmission to that after transmission  
In this case, if two data differ from each other, a transmit error is judged to have occurred.  
(b) Method of using the slave address register (SVA)  
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit  
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is  
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged  
to have occurred.  
338  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (µPD78054 Subseries)  
16.4.5 SCK0/P27 pin output manipulation  
Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to  
normal serial clock output.  
P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to  
be controlled with the RELT and CMDT bits of serial bus interface control register (SBIC).)  
SCK0/P27 pin output manipulating procedure is described below.  
<1> Set the serial operating mode register 0 (CSIM0) (SCK0 pin enabled for serial operation in the output mode).  
SCK0 = 1 with serial transfer suspended.  
<2> Manipulate the P27 output latch with a bit manipulation instruction.  
Figure 16-34. SCK0/P27 Pin Configuration  
Manipulated by bit  
manipulation instruction  
To Internal  
Circuit  
P27 Output  
Latch  
SCK0/P27  
SCK0 (1 while transfer is stopped)  
From Serial Clock  
Control Circuit  
When CSIE0 = 1  
and  
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.  
339  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
340  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
The µPD78054Y subseries incorporates three channels of serial interfaces. Differences between channels 0,  
1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface  
channel 1. Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel  
2).  
Table 17-1. Differences between Channels 0, 1, and 2  
Channel 0  
Channel 1  
Channel 2  
Serial Transfer Mode  
2
3
2
3
fXX/2, fXX/2 , fXX/2 ,  
fXX/2, fXX/2 , fXX/2 ,  
4
5
6
4
5
6
fXX/2 , fXX/2 , fXX/2 ,  
fXX/2 , fXX/2 , fXX/2 ,  
Baud rate generator  
Clock selection  
7
8
7
8
fXX/2 , fXX/2 , external fXX/2 , fXX/2 , external output  
clock, TO2 output  
clock, TO2 output  
MSB/LSB switchable  
as the start bit  
MSB/LSB switchable  
as the start bit  
MSB/LSB switchable  
as the start bit  
3-wire serial I/O  
Transfer method  
Automatic transmit/  
receive function  
Serial transfer end  
Serial transfer end  
interrupt request flag  
(CSIIF1)  
Serial transfer end  
interrupt request flag  
(SRIF)  
Transfer end flag interrupt request flag  
(CSIIF0)  
2
I C bus (Inter IC Bus)  
Use possible  
None  
None  
2-wire serial I/O  
None  
UART  
Use possible  
(Asynchronous serial interface)  
341  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.1 Serial Interface Channel 0 Functions  
Serial interface channel 0 employs the following four modes.  
• Operation stop mode  
• 3-wire serial I/O mode  
• 2-wire serial I/O mode  
2
• I C (Inter IC) bus mode  
2
Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, I C bus) while the  
operation of serial interface channel 0 is enabled. Stop the serial operation before switching  
the operation mode.  
(1) Operation stop mode  
This mode is used when serial transfer is not carried out. Power consumption can be reduced.  
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)  
This mode is used for 8-bit data transfer using three lines, one each for serial clock (SCK0), serial output (SO0)  
and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data  
transfer processing time.  
The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected  
regardless of their start bit recognition.  
This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate  
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.  
(3) 2-wire serial I/O mode (MSB-first)  
This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or  
SB1).  
This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level  
and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or  
more devices can be removed, resulting in the increased number of available input/output ports.  
342  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
2
(4) I C (Inter IC) bus mode (MSB-first)  
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and  
serial data bus (SDA0 or SDA1).  
2
This mode is in compliance with the I C bus format. In this mode, the transmitter can output three kinds of  
data onto the serial data bus: “start condition”, “data”, and “stop condition”, to be actually sent or received.  
The receiver automatically distinguishes the received data into “start condition”, “data”, or “stop condition”,  
by hardware.  
2
Figure 17-1. Serial Bus Configuration Example Using I C Bus  
VDD  
VDD  
Master CPU  
Slave CPU1  
SCL  
SDA0 (SDA1)  
SCL  
SDA0 (SDA1)  
Slave CPU2  
SCL  
SDA0 (SDA1)  
Slave CPUn  
SCL  
SDA0 (SDA1)  
343  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.2 Serial Interface Channel 0 Configuration  
Serial interface channel 0 consists of the following hardware.  
Table 17-2. Serial Interface Channel 0 Configuration  
Item  
Register  
Configuration  
Serial I/O shift register 0 (SIO0)  
Slave address register (SVA)  
Timer clock select register 3 (TCL3)  
Serial operating mode register 0 (CSIM0)  
Serial bus interface control register (SBIC)  
Interrupt timing specify register (SINT)  
Control register  
Note  
Port mode register 2 (PM2)  
Note Refer to Figure 6-7. Block Diagram of P20, P21, P23 to P26 and Figure 6-8. Block Diagram of  
P22, P27.  
344  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-2. Serial Interface Channel 0 Block Diagram  
Internal Bus  
Serial Bus Interface  
Control Register  
Serial Operating Mode Register 0  
Slave Address  
Register (SVA)  
CSIM CSIM CSIM CSIM CSIM  
CSIE0 COI WUP  
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
04  
03  
02  
01  
00  
SVAM  
Match  
BSYE  
PM25  
Control  
Circuit  
CLRSET  
SI0/SB0/  
SDA0/P25  
Serial I/O Shift  
Register 0 (SIO0)  
D
Q
Selector  
P25  
Output Latch  
Output  
Control  
Acknowledge  
Output Circuit  
Selector  
SO0/SB1/  
SDA1/P26  
PM26  
Stop Condition/  
Start Condition/  
Acknowledge  
Detector  
ACKD  
CMDD  
RELD  
WUP  
Output  
Control  
Interrupt  
Request  
Signal  
P26 Output Latch  
CLD  
INTCSI0  
fxx/2-fxx/28  
Serial Clock  
Counter  
SCK0/  
SCL/P27  
Generator  
TO2  
PM27  
Output  
Control  
1/16  
Divider  
Serial Clock  
Control Circuit  
Selector  
Selector  
CSIM00  
CSIM01  
CSIM00  
CSIM01  
4
2
P27  
Output Latch  
CLD  
SIC SVAM  
TCL33 TCL32 TCL31 TCL30  
CLC WREL WAT1 WAT0  
Interrupt Timing  
Specify Register  
Timer Clock  
Select  
Register 3  
Internal Bus  
Remark Output Control selects between CMOS output and N-ch open drain output.  
345  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(1) Serial I/O shift register 0 (SIO0)  
This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception  
(shift operation) in synchronization with the serial clock.  
SIO0 is set with an 8-bit memory manipulation instruction.  
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.  
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In  
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.  
2
Note that, if a bus is driven in the I C bus mode or 2-wire serial I/O mode, the bus pin must serve for both  
input and output. Therefore, the transmission N-ch open-drain output of the device which will start reception  
of data must set to high impedance beforehand. Consequently, write FFH to SIO0 in advance.  
2
In the I C bus mode, set SIO0 to FFH with bit 7 (BSYE) of the serial bus interface control register (SBIC) set  
to 0.  
RESET input makes SIO0 undefined.  
2
Caution Do not execute an instruction that writes SIO0 in the I C bus mode while WUP (bit 5 of the  
serial operating mode register 0 (CSIM0)) = 1. Even if such an instruction is not executed,  
data can be received when the wake-up function is used (WUP = 1). For the detail of the wake-  
up function, refer to 17.4.4 (1) (c) Wake-up function.  
(2) Slave address register (SVA)  
This is an 8-bit register to set the slave address value for connection of a slave device to the serial bus.  
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O mode.  
The master device outputs a slave address for selection of a particular slave device to the connected slave  
device. These two data (the slave address output from the master device and the SVA value) are compared  
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of  
serial operating mode register 0 (CSIM0) becomes 1.  
Address comparison can also be executed on the data of LSB-masked high-order 7 bits by setting bit 4 (SVAM)  
of the interrupt timing specify register (SINT) to (1).  
If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)  
2
is cleared to 0. In the I C bus mode, the wake-up function can be used by setting the bit 5 (WUP) of CSIM0.  
In this case, the interrupt request signal (INTCSI0) is generated when the slave address output by the master  
coincides with the value of SVA (the interrupt request signal is also generated when the stop condition is  
detected), and it can be learned by this interrupt request that the master requests for communication. To use  
the wake-up function, set SIC to 1.  
2
Further, when SVA transmits data as master or slave device in the the I C bus mode or 2-wire serial I/O mode,  
errors can be detected using SVA.  
RESET input makes SVA undefined.  
(3) SO0 latch  
This latch holds SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by  
software.  
(4) Serial clock counter  
This counter counts the serial clocks to be output and input during transmission/reception and to check whether  
8-bit data has been transmitted/received.  
(5) Serial clock control circuit  
This circuit controls serial clock supply to the serial I/O shift register 0 (SIO0). When the internal system clock  
is used, the circuit also controls clock output to the SCK0/SCL/P27 pin.  
346  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(6) Interrupt request signal generator  
This circuit controls interrupt request signal generation. It generates interrupt request signals according to  
the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation  
mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 17-3.  
(7) Acknowledge output circuit and stop condition/start condition/acknowledge detector  
2
These two circuits output and detect various control signals in the I C mode.  
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.  
Table 17-3. Serial Interface Channel 0 Interrupt Request Signal Generation  
Serial Transfer mode  
BSYE WUP WAT1 WAT0 ACKE Description  
3-wire or 2-wire serial I/O mode  
0
0
0
0
0
0
0
An interrupt request signal is generated each  
time 8 serial clocks are counted.  
Other than above  
1
Setting prohibited  
2
I C bus mode (transmit)  
0
0
An interrupt request signal is generated each  
time 8 serial clocks are counted (8-clock wait).  
Normally,duringtransmissionthesettingsWAT21,  
WAT0 = 1, 0, are not used. They are used only  
when wanting to coordinate receive time and  
processing systematically using software. ACK  
information is generated by the receiving side,  
thus ACKE should be set to 0 (disable).  
An interrupt request signal is generated each  
time 9 serial clocks are counted (9-clock wait).  
ACK information is generated by the receiving  
side, thus ACKE should be set to 0 (disable).  
Setting prohibited  
1
1
0
Other than above  
2
I C bus mode (receive)  
1
0
1
0
1
0
An interrupt request signal is generated each  
time 8 serial clocks are counted (8-clock wait).  
ACKinformationisoutputbymanipulatingACKT  
by software after an interrupt is generated.  
An interrupt request signal is generated each  
time 9 serial clocks are counted (9-clock wait).  
To automatically generate ACK information,  
presetACKEto1beforetransferstart.However,  
in the case of the master, set ACKE to 0  
(disable) before receiving the last data.  
After address is received, if the values of the  
serial I/O shift register 0 (SI00) and the slave  
address register (SVA) match, and if the stop  
conditionisdetected,aninterruptrequestsignal  
is generated.  
1
0/1  
1
1
1
1
1
To automatically generate ACK information,  
presetACKEto1(enable)beforetransferstart.  
Setting prohibited  
Other than above  
Remark BSYE: Bit 7 of serial bus interface control register (SBIC)  
ACKE: Bit 5 of serial bus interface control register (SBIC)  
347  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.3 Serial Interface Channel 0 Control Registers  
The following four types of registers are used to control serial interface channel 0.  
• Timer clock select register 3 (TCL3)  
• Serial operating mode register 0 (CSIM0)  
• Serial bus interface control register (SBIC)  
• Interrupt timing specify register (SINT)  
(1) Timer clock select register 3 (TCL3)  
This register sets the serial clock of serial interface channel 0.  
TCL3 is set with an 8-bit memory manipulation instruction.  
RESET input sets TCL3 to 88H.  
348  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-3. Timer Clock Select Register 3 Format  
Symbol  
7
6
5
4
3
2
1
0
Address After Reset R/W  
88H R/W  
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H  
Serial Interface Channel 0 Serial Clock Selection  
TCL33 TCL32 TCL31 TCL30  
Serial Clock in I2C Bus Mode  
Serial Clock in 2-Wire or 3-Wire  
Serial I/O Mode  
MCS = 1  
MCS = 1  
MCS = 0  
MCS = 0  
fXX/25 Setting prohibited  
fXX/26 fX/26 (78.1 kHz)  
fXX/27 fX/27 (39.1 kHz)  
fXX/28 fX/28 (19.5 kHz)  
fXX/29 fX/29 (9.77 kHz)  
fXX/210 fX/210 (4.88 kHz)  
fXX/211 fX/211 (2.44 kHz)  
fXX/212 fX/212 (1.22 kHz)  
Setting prohibited  
Setting prohibited  
fX/22 (1.25 MHz)  
fX/23 (625 kHz)  
fX/24 (313 kHz)  
fX/25 (156 kHz)  
fX/26 (78.1 kHz)  
fX/27 (39.1 kHz)  
fX/28 (19.5 kHz)  
fX/26 (78.1 kHz) fXX/2  
fX/27 (39.1 kHz) fXX/22  
fX/28 (19.5 kHz) fXX/23  
fX/29 (9.77 kHz) fXX/24  
fX/210 (4.88 kHz) fXX/25  
fX/211 (2.44 kHz) fXX/26  
fX/212 (1.22 kHz) fXX/27  
fX/213 (0.61 kHz) fXX/28  
fX/22 (1.25 MHz)  
fX/23 (625 kHz)  
fX/24 (313 kHz)  
fX/25 (156 kHz)  
fX/26 (78.1 kHz)  
fX/27 (39.1 kHz)  
fX/28 (19.5 kHz)  
fX/29 (9.8 kHz)  
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Other than above  
Serial Interface Channel 1 Serial Clock Selection  
MCS = 1  
TCL37 TCL36 TCL35 TCL34  
MCS = 0  
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
fXX/2  
Setting prohibited  
fX/22 (1.25 MHz)  
fX/23 (625 kHz)  
fX/24 (313 kHz)  
fX/25 (156 kHz)  
fX/26 (78.1 kHz)  
fX/27 (39.1 kHz)  
fX/28 (19.5 kHz)  
fX/22 (1.25 MHz)  
fX/23 (625 kHz)  
fX/24 (313 kHz)  
fX/25 (156 kHz)  
fX/26 (78.1 kHz)  
fX/27 (39.1 kHz)  
fX/28 (19.5 kHz)  
fX/29 (9.8 kHz)  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
Other than above  
Setting prohibited  
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
3. MCS : Oscillation mode selection register (OSMS) bit 0  
4. Figures in parentheses apply to operation with fX = 5.0 MHz.  
349  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(2) Serial operating mode register 0 (CSIM0)  
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up  
function and displays the address comparator match signal.  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
2
Caution Do not switch the operation mode (3-wire serial I/O, 2-wire serial I/O, I C bus) while the  
operation of serial interface channel 0 is enabled. Stop the serial operation before switching  
the operation mode.  
350  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-4. Serial Operating Mode Register 0 Format  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
R/WNote 1  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0/SCL pin from off-chip  
8-bit timer register 2 (TM2) outputNote2  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
02  
P25 Pin Function P26 Pin Function  
Pin Function  
Note3 Note3  
3-wire serial  
l/O mode  
SI0Note3  
(Input)  
SO0  
SCK0 (CMOS  
0
1
MSB  
LSB  
0
×
1
×
0
0
0
0
0
0
1
1
(CMOS output) input/output)  
Note4 Note4  
SB1/SDA1  
P25 (CMOS  
input/output)  
0
1
×
×
(N-ch open-drain  
SCK0/SCL  
2-wire serial  
l/O mode  
or  
input/output)  
(N-ch open-  
drain input/  
output)  
1
1
MSB  
Note4 Note4  
SB0/SDA0  
(N-ch open-drain  
input/output)  
I2C Bus Mode  
P26 (CMOS  
input/output)  
0
0
×
×
0
1
R/W WUP Wake-up Function ControlNote 5  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after detecting start condition  
(when CMDD = 1) matches the slave address register (SVA) data in I2C bus mode  
R
COI  
0
Slave Address Comparison Result FlagNote 6  
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data  
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data  
1
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
Notes 1. Bit 6 (COI) is a read-only bit.  
2
2. I C bus mode, the clock frequency becomes 1/16 of that output from TO2.  
3. Can be used as P25 (CMOS input/output) when used only for transmission.  
4. Can be used freely as port function.  
5. To use the wake-up function (WUP = 1), set the bit 5 (SIC) of the interrupt timing specify register  
(SINT) to 1. Do not execute an instruction that writes the serial I/O shift register 0 (SIO0) while  
WUP = 1.  
6. When CSIE0 = 0, COI becomes 0.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
351  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(3) Serial bus interface control register (SBIC)  
This register sets serial bus interface operation and displays statuses.  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Figure 17-5. Serial Bus Interface Control Register Format (1/2)  
Symbol  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
R/WNote  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
FF61H  
00H  
R/W  
R/W  
R
Used for stop condition signal output.  
When RELT = 1, SO0 Iatch is set to 1. After SO0 latch setting, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
RELT  
Used for start condition signal output.  
When CMDT = 1, SO0 Iatch is cleared to (0). After SO0 latch clearance, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
RELD Stop Condition Detection  
Clear Conditions (RELD = 0)  
Set Conditions (RELD =1)  
• When transfer start instruction is executed  
• If SIO0 and SVA values do not match in  
address reception  
• When stop condition signal is detected  
• When CSIE0 = 0  
• When RESET input is applied  
R
CMDD Start Condition Detection  
Clear Conditions (CMDD = 0)  
Set Conditions (CMDD = 1)  
• When transfer start instruction is executed  
• When stop condition signal is detected  
• When CSIE0 = 0  
• When start condition signal is detected  
• When RESET input is applied  
R/W  
Used to generate the ACK signal by software when 8-clock wait mode is selected.  
Keeps SDA0 (SDA1) low from set instruction (ACKT=1) execution to the next falling edge of SCL.  
Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.  
ACKT  
Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.  
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, ACKT) are 0 when read after the data is set.  
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
352  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-5. Serial Bus Interface Control Register Format (2/2)  
ACKE Acknowledge Signal Output Control Note 1  
R/W  
Disables acknowledge signal automatic output. (However, output with ACKT is enabled)  
Used for reception when 8-clock wait mode is selected or for transmission.Note 2  
0
1
Enables acknowledge signal automatic output.  
Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle  
(automatically output when ACKE = 1).  
However, not automatically cleared to 0 after acknowledge signal output.  
Used in reception with 9-clock wait mode selected.  
R
ACKD Acknowledge Detection  
Clear Conditions (ACKD = 0)  
Set Conditions (ACKD = 1)  
• While executing the transfer start instruction  
• When CSIE0 = 0  
• When acknowledge signal (ACK) is detected at the  
rising edge of SCL clock after completion of  
transfer  
• When RESET input is applied  
Note3  
R/W  
BSYE Control of N-ch Open-Drain Output for Transmission in I2C Bus ModeNote 4  
Output enabled (transmission)  
Output disabled (reception)  
0
1
Notes 1. Setting should be performed before transfer.  
2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using  
ACKT.  
3. The busy mode can be canceled by start of serial interface transfer or reception of address signal.  
However, the BSYE flag is not cleared to 0.  
4. When using the wake-up function, be sure to set BSYE to 1.  
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
353  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(4) Interrupt timing specify register (SINT)  
This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level  
status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SINT to 00H.  
Figure 17-6. Interrupt Timing Specify Register Format (1/2)  
Symbol  
SINT  
7
0
<6>  
<5>  
<4>  
<3>  
<2>  
1
0
Address After Reset R/W  
R/WNote 1  
CLD SIC SVAM CLC WREL WAT1 WAT0  
FF63H  
00H  
R/W  
WAT1  
0
Wait and Interrupt Control  
WAT0  
0
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.  
(keeping clock output in high impedance)  
0
1
Setting prohibited  
1
0
Used in I2C bus mode. (8-clock wait)  
Generates interrupt service request at rising edge of 8th SCK0 clock cycle.  
(In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are  
output. In the case of slave device, makes SCL output low to request wait state after 8 clock  
pulses are input.)  
Used in I2C bus mode. (9-clock wait)  
1
1
Generates interrupt service request at rising edge of 9th SCK0 clock cycle.  
(In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are  
output. In the case of slave device, makes SCL output low to request wait state after 9 clock  
pulses are input.)  
R/W  
WREL  
0
Wait Sate Cancellation Control  
Wait state has been cancelled.  
Cancels wait state. Automatically cleared to 0 when the state is cancelled.  
(Used to cancel wait state by means of WAT0 and WAT1.)  
1
Clock Level ControlNote 2  
CLC  
0
R/W  
Used in I2C bus mode.  
Make output level of SCL pin low unless serial transfer is being performed.  
1
Used in I2C bus mode.  
Make SCL pin enter high-impedance state unless serial transfer is being performed.  
(except for clock line which is kept high)  
Used to enable master device to generate start condition and stop condition signals.  
Notes 1. Bit 6 (CLD) is a read-only bit.  
2
2. When not using the I C mode, set CLC to 0.  
354  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-6. Interrupt Timing Specify Register Format (2/2)  
R/W  
R/W  
SVAM SVA Bit to be Used as Slave Address  
0
1
Bits 0 to 7  
Bits 1 to 7  
SIC  
0
INTCSI0 Interrupt Cause SelectionNote1  
CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer  
1
CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer  
SCK0/SCL Pin LevelNote 2  
Low level  
R
CLD  
0
1
High level  
2
Notes 1. When using wake-up function in the I C mode, set SIC to 0.  
2. When CSIE0 = 0, CLD becomes 0.  
Remark SVA : Slave address register  
CSIIF0 : Interrupt request flag corresponding to INTCSI0  
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
355  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.4 Serial Interface Channel 0 Operations  
The following four operating modes are available to the serial interface channel 0.  
• Operation stop mode  
• 3-wire serial I/O mode  
• 2-wire serial I/O mode  
2
• I C (Inter IC) bus mode  
17.4.1 Operation stop mode  
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial  
I/O shift register 0 (SIO0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register.  
In the operation stop mode, the P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 and P27/SCK0/SCL pins can be used  
as general input/output ports.  
(1) Register setting  
The operation stop mode is set with the serial operating mode register 0 (CSIM0).  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
FF60H 00H R/W  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
356  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.4.2 3-wire serial I/O mode operation  
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate  
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.  
Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).  
(1) Register setting  
The 3-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0) and serial bus interface  
control register (SBIC).  
(a) Serial operating mode register 0 (CSIM0)  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/WNote 1  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0 pin from off-chip  
8-bit timer register 2 (TM2) output  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SIO/SB0/SDA0  
SO0/SB1/SDA1 SCK0/SCL/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
02  
/P25 Pin Function /P26 Pin Function  
Pin Function  
Note 2  
Note 2  
0
1
MSB  
LSB  
3-wire serial  
l/O mode  
SI0Note 2  
(Input)  
SO0  
SCK0 (CMOS  
0
×
1
×
0
0
0
1
(CMOS output) input/output)  
1
1
2-wire serial I/O mode (See the section 17.4.3, “2-wire serial I/O mode operation”.)  
or  
I2C bus mode (See the section 17.4.4, “I2C bus mode operation”.)  
R/W WUP Wake-up Function ControlNote 3  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after detecting start condition  
(when CMDD = 1) matches the slave address register (SVA) data in I2C bus mode  
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
Notes 1. Bit 6 (COI) is a read-only bit.  
2. Can be used as P25 (CMOS input/output) when used only for transmission.  
3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
357  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(b) Serial bus interface control register (SBIC)  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Symbol  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
FF61H 00H R/W  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
R/W  
R/W  
When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
RELT  
When CMDT = 1, SO0 Iatch is cleared to 0. After SO0 latch clearance, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
358  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(2) Communication operation  
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/  
reception is carried out in synchronization with the serial clock.  
Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0).  
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the  
SI0 pin is latched in SIO0 at the rising edge of SCK0.  
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)  
is set.  
Figure 17-7. 3-Wire Serial I/O Mode Timings  
SCK0  
SI0  
1
2
3
4
5
6
7
8
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SO0  
DO7  
DO6  
DO5  
DO4  
DO3  
DO2  
DO1  
DO0  
CSIIF0  
End of Transfer  
Transfer Start at the Falling Edge of SCK0  
The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses. Thus, the SO0 pin output status  
can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC).  
However, do not carry out this manipulation during serial transfer.  
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27  
output latch (refer to 17.4.7 SCK0/SCL/P27 pin output manipulation).  
(3) Other signals  
Figure 17-8 shows RELT and CMDT operations.  
Figure 17-8. RELT and CMDT Operations  
SO0 latch  
RELT  
CMDT  
359  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(4) MSB/LSB switching as the start bit  
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.  
Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the  
figure, MSB/LSB can be read/written in reverse form.  
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of the serial operating mode register  
0 (CSIM0).  
Figure 17-9. Circuit of Switching in Transfer Bit Order  
7
6
Internal Bus  
1
0
LSB-first  
MSB-first  
Read/Write Gate  
Read/Write Gate  
SO0 Latch  
SI0  
Serial I/O Shift Register 0 (SIO0)  
D
Q
SO0  
SCK0  
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains  
unchanged.  
Thus, switching between MSB-first and LSB-first must be performed before writing data to SIO0.  
(5) Transfer start  
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two  
conditions are satisfied.  
• Serial interface channel 0 operation control bit (CSIE0) = 1.  
• Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer.  
Caution If CSIE0 is set to “1” after data write to SIO0, transfer does not start.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)  
is set.  
360  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.4.3 2-wire serial I/O mode operation  
The 2-wire serial I/O mode can cope with any communication format by program.  
Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or  
SB1).  
Figure 17-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode  
VDD  
VDD  
Master  
Slave  
SCK0  
SCK0  
SB0 (SB1)  
SB0 (SB1)  
(1) Register setting  
The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface  
control register (SBIC), and the interrupt timing specify register (SINT).  
361  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(a) Serial operating mode register 0 (CSIM0)  
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM0 to 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset R/W  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
FF60H  
00H  
R/WNote 1  
R/W CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input Clock to SCK0 pin from off-chip  
8-bit timer register 2 (TM2) output  
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM  
Operation  
Mode  
SIO/SB0/SDA0  
SO0/SB1/SDA1 SCK0/SCL/P27  
PM25 P25 PM26 P26 PM27 P27  
Start Bit  
04  
03  
02  
/P25 Pin Function /P26 Pin Function  
Pin Function  
0
×
3-wire Serial I/O mode (See Section 17.4.2, “3-wire serial I/O mode operation”  
Note 2 Note 2  
SB1/SDA1  
(N-ch open-drain  
input/output)  
P25 (CMOS  
input/output  
0
1
×
×
0
0
0
0
1
1
2-wire serial  
l/O mode  
or  
SCK0/SCL  
(N-ch open-drain  
input/output)  
1
1
MSB  
I2C bus mode  
Note 2 Note 2  
SB0/SDA0  
(N-ch open-drain  
input/output)  
P26 (CMOS  
input/output)  
0
0
×
×
R/W WUP Wake-up Function Control Note 3  
0
1
Interrupt request signal generation with each serial transfer in any mode  
Interrupt request signal generation when the address received after detecting start condition  
(when CMDD = 1) matches the slave address register (SVA) data in I2C bus mode  
R
COI  
0
Slave Address Comparison Result FlagNote4  
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data  
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data  
1
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Operation stopped  
Operation enabled  
Notes 1. Bit 6 (COI) is a read-only bit.  
2. Can be used freely as port function.  
3. Be sure to set WUP to 0 when the 2-wire serial I/O mode.  
4. When CSIE0=0, COI becomes 0.  
Remark  
×
: don’t care  
PM×× : Port mode register  
P×× : Port output latch  
362  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(b) Serial bus interface control register (SBIC)  
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Symbol  
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
FF61H 00H R/W  
R/W  
R/W  
When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
RELT  
When CMDT = 1, SO0 Iatch is cleared to 0. After SO0 latch clearance, automatically cleared to 0.  
Also cleared to 0 when CSIE0 = 0.  
CMDT  
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
363  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(c) Interrupt timing specify register (SINT)  
SINT is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SINT to 00H.  
Symbol  
SINT  
7
0
<6>  
<5>  
<4>  
<3>  
<2>  
1
0
Address After Reset R/W  
R/WNote 1  
CLD SIC SVAM CLC WREL WAT1 WAT0  
FF63H  
00H  
R/W SIC  
0
INTCSI0 Interrupt Factor Selection  
CSIIF0 is set upon termination of serial interface channel 0 transfer  
1
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer  
SCK0 Pin LevelNote 2  
Low level  
R
CLD  
0
1
High level  
Notes 1. Bit 6 (CLD) is a read-only bit.  
2. When CSIE0 = 0, CLD becomes 0.  
Caution Be sure to set bits 0 to 3 to 0 in the 2-wire serial I/O mode is used.  
Remark CSIIF0 : Interrupt request flag corresponding to INTCSI0  
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
364  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(2) Communication operation  
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception  
is carried out bit-wise in synchronization with the serial clock.  
Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge  
of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/SDA0/P25  
(or SB1/SDA1/P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched  
into the shift register at the rising edge of SCK0.  
Upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request  
flag (CSIIF0) is set.  
Figure 17-11. 2-Wire Serial I/O Mode Timings  
1
2
3
4
5
6
7
8
SCK0  
SB0 (SB1)  
CSIIF0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
End of Transfer  
Transfer Start at the Falling Edge of SCK0  
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be  
externally connected to a pull-up resistor. Because it is necessary to set the N-ch open-drain ouput to high  
impedance for data reception, write FFH to SIO0 in advance.  
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be  
manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC). However,  
do not carry out this manipulation during serial transfer.  
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27  
output latch (refer to 17.4.7 SCK0/SCL/P27 pin output manipulation).  
365  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(3) Other signals  
Figure 17-12 shows RELT and CMDT operations.  
Figure 17-12. RELT and CMDT Operations  
SO0 Latch  
RELT  
CMDT  
(4) Transfer start  
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two  
conditions are satisfied.  
• Serial interface channel 0 operation control bit (CSIE0) = 1  
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.  
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.  
2. Because the N-ch open-drain output must be set to high-impedance state for data  
reception, write FFH to SIO0 in advance.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)  
is set.  
(5) Error detection  
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination  
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way.  
(a) Method of comparing SIO0 data before transmission to that after transmission  
In this case, if two data differ from each other, a transmit error is judged to have occurred.  
(b) Method of using the slave address register (SVA)  
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit  
(match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0) is  
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged  
to have occurred.  
366  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
2
17.4.4 I C bus mode operation  
2
The I C bus mode is provided for when communication operations are performed between a single master device  
and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is  
based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master  
device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data  
bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple  
microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port  
pins and on-board wires.  
2
In the I C bus specification, the master sends start condition, data, and stop condition signals to slave devices  
through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the  
2
signal detection function incorporated as hardware. This function simplifies the application program to control I C  
bus.  
An example of a serial bus configuration is shown in Figure 17-13. This system below is composed of CPUs and  
2
peripheral ICs having serial interface hardware that complies with the I C bus specification.  
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open-  
2
drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I C bus.  
2
The signals used in the I C bus mode are described in Table 17-4.  
2
Figure 17-13. Example of Serial Bus Configuration Using I C Bus  
VDD VDD  
Master CPU  
Slave CPU1  
Serial clock  
SCL  
SDA0(SDA1)  
SCL  
SDA0(SDA1)  
Serial data bus  
Slave CPU2  
SCL  
SDA0(SDA1)  
Slave IC  
SCL  
SDA  
367  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
2
(1) I C bus mode functions  
2
In the I C bus mode, the following functions are available.  
(a) Automatic identification of serial data  
Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series  
through the serial data bus.  
(b) Chip selection by specifying device addresses  
2
The master device can select a specific slave device connected to the I C bus and communicate with it by  
sending in advance the address data corresponding to the destination device.  
(c) Wake-up function  
An interrupt request is generated during slave operation when the received address matches the value of slave  
address register (SVA). (the interrupt request also occurs when the stop condition is detected). Therefore,  
2
CPUs other than the selected slave device on the I C bus can perform independent operations during the  
serial communication.  
(d) Acknowledge signal (ACK) control function  
The master device and a slave device send and receive acknowledge signals to confirm that the serial  
communication has been executed normally.  
(e) Wait signal (WAIT) control function  
When a slave device is preparing for data transmission or reception and requires more waiting time, the slave  
device outputs a wait signal on the bus to inform the master device of the wait status.  
2
(2) I C bus definition  
2
This section describes the format of serial data communications and functions of the signals used in the I C  
bus mode.  
First, the transfer timings of the start condition, data, and stop condition signals, which are output onto the  
2
signal data bus of the I C bus, are shown in Figure 17-14.  
2
Figure 17-14. I C Bus Serial Data Transfer Timing  
SCL  
1-7  
8
9
1-7  
8
9
1-7  
8
9
SDA0(SDA1)  
Start  
condition  
Address R/W ACK  
Data  
ACK  
Data  
ACK  
Stop  
condition  
The start condition, slave address, and stop condition signals are output by the master. The acknowledge  
signal (ACK) is output by either the master or the slave device (normally by the device which has received  
the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device.  
368  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(a) Start condition  
When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is  
recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0  
(or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See section  
2
17.4.5, "Cautions on Use of I C Bus Mode," for details of the start condition output.  
The start condition signal is detected by hardware incorporated in slave devices.  
Figure 17-15. Start Condition  
H
SCL  
SDA0(SDA1)  
(b) Address  
The 7 bits following the start condition signal are defined as an address.  
The 7-bit address data is output by the master device to specify a specific slave from among those connected  
to the bus line. Each slave device on the bus line must therefore have a different address.  
Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the  
data of the slave address register (SVA). After the comparison, only the slave device in which the data are a  
match becomes the communication partner, and subsequently performs communication with the master device  
until the master device sends a start condition or stop condition signal.  
Figure 17-16. Address  
SCL  
1
2
3
4
5
6
7
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
SDA0(SDA1)  
Address  
(c) Transfer direction specification  
The 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer  
direction specification bit. If this bit is 0, it is the master device which will send data to the slave. If it is 1, it  
is the slave device which will send data to the master.  
Figure 17-17. Transfer Direction Specification  
SCL  
1
2
3
4
5
6
7
8
SDA0(SDA1)  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
Transfer direction  
specification  
369  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(d) Acknowledge signal (ACK)  
The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is  
used between the sending side and receiving side devices for confirmation of correct data transfer. In principle,  
the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data.  
The only exception is when the receiving side is the master device and the 8-bit data is the last transfer data;  
the master device outputs no acknowledge signal in this case.  
The sending side that has tranferred 8-bit data waits for the acknowledge signal which will be sent from the  
receiving side. If the sending side device receives the acknowledge signal, which means a successful data  
transfer, it proceeds to the next processing. If this signal is not sent back from the slave device, this means  
that the data sent has not been received by the slave device, and therefore the master device outputs a stop  
condition signal to terminate subsequent transmissions.  
Figure 17-18. Acknowledge Signal  
SCL  
1
2
3
4
5
6
7
8
9
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
ACK  
SDA0 (SDA1)  
(e) Stop condition  
If the SDA0 (SDA1) pin level changes from low to high while the SCL pin is high, this transition is defined as  
a stop condition signal.  
The stop condition signal is output from the master to the slave device to terminate a serial transfer.  
The stop condition signal is detected by hardware incorporated in the slave device.  
Figure 17-19. Stop Condition  
H
SCL  
SDA0(SDA1)  
370  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(f) Wait signal (WAIT)  
The wait signal is output by a slave device to inform the master device that the slave device is in wait state due  
to preparing for transmitting or receiving data.  
During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay  
subsequent transfers. When the wait state is released, the master device can start the next transfer. For the  
2
releasing operation of slave devices, see section 17.4.5, “Cautions on Use of I C Bus Mode.”  
Figure 17-20. Wait Signal  
(a) Wait of 8 Clock Cycles  
Set low because slave device drives low,  
though master device returns to Hi-Z state.  
No wait is inserted after 9th clock cycle.  
(and before master device starts next transfer.)  
SCL of  
master device  
6
7
8
9
1
2
3
4
SCL of  
slave device  
SCL  
D2  
D1  
D0  
D7  
D6  
D5  
D4  
ACK  
SDA0(SDA1)  
Output by manipulating ACKT  
(b) Wait of 9 Clock Cycles  
Set low because slave device drives low,  
though master device returns to Hi-Z state.  
SCL of  
master device  
6
7
8
9
1
2
3
SCL of  
slave device  
SCL  
D2  
D1  
D0  
ACK  
D7  
D6  
D5  
SDA0(SDA1)  
Output based on the value set in ACKE in advance  
371  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(3) Register setting  
2
The I C mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control  
register (SBIC), and the interrupt timing specify register (SINT).  
(a) Serial operating mode register 0 (CSIM0)  
CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets 00H.  
Symbol  
<7>  
<6>  
<5>  
4
3
2
1
0
Address After Reset  
FF60H 00H  
R/W  
CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00  
R/WNote1  
R/W  
CSIM01 CSIM00  
Serial Interface Channel 0 Clock Selection  
0
1
1
×
0
1
Input clock from off-chip to SCL pin  
Note 2  
8-bit timer register 2 (TM2) output (See  
)
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)  
R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operation  
Start SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27  
bit P25 pin function P26 pin function pin function  
3-wire serial I/O mode (see section 17.4.2 "Operation in 3-wire serial I/O mode")  
04  
03  
02  
mode  
0
×
1
1
0
×
×
0
0
0
1
2-wire  
MSB P25  
(CMOS I/O)  
SB1/SDA1  
N-ch open-  
drain I/O  
SCK0/SCL  
N-ch open-  
drain I/O  
Note 3 Note 3  
serial I/O or  
2
I C bus mode  
1
1
1
0
0
×
×
0
1
2-wire  
MSB SB0/SDA0  
N-ch open-  
P26  
SCK0/SCL  
Note 3 Note 3  
serial I/O or  
(CMOS I/O) N-ch open-  
drain I/O  
2
I C bus mode  
drain I/O  
Note 4  
R/W  
WUP  
Wake-up Function Control  
0
1
Interrupt request signal generation with each serial transfer in any mode  
2
In I C bus mode, interrupt request signal is generated when the address data received after start condition  
detection (when CMDD = 1) matches data in slave address register (SVA).  
Note 5  
R
COI  
0
Slave Address Comparison Result Flag (See  
)
Slave address register (SVA) not equal to data in serial I/O shift register 0 (SIO0)  
Slave address register (SVA) equal to data in serial I/O shift register 0 (SIO0)  
1
R/W CSIE0 Serial Interface Channel 0 Operation Control  
0
1
Stops operation.  
Enables operation.  
Notes 1. Bit 6 (COI) is a read-only bit.  
2
2. In the I C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2.  
3. Can be used freely as a port.  
4. To use the wake-up function (WUP = 1), set the bit 5 (SIC) of the interrupt timing specify register (SINT)  
to 1. Do not execute an instruction that writes the serial I/O shift register 0 (SIO0) while WUP = 1.  
5. When CSIE0 = 0, COI is 0.  
Remark  
×
: Don’t care  
PM×× : Port mode register  
P×× : Port output latch  
372  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(b) Serial bus interface control register (SBIC)  
SBIC is set by a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SBIC to 00H.  
Symbol  
SBIC BSYE ACKD ACKE  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
R/WNote  
CMDD  
FF61H  
00H  
ACKT  
RELD CMDT RELT  
R/W  
RELT  
Use for stop condition output. When RELT = 1, SO0 latch is set to 1. After SO0 latch setting, automatically  
cleared to 0. Also cleared to 0 when CSIE0 = 0.  
R/W CMDT  
Use for start condition output. When CMDT = 1, SO0 latch is cleared to 0. After clearing SO0 latch,  
automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.  
R
RELD  
0
Stop Condition Detection  
Clear Conditions  
• When transfer start instruction is executed  
• If SIO0 and SVA values do not match in address reception  
• When CSIE0 = 0  
• When RESET input is applied  
1
Setting Condition  
• When stop condition is detected  
R
CMDD  
0
Start Condition Detection  
Clear Conditions  
• When transfer start instruction is executed  
• When stop condition is detected  
• When CSIE0 = 0  
• When RESET input is applied  
1
Setting Condition  
• When start condition is detected  
R/W ACKT  
SDA0 (SDA1) is set to low after the Set instruction execution (ACKT = 1) before the next SCL falling edge.  
Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared to 0 if CSIE =  
0 when a transfer by the serial interface is started.  
(continued)  
Note Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only bits.  
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, ACKT) are 0 when read after the data is set.  
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
373  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Note 1  
R/W ACKE  
0
Acknowledge Signal Automatic Output Control  
Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting  
Note 2  
data.  
1
Enabled.  
After completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of  
SCL clock (automatically output when ACKE = 1). However, not automatically cleared to 0 after  
acknowledge signal output. Used for reception when the 9-clock wait mode is selected.  
R
ACKD  
0
Acknowledge Detection  
Clear Conditions  
• When transfer start instruction is executed  
• When CSIE0 = 0  
• When RESET input is applied  
1
Set Conditions  
• When acknowledge signal is detected at the rising edge of SCL clock after completion of transfer  
2
Note 4  
R/W BSYE  
Control of N-ch Open-Drain Output for Transmission in I C Bus Mode  
Note 3  
0
1
Output enabled (transmission)  
Output disabled (reception)  
Notes 1. This setting must be performed prior to transfer start.  
2. In the 8-clock wait mode, use ACKT for output of the acknowledge signal after normal data reception.  
3. The busy mode can be released by the start of a serial interface transfer or reception of an address  
signal. However, the BSYE flag is not cleared.  
4. When using the wake-up function, be sure to set BSYE to 1.  
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)  
374  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(c) Interrupt timing specification register (SINT)  
SINT is set by the 1-bit or 8-bit memory manipulation instruction.  
RESET input sets SINT to 00H.  
Symbol  
SINT  
7
0
<6>  
<5>  
<4>  
<3>  
<2>  
1
0
Address After Reset R/W  
R/WNote1  
CLD SIC  
FF63H  
00H  
SVAM CLC WREL  
WAT1 WAT0  
Note 2  
R/W WAT1 WAT0  
Interrupt control by wait (See  
)
0
0
Interrupt service request is generated on rise of 8th SCK0 clock cycle (clock output is high  
impedance).  
0
1
1
0
Setting prohibited  
2
Used in I C bus mode (8-clock wait)  
Generates an interrupt service request on rise of 8th SCL clock cycle. (In case of master device,  
SCL pin is driven low after output of 8 clock cycles, to enter the wait state. In case of slave device,  
SCL pin is driven low after input of 8 clock cycles, to require the wait state.)  
2
1
1
Used in I C bus mode (9-clock wait)  
Generates an interrupt service request on rise of 9th SCL clock cycle. (In case of master device,  
SCL pin is driven low after output of 9 clock cycles, to enter the wait state. In case of slave device,  
SCL pin is driven low after input of 9 clock cycles, to require the wait state.)  
R/W WREL  
Wait release control  
0
1
Indicates that the wait state has been released.  
Releases the wait state. Automatically cleared to 0 after releasing the wait state. This bit is used to release  
the wait state set by means of WAT0 and WAT1.  
R/W  
CLC  
Clock level control  
2
0
1
Used in I C bus mode. In cases other than serial transfer, SCL pin output is driven low.  
2
Used in I C bus mode. In cases other than serial transfer, SCL pin output is set to high impedance. (Clock  
line is held high.) Used by master device to generate the start condition and stop condition signals.  
R/W SVAM  
SVA bits used as slave address  
Bits 0 to 7  
0
1
Bits 1 to 7  
Note 3  
R/W  
R
SIC  
0
INTCSAI0 interrupt source selection  
CSIIF0 is set to 1 after end of serial interface channel 0 transfer.  
1
CSIIF0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected.  
Note 4  
CLD  
SCL pin level (See  
Low level  
)
0
1
High level  
Notes 1. Bit 6 (CLD) is read-only.  
2
2. When the I C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT0 and WAT1, respectively.  
2
3. When using the wake-up function in I C mode, be sure to set SIC to 1.  
4. When CSIE0 = 0, CLD is 0.  
Remark SVA  
: Slave address register  
CSIIF0 : Interrupt request flag corresponding to INTCSI0  
CSIE0 : Bit 7 of serial operating mode register 0 (CSIM0)  
375  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(4) Various signals  
2
A list of signals in the I C bus mode is given in Table 17-4.  
2
Table 17-4. Signals in I C Bus Mode  
Signal name  
Description  
Definition :  
Function :  
Note 1  
Start condition  
SDA0 (SDA1) falling edge when SCL is high  
Indicates that serial communication starts and subsequent data are address data.  
Master  
Signaled by :  
Signaled when : CMDT is set.  
Affected flag(s) : CMDD (is set.)  
Note 1  
Stop condition  
Definition :  
Function :  
SDA0 (SDA1) rising edge when SCL is high  
Indicates end of serial transmission.  
Master  
Signaled by :  
Signaled when : RELT is set.  
Affected flag(s) : RELD (is set) and CMDD (is cleared)  
Acknowledge signal (ACK)  
Definition :  
Function :  
Low level of SDA0(SDA1) pin during one SCL clock cycle after serial reception  
Indicates completion of reception of 1 byte.  
Master or slave  
Signaled by :  
Signaled when : ACKT is set with ACKE = 1.  
Affected flag(s) : ACKD (is set.)  
Wait (WAIT)  
Definition :  
Function :  
Low-level signal output to SCL  
Indicates state in which serial reception is not possible.  
Slave  
Signaled by :  
Signaled when : WAT1, WAT0 = 1x.  
Affected flag(s) : None  
Serial Clock (SCL)  
Address (A6 to A0)  
Transfer direction (R/W)  
Data (D7 to D0)  
Definition :  
Function :  
Synchronization clock for output of various signals  
Serial communication synchronization signal.  
Master  
Signaled by :  
Signaled when : See Note 2 below.  
Affected flag(s) : CSIIF0. Also see Note 3 below.  
Definition :  
Function :  
7-bit data synchronized with SCL immediately after start condition signal  
Indicates address value for specification of slave on serial bus.  
Master  
Signaled by :  
Signaled when : See Note 2 below.  
Affected flag(s) : CSIIF0. Also see Note 3 below.  
Definition :  
Function :  
1-bit data output in synchronization with SCL after address output  
Indicates whether data transmission or reception is to be performed.  
Master  
Signaled by :  
Signaled when : See Note 2 below.  
Affected flag(s) : CSIIF0. Also see Note 3 below.  
Definition :  
Function :  
8-bit data synchronized with SCL, not immediately after start condition  
Contains data actually to be sent.  
Master or slave  
Signaled by :  
Signaled when : See Note 2 below.  
Affected flag(s) : CSIIF0. Also see Note 3 below.  
Notes 1. The level of the serial clock can be controlled by CLC of interrupt timing specify register (SINT).  
2. Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start directive). In the  
wait state, the serial transfer operation will be started after the wait state is released.  
3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle  
of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock  
cycle of SCL. CSIIF0 is set if an address is received and that address coincides with the value of  
the slave address register (SVA) when WUP = 1, or if the stop condition is detected.  
376  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(5) Pin configurations  
The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below.  
(a) SCL  
Pin for serial clock input/output dual-function pin.  
<1> Master ..... N-ch open-drain output  
<2> Slave ....... Schmitt input  
(b) SDA0 (SDA1)  
Serial data input/output dual-function pin.  
Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices.  
Note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because  
open-drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the  
2
I C bus.  
Figure 17-21. Pin Configuration  
Slave devices  
VDD  
Master device  
SCL  
SCL  
Clock output  
(Clock input)  
(Clock output)  
Clock input  
VDD  
SDA0(SDA1)  
SDA0(SDA1)  
Data output  
Data input  
Data output  
Data input  
Caution To receive data, the N-ch open-drain output must be set to high-impedance state. Therefore,  
set the bit 7 (BSYE) of the serial bus interface control register (SBIC) to 1 in advance, and  
write FFH to the serial I/O shift register 0 (SIO0).  
When the wake-up function is used (by setting the bit 5 (WUP) of the serial operating mode  
register 0 (CSIM0)), however, do not write FFH to SIO0 before reception. Even if FFH is not  
written to SIO0, the N-ch open-drain output is always in high-impedance state.  
(6) Address match detection method  
2
In the I C mode, the master can select a specific slave device by sending slave address data.  
CSIIF0 is set if the slave address transmitted by the master coincides with the value set to the slave address  
register (SVA) when a slave device address has a slave register (SVA), and the wake-up function specify bit  
(WUP) = 1 (CSIIF0 is also set when the stop condition is detected).  
When using the wake-up function, set SIC to 1.  
Caution Slave selection/non-selection is detected by matching of the data (address) received after  
start condition.  
For this match detection, match detection interrupt request (INTCSI0) of the address to be  
generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection  
by slave address when WUP = 1.  
377  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(7) Error detection  
2
In the I C bus mode, transmission error detection can be performed by the following methods because the  
serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0)  
register of the transmitting device.  
(a) Comparison of SIO0 data before and after transmission  
In this case, a transmission error is judged to have occurred if the two data values are different.  
(b) Using the slave address register (SVA)  
Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit (match  
signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1" indicates normal  
transmission, and "0" indicates a transmission error.  
(8) Communication operation  
2
In the I C bus mode, the master selects the slave device to be communicated with from among multiple  
devices by outputting address data onto the serial bus.  
After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and  
starts serial communication with the selected slave device.  
Data communication timing charts are shown in Figures 17-22 and 17-23.  
In the transmitting device, the serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in  
synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-  
first basis from the SDA0 or SDA1 pin to the receiving device.  
In the receiving device, the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchronization  
with the rising edge of SCL.  
(9) Start of transfer  
A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two  
conditions have been satisfied:  
• The serial interface channel 0 operation control bit (CSIE0) = 1.  
• After an 8-bit serial transfer, the internal serial clock is stopped or SCL is low.  
Cautions 1. Be sure to set CSIE0 to 1 before writing data in SIO0. Setting CSIE0 to 1 after writing data  
in SIO0 does not initiate transfer operation.  
2. Because the N-ch open-drain output must be high-impedance state during data reception,  
set bit 7 (BSYE) of serial bus interface control register (SBIC) to 1 before writing FFH to  
SIO0.  
Do not write FFH to SIO0 before reception when the wake-up function is used (by setting  
the bit 5 (WUP) of the serial operating mode register 0 (CSIM0)). Even if FFH is not written  
to SIO0, the N-ch open-drain output is always in high-impedance state.  
3. If data is written to SIO0 while the slave is in the wait state, that data is held. The transfer  
is started when SCL is output after the wait state is cleared.  
When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag  
(CSIIF0) is set.  
378  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-22. Data Transmission from Master to Slave  
(Both Master and Slave Selected 9-Clock Wait) (1 of 3)  
(a) Start Condition to Address  
Master device operation  
SIO0 Address  
SIO0 Data  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
L
P27  
H
L
L
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
L
WREL  
SIC  
INTCSI0  
Transfer line  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
A6 A5 A4 A3 A2 A1 A0 W ACK  
D7 D6 D5 D4 D3  
SDA0  
Slave device operation  
SIO0 FFH  
Write SIO0  
COI  
ACKD  
CMDD  
L
RELD  
CLD  
P27  
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
H
H
L
L
L
L
WREL  
SIC  
H
INTCSI0  
CSIE0  
H
L
P25  
PM25  
PM27  
L
L
379  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-22. Data Transmission from Master to Slave  
(Both Master and Slave Selected 9-Clock Wait) (2 of 3)  
(b) Data  
Master device operation  
SIO0 Address  
SIO0 Data  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
L
P27  
H
L
L
L
L
L
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
WREL  
SIC  
INTCSI0  
Transfer line  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
D7 D6 D5 D4 D3 D2 D1 D0 ACK  
D7 D6 D5 D4 D3  
SDA0  
Slave device operation  
SIO0 FFH  
SIO0 FFH  
Write SIO0  
COI  
ACKD  
CMDD  
L
RELD  
CLD  
P27  
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
H
H
L
L
L
L
WREL  
SIC  
H
INTCSI0  
CSIE0  
H
L
P25  
PM25  
PM27  
L
L
380  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-22. Data Transmission from Master to Slave  
(Both Master and Slave Selected 9-Clock Wait) (3 of 3)  
(c) Stop Condition  
Master device operation  
SIO0 Data  
SIO0 Address  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
L
P27  
H
L
L
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
WREL  
SIC  
INTCSI0  
Transfer line  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
D7 D6 D5 D4 D3 D2 D1 D0 ACK  
A6 A5 A4 A3  
SDA0  
Slave device operation  
SIO0 FFH  
SIO0 FFH  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
P27  
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
H
H
L
L
L
WREL  
SIC  
H
INTCSI0  
CSIE0  
P25  
PM25  
PM27  
L
381  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-23. Data Transmission from Slave to Master  
(Both Master and Slave Selected 9-Clock Wait) (1 of 3)  
(a) Start Condition to Address  
Master device operation  
SIO0 Address  
SIO0 FFH  
Write SIO0  
COI  
ACKD  
CMDD  
L
RELD  
CLD  
P27  
H
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
L
WREL  
SIC  
INTCSI0  
Transfer line  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
D7 D6 D5 D4 D3  
A6 A5 A4 A3 A2 A1 A0  
ACK  
SDA0  
R
Slave device operation  
SIO0 Data  
Write SIO0  
COI  
ACKD  
CMDD  
L
RELD  
CLD  
P27  
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
L
L
H
WREL  
SIC  
INTCSI0  
CSIE0  
H
L
P25  
PM25  
PM27  
L
L
382  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-23. Data Transmission from Slave to Master  
(Both Master and Slave Selected 9-Clock Wait) (2 of 3)  
(b) Data  
Master device operation  
SIO0 FFH  
SIO0 FFH  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
L
P27  
H
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
H
H
L
L
L
L
L
WREL  
SIC  
INTCSI0  
Transfer line  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
5
ACK  
D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3  
D7  
SDA0  
Slave device operation  
SIO0 Data  
SIO0 Data  
Write SIO0  
COI  
ACKD  
CMDD  
L
L
RELD  
CLD  
P27  
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
L
L
L
L
WREL  
SIC  
H
INTCSI0  
CSIE0  
H
L
P25  
PM25  
PM27  
L
L
383  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-23. Data Transmission from Slave to Master  
(Both Master and Slave Selected 9-Clock Wait) (3 of 3)  
(c) Stop Condition  
Master device operation  
SIO0 FFH  
SIO0 Address  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
L
P27  
H
L
WUP  
BSYE  
ACKE  
CMDT  
RELT  
CLC  
L
L
WREL  
SIC  
INTCSI0  
Transfer line  
SCL  
1
2
3
4
5
6
7
8
9
1
2
3
4
A6 A5 A4 A3  
D7  
D6 D5 D4 D3 D2 D1 D0  
SDA0  
NAK  
Slave device operation  
SIO0 Data  
Write SIO0  
COI  
ACKD  
CMDD  
RELD  
CLD  
P27  
WUP  
BSYE  
ACKE  
L
L
L
CMDT  
RELT  
CLC  
WREL  
SIC  
H
INTCSI0  
CSIE0  
H
L
P25  
PM25  
PM27  
L
L
384  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
2
17.4.5 Cautions on use of I C bus mode  
(1) Start condition output (master)  
The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change  
the SCL pin to high in order to output a start condition signal. Set 1 in CLC of interrupt timing specify  
register (SINT) to drive the SCL pin high.  
After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output.  
If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set  
to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state).  
Figure 17-24. Start Condition Output  
SCL  
SDA0(SDA1)  
CLC  
CMDT  
CLD  
385  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(2) Slave wait release (slave transmission)  
Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or  
execution of an serial I/O shift register 0 (SIO0) write instruction.  
If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the  
clock rises without the start transmission bit being output in the data line. Therefore, as shown in Figure 17-  
25, data should be transmitted by manipulating the P27 output latch through the program. At this time,  
control the low-level width ("a" in Figure 17-25) of the first serial clock at the timing used for setting the P27  
output latch to 1 after execution of an SIO0 write instruction.  
In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is  
completed), set 1 in the WREL flag of SINT and release the wait.  
For these timings, see Figure 17-23.  
Figure 17-25. Slave Wait Release (Transmission)  
Master device operation  
Writing  
FFH  
to SIO0  
Software operation  
Hardware operation  
Setting Setting  
ACKD CSIIF0  
Serial reception  
Transfer line  
SCL  
9
2
3
a
1
SDA0(SDA1)  
A0  
R
ACK  
D7  
D6  
D5  
Slave device operation  
Software operation  
P27  
output  
latch 0  
P27  
output  
latch 1  
Write  
data  
to SIO0  
ACK  
output  
Wait  
release  
Setting  
CSIIF0  
Hardware operation  
Serial transmission  
386  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(3) Slave wait release (slave reception)  
The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register  
(SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed.  
When the slave receives data, the first bit of the data sent from the master may not be received if the SCL  
line immediately goes into a high-impedance state after an instruction that writes data to SIO has been  
executed.  
This is because SIO0 does not start operating if the SCL line is in the high-impedance state while the  
instruction that writes data to SIO0 is executed (until the next instruction is executed).  
Therefore, receive the data by manipulating the output latch of P27 by program, as shown in Figure 17-26.  
For this timing, refer to Figure 17-22.  
Figure 17-26. Slave Wait Release (Reception)  
Master device operation  
Writing  
data to  
SIO0  
Software operation  
Hardware operation  
Setting Setting  
ACKD CSIIF0  
Serial transmission  
Transfer line  
SCL  
9
1
2
3
SDA0 (SDA1)  
A0  
W
ACK  
D7  
D6  
D5  
Slave device operation  
P27  
Write  
FFH  
P27  
output  
latch 1  
Software operation  
Hardware operation  
output  
latch 0 to SIO0  
ACK Setting  
Wait  
release  
Serial reception  
output  
CSIIF0  
387  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
(4) Reception completion of salve  
In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface  
control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1).  
This is to avoid the situation where the slave cannot judge which of the start condition and data comes first  
and therefore, the wake-up condition cannot be used when the slave receives the undefined number of data  
from the master.  
2
17.4.6 Restrictions in I C bus mode  
The following restrictions are applied to the µPD78054Y subseries.  
2
• Restrictions when used as slave device in I C bus mode  
Subject:  
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y, 78P058Y, IE-78064-R-EM,  
IE-780308-R-EM  
Description:  
If the wake-up function is executed (by setting the bit 5 of the serial operating mode  
Note  
register 0 (CSIM0) to 1) in the serial transfer status  
, the µPD78054Y subseries checks  
the address of the data between the other slave and master. If that data happens to  
coincide with the slave address of the µPD78054Y subseries, the µPD78054Y subseries  
takes part in communication, destroying the communication data.  
Note The serial transfer status is the status since data has been written to the serial  
I/O shift register 0 (SIO0) until the interrupt request flag (CSIIF0) is set to 1 by  
completion of the serial transfer.  
Preventive measure: The above phenomenon can be avoided by modifying the program.  
Before executing the wake-up function, execute the following program that clears the  
serial transfer status. When executing the wake-up function, do not execute an instruction  
that writes data to SIO0. Even if such an instruction is not executed, data can be received  
while the wake-up function is executed.  
This program releases the serial transfer status. To release the serial transfer status,  
the serial interface channel 0 must be once disabled (by clearing the CSIE0 flag (bit 7 of  
the serial operating mode register (CSIM0) to 0). If the serial interface channel 0 is  
2
disabled in the I C bus mode, however, the SCL pin outputs a high level, and SDA0  
2
(SDA1) pin outputs a low level, affecting communication of the I C bus. Therefore, this  
program makes the SCL and SDA0 (SDA1) pins go into a high-impedance state to prevent  
2
the I C bus from being affected.  
In this example, the SDA0 (/P25) pin is used as a serial data input/output pin. When the  
SDA1 (/P26) is used, take P2.5 and PM2.5 in the program example below as P2.6 and  
PM2.6.  
For the timing of each signal when this program is executed, refer to Figure 17-22.  
388  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
• Example of program releasing serial transfer status  
SET1 P2.5; <1>  
SET1 PM2.5; <2>  
SET1 PM2.7; <3>  
CLR1 CSIE0; <4>  
SET1 CSIE0; <5>  
SET1 RELT;  
CLR1 PM2.7; <7>  
CLR1 P2.5; <8>  
CLR1 PM2.5; <9>  
<6>  
2
<1> This instruction prevents the SDA0 pin from outputting a low level when the I C bus mode is restored  
by instruction <5>. The output of the SDA0 pin goes into a high-impedance state.  
<2> This instruction sets the P25 (/SDA0) pin in the input mode to protect the SDA0 line from adverse  
influence when the port mode is set by instruction <4>. The P25 pin is set in the input mode when  
instruction <2> is executed.  
<3> This instruction sets the P27 (/SCL) pin in the input mode to protect the SCL line from adverse influence  
when the port mode is set by instruction <4>. The P27 pin is set in the input mode when instruction  
<3> is executed.  
2
<4> This instruction changes the mode from I C bus mode to port mode.  
2
<5> This instruction restores the I C bus mode from the port mode.  
<6> This instruction prevents the SDA0 pin from outputting a low level when instruction <8> is executed.  
<7> This instruction sets the P27 pin in the output mode because the P27 pin must be in the output mode  
2
in the I C bus mode.  
<8> This instruction clears the output latch of the P25 pin to 0 because the output latch of the P25 pin  
2
must be set to 0 in the I C bus mode.  
<9> This instruction sets the P25 pin in the output mode because the P25 pin must be in the output mode  
2
in the I C bus mode.  
Remark RELT: Bit 0 of serial bus interface control register (SBIC)  
389  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
17.4.7 SCK0/SCL/P27 pin output manipulation  
The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock.  
The value of serial clocks can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are  
controlled with the RELT and CMDT bits of serial bus interface control register (SBIC)).  
The SCK0/SCL/P27 pin output should be manipulated as described below.  
(1) In 3-wire serial I/O mode and 2-wire serial I/O mode  
The output level of the SCK0/SCL/P27 pin is manipulated by the P27 output latch.  
<1> Set the serial operating mode register 0 (CSIM0) (SCK0 pin is set in the output mode and serial operation  
is enabled). SCK0 = 1 while serial transfer is stopped.  
<2> Manipulate the content of the P27 output latch by executing the bit manipulation instruction.  
Figure 17-27. SCK0/SCL/P27 Pin Configuration  
Manipulated by bit manipulation instruction  
SCK0/SCL/P27  
To internal logic  
P27  
output latch  
SCK0 (1 while transfer is stopped)  
From serial clock  
controller  
CSIE0 = 1 and CSIM01, CSIM00 are 1, 0 or 1, 1, respectively  
2
(2) In I C bus mode  
The output level of the SCK0/SCL/P27 pin is manipulated by the CLC bit of the interrupt timing specify  
register (SINT).  
<1> Set the serial operating mode register 0 (CSIM0) (SCL pin is set in the output mode and serial operation  
is enabled). Set 1 to the P27 output latch. SCL = 0 while serial transfer is stopped.  
<2> Manipulate the CLC bit of SINT by executing the bit manipulation instruction.  
Figure 17-28. SCK0/SCL/P27 Pin Configuration  
Set 1  
SCK0/SCL/P27  
To internal logic  
P27  
output latch  
SCLNote  
From serial clock  
controller  
CSIE0 = 1 and CSIM01 and CSIM00 are 1, 0 or 1, 1, respectively  
Note The level of the SCL signal is in accordance with the contents of the logic circuits shown in Figure  
17-29.  
390  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (µPD78054Y Subseries)  
Figure 17-29. Logic Circuit of SCL Signal  
CLC (manipulated by bit manipulation instruction)  
SCL  
Wait request signal  
Serial clock (low while transfer is stopped)  
Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit.  
2. CLC: Bit 3 of interrupt timing specify register (SINT)  
391  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
392  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
18.1 Serial Interface Channel 1 Functions  
Serial interface channel 1 employs the following three modes.  
• Operation stop mode  
• 3-wire serial I/O mode  
• 3-wire serial I/O mode with automatic transmit/receive function  
(1) Operation stop mode  
This mode is used when serial transfer is not carried out to reduce power consumption.  
(2) 3-wire serial I/O mode (MSB-/LSB-first switchable)  
This mode is used for 8-bit data transfer using three lines, each for serial clock (SCK1), serial output (SO1)  
and serial input (SI1).  
The 3-wire serial I/O mode enables simultaneous transmission/reception and so decreases the data transfer  
processing time.  
Since the start bit of 8-bit data to undergo serial transfer is switchable between MSB and LSB, connection  
is enabled with either start bit device.  
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which  
incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K series.  
(3) 3-wire serial I/O mode with automatic transmit/receive function (MSB-/LSB-first switchable)  
The mode of the same function as (2) 3-wire serial I/O mode added with the automatic transmit/receive  
function.  
The automatic transmit/receive function is used to transmit/receive data with a maximum of 32 bytes. This  
function enables the hardware to transmit/receive data to/from the OSD (On Screen Display) device and a  
device with built-in display controller/driver independently of the CPU, thus the software load can be alleviated.  
393  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
18.2 Serial Interface Channel 1 Configuration  
Serial interface channel 1 consists of the following hardware.  
Table 18-1. Serial Interface Channel 1 Configuration  
Item  
Register  
Configuration  
Serial I/O shift register 1 (SIO1)  
Automatic data transmit/receive address pointer (ADTP)  
Control register  
Timer clock select register 3 (TCL3)  
Serial operating mode register 1 (CSIM1)  
Automatic data transmit/receive control register (ADTC)  
Automatic data transmit/receive interval specify register (ADTI)  
Note  
Port mode register 2 (PM2)  
Note Refer to Figure 6-5, 6-7 Block Diagram of P20, P21, P23 to P26 and Figure 6-6, 6-8 Block Diagram  
of P22, P27.  
394  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-1. Serial Interface Channel 1 Block Diagram  
Internal Bus  
Automatic Data  
Transmit/Receive  
Address Pointer  
(ADTP)  
Buffer RAM  
Internal Bus  
Automatic Data  
Automatic Data  
ATE  
Transmit/Receive Interval  
Transmit/Receive  
Serial Operating  
Mode Register 1  
Specify Register  
Control Register  
DIR  
DIR  
CSIM CSIM  
ADTI ADTI ADTI ADTI ADTI ADTI  
BUSY BUSY  
RE ARLD ERCE ERR TRF STRB  
CSIE1 DIR ATE  
TRF  
1
0
11  
10  
7
4
3
2
1
0
Serial I/O  
Shift Register 1  
(SIO1)  
SI1/  
P20  
ADTI0-ADTI4  
Match  
PM21  
Selector  
SO1/  
P21  
P21 Output  
Latch  
5-Bit Counter  
PM23  
STB/  
P23  
Hand-  
shake  
BUSY/  
P24  
ARLD  
Serial Clock  
Counter  
INTCSI1  
SIOI write  
Clear  
fxx/2–fxx/28  
Selector  
4
SCK1/  
P22  
Selector  
R
Q
S
TO2  
TCL TCL TCL TCL  
37 36 35 34  
P22 Output Latch  
PM22  
Timer Clock  
Select Register 3  
Internal Bus  
395  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(1) Serial I/O shift register 1 (SIO1)  
This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception  
(shift operation) in synchronization with the serial clock.  
SIO1 is set with an 8-bit memory manipulation instruction.  
When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts  
serial operation.  
In transmission, data written to SIO1 is output to the serial output (SO1). In reception, data is read from the  
serial input (SI1) to SIO1.  
RESET input makes SIO1 undefined.  
Caution Do not write data to SIO1 while the automatic transmit/receive function is activated.  
(2) Automatic data transmit/receive address pointer (ADTP)  
This register stores value of (the number of transmit data bytes-1) while the automatic transmit/receive function  
is activated. As data is transferred/received, it is automatically decremented.  
ADTP is set with an 8-bit memory manipulation instruction. The high-order 3 bits must be set to 0.  
RESET input sets ADTP to 00H.  
Caution Do not write data to ADTP while the automatic transmit/receive function is activated.  
(3) Serial clock counter  
This counter counts the serial clocks to be output and input during transmission/reception to check whether  
8-bit data has been transmitted/received.  
396  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
18.3 Serial Interface Channel 1 Control Registers  
The following four types of registers are used to control serial interface channel 1.  
• Timer clock select register 3 (TCL3)  
• Serial operating mode register 1 (CSIM1)  
• Automatic data transmit/receive control register (ADTC)  
• Automatic data transmit/receive interval specify register (ADTI)  
(1) Timer clock select register 3 (TCL3)  
This register sets the serial clock of serial interface channel 1.  
TCL3 is set with an 8-bit memory manipulation instruction.  
RESET input sets TCL3 to 88H.  
Remark Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial  
interface channel 0.  
397  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-2. Timer Clock Select Register 3 Format  
Symbol  
7
6
5
4
3
2
1
0
Address After Reset R/W  
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H  
88H  
R/W  
Serial Interface Channel 1 Serial Clock Selection  
MCS = 1  
TCL37 TCL36 TCL35 TCL34  
MCS = 0  
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
fXX/2  
Setting prohibited  
f
f
f
f
f
f
f
f
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
X/29 (9.8 kHz)  
fXX/22  
fXX/23  
fXX/24  
fXX/25  
fXX/26  
fXX/27  
fXX/28  
f
f
f
f
f
f
f
X/22 (1.25 MHz)  
X/23 (625 kHz)  
X/24 (313 kHz)  
X/25 (156 kHz)  
X/26 (78.1 kHz)  
X/27 (39.1 kHz)  
X/28 (19.5 kHz)  
Other than above  
Setting prohibited  
Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand.  
Remarks 1. fXX  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
2. fX  
3. MCS : Bit 0 of oscillation mode selection register (OSMS)  
4. Figures in parentheses apply to operation with fX = 5.0 MHz  
398  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(2) Serial operating mode register 1 (CSIM1)  
This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic  
transmit/receive operation enable/stop.  
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM1 to 00H.  
Figure 18-3. Serial Operation Mode Register 1 Format  
Symbol  
CSIM1 CSIE1 DIR ATE  
<7>  
6
<5>  
4
0
3
0
2
0
1
0
Address After Reset R/W  
FF68H 00H R/W  
CSIM11 CSIM10  
CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection  
0
1
1
×
0
1
Clock externally input to SCK1 pinNote 1  
8-bit timer register 2 (TM2) output  
Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)  
ATE  
0
Serial Interface Channel 1 Operating Mode Selection  
3-wire serial I/O mode  
3-wire serial I/O mode with automatic transmit/receive  
function  
1
DIR  
0
Start Bit  
MSB  
SI1 Pin Function  
SO1 Pin Function  
SI1/P20  
(Input)  
SO1  
(CMOS output)  
1
LSB  
Shift Register Serial Clock Counter SI1/P20 Pin SO1/P21 Pin SCK1/P22  
CSIE1 CSIM11  
PM20 P20 PM21 P21 PM22 P22  
1 Operation Operation Control  
Function  
Function  
Pin Function  
Note 2 Note 2 Note 2  
Note 2 Note 2 Note 2  
Operation  
stop  
Clear  
P20 (CMOS P21 (CMOS P22 (CMOS  
input/output) input/output) input/output)  
0
1
×
×
×
×
×
×
×
SCK1  
(Input)  
0
1
×
Note 3 Note 3  
Operation  
enable  
Count  
SI1Note 3 SO1 (CMOS  
1
×
0
0
(input)  
output)  
operation  
SCK1  
(CMOS  
output)  
1
0
1
Notes 1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB)  
of the automatic data transmit/receive control register (ADTC) to 0, 0.  
2. Can be used freely as port function.  
3. Can be used as P20 (CMOS input/output) when only transmitter is used (clear bit 7 (RE) of ADTC to 0).  
Remark  
×
: Don't care  
PM×× : Port mode register  
P×× : Port output latch  
399  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(3) Automatic data transmit/receive control register (ADTC)  
This register sets automatic transmit/receive enable/disable, the operating mode, strobe output enable/  
disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive  
execution and error detection.  
ADTC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ADTC to 00H.  
Figure 18-4. Automatic Data Transmit/Receive Control Register Format  
Symbol  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
R/WNote 1  
ADTC  
RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H  
00H  
R/W  
BUSY1 BUSY0 Busy Input Control  
0
1
1
×
0
1
Not using busy input  
Busy input enable (active high)  
Busy input enable (active low)  
R/W  
STRB Strobe Output Control  
0
1
Strobe output disable  
Strobe output enable  
R
TRF  
0
Status of Automatic Transmit/Receive FunctionNote 2  
Detection of termination of automatic transmission/  
reception (This bit is set to 0 upon suspension of  
automatic transmission/reception or when ARLD = 0.)  
During automatic transmission/reception  
(This bit is set to 1 when data is written to SIO1.)  
1
R
ERR Error Detection of Automatic Transmit/Receive  
Function  
No error  
0
(This bit is set to 0 when data is written to SIO1)  
1
Error occurred  
R/W  
R/W  
R/W  
ERCE Error Check Control of Automatic Transmit/  
Receive Function  
0
1
Error check disable  
Error check enable (only when BUSY1 = 1)  
ARLD Operating Mode Selection of Automatic Transmit/  
Receive Function  
0
1
Single operating mode  
Repetitive operating mode  
RE  
Receive Control of Automatic Transmit/Receive  
Function  
0
1
Receive disable  
Receive enable  
Notes 1. Bits 3 and 4 (TRF and ERR) are Read-Only bits.  
2. The termination of automatic transmission/reception should be discriminated by using TRF, not CSIIF1  
(Interrupt request flag).  
Caution When an external clock input is selected with bit 1 (CSIM11) of the serial operating mode register  
1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0 (When an external clock is input, hand  
shake control cannot be performed).  
Remark ×: Don't care  
400  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(4) Automatic data transmit/receive interval specify register (ADTI)  
This register sets the automatic data transmit/receive function data transfer interval.  
ADTI is set by a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ADTI to 00H.  
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (1/4)  
Symbol  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI ADTI7  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
ADTI7 Data Transfer Interval Control  
0
1
No control of interval by ADTINote 1  
Control of interval by ADTI (ADTI0 to ADTI4)  
Data Transfer Interval Specification (fXX = 5.0 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote 2  
18.4 µ s + 0.5/fSCK  
31.2 µs + 0.5/fSCK  
44.0 µs + 0.5/fSCK  
MaximumNote 2  
20.0 µ s + 1.5/fSCK  
32.8 µs + 1.5/fSCK  
45.6 µs + 1.5/fSCK  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
µ
µ
56.8 s + 0.5/fSCK  
58.4 s + 1.5/fSCK  
69.6µs + 0.5/fSCK  
71.2 µ s + 1.5/fSCK  
µ
µ
82.4 s + 0.5/fSCK  
84.0 s + 1.5/fSCK  
95.2µs + 0.5/fSCK  
108.0µs + 0.5/fSCK  
120.8 µ s + 0.5/fSCK  
133.6µs + 0.5/fSCK  
146.4µs + 0.5/fSCK  
159.2µs + 0.5/fSCK  
172.0µs + 0.5/fSCK  
184.8µs + 0.5/fSCK  
197.6µs + 0.5/fSCK  
210.4µs + 0.5/fSCK  
96.8 µs + 1.5/fSCK  
109.6µs + 1.5/fSCK  
122.4µs + 1.5/fSCK  
135.2µs + 1.5/fSCK  
148.0µs + 1.5/fSCK  
160.8µs + 1.5/fSCK  
173.6µs + 1.5/fSCK  
186.4µs + 1.5/fSCK  
199.2µs + 1.5/fSCK  
212.0µs + 1.5/fSCK  
Notes 1. The interval is dependent only on CPU processing.  
2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are  
found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which  
is calculated by the following expressions is smaller than 2/fSCK, the minimum interval time is 2/fSCK.  
6
6
2
28  
fXX  
0.5  
fSCK  
2
36  
fXX  
1.5  
fSCK  
Minimum = (n+1) ×  
+
+
, Maximum = (n+1) ×  
+
+
fXX  
fXX  
Cautions 1. Do not write ADTI during operation of automatic data transmit/receive function.  
2. Bits 5 and 6 must be set to zero.  
3. To control the data transfer interval by means of automatic transmission/reception with  
ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
3. fSCK : Serial clock frequency  
401  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4)  
Symbol  
ADTI ADTI7  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
Data Transfer Interval Specification (fXX = 5.0 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote  
MaximumNote  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
223.2 µs + 0.5/fSCK  
236.0 µs + 0.5/fSCK  
248.8 µs + 0.5/fSCK  
261.6 µs + 0.5/fSCK  
274.4 µs + 0.5/fSCK  
287.2 µs + 0.5/fSCK  
300.0 µs + 0.5/fSCK  
312.8 µs + 0.5/fSCK  
325.6 µs + 0.5/fSCK  
338.4 µs + 0.5/fSCK  
351.2 µs + 0.5/fSCK  
364.0 µs + 0.5/fSCK  
376.8 µs + 0.5/fSCK  
389.6 µs + 0.5/fSCK  
402.4 µs + 0.5/fSCK  
415.2 µs + 0.5/fSCK  
224.8 µs + 1.5/fSCK  
237.6 µs + 1.5/fSCK  
250.4 µs + 1.5/fSCK  
263.2 µs + 1.5/fSCK  
276.0 µs + 1.5/fSCK  
288.8 µs + 1.5/fSCK  
301.6 µs + 1.5/fSCK  
314.4 µs + 1.5/fSCK  
327.2 µs + 1.5/fSCK  
340.0 µs + 1.5/fSCK  
352.8 µs + 1.5/fSCK  
365.6 µs + 1.5/fSCK  
378.4 µs + 1.5/fSCK  
391.2 µs + 1.5/fSCK  
404.0 µs + 1.5/fSCK  
416.8 µs + 1.5/fSCK  
Note The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum  
which is calculated by the following expressions is smaller than 2/fSCK, the minimum interval time  
is 2/fSCK.  
6
0.5  
fSCK  
2
28  
fXX  
Minimum = (n+1) ×  
+
+
+
+
fXX  
6
1.5  
fSCK  
2
36  
fXX  
Maximum = (n+1) ×  
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Zero must be set in bits 5 and 6.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
3. fSCK : Serial clock frequency  
402  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4)  
Symbol  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI ADTI7  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
ADTI7 Data Transfer Interval Control  
0
1
No control of interval by ADTINote 1  
Control of interval by ADTI (ADTI0 to ADTI4)  
Data Transfer Interval Specification (fXX = 2.5 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote 2  
MaximumNote 2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
36.8µs + 0.5/fSCK  
40.0 µs + 1.5/fSCK  
µ
µ
62.4 s + 0.5/fSCK  
65.6 s + 1.5/fSCK  
µ
µ
88.0 s + 0.5/fSCK  
91.2 s + 1.5/fSCK  
113.6 µs + 0.5/fSCK  
139.2 µs + 0.5/fSCK  
164.8 µs + 0.5/fSCK  
190.4 µs + 0.5/fSCK  
216.0 µs + 0.5/fSCK  
241.6 µs + 0.5/fSCK  
267.2 µs + 0.5/fSCK  
292.8 µs + 0.5/fSCK  
318.4 µs + 0.5/fSCK  
344.0 µs + 0.5/fSCK  
369.6 µs + 0.5/fSCK  
395.2 µs + 0.5/fSCK  
420.8 µs + 0.5/fSCK  
116.8 µs + 1.5/fSCK  
142.4 µs + 1.5/fSCK  
168.0 µs + 1.5/fSCK  
193.6 µs + 1.5/fSCK  
219.2 µs + 1.5/fSCK  
244.8 µs + 1.5/fSCK  
270.4 µs + 1.5/fSCK  
296.0 µs + 1.5/fSCK  
321.6 µs + 1.5/fSCK  
347.2 µs + 1.5/fSCK  
372.8 µs + 1.5/fSCK  
398.4 µs + 1.5/fSCK  
424.0 µs + 1.5/fSCK  
Notes 1. The interval is dependent only on CPU processing.  
2. The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a  
minimum which is calculated by the following expressions is smaller than 2/fSCK, the minimum  
interval time is 2/fSCK.  
6
2
28  
fXX  
0.5  
fSCK  
Minimum = (n+1) ×  
+
+
+
+
fXX  
6
2
36  
fXX  
1.5  
fSCK  
Maximum = (n+1) ×  
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Bits 5 and 6 must be set to zero.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX  
: Main system clock frequency (fX or fX/2)  
: Main system clock oscillation frequency  
2. fX  
3. fSCK : Serial clock frequency  
403  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4)  
Symbol  
ADTI ADTI7  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
Data Transfer Interval Specification (fXX = 2.5 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote  
MaximumNote  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
446.4 µs + 0.5/fSCK  
472.0 µs + 0.5/fSCK  
497.6 µs + 0.5/fSCK  
523.2µs + 0.5/fSCK  
449.6 µs + 1.5/fSCK  
475.2 µs + 1.5/fSCK  
µ
500.8 s + 1.5/fSCK  
526.4µs + 1.5/fSCK  
µ
548.8 s + 0.5/fSCK  
552.0 µs + 1.5/fSCK  
µ
574.4µs + 0.5/fSCK  
600.0µs + 0.5/fSCK  
625.6µs + 0.5/fSCK  
651.2µs + 0.5/fSCK  
676.8µs + 0.5/fSCK  
702.4µ s + 0.5/fSCK  
728.0µs + 0.5/fSCK  
577.6 s + 1.5/fSCK  
µ
603.2 s + 1.5/fSCK  
628.8µs + 1.5/fSCK  
654.4µs + 1.5/fSCK  
680.0µs + 1.5/fSCK  
705.6µs + 1.5/fSCK  
731.2µs + 1.5/fSCK  
756.8µs + 1.5/fSCK  
782.4µs + 1.5/fSCK  
µ
753.6 s + 0.5/fSCK  
779.2µs + 0.5/fSCK  
µ
µ
804.8 s + 0.5/fSCK  
808.0 s + 1.5/fSCK  
830.4µs + 0.5/fSCK  
833.6µs + 1.5/fSCK  
Note The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum  
which is calculated by the following expressions is smaller than 2/fSCK, the minimum interval time  
is 2/fSCK.  
6
0.5  
fSCK  
28  
fXX  
2
Minimum = (n+1) ×  
+
+
+
+
fXX  
6
1.5  
fSCK  
36  
fXX  
2
Maximum = (n+1) ×  
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Bits 5 and 6 must be set to zero.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX : Main system clock frequency (fX or fX/2)  
2. fX  
: Main system clock oscillation frequency  
3. fSCK : Serial clock frequency  
404  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
18.4 Serial Interface Channel 1 Operations  
The following three operating modes are available to the serial interface channel 1.  
• Operation stop mode  
• 3-wire serial I/O mode  
• 3-wire serial I/O mode with automatic transmit/receive function  
18.4.1 Operation stop mode  
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. The serial  
I/O shift register 1 (SIO1) does not carry out shift operation either, and thus it can be used as an ordinary 8-bit register.  
In the operation stop mode, the P20/SI1, P21/SO1, P22/SCK1, P23/STB and P24/BUSY pins can be used as  
ordinary input/output ports.  
(1) Register setting  
The operation stop mode is set with the serial operating mode register 1 (CSIM1).  
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM1 to 00H.  
Symbol  
<7>  
6
<5>  
4
0
3
0
2
0
1
0
Address After Reset R/W  
FF68H 00H R/W  
CSIM1 CSIE1 DIR ATE  
CSIM11 CSIM10  
Shift Register Serial Clock Counter SI1/P20 Pin SO1/P21 Pin SCK1/P22  
CSIE1 CSIM11  
PM20 P20 PM21 P21 PM22 P22  
1 Operation Operation Control  
Function  
Function  
Pin Function  
Note 1 Note 1 Note 1  
Note 1 Note 1 Note 1  
Operation  
stop  
Clear  
P20 (CMOS P21 (CMOS P22 (CMOS  
input/output) input/output) input/output)  
0
1
×
×
×
×
×
×
×
SCK1  
(Input)  
0
1
×
Note 2 Note 2  
Operation  
enable  
Count  
SI1Note 2 SO1 (CMOS  
1
×
0
0
(Input)  
output)  
operation  
SCK1  
(CMOS  
output)  
1
0
1
Notes 1. Can be used freely as port function.  
2. Can be used as P20 (CMOS input/output) when only transmitter is used (clear bit 7 (RE) of the  
automatic data transmit/receive control register (ADTC) to 0).  
Remark  
×
: Don't care  
PM×× : Port mode register  
P××  
: Port output latch  
405  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
18.4.2 3-wire serial I/O mode operation  
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate  
a conventional synchronous serial interface such as the 75X/XL, 78K and 17K series.  
Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1).  
(1) Register setting  
The 3-wire serial I/O mode is set with the serial operating mode register 1 (CSIM1).  
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM1 to 00H.  
Symbol  
<7>  
6
<5>  
4
0
3
0
2
0
1
0
Address After Reset R/W  
FF68H 00H R/W  
CSIM1 CSIE1 DIR ATE  
CSIM11 CSIM10  
CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection  
0
1
1
×
0
1
Clock externally input to SCK1 pinNote  
8-bit timer register 2 (TM2) output  
Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)  
ATE  
0
Serial Interface Channel 1 Operating Mode Selection  
3-wire serial I/O mode  
3-wire serial I/O mode with automatic transmit/receive function  
1
DIR  
0
Start Bit  
MSB  
SO1 Pin Function  
SO1 Pin Function  
SI1/P20  
(Input)  
SO1  
(CMOS output)  
1
LSB  
Note If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB)  
of the automatic data transmit/receive control register (ADTC) to 0, 0.  
Remark ×: Don't care  
Shift Register 1 Serial Clock Counter SI1/P20 Pin SO1/P21 Pin SCK1/P22  
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22  
Operation  
Operation Control  
Function  
Function  
Pin Function  
Note 1 Note 1 Note 1  
Note 1 Note 1 Note 1  
Operation  
stop  
Clear  
P20 (CMOS P21 (CMOS P22 (CMOS  
input/output) input/output) input/output)  
0
1
×
×
×
×
×
×
×
SCK1  
(Input)  
0
1
×
Note 2 Note 2  
Operation  
enable  
Count  
SI1Note 2 SO1 (CMOS  
1
×
0
0
(Input)  
output)  
operation  
SCK1  
(CMOS  
output)  
1
0
1
Notes 1. Can be used freely as port function.  
2. Can be used as P20 (CMOS input/output) when only transmitter is used (clear bit 7 (RE) of ADTC  
to 0).  
Remark  
×
: Don't care  
PM×× : Port mode register  
P××  
: Port output latch  
406  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(2) Communication operation  
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/  
reception is carried out in synchronization with the serial clock.  
Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1.  
The transmit data is held in the SO1 latch and is output from the SO1 pin. The receive data input to the SI1  
pin is latched into SIO1 at the rising edge of SCK1.  
Upon termination of 8-bit transfer, the SIO1 operation stops automatically and the interrupt request flag  
(CSIIF1) is set.  
Figure 18-6. 3-Wire Serial I/O Mode Timings  
SCK1  
SI1  
1
2
3
4
5
6
7
8
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SO1  
DO7  
DO6  
DO5  
DO4  
DO3  
DO2  
DO1  
DO0  
CSIIF1  
End of Transfer  
Transfer Start at the Falling Edge of SCK1  
SIO1 Write  
Caution SO1 pin becomes low level by SIO1 write.  
407  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(3) MSB/LSB switching as the start bit  
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.  
Figure 18-7 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the  
figure, MSB/LSB can be read/written in reverse form.  
MSB/LSB switching as the start bit can be specified with bit 6 (DIR) of the serial operating mode register 1  
(CSIM1).  
Figure 18-7. Circuit of Switching in Transfer Bit Order  
7
6
Internal Bus  
1
0
LSB-first  
MSB-first  
Read/Write Gate  
Read/Write Gate  
SO1 Latch  
SI1  
Serial IO Shift Register 1 (SIO1)  
D
Q
SO1  
SCK1  
Start bit switching is realized by switching the bit order for data write to SIO1. The SIO1 shift order remains  
unchanged.  
Thus, switching between MSB-first and LSB-first must be performed before writing data to the SIO1.  
(4) Transfer start  
Serial transfer is started by setting transfer data to the serial I/O shift register 1 (SIO1) when the following two  
conditions are satisfied.  
Serial interface channel 1 operation control bit (CSIE1) = 1  
Internal serial clock is stopped or SCK1 is a high level after 8-bit serial transfer.  
Caution If CSIE1 is set to "1" after data write to SIO1, transfer does not start.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF1)  
is set.  
408  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function  
This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of  
software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes,  
and data can be received and stored in the RAM by the set number of bytes.  
Handshake signals (STB and BUSY) are supported by hardware to transmit/receive data continuously. OSD (On  
Screen Display) LSI and peripheral LSI including LCD controller/driver can be connected without difficulty.  
(1) Register setting  
The 3-wire serial I/O mode with automatic transmit/receive function is set with the serial operating mode  
register 1 (CSIM1), the automatic data transmit/receive control register (ADTC) and the automatic data  
transmit/receive interval specify register (ADTI).  
(a) Serial operating mode register 1 (CSIM1)  
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM1 to 00H.  
409  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Symbol  
CSIM1 CSIE1 DIR ATE  
<7>  
6
<5>  
4
0
3
0
2
0
1
0
Address After Reset R/W  
FF68H 00H R/W  
CSIM11 CSIM10  
CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection  
0
1
1
×
0
1
Clock externally input to SCK1 pinNote 1  
8-bit timer register 2 (TM2) output  
Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)  
ATE  
0
Serial Interface Channel 1 Operating Mode Selection  
3-wire serial I/O mode  
1
3-wire serial I/O mode with automatic transmit/receive function  
DIR  
0
Start Bit  
MSB  
SI1 Pin Function  
SO1 Pin Function  
SI1/P20  
(Input)  
SO1  
(CMOS output)  
1
LSB  
Shift Register 1 Serial Clock Counter SI1/P20 Pin SO1/P21 Pin SCK1/P22  
PM20 P20 PM21 P21 PM22 P22  
CSIE1 CSIM11  
Operation  
Operation Control  
Function  
Function  
Pin Function  
Note 2 Note 2 Note 2  
Note 2 Note 2 Note 2  
Operation  
stop  
Clear  
P20 (CMOS P21 (CMOS P22 (CMOS  
input/output) input/output) input/output)  
0
1
×
×
×
×
×
×
×
SCK1  
(Input)  
0
1
×
Note 3 Note 3  
Operation  
enable  
Count  
SI1Note 3 SO1 (CMOS  
1
×
0
0
(Input)  
output)  
operation  
SCK1  
(CMOS  
output)  
1
0
1
Notes 1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY 1) and bit  
2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0.  
2. Can be used freely as port function.  
3. Can be used as P20 (CMOS input/output) when only transmitter is used (clear bit 7 (RE) of  
ADTC to 0).  
Remark  
×
: Don't care  
PM×× : Port mode register  
P×× : Port output latch  
410  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(b) Automatic data transmit/receive control register (ADTC)  
ADTC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ADTC to 00H.  
Symbol  
ADTC  
<7>  
<6>  
<5>  
<4>  
<3>  
<2>  
<1>  
<0>  
Address After Reset R/W  
R/WNote 1  
RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H  
00H  
R/W  
BUSY1 BUSY0 Busy Input Control  
0
1
1
×
0
1
Not using busy input  
Busy input enable (active high)  
Busy input enable (active low)  
R/W  
STRB Strobe Output Control  
0
1
Strobe output disable  
Strobe output enable  
R
TRF  
0
Status of Automatic Transmit/Receive FunctionNote 2  
Detection of termination of automatic transmission/  
reception (This bit is set to 0 upon suspension of  
automatic transmission/reception or when ARLD = 0.)  
During automatic transmission/reception  
(This bit is set to 1 when data is written to SIO1.)  
1
R
ERR Error Detection of Automatic Transmit/Receive  
Function  
No error  
0
(This bit is set to 0 when data is written to SIO1)  
1
Error occurred  
R/W  
R/W  
R/W  
ERCE Error Check Control of Automatic Transmit/  
Receive Function  
0
1
Error check disable  
Error check enable (only when BUSY1 = 1)  
ARLD Operating Mode Selection of Automatic Transmit/  
Receive Function  
0
1
Single operating mode  
Repetitive operating mode  
RE  
Receive Control of Automatic Transmit/Receive  
Function  
0
1
Receive disable  
Receive enable  
Notes 1. Bits 3 and 4 (TRF and ERR) are Read-Only bits.  
2. The termination of automatic transmission/reception should be discriminated by using TRF, not  
CSIIF1 (Interrupt request flag).  
Caution When an external clock input is selected with bit 1 (CSIM11) of the serial operating mode  
register 1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0 (handshake control  
cannot be executed when the external clock is input).  
Remark ×: Don't care  
411  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(c) Automatic data transmit/receive interval specify register (ADTI)  
This register sets the automatic data transmit/receive function data transfer interval.  
ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H.  
Symbol  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI ADTI7  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
ADTI7 Data Transfer Interval Control  
0
1
No control of interval by ADTINote 1  
Control of interval by ADTI (ADTI0 to ADTI4)  
Data Transfer Interval Specification (fXX = 5.0 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote 2  
MaximumNote 2  
20.0 µs + 1.5/fSCK  
32.8 µs + 1.5/fSCK  
45.6 µs + 1.5/fSCK  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
18.4 µs + 0.5/fSCK  
31.2 µs + 0.5/fSCK  
44.0 µs + 0.5/fSCK  
56.8µs + 0.5/fSCK  
69.6µs + 0.5/fSCK  
µ
58.4 s + 1.5/fSCK  
µ
71.2 s + 1.5/fSCK  
µ
µ
82.4 s + 0.5/fSCK  
84.0 s + 1.5/fSCK  
µ
95.2µs + 0.5/fSCK  
108.0µ s + 0.5/fSCK  
120.8µs + 0.5/fSCK  
133.6µs + 0.5/fSCK  
146.4µs + 0.5/fSCK  
159.2µs + 0.5/fSCK  
172.0µs + 0.5/fSCK  
184.8 µs + 0.5/fSCK  
197.6 µs + 0.5/fSCK  
210.4 µs + 0.5/fSCK  
96.8 s + 1.5/fSCK  
109.6µs + 1.5/fSCK  
122.4µs + 1.5/fSCK  
135.2µs + 1.5/fSCK  
148.0µs + 1.5/fSCK  
160.8µs + 1.5/fSCK  
173.6µs + 1.5/fSCK  
186.4µs + 1.5/fSCK  
199.2µs + 1.5/fSCK  
212.0µs + 1.5/fSCK  
Notes 1. The interval is dependent only on CPU processing.  
2. The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a  
minimum which is calculated by the following expressions is smaller than 2/fSCK, the minimum  
interval time is 2/fSCK.  
6
26  
fXX  
1.5  
fSCK  
36  
fXX  
0.5  
fSCK  
2
28  
fXX  
Minimum = (n+1) ×  
+
+
, Maximum = (n+1) ×  
+
+
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Zero must be set in bits 5 and 6.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX  
:
:
Main system clock frequency (fX or fX/2)  
Main system clock oscillation frequency  
2. fX  
3. fSCK : Serial clock frequency  
412  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Symbol  
ADTI ADTI7  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
Data Transfer Interval Specification (fXX = 5.0 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote  
MaximumNote  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
223.2 µs + 0.5/fSCK  
236.0 µs + 0.5/fSCK  
248.8 µs + 0.5/fSCK  
261.6 µs + 0.5/fSCK  
274.4 µs + 0.5/fSCK  
287.2 µs + 0.5/fSCK  
300.0 µs + 0.5/fSCK  
312.8 µs + 0.5/fSCK  
325.6 µs + 0.5/fSCK  
338.4 µs + 0.5/fSCK  
351.2 µs + 0.5/fSCK  
364.0 µs + 0.5/fSCK  
376.8 µs + 0.5/fSCK  
389.6 µs + 0.5/fSCK  
402.4 µs + 0.5/fSCK  
415.2 µs + 0.5/fSCK  
224.8 µs + 1.5/fSCK  
237.6 µs + 1.5/fSCK  
250.4 µs + 1.5/fSCK  
263.2 µs + 1.5/fSCK  
276.0 µs + 1.5/fSCK  
288.8 µs + 1.5/fSCK  
301.6 µs + 1.5/fSCK  
314.4 µs + 1.5/fSCK  
327.2 µs + 1.5/fSCK  
340.0 µs + 1.5/fSCK  
352.8 µs + 1.5/fSCK  
365.6 µs + 1.5/fSCK  
378.4 µs + 1.5/fSCK  
391.2 µs + 1.5/fSCK  
404.0 µs + 1.5/fSCK  
416.8 µs + 1.5/fSCK  
Note The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum  
which is calculated by the following expressions is smaller than 2/fSCK, the minimum interval time  
is 2/fSCK.  
6
0.5  
fSCK  
28  
fXX  
2
Minimum = (n+1) ×  
+
+
+
+
fXX  
6
36  
fXX  
1.5  
fSCK  
2
Maximum = (n+1) ×  
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Bits 5 and 6 must be set to zero.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX  
:
:
Main system clock frequency (fX or fX/2)  
Main system clock oscillation frequency  
2. fX  
3. fSCK : Serial clock frequency  
413  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Symbol  
ADTI ADTI7  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
ADTI7 Data Transfer Interval Control  
0
1
No control of interval by ADTINote 1  
Control of interval by ADTI (ADTI0 to ADTI4)  
Data Transfer Interval Specification (fXX = 2.5 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote 2  
36.8 µs + 0.5/fSCK  
62.4µs + 0.5/fSCK  
MaximumNote 2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
40.0 µs + 1.5/fSCK  
65.6µ s + 1.5/fSCK  
91.2µs + 1.5/fSCK  
116.8 µs + 1.5/fSCK  
142.4 µs + 1.5/fSCK  
168.0 µs + 1.5/fSCK  
193.6 µs + 1.5/fSCK  
219.2 µs + 1.5/fSCK  
244.8 µs + 1.5/fSCK  
270.4 µs + 1.5/fSCK  
296.0 µs + 1.5/fSCK  
321.6 µs + 1.5/fSCK  
347.2 µs + 1.5/fSCK  
372.8 µs + 1.5/fSCK  
398.4 µs + 1.5/fSCK  
424.0 µs + 1.5/fSCK  
µ
88.0 s + 0.5/fSCK  
113.6 µs + 0.5/fSCK  
139.2 µs + 0.5/fSCK  
164.8 µs + 0.5/fSCK  
190.4 µs + 0.5/fSCK  
216.0 µs + 0.5/fSCK  
241.6 µs + 0.5/fSCK  
267.2 µs + 0.5/fSCK  
292.8 µs + 0.5/fSCK  
318.4 µs + 0.5/fSCK  
344.0 µs + 0.5/fSCK  
369.6 µs + 0.5/fSCK  
395.2 µs + 0.5/fSCK  
420.8 µs + 0.5/fSCK  
Notes 1. The interval is dependent only on CPU processing.  
2. The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a  
minimum which is calculated by the following expressions is smaller than 2/fSCK, the minimum  
interval time is 2/fSCK.  
6
2
0.5  
fSCK  
28  
fXX  
Minimum = (n+1) ×  
+
+
+
+
fXX  
6
2
1.5  
fSCK  
36  
fXX  
Maximum = (n+1) ×  
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Bits 5 and 6 must be set to zero.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX  
2. fX  
:
:
:
Main system clock frequency (fX or fX/2)  
Main system clock oscillation frequency  
Serial clock frequency  
3. fSCK  
414  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Symbol  
ADTI ADTI7  
7
6
0
5
0
4
3
2
1
0
Address After Reset R/W  
FF6BH 00H R/W  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
Data Transfer Interval Specification (fXX = 2.5 MHz Operation)  
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0  
MinimumNote  
MaximumNote  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
446.4 µs + 0.5/fSCK  
472.0 µs + 0.5/fSCK  
497.6 µs + 0.5/fSCK  
449.6 µs + 1.5/fSCK  
475.2 µs + 1.5/fSCK  
500.8µs + 1.5/fSCK  
µ
µ
523.2 s + 0.5/fSCK  
526.4 s + 1.5/fSCK  
µ
548.8 s + 0.5/fSCK  
552.0 µs + 1.5/fSCK  
µ
µ
574.4 s + 0.5/fSCK  
577.6 s + 1.5/fSCK  
µ
600.0 s + 0.5/fSCK  
603.2µs + 1.5/fSCK  
µ
625.6µs + 0.5/fSCK  
651.2µs + 0.5/fSCK  
676.8µs + 0.5/fSCK  
702.4µs + 0.5/fSCK  
728.0µs + 0.5/fSCK  
753.6µs + 0.5/fSCK  
779.2µ s + 0.5/fSCK  
804.8µs + 0.5/fSCK  
628.8 s + 1.5/fSCK  
654.4µ s + 1.5/fSCK  
680.0µs + 1.5/fSCK  
µ
705.6 s + 1.5/fSCK  
731.2µs + 1.5/fSCK  
µ
756.8 s + 1.5/fSCK  
782.4µ s + 1.5/fSCK  
808.0µs + 1.5/fSCK  
833.6µ s + 1.5/fSCK  
µ
830.4 s + 0.5/fSCK  
Note The data transfer interval includes an error. The data transfer minimum and maximum intervals  
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum  
which is calculated by the following expressions is smaller than 2/fSCK, the minimum interval time  
is 2/fSCK.  
6
28  
fXX  
0.5  
fSCK  
2
Minimum = (n+1) ×  
+
+
+
+
fXX  
6
36  
fXX  
1.5  
fSCK  
2
Maximum = (n+1) ×  
fXX  
Cautions 1. Do not write data to ADTI during operation of automatic data transmit/receive  
function.  
2. Bits 5 and 6 must be set to zero.  
3. To control the data transfer interval by means of automatic transmission/reception  
with ADTI, busy control (refer to 18.4.3 (4) (a) Busy control option) is disabled.  
Remarks 1. fXX  
2. fX  
:
:
:
Main system clock frequency (fX or fX/2)  
Main system clock oscillation frequency  
Serial clock frequency  
3. fSCK  
415  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(2) Automatic transmit/receive data setting  
(a) Transmit data setting  
<1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at  
maximum). The transmit data should be in the order from high-order address to low-order address.  
<2> Set to the automatic data transmit/receive address pointer (ADTP) the value obtained by  
subtracting 1 from the number of transmit data bytes.  
(b) Automatic transmit/receive mode setting  
<1> Set bit 7 (CSIE1) to 1 and bit 5 (ATE) to 1 of the serial operating mode register 1 (CSIM1) to 1.  
<2> Set bit 7 (RE) of the automatic data transmit/receive control register (ADTC) to 1.  
<3> Set a data transmit/receive interval in the automatic data transmit/receive interval specify register  
(ADTI).  
<4> Write any value to the serial I/O shift register 1 (SIO1) (transfer start trigger).  
Caution Writing any value to SIO1 orders the start of automatic transmit/receive operation and  
the written value has no meaning.  
The following operations are automatically carried out when (a) and (b) are carried out.  
After the buffer RAM data specified with ADTP is transferred to SIO1, transmission is carried out (start  
of automatic transmission/reception).  
The received data is written to the buffer RAM address specified with ADTP.  
ADTP is decremented and the next data transmission/reception is carried out. Data transmission/  
reception continues until the ADTP decremental output becomes 00H and address FAC0H data is  
output (end of automatic transmission/reception).  
When automatic transmission/reception is terminated, bit 3 (TRF) of ADTC is cleared to 0.  
416  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(3) Communication operation  
(a) Basic transmission/reception mode  
This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number  
of data are transmitted/received in 8-bit units.  
Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1)  
of the serial operating mode register 1 (CSIM1) is set to 1.  
The interrupt request flag (CSIIF1) is set upon completion of transmission of the last byte. However, judge  
the completion of the automatic transmission/reception not with CSIIF1 but bit 3 (TRF) of the automatic  
data transmit/receive control register (ADTC).  
If busy control and strobe control are not executed, the P23/STB and P24/BUSY pins can be used as  
normal input/output ports.  
Figure 18-8 shows the basic transmission/reception mode operation timings, and Figure 18-9 shows the  
operation flowchart. Figure 18-10 shows the operation of the buffer RAM when 6 bytes of data are  
transmitted or received.  
Figure 18-8. Basic Transmission/Reception Mode Operation Timings  
Interval  
SCK1  
SO1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
SI1  
CSIIF1  
TRF  
Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/receive  
functionwrites/readsdatato/fromthebufferRAMafter1-bytetransmission/reception,  
an interval is inserted till the next transmission/reception. As the buffer RAM write/  
read is performed at the same time as CPU processing, the maximum interval is  
dependent upon CPU processing and the value of the automatic data transmit/  
receive interval specify register (ADTI) (see (5) "Automatic data transmit/receive  
interval").  
2. When TRF is cleared, the SO1 pin becomes low level.  
Remark CSIIF1 : Interrupt request flag  
TRF  
: Bit 3 of automatic data transmit/receive control register (ADTC)  
417  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-9. Basic Transmission/Reception Mode Flowchart  
Start  
Write transmit data  
in buffer RAM  
Set ADTP to the value (pointer  
value) obtained by subtracting 1  
from the number of transmit  
data bytes  
Software Execution  
Set the transmission/reception  
operation interval time in ADTI  
Write any data to SIO1  
(Start trigger)  
Write transmit data from  
buffer RAM to SIO1  
Transmission/reception  
operation  
Decrement pointer value  
Hardware Execution  
Write receive data from  
SIO1 to buffer RAM  
No  
No  
Pointer value = 0  
Yes  
TRF = 0  
Software Execution  
Yes  
End  
ADTP : Automatic data transmit/receive address pointer  
ADTI : Automatic data transmit/receive interval specify register  
SIO1 : Serial I/O shift register 1  
TRF : Bit 3 of automatic data transmit/receive control register (ADTC)  
418  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
In 6-byte transmission/reception (ARLD=0, RE=1) in basic transmit/receive mode, buffer RAM operates as follows.  
(i) Before transmission/reception (Refer to Figure 18-10 (a))  
After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not  
transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission  
of the first byte is completed, the receive data 1 (R1) is transferred from SIO1 to the buffer RAM, and  
automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2)  
is transferred from the buffer RAM to SIO1.  
(ii) 4th byte transmission/reception point (Refer to Figure 18-10 (b))  
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from  
the buffer RAM to SIO1. When transmission of the fourth byte is completed, the receive data 4 (R4)  
is transferred from SIO1 to the buffer RAM, and ADTP is decremented.  
(iii) Completion of transmission/reception (Refer to Figure 18-10 (c))  
When transmission of the sixth byte is completed, the receive data 6 (R6) is transferred from SIO1  
to the buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation).  
Figure 18-10. Buffer RAM Operation in 6-Byte Transmission/Reception  
(in Basic Transmit/Receive Mode) (1/2)  
(a) Before transmission/reception  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
Transmit data 3 (T3)  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
Transmit data 6 (T6)  
Receive data 1 (R1) SIO1  
5
0
ADTP  
–1  
FAC0H  
CSIIF1  
419  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-10. Buffer RAM Operation in 6-Byte Transmission/Reception  
(in Basic Transmit/Receive Mode) (2/2)  
(b) 4th byte transmission/reception  
FADFH  
FAC5H  
Receive data 1 (R1)  
Receive data 2 (R2)  
Receive data 3 (R3)  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
Transmit data 6 (T6)  
Receive data 4 (R4) SIO1  
2
0
ADTP  
–1  
FAC0H  
CSIIF1  
(c) Completion of transmission/reception  
FADFH  
FAC5H  
Receive data 1 (R1)  
SIO1  
Receive data 2 (R2)  
Receive data 3 (R3)  
Receive data 4 (R4)  
Receive data 5 (R5)  
Receive data 6 (R6)  
0
1
ADTP  
CSIIF1  
FAC0H  
420  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(b) Basic transmission mode  
In this mode, the specified number of 8-bit unit data are transmitted.  
Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1)  
of the serial operating mode register 1 (CSIM1) is set to 1.  
The interrupt request flag (CSIIF1) is set upon completion of transmission of the last byte. However, judge  
the completion of the automatic transmission/reception not with CSIIF1 but bit 3 (TRF) of the automatic  
data transmit/receive control register (ADTC).  
If receive operation, busy control and strobe control are not executed, the P20/SI1, P23/STB and P24/  
BUSY pins can be used as normal input/ports.  
Figure 18-11 shows the basic transmission mode operation timings, and Figure 18-12 shows the operation  
flowchart. Figure 18-13 shows the operation of the buffer RAM when 6 bytes of data are transmitted or  
received.  
Figure 18-11. Basic Transmission Mode Operation Timings  
Interval  
SCK1  
SO1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
CSIIF1  
TRF  
Cautions 1. Because, in the basic transmission mode, the automatic transmit/receive function  
reads data from the buffer RAM after 1-byte transmission, an interval is inserted till  
the next transmission. As the buffer RAM read is performed at the same time as CPU  
processing, the maximum interval is dependent upon CPU processing and the value  
of the automatic data transmit/receive interval specify register (ADTI) (see (5)  
"Automatic data transmit/receive interval").  
2. When TRF is cleared, the SO1 pin becomes low level.  
Remark CSIIF1 : Interrupt request flag  
TRF  
: Bit 3 of automatic data transmit/receive control register (ADTC)  
421  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-12. Basic Transmission Mode Flowchart  
Start  
Write transmit data  
in buffer RAM  
Set ADTP to the value (pointer  
value) obtained by subtracting 1  
from the number of transmit  
data bytes  
Software Execution  
Set the transmission/reception  
operation interval time in ADTI  
Write any data to SIO1  
(Start trigger)  
Write transmit data from  
buffer RAM to SIO1  
Decrement pointer value  
Transmission operation  
Hardware Execution  
No  
No  
Pointer value = 0  
Yes  
TRF = 0  
Software Execution  
Yes  
End  
ADTP : Automatic data transmit/receive address pointer  
ADTI : Automatic data transmit/receive interval specify register  
SIO1 : Serial I/O shift register 1  
TRF : Bit 3 of automatic data transmit/receive control register (ADTC)  
422  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, buffer RAM operates as follows.  
(i) Before transmission (Refer to Figure 18-13 (a))  
After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not  
transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission  
of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented.  
Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.  
(ii) 4th byte transmission point (Refer to Figure 18-13 (b))  
Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer  
RAM to SIO1. When transmission of the fourth byte is completed, ADTP is decremented.  
(iii) Completion of transmission (Refer to Figure 18-13 (c))  
When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is set (INTCSI1  
generation).  
Figure 18-13. Buffer RAM Operation in 6-Byte Transmission  
(in Basic Transmit Mode) (1/2)  
(a) Before transmission  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
Transmit data 3 (T3)  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
Transmit data 6 (T6)  
SIO1  
5
0
ADTP  
CSIIF1  
–1  
FAC0H  
423  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-13. Buffer RAM Operation in 6-Byte Transmission  
(in Basic Transmit Mode) (2/2)  
(b) 4th byte transmission point  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
SIO1  
Transmit data 3 (T3)  
2
ADTP  
CSIIF1  
Transmit data 4 (T4)  
–1  
Transmit data 5 (T5)  
FAC0H  
Transmit data 6 (T6)  
0
(c) Completion of transmission  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
Transmit data 3 (T3)  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
Transmit data 6 (T6)  
SIO1  
0
1
ADTP  
CSIIF1  
FAC0H  
424  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(c) Repeat transmission mode  
In this mode, data stored in the buffer RAM is transmitted repeatedly.  
Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1)  
of the serial operating mode register 1 (CSIM1).  
Unlike the basic transmission mode, after the last byte (data in address FAC0H) has been transmitted,  
the interrupt request flag (CSIIF1) is not set, the value at the time when the transmission was started is  
set in the automatic data transmit/receive address pointer (ADTP) again, and the buffer RAM contents  
are transmitted again.  
When a reception operation, busy control and strobe control are not performed, the P20/SI1, P23/STB  
and P24/BUSY pins can be used as ordinary input/output ports.  
The repeat transmission mode operation timing is shown in Figure 18-14, and the operation flowchart in  
Figure 18-15. Figure 18-16 shows the operation of the buffer RAM when 6 bytes of data are transmitted  
in the repeat transmission mode.  
Figure 18-14. Repeat Transmission Mode Operation Timing  
Interval  
Interval  
SCK1  
SO1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5  
Caution Since, in the repeat transmission mode, a read is performed on the buffer RAM after the  
transmissionofonebyte, theintervalisincludedintheperioduptothenexttransmission.  
As the buffer RAM read is performed at the same time as CPU processing, the maximum  
interval is dependent upon the CPU operation and the value of the automatic data  
transmit/receive interval specify register (ADTI) (see (5) "Automatic data transmit/  
receive interval").  
425  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-15. Repeat Transmission Mode Flowchart  
Start  
Write transmit data  
in buffer RAM  
Set ADTP to the value (pointer  
value) obtained by subtracting 1  
from the number of transmit  
data bytes  
Software Execution  
Set the transmission/reception  
operation interval time in ADTI  
Write any data to SIO1  
(Start trigger)  
Write transmit data from  
Decrement pointer value  
buffer RAM to SIO1  
Transmission operation  
Hardware Execution  
No  
Pointer value = 0  
Yes  
Reset ADTP  
ADTP : Automatic data transmit/receive address pointer  
ADTI : Automatic data transmit/receive interval specify register  
SIO1 : Serial I/O shift register 1  
426  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
In 6-byte transmission (ARLD=1, RE=0) in repeat transmit mode, buffer RAM operates as follows.  
(i) Before transmission (Refer to Figure 18-16 (a))  
After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not  
transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission  
of the first byte is completed, automatic data transmit/receive address pointer (ADTP) is decremented.  
Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.  
(ii) Upon completion of transmission of 6 bytes (Refer to Figure 18-16 (b))  
When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is not set. The  
first pointer value is set to ADTP again.  
(iii) 7th byte transmission point (Refer to Figure 18-16 (c))  
Transmit data 1 (T1) is transferred from the buffer RAM to SIO1 again. When transmission of the  
first byte is completed, ADTP is decremented. Then transmit data 2 (T2) is transferred from the buffer  
RAM to SIO1.  
Figure 18-16. Buffer RAM Operation in 6-Byte Transmission  
(in Repeat Transmit Mode) (1/2)  
(a) Before transmission  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
Transmit data 3 (T3)  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
Transmit data 6 (T6)  
SIO1  
5
0
ADTP  
CSIIF1  
–1  
FAC0H  
427  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-16. Buffer RAM Operation in 6-Byte Transmission  
(in Repeat Transmit Mode) (2/2)  
(b) Upon completion of transmission of 6 bytes  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
SIO1  
Transmit data 3 (T3)  
0
ADTP  
CSIIF1  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
FAC0H  
Transmit data 6 (T6)  
0
(c) 7th byte transmission point  
FADFH  
FAC5H  
Transmit data 1 (T1)  
Transmit data 2 (T2)  
Transmit data 3 (T3)  
Transmit data 4 (T4)  
Transmit data 5 (T5)  
Transmit data 6 (T6)  
SIO1  
5
ADTP  
CSIIF1  
–1  
FAC0H  
0
428  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(d) Automatic transmission/reception suspending and restart  
Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial  
operating mode register 1 (CSIM1) to 0.  
If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0. It  
is suspended upon completion of 8-bit data transfer.  
When suspended, bit 3 (TRF) of the automatic data transmit/receive control register (ADTC) is set to 0  
after transfer of the 8th bit, and all the port pins used with the serial interface pins for dual function (P20/  
SI1, P21/SO1, P22/SCK1, P23/STB and P24/BUSY) are set to the port mode.  
During restart of transmission/reception, remaining data can be transferred by setting CSIE1 to 1 and  
writing any data to the serial I/O shift register 1 (SIO1).  
Cautions 1. IftheHALTinstructionisexecutedduringautomatictransmission/reception, transfer  
is suspended and the HALT mode is set if during 8-bit data transfer. When the HALT  
mode is cleared, automatic transmission/reception is restarted from the suspended  
point.  
2. When suspending automatic transmission/reception, do not change the operating  
mode to 3-wire serial I/O mode while TRF = 1.  
Figure 18-17. Automatic Transmission/Reception Suspension and Restart  
Suspend  
CSIE1 = 0 (Suspended Command)  
Restart Command  
CSIE1 = 1, Write to SIO1  
SCK1  
SO1  
SI1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
Remark CSIE1 : Bit 7 of serial operating mode register 1 (CSIM1)  
429  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(4) Synchronization Control  
Busy control and strobe control are functions for synchronizing sending and receiving between the master  
device and slave device.  
By using these functions, it is possible to detect bit slippage during sending and receiving.  
(a) Busy control Option  
Busy control is a function which causes the master device’s serial transmission to wait when the slave  
device outputs a busy signal to the master device, and maintain the wait state while that busy signal is  
active.  
When the busy control option is used, the conditions shown below are necessary.  
• Bit 5 (ATE) of serial operation mode register 1 (CSIM1) should be set at (1).  
• Bit 1 (BUSY1) of the auto data send and receive control register (ADTC) should be set at (1).  
The system configuration between the master device and slave device in cases where the busy control  
option is used is shown in Figure 18-18.  
Figure 18-18. System Configuration When the Busy Control Option is Used  
Master Device  
(µPD78054, 78054Y Sub-series)  
Slave Device  
SCK1  
SCK1  
SO1  
SI1  
SO1  
SI1  
BUSY  
The master device inputs the busy signal output by the slave device to pin BUSY/P24. In sync with the  
fall of the serial clock, the master device samples the input busy signal. Even if the busy signal becomes  
active during sending or receiving of 8 bit data, the wait does not apply. If the busy signal becomes active  
at the rise of the serial clock 2 clock cycles after sending or receiving of 8 bit data ends, the busy input  
first becomes effective at that point, and thereafter, sending or receiving of data waits during the period  
that the busy signal is active.  
The busy signal’s active level is set in bit 0 (BUSY0) of ADTC.  
BUSY0 = 0: Active High  
BUSY0 = 1: Active Low  
430  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock.  
The busy signal cannot be controlled with an external clock.  
The operation timing when the busy control option is used is shown in Figure 18-19.  
Caution Busy control cannot be used at the same time as interval timing control using the auto  
datasendandreceiveintervalinstructionregister(ADTI). Ifbothareusedsimultaneously,  
busy control becomes invalid.  
Figure 18-19. Operation Timings when Using Busy Control Option (BUSY0 = 0)  
SCK1  
SO1  
SI1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
BUSY  
Wait  
CSIIF1  
Busy Input Clear  
Busy Input Valid  
TRF  
Caution When TRF is cleared, the SO1 pin becomes low level.  
Remark CSIIF1: Interrupt request flag  
TRF : Bit 3 of the auto data send and receive control register (ADTC)  
If the busy signal becomes inactive, the wait is canceled. If the sampled busy signal is inactive, sending  
or receiving of the next 8 bit data begins from the fall of the next serial clock cycle.  
Furthermore, the busy signal is asynchronous with the serial clock, so even if the slave side inactivates  
the busy signal, it takes nearly 1 clock cycle at the most until it is sampled again. Also, it takes another  
0.5 clock cycle after sampling until data transmission resumes.  
Therefore, in order to definitely cancel a wait state, it is necessary for the slave side to keep the busy  
signal for at least 1.5 clock cycles.  
Figure 18-20 shows the timing of the busy signal and wait cancel. In this figure, an example of the case  
where the busy signal becomes active when sending or receiving starts is shown.  
431  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-20. Busy Signal and Wait Cancel (when BUSY0 = 0)  
SCK1  
SO1  
SI1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
1.5 clocks (min.)  
BUSY  
In the case where the busy  
signal becomes inactive  
directly when sampled  
(Active High)  
Wait  
BUSY Input Cancel  
BUSY Input Effective  
(b) Busy & strobe control option  
Strobe control is a function for synchronizing the sending and receiving of data between a master device  
and slave device. When sending or receiving of 8 bit data ends, the strobe signal is output by the master  
device from pin STB/P23. Through this means, the slave device can know the timing of the end of master  
data transmission. Therefore, even if there is noise in the serial clock and bit slippage occurs,  
synchronization is maintained and bit slippage has no effect on transmission of the next byte.  
In the case that the strobe control option is used, the conditions shown below are necessary.  
• Set bit 5 (ATE) of serial operation mode register 1 (CSIM1) at (1).  
• Set bit 2 (STRB) of the auto data send and receive control register (ADTC) at (1).  
Normally, busy control and strobe control are used simultaneously as handshake signals. In this case,  
together with output of the strobe signal from pin STB/P23, pin BUSY/P24 can be sampled and sending  
or receiving can wait while the busy signal is being input.  
If strobe control is not carried out, pin P23/STB can be used as a normal I/O port.  
Operation timing when busy and strobe control are used is shown in Figure 18-21.  
Furthermore, if strobe control is used, the interrupt request flag (CSIIF1), set when sending or receiving  
ends, is set after the strobe signal is output.  
432  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
Figure 18-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0)  
SCK1  
SO1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
SI1  
STB  
BUSY  
CSIIF1  
Busy Input Clear  
Busy Input Valid  
TRF  
Caution When TRF is cleared, the SO1 pin becomes low level.  
Remarks CSIIF1: Interrupt request flag  
TRF : Bit 3 of the auto data send and receive control register (ADTC)  
433  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(c) Bit Slippage Detection Function Through the Busy Signal  
During an auto send and receive operation, noise occur in the serial clock signal output by the master  
device and bit slippage may occur in the slave device side serial clock. At this time, if the strobe control  
option is not used, this bit slippage will have an effect on sending of the next byte. In such a case, the  
busy control option can be used on the master device side and, by checking the busy signal during sending,  
bit slippage can be detected.  
Bit slippage detection through the busy signal is accomplished as follows.  
The slave side outputs a busy signal after the serial clock rises on the 8th cycle of data sending or receiving  
(at this time, if application of the wait state by the busy signal is not desired, the busy signal is made inactive  
within 2 clock cycles).  
The master device side samples the busy signal in sync with the fall of the serial clock’s front side. If  
no bit slippage is occurring, the busy signal will be inactive in sampling for 8 clock cycles. If the busy  
signal is found to be active in sampling, it is regarded as an occurrence of bit slippage error processing  
is executed (bit 4 (ERR) of the auto data send and receive control register (ADTC) is set at (1)).  
The operation timing of the bit slippage detection function through the busy signal is shown in Figure 18-  
22.  
Figure 18-22. Operation Timing of the Bit Slippage Detection Function Through the Busy SIgnal  
(when BUSY0 = 1)  
SCK1  
(Master Side)  
Bit Slippage Due to Noise  
SCK1  
(Slave Side)  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7  
D7  
D7 D6 D5 D4 D3 D2 D1  
D0  
D0  
SO1  
SI1  
D7 D6 D5 D4 D3 D2 D1  
BUSY  
CSIIF1  
CSIE1  
ERR  
Error Interrupt  
Request Generation  
Error Detection  
No Busy Detection  
Remark CSIIF1 : Interrupt Request Flag  
CSIE1 : Bit 7 of serial operation mode register 1 (CSIM1)  
ERR : Bit 4 of the auto data send and receive control register (ADTC)  
434  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(5) Automatic transmit/receive interval time  
When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are  
performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/  
receive.  
Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when  
using the automatic transmit/receive function by the internal clock, the interval depends on the value which  
is set in the automatic transmit/receive interval specification register (ADTI) and the CPU processing at the  
rising edge of the eighth serial clock. Whether it depends on the ADTI or not can be selected by the setting  
of its bit 7 (ADTI7). When it is set to 0, the interval depends only on the CPU processing. When it is set to  
1, the interval depends on the contents of the ADTI or CPU processing, whichever is greater.  
When the automatic transmit/receive function is used by an external clock, it must be selected so that the  
interval may be longer than the value indicated by paragraph (b).  
Figure 18-23. Automatic Data Transmit/Receive Interval  
Interval  
SCK1  
SO1  
SI1  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
D7 D6 D5 D4 D3 D2 D1 D0  
CSIIF1  
Remark CSIIF1: Interrupt request flag  
435  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(a) When the automatic transmit/receive function is used by the internal clock  
If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates.  
If the auto send and receive function is operated by the internal clock, interval timing by CPU processing  
is as follows.  
When bit 7 (ADTI7) of automatic data transmit/receive interval specify register (ADTI) is set to 0, the  
interval depends on the CPU processing. When ADTI7 is set to 1, it depends on the contents of the ADTI  
or CPU processing, whichever is greater.  
Refer to Figure 18-5, “Automatic Data Transmit/Receive Interval Specify Register Format” for the intervals  
which are set by the ADTI.  
Table 18-2. Interval Timing Through CPU Processing (when the internal clock is operating)  
CPU Processing  
When using multiplication instruction  
When using division instruction  
External access 1 wait mode  
Other than above  
Interval Time  
Max. (2.5TSCK, 13TCPU)  
Max. (2.5TSCK, 20TCPU)  
Max. (2.5TSCK, 9TCPU)  
Max. (2.5TSCK, 7TCPU)  
Remark TSCK  
: 1/fSCK  
fSCK  
TCPU  
fCPU  
: Serial clock frequency  
: 1/fCPU  
: CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control  
register (PCC) and bit 0 (MCS) of the oscillation mode selection register (OSMS))  
MAX. (a, b) : a or b, whichever is greater  
Figure 18-24. Operation Timing with Automatic Data Transmit/Receive Function Performed by  
Internal Clock  
f
X
TCPU  
fCPU  
TSCK  
Interval  
SCK1  
SO1  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
SI1  
fX  
: Main system clock oscillation frequency  
fCPU : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) and  
bit 0 (MCS) of the oscillation mode select register (OSMS).  
TCPU : 1/fCPU  
TSCK : 1/fSCK  
fSCK : Serial clock frequency  
436  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 18 SERIAL INTERFACE CHANNEL 1  
(b) When the automatic transmit/receive function is used by the external clock  
If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is  
set.  
When the automatic transmit/receive function is used by the external clock, it must be selected so that  
the interval may be longer than the values shown as follows.  
Table 18-3. Interval Timing Through CPU Processing (when the external clock is operating)  
CPU Processing  
When using multiplication instruction  
When using division instruction  
External access 1 wait mode  
Other than above  
Interval Time  
13TCPU  
20TCPU  
9TCPU  
7TCPU  
Remark TCPU : 1/fCPU  
fCPU : CPU clock (set by the bits 0 to 2 (PCC0 to PCC2) of the processor clock control register  
(PCC) and bit 0 (MCS) of the oscillation mode selection register (OSMS))  
437  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
438  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.1 Serial Interface Channel 2 Functions  
Serial interface channel 2 has the following three modes.  
• Operation stop mode  
• Asynchronous serial interface (UART) mode  
• 3-wire serial I/O mode  
(1) Operation stop mode  
This mode is used when serial transfer is not carried out to reduce power consumption.  
(2) Asynchronous serial interface (UART) mode  
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is  
possible.  
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud  
rates. In addition, the baud rate can be defined also by scaling the input clock to the ASCK pin.  
The MIDI standard baud rate (31.25 kbps) can also be used by employing the dedicated UART baud rate  
generator.  
(3) 3-wire serial I/O mode (MSB-/LSB-first switchable)  
In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines  
(SI2, SO2).  
In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer  
processing speed.  
Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection  
to devices using either as the start bit.  
The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which  
incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K  
series, etc.  
Caution In the 3-wire serial I/O mode of serial interface channel 2, only the output of the internal  
baud rate generator can be used for the operation clock. It is not possible to input a clock  
to pin SCK2 from external.  
439  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.2 Serial Interface Channel 2 Configuration  
Serial interface channel 2 consists of the following hardware.  
Table 19-1. Serial Interface Channel 2 Configuration  
Item  
Register  
Configuration  
Transmit shift register (TXS)  
Receive shift register (RXS)  
Receive buffer register (RXB)  
Control register  
Serial operating mode register 2 (CSIM2)  
Asynchronous serial interface mode register (ASIM)  
Asynchronous serial interface status register (ASIS)  
Note  
Baud rate generator control register (BRGC)  
Note Refer to Figure 6-15 Block Diagram of P70 and Figure 6-16 Block Diagram of P71, P72.  
440  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
Figure 19-1. Serial Interface Channel 2 Block Diagram  
Internal Bus  
Asynchronous  
Serial Interface  
Mode Register  
Asynchronous  
Serial Interface  
Status Register  
Direction  
Control Circuit  
Receive Buffer  
Register  
PE FE OVE  
TXE RXE PS1 PS0 CL  
SL ISRM SCK  
(RXB/SIO2)  
Transmit Shift  
Register  
(TXS/SIO2)  
Direction  
Control Circuit  
Receive Shift  
Register (RXS)  
RxD/SI2/  
P70  
TxD/SO2/  
P71  
PM71  
SCK Output  
Control Circuit  
INTSER  
Reception  
Control  
Circuit  
Transmission  
Control  
Circuit  
INTSR/INTCSI2  
ISRM  
INTST  
PM72  
ASCK/  
SCK2/P72  
Note  
Baud Rate Generator  
fxx-fxx/210  
SCK  
CSIE2  
4
4
TXE  
RXE  
CSIM  
22  
CSIE2  
CSCK  
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0  
Serial Operating  
Mode Register 2  
Baud Rate Generator  
Control Register  
Internal Bus  
Note See Figure 19-2 for the baud rate generator configuration.  
441  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
Figure 19-2. Baud Rate Generator Block Diagram  
CSIE2  
TXE  
Start Bit  
Sampling Clock  
5-Bit  
Counter  
ASCK/SCK2/P72  
fxx-fxx/210  
Transmit  
Clock  
1/2  
Selector  
4
Match  
TPS0-TPS3  
SCK  
MDL0-MDL3  
Decoder  
4
Receive  
Clock  
Match  
1/2  
5-Bit  
Counter  
4
RXE  
Start Bit Detection  
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0  
Baud Rate Generator  
Control Register  
Internal Bus  
442  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(1) Transmit shift register (TXS)  
This register is used to set the transmit data. The data written in TXS is transmitted as serial data.  
If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.  
Writing data to TXS starts the transmit operation.  
TXS is written to with an 8-bit memory manipulation instruction. It cannot be read.  
TXS value is FFH after RESET input.  
Caution Do not write a data to TXS during a transmit operation. TXS and the receive buffer register  
(RXB) are allocated to the same address, and when a read is performed, the value of RXB  
is read.  
(2) Receive shift register (RXS)  
This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is  
received, the receive data is transferred to the receive buffer register (RXB).  
RXS cannot be directly manipulated by a program.  
(3) Receive buffer register (RXB)  
This register holds receive data. Each time one byte of data is received, new receive data is transferred from  
the receive shift register (RXS).  
If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of  
RXB is always set to 0.  
RXB is read with an 8-bit memory manipulation instruction. It cannot be written to.  
RXB value is FFH after RESET input.  
Caution Since RXB and the transmit shift register (TXS) are allocated to the same address, even if  
a write instruction to RXB is executed, the value is written to TXS.  
(4) Transmission control circuit  
This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data  
written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial  
interface mode register (ASIM).  
(5) Reception control circuit  
This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface  
mode register (ASIM). It also checks errors such as parity error during a receive operation, and if an error  
is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with the  
error contents.  
443  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.3 Serial Interface Channel 2 Control Registers  
Serial interface channel 2 is controlled by the following four registers.  
• Serial Operating Mode Register 2 (CSIM2)  
• Asynchronous Serial Interface Mode Register (ASIM)  
• Asynchronous Serial Interface Status Register (ASIS)  
• Baud Rate Generator Control Register (BRGC)  
(1) Serial operating mode register 2 (CSIM2)  
This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.  
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM2 to 00H.  
Figure 19-3. Serial Operating Mode Register 2 Format  
Symbol  
<7>  
6
0
5
0
4
0
3
0
2
1
0
0
Address After Reset R/W  
FF72H 00H R/W  
CSIM  
22  
CSIM2 CSIE2  
CSCK  
CSCK Selection of Serial Operating mode  
0
1
UART mode  
3-wire serial I/O mode  
CSIM22 First Bit Specification  
0
1
MSB  
LSB  
CSIE2 Operation Control in 3-wire Serial I/O Mode  
0
1
Operation stopped  
Operation enabled  
Cautions 1. Ensure that bits 0 and 3 to 6 are set to 0.  
2. When UART mode is selected, CSIM2 should be set to 00H.  
444  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(2) Asynchronous serial interface mode register (ASIM)  
This register is set when serial interface channel 2 is used in the asynchronous serial interface mode.  
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ASIM to 00H.  
Figure 19-4. Asynchronous Serial Interface Mode Register Format  
Symbol  
<7>  
<6>  
5
4
3
2
1
0
Address After Reset R/W  
FF70H 00H R/W  
ASIM TXE RXE PS1 PS0  
CL  
SL ISRM SCK  
SCK Clock Selection in Asynchronous Serial Interface  
Mode  
0
1
Input clock from off-chip to ASCK pin  
Dedicated baud rate generator outputNote  
ISRM Control of Reception Completion Interrupt Request  
in Case of Error Generation  
Reception completion interrupt request generated  
in case of error generation  
0
Reception completion interrupt request not  
generated in case of error generation  
1
SL  
0
Transmit Data Stop Bit Length Specification  
1 bit  
1
2 bits  
CL  
0
Character Length Specification  
7 bits  
8 bits  
1
PS1  
0
PS0 Parity Bit Specification  
0
No Parity  
0 parity always added in transmission  
No parity test in reception (parity error not  
generated)  
0
1
1
1
0
1
Odd parity  
Even parity  
RXE Receive Operation Control  
0
1
Receive operation stopped  
Receive operation enabled  
TXE Transmit Operation Control  
0
1
Transmit operation stopped  
Transmit operation enabled  
Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as  
an input/output port.  
Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.  
2. The serial transmit/receive operation must be stopped before changing the operating  
mode.  
445  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
Table 19-2. Serial Interface Channel 2 Operating Mode Settings  
(1) Operation Stop Mode  
ASIM  
CSIM2  
P71 PM72  
PM70 P70 PM71 P72 Start Shift  
P72/SCK2  
/ASCK Pin  
Functions  
P70/SI2  
/RxD Pin /TxD Pin  
Functions Functions  
P71/SO2  
Bit  
Clock  
TXE RXE SCK CSIE2  
CSCK  
CSIM22  
Note1  
×
Note1  
×
Note1  
×
Note1  
×
Note1  
×
Note1  
×
0
0
×
0
×
×
P70  
P71  
P72  
Other than above  
Setting prohibited  
(2) 3-wire Serial I/O Mode  
ASIM  
CSIM2  
P71 PM72  
PM70 P70 PM71  
P72 Start Shift  
Bit Clock  
P72/SCK2  
/ASCK Pin  
Functions  
P70/SI2  
/RxD Pin /TxD Pin  
Functions Functions  
SI2Note2  
P71/SO2  
TXE RXE SCK CSIE2  
CSCK  
1
CSIM22  
Note2  
1Note2  
×
1
MSB Internal  
clock  
SO2  
(CMOS  
output)  
SCK2 output  
1
0
0
0
0
1
0
1
0
1
1
LSB  
SI2 Note2  
SO2  
(CMOS  
output)  
Other than above  
Setting prohibited  
(3) Asynchronous Serial Interface Mode  
ASIM  
CSIM2  
P71 PM72  
PM70 P70 PM71  
P72 Start Shift  
Bit Clock  
P72/SCK2  
/ASCK Pin  
Functions  
P70/SI2  
/RxD Pin /TxD Pin  
Functions Functions  
P71/SO2  
TXE RXE SCK CSIE2  
CSCK  
0
CSIM22  
Note1  
×
Note1  
×
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
×
LSB External  
clock  
TxD  
P70  
ASCK input  
0
(CMOS  
output)  
Note1  
Note  
1
1
1
Internal  
clock  
P72  
×
×
Note1  
Note  
1
1
0
0
×
External  
clock  
ASCK input  
P72  
1
1
×
×
×
×
RxD  
P71  
Note  
1
Note  
Internal  
clock  
×
×
TxD  
(CMOS  
output)  
External  
clock  
ASCK input  
P72  
0
1
1
×
Note  
1
Note  
Internal  
clock  
×
×
Other than above  
Setting prohibited  
Notes 1. Can be used freely as port function.  
2. Can be used as P70 (CMOS input/output) when only transmitter is used.  
Remark  
×
: Don't care  
PM×× : Port mode register  
P×× : Port output latch  
446  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(3) Asynchronous serial interface status register (ASIS)  
This is a register which displays the type of error when a reception error is generated in the asynchronous  
serial interface mode.  
ASIS is read with a 8-bit memory manipulation instruction.  
In 3-wire serial I/O mode, the contents of the ASIS are undefined.  
RESET input sets ASIS to 00H.  
Figure 19-5. Asynchronous Serial Interface Status Register Format  
Symbol  
ASIS  
7
0
6
0
5
0
4
0
3
0
2
1
0
Address After Reset R/W  
FF71H 00H  
PE  
FE  
OVE  
R
OVE Overrun Error Flag  
0
Overrun error not generated  
Overrun error generatedNote 1  
(When next receive operation is completed before  
data from receive buffer register is read)  
1
FE  
0
Framing Error Flag  
Framing error not generated  
Framing error generatedNote 2  
(When stop bit is not detected)  
1
PE  
0
Parity Error Flag  
Parity error not generated  
Parity error generated (When transmit data parity  
does not match)  
1
Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors  
will continue to be generated until RXB is read.  
2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface  
mode register (ASIM), only single stop bit detection is performed during reception.  
447  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(4) Baud rate generator control register (BRGC)  
This register sets the serial clock for serial interface channel 2.  
BRGC is set with an 8-bit memory manipulation instruction.  
RESET input sets BRGC to 00H.  
Figure 19-6. Baud Rate Generator Control Register Format (1/2)  
Symbol  
7
6
5
4
3
2
1
0
Address After Reset R/W  
FF73H 00H R/W  
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0  
MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection  
k
fSCK/16  
fSCK/17  
fSCK/18  
fSCK/19  
fSCK/20  
fSCK/21  
fSCK/22  
fSCK/23  
fSCK/24  
fSCK/25  
fSCK/26  
fSCK/27  
fSCK/28  
fSCK/29  
fSCK/30  
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Note  
fSCK  
Note Can only be used in 3-wire serial I/O mode.  
Remarks 1. fSCK : 5-bit counter source clock  
2. k  
: Value set in MDL0 to MDL3 (0 k 14)  
448  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
Figure 19-6. Baud Rate Generator Control Register Format (2/2)  
5-Bit Counter Source Clock Selection  
TPS3 TPS2 TPS1 TPS0  
n
MCS = 1  
MCS = 0  
10  
10  
11  
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
fXX/2  
fXX  
fXX/2  
(4.9 kHz)  
(5.0 MHz)  
(2.5 MHz)  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
fX/2  
(2.4 kHz)  
(2.5 MHz)  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
(4.9 kHz)  
11  
1
fX  
fX/2  
2
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fX/2  
fX/2  
2
2
3
4
5
6
7
8
9
2
3
fX/2  
fX/2  
3
3
4
fX/2  
fX/2  
4
4
5
fX/2  
fX/2  
5
5
6
fX/2  
fX/2  
6
6
7
fX/2  
fX/2  
7
7
8
fX/2  
fX/2  
8
8
9
fX/2  
fX/2  
9
9
10  
fX/2  
fX/2  
10  
Other than above  
Setting prohibited  
Caution When data is written to BRGC during a communication operation, baud rate generator output  
is disrupted and communication cannot be performed normally. Therefore, data must not  
be written to BRGC during a communication operation.  
Remarks 1. fX  
:
:
Main system clock oscillation frequency  
Main system clock frequency (fX or fX/2)  
2. fXX  
3. MCS : Oscillation mode selection register (OSMS) bit 0  
4. n Value set in TPS0 to TPS3 (1 n 11)  
:
5. Figures in parentheses apply to operation with fX = 5.0 MHz  
449  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal  
scaled from the clock input from the ASCK pin.  
(a) Generation of baud rate transmit/receive clock by means of main system clock  
The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from  
the main system clock is found from the following expression.  
fXX  
[Baud rate] =  
where,  
[Hz]  
n
2 × (k+16)  
fX  
fXX  
n
: Main system clock oscillation frequency  
: Main system clock frequency (fx or fx/2)  
: Value set in TPS0 to TPS3 (1 n 11)  
: Value set in MDL0 to MDL3 (0 k 14)  
k
Table 19-3. Relation between Main System Clock and Baud Rate  
fx = 5.0 MHz  
fx = 4.19 MHz  
Baud  
Rate  
(bps)  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)  
75  
00H  
E6H  
E0H  
D0H  
C0H  
B0H  
A0H  
90H  
80H  
70H  
64H  
60H  
50H  
1.73  
0.88  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
0
0BH  
03H  
EBH  
DBH  
CBH  
BBH  
ABH  
9BH  
8BH  
7BH  
71H  
6BH  
5BH  
1.14  
–2.01  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
–1.31  
1.14  
1.14  
EBH  
E3H  
DBH  
CBH  
BBH  
ABH  
9BH  
8BH  
7BH  
6BH  
61H  
5BH  
1.14  
–2.01  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
–1.31  
1.14  
110  
06H  
00H  
E0H  
D0H  
C0H  
B0H  
A0H  
90H  
80H  
74H  
70H  
60H  
0.88  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
0
150  
300  
600  
1200  
2400  
4800  
9600  
19200  
31250  
38400  
76800  
1.73  
1.73  
1.73  
1.73  
Remark MCS: Oscillation mode selection register bit 0  
450  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin  
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate  
generated from the clock input from the ASCK pin is obtained with the following expression.  
fASCK  
[Baud rate] =  
[Hz]  
2 × (k+16)  
fASCK  
k
:
:
Frequency of clock input to ASCK pin  
Value set in MDL0 to MDL3 (0 k 14)  
Table 19-4. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)  
Baud Rate (bps)  
75  
ASCK Pin Input Frequency  
2.4 kHz  
110  
3.52 kHz  
150  
4.8 kHz  
300  
9.6 kHz  
600  
19.2 kHz  
1200  
38.4 kHz  
2400  
76.8 kHz  
4800  
153.6 kHz  
307.2 kHz  
614.4 kHz  
1000.0 kHz  
1228.8 kHz  
9600  
19200  
31250  
38400  
451  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.4 Serial Interface Channel 2 Operation  
Serial interface channel 2 has the following three modes.  
• Operation stop mode  
• Asynchronous serial interface (UART) mode  
• 3-wire serial I/O mode  
19.4.1 Operation stop mode  
In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.  
In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal  
input/output ports.  
(1) Register setting  
Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the  
asynchronous serial interface mode register (ASIM).  
(a) Serial operating mode register 2 (CSIM2)  
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM2 to 00H.  
Symbol  
<7>  
6
0
5
0
4
0
3
0
2
1
0
0
Address After Reset R/W  
FF72H 00H R/W  
CSIM  
22  
CSIM2 CSIE2  
CSCK  
CSIE2 Operation Control in 3-wire Serial I/O Mode  
0
1
Operation stopped  
Operation enabled  
Caution Ensure that bits 0 and 3 to 6 are set to 0.  
452  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(b) Asynchronous serial interface mode register (ASIM)  
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ASIM to 00H.  
Symbol  
ASIM TXE RXE PS1 PS0  
<7>  
<6>  
5
4
3
2
1
0
Address After Reset R/W  
FF70H 00H R/W  
CL  
SL ISRM SCK  
RXE Receive Operation Control  
0
1
Receive operation stopped  
Receive operation enabled  
TXE Transmit Operation Control  
0
1
Transmit operation stopped  
Transmit operation enabled  
453  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.4.2 Asynchronous serial interface (UART) mode  
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.  
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.  
In addition, the baud rate can be defined also by scaling the input clock to the ASCK pin.  
The MIDI standard baud rate (31.25 kbps) can also be used by employing the dedicated UART baud rate generator.  
(1) Register setting  
UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial  
interface mode register (ASIM), the asynchronous serial interface status register (ASIS), and the baud rate  
generator control register (BRGC).  
(a) Serial operating mode register 2 (CSIM2)  
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM2 to 00H.  
When the UART mode is selected, 00H should be set in CSIM2.  
Symbol  
<7>  
6
0
5
0
4
0
3
0
2
1
0
0
Address After Reset R/W  
FF72H 00H R/W  
CSIM  
22  
CSIM2 CSIE2  
CSCK  
CSCK Selection of Serial Operating Mode  
0
1
UART mode  
3-wire serial I/O mode  
CSIM22 First Bit Specification  
0
1
MSB  
LSB  
CSIE2 Operation Control in 3-wire Serial I/O Mode  
0
1
Operation stopped  
Operation enabled  
Caution Ensure that bits 0 and 3 to 6 are set to 0.  
454  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(b) Asynchronous serial interface mode register (ASIM)  
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ASIM to 00H.  
Symbol  
<7>  
<6>  
5
4
3
2
1
0
Address After Reset R/W  
FF70H 00H R/W  
ASIM TXE RXE PS1 PS0  
CL  
SL ISRM SCK  
SCK Clock Selection in Asynchronous Serial Interface  
Mode  
0
1
Input clock from off-chip to ASCK pin  
Dedicated baud rate generator outputNote  
ISRM Control of Reception Completion Interrupt Request  
in Case of Error Generation  
Reception completion interrupt request generated  
in case of error generation  
0
Reception completion interrupt request not  
generated in case of error generation  
1
SL  
0
Transmit Data Stop Bit Length Specification  
1 bit  
1
2 bits  
CL  
0
Character Length Specification  
7 bits  
8 bits  
1
PS1  
0
PS0 Parity Bit Specification  
0
No Parity  
0 parity always added in transmission  
No parity test in reception (parity error not  
generated)  
0
1
1
1
0
1
Odd parity  
Even parity  
RXE Receive Operation Control  
0
1
Receive operation stopped  
Receive operation enabled  
TXE Transmit Operation Control  
0
1
Transmit operation stopped  
Transmit operation enabled  
Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used  
as an input/output port.  
Caution The serial transmit/receive operation must be stopped before changing the operating  
mode.  
455  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(c) Asynchronous serial interface status register (ASIS)  
ASIS is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ASIS to 00H.  
Symbol  
ASIS  
7
0
6
0
5
0
4
0
3
0
2
1
0
Address After Reset R/W  
FF71H 00H  
PE  
FE  
OVE  
R
OVE Overrun Error Flag  
0
Overrun error not generated  
Overrun error generatedNote 1  
(When next receive operation is completed before  
data from receive buffer register is read)  
1
FE  
0
Framing Error Flag  
Framing error not generated  
Framing error generatedNote 2  
(When stop bit is not detected)  
1
PE  
0
Parity Error Flag  
Parity error not generated  
Parity error generated (When transmit data parity  
does not match)  
1
Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun  
errors will continue to be generated until RXB is read.  
2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial  
interface mode register (ASIM), only single stop bit detection is performed during reception.  
456  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(d) Baud rate generator control register (BRGC)  
BRGC is set with an 8-bit memory manipulation instruction.  
RESET input sets BRGC to 00H.  
Symbol  
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0  
7
6
5
4
3
2
1
0
Address After Reset R/W  
FF73H 00H R/W  
MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection  
k
fSCK/16  
fSCK/17  
fSCK/18  
fSCK/19  
fSCK/20  
fSCK/21  
fSCK/22  
fSCK/23  
fSCK/24  
fSCK/25  
fSCK/26  
fSCK/27  
fSCK/28  
fSCK/29  
fSCK/30  
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
(continued)  
Remark  
fSCK : 5-bit counter source clock  
Value set in MDL0 to MDL3 (0 k 14)  
k
:
457  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
5-Bit Counter Source Clock Selection  
TPS3 TPS2 TPS1 TPS0  
n
MCS = 1  
MCS = 0  
10  
10  
11  
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
fXX/2  
fXX  
fX/2  
(4.9 kHz)  
(5.0 MHz)  
(2.5 MHz)  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
fX/2  
(2.4 kHz)  
(2.5 MHz)  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
(4.9 kHz)  
11  
1
fX  
fX/2  
2
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fX/2  
fX/2  
2
2
3
4
5
6
7
8
9
2
3
fX/2  
fX/2  
3
3
4
fX/2  
fX/2  
4
4
5
fX/2  
fX/2  
5
5
6
fX/2  
fX/2  
6
6
7
fX/2  
fX/2  
7
7
8
fX/2  
fX/2  
8
8
9
fX/2  
fX/2  
9
9
10  
fX/2  
fX/2  
10  
Other than above  
Setting prohibited  
Caution When a data is written to BRGC during a communication operation, baud rate generator  
output is disrupted and communication cannot be performed normally. Therefore, data  
must not be written to BRGC during a communication operation.  
Remarks 1. fX  
:
:
Main system clock oscillation frequency  
Main system clock frequency (fX or fX/2)  
2. fXX  
3. MCS : Oscillation mode selection register (OSMS) bit 0  
4. n Value set in TPS0 to TPS3 (1 n 11)  
:
5. Figures in parentheses apply to operation with fX = 5.0 MHz.  
458  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or  
a signal scaled from the clock input from the ASCK pin.  
(i) Generation of baud rate transmit/receive clock by means of main system clock  
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated  
from the main system clock is obtained with the following expression.  
fXX  
[Baud rate] =  
where,  
[Hz]  
n
2 × (k+16)  
fX  
fXX  
n
: Main system clock oscillation frequency  
: Main system clock frequency (fx or fx/2)  
: Value set in TPS0 to TPS3 (1 n 11)  
: Value set in MDL0 to MDL3 (0 k 14)  
k
Table 19-5. Relation between Main System Clock and Baud Rate  
fx = 5.0 MHz  
fx = 4.19 MHz  
Baud  
Rate  
(bps)  
MCS = 1  
MCS = 0  
MCS = 1  
MCS = 0  
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)  
75  
00H  
E6H  
E0H  
D0H  
C0H  
B0H  
A0H  
90H  
80H  
70H  
64H  
60H  
50H  
1.73  
0.88  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
0
0BH  
03H  
EBH  
DBH  
CBH  
BBH  
ABH  
9BH  
8BH  
7BH  
71H  
6BH  
5BH  
1.14  
–2.01  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
–1.31  
1.14  
1.14  
EBH  
E3H  
DBH  
CBH  
BBH  
ABH  
9BH  
8BH  
7BH  
6BH  
61H  
5BH  
1.14  
–2.01  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
1.14  
–1.31  
1.14  
110  
06H  
00H  
E0H  
D0H  
C0H  
B0H  
A0H  
90H  
80H  
74H  
70H  
60H  
0.88  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
1.73  
0
150  
300  
600  
1200  
2400  
4800  
9600  
19200  
31250  
38400  
76800  
1.73  
1.73  
1.73  
1.73  
Remark MCS: Oscillation mode selection register bit 0  
459  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin  
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate  
generated from the clock input from the ASCK pin is obtained with the following expression.  
fASCK  
[Baud rate] =  
[Hz]  
2 × (k+16)  
where,  
fASCK  
:
:
Frequency of clock input to ASCK pin  
k
Value set in MDL0 to MDL3 (0 k 14)  
Table 19-6. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)  
Baud Rate (bps)  
75  
ASCK Pin Input Frequency  
2.4 kHz  
110  
3.52 kHz  
150  
4.8 kHz  
300  
9.6 kHz  
600  
19.2 kHz  
1200  
38.4 kHz  
2400  
76.8 kHz  
4800  
153.6 kHz  
307.2 kHz  
614.4 kHz  
1000.0 kHz  
1228.8 kHz  
9600  
19200  
31250  
38400  
460  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(2) Communication operation  
(a) Data format  
The transmit/receive data format is as shown in Figure 19-7.  
Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format  
One Data Frame  
Start  
Bit  
Parity  
Bit  
D0 D1 D2 D3 D4 D5 D6 D7  
Stop Bit  
Character Bits  
One data frame consists of the following bits.  
• Start bits.................. 1 bit  
• Character bits ......... 7 bits/8 bits  
• Parity bits ................ Even parity/odd parity/0 parity/no parity  
• Stop bit(s) ............... 1 bit/2 bits  
The character bit length, parity, and stop bit length for each data frame are specified with asynchronous  
serial interfaece mode register (ASIM).  
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in  
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is  
always "0".  
The serial transfer rate is set with ASIM and the baud rate generator control register (BRGC).  
If a serial data receive error is generated, the receive error contents can be determined by reading the  
status of the asynchronous serial interface status register (ASIS).  
461  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(b) Parity types and operation  
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity  
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd  
number) error can be detected. With 0 parity and no parity, an error cannot be detected.  
(i) Even parity  
• Transmission  
The number of bits with a value of “1”, including the parity bit, in the transmit data is controlled to  
be even.  
The value of the parity bit is as follows:  
Number of bits with a value of “1” in transmit data is odd : 1  
Number of bits with a value of “1” in transmit data is even : 0  
• Reception  
The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If  
it is odd, a parity error occurs.  
(ii) Odd parity  
• Transmission  
Conversely to the situation with even parity, the number of bits with a value of “1”, including the  
parity bit, in the transmit data is controlled to be odd. The value of the parity bit is as follows:  
Number of bits with a value of “1” in transmit data is odd : 0  
Number of bits with a value of “1” in transmit data is even : 1  
• Reception  
The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If  
it is even, a parity error occurs.  
(iii) 0 Parity  
When transmitting, the parity bit is set to “0” irrespective of the transmit data.  
At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective  
of whether the parity bit is set to “0” or “1”.  
(iv) No parity  
A parity bit is not added to the transmit data. At reception, data is received assuming that there is  
no parity bit. Since there is no parity bit, a parity error is not generated.  
462  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(c) Transmission  
A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit,  
parity bit and stop bit(s) are added automatically.  
When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when  
the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is  
generated.  
Figure 19-8. Asynchronous Serial Interface Transmission Completion  
Interrupt Request Generation Timing  
(a) Stop bit length: 1  
STOP  
TxD (Output)  
INTST  
D0  
D1  
D2  
D6  
D7  
Parity  
START  
(b) Stop bit length: 2  
TxD (Output)  
INTST  
D0  
D1  
D2  
D6  
D7  
Parity  
STOP  
START  
Caution Do not rewrite the asynchronous serial interface mode register (ASIM) during a  
transmit operation. If rewriting of the ASIM register is performed during transmission,  
subsequent transmit operations may not be possible (the normal state is restored by  
RESET input).  
Whether transmission is in progress or not can be determined by software using a  
transmission completion interrupt (INTST) or the interrupt request flag (STIF) set by  
the INTST.  
463  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(d) Reception  
When the bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive  
operation is enabled and sampling of the RxD pin input is performed.  
RxD pin input sampling is performed using the serial clock specified by ASIM.  
When the RxD pin input becomes low, the 5-bit counter of the baud rate generator (refer to Figure 19-  
2) starts counting, and at the time when the half time determined by specified baud rate has passed, the  
data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start  
timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and  
data sampling is performed. When character data, a parity bit and one stop bit are detected after the  
start bit, reception of one frame of data ends.  
When one frame of data has been received, the receive data in the shift register is transferred to the receive  
buffer register (RXB), and a reception completion interrupt request (INTSR) is generated.  
Even if an error is generated, the receive data in which the error was generated is transferred to RXB.  
If bit 1 (ISRM) of ASIM is cleared (0) when the error is generated, INTSR will be generated. If ISRM is  
set (1), INTSR will not be generated.  
If the RXE bit is reset (0) during the receive operation, the receive operation is stopped immediately. In  
this case, the contents of RXB and ASIS are not changed, and INTSR and INTSER are not generated.  
Figure 19-9. Asynchronous Serial Interface Reception Completion  
Interrupt Request Generation Timing  
STOP  
RxD (Input)  
INTSR  
D0  
D1  
D2  
D6  
D7  
Parity  
START  
Caution The receive buffer register (RXB) must be read even if a receive error is generated. If  
RXB is not read, an overrun error will be generated when the next data is received, and  
the receive error state will continue indefinitely.  
464  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(e) Receive errors  
Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.  
When the data reception result error flag is set in the asynchronous serial interface status register (ASIS),  
a receive error interrupt request (INTSER) is generated. INTSER is generated before receive completion  
interrupt request (INTSR). Receive error causes are shown in Table 19-7.  
What type of error was generated can be detected by reading the contents of ASIS in the reception error  
interrupt servicing (INTSER). (see Figures 19-9 and 19-10).  
The contents of ASIS are reset (0) by reading the receive buffer register (RXB) or receiving the next data  
(if there is an error in the next data, the corresponding error flag is set).  
Table 19-7. Receive Error Causes  
Receive Errors  
Cause  
Parity error  
Transmission-time parity specification and reception data parity do not match  
Stop bit not detected  
Framing error  
Overrun error  
Reception of next data is completed before data is read from receive register buffer  
Figure 19-10. Receive Error Timing  
STOP  
RxD (Input)  
D0  
D1  
D2  
D6  
D7  
Parity  
START  
INTSRNote  
INTSER (when framing/  
overrun error occurs)  
INTSER (when parity  
error occurs)  
Note If a reception error is generated while bit 1 (ISRM) of asynchronous serial interface mode register  
(ASIM) is set (1), INTSR will not be generated.  
Cautions 1. The contents of the ASIS register are reset (0) by reading the receive buffer register  
(RXB) or receiving the next data. To ascertain the error contents, ASIS must be read  
before reading RXB.  
2. The receive buffer register (RXB) must be read even if a receive error is generated.  
If RXB is not read, an overrun error will be generated when the next data is received,  
and the receive error state will continue indefinitely.  
465  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(3) UART mode cautions  
(a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared and the  
transmission operation is stopped during transmission, be sure to set the transmit shift register (TXS) to  
FFH, then set the TXE to 1 before executing the next transmission.  
(b) When bit 6 (RXE) of ASIM is cleared and the receive operation is stopped during reception, the state of  
the receive buffer register (RXB) and whether the receive completion interrupt request (INTSR) is  
generated depend on the timing of clearing. Figure 19-11 shows the timing.  
Figure 19-11. The State of Receive Buffer Register (RXB) and Whether  
the Receive Completion Interrupt Request (INTSR) is Generated  
RxD Pin  
Parity  
RXB  
INTSR  
<1>  
<3>  
<2>  
When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.  
When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.  
When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.  
466  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.4.3 3-wire serial I/O mode  
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate  
a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc.  
Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).  
(1) Register setting  
3-wireserialI/Omodesettingsareperformedusingserialoperatingmoderegister2(CSIM2), theasynchronous  
serial interface mode register (ASIM), and the baud rate generator control register (BRGC).  
(a) Serial operating mode register 2 (CSIM2)  
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets CSIM2 to 00H.  
Symbol  
<7>  
6
0
5
0
4
0
3
0
2
1
0
0
Address After Reset R/W  
FF72H 00H R/W  
CSIM  
22  
CSIM2 CSIE2  
CSCK  
CSCK Selection of Serial Operation Mode  
0
1
UART mode  
3-wire serial I/O mode  
CSIM22 First Bit Specification  
0
1
MSB  
LSB  
CSIE2 Operation Control in 3-wire Serial I/O Mode  
0
1
Operation stopped  
Operation enabled  
Caution Ensure that bits 0 and 3 to 6 are set to 0.  
467  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(b) Asynchronous serial interface mode register (ASIM)  
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets ASIM to 00H.  
When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.  
Symbol  
<7>  
<6>  
5
4
3
2
1
0
Address After Reset R/W  
FF70H 00H R/W  
ASIM TXE RXE PS1 PS0  
CL  
SL ISRM SCK  
SCK Clock Selection in Asynchronous Serial Interface  
Mode  
0
1
Input clock from off-chip to ASCK pin  
Dedicated baud rate generator output  
ISRM Control of Reception Completion Interrupt Request  
in Case of Error Generation  
Reception completion interrupt request generated  
in case of error generation  
0
Reception completion interrupt request not  
generated in case of error generation  
1
SL  
0
Transmit Data Stop Bit Length Specification  
1 bit  
1
2 bits  
CL  
0
Character Length Specification  
7 bits  
8 bits  
1
PS1  
0
PS0 Parity Bit Specification  
0
No Parity  
0 parity always added in transmission  
No parity test in reception (parity error not  
generated)  
0
1
1
1
0
1
Odd parity  
Even parity  
RXE Receive Operation Control  
0
1
Receive operation stopped  
Receive operation enabled  
TXE Transmit Operation Control  
0
1
Transmit operation stopped  
Transmit operation enabled  
468  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(c) Baud rate generator control register (BRGC)  
BRGC is set with an 8-bit memory manipulation instruction.  
RESET input sets BRGC to 00H.  
Symbol  
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0  
7
6
5
4
3
2
1
0
Address After Reset R/W  
FF73H 00H R/W  
MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection  
k
fSCK/16  
fSCK/17  
fSCK/18  
fSCK/19  
fSCK/20  
fSCK/21  
fSCK/22  
fSCK/23  
fSCK/24  
fSCK/25  
fSCK/26  
fSCK/27  
fSCK/28  
fSCK/29  
fSCK/30  
fSCK  
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Remark  
fSCK : 5-bit counter source clock  
Value set in MDL0 to MDL3 (0 k 14)  
k
:
469  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
5-Bit Counter Source Clock Selection  
TPS3 TPS2 TPS1 TPS0  
n
MCS = 1  
MCS = 0  
10  
10  
11  
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
fXX/2  
fXX  
fX/2  
(4.9 kHz)  
(5.0 MHz)  
(2.5 MHz)  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
fX/2  
(2.4 kHz)  
(2.5 MHz)  
(1.25 MHz)  
(625 kHz)  
(313 kHz)  
(156 kHz)  
(78.1 kHz)  
(39.1 kHz)  
(19.5 kHz)  
(9.8 kHz)  
(4.9 kHz)  
11  
1
fX  
fX/2  
2
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fXX/2  
fX/2  
fX/2  
2
2
3
4
5
6
7
8
9
2
3
fX/2  
fX/2  
3
3
4
fX/2  
fX/2  
4
4
5
fX/2  
fX/2  
5
5
6
fX/2  
fX/2  
6
6
7
fX/2  
fX/2  
7
7
8
fX/2  
fX/2  
8
8
9
fX/2  
fX/2  
9
9
10  
fX/2  
fX/2  
10  
Other than above  
Setting prohibited  
Caution When a Data is written to BRGC during a communication operation, baud rate generator  
output is disrupted and communication cannot be performed normally. Therefore, data  
must not be written to BRGC during a communication operation.  
Remarks 1. fX  
:
:
Main system clock oscillation frequency  
Main system clock frequency (fX or fX/2)  
2. fXX  
3. MCS : Oscillation mode selection register (OSMS) bit 0  
4. n Value set in TPS0 to TPS3 (1 n 11)  
:
5. Figures in parentheses apply to operation with fX = 5.0 MHz.  
470  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
When the 3-wire serial I/O mode is used, set BRGC as described below.  
(i) When the baud rate generator is not used:  
Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.  
The serial clock frequency becomes 1/2 of the source clock frequency for the 5-bit counter.  
(ii) When the baud rate generator is used:  
Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.  
The serial clock frequency is calculated by the following formula:  
fXX  
Serial clock frequency=  
[Hz]  
n
2 x (k + 16)  
Remarks 1. fX  
2. fXX  
:
:
:
:
Main system clock oscillation frequency  
Main system clock frequency (fX or fX/2)  
Value set in TPS0 to TPS3 (1 n 11)  
Value set in MDL0 to MDL3 (0 k 14)  
3. n  
4. k  
471  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(2) Communication operation  
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/  
received bit by bit in synchronization with the serial clock.  
Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in  
synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output  
from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2)  
on the rise of SCK2.  
At the end of an 8-bit transfer, the operation of the TXS/SIO2 or RXS stops automatically, and the interrupt  
request flag (SRIF) is set.  
Figure 19-12. 3-Wire Serial I/O Mode Timing  
SCK2  
SI2  
1
2
3
4
5
6
7
8
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SO2  
DO7  
DO6  
DO5  
DO4  
DO3  
DO2  
DO1  
DO0  
SRIF  
End of Transfer  
Transfer Start at the Falling Edge of SCK2  
472  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
(3) MSB/LSB switching as the start bit  
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.  
Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown  
in the figure, MSB/LSB can be read/written in reverse form.  
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of the serial operating mode register  
2 (CSIM2).  
Figure 19-13. Circuit of Switching in Transfer Bit Order  
7
6
Internal Bus  
1
0
LSB-first  
MSB-first  
Read/Write Gate  
Read/Write Gate  
SO2 Latch  
SI2  
Transmit Shift Register (TXS/SIO2)  
D
Q
SO2  
SCK2  
Start bit switching is realized by switching the bit order for data write to TXS/SIO2. The TXS/SIO2 shift order  
remains unchanged.  
Thus, switching between MSB-first and LSB-first must be performed before writing data to the TXS/SIO2.  
(4) Transfer start  
Serial transfer is started by setting transfer data to the transmission shift register (TXS/SIO2) when the  
following two conditions are satisfied.  
Serial interface channel 2 operation control bit (CSIE2) = 1  
Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer.  
Caution If CSIE2 is set to "1" after data write to TXS/SIO2, transfer does not start.  
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is  
set.  
473  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
19.4.4 Limitations when UART mode is used  
In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception  
error interrupt request (INTSER) has occurred and then cleared. Consequently, the following phenomenon may occur.  
Description  
If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the reception completion  
interrupt request (INTSR) does not occur on occurrence of a reception error. If the receive buffer register (RXB)  
is read at certain timing (a in Figure 19-14) during the reception error interrupt (INTSER) processing, the internal  
error flag is cleared to 0. As a result, it is judged that no reception error has occurred, and INTSR, which must  
not occur, occurs. Figure 19-14 illustrates this operation.  
Figure 19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1)  
fsck  
INTSER (when framing/  
overrun error occurs)  
a
Error flag  
(internal flag)  
Cleared on  
reading RXB  
INTSR  
Interrupt routine of CPU  
It is judged that reception error has not  
occurred, and INTSR occurs  
Reading RXB  
Remark ISRM : Bit 1 of asynchronous serial interface mode register (ASIM)  
fSCK : Source clock of 5-bit counter of baud rate generator  
RXB : Receive buffer register  
To avoid this phenomenon, take the following measures:  
Countermeasures  
• In case of framing error or overrun error  
Disable the receive buffer register (RXB) from being read for a certain time (T2 in Figure 19-15) after the  
reception error interrupt request (INTSER) has occurred.  
474  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
• In case of parity error  
Disable the receive buffer register (RXB) from being read for a certain time (T1 + T2 in Figure 19-15) after  
the reception error interrupt request (INTSER) has occurred.  
Figure 19-15. Receive Buffer Register Read Disable Period  
RxD (input)  
STOP  
D0  
D1  
D2  
D6  
D7 Parity  
START  
INTSR  
INTSER (on occurrence of  
framing/overrun error)  
INTSER (on occurrence of  
parity error)  
T1  
T2  
T1 : Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate)  
T2 : Time of 2 clocks of source clock (fSCK) of 5-bit counter selected by BRGC  
Example of preventive measures  
Here is an example of the above preventive measures.  
[Condition]  
fX = 5.0 MHz  
Processor clock control register (PCC) = 00H  
Oscillation mode select register (OSMS) = 01H  
Baud rate generator control register (BRGC) = B0H (2400 bps selected as baud rate)  
TCY = 0.4 µs (tCY = 0.2 µs)  
1
T1 =  
= 416.7 µs  
2400  
T2 = 12.8 × 2 = 25.6 µs  
T1 + T2  
= 2212 (clocks)  
tCY  
475  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 19 SERIAL INTERFACE CHANNEL 2  
[Example]  
UART reception error interrupt  
(INTSER) servicing  
Main processing  
EI  
Occurrence of INTSER  
Instructions  
equivalent to  
2205 CPU  
7 clocks of CPU clock (MIN.)  
(time from interrupt request to servicing)  
clocks (MIN.)  
are necessary.  
MOV A, RXB  
RETI  
476  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 20 REAL-TIME OUTPUT PORT  
20.1 Real-Time Output Port Functions  
Data set previously in the real-time output buffer register can be transferred to the output latch by hardware  
concurrently with timer interrupt requests or external interrupt request generation, then output externally. This is called  
the real-time output function. The pins that output data externally are called real-time output ports.  
By using a real-time output, a signal which has no jitter can be output. This port is therefore suitable for control  
of stepping motors, etc.  
Port mode/real-time output port mode can be specified bit-wise.  
477  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 20 REAL-TIME OUTPUT PORT  
20.2 Real-Time Output Port Configuration  
The real-time output port consists of the following hardware.  
Table 20-1. Real-time Output Port Configuration  
Item  
Register  
Control register  
Configuration  
Real-time output buffer register (RTBL, RTBH)  
Port mode register 12 (PM12)  
Real-time output port mode register (RTPM)  
Real-time output port control register (RTPC)  
Figure 20-1. Real-time Output Port Block Diagram  
Internal Bus  
Real-time Output Port  
Control Register  
Port Mode  
Register 12  
(PM12)  
EXTR  
BYTE  
INTP2  
INTTM1  
INTTM2  
Real-time Output  
Buffer Register  
Lower 4 Bits  
(RTBL)  
Real-time Output  
Buffer Register  
Higher 4 Bits  
(RTBH)  
Output Trigger  
Control Circuit  
Real-time Output port  
Mode Register (RTPM)  
Output Latch  
P120  
P127  
478  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 20 REAL-TIME OUTPUT PORT  
(1) Real-time output buffer register (RTBL, RTBH)  
Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown  
in Figure 20-2.  
When specifying 4 bits × 2 channels as the operating mode, data are set individually in RTBL and RTBH.  
When specifying 8 bits × 1 channel as the operating mode, data are set to both RTBL and RTBH by writing  
8-bit data to either RTBL or RTBH.  
Table 20-2 shows operations during manipulation of RTBL and RTBH.  
Figure 20-2. Real-time Output Buffer Register Configuration  
Higher  
4 Bits  
Lower  
4 Bits  
FF30H  
FF31H  
RTBL  
RTBH  
Table 20-2. Operation in Real-time Output Buffer Register Manipulation  
Note1  
Note2  
In Read  
In Write  
Register to be  
Manipulated  
Operating Mode  
4 Bits × 2 Channels  
8 Bits × 1 Channel  
Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits  
RTBL  
RTBH  
RTBL  
RTBH  
RTBH  
RTBH  
RTBH  
RTBH  
RTBL  
RTBL  
RTBL  
RTBL  
Invalid  
RTBH  
RTBH  
RTBH  
RTBL  
Invalid  
RTBL  
RTBL  
Notes 1. Only the bits set in the real-time output port mode can be read. When a bit set in the port mode  
is read, 0 is read.  
2. After setting data in the real-time output port, output data should be set in RTBL and RTBH by the  
time a real-time output trigger is generated.  
479  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 20 REAL-TIME OUTPUT PORT  
20.3 Real-Time Output Port Control Registers  
The following three registers control the real-time output port.  
• Port mode register 12 (PM12)  
• Real-time output port mode register (RTPM)  
• Real-time output port control register (RTPC)  
(1) Port mode register 12 (PM12)  
This register sets the input or output mode of port 12 pins (P120 through P127) which are multiplexed with  
real-time output pins (RTP0 through RTP7). To use port 12 as a real-time output port, the port pin that performs  
real-time output must be set in the output mode (PM12n = 0: n = 0 to 7).  
PM12 is set by using a 1-bit or 8-bit memory manipulation instruction.  
This register is set to FFH by RESET input.  
Figure 20-3. Port Mode Register 12 Format  
Symbol  
7
6
5
4
3
2
1
0
Address After Reset  
FF2CH FFH  
R/W  
R/W  
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120  
PM12n  
Selects I/O mode of P12n pin (n = 0 to 7)  
Output mode (output buffer ON)  
0
1
Input mode (ourput buffer OFF)  
(2) Real-time output port mode register (RTPM)  
This register selects the real-time output port mode/port mode bit-wise.  
RTPM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets this register to 00H.  
Figure 20-4. Real-time Output Port Mode Register Format  
After  
Reset  
Symbol  
7
6
5
4
3
2
1
0
Address  
FF34H  
R/W  
R/W  
RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0  
00H  
RTPMn  
Real-time Output Port Selection (n = 0 to 7)  
Port mode  
0
1
Real-time Output Port Mode  
Cautions 1. When using these bits as a real-time output port, set the ports to which real-time output  
is performed to the output mode (clear the corresponding bit of the port mode register  
12 (PM12) to 0).  
2. In the port specified as a real-time output port, data cannot be set to the output latch.  
Therefore, when setting an initial value, data should be set to the output latch before  
setting the real-time output mode.  
480  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 20 REAL-TIME OUTPUT PORT  
(3) Real-time output port control register (RTPC)  
This register sets the real-time output port operating mode and output trigger.  
Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger.  
RTPC is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets this register to 00H.  
Figure 20-5. Real-time Output Port Control Register Format  
After  
Reset  
Address  
FF36H  
R/W  
R/W  
Symbol  
RTPC  
7
0
6
0
5
0
4
0
3
0
2
0
<1> <0>  
00H  
BYTE EXTR  
EXTR  
Real-time Output Control by INTP2  
INTP2 not specified as real-time output trigger  
INTP2 specified as real-time output trigger  
0
1
BYTE  
Real-time Output Port Operating Mode  
4 Bits × 2 Channels  
0
1
8 Bits × 1 Channel  
Table 20-3. Real-time Output Port Operating Mode and Output Trigger  
BYTE  
0
EXTR  
Operating Mode  
RTBH Port Output  
INTTM2  
RTBL Port Output  
INTTM1  
0
1
0
1
4 Bits × 2 Channels  
INTTM1  
INTP2  
INTTM1  
INTP2  
1
8 Bits × 1 Channel  
481  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 20 REAL-TIME OUTPUT PORT  
[MEMO]  
482  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.1 Interrupt Function Types  
The following three types of interrupt functions are used.  
(1) Non-maskable interrupt  
This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo  
interrupt priority control and is given top priority over all other interrupt requests.  
It generates a standby release signal.  
Non-maskable interrupt includes one interrupt request source from watchdog timer.  
(2) Maskable interrupts  
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group  
and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, PR1L).  
Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same  
priority are simultaneously generated, each interrupts has a predetermined priority (see Table 21-1).  
A standby release signal is generated.  
Maskable interrupt includes 7 external interrupt request sources and 13 internal interrupt request sources.  
(3) Software interrupt  
This is a vectored interrupt that occurs when the BRK instruction is executed. It is acknowledged even in a  
disabled state. The software interrupt does not undergo interrupt priority control.  
483  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.2 Interrupt Sources and Configuration  
Interrupt sources includes total of 22 non-maskbale, maskable, software interrupts (refer to Table 21-1).  
Table 21-1. Interrupt Source List (1/2)  
Note 2  
Note 1  
Vector  
Table  
Address  
Basic  
Interrupt Source  
Trigger  
Interrupt  
Type  
Default  
Priority  
Internal/  
External  
Configuration  
Type  
Name  
Non-  
maskable  
Watchdog timer overflow (with  
0
INTWDT  
(A)  
watchdog timer mode 1 selected)  
Internal  
0004H  
Watchdog timer overflow (with  
interval timer mode selected)  
INTWDT  
(B)  
(C)  
1
2
3
4
5
6
7
INTP0  
INTP1  
INTP2  
INTP3  
INTP4  
INTP5  
INTP6  
0006H  
0008H  
000AH  
000CH  
000EH  
0010H  
0012H  
Pin input edge detection  
External  
(D)  
End of serial interface channel 0  
transfer  
8
INTCSI0  
0014H  
Maskable  
End of serial interface channel 1  
transfer  
9
INTCSI1  
INTSER  
0016H  
0018H  
Serial interface channel 2 UART reception  
error generation  
10  
Internal  
(B)  
End of serial interface channel 2  
UART reception  
INTSR  
11  
12  
001AH  
001CH  
End of serial interface channel 2  
3-wire transfer  
INTCSI2  
End of serial interface channel 2  
UART transfer  
INTST  
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests.  
0 is the highest priority and 20 is the lowest priority.  
2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 21-1.  
484  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Table 21-1. Interrupt Source List (2/2)  
Note 2  
Note 1  
Default  
Priority  
Vector  
Table  
Address  
Basic  
Interrupt Source  
Interrupt  
Type  
Internal/  
External  
Configuration  
Type  
Name  
Trigger  
Reference time interval signal from  
watch timer  
Maskable  
13  
INTTM3  
Internal  
001EH  
0020H  
(B)  
Generation of 16-bit timer register,  
capture/compare register (CR00)  
match signal  
14  
15  
INTTM00  
INTTM01  
Generation of 16-bit timer register,  
capture/compare register (CR01)  
match signal  
0022H  
Generation of 8-bit timer/event  
counter 1 match signal  
16  
17  
INTTM1  
INTTM2  
0024H  
0026H  
Generation of 8 bit timer/event  
counter 2 match signal  
18  
INTAD  
BRK  
End of A/D converter conversion  
BRK instruction execution  
0028H  
003EH  
Software  
(E)  
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests.  
0 is the highest priority and 18 is the lowest priority.  
2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 21-1.  
485  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-1. Basic Configuration of Interrupt Function (1/2)  
(A) Internal non-maskable interrupt  
Internal Bus  
Vector Table  
Priority Control  
Circuit  
Interrupt  
Request  
Address  
Generator  
Standby  
Release Signal  
(B) Internal maskable interrupt  
Internal Bus  
IE  
MK  
PR  
ISP  
Vector Table  
Priority Control  
Circuit  
Address  
Interrupt  
Request  
IF  
Generator  
Standby  
Release Signal  
(C) External maskable interrupt (INTP0)  
Internal Bus  
Sampling Clock  
External Interrupt Mode  
Register (INTM0)  
Select Register  
MK  
IE  
PR  
ISP  
(SCS)  
Vector Table  
Address  
Generator  
Priority Control  
Circuit  
Sampling  
Clock  
Edge  
Detector  
Interrupt  
Request  
IF  
Standby  
Release Signal  
486  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-1. Basic Configuration of Interrupt Function (2/2)  
(D) External maskable interrupt (except INTP0)  
Internal Bus  
MK  
External Interrupt  
Mode Register  
(INTM0, INTM1)  
IE  
PR  
ISP  
Vector Table  
Address  
Generator  
Priority Control  
Circuit  
Interrupt  
Request  
Edge  
Detector  
IF  
Standby  
Release Signal  
(E) Software interrupt  
Internal Bus  
Vector Table  
Address  
Generator  
Interrupt  
Request  
Priority Control  
Circuit  
Remark  
IF  
IE  
:
:
Interrupt request flag  
Interrupt enable flag  
ISP : Inservice priority flag  
MK  
PR  
:
:
Interrupt mask flag  
Priority specify flag  
487  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.3 Interrupt Function Control Registers  
The following six types of registers are used to control the interrupt functions.  
• Interrupt request flag register (IF0L, IF0H, IF1L)  
• Interrupt mask flag register (MK0L, MK0H, MK1L)  
• Priority specify flag register (PR0L, PR0H, PR1L)  
• External interrupt mode register (INTM0, INTM1)  
• Sampling clock select register (SCS)  
• Program status word (PSW)  
Table 21-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding  
to interrupt request sources.  
Table 21-2. Various Flags Corresponding to Interrupt Request Sources  
Interrupt Source  
Interrupt Request Flag  
Register  
Interrupt Mask Flag  
Register  
Priority Specify Flag  
Register  
INTWDT  
TMIF4  
IF0L  
IF0H  
IF1L  
TMMK4  
PMK0  
MK0L  
MK0H  
MK1L  
TMPR4  
PR0L  
PR0H  
PR1L  
INTP0  
PIF0  
PPR0  
INTP1  
PIF1  
PMK1  
PPR1  
INTP2  
PIF2  
PMK2  
PPR2  
INTP3  
PIF3  
PMK3  
PPR3  
INTP4  
PIF4  
PMK4  
PPR4  
INTP5  
PIF5  
PMK5  
PPR5  
INTP6  
PIF6  
PMK6  
PPR6  
INTCSI0  
INTCSI1  
INTSER  
INTSR/INTCSI2  
INTST  
CSIIF0  
CSIIF1  
SERIF  
SRIF  
CSIMK0  
CSIMK1  
SERMK  
SRMK  
CSIPR0  
CSIPR1  
SERPR  
SRPR  
STIF  
STMK  
STPR  
INTTM3  
INTTM00  
INTTM01  
INTTM1  
INTTM2  
INTAD  
TMIF3  
TMIF00  
TMIF01  
TMIF1  
TMIF2  
ADIF  
TMMK3  
TMMK00  
TMMK01  
TMMK1  
TMMK2  
ADMK  
TMPR3  
TMPR00  
TMPR01  
TMPR1  
TMPR2  
ADPR  
488  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(1) Interrupt request flag registers (IF0L, IF0H, IF1L)  
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction  
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request  
or upon application of RESET input.  
IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used  
as a 16-bit register IF0 use a 16-bit memory manipulation instruction for the setting.  
RESET input sets these registers to 00H.  
Figure 21-2. Interrupt Request Flag Register Format  
After  
Reset  
Address  
FFE0H  
R/W  
R/W  
Symbol <7> <6> <5>  
<4> <3> <2> <1> <0>  
00H  
IF0L PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 TMIF4  
<7> <6> <5>  
<4> <3> <2> <1> <0>  
FFE1H  
FFE2H  
00H  
00H  
R/W  
R/W  
IF0H TMIF01 TMIF00 TMIF3 STIF SRIF SERIF CSIIF1 CSIIF0  
<7>  
6
0
5
0
4
0
3
0
<2> <1> <0>  
ADIF TMIF2 TMIF1  
IF1L WTIFNote  
× × IF×  
Interrupt Request Flag  
No interrupt request signal  
0
1
Interrupt request signal is generated;  
Interrupt request state  
Note WTIF is test input flag. Vectored interrupt request is not generated.  
Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer mode.  
If a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0.  
2. Set always 0 in IF1L bits 3 through 6.  
489  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)  
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set  
standby clear enable/disable.  
MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H  
are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.  
RESET input sets these registers to FFH.  
Figure 21-3. Interrupt Mask Flag Register Format  
After  
Reset  
Address  
FFE4H  
R/W  
R/W  
Symbol <7> <6> <5>  
<4> <3> <2> <1>  
<0>  
FFH  
MK0L PMK6 PMK5 PMK4 PMK3 PMK2 PMK PMK TMMK4  
<7> <6> <5>  
<4> <3> <2> <1>  
<0>  
FFE5H  
FFE6H  
FFH  
FFH  
R/W  
R/W  
MK0H TMMK01 TMMK00 TMMK3 STMK SRMK SERMK CSIMK1 CSIMK0  
<7>  
6
1
5
1
4
3
<2> <1>  
<0>  
MK1L WTMKNote  
1
1
ADMK TMMK2 TMMK1  
× × MK  
×
Interrupt Servicing Control  
0
1
Interrupt servicing enabled  
Interrupt servicing disabled  
Note WTMK controls standby mode release enable/disable. It does not perform control of interrupt function.  
Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value  
becomes undefined.  
2. Because port 0 has a dual function as the external interrupt request input, when the  
output level is changed by specifying the output mode of the port function, an interrupt  
request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the  
output mode.  
3. Set always 1 in MK1L bits 3 through 6.  
490  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(3) Priority specify flag registers (PR0L, PR0H, and PR1L)  
The priority specify flag is used to set the corresponding maskable interrupt priority orders.  
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are  
used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.  
RESET input sets these registers to FFH.  
Figure 21-4. Priority Specify Flag Register Format  
After  
Reset  
Address  
FFE8H  
R/W  
R/W  
Symbol <7> <6> <5> <4>  
<3> <2>  
<1>  
<0>  
FFH  
PR0L PPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 TMPR4  
<7> <6> <5> <4>  
<3> <2>  
<1>  
<0>  
FFE9H  
FFEAH  
FFH  
FFH  
R/W  
R/W  
PR0H TMPR01TMPR00TMPR3 STPR SRPR SERPRCSIPR1 CSIPR0  
7
1
6
1
5
1
4
1
3
1
<2>  
<1>  
<0>  
PR1L  
ADPR TMPR2 TMPR1  
× × PR  
×
Priority Level Selection  
High priority level  
Low priority level  
0
1
Cautions 1. If a watchdog timer is used in watchdog timer mode 1, set TMPR4 flag to 1.  
2. Set always 1 in PR1L bits 3 through 7.  
491  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(4) External interrupt mode register (INTM0, INTM1)  
These registers set the valid edge for INTP0 to INTP6.  
INTM0 and INTM1 are set by 8-bit memory manipulation instructions.  
RESET input sets these registers to 00H.  
Figure 21-5. External Interrupt Mode Register 0 Format  
After  
Reset  
Address  
FFECH  
R/W  
R/W  
Symbol  
7
6
5
4
3
2
1
0
0
0
INTM0 ES31 ES30 ES21 ES20 ES11 ES10  
00H  
ES11 ES10  
INTP0 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES21 ES20  
INTP1 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES31 ES30  
INTP2 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
Caution Before setting the valid edge of the INTP0/TIO0/P00 pin, stop the timer operation by  
clearing the bits 1 through 3 (TMC01 through TMC03) of the 16-bit timer mode control  
register to 0, 0, 0.  
492  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-6. External Interrupt Mode Register 1 Format  
After  
Reset  
Address  
FFEDH  
R/W  
R/W  
Symbol  
7
6
5
4
3
2
1
0
INTM1 ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40  
00H  
ES41 ES40  
INTP3 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES51 ES50  
INTP4 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES61 ES60  
INTP5 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
ES71 ES70  
INTP6 Valid Edge Selection  
Falling edge  
0
0
1
1
0
1
0
1
Rising edge  
Setting prohibited  
Both falling and rising edges  
493  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(5) Sampling clock select register (SCS)  
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled  
data reception is carried out using INTP0, digital noise is removed with sampling clocks.  
SCS is set with an 8-bit memory manipulation instruction.  
RESET input sets SCS to 00H.  
Figure 21-7. Sampling Clock Select Register Format  
After  
Reset  
Address  
FF47H  
R/W  
R/W  
Symbol  
SCS  
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SCS1 SCS0  
00H  
INTP0 Sampling Clock Selection  
SCS1 SCS0  
MCS = 1  
MCS = 0  
0
0
1
1
0
1
0
1
fxx/2N  
fxx/27  
fxx/25  
fxx/26  
f
f
f
x/27(39.1 kHz)  
x/25(156.3 kHz)  
x/26(78.1 kHz)  
f
f
f
x/28(19.5 kHz)  
x/26(78.1 kHz)  
x/27(39.1 kHz)  
N
5
6
7
Caution fXX/2 is a clock to be supplied to the CPU and fXX/2 , fXX/2 and fXX/2 are clocks to be supplied  
N
to the peripheral hardware. fXX/2 stops in the HALT mode.  
Remarks 1. N  
:
Value (N=0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register  
(PCC)  
2. fXX  
:
:
Main system clock frequency (fX or fX/2)  
Main system clock oscillation frequency  
3. fX  
4. MCS : Oscillation mode selection register (OSMS) bit 0  
5. Values in parentheses when operated with fX = 5.0 MHz.  
494  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
When the sampled INTP0 input level is active twice in succession, the noise eliminator sets interrupt request  
flag (PIF0) to 1.  
Figure 21-8 shows the noise eliminator input/output timing.  
Figure 21-8. Noise Eliminator Input/Output Timing (during rising edge detection)  
(a) When input is less than the sampling cycle (tSMP)  
tSMP  
Sampling Clock  
INTP0  
"L"  
PIF0  
Because INTP0 level is not high level at the time of sampling,  
PIF0 flag remains at low level.  
(b) When input is equal to or twice the sampling cycle (tSMP)  
tSMP  
Sampling Clock  
INTP0  
<1>  
<2>  
PIF0  
Because the sampled INTP0 level is high level twice in succession in <2>,  
PIF0 flag is set to 1.  
(c) When input is twice or more than the cycle frequency (tSMP)  
tSMP  
Sampling Clock  
INTP0  
PIF0  
When INTP0 level becomes high level twice in succession,  
PIF0 flag is set to 1.  
495  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(6) Program status word (PSW)  
The program status word is a register to hold the instruction execution result and the current status for interrupt  
request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt  
processing are mapped.  
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and  
dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK  
instruction is executed, contents of the PSW is automatically saved to the stack and the IE flag is reset to 0.  
If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged  
interrupt are transferred to the ISP flag. Contents of the PSW is also saved into the stack with the PUSH PSW  
instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions.  
RESET input sets PSW to 02H.  
Figure 21-9. Program Status Word Configuration  
State after  
Reset  
7
6
Z
5
4
3
2
0
1
0
02H  
PSW  
IE  
RBS1 AC RBS0  
ISP  
CY  
Used when normal instruction is executed  
ISP  
0
Priority of Interrupt Currently Being Received  
High-priority interrupt servicing  
(low-priority interrupt disable)  
Interrupt request not acknowledged or low-priority  
interrupt servicing  
1
(all-maskable interrupts enable)  
IE  
0
Interrupt Request Acknowledge Enable/Disable  
Disable  
Enable  
1
496  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.4 Interrupt Servicing Operations  
21.4.1 Non-maskable interrupt request acknowledge operation  
A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge  
disable state. It does not undergo interrupt priority control and has highest priority over all other interrupt requests.  
If a non-maskable interrupt request is acknowledged, the contents of acknowledged interrupt is saved in the stacks,  
program status word (PSW) and program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector  
table contents are loaded into PC and branched.  
A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program  
is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following  
RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request  
is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt  
request is acknowledged after termination of the non-maskable interrupt service program execution.  
Figure 21-10 shows the flowchart from generation of non-maskable interrupt request to acknowledgment, Figure  
21-11 shows non-maskable interrupt request acknowledge timing, and Figure 21-12 shows acknowledge operation  
when multiple non-maskable interrupt requests are generated.  
497  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-10. Flowchart of Generation from Non-Maskable Interrupt Request to Acknowledgment  
Start  
WDTM4=1  
(with watchdog timer  
No  
mode selected)?  
Interval timer  
Yes  
No  
Overflow in WDT?  
Yes  
WDTM3=0  
No  
(with non-maskable  
interrupt request  
selected)?  
Reset processing  
Yes  
Interrupt request generation  
No  
WDT interrupt servicing?  
Interrupt request  
held pending  
Yes  
Interrupt control  
register unaccessed?  
No  
Yes  
Interrupt  
service start  
WDTM : Watchdog timer mode register  
WDT : Watchdog timer  
Figure 21-11. Non-Maskable Interrupt Request Acknowledge Timing  
PSW and PC Save, Jump Interrupt Sevicing  
to Interrupt Servicing  
Program  
CPU Instruction  
TMIF4  
Instruction  
Instruction  
The interrupt request generated during this period is acknowledged at the timing of .  
TMIF4 : Watchdog timer interrupt request flag  
498  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation  
(a) If a new non-maskable interrupt request is generated during  
non-maskable interrupt servicing program execution  
Main Routine  
NMI  
Request <2>  
NMI Request <1>  
NMI Request <1> is executed.  
NMI Request <2> is reserved.  
1 Instruction  
Execution  
Reserved NMI Request <2> is processed.  
(b) If two non-maskable interrupt requests are generated during  
non-maskable interrupt servicing program execution  
Main Routine  
NMI Request <1> is executed.  
NMI  
NMI Request <2> is reserved.  
NMI Request <3> is reserved.  
Request <2>  
NMI Request <1>  
NMI  
Request <3>  
1 Instruction  
Execution  
NMI Request <2> is processed.  
NMI requests <3> is not acknowledged  
(only one request has been acknowledged,  
even when two or more NMI requests are  
generated).  
499  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.4.2 Maskable interrupt request acknowledge operation  
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt  
mask flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set  
to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with ISP  
flag reset to 0).  
Table 21-3 shows the time from generation of maskable interrupt request to interrupt servicing.  
For the interrupt request acknowledging timing, refer to Figure 21-14 and 21-15.  
Table 21-3. Times from Maskable Interrupt Request Generation to Interrupt Service  
Note  
Minimum Time  
7 clocks  
Maximum Time  
32 clocks  
When ××PR×=0  
When ××PR×=1  
8 clocks  
33 clocks  
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.  
1
fCPU  
Remark 1 clock :  
(fCPU: CPU clock)  
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority  
with the priority specify flag is acknowledged first. If two or more requests are specified for the same priority with  
priority specify flag, the interrupt request with higher default priority is acknowledged first.  
Any reserved interrupt requests are acknowledged when they become acknowledgeable.  
Figure 21-13 shows interrupt request acknowledge algorithms.  
If a maskable interrupt request is acknowledged, the contents of acknowledged interrupt is saved in the stacks,  
program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged  
interrupt priority specify flag contents are transferred to the ISP flag. Further, the vector table data determined for  
each interrupt request is loaded into PC and branched.  
Return from the interrupt is possible with the RETI instruction.  
500  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-13. Interrupt Request Acknowledge Processing Algorithm  
Start  
No  
× × IF=1?  
Yes (Interrupt Request  
Generation)  
No  
× × MK=0?  
Yes  
Interrupt request  
reserve  
Yes (High priority)  
× × PR=0?  
No (Low Priority)  
Any high-  
priority interrupt request  
Any  
Yes  
Simultaneously  
generated ××PR=0  
interrupt requests?  
among simultaneously generated  
××PR=0 interrupt  
Yes  
requests?  
Interrupt request  
reserve  
Interrupt request  
reserve  
No  
No  
No  
Any  
Simultaneously  
IE=1?  
Yes  
generated high-priority  
interrupt requests?  
Yes  
Interrupt request  
reserve  
Interrupt request  
reserve  
Vectored interrupt  
servicing  
No  
No  
No  
IE=1?  
Yes  
Interrupt request  
reserve  
ISP=1?  
Yes  
Interrupt request  
reserve  
Vectored interrupt  
servicing  
××IF  
××MK  
××PR  
IE  
:
:
:
:
:
Interrupt request flag  
Interrupt mask flag  
Priority specify flag  
Flag to control acknowledgment of maskable interrupt request (1 = enable, 0 = disable)  
Flag to indicate the priority of interrupt currently being serviced (0 = servicing interrupt of high priority,  
1 = not acknowledging interrupt request or servicing interrupt of low priority)  
ISP  
501  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time)  
6 Clocks  
PSW and PC Save,  
Jump to Interrupt  
Servicing  
Interrupt  
Servicing  
Program  
CPU Processing  
Instruction  
Instruction  
× × IF  
(× × PR=1)  
8 Clocks  
× × IF  
(× × PR=0)  
7 Clocks  
1
fCPU  
Remark 1 clock :  
(fCPU: CPU clock)  
Figure 21-15. Interrupt Request Acknowledge Timing (Maximum Time)  
25 Clocks  
6 Clocks  
PSW and PC Save,  
Jump to Interrupt  
Servicing  
Interrupt  
Servicing  
Program  
CPU Processing  
Instruction  
Divide Instruction  
× × IF  
(× × PR=1)  
33 Clocks  
× × IF  
(× × PR=0)  
32 Clocks  
1
fCPU  
Remark 1 clock :  
(fCPU: CPU clock)  
502  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.4.3 Software interrupt request acknowledge operation  
A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled.  
If a software interrupt request is acknowledged, the contents is saved in the stacks, program status word (PSW)  
and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and  
003FH) are loaded into PC and branched.  
Return from the software interrupt is possible with the RETB instruction.  
Caution Do not use the RETI instruction for returning from the software interrupt.  
21.4.4 Multiple interrupt servicing  
Acknowledging another interrupt request while servicing an interrupt is called a multiple interrupt.  
A multiple interrupt is not generated unless interrupt request acknowledge enabled state (IE = 1) is set (except  
non-maskable interrupt). When an interrupt request is acknowledged, interrupt request becomes acknowledge  
disabled state (IE = 0). Therefore, to enable a multiple interrupt, set IE flag to (1) with EI instruction during interrupt  
servicing, and set interrupt enable state.  
In some cases, a multiple interrupt is not enabled even during interrupt enable state. It is controlled with the interrupt  
priority. There are two interrupt priorities : default priority and programmable priority. The multiple interrupt is  
controlled with programmable priority.  
If an interrupt request of the same priority as or a higher priority than the interrupt currently being serviced is  
generated, it is acknowledged as a multiple interrupt. If an interrupt request of the priority lower than the interrupt  
currently being serviced is generated, it is not acknowledged as a multiple interrupt.  
An interrupt request that is not acknowledged due to interrupt disable or low priority is reserved. The reserved  
interrupt request is acknowledged after the current interrupt servicing is completed and one instruction of the main  
processing is executed.  
A multiple interrupt is not acknowledged while a non-maskable interrupt is being serviced.  
Table 21-4 shows the interrupt requests that are capable of multiple interrupts, and Figure 21-16 shows examples  
of multiple interrupts.  
Table 21-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing  
Multiple Interrupt  
Maskable Interrupt Request  
Non-maskable  
Request  
Interrupt  
Request  
PR = 0  
PR = 1  
Interrupt being  
Serviced  
IE = 1  
IE = 0  
IE = 1  
IE = 0  
Non-maskable interrupt  
Maskable interrupt  
D
E
E
E
D
E
E
E
D
D
D
D
D
D
E
E
D
D
D
D
ISP = 0  
ISP = 1  
Software interrupt  
Remarks 1. E : Multiple interrupt enable  
2. D : Multiple interrupt disable  
3. ISP and IE are the flags contained in PSW  
ISP=0 : An interrupt with higher priority is being serviced  
ISP=1 : An interrupt request is not accepted or an interrupt with lower priority is being  
serviced  
IE=0 : Interrupt request acknowledge is disabled  
IE=1 : Interrupt request acknowledge is enabled  
4. PR is a flag contained in PR0L, PR0H, and PR1L  
PR=0  
PR=1  
: Higher priority level  
: Lower priority level  
503  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-16. Multiple Interrupt Example (1/2)  
Example 1. A multiple interrupt is generated at twice  
Main Processing  
INTxx  
INTyy  
INTzz  
Servicing  
Servicing  
Servicing  
IE=0  
IE=0  
IE=0  
EI  
EI  
EI  
INTxx  
(PR=1)  
INTyy  
(PR=0)  
INTzz  
(PR=0)  
RETI  
RETI  
RETI  
While servicing interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and a multiple  
interrupt is generated. Before each interrupt request acknowledgment, the EI instruction is always issued and  
interrupt request acknowledgment is enabled.  
PR = 0  
PR = 1  
IE = 0  
:
:
:
High priority level  
Low priority level  
Interrupt request acknowledgment disabled  
Example 2. A multiple interrupt is not generated with priority control  
Main Processing  
INTxx  
INTyy  
Servicing  
Servicing  
EI  
IE=0  
EI  
INTyy  
(PR=1)  
INTxx  
(PR=0)  
RETI  
1 Instruction  
Execution  
IE=0  
RETI  
Interrupt request INTyy generated while servicing interrupt INTxx is not acknowledged because it has a lower  
priority than INTxx, and a multiple interrupt is not generated. The INTyy request is reserved and acknowledged after  
execution of one main processing instruction.  
PR = 0  
PR = 1  
IE = 0  
:
:
:
High priority level  
Low priority level  
Interrupt request acknowledgment disabled  
504  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
Figure 21-16. Multiple Interrupt Example (2/2)  
Example 3. A multiple interrupt is not generated because interrupt is disabled  
Main Processing  
INTxx  
INTyy  
Servicing  
Servicing  
IE=0  
EI  
INTyy  
(PR=0)  
INTxx  
(PR=0)  
RETI  
IE=0  
1 Instruction  
Execution  
RETI  
Because interrupts are disabled during interrupt INTxx servicing (EI instruction is not issued), interrupt request  
INTyy is not acknowledged, and a multiple interrupt is not generated. INTyy request is reserved and acknowledged  
after execution of one main processing instruction.  
PR = 0  
IE = 0  
:
:
High priority level  
Interrupt request acknowledgment disabled  
505  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.4.5 Interrupt request reserve  
In some cases, the acknowledgment of the interrupt request is reserved even an interrupt request is generated  
during processing of the instruction until the execution of the next instruction is completed. The following shows this  
type of instructions (interrupt request reserve instruction).  
• MOV  
PSW, #byte  
• MOV A, PSW  
• MOV  
• MOV1  
• MOV1  
• AND1  
• OR1  
• XOR1  
• SET1  
• CLR1  
• RETB  
• RETI  
• PUSH  
• POP  
• BT  
PSW, A  
PSW.bit, CY  
CY, PSW.bit  
CY, PSW.bit  
CY, PSW.bit  
CY, PSW.bit  
PSW.bit  
PSW.bit  
PSW  
PSW  
PSW.bit, $addr16  
PSW.bit, $addr16  
PSW.bit, $addr16  
• BF  
• BTCLR  
• EI  
• DI  
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers  
Caution The BRK instruction is not an interrupt request reserve instruction shown above. However, in  
the case of software interrupt that is started up with the execution of the BRK instruction, the  
IE flag is cleared to 0. Therefore, interrupts are not acknowledged even when a maskable  
interrupt request is issued during the execution of the BRK instruction. However, non-maskable  
interrupt requests are acknowledged.  
Figure 21-17 shows the timing when an interrupt request is reserved.  
Figure 21-17. Interrupt Request Hold  
Save PSW and PC,  
Jump to interrupt service  
Interrupt service  
program  
CPU processing  
Instruction N  
Instruction M  
× × IF  
Remarks 1. Instruction N: Instruction that holds interrupts requests  
2. Instruction M: Instructions other than instruction N  
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).  
506  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
21.5 Test Functions  
Upon occurrence of watch timer overflow and the detection of the falling falling edge of port 4, the corresponding  
test input flag is set (1) and a standby release signal is generated. Unlike in the case of interrupt functions, vector  
processing is not performed.  
There are two test input sources as shown in Table 21-5. The basic configuration is shown in Figure 21-18.  
Table 21-5. Test Input Factors  
Test Input Factors  
Trigger  
Internal/  
external  
Name  
INTWT  
INTPT4  
Watch timer overflow  
Internal  
External  
Falling edge detection at port 4  
Figure 21-18. Basic Configuration of Test Function  
Internal bus  
MK  
Test input  
signal  
Standby  
release signal  
IF  
Remark IF: test input flag  
MK: test mask flag  
21.5.1 Registers controlling the test function  
The test function is controlled by the following three registers.  
• Interrupt request flag register 1L (IF1L)  
• Interrupt mask flag register 1L (MK1L)  
• Key return mode register (KRM)  
The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table  
21-6.  
Table 21-6. Flags Corresponding to Test Input Signals  
Test input signal name  
INTWT  
Test input flag  
WTIF  
KRIF  
Test mask flag  
WTMK  
KRMK  
INTPT4  
507  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(1) Interrupt request flag register 1L (IF1L)  
It indicates whether a watch timer overflow is detected or not.  
It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction.  
It is set to 00H by the RESET signal input.  
Figure 21-19. Format of Interrupt Request Flag Register 1L  
When  
Reset  
Address  
FFE2H  
R/W  
R/W  
Symbol <7>  
IF1L WTIF  
6
0
5
0
4
0
3
0
<2> <1> <0>  
00H  
ADIF TMIF2 TMIF1  
WTIF  
Watch timer overflow detection flag  
Not detected  
Detected  
0
1
Caution Be sure to set bits 3 through 6 to 0.  
(2) Interrupt mask flag register 1L (MK1L)  
It is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer.  
It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction.  
It is set to FFH by the RESET signal input.  
Figure 21-20. Format of Interrupt Mask Flag Register 1L  
When  
Reset  
Address  
FFE6H  
R/W  
R/W  
Symbol <7>  
MK1L WTMK  
6
1
5
1
4
0
3
0
<2> <1> <0>  
FFH  
ADMK TMMK2 TMMK1  
WTMK  
Standby mode control by watch timer  
Enables releasing the standby mode.  
Disables releasing the standby mode.  
0
1
Caution Be sure to set bits 3 through 6 to 1.  
508  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS  
(3) Key return mode register (KRM)  
This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge  
detection).  
KRM is set with a 1-bit or 8-bit memory manipulation instruction.  
RESET input sets KRM to 02H.  
Figure 21-21. Key Return Mode Register Format  
When  
Reset  
Address  
FFF6H  
R/W  
R/W  
Symbol  
KRM  
7
0
6
0
5
0
4
0
3
0
2
0
<1> <0>  
02H  
KRMK KRIF  
KRIF  
Key Return Signal  
0
1
Not detected  
Detected (port 4 falling edge detection)  
KRMK  
Standby Mode Control by Key Return Signal  
Standby mode release enabled  
0
1
Standby mode release disabled  
Caution When port 4 falling edge detection is used, be sure to clear KRIF to 0 (not cleared to 0  
automatically)  
21.5.2 Test input signal acknowledge operation  
(1) Internal test signal  
The internal test input signal (INTWT) is generated with watch timer overflow, and the WTIF flag is set. If not  
masked with bit 7 (WTMK) of interrupt mask flag register 1L (MK1L) at this time, a standby release signal is  
generated. The watch function is available by checking the WTIF flag using a shorter cycle than the watch  
timer overflow cycle.  
(2) External test signal  
When a falling edge (external test input signal) is input to the port 4 (P40 to P47) pins, KRIF is set. If not masked  
with bit 1 (KRMK) of key return mode register (KRM) at this time, a standby release signal is generated. If  
port 4 is used as key matrix return signal input, whether or not a key input has been applied can be checked  
from the KRIF status.  
509  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
510  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
22.1 External Device Expansion Functions  
The external device expansion functions connect external devices to areas other than the internal ROM, RAM,  
and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe,  
wait, address strobe etc.  
Table 22-1. Pin Functions in External Memory Expansion Mode  
Pin function at external device connection  
Alternate function  
Name  
Function  
AD0 to AD7  
A8 to A15  
RD  
Multiplexed address/data bus  
Address bus  
P40 to P47  
P50 to P57  
P64  
Read strobe signal  
Write strobe signal  
Wait signal  
WR  
P65  
WAIT  
P66  
ASTB  
Address strobe signal  
P67  
Table 22-2. State of Ports 4 to 6 Pins in External Memory Expansion Mode  
Ports and bits  
Port 4  
0-7  
Port 5  
Port 6  
Modes  
0
1
2
3
4
5
6
7
0-3  
Port  
Port  
Port  
Port  
Port  
4-7  
Single-chip mode  
Port  
Port  
Port  
Port  
256-byte expansion mode  
4K-byte expansion mode  
16K-byte expansion mode  
Full address mode  
Address/data  
Address/data  
Address/data  
Address/data  
RD, WR, WAIT, ASTB  
RD, WR, WAIT, ASTB  
RD, WR, WAIT, ASTB  
RD, WR, WAIT, ASTB  
Address  
Address  
Address  
Port  
Port  
Caution  
When the external wait function is not used, the WAIT pin can be used as a port in all modes.  
511  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Memory maps when using the external device expansion function are as follows.  
Figure 22-1. Memory Map when Using External Device Expansion Function (1/4)  
(a) Memory map of µPD78P054, 78P058,  
78P058Y when the µPD78052, 78052Y  
and internal PROM are 16 Kbytes  
(b) Memory map of µPD78P054, 78P058,  
78P058Y when the µPD78053, 78053Y  
and internal PROM are 24 Kbytes  
FFFFH  
FFFFH  
SFR  
SFR  
FF00H  
FEFFH  
FF00H  
FEFFH  
Internal High-Speed RAM  
Internal High-Speed RAM  
FD00H  
FCFFH  
FB00H  
FAFFH  
Reserved  
Reserved  
FAE0H  
FADFH  
FAE0H  
FADFH  
Internal Buffer RAM  
Internal Buffer RAM  
FAC0H  
FABFH  
Reserved  
FA80H  
FA7FH  
FAC0H  
FABFH  
Reserved  
FA80H  
FA7FH  
Full-Address Mode  
(when MM2-MM0=111)  
Full-Address Mode  
(when MM2-MM0=111)  
A000H  
9FFFH  
16-Kbyte Expansion Mode  
(when MM2-MM0=101)  
8000H  
7FFFH  
7000H  
6FFFH  
16-Kbyte Expansion Mode  
(when MM2-MM0=101)  
4-Kbyte Expansion Mode  
(when MM2-MM0=100)  
6100H  
60FFH  
5000H  
4FFFH  
256-byte Expansion Mode  
(when MM2-MM0=011)  
4-Kbyte Expansion Mode  
(when MM2-MM0=100)  
6000H  
5FFFH  
4100H  
40FFH  
256-byte Expansion Mode  
(when MM2-MM0=011)  
4000H  
3FFFH  
Single-chip Mode  
Single-chip Mode  
0000H  
0000H  
512  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-1. Memory Map when Using External Device Expansion Function (2/4)  
(c) Memory map of µPD78P054, 78P058,  
78P058Y when the µPD78054, 78054Y  
and internal PROM are 32 Kbytes  
(d) Memory map of µPD78P058, 78P058Y  
when the µPD78055, 78055Y and  
internal PROM are 40 Kbytes  
FFFFH  
FFFFH  
SFR  
SFR  
FF00H  
FEFFH  
FF00H  
FEFFH  
Internal High-Speed RAM  
Internal High-Speed RAM  
FB00H  
FB00H  
FAFFH  
Reserved  
FAFFH  
Reserved  
FAE0H  
FADFH  
FAE0H  
FADFH  
Internal Buffer RAM  
Internal Buffer RAM  
FAC0H  
FABFH  
Reserved  
FA80H  
FA7FH  
FAC0H  
FABFH  
Reserved  
FA80H  
FA7FH  
Full-Address Mode  
(when MM2-MM0=111)  
Full-Address Mode  
(when MM2-MM0=111)  
E000H  
DFFFH  
16-Kbyte Expansion Mode  
(when MM2-MM0=101)  
C000H  
BFFFH  
16-Kbyte Expansion Mode  
(when MM2-MM0=101)  
B000H  
AFFFH  
4-Kbyte Expansion Mode  
(when MM2-MM0=100)  
9000H  
8FFFH  
A100H  
A0FFH  
4-Kbyte Expansion Mode  
(when MM2-MM0=100)  
256-byte Expansion Mode  
(when MM2-MM0=011)  
8100H  
80FFH  
A000H  
9FFFH  
256-byte Expansion Mode  
(when MM2-MM0=011)  
8000H  
7FFFH  
Single-chip Mode  
Single-chip Mode  
0000H  
0000H  
513  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-1. Memory Map when Using External Device Expansion Function (3/4)  
(e) Memory map of µPD78P058, 78P058Y  
when the µPD78056, 78056Y and  
internal PROM are 48 Kbytes  
FFFFH  
SFR  
FF00H  
FEFFH  
Internal High-Speed RAM  
FB00H  
FAFFH  
Reserved  
FAE0H  
FADFH  
Internal Buffer RAM  
FAC0H  
FABFH  
Reserved  
FA80H  
FA7FH  
Full-Address Mode  
(when MM2-MM0=111)  
or  
16-Kbyte Expansion Mode  
(when MM2-MM0=101)  
D000H  
CFFFH  
4-Kbyte Expansion Mode  
(when MM2-MM0=100)  
C100H  
C0FFH  
256-byte Expansion Mode  
(when MM2-MM0=011)  
C000H  
BFFFH  
Single-chip Mode  
0000H  
514  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-1. Memory Map when Using External Device Expansion Function (4/4)  
(f) µPD78058, 78058Y, 78P058, 78P058Y Memory  
map when internal ROM (PROM) size is  
56 Kbytes  
(g)  
µPD78058, 78058Y, 78P058, 78P058Y Memory  
map when internal ROM (PROM) size is  
60 Kbytes  
FFFFH  
FFFFH  
SFR  
SFR  
FF00H  
FEFFH  
FF00H  
FEFFH  
Internal High-Speed RAM  
Internal High-Speed RAM  
FB00H  
FAFFH  
FB00H  
FAFFH  
Reserved  
Reserved  
FAE0H  
FAE0H  
FADFH  
FADFH  
Internal Buffer RAM  
Internal Buffer RAM  
FAC0H  
FABFH  
Reserved  
F800H  
FAC0H  
FABFH  
Reserved  
F800H  
F7FFH  
F7FFH  
Internal Expansion RAM  
Internal Expansion RAM  
F400H  
F3FFH  
F400H  
F3FFH  
Full-Address Mode  
(when MM2-MM0=111)  
or  
Reserved  
16-Kbyte Expansion Mode  
(when MM2-MM0=101)  
F000H  
EFFFH  
F000H  
EFFFH  
4-Kbyte Expansion Mode  
(when MM2-MM0=100)  
E100H  
F0FFH  
256-byte Expansion Mode  
(when MM2-MM0=011)  
E000H  
DFFFH  
Single-chip mode  
Single-chip Mode  
0000H  
0000H  
Caution When the internal ROM (PROM) size is 60 Kbytes, the area from F000H to F3FFH cannot be used.  
F000H to F3FFH can be used as external memory by setting the internal ROM (PROM) size to  
less than 56 Kbytes by the memory size switching register (IMS).  
515  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
22.2 External Device Expansion Function Control Register  
The external device expansion function is controlled by the memory expansion mode register (MM) and memory  
size switching register (IMS).  
(1) Memory expansion mode register (MM)  
MM sets the wait count and external expansion area, and also sets the input/output of port 4.  
MM is set with an 1-bit memory or 8-bit memory manipulation instruction.  
RESET input sets this register to 10H.  
Figure 22-2. Memory Expansion Mode Register Format  
When  
Reset  
Address  
FFF8H  
R/W  
R/W  
Symbol  
MM  
7
0
6
0
5
4
3
0
2
1
0
10H  
PW1 PW0  
MM2 MM1 MM0  
Single-chip/  
Memory Expansion  
Mode Selection  
P40-P47, P50-P57, P64-P67 Pin state  
MM2 MM1 MM0  
P40-P47 P50-P53  
P64-P67  
P54, P55  
P56, P57  
0
0
0
0
0
1
Input  
Port  
mode  
Single-chip mode  
Port mode  
Output  
256-byte  
mode  
0
1
1
1
1
0
0
1
1
0
1
1
Port mode  
P64=RD  
4K-byte  
mode  
Port mode  
P65=WR  
P66=WAIT  
P67=ASTB  
Memory  
expansion  
mode  
AD0-AD7  
16K-byte  
mode  
A8-A11  
Port mode  
A14, A15  
A12, A13  
Full  
address  
modeNote  
Other than above  
Setting prohibited  
PW1 PW0  
Wait Control  
0
0
0
1
No wait  
Wait (one wait state insertion)  
Setting prohibited  
1
1
0
1
Wait control by external wait pin  
Note  
The full address mode allows external expansion to the entire 64-Kbyte address space except for  
the internal ROM, RAM, and SFR areas and the reserved areas.  
Remark P60 to P63 enter the port mode without regard to the mode (single-chip mode or memory expansion  
mode).  
516  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
(2) Memory size switching register (IMS)  
This register specifies the internal memory size. In principle, use IMS in a default status. However, when  
using the external device expansion function with the µPD78058, set IMS so that the internal ROM capacity  
is 56 Kbytes or lower.  
IMS is set with an 8-bit memory manipulation instruction.  
RESET input sets this register to the value indicated in Table 22-3.  
Figure 22-3. Memory Size Switching Register Format  
After  
Reset  
Symbol  
7
6
5
4
0
3
2
1
0
Address  
FFF0H  
R/W  
R/W  
IMS RAM2 RAM1 RAM0  
ROM3 ROM2 ROM1 ROM0  
Note  
ROM3 ROM2 ROM1 ROM0 Internal ROM size selection  
0
0
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
16 Kbytes  
24 Kbytes  
32 Kbytes  
40 Kbytes  
48 Kbytes  
56 Kbytes  
60 Kbytes  
Setting prohibited  
Other than above  
RAM2 RAM1 RAM0 Internal high-speed RAM size selection  
0
1
1
1
0
0
512 bytes  
1024 bytes  
Other than above  
Setting prohibited  
Note The values after reset depend on the product. (See Table 22-3)  
Table 22-3. Values when the Memory Size Switching Register is Reset  
Part number  
Reset value  
44H  
µPD78052, 78052Y  
µPD78053, 78053Y  
µPD78054, 78054Y  
µPD78055, 78055Y  
µPD78056, 78056Y  
µPD78058, 78058Y  
C6H  
C8H  
CAH  
CCH  
CFH  
517  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
22.3 External Device Expansion Function Timing  
Timing control signal output pins in the external memory expansion mode are as follows.  
(1) RD pin (Alternate function: P64)  
Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from  
external memory.  
During internal memory access, the read strobe signal is not output (maintains high level).  
(2) WR pin (Alternate function: P65)  
Write strobe signal output pin. The write strobe signal is output in data access to external memory.  
During internal memory access, the write strobe signal is not output (maintains high level).  
(3) WAIT pin (Alternate function: P66)  
External wait signal input pin. When the external wait is not used, the WAIT pin can be used as an input/output  
port.  
During internal memory access, the external wait signal is ignored.  
(4) ASTB pin (Alternate function: P67)  
Address strobe signal output pin. Timing signal is output without regard to the data accesses and instruction  
fetches from external memory. The ASTB signal is also output when the internal memory is accessed.  
(5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57)  
Address/data signal output pin. Valid signal is output or input during data accesses and instruction fetches  
from external memory.  
These signals change when the internal memory is accessed (output values are undefined).  
Timing charts are shown in Figure 22-4 to 22-7.  
518  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-4. Instruction Fetch from External Memory  
(a) No wait (PW1, PW0 = 0, 0) setting  
ASTB  
RD  
AD0-AD7  
A8-A15  
Lower Address  
Operation Code  
Higher Address  
(b) Wait (PW1, PW0 = 0, 1) setting  
ASTB  
RD  
AD0-AD7  
A8-A15  
Lower Address  
Operation Code  
Higher Address  
Internal Wait Signal  
(1-clock wait)  
(c) External wait (PW1, PW0 = 1, 1) setting  
ASTB  
RD  
AD0-AD7  
Lower Address  
Operation Code  
Higher Address  
A8-A15  
WAIT  
519  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-5. External Memory Read Timing  
(a) No wait (PW1, PW0 = 0, 0) setting  
ASTB  
RD  
AD0-AD7  
A8-A15  
Lower Address  
Read Data  
Higher Address  
(b) Wait (PW1, PW0 = 0, 1) setting  
ASTB  
RD  
AD0-AD7  
A8-A15  
Lower Address  
Read Data  
Higher Address  
Internal Wait Signal  
(1-clock wait)  
(c) External wait (PW1, PW0 = 1, 1) setting  
ASTB  
RD  
AD0-AD7  
Lower Address  
Read Data  
A8-A15  
WAIT  
Higher Address  
520  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-6. External Memory Write Timing  
(a) No wait (PW1, PW0 = 0, 0) setting  
ASTB  
WR  
Hi-Z  
AD0-AD7  
A8-A15  
Lower Address  
Write Data  
Higher Address  
(b) Wait (PW1, PW0 = 0, 1) setting  
ASTB  
WR  
Hi-Z  
Lower Address  
Write Data  
AD0-AD7  
A8-A15  
Higher Address  
Internal Wait Signal  
(1-clock wait)  
(c) External wait (PW1, PW0 = 1, 1) setting  
ASTB  
WR  
Hi-Z  
Lower Address  
AD0-AD7  
Write Data  
A8-A15  
WAIT  
Higher Address  
521  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
Figure 22-7. External Memory Read Modify Write Timing  
(a) No wait (PW1, PW0 = 0, 0) setting  
ASTB  
RD  
WR  
Hi-Z  
Lower Address  
Read Data  
Write Data  
AD0-AD7  
A8-A15  
Higher Address  
(b) Wait (PW1, PW0 = 0, 1) setting  
ASTB  
RD  
WR  
Hi-Z  
Lower Address  
Read Data  
Write Data  
AD0-AD7  
A8-A15  
Higher Address  
Internal Wait Signal  
(1-clock wait)  
(c) External wait (PW1, PW0 = 1, 1) setting  
ASTB  
RD  
WR  
Hi-Z  
Lower Address  
AD0-AD7  
Read Data  
Write Data  
Higher Address  
A8-A15  
WAIT  
522  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION  
22.4 Example of Connection with Memory  
This section provides µPD78054 and external memory connection examples in Figure 22-8. SRAMs are used as  
the external memory in these diagrams. In addition, the external device expansion function is used in the full-address  
mode, and the address from 0000H to 7FFFH (32 Kbytes) are allocated for internal ROM, and the addresses after  
8000H for SRAM.  
Figure 22-8. Connection Example of µPD78054 and Memory  
VDD  
VDD  
µPD78054  
µPD43256B  
CS  
RD  
OE  
Data  
Bus  
WR  
WE  
I/O1-I/O8  
A0-A14  
A8-A14  
Address  
Bus  
µPD74HC573  
ASTB  
LE  
Q0-Q7  
D0-D7  
OE  
AD0-AD7  
523  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
524  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
23.1 Standby Function and Configuration  
23.1.1 Standby function  
The standby function is designed to decrease power consumption of the system. The following two modes are  
available.  
(1) HALT mode  
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.  
System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in  
the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out  
intermittent operations such as in watch applications.  
(2) STOP mode  
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops  
and the whole system stops. CPU current consumption can be considerably decreased.  
Data memory low-voltage hold (down to VDD = 1.8 V) is possible. Thus, the STOP mode is effective to hold  
data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt  
request, it enables intermittent operations to be carried out.  
However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode  
is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request.  
In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The  
input/output port output latch and output buffer statuses are also held.  
Cautions 1. The STOP mode can be used only when the system operates with the main system clock  
(subsystem clock oscillation cannot be stopped). The HALT mode can be used with either  
the main system clock or the subsystem clock.  
2. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and  
execute the STOP instruction.  
3. The following sequence is recommended for power consumption reduction of the A/D  
converter when the standby function is used: first clear bit 7 (CS) of A/D converter mode  
register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP  
instruction.  
525  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
23.1.2 Standby function control register  
A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with  
the oscillation stabilization time select register (OSTS).  
OSTS is set with an 8-bit memory manipulation instruction.  
17  
18  
RESET input sets OSTS to 04H. However, it takes 2 /fX, not 2 /fX, until the STOP mode is cleared by RESET  
input.  
Figure 23-1. Oscillation Stabilization Time Select Register Format  
After  
Reset  
Symbol  
OSTS  
7
0
6
0
5
0
4
0
3
0
2
1
0
Address  
FFFAH  
R/W  
R/W  
OSTS2 OSTS1 OSTS0  
04H  
Selection of Oscillation Stabilization  
Time when STOP Mode is Released  
OSTS2OSTS1OSTS0  
MCS = 1  
MCS = 0  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
212/fxx 212/fx(819ms)  
213/fx(1.64 ms)  
214/fxx 214/fx(3.28 ms) 215/fx(6.55 ms)  
215/fxx 215/fx(6.55 ms) 216/fx(13.1 ms)  
216/fxx 216/fx(13.1 ms) 217/fx(26.2 ms)  
217/fxx 217/fx(26.2 ms) 218/fx(52.4 ms)  
Other than above Setting prohibited  
Caution The wait time after STOP mode clear does not include the time (see "a" in the illustration below)  
from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by  
interrupt request generation.  
STOP Mode Clear  
X1 Pin  
Voltage  
Waveform  
a
VSS  
Remarks 1. fXX  
:Main system clock frequency (fX or fX/2)  
:Main system clock oscillation frequency  
2. fX  
3. MCS :Bit 0 of oscillation mode select register (OSMS)  
4. Values in parentheses apply to operating at fX = 5.0 MHz  
526  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
23.2 Standby Function Operations  
23.2.1 HALT mode  
(1) HALT mode set and operating status  
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the  
subsystem clock.  
The operating status in the HALT mode is described below.  
Table 23-1. HALT Mode Operating Status  
Setting of HALT Mode  
On Execution of HALT Instruction during Main  
System Clock Operation  
On Execution of HALT Instruction during  
Subsystem Clock Operation  
Without subsystem  
With subsystem  
When main system clock When main system  
Note 1  
Note 1  
Item  
clock  
clock  
continues oscillation  
clock stops oscillation  
Clock generator  
CPU  
Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops.  
Operation stops.  
Port (output latch)  
16-bit timer/event counter  
Status before HALT mode setting is held.  
Operable.  
Operable when watch  
timer output is selected  
as count clock (fXT is  
selected as count clock  
of watch timer) or when  
TI00 is selected.  
8-bit timer/event counter  
Watch timer  
Operable.  
Operable when TI1 or  
TI2 is selected as  
count clock.  
7
Operable when fXX/2 is Operable.  
selected as count clock.  
Operable when fXT is  
selected as count clock.  
Watchdog timer  
A/D converter  
Operable.  
Operable.  
Operable.  
Operable.  
Operable.  
Operation stops.  
Operation stops.  
D/A converter  
Real-time output port  
Serial interface  
Other than  
Operable when  
automatic  
transmit/  
receive  
external SCK is used.  
function  
Automatic  
transmit/  
receive  
Operation stops.  
function  
External interrupt  
INTP0  
INTP0 is operable when clock supplied for peripheral hardware is selected  
Operation stops.  
5
6
7
as sampling clock (fXX/2 , fXX/2 , fXX/2 ).  
INTP1-INTP6  
AD0-AD7  
A0-A15  
Operable.  
Bus line for  
external  
High impedance.  
Status before HALT mode setting is held.  
Low level.  
expansion  
ASTB  
WR, RD  
WAIT  
High level.  
High impedance.  
Notes 1. Including when external clock is not supplied  
2. Including when external clock is supplied  
527  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
(2) HALT mode clear  
The HALT mode can be cleared with the following four types of sources.  
(a) Clear upon unmasked interrupt request  
When an unmasked interrupt request is generated, the HALT mode is cleared. If interrupt request  
acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction  
is executed.  
Figure 23-2. HALT Mode Clear upon Interrupt Request Generation  
HALT  
Instruction  
Interrupt  
Request  
Wait  
Wait  
Standby  
Release Signal  
Operating  
Mode  
HALT Mode  
Operating Mode  
Oscillation  
Clock  
Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby  
status is acknowledged.  
2. Wait time will be as follows:  
• When vectored interrupt service is carried out:  
8 to 9 clocks  
• When vectored interrupt service is not carried out: 2 to 3 clocks  
(b) Clear upon non-maskable interrupt request  
When a non-maskable interrupt request is generated, the HALT mode is cleared and vectored interrupt  
service is carried out whether interrupt acknowledge is enabled or disabled.  
(c) Clear upon unmasked test input  
When an unmasked test signal is input, the HALT mode is cleared and the next address instruction of  
the HALT instruction is executed.  
528  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
(d) Clear upon RESET input  
When a RESET signal is input, the HALT mode is released, and as is the case with normal reset  
operation, a program is executed after branch to the reset vector address.  
Figure 23-3. HALT Mode Release by RESET Input  
Wait  
(217/fx : 26.2 ms)  
HALT  
Instruction  
RESET  
Signal  
Oscillation  
Operating  
Mode  
Reset  
Period  
Stabilization  
Wait Status  
Operating  
Mode  
HALT Mode  
Oscillation  
Oscillation  
stop  
Oscillation  
Clock  
Remarks 1. fX: main system clock oscillation frequency  
2. ( ): fX: 5.0 MHz  
Table 23-2. Operation after HALT Mode Release  
Release Source  
Maskable interrupt  
request  
MK××  
PR××  
IE  
0
ISP  
×
Operation  
0
0
0
0
0
1
0
0
1
1
1
×
Next address instruction execution  
Interrupt service execution  
1
×
0
1
Next address instruction execution  
×
1
0
1
Interrupt service execution  
HALT mode hold  
×
×
×
Non-maskable interrupt  
request  
×
Interrupt service execution  
Test input  
0
1
×
×
×
×
×
×
Next address instruction execution  
HALT mode hold  
RESET input  
Reset processing  
Remark x: Don't care  
529  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
23.2.2 STOP mode  
(1) STOP mode set and operating status  
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.  
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor  
to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode  
in a system where an external clock is used for the main system clock.  
2. Because the interrupt request signal is used to clear the standby mode, if there is an  
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the  
standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT  
mode immediately after execution of the STOP instruction. After the wait set using the  
oscillation stabilization time select register (OSTS), the operating mode is set.  
The operating status in the STOP mode is described below.  
Table 23-3. STOP Mode Operating Status  
Setting of STOP Mode  
With subsystem clock  
Without subsystem clock  
Item  
Clock generator  
CPU  
Only main system clock stops oscillation.  
Operation stops.  
Port (output latch)  
16-bit timer/event counter  
Status before STOP mode setting is held.  
Operable when watch timer output is  
selected as count clock (fXT is selected as  
count clock of watch timer)  
Operation stops.  
8-bit timer/event counter  
Watch timer  
Operable when TI1 and TI2 are selected for the count clock.  
Operable when fXT is selected for the  
count clock.  
Operation stops.  
Watchdog timer  
A/D converter  
Operation stops.  
D/A converter  
Operable.  
Real-time output port  
Operable when external trigger is used or TI1 and TI2 are selected for the 8-bit  
timer/event counter count clock.  
Serial interface  
Other than  
Operable when externally supplied clock is specified as the serial clock.  
automatic  
transmit/receive  
function and  
UART  
Automatic  
Operation stops.  
transmit/receive  
function and  
UART  
External interrupt INTP0  
INTP1-INTP6  
Not operable.  
Operable.  
Bus line for  
external  
AD0-AD7  
A0-A15  
ASTB  
High impedance.  
Status before STOP mode setting is held.  
Low level.  
expansion  
WR, RD  
WAIT  
High level.  
High impedance.  
530  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
(2) STOP mode release  
The STOP mode can be cleared with the following three types of sources.  
(a) Release by unmasked interrupt request  
When an unmasked interrupt request is generated, the STOP mode is cleared. If interrupt request  
acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried  
out. If interrupt request acknowledge is disabled, the next address instruction is executed.  
Figure 23-4. STOP Mode Release by Interrupt Request Generation  
Wait  
Interrupt  
Request  
STOP  
Instruction  
(Time set by OSTS)  
Standby  
Release Signal  
Operationg  
Mode  
Oscillation Stabilization  
Wait Status  
Operating  
Mode  
STOP Mode  
Oscillation  
Oscillation Stop  
Oscillation  
Clock  
Remark The broken line indicates the case when the interrupt request which has cleared the standby  
status is acknowledged.  
(b) Release by unmasked test input  
When an unmasked test signal is input, the STOP mode is cleared. And after the lapse of oscillation  
stabilization time, the instruction at the next address of the STOP instruction is executed.  
531  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 23 STANDBY FUNCTION  
(c) Release by RESET input  
When a RESET signal is input, the STOP mode is released. And after the lapse of oscillation stabilization  
time, reset operation is carried out.  
Figure 23-5. Release by STOP Mode RESET Input  
Wait  
(217/fx : 26.2 ms)  
STOP  
Instruction  
RESET  
Signal  
Oscillation  
Operating  
Mode  
Reset  
Period  
Stabilization  
Wait Status  
Operating  
Mode  
STOP Mode  
Oscillation  
Oscillation Stop  
Oscillation  
Clock  
Remarks 1. fX: main system clock oscillation frequency  
2. ( ): fX: 5.0 MHz  
Table 23-4. Operation after STOP Mode Release  
Release Source  
MK××  
PR××  
IE  
0
ISP  
×
×
1
Operation  
Maskable interrupt request  
0
0
0
0
0
1
0
1
0
0
1
1
1
×
Next address instruction execution  
Interrupt service execution  
1
0
Next address instruction execution  
×
1
0
1
Interrupt service execution  
STOP mode hold  
×
×
×
×
×
×
×
×
Test input  
Next address instruction execution  
STOP mode hold  
RESET input  
Reset processing  
Remark ×: Don't care  
532  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 24 RESET FUNCTION  
24.1 Reset Function  
The following two operations are available to generate the reset signal.  
(1) External reset input with RESET pin  
(2) Internal reset by watchdog timer overrun time detection  
External reset and internal reset have no functional differences. In both cases, program execution starts at the  
address at 0000H and 0001H by RESET input.  
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware  
is set to the status as shown in Table 24-1. Each pin has high impedance during reset input or during oscillation  
stabilization time just after reset clear.  
When a high level is input to the RESET input, the reset is cleared and program execution starts after the lapse  
17  
of oscillation stabilization time (2 /fX). The reset applied by watchdog timer overflow is automatically cleared after  
17  
a reset and program execution starts after the lapse of oscillation stabilization time (2 /fX) (see Figure 24-2 to 24-  
4).  
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.  
2. During reset input, main system clock oscillation remains stopped but subsystem clock  
oscillation continues.  
3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.  
However, the port pin becomes high-impedance.  
Figure 24-1. Block Diagram of Reset Function  
Reset  
Signal  
RESET  
Reset Control Circuit  
Over-  
flow  
Interrupt  
Function  
Watchdog Timer  
Stop  
Count Clock  
533  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 24 RESET FUNCTION  
Figure 24-2. Timing of Reset Input by RESET Input  
X1  
Oscillation  
Stabilization  
Time Wait  
Reset Period  
(Oscillation  
Stop)  
Normal Operation  
(Reset Processing)  
Normal Operation  
RESET  
Internal  
Reset Signal  
Delay  
Delay  
Hi-Z  
Port Pin  
Figure 24-3. Timing of Reset due to Watchdog Timer Overflow  
X1  
Reset Period  
(Oscillation  
Stop)  
Oscillation  
Stabilization  
Time Wait  
Normal Operation  
(Reset Processing)  
Normal Operation  
Watchdog  
Timer  
Overflow  
Internal  
Reset Signal  
Hi-Z  
Port Pin  
Figure 24-4. Timing of Reset Input in STOP Mode by RESET Input  
X1  
STOP Instruction Execution  
Stop Status  
(Oscillation  
Stop)  
Reset Period  
(Oscillation  
Stop)  
Oscillation  
Stabilization  
Time Wait  
Normal Operation  
(Reset Processing)  
Normal Operation  
RESET  
Internal  
Reset Signal  
Delay  
Delay  
Hi-Z  
Port Pin  
534  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 24 RESET FUNCTION  
Table 24-1. Hardware Status after Reset (1/2)  
Hardware  
Status after Reset  
Note1  
Program counter (PC)  
Stack pointer (SP)  
The contents of reset vector  
tables (0000H and 0001H)  
are set.  
Undefined  
02H  
Program status word (PSW)  
RAM  
Note2  
Data memory  
Undefined  
Note2  
General register  
Undefined  
Ports 0 to 3, Port 7, Port 12, Port 13  
(P0 to P3, P7, P12, P13)  
00H  
Port (Output latch)  
Ports 4 to 6 (P4 to P6)  
Undefined  
FFH  
Port mode register (PM0 to PM3, PM5 to PM7, PM12, PM13)  
Pull-up resistor option register (PUOH, PUOL)  
Processor clock control register (PCC)  
00H  
04H  
Oscillation mode selection register (OSMS)  
Memory size switching register (IMS)  
00H  
Note3  
Note4  
Internal expansion RAM size switching register (IXS)  
0AH  
10H  
Memory expansion mode register (MM)  
Oscillation stabilization time select register (OSTS)  
Timer register (TM0)  
04H  
0000H  
Undefined  
00H  
Capture/compare register (CR00, CR01)  
Clock selection register (TCL0)  
Mode control register (TMC0)  
Capture/compare control register 0 (CRC0)  
Output control register (TOC0)  
Timer register (TM1, TM2)  
16-bit timer/event counter  
00H  
04H  
00H  
00H  
Compare registers (CR10, CR20)  
Clock select register (TCL1)  
Undefined  
00H  
8-bit timer/event counter  
1 and 2  
Mode control registers (TMC1)  
Output control register (TOC1)  
00H  
00H  
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware  
statuses become undefined. All other hardware statuses remains unchanged after reset.  
2. When reset in the standby mode, the state before reset is held even after reset.  
3. The values after reset depend on the product.  
µPD78052, 78052Y : 44H, µPD78053, 78053Y : C6H, µPD78054, 78054Y : C8H,  
µPD78P054 : C8H, µPD78055, 78055Y : CAH, µPD78056, 78056Y : CCH,  
µPD78058, 78058Y : CFH, µPD78P058, 78P058Y: CFH  
4. Provided only in the µPD78058, 78058Y, 78P058, and 78P058Y.  
535  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 24 RESET FUNCTION  
Table 24-1. Hardware Status after Reset (2/2)  
Hardware  
Status after Reset  
Watch timer  
Mode control register (TMC2)  
00H  
00H  
Clock select register (TCL2)  
Watchdog timer  
Serial interface  
Mode register (WDTM)  
00H  
Clock select register (TCL3)  
88H  
Shift registers (SIO0, SIO1)  
Undefined  
00H  
Mode registers (CSIM0, CSIM1, CSIM2)  
Serial bus interface control register (SBIC)  
Slave address register (SVA)  
00H  
Undefined  
00H  
Automatic data transmit/receive control register (ADTC)  
Automatic data transmit/receive address pointer (ADTP)  
Automatic data transmit/receive interval specify register (ADTI)  
Asynchronous serial interface mode register (ASIM)  
Asynchronous serial interface status register (ASIS)  
Baud rate generator control register (BRGC)  
Transmit shift register (TXS)  
00H  
00H  
00H  
00H  
00H  
FFH  
Receive buffer register (RXB)  
Interrupt timing specify register (SINT)  
Mode register (ADM)  
00H  
01H  
A/D converter  
Conversion result register (ADCR)  
Input select register (ADIS)  
Undefined  
00H  
D/A converter  
Mode register (DAM)  
00H  
Conversion value setting register (DACS0, DACS1)  
Mode register (RTPM)  
00H  
Real-time output port  
00H  
Control register (RTPC)  
00H  
Buffer register (RTBL, RTBH)  
00H  
(Note)  
ROM correction  
Correction address register (CORAD0, CORAD1)  
Correction control register (CORCN)  
Request flag register (IF0L, IF0H, IF1L)  
Mask flag register (MK0L, MK0H, MK1L)  
Priority specify flag register (PR0L, PR0H, PR1L)  
External interrupt mode register (INTM0, INTM1)  
Key return mode register (KRM)  
Sampling clock select register (SCS)  
0000H  
00H  
Interrupt  
00H  
FFH  
FFH  
00H  
02H  
00H  
Note Provided only in the µPD78058, 78058Y, 78P058, 78P058Y.  
536  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
25.1 ROM Correction Functions  
The µPD78058, 78058Y subseries can replace part of a program in the mask ROM with a program in the internal  
expansion RAM.  
Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM  
correction.  
The ROM correction can correct two places (max.) of the internal ROM (program).  
Caution The ROM correction cannot be emulated by the in-circuit emulator (IE-78000-R, IE-78000-R-A,  
IE-78K0-NS, IE-78001-R-A).  
25.2 ROM Correction Configuration  
The ROM correction is executed by the following hardware.  
Table 25-1. ROM Correction Configuration  
Item  
Configuration  
Register  
Correction address registers 0 and 1 (CORAD0, CORAD1)  
Correction control register (CORCN)  
Control register  
Figure 25-1 shows a block diagram of the ROM correction.  
Figure 25-1. Block Diagram of ROM Correction  
Program counter (PC)  
Comparator  
Match  
Correction branch request  
signal (BR !7FDH)  
Correction address  
register (CORADn)  
CORENn CORSTn  
Correction control register  
Internal bus  
Remark n = 0, 1  
537  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
(1) Correction address registers 0 and 1 (CORAD0, CORAD1)  
These registers set the start address (correction address) of the instruction(s) to be corrected in the mask  
ROM.  
The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0  
and CORAD1. If only one place needs to be corrected, set the address to either of the registers.  
CORAD0 and CORAD1 are set with a 16-bit memory manipulation instruction.  
RESET input sets CORAD0 and CORAD1 to 0000H.  
Figure 25-2. Correction Address Registers 0 and 1 Format  
State  
Symbol  
15  
0
Address  
R/W  
R/W  
after reset  
CORAD0  
FF38H/FF39H  
0000H  
CORAD1  
FF3AH/FF3BH  
0000H  
R/W  
Cautions 1. Set the CORAD0 and CORAD1 when bit 1 (COREN0) and bit 3 (COREN1) of the correction  
control register (CORCN : see Figure 25-3) are 0.  
2. Only addresses where operation codes are stored can be set in CORAD0 and CORAD1.  
3. Do not set the following addresses to CORAD0 and CORAD1.  
• Address value in table area of table reference instruction (CALLT instruction) : 0040H  
to 007FH  
• Address value in vector table area : 0000H to 003FH  
(2) Comparator  
The comparator always compares the correction address value set in correction address registers 0 and 1  
(CORAD0, CORAD1) with the fetch address value. When bit 1 (COREN0) or bit 3 (COREN1) of the correction  
control register (CORCN) is 1 and the correction address matches the fetch address value, the correction  
branch request signal (BR !F7FDH) is generated from the ROM correction circuit.  
538  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
25.3 ROM Correction Control Registers  
The ROM correction is controlled with the correction control register (CORCN).  
(1) Correction control register (CORCN)  
This register controls whether or not the correction branch request signal is generated when the fetch  
address matches the correction address set in correction address registers 0 and 1. The correction control  
register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0,  
CORST1). The correction enable flags enable or disable the comparator match detection signal, and  
correction status flags show the values are matched. CORCN is set with a 1-bit or 8-bit memory manipulation  
instruction.  
RESET input sets CORCN to 00H.  
Figure 25-3. Correction Control Register Format  
State  
Symbol  
CORCN  
7
0
6
0
5
0
4
0
<3> <2> <1> <0>  
Address  
FF8AH  
R/W  
after reset  
COREN1 CORST1 COREN0 CORST0  
R/W Note  
00H  
CORST0  
Correction address register 0 and fetch address match detection  
0
1
Not detected  
Detected  
Correction address register 0 and fetch address match  
detection control  
COREN0  
0
1
Disabled  
Enabled  
CORST1  
Correction address register 1 and fetch address match detection  
Not detected  
Detected  
0
1
Correction address register 1 and fetch address match  
detection control  
COREN1  
Disabled  
Enabled  
0
1
Note Bits 0 and 2 are read-only bits.  
539  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
25.4 ROM Correction Application  
(1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as  
TM  
EEPROM ) outside the microcontroller.  
When two places should be corrected, store the branch destination judgment program as well. The branch  
destination judgment program checks which one of the addresses set to CORAD0 or CORAD1 generates the  
correction branch.  
Figure 25-4. Storing Example to EEPROM (when one place is corrected)  
Source program  
CSEG AT 1000H  
EEPROM  
00  
10  
0D  
02  
9B  
02  
10  
00H  
01H  
02H  
ADD  
BR  
A, #2  
RA78K/0  
!1002H  
FFH  
Figure 25-5. Connecting Example with EEPROM (using 2-wire serial I/O mode)  
EEPROM  
PD78058, 78058Y  
µ
VDD  
VDD  
VDD  
CE  
SCK0  
SB1  
SCL  
SDA  
CS  
P32  
540  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
(2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program.  
Figure 25-6. Initialization Routine  
Initialization  
ROM correction  
No  
Is ROM  
correction used ?  
Note  
Yes  
Load the contents of external nonvolatile memory  
into internal expansion RAM  
Correction address register setting  
ROM correction enabled  
Main program  
Note Whether the ROM correction is used or not should be judged by the port input level. For example, when  
the P20 input level is high, the ROM correction is used, otherwise, it is not used.  
(3) After reset, store the contents that have been previously stored in the external nonvolatile memory with  
initialization routine for ROM correction of the user to internal expansion RAM (see Figure 25-6).  
Set the start address of the instruction to be corrected to CORAD0 and CORAD1, and set bits 1 and 3  
(COREN0, COREN1) of the correction control register (CORCN) to 1.  
(4) Set the entire-space branch instruction (BR !addr16) to the specified address (F7FDH) of the internal  
expansion RAM with the main program.  
(5) After the main program is started, the fetch address value and the values set in CORAD0 and CORAD1 are  
always compared by the comparator in the ROM correction circuit. When these values match, the correction  
branch request signal is generated. Simultaneously the corresponding correction status flag (CORST0 or  
CORST1) is set to 1.  
(6) Branch to the address F7FDH by the correction branch request signal.  
(7) Branch to the internal expansion RAM address set with the main program by the entire-space branch  
instruction of the address F7FDH.  
(8) When one place is corrected, the correction program is executed. When two places are corrected, the  
correction status flag is checked with the branch destination judgment program, and branches to the correction  
program.  
541  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
Figure 25-7. ROM Correction Operation  
Internal ROM program start  
Does fetch address  
match with correction  
address?  
No  
Yes  
ROM correction  
Set correction status flag  
Correction branch  
(branch to address F7FDH)  
Correction program execution  
542  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
25.5 ROM Correction Example  
The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2”  
is as follows.  
Figure 25-8. ROM Correction Example  
Internal expansion RAM  
F400H  
Internal ROM  
0000H  
0080H  
Program start  
F702H  
ADD A, #2  
BR !1002H  
(3)  
ADD A, #1  
MOV B, A  
1000H  
1002H  
(2)  
(1)  
F7FDH  
F7FFH  
BR !F702H  
EFFFH  
(1) Branches to address F7FDH when the preset value 1000H in the correction address register matches the fetch  
address value after the main program is started.  
(2) Branches to any address (address F702H in this example) by setting the entire-space branch instruction (BR  
!addr16) to address F7FDH with the main program.  
(3) Returns to the internal ROM program after executing the substitute instruction ADD A, #2.  
543  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
25.6 Program Execution Flow  
Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used.  
Figure 25-9. Program Transition Diagram (when one place is corrected)  
FFFFH  
F7FFH  
BR !JUMP  
F7FDH  
(2)  
Correction program  
JUMP  
(1)  
(3)  
Internal ROM  
Correction place  
xxxxH  
Internal ROM  
0000H  
(1) Branches to address F7FDH when fetch address matches correction address  
(2) Branches to correction program  
(3) Returns to internal ROM program  
Remark Area filled with diagonal lines : Internal expansion RAM  
JUMP : Correction program start address  
544  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
Figure 25-10. Program Transition Diagram (when two places are corrected)  
FFFFH  
F7FFH  
F7FDH  
(6)  
BR !JUMP  
(2)  
Correction program 2  
yyyyH  
(7)  
Correction program 1  
xxxxH  
(3)  
Destination judge program  
(8)  
JUMP  
(4)  
(5)  
Internal ROM  
Correction place 2  
Internal ROM  
(1)  
Correction place 1  
Internal ROM  
0000H  
(1) Branches to address F7FDH when fetch address matches correction address  
(2) Branches to branch destination judgment program  
(3) Branches to correction program 1 by branch destination judgment program (BTCLR !CORST0, $xxxxH)  
(4) Returns to internal ROM program  
(5) Branches to address F7FDH when fetch address matches correction address  
(6) Branches to branch destination judgment program  
(7) Branches to correction program 2 by branch destination judgment program (BTCLR !CORST1, $yyyyH)  
(8) Returns to internal ROM program  
Remark Area filled with diagonal lines : Internal expansion RAM  
JUMP : Destination judge program start address  
545  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 25 ROM CORRECTION  
25.7 Cautions on ROM Correction  
(1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where  
instruction codes are stored.  
(2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag  
(COREN0, COREN1) is 0 (when the correction branch is in disabled state). If address is set to CORAD0 or  
CORAD1 when COREN0 or COREN1 is 1 (when the correction branch is in enabled state), the correction  
branch may start with the different address from the set address value.  
(3) Do not set the address value of instruction immediately after the instruction that sets the correction enable  
flag (COREN0, COREN1) to 1, to correction address register 0 or 1 (CORAD0, CORAD1) ; the correction  
branch may not start.  
(4) Do not set the address value in table area of table reference instruction (CALLT instruction) (0040H to 007FH),  
and the address value in vector table area (0000H to 003FH) to correction address registers 0 and 1 (CORAD0,  
CORAD1).  
(5) Do not set two addresses immediately after the instructions shown below to correction address registers 0  
and 1 (CORAD0, CORAD1). (that is, when the mapped terminal address of these instructions is N, do not  
set the address values of N+1 and N+2.)  
• RET  
• RETI  
• RETB  
• BR $addr16  
• STOP  
• HALT  
546  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
The µPD78054, 78054Y subseries include the µPD78P054, 78P058, 78P058Y as PROM versions.  
For purposes of simplification, in this chapter, the description of the µPD78P058 applies to both the µPD78P058  
and 78P058Y. Similarly, the µPD78052, 78053, 78054, 78055, 78056, and 78058 are treated as the representative  
models of the mask ROM products.  
The µPD78P054, 78P058 replace the internal mask ROM of the µPD78054, 78058 with one-time PROM or  
EPROM. Table 26-1 lists the differences among the µPD78P054, 78P058 and the mask ROM versions. Table 26-  
2 lists the differences between the µPD78P054 and the µPD78P058.  
Table 26-1. Differences between µPD78P054, 78P058 and Mask ROM Versions  
Item  
Internal ROM structure  
Internal ROM capacity  
µPD78P054, 78P058  
Mask ROM version  
Mask ROM  
One-time PROM/EPROM  
µPD78P054: 32 Kbytes  
µPD78P058: 60 Kbytes  
µPD78052: 16 Kbytes  
µPD78053: 24 Kbytes  
µPD78054: 32 Kbytes  
µPD78055: 40 Kbytes  
µPD78056: 48 Kbytes  
µPD78058: 60 Kbytes  
Internal high-speed RAM capacity  
1024 bytes  
µPD78052: 512 bytes  
µPD78053: 1024 bytes  
µPD78054: 1024 bytes  
µPD78055: 1024 bytes  
µPD78056: 1024 bytes  
µPD78058: 1024 bytes  
Internal expansion RAM capacity  
µPD78P054: None  
µPD78P058: 1024 bytes  
µPD78052: None  
µPD78053: None  
µPD78054: None  
µPD78055: None  
µPD78056: None  
µPD78058: 1024 bytes  
Note 1  
Changing internal ROM and internal high- Enable  
speed RAM capacities with memory size  
switching register  
Disable  
Note 2  
Changing of internal expansion RAM  
capacity by internal expansion RAM size  
switching register  
Enable with µPD78P058 only  
Disable  
IC pin  
None  
Available  
None  
VPP pin  
Available  
None  
Mask option with on-chip pull-up resistor  
for P60 to P63 pins  
None  
Electrical characteristics  
Refer to the separate Data Sheet.  
547  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
Notes 1. The internal ROM and internal high-speed RAM capacities are set as follows by RESET input:  
Internal PROM: 32K bytes (µPD78P054), 60K bytes (µPD78P058)  
Internal high-speed RAM: 1024 bytes  
2. The internal expansion RAM is set to 1024 bytes by RESET input.  
Caution The noise immunity and noise radiation differ between PROM versions and mask ROM versions.  
When considering replacement of PROM versions with mask ROM versions in the stage between  
test production and mass production, evaluate thoroughly with CS products (not ES products)  
of the mask ROM versions.  
Remarks 1. The µPD78P054 is a PROM model corresponding to the µPD78052, 78053, and 78054.  
The µPD78P058 is a PROM model corresponding to the µPD78055, 78056, and 78058.  
2. Only the µPD78058 and 78P058 are provided with an internal expansion RAM size switching  
register.  
Table 26-2. Differences between µPD78P054 and 78P058  
Item  
µPD78P054  
32 Kbytes  
µPD78P058  
60 Kbytes  
1024 bytes  
Provided  
Internal PROM  
Internal expansion RAM  
Internal expansion RAM  
size switching register  
Not provided  
Not provided  
548  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.1 Memory Size Switching Register (µPD78P054)  
The µPD78P054 allows users to define its internal ROM and high-speed RAM sizes using the memory size  
switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal  
ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction.  
RESET input sets IMS to C8H.  
Figure 26-1. Memory Size Switching Register Format (µPD78P054)  
After  
Reset  
Address  
FFF0H  
R/W  
R/W  
Symbol  
7
6
5
4
0
3
2
1
0
C8H  
IMS RAM2 RAM1 RAM0  
ROM3 ROM2 ROM1 ROM0  
ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity selection  
0
0
1
1
1
0
0
1
0
0
0
0
16 Kbytes  
24 Kbytes  
32 Kbytes  
Other than above  
Setting prohibited  
RAM2 RAM1 RAM0 Internal High-Speed RAM Capacity Selection  
0
1
1
1
0
0
512 bytes  
1024 bytes  
Other than above  
Setting prohibited  
The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-3.  
Table 26-3. Examples of Memory Size Switching Register Settings (µPD78P054)  
Relevant Mask ROM Version  
µPD78052  
IMS Setting  
44H  
µPD78053  
C6H  
µPD78054  
C8H  
549  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.2 Memory Size Switching Register (µPD78P058)  
The µPD78P058 allows users to define its internal ROM and high-speed RAM sizes using the memory size  
switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal  
ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction.  
RESET input sets IMS to CFH.  
Figure 26-2. Memory Size Switching Register Format (µPD78P058)  
After  
Reset  
Address  
FFF0H  
R/W  
R/W  
Symbol  
7
6
5
4
0
3
2
1
0
CFH  
IMS RAM2 RAM1 RAM0  
ROM3 ROM2 ROM1 ROM0  
ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity selection  
0
0
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
16 Kbytes  
24 Kbytes  
32 Kbytes  
40 Kbytes  
48 Kbytes  
56 Kbytes  
60 Kbytes  
Setting prohibited  
Other than above  
RAM2 RAM1 RAM0 Internal High-Speed RAM Capacity Selection  
0
1
1
1
0
0
512 bytes  
1024 bytes  
Other than above  
Setting prohibited  
The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-4.  
Table 26-4. Examples of Memory Size Switching Register Settings (µPD78P058)  
Relevant Mask ROM Version  
µPD78052, 78052Y  
µPD78053, 78053Y  
µPD78054, 78054Y  
µPD78055, 78055Y  
µPD78056, 78056Y  
µPD78058, 78058Y  
IMS Setting  
44H  
C6H  
C8H  
CAH  
CCH  
CFH  
550  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.3 Internal Expansion RAM Size Switching Register  
The µPD78P058 allows users to define its internal expansion RAM size using the internal expansion RAM size  
switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different-size internal  
expansion RAM is possible. The IXS is set by an 8-bit memory manipulation instruction.  
RESET signal input sets IXS to 0AH.  
Figure 26-3. Internal Expansion RAM Size Switching Register Format  
After  
Reset  
Address  
FFF4H  
R/W  
W
Symbol  
IXS  
7
0
6
0
5
0
4
0
3
2
1
0
0AH  
IXRAM3 IXRAM2 IXRAM1 IXRAM0  
IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal extension RAM capacity selection  
1
1
1
0
0
1
0
0
0 bytes  
1024 bytes  
Other than above  
Setting prohibited  
The value in the IXS that has the identical memory map to the mask ROM versions is given in Table 26-5.  
Table 26-5. Value Set to the Internal Expansion RAM Size Switching Register  
Pertinent mask ROM versions  
µPD78052, 78052Y  
µPD78053, 78053Y  
µPD78054, 78054Y  
µPD78055, 78055Y  
µPD78056, 78056Y  
µPD78058, 78058Y  
Value set to IXS  
0CH  
0AH  
Remark If a program for the µPD78P058 or 78P058Y which  
includes “MOV IXS, #0CH” is implemented with the  
µPD78055, 78055Y, 78056, or 78056Y, this  
instruction is ignored and causes no malfunction.  
551  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.4 PROM Programming  
The µPD78P054 and 78P058 incorporate a 32-Kbyte and 60-Kbyte PROM as program memory, respectively.  
To write a program into the µPD78P054 or 78P058 PROM, make the device enter the PROM programming mode  
by setting the levels of the VPP and RESET pins as specified. For the connection of unused pins, see paragraph  
(2) “PROM programming mode” in section 1.5 or 2.5 Pin Configuration (Top View).  
Caution In case of the µPD78P054, write the program in the range of addresses 0000H to 7FFFH (specify  
the last address as 7FFFH.)  
In case of the µPD78P058, write the program in the range of addresses 0000H to EFFFH (specify  
the last address as EFFFH.)  
The program cannot be correctly written by a PROM programmer which does not have a write  
address specification function.  
26.4.1 Operating modes  
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the µPD78P054  
and µPD78P058 are set to the PROM programming mode. This is one of the operating modes shown in Table 26-  
6 below according to the setting of the CE, OE, and PGM pins.  
The PROM contents can be read by setting the read mode.  
Table 26-6. PROM Programming Operating Modes  
Pin  
RESET  
VPP  
VDD  
CE  
OE PGM  
D0-D7  
Data input  
Operating mode  
Page data latch  
Page write  
H
H
L
L
H
H
L
H
L
High impedance  
Data input  
Byte write  
L
+12.5 V +6.5 V  
Program verify  
L
H
H
L
Data output  
L
×
×
L
H
L
Program inhibit  
High impedance  
Read  
L
H
×
×
Data output  
Output disabled  
Standby  
+5 V  
+5V  
L
H
×
High impedance  
High impedance  
H
Remark ×: L or H  
(1) Read mode  
Read mode is set by setting CE to L and OE to L.  
(2) Output disable mode  
If OE is set to H, data output becomes high impedance and the output disable mode is set.  
Therefore, if multiple µPD78P054s or 78P058s are connected to the data bus, data can be read from any one  
device by controlling the OE pin.  
552  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
(3) Standby mode  
Setting CE to H sets the standby mode.  
In this mode, data output becomes high impedance irrespective of the status of OE.  
(4) Page data latch mode  
Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.  
In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.  
(5) Page write mode  
After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed  
by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=H and OE=H. After this, program  
verification can be performed by setting CE to L and OE to L.  
If programming is not performed by one program pulse, repeated write and verify operations are executed  
X times (X 10).  
(6) Byte write mode  
A byte write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=L and OE=H.  
After this, program verification can be performed by setting OE to L.  
If programming is not performed by one program pulse, repeated write and verify operations are executed  
X times (X 10).  
(7) Program verify mode  
Setting CE to L, PGM to H, and OE to L sets the program verify mode.  
After writing is performed, this mode should be used to check whether the data was written correctly.  
(8) Program inhibit mode  
The program inhibit mode is used when the OE pins, VPP pins and pins D0 to D7 of multiple µPD78P054s  
or 78P058s are connected in parallel and any one of these devices must be written to.  
The page write mode or byte write mode described above is used to perform a write. At this time, the write  
is not performed on the device which has the PGM pin driven high.  
553  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.4.2 PROM write procedure  
Figure 26-4. Page Program Mode Flowchart  
Start  
Address = G  
VDD = 6.5 V, VPP= 12.5 V  
Remark:  
G = Start address  
N = Last address of program  
X = 0  
Latch  
Address = Address + 1  
Latch  
Address = Address + 1  
Latch  
Address = Address + 1  
Latch  
Address = Address + 1  
X = X + 1  
No  
Yes  
X = 10?  
0.1-ms program pulse  
Fail  
Verify 4 Bytes  
Pass  
No  
Address = N?  
Yes  
VDD = 4.5 to 5.5 V, VPP= VDD  
Fail  
Pass  
All bytes verified?  
All Pass  
End of write  
Defective product  
554  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
Figure 26-5. Page Program Mode Timing  
Page  
Program  
Page Data Latch  
Program Verify  
A2-A16  
A0, A1  
D0-D7  
Hi-Z  
Data Input  
Data Output  
VPP  
VPP  
VDD  
VDD+1.5  
VDD  
VDD  
VIH  
CE  
VIL  
VIH  
VIL  
VIH  
PGM  
OE  
VIL  
555  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
Figure 26-6. Byte Program Mode Flowchart  
Start  
Remark:  
Address = G  
G = Start address  
N = Last address of program  
VDD = 6.5 V, VPP= 12.5 V  
X = 0  
X = X + 1  
No  
X = 10?  
Yes  
0.1-ms program pulse  
Address = Address + 1  
Fail  
Verify  
Pass  
No  
Address = N?  
Yes  
VDD = 4.5 to 5.5 V, VPP= VDD  
Pass  
Fail  
All bytes verified?  
All Pass  
End of write  
Defective product  
556  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
Figure 26-7. Byte Program Mode Timing  
Program  
Program Verify  
A0-A16  
D0-D7  
Hi-Z  
Data Input  
Data Output  
VPP  
VPP  
VDD  
VDD  
VDD+1.5  
VDD  
VIH  
CE  
PGM  
OE  
VIL  
VIH  
VIL  
VIH  
VIL  
Cautions 1. Be sure to apply VDD before applying VPP, and remove it after removing VPP.  
2. VPP must not exceed +13.5 V including overshoot voltage.  
3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied  
to the VPP pin may have an adverse affect on device reliability.  
557  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.4.3 PROM reading procedure  
PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.  
(1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in paragraph,  
(2) “PROM programming mode” in section 1.5 or 2.5 Pin Configuration (Top View).  
(2) Supply +5 V to the VDD and VPP pins.  
(3) Input the address of data to be read to pins A0 through A16.  
(4) Read mode is entered.  
(5) Data is output to pins D0 through D7.  
The timing for steps (2) through (5) above is shown in Figure 26-8.  
Figure 26-8. PROM Read Timing  
A0-A16  
Address Input  
CE (Input)  
OE (Input)  
D0-D7  
Hi-Z  
Hi-Z  
Data Output  
558  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 26 µPD78P054, 78P058  
26.5 Erasure Procedure (µPD78P054KK-T and 78P058KK-T Only)  
With the µPD78P054KK-T or 78P058KK-T, it is possible to erase ( or set all contents to FFH) the data contents  
written in the program memory, and rewrite the memory.  
The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter.  
Typically, data is erased by 254-nm ultraviolet light rays. The minimum lighting level to completely erase the written  
data is shown below.  
2
• UV intensity × exposure time: 30 W.s/cm or more  
• Exposure time: 40 minutes or more (using a 12 mW/cm ultraviolet lamp. A longer exposure time may be  
2
required in case of deterioration of the ultraviolet lamp or dirt on the package window).  
When erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube.  
26.6 Opaque Film Masking the Window (µPD78P054KK-T and 78P058KK-T Only)  
To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from mulfunction  
due to light coming in through the erasure window, mask the window with opaque film after writing the EPROM.  
26.7 Screening of One-Time PROM Versions  
One-time PROM versions (µPD78P054GC-3B9, 78P054GC-8BT, 78P054GK-BE9, 78P058GC-8BT, and  
78P058YGC-8BT) cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore,  
after users have written data into the PROM, screening should be implemented by user: that is, store devices at  
high temperature for one day as specified below, and verify their contents after the devices have returned to room  
temperature.  
Storage Temperature  
Storage Time  
24 hours  
125°C  
For users who do not wish to implement screening by themselves, NEC provides such users with a charged  
service in which NEC performs a series of processes from writing one-time PROMs and screening them to verifying  
TM  
their contents for users by request. The PROM version devices which provide this service are called QTOP  
microcontrollers. For details, please consult an NEC sales representative.  
559  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
560  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
This chapter describes each instruction set of the µPD78054 and 78054Y subseries as list table. For details of  
its operation and operation code, refer to the separate document “78K/0 Series User’s Manual, Instruction  
(U12326E).”  
561  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
27.1 Legends Used in Operation List  
27.1.1 Operand identifiers and description methods  
Operands are described in “Operand” column of each instruction in accordance with the description method of  
the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more  
description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and  
must be described as they are. Each symbol has the following meaning.  
• # : Immediate data specification  
• ! : Absolute address specification  
• $ : Relative address specification  
• [ ] : Indirect address specification  
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to  
describe the #, !, $, and [ ] symbols.  
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in  
parentheses in the table below, R0, R1, R2, etc.) can be used for description.  
Table 27-1. Operand Identifiers and Description Methods  
Identifier  
Description Method  
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),  
AX (RP0), BC (RP1), DE (RP2), HL (RP3)  
rp  
Note  
sfr  
sfrp  
Special-function register symbol  
Note  
Special-function register symbol (16-bit manipulatable register even addresses only)  
saddr  
FE20H-FF1FH Immediate data or labels  
saddrp  
FE20H-FF1FH Immediate data or labels (even address only)  
addr16  
0000H-FFFFH Immediate data or labels  
(Only even addresses for 16-bit data transfer instructions)  
0800H-0FFFH Immediate data or labels  
addr11  
addr5  
0040H-007FH Immediate data or labels (even address only)  
word  
byte  
bit  
16-bit immediate data or label  
8-bit immediate data or label  
3-bit immediate data or label  
RBn  
RB0 to RB3  
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.  
Remark For special-function register symbols, refer to Table 5-6. Special-Function Register List.  
562  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
27.1.2 Description of “operation” column  
A
: A register; 8-bit accumulator  
: X register  
X
B
: B register  
C
: C register  
D
: D register  
E
: E register  
H
: H register  
L
: L register  
AX  
BC  
DE  
HL  
PC  
SP  
: AX register pair; 16-bit accumulator  
: BC register pair  
: DE register pair  
: HL register pair  
: Program counter  
: Stack pointer  
PSW : Program status word  
CY  
AC  
Z
: Carry flag  
: Auxiliary carry flag  
: Zero flag  
RBS : Register bank select flag  
IE : Interrupt request enable flag  
NMIS : Non-maskable interrupt servicing flag  
( )  
: Memory contents indicated by address or register contents in parentheses  
: Higher 8 bits and lower 8 bits of 16-bit register  
: Logical product (AND)  
×
H, ×  
L
: Logical sum (OR)  
: Exclusive logical sum (exclusive OR)  
: Inverted data  
addr16 : 16-bit immediate data or label  
jdisp8 : Signed 8-bit data (displacement value)  
27.1.3 Description of “flag operation” column  
(Blank) : Nt affected  
0
: Cleared to 0  
1
: Set to 1  
×
R
: Set/cleared according to the result  
: Previously saved value is restored  
563  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
27.2 Operation List  
Clock  
Flag  
Instruction  
Mnemonic  
Group  
Operands  
r, #byte  
Byte  
Operation  
Note 1 Note 2  
Z
AC CY  
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
4
6
2
2
4
4
8
8
4
4
4
4
8
8
6
6
6
6
2
4
8
4
4
8
8
8
7
7
5
5
5
5
r byte  
(saddr) byte  
sfr byte  
A r  
saddr, #byte  
sfr, #byte  
A, r  
Note 3  
Note 3  
r, A  
r A  
A, saddr  
saddr, A  
A, sfr  
A (saddr)  
(saddr) A  
A sfr  
sfr, A  
sfr A  
A, !addr16  
!addr16, A  
PSW, #byte  
A, PSW  
9 + n A (addr16)  
9 + m (addr16) A  
7
5
5
PSW byte  
A PSW  
PSW A  
×
×
×
×
×
×
PSW, A  
MOV  
A, [DE]  
5 + n A (DE)  
5 + m (DE) A  
5 + n A (HL)  
5 + m (HL) A  
8-bit data  
transfer  
[DE], A  
A, [HL]  
[HL], A  
A, [HL + byte]  
[HL + byte], A  
A, [HL + B]  
[HL + B], A  
A, [HL + C]  
[HL + C], A  
A, r  
9 + n A (HL + byte)  
9 + m (HL + byte) A  
7 + n A (HL + B)  
7 + m (HL + B) A  
7 + n A (HL + C)  
7 + m (HL + C) A  
Note 3  
6
6
A r  
A, saddr  
A, sfr  
A (saddr)  
A sfr  
A, !addr16  
A, [DE]  
10 + n + m A (addr16)  
6 + n + m A (DE)  
XCH  
A, [HL]  
6 + n + m A (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
10 + n + m A (HL + byte)  
10 + n + m A (HL + B)  
10 + n + m A (HL + C)  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
3. Except "r = A"  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
4. m is the number of waits when external memory expansion area is written to.  
564  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
rp, #word  
Byte  
Operation  
Note 1 Note 2  
Z
AC CY  
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
6
8
6
6
4
4
10  
10  
8
rp word  
saddrp, #word  
sfrp, #word  
AX, saddrp  
saddrp, AX  
AX, sfrp  
(saddrp) word  
sfrp word  
AX (saddrp)  
(saddrp) AX  
AX sfrp  
8
16-bit  
data  
MOVW  
8
sfrp, AX  
8
sfrp AX  
transfer  
Note 3  
Note 3  
AX, rp  
AX rp  
rp, AX  
rp AX  
AX, !addr16  
!addr16, AX  
AX, rp  
10 12 + 2n AX (addr16)  
10 12 + 2m (addr16) AX  
Note 3  
Note 4  
XCHW  
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
8
5
AX rp  
A, #byte  
A, CY A + byte  
(saddr), CY (saddr) + byte  
A, CY A + r  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte  
A, r  
r, A  
r, CY r + A  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A + (saddr)  
ADD  
9 + n A, CY A + (addr16)  
5 + n A, CY A + (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
A, #byte  
9 + n A, CY A + (HL + byte)  
9 + n A, CY A + (HL + B)  
9 + n A, CY A + (HL + C)  
8-bit  
operation  
8
5
A, CY A + byte + CY  
(saddr), CY (saddr) + byte + CY  
A, CY A + r + CY  
saddr, #byte  
A, r  
Note 4  
r, A  
r, CY r + A + CY  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A + (saddr) + CY  
ADDC  
9 + n A, CY A + (addr16) + CY  
5 + n A, CY A + (HL) + CY  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
9 + n A, CY A + (HL + byte) + CY  
9 + n A, CY A + (HL + B) + CY  
9 + n A, CY A + (HL + C) + CY  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
3. Only when rp = BC, DE or HL  
4. Except "r = A"  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
4. m is the number of waits when external memory expansion area is written to.  
565  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
A, #byte  
Byte  
Operation  
A, CY A – byte  
Note 1 Note 2  
Z
AC CY  
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
8
5
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte  
A, r  
(saddr), CY (saddr) – byte  
A, CY A – r  
Note 3  
Note 3  
Note 3  
r, A  
r, CY r – A  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A – (saddr)  
SUB  
9 + n A, CY A – (addr16)  
5 + n A, CY A – (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
A, #byte  
saddr, #byte  
A, r  
9 + n A, CY A – (HL + byte)  
9 + n A, CY A – (HL + B)  
9 + n A, CY A – (HL + C)  
8
5
A, CY A – byte – CY  
(saddr), CY (saddr) – byte – CY  
A, CY A – r – CY  
r, A  
r, CY r – A – CY  
A, saddr  
A, !addr16  
A, [HL]  
A, CY A – (saddr) – CY  
8-bit  
SUBC  
operation  
9 + n A, CY A – (addr16) – CY  
5 + n A, CY A – (HL) – CY  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
A, #byte  
saddr, #byte  
A, r  
9 + n A, CY A – (HL + byte) – CY  
9 + n A, CY A – (HL + B) – CY  
9 + n A, CY A – (HL + C) – CY  
8
5
A A byte  
(saddr) (saddr) byte  
A A r  
r, A  
r r A  
A, saddr  
A, !addr16  
A, [HL]  
A A (saddr)  
AND  
9 + n A A (addr16)  
5 + n A A (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
9 + n A A (HL + byte)  
9 + n A A (HL + B)  
9 + n A A (HL + C)  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
3. Except "r = A"  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
566  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
A, #byte  
Byte  
Operation  
Note 1 Note 2  
Z
AC CY  
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
8
5
A A byte  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte  
A, r  
(saddr) (saddr) byte  
A A r  
Note 3  
Note 3  
Note 3  
r, A  
r r A  
A, saddr  
A, !addr16  
A, [HL]  
A A (saddr)  
OR  
9 + n A A (addr16)  
5 + n A A (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
A, #byte  
saddr, #byte  
A, r  
9 + n A A (HL + byte)  
9 + n A A (HL + B)  
9 + n A A (HL + C)  
8
5
A A byte  
(saddr) (saddr) byte  
A A r  
r, A  
r r A  
A, saddr  
A, !addr16  
A, [HL]  
A A (saddr)  
8-bit  
XOR  
operation  
9 + n A A (addr16)  
5 + n A A (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
A, #byte  
saddr, #byte  
A, r  
9 + n A A (HL + byte)  
9 + n A A (HL + B)  
9 + n A A (HL + C)  
8
5
A – byte  
(saddr) – byte  
A – r  
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, A  
r – A  
A, saddr  
A, !addr16  
A, [HL]  
A – (saddr)  
CMP  
9 + n A – (addr16)  
5 + n A – (HL)  
A, [HL + byte]  
A, [HL + B]  
A, [HL + C]  
9 + n A – (HL + byte)  
9 + n A – (HL + B)  
9 + n A – (HL + C)  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
3. Except "r = A"  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
567  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
AX, #word  
Byte  
Operation  
AX, CY AX + word  
Note 1 Note 2  
Z
×
×
×
AC CY  
ADDW  
SUBW  
CMPW  
MULU  
DIVUW  
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
6
6
6
6
×
×
×
×
×
×
16-bit  
AX, #word  
AX, CY AX – word  
AX – word  
operation  
AX, #word  
6
X
16  
25  
2
AX A × X  
Multiply/  
divide  
C
AX (Quotient), C (Remainder) AX ÷ C  
r r + 1  
r
×
×
×
×
×
×
×
×
INC  
saddr  
r
4
(saddr) (saddr) + 1  
r r – 1  
Increment/  
decrement  
2
DEC  
saddr  
rp  
4
(saddr) (saddr) – 1  
rp rp + 1  
INCW  
DECW  
ROR  
4
rp  
4
rp rp – 1  
A, 1  
A, 1  
A, 1  
A, 1  
2
(CY, A7 A0, Am – 1 Am) × 1 time  
(CY, A0 A7, Am + 1 Am) × 1 time  
(CY A0, A7 CY, Am – 1 Am) × 1 time  
(CY A7, A0 CY, Am + 1 Am) × 1 time  
×
×
×
×
ROL  
2
RORC  
ROLC  
2
2
Rotate  
A3 – 0 (HL)3 – 0, (HL)7 – 4 A3 – 0,  
(HL)3 – 0 (HL)7 – 4  
ROR4  
[HL]  
[HL]  
2
2
2
2
10 12 + n + m  
10 12 + n + m  
A3 – 0 (HL)7 – 4, (HL)3 – 0 A3 – 0,  
(HL)7 – 4 (HL)3 – 0  
ROL4  
Decimal Adjust Accumulator after  
Addition  
ADJBA  
ADJBS  
4
4
×
×
×
×
×
×
BCD  
adjust  
Decimal Adjust Accumulator after  
Subtract  
CY, saddr.bit  
CY, sfr.bit  
3
3
2
3
2
3
3
2
3
2
6
4
6
6
4
6
7
7
7
CY (saddr.bit)  
CY sfr.bit  
×
×
×
×
×
CY, A.bit  
CY A.bit  
CY, PSW.bit  
CY, [HL].bit  
saddr.bit, CY  
sfr.bit, CY  
CY PSW.bit  
Bit  
7 + n CY (HL).bit  
MOV1  
manipulate  
8
8
8
(saddr.bit) CY  
sfr.bit CY  
A.bit, CY  
A.bit CY  
PSW.bit, CY  
[HL].bit, CY  
PSW.bit CY  
×
×
8 + n + m (HL).bit CY  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
4. m is the number of waits when external memory expansion area is written to.  
568  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
CY, saddr.bit  
Byte  
Operation  
CY CY (saddr.bit)  
Note 1 Note 2  
Z
AC CY  
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
6
4
6
6
4
6
6
4
6
4
4
6
4
4
6
2
2
2
7
7
7
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CY, sfr.bit  
CY, A.bit  
CY, PSW.bit  
CY, [HL].bit  
CY, saddr.bit  
CY, sfr.bit  
CY, A.bit  
CY, PSW.bit  
CY, [HL].bit  
CY, saddr.bit  
CY, sfr.bit  
CY, A.bit  
CY, PSW. bit  
CY, [HL].bit  
saddr.bit  
sfr.bit  
CY CY sfr.bit  
CY CY A.bit  
CY CY PSW.bit  
AND1  
7 + n CY CY (HL).bit  
7
7
7
CY CY (saddr.bit)  
CY CY sfr.bit  
CY CY A.bit  
OR1  
CY CY PSW.bit  
7 + n CY CY (HL).bit  
7
7
7
CY CY (saddr.bit)  
CY CY sfr.bit  
CY CY A.bit  
XOR1  
SET1  
CLR1  
Bit  
manipulate  
CY CY PSW.bit  
7 + n CY CY (HL).bit  
6
8
6
(saddr.bit) 1  
sfr.bit 1  
A.bit  
A.bit 1  
PSW.bit  
[HL].bit  
PSW.bit 1  
×
×
×
×
×
8 + n + m (HL).bit 1  
saddr.bit  
sfr.bit  
6
8
6
(saddr.bit) 0  
sfr.bit 0  
A.bit  
A.bit 0  
PSW.bit  
[HL].bit  
PSW.bit 0  
×
8 + n + m (HL).bit 0  
SET1  
CLR1  
NOT1  
CY  
CY 1  
CY 0  
CY CY  
1
0
×
CY  
CY  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
4. m is the number of waits when external memory expansion area is written to.  
569  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
Byte  
Operation  
Note 1 Note 2  
Z
AC CY  
(SP – 1) (PC + 3)H, (SP – 2) (PC + 3)L,  
PC addr16, SP SP – 2  
CALL  
!addr16  
!addr11  
3
2
7
5
(SP – 1) (PC + 2)H, (SP – 2) (PC + 2)L,  
PC15 – 11 00001, PC10 – 0 addr11,  
SP SP – 2  
CALLF  
CALLT  
(SP – 1) (PC + 1)H, (SP – 2) (PC + 1)L,  
PCH (00000000, addr5 + 1),  
PCL (00000000, addr5),  
SP SP – 2  
[addr5]  
1
6
Call/return  
(SP – 1) PSW, (SP – 2) (PC + 1)H,  
(SP – 3) (PC + 1)L, PCH (003FH),  
PCL (003EH), SP SP – 3, IE 0  
BRK  
RET  
1
1
1
6
6
6
PCH (SP + 1), PCL (SP),  
SP SP + 2  
PCH (SP + 1), PCL (SP),  
PSW (SP + 2), SP SP + 3,  
NMIS 0  
RETI  
RETB  
R
R
R
R
R
R
PCH (SP + 1), PCL (SP),  
PSW (SP + 2), SP SP + 3  
1
1
1
1
1
6
2
4
2
4
PSW  
rp  
(SP – 1) PSW, SP SP – 1  
PUSH  
POP  
(SP – 1) rpH, (SP – 2) rpL,  
SP SP – 2  
PSW  
rp  
PSW (SP), SP SP + 1  
R
R
R
Stack  
manipulate  
rpH (SP + 1), rpL (SP),  
SP SP + 2  
SP, #word  
SP, AX  
AX, SP  
!addr16  
$addr16  
AX  
4
2
2
3
2
2
2
2
2
2
6
6
8
6
6
6
6
10  
8
SP word  
MOVW  
BR  
SP AX  
8
AX SP  
PC addr16  
Uncondi-  
tional  
PC PC + 2 + jdisp8  
PCH A, PCL X  
PC PC + 2 + jdisp8 if CY = 1  
PC PC + 2 + jdisp8 if CY = 0  
PC PC + 2 + jdisp8 if Z = 1  
PC PC + 2 + jdisp8 if Z = 0  
branch  
BC  
$addr16  
$addr16  
$addr16  
$addr16  
BNC  
BZ  
Conditional  
branch  
BNZ  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
570  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Clock  
Flag  
Instruction  
Group  
Mnemonic  
Operands  
Byte  
Operation  
Note 1 Note 2  
Z
AC CY  
saddr.bit, $addr16  
sfr.bit, $addr16  
A.bit, $addr16  
3
4
3
3
3
4
4
3
4
3
8
9
11  
PC PC + 3 + jdisp8 if(saddr.bit) = 1  
PC PC + 4 + jdisp8 if sfr.bit = 1  
PC PC + 3 + jdisp8 if A.bit = 1  
PC PC + 3 + jdisp8 if PSW.bit = 1  
BT  
8
PSW.bit, $addr16  
[HL].bit, $addr16  
saddr.bit, $addr16  
sfr.bit, $addr16  
A.bit, $addr16  
9
10  
10  
11 + n PC PC + 3 + jdisp8 if (HL).bit = 1  
11  
11  
PC PC + 4 + jdisp8 if(saddr.bit) = 0  
PC PC + 4 + jdisp8 if sfr.bit = 0  
PC PC + 3 + jdisp8 if A.bit = 0  
PC PC + 4 + jdisp8 if PSW. bit = 0  
BF  
8
PSW.bit, $addr16  
[HL].bit, $addr16  
11  
10  
11 + n PC PC + 3 + jdisp8 if (HL).bit = 0  
PC PC + 4 + jdisp8  
if(saddr.bit) = 1  
Conditional  
branch  
saddr.bit, $addr16  
4
10  
12  
then reset(saddr.bit)  
PC PC + 4 + jdisp8 if sfr.bit = 1  
then reset sfr.bit  
sfr.bit, $addr16  
A.bit, $addr16  
PSW.bit, $addr16  
[HL].bit, $addr16  
B, $addr16  
4
3
4
3
2
2
3
8
12  
BTCLR  
PC PC + 3 + jdisp8 if A.bit = 1  
then reset A.bit  
PC PC + 4 + jdisp8 if PSW.bit = 1  
then reset PSW.bit  
12  
×
×
×
PC PC + 3 + jdisp8 if (HL).bit = 1  
then reset (HL).bit  
10 12 + n + m  
B B – 1, then  
PC PC + 2 + jdisp8 if B 0  
6
6
8
C C –1, then  
PC PC + 2 + jdisp8 if C 0  
DBNZ  
C, $addr16  
(saddr) (saddr) – 1, then  
PC PC + 3 + jdisp8 if(saddr) 0  
saddr. $addr16  
RBn  
10  
SEL  
NOP  
EI  
2
1
2
2
2
2
4
2
6
6
6
6
RBS1, 0 n  
No Operation  
IE 1(Enable Interrupt)  
IE 0(Disable Interrupt)  
Set HALT Mode  
CPU  
control  
DI  
HALT  
STOP  
Set STOP Mode  
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access.  
2. When an area except the internal high-speed RAM area is accessed.  
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock  
control register (PCC).  
2. This clock cycle applies to internal ROM program.  
3. n is the number of waits when external memory expansion area is read from.  
4. m is the number of waits when external memory expansion area is written to.  
571  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
27.3 Instructions Listed by Addressing Type  
(1) 8-bit instructions  
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,  
ROLC, ROR4, ROL4, PUSH, POP, DBNZ  
572  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
Second Operand  
[HL + byte]  
Note  
#byte  
A
r
sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16  
1
None  
First Operand  
A
[HL + C]  
ADD  
ADDC  
SUB  
SUBC  
AND  
OR  
MOV MOV MOV MOV MOV MOV MOV MOV  
ROR  
XCH XCH XCH XCH  
XCH XCH XCH  
ADD ADD  
ROL  
ADD  
ADDC  
SUB  
SUBC  
AND  
OR  
ADD ADD  
ADDC ADDC  
SUB SUB  
SUBC SUBC  
AND AND  
RORC  
ROLC  
ADDC ADDC  
SUB SUB  
SUBC SUBC  
AND AND  
XOR  
CMP  
OR  
OR  
OR  
OR  
XOR  
CMP  
XOR XOR  
CMP CMP  
XOR XOR  
CMP CMP  
r
MOV MOV  
ADD  
INC  
DEC  
ADDC  
SUB  
SUBC  
AND  
OR  
XOR  
CMP  
B, C  
sfr  
DBNZ  
DBNZ  
MOV MOV  
saddr  
MOV MOV  
ADD  
INC  
DEC  
ADDC  
SUB  
SUBC  
AND  
OR  
XOR  
CMP  
!addr16  
PSW  
MOV  
MOV MOV  
PUSH  
POP  
[DE]  
[HL]  
MOV  
MOV  
ROR4  
ROL4  
[HL + byte]  
[HL + B]  
MOV  
[HL + C]  
X
C
MULU  
DIVUW  
Note Except r = A  
573  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
(2) 16-bit instructions  
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW  
Second Operand  
Note  
#word  
AX  
rp  
sfrp  
saddrp  
MOVW  
!addr16  
MOVW  
SP  
None  
1st Operand  
AX  
ADDW  
SUBW  
CMPW  
MOVW  
XCHW  
MOVW  
MOVW  
Note  
rp  
MOVW  
MOVW  
INCW  
DECW  
PUSH  
POP  
sfrp  
MOVW  
MOVW  
MOVW  
MOVW  
MOVW  
MOVW  
saddrp  
!addr16  
SP  
MOVW  
Note Only when rp = BC, DE, HL  
(3) Bit manipulation instructions  
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR  
Second Operand  
A.bit  
sfr.bit  
saddr.bit  
PSW.bit  
[HL].bit  
CY  
$addr16  
None  
First Operand  
A.bit  
MOV1  
BT  
SET1  
CLR1  
BF  
BTCLR  
sfr.bit  
MOV1  
MOV1  
MOV1  
MOV1  
BT  
SET1  
CLR1  
BF  
BTCLR  
saddr.bit  
PSW.bit  
[HL].bit  
CY  
BT  
SET1  
CLR1  
BF  
BTCLR  
BT  
SET1  
CLR1  
BF  
BTCLR  
BT  
SET1  
CLR1  
BF  
BTCLR  
MOV1  
AND1  
OR1  
MOV1  
MOV1  
AND1  
OR1  
MOV1  
AND1  
OR1  
MOV1  
AND1  
OR1  
SET1  
CLR1  
NOT1  
AND1  
OR1  
XOR1  
XOR1  
XOR1  
XOR1  
XOR1  
574  
Download from Www.Somanuals.com. All Manuals Search And Download.  
CHAPTER 27 INSTRUCTION SET  
(4) Call/instructions/branch instructions  
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ  
Second Operand  
AX  
!addr16  
!addr11  
CALLF  
[addr5]  
CALLT  
$addr16  
BR  
First Operand  
Basic instruction  
BR  
CALL  
BR  
BC  
BNC  
BZ  
BNZ  
Compound  
instruction  
BT  
BF  
BTCLR  
DBNZ  
(5) Other instructions  
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP  
575  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
576  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES  
AND µPD78058F, 78058FY SUBSERIES  
Table A-1 shows the major differences between the µPD78054, 78054Y Subseries and µPD78058F, 78058FY  
Subseries.  
577  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y SUBSERIES AND µPD78058F, 78058FY SUBSERIES  
Table A-1. Major differences between µPD78054, 78054Y Subseries and µPD78058F, 78058FY Subseries  
Part Number  
µPD78054, 78054Y Subseries  
µPD78058F, 78058FY Subseries  
Provided  
Item  
EMI noise measure  
PROM version  
None  
µPD78P054  
µPD78P058F  
µPD78P058  
µPD78P058Y  
µPD78P058Y  
Supply voltage  
VDD = 2.0 to 6.0 V  
VDD = 2.7 to 6.0 V  
Internal ROM capacity  
µPD78052 : 16 Kbytes  
µPD78053 : 24 Kbytes  
µPD78054 : 32 Kbytes  
µPD78P054 : 32 Kbytes  
µPD78055 : 40 Kbytes  
µPD78056 : 48 Kbytes  
µPD78058 : 60 Kbytes  
µPD78P058 : 60 Kbytes  
µPD78052 : 512 bytes  
µPD78053 : 1024 bytes  
µPD78054 : 1024 bytes  
µPD78P054 : 1024 bytes  
µPD78055 : 1024 bytes  
µPD78056 : 1024 bytes  
µPD78058 : 1024 bytes  
µPD78P058 : 1024 bytes  
µPD78058 : 1024 bytes  
µPD78P058 : 1024 bytes  
Positive power supply (including ports)  
Ground potential (including ports)  
Analog power supply for A/D converter,  
D/A converter  
µPD78056F: 48 Kbytes  
µPD78058F: 60 Kbytes  
Internal high-speed RAM capacity  
µPD78056F: 1024 bytes  
µPD78058F: 1024 bytes  
Internal expansion RAM capacity  
µPD78058F: 1024 bytes  
VDD pin  
VSS pin  
AVDD pin  
Positive power supply (excluding ports)  
Ground potential (excluding ports)  
Analog power supply for A/D converter,  
D/A converter and power supply for ports  
Ground for A/D converter, D/A converter  
and ground for ports  
AVSS pin  
Package  
Ground for A/D converter, D/A converter  
80-pin plastic QFP  
80-pin plastic QFP  
(14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP  
(14 × 14 mm, Resin thickness: 2.7 mm)  
80-pin plastic QFP  
(14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch)  
(12 × 12 mm)  
(14 × 14 mm, Resin thickness: 1.4 mm)  
80-pin plastic TQFP (Fine pitch)  
(12 × 12 mm)  
Note  
80-pin ceramic WQFN (14 × 14 mm)  
Electrical characteristics,  
Refer to individual data sheet.  
recommended soldering conditions  
Note PROM version only  
578  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
The following development tools are available for the development of systems which employ the µPD78054 and  
78054Y subseries.  
Figure B-1 shows the configuration of the development tools.  
579  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
Figure B-1. Development Tool Configuration (1/2)  
(1) When using in-circuit emulator IE-78K0-NS  
Language processing software  
Debugging tool  
• Assembler package  
• C compiler package  
• C library source file  
• Device file  
• System simulator  
• Integrated debugger  
• Device file  
PROM programming tool  
• PG-1500 controller  
Embedded software  
• Real-time OS  
• OS  
Host machine (PC)  
Interface adapter,  
PC card interface, etc.  
PROM programming  
environment  
In-circuit emulator  
PROM  
programmer  
Emulation board  
Power supply  
unit  
Programmer  
adapter  
Emulation probe  
PROM-contained  
version  
Conversion socket  
or  
conversion adapter  
Target system  
580  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
Figure B-1. Development Tool Configuration (2/2)  
(2) When using in-circuit emulator IE-78001-R-A  
Language processing software  
Debugging tool  
• Assembler package  
• C compiler package  
• C library source file  
• Device file  
• System simulator  
• Integrated debugger  
• Device file  
PROM programming tool  
• PG-1500 controller  
Embedded software  
• Real-time OS  
• OS  
Host machine (PC or EWS)  
Interface board  
PROM programming  
environment  
In-circuit emulator  
Interface adapter  
Emulation board  
I/O board  
PROM  
programmer  
Programmer  
adapter  
Probe board  
Emulation probe conversion board  
PROM-contained  
version  
Emulation probe  
Conversion socket  
or  
conversion adapter  
Target system  
Remark The parts shown within broken lines differ depending on the developing environment. Refer to  
B.3.1 Hardware.  
581  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.1 Language Processing Software  
RA78K/0  
A program that converts a program written in mnemonic into object  
codes that microcomputers can process.  
Assembler Package  
Providedwithfunctionstoautomaticallyperformgenerationofsymbol  
table, optimizing processing of branch instructions, etc.  
UsedincombinationwithseparatelyavailableDeviceFile(DF78054).  
<Precautions for the use in PC environment>  
Although Assembler Package is a DOS-based application, it can be  
used in a Windows environment through the use of Project Manager  
(included in Assembler Package) on Windows.  
Part number: µSxxxxRA78K0  
CC78K/0  
A program which converts a program written in C language into  
object codes that microcomputers can process.  
Used in combination with separately available Assembler Package  
and Device File.  
C Compiler Package  
<Precautions for the use in PC environment>  
Although C Compiler Package is a DOS-based application, it can be  
used in Windows environment through the use of Project Manager  
(included in Assembler Package) on Windows.  
Part number: µSxxxxCC78K0  
Note  
DF78054  
A file which contains information peculiar to the device.  
Usedincombinationwithseparatelyavailabletools(RA78K/0,CC78K/0,  
SM78K0, ID78K0-NS, ID78K0).  
Device File  
Supporting OS and host machines are dependent on the tool to be  
combined with.  
Part number: µSxxxxDF78054  
CC78K/0-L  
A source file of functions which configure the object library included  
in C Compiler package.  
C Library Source File  
Required when modifying the object library included in C Compiler  
Package for customization.  
Since this is a source file, its operation environment is independent  
from OS.  
Part number: µSxxxxCC78K0-L  
Note The DF78054 can commonly be used for all the products of the RA78K/0, CC78K/0, SM78K0, ID78K0-  
NS, and ID78K0  
.
582  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
Remark xxxx in the part number differs depending on the host machine and OS used.  
µSxxxx RA78K0  
µSxxxx CC78K0  
µSxxxx DF78078  
µSxxxx CC78K0-L  
xxxx  
Host Machine  
OS  
Supply Media  
3.5-inch 2HD FD  
3.5-inch 2HC FD  
Notes 1, 2  
Notes 1, 2  
AA13 PC-9800 series  
AB13 IBM PC/AT™ and  
BB13 compatibles  
3P16 HP9000 series 700™  
3K13 SPARCstation™  
3K15  
Japanese Windows  
Japanese Windows  
Notes 1, 2  
English Windows  
HP-UX™ (rel. 9.05)  
DAT (DDS)  
SunOS™ (rel. 4.1.4)  
3.5-inch 2HC FD  
1/4-inch CGMT  
3.5-inch 2HC FD  
3R13 NEWS™ (RISC)  
NEWS-OS™ (rel. 6.1)  
Notes 1. Operates also in DOS environment.  
2. Does not support WindowsNT™  
583  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.2 PROM Writing Tools  
B.2.1 Hardware  
PG-1500  
APROMprogrammerthat, byconnectingtheattachedboardandseparately  
available PROM programmer adapter, is capable of programming single-  
chipmicrocomputersincorporatingaPROMonstand-alonebasisorthrough  
operation from the host machine.  
PROM Programmer  
Also capable of programming typical 256-Kbit to 4-Mbit PROM.  
PA-78P054GC  
A PROM programmer adapter for the µPD78P054, 78P058, and 78P058Y.  
PA-78P054GK  
Used connected to the PG-1500.  
PA-78P054KK-T  
PA-78P054GC  
PA-78P054GK  
:
:
80-pin plastic QFP (GC-3B9, GC-8BT type)  
80-pin plastic QFP (GK-BE9 type)  
PROM Programmer Adapter  
PA-78P054KK-T : 80-pin ceramic WQFN (KK-T type)  
B.2.2 Software  
PG-1500 Controller  
Connects PG-1500 and the host machine with serial and parallel interface,  
and controls the PG-1500 on the host machine.  
The PG-1500 controller is a DOS-based application. Use it with the DOS  
prompt on Windows.  
Part number: µSxxxxPG1500  
Remark xxxx in the part number differs depending on the host machine and OS used.  
µSxxxx PG1500  
xxxx  
Host Machine  
OS  
Supply Media  
5A13  
PC-9800 series  
MS-DOS  
3.5-inch 2HD FD  
Note  
(ver. 3.30 to ver. 6.2  
)
5B13  
IBM PC/AT and  
compatibles  
Refer to B.4  
3.5-inch 2HC FD  
Note MS-DOS ver. 5.0 or later has a task swap function, but it cannot be used with the above  
software.  
584  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.3 Debugging Tools  
B.3.1 Hardware (1/2)  
(1) When using in-circuit emulator IE-78K0-NS  
Note  
IE-78K0-NS  
An in-circuit emulator to debug hardware and software when developing  
In-circuit Emulator  
applicationsystemsthatusethe78K/0Series. Supportsintegrateddebugger  
(ID78K0-NS). Used in combination with a power supply unit, emulation  
probe, and interface adapter to connect to the host machine.  
An adapter to supply voltage from AC100 to 240-V outlet.  
IE-70000-MC-PS-B  
Power Supply Adapter  
Note  
IE-70000-98-IF-C  
An adapter required for using a PC-9800 series computer (except notebook-  
type personal computer) as the host machine for the IE-78K0-NS.  
A PC card and an interface cable required for using PC-9800 series  
notebook-type personal computerasthe hostmachinefortheIE-78K0-NS.  
An adapter required when using an IBM PC/AT and compatible as the host  
machine for the IE-78K0-NS.  
Interface Adapter  
Note  
IE-70000-CD-IF  
PC Card Interface  
Note  
IE-70000-PC-IF-C  
Interface Adapter  
Note  
IE-780308-NS-EM1  
Emulation Board  
NP-80GC  
A board to emulate peripheral hardware peculiar to the device. Used in  
combination with an in-circuit emulator.  
A probe to connect an in-circuit emulator and a target system.  
For 80-pin plastic QFP (GC-3B9, GC-8BT type)  
Emulation Probe  
EV-9200GC-80 Conversion  
A conversion socket to connect the board of a target system that is  
designed to mount 80-pin plastic QFP (GC-3B9, GC-8BT type) and the  
NP-80GC.  
Socket  
(refer to Figure B-2)  
The µPD78P054KK-T, 78P058KK-T, and 78P058YKK-T (ceramic WQFN)  
can be mounted instead of connecting NP-80GC.  
NP-80GK  
Emulation Probe  
TGK-080SDW  
A probe to connect an in-circuit emulator and the target system.  
For 80-pin plastic TQFP (GK-BE9 type).  
A conversion adapter to connect the board of a target system designed to  
mount 80-pin plastic QFP (GK-BE9 type) to the NP-80GK.  
Conversion Adapter  
(refer to Figure B-3)  
Note Under development  
Remarks 1. The NP-80GC and NP-80GK are products of Naito Densei  
Machidaseisakusho Co., Ltd.  
Contact: Naito Densei Machidaseisakusho Co., Ltd (Tel: (044)822-3813)  
2. The TGK-080SDW is a product of TOKYO ELETECH Corporation.  
Contact: Daimaru Kogyo Co., Ltd.  
Tokyo Electronic Component Department (Tel: (03)3820-7112)  
Osaka Electronic Component Department (Tel: (06)244-6672)  
3. The TGK-080SDW is sold singly.  
4. The EV-9200GC-80 is sold in a set of five.  
585  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.3.1 Hardware (2/2)  
(2) When using in-circuit emulator IE-78001-R-A  
Note 1  
IE-78001-R-A  
An in-circuit emulator to debug hardware and software when developing  
In-circuit Emulator  
applicationsystemsthatusethe78K/0Series. Supportsintegrateddebugger  
(ID78K0). Used in combination with an interface adapter to connect to an  
emulation probe and the host machine.  
IE-70000-98-IF-B or  
An adapter required for using a PC-9800 series (except notebook-type  
personal computer) as the host machine for the IE-78001-R-A.  
Note 1  
IE-70000-98-IF-C  
Interface Adapter  
IE-70000-PC-IF-B or  
An adapter required for using an IBM PC/AT or compatible as the host  
machine for the IE-78001-R-A.  
Note 1  
IE-70000-PC-IF-C  
Interface adapter  
IE-78000-R-SV3  
Interface Adapter  
An adapter and a cable required for using EWS as the host machine for the  
IE-78001-R-A. Used connected to the board in the IE-78001-R-A.  
TM  
Supports 10Base-5 for Ethernet . A separately available adapter required  
for other systems.  
Note 1  
IE-780308-NS-EM1  
Emulation Board  
A board to emulate peripheral hardware peculiar to the device. Used in  
combination with an in-circuit emulator and emulation probe conversion  
board.  
Note 1  
IE-78K0-R-EX1  
A board required for using the IE-780308-NS-EM1 with the IE-78001-R-A  
EmulationProbeConversion  
Board  
IE-780308-R-EM  
Aboardtoemulateperipheralhardwarepeculiartothedevice(IE-780308-R-EM  
supports 2.0 to 5.0V, IE-78064-R-EM supports 3.0 to 6.0V). Used in  
combination with the IE-78001-R-A.  
Note 2  
IE-78064-R-EM  
Emulation board  
EP-78230GC-R  
Emulation Probe  
A probe to connect an in-circuit emulator and the target system.  
For 80-pin plastic QFP (GC-3B9, GC-8BT type).  
EV-9200GC-80  
A conversion socket to connect the board of a target system designed  
to mount80-pinplasticQFP (GC-3B9,GC-8BTtype) and theEP-78230GC-R.  
The µPD78P054KK-T, 78P058KK-T, or 78P058YKK-T (ceramic WQFN)  
can be mounted instead of connecting the EP-78230GC-R.  
A probe to connect an in-circuit emulator and the target system.  
For 80-pin plastic TQFP (GK-BE9 type).  
Conversion Socket  
(refer to Figure B-2)  
EP-78054GK-R  
Emulation Probe  
TGK-080SDW  
A conversion adapter to connect the board of a target system designed to  
mount 80-pin plastic TQFP (GK-BE9 type) to the EP-78054GK-R.  
Conversion Adapter  
(refer to Figure B-3)  
Notes 1. Under development  
2. Maintenance product  
Remarks 1. The TGK-080SDW is a product of TOKYO ELETECH Corporation.  
Contact: Daimaru Kogyo Co., Ltd.  
Tokyo Electronic Component Department (Tel: (03)3820-7112)  
Osaka Electronic Component Department (Tel: (06)244-6672)  
2. The TGK-080SDW is sold singly.  
3. The EV-9200GC-80 is sold in a set of five.  
586  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.3.2 Software (1/2)  
SM78K0  
Capable of debugging in C source level or assembler level while simulating  
the operation of the target system on the host machine.  
The SM78K0 operates on Windows.  
System Simulator  
The use of the SM78K0 enables the verification of logic and performance  
of applications independently from hardware development without using in-  
circuit emulator and improves the development efficiency and the software  
quality.  
Used in combination with separately available Device File (DF78054).  
Part number: µSxxxxSM78K0  
Remark xxxx in the part number differs depending on the host machine and OS used.  
µSxxxx SM78K0  
xxxx  
AA13  
AB13  
BB13  
Host Machine  
PC-9800 series  
OS  
Supply Media  
3.5-inch 2HD FD  
3.5-inch 2HC FD  
Notes 1, 2  
Notes 1, 2  
Japanese Windows  
Japanese Windows  
IBM PC/AT and  
compatible  
Note  
English Windows  
Note Does not support WindowsNT.  
587  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.3.2 Software (2/2)  
Note  
A control program to debug the 78K/0 Series.  
ID78K0-NS  
Adopting Windows on personal computers and OSF/Motif™ on EWS as  
graphical user interface, presents the appearance and the operability  
conforming to them. Enhancing the debugging function that supports C  
language, the trace result can be displayed in the C language level by using  
windowintegrationfunctionwhichcorrelatesthesourceprogram,disassembly  
display, and memory display to the trace result. In addition, the debugging  
efficiency of programs using real-time OS can be improved by integrating  
functionextensionmodulessuchastaskdebuggersandsystemperformance  
analyzers.  
Integrated debugger  
(supporting in-circuit emulator  
IE-78K0-NS)  
ID78K0  
Integrated Debugger  
(supporting in-circuit emulator  
IE-78001-R-A)  
Used in combination with separately available Device File (DF78054).  
Part number: µSxxxxID78K0-NS, µSxxxxID78K0.  
Note Under development  
Remark xxxx in the part number differs depending on the host machine and OS used.  
µSxxxx ID78K0-NS  
xxxx  
AA13  
AB13  
BB13  
Host Machine  
PC-9800 series  
IBM PC/AT and  
compatible  
OS  
Supply Media  
3.5-inch 2HD FD  
3.5-inch 2HC FD  
Note  
Note  
Japanese Windows  
Japanese Windows  
Note  
English Windows  
Note Does not support WindowsNT.  
µSxxxx ID78K0  
xxxx  
Host Machine  
PC-9800 series  
IBM PC/AT and  
compatible  
OS  
Supply Media  
3.5-inch 2HD FD  
3.5-inch 2HC FD  
Note  
Note  
AA13  
AB13  
BB13  
3P16  
3K13  
3K15  
3R13  
Japanese Windows  
Japanese Windows  
Note  
English Windows  
HP-UX (Rel. 9.05)  
SunOS (Rel. 4.1.4)  
HP9000 series 700  
SPARCstation  
DAT (DDS)  
3.5-inch 2HC FD  
1/4-inch CGMT  
3.5-inch 2HC FD  
NEWS (RISC)  
NEWS-OS (Rel. 6.1)  
Note Does not support WindowsNT.  
588  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
B.4 OS for IBM PC  
The following OSs are supported for IBM PC.  
Table B-1. OS for IBM PC  
OS  
PC DOS  
Version  
Ver. 5.02 to Ver. 6.3  
Note  
Note  
J6.1/V  
to J6.3/V  
Note  
IBM DOS™  
MS-DOS  
J5.02/V  
Ver. 5.0 to Ver. 6.22  
Note  
Note  
5.0/V  
to 6.2/V  
Note Only English mode is supported.  
Caution MS-DOS ver. 5.0 or later has a task swap function, but it cannot be used  
with the above software.  
B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A  
If you have a former in-circuit emulator for the 78K/0 Series (IE-78000-R or IE-78000-R-A), your in-circuit emulator  
can be upgraded to be equivalent to the IE-78001-R-A in-circuit emulator by simply replacing the break board with  
the IE-78001-R-BK (under development).  
Table B-2. Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A  
Note  
In-circuit Emulator  
IE-78000-R  
IE-78000-R-A  
Cabinet Upgrading  
Required  
Not required  
Board to be Purchased  
IE-78001-R-BK  
Note To upgrade your cabinet, bring it to NEC.  
589  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
Drawing and Footprint for Conversion Socket (EV-9200GC-80)  
Figure B-2. EV-9200GC-80 Drawing (For Reference Only)  
A
B
M
N
E
O
F
EV-9200GC-80  
1
No.1 pin index  
P
G
H
I
EV-9200GC-80-G0  
ITEM  
A
MILLIMETERS  
18.0  
14.4  
14.4  
18.0  
4-C 2.0  
0.8  
INCHES  
0.709  
0.567  
0.567  
0.709  
4-C 0.079  
0.031  
0.236  
0.63  
B
C
D
E
F
G
H
I
6.0  
16.0  
18.7  
6.0  
0.736  
0.236  
0.63  
J
K
16.0  
18.7  
8.2  
L
0.736  
0.323  
0.315  
0.098  
0.079  
0.014  
0.091  
0.059  
M
O
N
P
8.0  
2.5  
2.0  
Q
R
S
0.35  
2.3  
1.5  
590  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
Figure B-3. EV-9200GC-80 Footprint (For Reference Only)  
Based on EV-9200GC-80  
(2) Pad drawing (in mm)  
G
J
K
L
C
B
A
EV-9200GC-80-P1E  
INCHES  
ITEM  
MILLIMETERS  
19.7  
A
B
C
D
E
F
G
H
I
0.776  
15.0  
0.591  
+0.003  
–0.002  
±
±
0.65 0.02 × 19=12.35 0.05 0.026–0.002  
+0.001 × 0.748=0.486  
+0.003  
–0.002  
+0.001 × 0.748=0.486  
±
±
0.65 0.02 × 19=12.35 0.05 0.026–0.002  
15.0  
19.7  
0.591  
0.776  
0.236  
0.236  
0.014  
+0.003  
–0.002  
±
6.0 0.05  
+0.003  
–0.002  
±
6.0 0.05  
+0.001  
–0.001  
±
0.35 0.02  
+0.001  
–0.002  
±
J
2.36 0.03  
0.093  
0.091  
0.062  
K
L
2.3  
+0.001  
–0.002  
±
1.57 0.03  
Dimensions of mount pad for EV-9200 and that for  
target device (QFP) may be different in some parts.  
For the recommended mount pad dimensions for  
QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING  
TECHNOLOGY MANUAL" (C10535E).  
Caution  
591  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX B DEVELOPMENT TOOLS  
Drawing of Conversion Adapter (TGK-080SDW)  
Figure B-4. TGK-080SDW Drawing (For Reference) (unit: mm)  
TGK-080SDW (TQPACK080SD + TQSOCKET080SDW)  
Package dimension (unit: mm)  
A
B
C
U
V
T
D
R
Q
Q
Q
e
c
M2 screw  
b
H
G F E  
P
a
S
O
O
O
N
d
Z
K
f
W
X
Y
I J J J  
L LLM  
g
v
k
u
t
r
j
i
s
q
h
p
Protrusion : 4 places  
o
l
n
m
ITEM MILLIMETERS  
INCHES  
0.709  
0.463  
ITEM MILLIMETERS  
INCHES  
0.020x0.748=0.374±0.004  
0.010  
A
B
C
D
E
F
18.0  
11.77  
0.5x19=9.5  
0.5  
a
b
c
d
e
f
0.5x19=9.5±0.10  
0.25  
φ
φ
0.209  
0.020x0.748=0.374  
0.020  
5.3  
φ
φ
0.209  
φ
0.051  
φ
0.140  
φ
0.012  
5.3  
φ
1.3  
0.5x19=9.5  
11.77  
18.0  
0.5  
0.020x0.748=0.374  
0.463  
φ
3.55  
φ
0.3  
1.85±0.2  
G
H
I
0.709  
g
h
i
0.020  
0.073±0.008  
1.58  
1.2  
0.062  
3.5  
0.138  
J
0.047  
j
2.0  
0.079  
K
L
7.64  
1.2  
0.301  
k
l
3.0  
0.118  
0.25  
0.010  
0.047  
M
N
O
P
Q
R
S
T
1.58  
1.58  
1.2  
0.062  
m
n
o
p
q
r
14.0  
0.551  
0.062  
1.4±0.2  
1.4±0.2  
0.055±0.008  
0.055±0.008  
0.047  
φ
φ
7.64  
1.2  
0.301  
h=1.8 1.3  
h=0.071 0.051  
0.047  
0 to 5°  
5.9  
0.000 to 0.197°  
0.232  
1.58  
0.062  
φ
3.55  
φ
0.140  
s
t
0.8  
0.031  
C 2.0  
12.31  
10.17  
6.8  
C 0.079  
2.4  
0.094  
U
V
W
X
Y
Z
0.485  
u
v
2.7  
0.106  
0.400  
3.9  
0.154  
0.268  
TGK-080SDW-G1E  
8.24  
0.324  
14.8  
0.583  
1.4±0.2  
0.055±0.008  
Note Product by TOKYO ELETECH CORPORATION.  
592  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX C EMBEDDED SOFTWARE  
For efficient program development and maintenance of the µPD78054, 78054Y Subseries, the following embedded  
software is available.  
Real-time OS (1/2)  
RX78K/0  
A real-time OS conforming to µITRON specifications.  
Real-time OS  
Added with the tool (configurator) to create the RX78K/0 nucleus and multiple information table.  
Used in combination with separately available Assembler Package (RA78K/0) and Device File  
(DF78054).  
<Precautions for the use in PC environment>  
Real-time OS is a DOS-based application. Use it with DOS prompt on Windows.  
Part number: µSxxxxRX78013-∆∆∆  
Caution When purchasing the RX78K/0, fill in the purchase application form in advance, and sign the  
License Agreement.  
Remark xxxx and ∆∆∆ in the part number differs depending on the host machine and OS used.  
µSxxxxRX78013-∆∆∆  
∆∆∆∆  
001  
Product Outline  
Evaluation object  
Max. No. for Use in Mass Production  
Do not use for mass production.  
100,000  
100K  
Mass-production object  
001M  
1,000,000  
010M  
S01  
10,000,000  
Source program  
Host Machine  
Source program for mass-production object  
xxxx  
OS  
Supply Media  
3.5-inch 2HD FD  
3.5-inch 2HC FD  
Notes1, 2  
Notes1, 2  
AA13  
AB13  
BB13  
3P16  
3K13  
3K15  
3R13  
PC-9800 series  
IBM PC/AT and  
compatibles  
Japanese Windows  
Japanese Windows  
Notes1, 2  
English Windows  
HP-UX (Rel. 9.05)  
SunOS (Rel. 4.1.4)  
HP9000 series 700  
SPARCstation  
DAT (DDS)  
3.5-inch 2HC FD  
1/4-inch CGMT  
3.5-inch 2HC FD  
NEWS (RISC)  
NEWS-OS (Rel. 6.1)  
Notes 1. Operates also in DOS environment.  
2. Does not support WindowsNT.  
593  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX C REGISTER INDEX  
Real-time OS (2/2)  
MX78K0  
OS  
A µITRON specification subset OS. Added with MX78K0 nucleus.  
Performs task management, event management, and time management. In task management,  
controls the execution order of tasks and performs processing to change the task to the one  
executed next.  
<Precautions for the use in PC environment>  
The MX78K0 is a DOS-based application. Use it with DOS prompt on Windows.  
Part number: µSxxxxMX78K0-∆∆  
Remark xxxx and ∆∆ in the part number differs depending on the host machine and OS used.  
µSxxxxMX78K0-∆∆  
∆∆∆  
001  
xx  
Product outline  
Evaluation object  
Max. No. for Use in Mass Production  
Use for preproduction.  
Mass-production object  
Source program  
Use for mass production.  
S01  
Can be purchased only when purchasing  
mass-produced object.  
xxxx  
Host Machine  
OS  
Supply Media  
3.5-inch 2HD FD  
3.5-inch 2HC FD  
Notes1, 2  
Notes1, 2  
AA13  
AB13  
BB13  
3P16  
3K13  
3K15  
3R13  
PC-9800 series  
IBM PC/AT and  
compatibles  
Japanese Windows  
Japanese Windows  
Notes1, 2  
English Windows  
HP-UX (Rel. 9.05)  
SunOS (Rel. 4.1.4)  
HP9000 series 700  
SPARCstation  
DAT (DOS)  
3.5-inch 2HC FD  
1/4-inch CGMT  
3.5-inch 2HC FD  
NEWS (RISC)  
NEWS-OS (Rel. 6.1)  
Notes 1. Operates also in DOS environment.  
2. Does not support WindowsNT.  
594  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX D REGISTER INDEX  
D.1 Register Index  
8-bit timer mode control register (TMC1).......................................................................................................... 225  
8-bit timer output control register (TOC1)......................................................................................................... 226  
8-bit timer register 1 (TM1) ................................................................................................................................ 223  
8-bit timer register 2 (TM2) ................................................................................................................................ 223  
16-bit timer mode control register (TMC0)........................................................................................................ 184  
16-bit timer output control register (TOC0)....................................................................................................... 186  
16-bit timer register (TM0) ................................................................................................................................. 182  
16-bit timer register (TMS)................................................................................................................................. 223  
[A]  
ADCR:  
ADIS:  
ADM:  
A/D conversion result register ........................................................................................................ 267  
A/D converter input select register................................................................................................. 271  
A/D converter mode register .......................................................................................................... 269  
Automatic data transmit/receive control register .................................................................. 400, 411  
Automatic data transmit/receive interval specify register .................................................... 401, 412  
Automatic data transmit/receive address pointer .......................................................................... 396  
Asynchronous serial interface mode register .......................................................445, 453, 455, 478  
Asynchronous serial interface status register ...................................................................... 447, 456  
ADTC:  
ADTI:  
ADTP:  
ASIM:  
ASIS:  
[B]  
BRGC:  
Baud rate generator control register ............................................................................. 448, 457, 469  
[C]  
CORAD0: Correction address register 0 ......................................................................................................... 538  
CORAD1: Correction address register 1 ......................................................................................................... 538  
CORCN: Correction control register .............................................................................................................. 539  
CR00:  
CR01:  
CR10:  
CR20:  
CRC0:  
CSIM0:  
CSIM1:  
CSIM2:  
Capture/compare register 00.......................................................................................................... 181  
Capture/compare register 01.......................................................................................................... 181  
Compare registers 10 ..................................................................................................................... 223  
Compare registers 20 ..................................................................................................................... 223  
Capture/compare control register 0 ............................................................................................... 185  
Serial operating mode register 0 ......................................... 296, 302, 315, 334, 350, 357, 382, 372  
Serial operating mode register 1 ................................................................................... 396, 399, 409  
Serial operating mode register 2 ...........................................................................444, 452, 454, 467  
[D]  
DACS0:  
DACS1:  
DAM:  
D/A conversion value set register 0 ............................................................................................... 283  
D/A conversion value set register 1 ............................................................................................... 283  
D/A converter mode register .......................................................................................................... 284  
[E]  
External interrupt mode register (INTM0) ................................................................................................ 189, 492  
External interrupt mode register (INTM1) ................................................................................................ 272, 492  
595  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX D REGISTER INDEX  
[I]  
IF0H:  
IF0L:  
IF1L:  
IMS:  
Interrupt request flag register 0H ................................................................................................... 489  
Interrupt request flag register 0L.................................................................................................... 489  
Interrupt request flag register 1L........................................................................................... 489, 508  
Memory size switching register ..................................................................................... 517, 549, 550  
External interrupt mode register ............................................................................................ 189, 492  
External interrupt mode register ............................................................................................ 272, 492  
Internal expansion RAM size switching register ........................................................................... 551  
INTM0:  
INTM1:  
IXS:  
Interrupt mask flag register 0H (MK0H) ............................................................................................................ 490  
Interrupt mask flag register 0L (MK0L) ............................................................................................................. 490  
Interrupt mask flag register 1L (MK1L) .................................................................................................... 490, 508  
Interrupt timing specify register (SINT) ................................................................... 300, 318, 336, 354, 364, 375  
[K]  
KRM:  
Key return mode register ....................................................................................................... 155, 509  
[M]  
MK0H:  
MK0L:  
MK1L:  
MM:  
Interrupt mask flag register 0H....................................................................................................... 490  
Interrupt mask flag register 0L ....................................................................................................... 490  
Interrupt mask flag register 1L .............................................................................................. 490, 508  
Memory expansion mode register ......................................................................................... 154, 516  
Memory size switching register (IMS) .............................................................................................. 517, 549, 550  
[O]  
OSMS:  
OSTS:  
Oscillation mode selection register ................................................................................................ 164  
Oscillation stabilization time select register................................................................................... 516  
[P]  
P0:  
Port0 ................................................................................................................................................ 134  
Port1 ................................................................................................................................................ 136  
Port2 ....................................................................................................................................... 137, 139  
Port3 ................................................................................................................................................ 141  
Port4 ................................................................................................................................................ 142  
Port5 ................................................................................................................................................ 143  
Port6 ................................................................................................................................................ 144  
Port7 ................................................................................................................................................ 146  
Port12 .............................................................................................................................................. 148  
Port13 .............................................................................................................................................. 149  
Processor clock control register ..................................................................................................... 161  
Port mode register 0 ....................................................................................................................... 150  
Port mode register 1 ....................................................................................................................... 150  
Port mode register 2 ....................................................................................................................... 150  
Port mode register 3 ..................................................................................... 150, 188, 227, 259, 264  
Port mode register 5 ....................................................................................................................... 150  
Port mode register 6 ....................................................................................................................... 150  
Port mode register 7 ....................................................................................................................... 150  
Port mode register 12 ............................................................................................................ 150, 480  
Port mode register 13 ..................................................................................................................... 150  
P1:  
P2:  
P3:  
P4:  
P5:  
P6:  
P7:  
P12:  
P13:  
PCC:  
PM0:  
PM1:  
PM2:  
PM3:  
PM5:  
PM6:  
PM7:  
PM12:  
PM13:  
596  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX D REGISTER INDEX  
PR0H:  
PR0L:  
PR1L:  
PSW:  
Priority specify flag register 0H ...................................................................................................... 491  
Priority specify flag register 0L ....................................................................................................... 491  
Priority specify flag register 1L ....................................................................................................... 491  
Program status word .............................................................................................................. 109, 496  
Pull-up resistor option register H ................................................................................................... 153  
Pull-up resistor option register L .................................................................................................... 153  
PUOH:  
PUOL:  
[R]  
RTBH:  
RTBL:  
RTPC:  
RTPM:  
RXB:  
RXS:  
Real-time output buffer register H.................................................................................................. 479  
Real-time output buffer register L .................................................................................................. 479  
Real-time output port control register ............................................................................................ 481  
Real-time output port mode register .............................................................................................. 480  
Receive buffer register ................................................................................................................... 443  
Receive shift register ...................................................................................................................... 443  
[S]  
SAR:  
SBIC:  
SCS:  
SFR:  
SINT:  
SIO0:  
SIO1:  
SVA:  
Successive approximation register ................................................................................................ 267  
Serial bus interface control register .................................... 298, 304, 316, 335, 352, 358, 363, 373  
Sampling clock select register............................................................................................... 190, 494  
Special-function register ................................................................................................................. 114  
Interrupt timing specify register ............................................................ 300, 318, 336, 354, 364, 375  
Serial I/O shift register 0........................................................................................................ 292, 346  
Serial I/O shift register 1................................................................................................................. 396  
Slave address register ........................................................................................................... 292, 346  
Serial operating mode register 0 (CSIM0) ............................................. 296, 302, 315, 334, 350, 357, 362, 372  
Serial operating mode register 1 (CSIM1) ....................................................................................... 396, 399, 409  
Serial operating mode register 2 (CSIM2) ...............................................................................444, 452, 454, 467  
[T]  
TCL0:  
TCL1:  
TCL2:  
TCL3:  
TM0:  
Timer clock select register 0 ................................................................................................. 182, 257  
Timer clock select register 1 .......................................................................................................... 223  
Timer clock select register 2 ......................................................................................... 242, 250, 262  
Timer clock select register 3 ......................................................................................... 294, 348, 397  
16-bit timer register ......................................................................................................................... 182  
8-bit timer register 1........................................................................................................................ 223  
8-bit timer register 2........................................................................................................................ 223  
16-bit timer mode control register .................................................................................................. 184  
8-bit timer mode control register .................................................................................................... 225  
Watch timer mode control register ................................................................................................. 245  
16-bit timer register ......................................................................................................................... 223  
16-bit timer output control register ................................................................................................. 186  
8-bit timer output control register ................................................................................................... 226  
Transmit shift register ..................................................................................................................... 443  
TM1:  
TM2:  
TMC0:  
TMC1:  
TMC2:  
TMS:  
TOC0:  
TOC1:  
TXS:  
[W]  
WDTM:  
Watchdog timer mode register ....................................................................................................... 252  
Watch timer mode control register (TMC2) ...................................................................................................... 245  
597  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
598  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX E REVISION HISTORY  
Major revisions by edition and revised chapters are shown below.  
Edition  
2nd  
Major revisions from previous version  
Revised Chapters  
P40/AD0-P47/AD7 pin I/O circuit types were changed.  
Connection method of unused AVREF1 pin was changed.  
CHAPTER 2 Pin Functions  
Caution on OVF0 flag operations was added.  
Interval time of interval timer was corrected.  
Buzzer output frequency was corrected.  
Description of settings of port mode register and output latch was  
added.  
CHAPTER 6 16-Bit Timer/Event Counter  
CHAPTER 8 Watch Timer  
CHAPTER 11 Buzzer Output Control Circuit  
CHAPTER 14 Serial Interface Channel 0  
CHAPTER 15 Serial Interface Channel 1  
CHAPTER 16 Serial Interface Channel 2  
Paragraph (2), "Memory size switching register (IMS)" was added  
in section 19.2.  
CHAPTER 19 External Device Expansion  
Function  
Embedded software were added.  
APPENDIX B Embedded Software  
Throughout the manual  
3rd  
µPD78055 and 78P058 were added as new devices.  
µPD78054Y subseries devices were added.  
Pin I/O circuits and unused pin connections were changed.  
CHAPTER 3 Pin Function  
(µPD78054 Subseries)  
Caution on oscillation mode switching was added.  
CHAPTER 7 Clock Generator  
Parts of list of maximum required time for switching CPU clock  
types were corrected.  
Available frequencies for 16-bit timer register count clock were  
changed.  
CHAPTER 8 16-bit Timer/Event Counter  
Caution on pulse width measurement operations was added.  
Timing chart for one-shot pulse output operation was corrected.  
Section 15.4, “Operations of D/A Converter,” was added.  
Section 15.5, “Cautions Related to D/A Converter,” was added.  
CHAPTER 15 D/A Converter  
Condition under which acknowledge detection flag (ACKD) is  
cleared was changed.  
CHAPTER 16 Serial Interface Channel 0  
(µPD78054 Subseries)  
Timing chart for RELD and CMDD operations (slave) was corrected.  
Description on automatic transmit/receive interval time was  
corrected.  
CHAPTER 18 Serial Interface Channel 1  
List of operation mode settings was corrected.  
CHAPTER 19 Serial Interface Channel 2  
CHAPTER 21 Interrupt and Test Functions  
Flowchart for non-maskable interrupt acknowledgement was  
corrected.  
Oscillation stabilization time after RESET input was corrected.  
ROM correction chapter was added.  
CHAPTER 23 Standby Function  
CHAPTER 25 ROM Correction  
CHAPTER 26 µPD78P054, 78P058  
Caution on write address specification in PROM programming  
mode was added.  
599  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX E REVISION HISTORY  
Edition  
Major revisions from previous version  
Revised Chapters  
4th  
Addition of following package to all devices:  
• 80-pin plastic QFP (14 × 14 mm, resin thickness: 1.4 mm)  
(under planning)  
Throughout  
edition  
Addition of following package to µPD78058  
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)  
Addition of description to Caution in Figure 8-6. 16-Bit Timer  
CHAPTER 8 16-BIT TIMER/EVENT COUNTER  
Output Control Register Format  
Change of Figure 11-3. Watchdog Timer Mode Register Format CHAPTER 11 WATCHDOG TIMER  
and addition of Note and Caution  
Addition of caution on serial I/O shift register 0 (SIO0) of  
CHAPTER 17 SERIAL INTERFACE CHANNEL 0  
µPD78054Y subseries  
(µPD78054Y Subseries)  
Correction of Figure 17-22. Data Transmission from Master to  
Slave (Both Master and Slave Selected 9-Clock Wait)  
Correction of Figure 17-23. Data Transmission from Slave to  
Master (Both Master and Slave Selected 9-Clock Wait)  
Addition of (3) Slave wait release (slave reception) to 17.4.5  
Cautions on use of I2C bus mode  
Addition of 17.4.6 Restrictions in I2C bus mode  
Addition of Caution to Figure 18-5. Automatic Data Transmit/  
CHAPTER 18 SERIAL INTERFACE  
CHANNEL 1  
Receive Interval Specify Register Format  
Addition of Caution to 18.4.3 (3) (d) Busy control option  
Addition of description on port mode register 12 (PM12)  
CHAPTER 20 REAL-TIME OUTPUT PORT  
Addition of following products:  
APPENDIX A DEVELOPMENT TOOLS  
APPENDIX B EMBEDDED SOFTWARE  
IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF,  
IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0, MX78K0  
Addition of IBM PC/AT compatible machine as host machine  
Change of supported OS version  
Addition of APPENDIX C REGISTER INDEX  
APPENDIX C REGISTER INDEX  
600  
Download from Www.Somanuals.com. All Manuals Search And Download.  
APPENDIX E REVISION HISTORY  
Edition  
4th  
Major revisions from previous version  
Revised Chapters  
The µPD78052(A),78053(A), and 78054(A) were added to the  
applicable types.  
Throughout  
edition  
The µPD78P054Y was deleted from the applicable types.  
The following package was deleted from the µPD78052, 78053,  
78054, 78055, 78056, 78058, 78P058, 78054Y Subseries:  
• 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)  
Figure 9-10. Square-Wave Output Operation Timing was added. CHAPTER 9 8-BIT TIMER/EVENT COUNTER  
Figure 9-13. Square-Wave Output Operation Timing was added.  
Note was added to Figure 16-4. Serial Operating Mode Register CHAPTER 16 SERIAL INTERFACE  
0 Format.  
CHANNEL 0 (µPD78054 Subseries)  
(4) Synchronization control and (5) Automatic transmit/receive CHAPTER 18 SERIAL INTERFACE  
Interval time were added to 18.4.3 3-wire serial I/O mode  
operation with automatic transmit/receive function.  
Precaution was added to 19.1 (3) 3-wire serial I/O mode  
(MSB-/LSB-first switchable).  
CHANNEL 1  
CHAPTER 19 SERIAL INTERFACE  
CHANNEL 2  
Figure 19-3. Serial Operating Mode Register 2 Format was  
changed.  
Table 19-2. Serial Interface Channel 2 Operating Mode Settings  
was changed.  
Figure 19-10. Receive Error Timing was corrected.  
19.4.4 Limitations when UART mode is used was added.  
APPENDIX A DIFFERENCES BETWEEN µPD78054, 78054Y  
APPENDIX A DIFFERENCES BETWEEN  
SUBSERIES AND µPD78058F,78058FY SUBSERIES was added. µPD78054, 78054Y SUBSERIES AND  
µPD78058F,78058FY SUBSERIES  
APPENDIX B DEVELOPMENT TOOL  
Entire revision: Support for in-circuit emulator IE-78K0-NS  
APPENDIX C EMBEDDED SOFTWARE  
Entire revision: Deletion of fuzzy inference development support  
system  
APPENDIX B DEVELOPMENT TOOL  
APPENDIX C EMBEDDED SOFTWARE  
601  
Download from Www.Somanuals.com. All Manuals Search And Download.  
[MEMO]  
602  
Download from Www.Somanuals.com. All Manuals Search And Download.  
AlthoughNEChastakenallpossiblesteps  
toensurethatthedocumentationsupplied  
to our customers is complete, bug free  
and up-to-date, we readily accept that  
errorsmayoccur. Despiteallthecareand  
precautions we've taken, you may  
encounterproblemsinthedocumentation.  
Please complete this form whenever  
you'd like to report errors or suggest  
improvements to us.  
Facsimile Message  
From:  
Name  
Company  
Tel.  
FAX  
Address  
Thank you for your kind support.  
North America  
Hong Kong, Philippines, Oceania Asian Nations except Philippines  
NEC Electronics Inc.  
Corporate Communications Dept.  
Fax: 1-800-729-9288  
1-408-588-6130  
NEC Electronics Hong Kong Ltd.  
Fax: +852-2886-9022/9044  
NEC Electronics Singapore Pte. Ltd.  
Fax: +65-250-3583  
Korea  
Japan  
Europe  
NEC Electronics Hong Kong Ltd.  
Seoul Branch  
Fax: 02-528-4411  
NEC Semiconductor Technical Hotline  
Fax: 044-548-7900  
NEC Electronics (Europe) GmbH  
Technical Documentation Dept.  
Fax: +49-211-6503-274  
South America  
Taiwan  
NEC do Brasil S.A.  
Fax: +55-11-6465-6829  
NEC Electronics Taiwan Ltd.  
Fax: 02-719-5951  
I would like to report the following error/make the following suggestion:  
Document title:  
Document number:  
Page number:  
If possible, please fax the referenced page or drawing.  
Document Rating  
Clarity  
Excellent  
Good  
Acceptable  
Poor  
Technical Accuracy  
Organization  
CS 98.2  
Download from Www.Somanuals.com. All Manuals Search And Download.  

Milwaukee Soldering Gun MW14 User Manual
Nilfisk ALTO Vacuum Cleaner 692003 User Manual
Nilfisk ALTO Vacuum Cleaner SR 1550C User Manual
NuTone Fan ILF120 User Manual
Omron Healthcare Nebulizer NE U22 User Manual
Panasonic All in One Printer DP 453D User Manual
Panasonic Camcorder AG DVC62 User Manual
Panasonic DVD Recorder DMR E30 User Manual
Panasonic Typewriter KX E3000 User Manual
Patton electronic Model Vehicle 1030 User Manual