DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P3116
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3116 replaces the µPD753108’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the µPD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
development stage using the µPD753104, 753106, or 753108, and for use in small-scale production.
Detailed information about functions is provided in the following User’s Manual. Be sure to read it before
designing:
µPD753108 User’s Manual: U10890E
FEATURES
Compatible with µPD753108
Memory capacity:
• PROM: 16384 × 8 bits
• RAM: 512 × 4 bits
Can be operated in same power supply voltage range as the mask version µPD753108
• VDD = 1.8 to 5.5 V
On-chip LCD controller/driver
QTOPTM microcontroller
Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.
This support includes writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number
Package
µPD75P3116GC-AB8
µPD75P3116GK-8A8
µPD75P3116GC-8BS
64-pin plastic QFP (14 × 14)
64-pin plastic LQFP (12 × 12)
64-pin plastic LQFP (14 × 14)
Caution This device does not provide an internal pull-up resistor connection function by means of mask
option.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U11369EJ3V0DS00 (3rd edition)
The mark
shows major revised points.
Date Published March 2002 N CP(K)
Printed in Japan
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1994
µPD75P3116
CONTENTS
1. PIN CONFIGURATION (TOP VIEW).................................................................................................
4
6
2. BLOCK DIAGRAM ............................................................................................................................
3. PIN FUNCTIONS ...............................................................................................................................
3.1 Port Pins ...................................................................................................................................................
3.2 Non-Port Pins ...........................................................................................................................................
7
7
9
3.3 Pin I/O Circuits ......................................................................................................................................... 11
3.4 Recommended Connection of Unused Pins ......................................................................................... 13
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 14
4.1 Differences Between Mk I Mode and Mk II Mode................................................................................... 14
4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 15
5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108 ............................... 16
6. MEMORY CONFIGURATION ........................................................................................................... 17
7. INSTRUCTION SET .......................................................................................................................... 19
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28
8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28
8.2 Program Memory Write Procedure ......................................................................................................... 29
8.3 Program Memory Read Procedure ......................................................................................................... 30
8.4 One-Time PROM Screening .................................................................................................................... 31
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 32
10. CHARACTERISTIC CURVES (REFERENCE VALUES) .................................................................. 47
11. PACKAGE DRAWINGS ................................................................................................................... 49
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 52
APPENDIX A. LIST OF µPD75308B, 753108, AND 75P3116 FUNCTIONS......................................... 54
APPENDIX B. DEVELOPMENT TOOLS................................................................................................ 56
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 65
Data Sheet U11369EJ3V0DS
3
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µPD75P3116
1. PIN CONFIGURATION (TOP VIEW)
• 64-pin plastic QFP (14 × 14): µPD75P3116GC-AB8
• 64-pin plastic LQFP (12 × 12): µPD75P3116GK-8A8
• 64-pin plastic LQFP (14 × 14): µPD75P3116GC-8BS
64636261605958575655545352515049
48
BIAS
VLC0
VLC1
1
2
3
4
5
6
7
8
S12
S13
S14
S15
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VLC2
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
Vss
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
9
P50/D4
P51/D5
P52/D6
P53/D7
10
11
12
13
14
15
16
P60/KR0/D0
P61/KR1/D1
P62/KR2/D2
17181920212223242526272829303132
Note Always connect the VPP pin directly to VDD during normal operation.
Data Sheet U11369EJ3V0DS
4
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µPD75P3116
PIN IDENTIFICATIONS
P00 to P03:
P10 to P13:
P20 to P23:
P30 to P33:
P50 to P53:
P60 to P63:
P80 to P83:
P90 to P93:
KR0 to KR3:
SCK:
Port 0
COM0 to COM3:
VLC0 to VLC2:
BIAS:
Common output 0 to 3
Port 1
LCD power supply 0 to 2
LCD power supply bias control
LCD clock
Port 2
Port 3
LCDCL:
SYNC:
Port 5
LCD synchronization
Port 6
TI0 to TI2:
PTO0 to PTO2:
BUZ:
Timer input 0 to 2
Port 8
Programmable timer output 0 to 2
Buzzer clock
Port 9
Key return 0 to 3
Serial clock
Serial input
Serial output
Serial data bus 0, 1
Reset
PCL:
Programmable clock
INT0, 1, 4:
INT2:
External vectored interrupt 0, 1, 4
External test input 2
SI:
SO:
X1, X2:
Main system clock oscillation 1, 2
Subsystem clock oscillation 1, 2
Programming power supply
Positive power supply
Ground
SB0, SB1:
RESET:
XT1, XT2:
VPP:
MD0 to MD3:
D0 to D7:
S0 to S23:
Mode selection 0 to 3
Data bus 0 to 7
Segment output 0 to 23
VDD:
Vss:
Data Sheet U11369EJ3V0DS
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5
µPD75P3116
2. BLOCK DIAGRAM
4
4
4
4
4
4
4
4
Port 0
Port 1
Port 2
Port 3
Port 5
Port 6
Port 8
Port 9
P00 to P03
P10 to P13
P20 to P23
Watch
BUZ/P23
timer
INTW fLCD
SP (8)
SBS
Program
counter (14)
Basic
interval
timer/
watchdog
timer
CY
ALU
Bank
P30/MD0 to
P33/MD3
INTBT
8-bit
TI0/P13
timer/event
counter #0
P50/D4 to
P53/D7
PTO0/P20
General-
purpose
register
INTT0 TOUT0
P60/D0 to
P63/D3
INTT1
TI1/TI2/
P12/INT2
8-bit
timer/event
counter #1
Cascaded
16-bit
timer/
event
counter
Program
memory
(PROM)
PTO1/P21
P80 to P83
P90 to P93
Decode
and
control
PTO2/
PCL/P22
TOUT0
8-bit
timer/event
counter #2
16384 × 8 bits
Data
memory
(RAM)
INTT2
SI/SB1/P03
SO/SB0/P02
SCK/P01
Clocked
serial
interface
512 × 4 bits
16 S0 to S15
INTCSI TOUT0
INT1
S16/P93 to
S19/P90
4
INT0/P10
INT1/P11
INT4/P00
S20/P83 to
S23/P80
4
Interrupt
control
INT2/P12/TI1/TI2
P60/KR0 to
P63/KR3
4
COM0 to COM3
4
fx/2N
CPU clock Φ
BIAS
fLCD
System clock
generator
Bit sequential
buffer (16)
VLC0
Clock
output
control
Clock
divider
Standby
control
VLC1
VLC2
Main
Sub
SYNC/P31
LCDCL/P30
VDD Vss VPP RESET
X1 X2 XT1XT2
PCL/PTO2/P22
Data Sheet U11369EJ3V0DS
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6
µPD75P3116
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
I/O
Alternate
Function
Function
8-Bit
I/O
Status
I/O Circuit
After Reset TypeNote 1
P00
Input INT4
SCK
4-bit input port (Port 0)
Connection of an internal pull-up resistor can be
specified by a software setting in 3-bit units.
—
—
—
—
—
Input
Input
Input
Input
<B>
P01
<F>-A
<F>-B
<M>-C
<B>-C
P02
SO/SB0
SI/SB1
Input INT0
P03
P10
4-bit input port (Port 1)
Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit units.
P10/INT0 can be used to select a noise eliminator.
P11
INT1
P12
TI1/TI2/INT2
TI0
P13
P20
I/O
I/O
I/O
PTO0
PTO1
PCL/PTO2
BUZ
4-bit I/O port (Port 2)
Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit units.
E-B
E-B
M-E
P21
P22
P23
P30
LCDCL/MD0
SYNC/MD1
MD2
Programmable 4-bit I/O port (Port 3)
Input and output can be specified in 1-bit units.
Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit units.
P31
P32
P33
MD3
P50Note 2
P51Note 2
P52Note 2
P53Note 2
D4
N-ch open-drain 4-bit I/O port (Port 5)
When set to open-drain, the withstanding voltage
is 13 V.
High
impedance
D5
D6
D7
Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.
2. The low-level input leakage current increases when input instructions or bit manipulation instructions are
executed.
Data Sheet U11369EJ3V0DS
7
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µPD75P3116
3.1 Port Pins (2/2)
Pin Name
I/O
I/O
Alternate
Function
Function
8-Bit
I/O
Status
I/O Circuit
After Reset TypeNote 1
P60
KR0/D0
Programmable 4-bit I/O port (Port 6)
—
Input
Input
Input
<F>-A
Input and output can be specified in 1-bit units.
Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit units.
P61
P62
P63
P80
P81
P82
P83
P90
P91
P92
P93
KR1/D1
KR2/D2
KR3/D3
S23
I/O
I/O
4-bit I/O port (Port 8)
√
H
H
Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit unitsNote 2
.
S22
S21
S20
S19
Programmable 4-bit I/O port (Port 9)
Connection of an internal pull-up resistor can be
specified by a software setting in 4-bit unitsNote 2
S18
.
S17
S16
Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.
2. Do not connect an internal pull-up resistor by software when these pins are used as segment signal outputs.
Data Sheet U11369EJ3V0DS
8
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µPD75P3116
3.2 Non-Port Pins (1/2)
Pin Name
I/O
Alternate
Function
Function
Status
I/O Circuit
After Reset TypeNote 1
TI0
Input P13
P12/INT2/TI2
P12/INT2/TI1
Output P20
External event pulse input to timer/event counter
Input
Input
<B>-C
TI1
TI2
PTO0
PTO1
PTO2
PCL
Timer/event counter output
E-B
P21
P22/PCL
P22/PTO2
P23
Clock output
BUZ
Frequency output (for buzzer or system clock trimming)
Serial clock I/O
SCK
SO/SB0
I/O
P01
Input
<F>-A
<F>-B
P02
Serial data output
Serial data bus I/O
SI/SB1
INT4
P03
Serial data input
Serial data bus I/O
<M>-C
<B>
Input P00
Input P10
Edge detection vectored interrupt input
(valid for detecting both rising and falling edges)
INT0
Edge detection vectored interrupt
input (detection edge is selectable)
INT0/P10 can be used to select a
noise eliminator.
With noise eliminator/
asynchronous is
selectable
Input
<B>-C
INT1
P11
Asynchronous
INT2
Input P12/TI1/TI2
Rising edge detection testable input Asynchronous
Parallel falling edge detection testable input
KR0 to KR3
X1
I/O
P60 to P63
—
Input
—
<F>-A
—
Input
Ceramic/crystal resonator connection for main system
clock oscillation. If using an external clock, input the signal
to X1 and input the inverted signal to X2.
X2
—
XT1
Input
—
Crystal resonator connection for subsystem clock oscillation.
If using an external clock, input the signal to XT1 and input
the inverted signal to XT2. XT1 can be used as a 1-bit (test)
input.
—
—
XT2
—
RESET
Input
—
System reset input (low-level active)
—
<B>
E-B
MD0 to MD3
D0 to D3
D4 to D7
VPPNote 2
Input P30 to P33
Mode selection for program memory (PROM) write/verify
Input
Input
I/O
P60/KR0 to P63/KR3 Data bus for program memory (PROM) write/verify
P50 to P53
<F>-A
M-E
—
—
—
Programmable power supply voltage applied for program
memory (PROM) write/verify.
—
During normal operation, connect directly to VDD.
Apply +12.5 V for PROM write/verify.
VDD
Vss
—
—
—
—
Positive power supply
Ground potential
—
—
—
—
Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.
2. The VPP pin does not operate correctly when it is not connected to the VDD pin during normal operation.
Data Sheet U11369EJ3V0DS
9
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µPD75P3116
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Alternate
Function
Function
Status
I/O Circuit
Type
After Reset
Note 1
Input
S0 to S15
Output
—
Segment signal output
Segment signal output
Segment signal output
Common signal output
G-A
H
S16 to S19
S20 to S23
Output P93 to P90
Output P83 to P80
Input
H
COM0 to COM3 Output
—
—
—
Note 1
—
G-B
—
VLC0 to VLC2
BIAS
—
Power supply for driving LCD
Output
Output for external split resistor cut
Note 2
Input
—
LCDCLNote 3
SYNCNote 3
Output P30/MD0
Output P31/MD1
Clock output for driving external expansion driver
Clock output for synchronization of external expansion driver
E-B
E-B
Input
Notes 1. VLCX (X = 0, 1, 2) is selected as the input source for the display outputs as shown below.
S0 to S23: VLC1, COM0 to COM2: VLC2, COM3: VLC0
2. When the split resistor is incorporated:
Low level
When the split resistor is not incorporated: High impedance
3. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
Data Sheet U11369EJ3V0DS
10
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µPD75P3116
3.3 Pin I/O Circuits
The I/O circuits for the µPD75P3116’s pins are shown in abbreviated form below.
Type A
Type D
VDD
VDD
Data
P-ch
OUT
P-ch
IN
Output
disable
N-ch
N-ch
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
CMOS standard input buffer
Type B
Type E-B
VDD
P.U.R.
P.U.R.
P-ch
enable
IN
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt-triggered input with hysteresis characteristics.
P.U.R. : Pull-Up Resistor
Type B-C
Type F-A
VDD
VDD
P.U.R.
P.U.R.
P-ch
P.U.R.
enable
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
Output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
(Continued)
Data Sheet U11369EJ3V0DS
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11
µPD75P3116
(Continued)
Type F-B
Type H
VDD
P.U.R.
P-ch
P.U.R.
enable
Output
disable
(P)
VDD
P-ch
N-ch
IN/OUT
SEG
data
Type G-A
Type E-B
P-ch
IN/OUT
Data
Output
disable
N-ch
Data
Output
disable
(N)
Output
disable
P.U.R. : Pull-Up Resistor
Type G-A
Type M-C
VDD
P-ch
N-ch
VLC0
P.U.R.
P-ch
IN/OUT
P-ch
N-ch
VLC1
P.U.R.
enable
P-ch N-ch
Data
OUT
N-ch
Output
disable
SEG
data
N-ch
P-ch
N-ch
VLC2
N-ch
P.U.R. : Pull-Up Resistor
Type G-B
Type M-E
IN/OUT
Data
P-ch
N-ch
N-ch
VLC0
(+13 V
withstand-
ing
Output
disable
P-ch
N-ch
VLC1
VDD
voltage)
P-ch N-ch
Input instruction
P-ch
P.U.R.Note
OUT
COM
data
N-ch P-ch
Voltage
controller
P-ch
N-ch
(+13 V
withstanding
voltage)
VLC2
N-ch
Note Pull-up resistor that operates only when an input
instruction is executed. (The current flows from
VDD to a pin when the pin is at low level.)
Data Sheet U11369EJ3V0DS
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12
µPD75P3116
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Unused Pin Connections
Pin
Recommended Connection
Connect to Vss or VDD.
Input: Independently connect to Vss or VDD via a resistor.
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
Output: Leave open.
Connect to Vss.
P10/INT0 and P11/INT1
P12/TI1/TI2/INT2
P13/TI0
Connect to Vss or VDD.
P20/PTO0
Input:
Independently connect to Vss or VDD via a resistor.
P21/PTO1
Output: Leave open.
P22/PTO2/PCL
P23/BUZ
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
P50/D4 to P53/D7
Input:
Connect to Vss.
Output: Connect to Vss.
P60/KR0/D0 to P63/KR3/D3
Input:
Independently connect to Vss or VDD via a resistor.
Output: Leave open.
S0 to S15
Leave open.
COM0 to COM3
S16/P93 to S19/P90
S20/P83 to S23/P80
VLC0 to VLC2
Input:
Independently connect to Vss or VDD via a resistor.
Output: Leave open.
Connect to Vss.
BIAS
Connect to Vss only when none of VLC0, VLC1 or VLC2 is used.
In other cases, leave open.
XT1Note
XT2Note
VPP
Connect to Vss.
Leave open.
Always connect to VDD directly.
Note When the subsystem clock is not used, select SOS.0 = 1 (on-chip feedback
resistor not used).
Data Sheet U11369EJ3V0DS
13
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µPD75P3116
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting the stack bank selection (SBS) register for the µPD75P3116 enables the program memory to be switched
between the Mk I mode and Mk II mode. This function is applicable when using the µPD75P3116 to evaluate the
µPD753104, 753106, or 753108.
When bit 3 of SBS is set to 1: Sets the Mk I mode (supports the Mk I mode for the µPD753104, 753106, and 753108)
When bit 3 of SBS is set to 0: Sets the Mk II mode (supports the Mk II mode for the µPD753104, 753106, and 753108)
4.1 Differences Between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode for the µPD75P3116.
Table 4-1. Differences Between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC13-0
16384
512 × 4
Program memory (bytes)
Data memory (bits)
Stack
Stack bank
Selectable via memory banks 0 and 1
No. of stack bytes
2 bytes
3 bytes
Instruction
Instruction
BRA !addr1 instruction
CALLA !addr1 instruction
CALL !addr instruction
Not available
Available
3 machine cycles
2 machine cycles
4 machine cycles
3 machine cycles
execution time CALLF !faddr instruction
Supported mask ROM products
When set to Mk I mode:
When set to Mk II mode:
µPD753104, 753106, and 753108
µPD753104, 753106, and 753108
Caution The Mk II mode supports a program area exceeding 16 KB for the 75X and 75XL Series. Therefore, this
mode is effective for enhancing software compatibility with products that have a program area of more
than 16 KB.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.
Data Sheet U11369EJ3V0DS
14
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µPD75P3116
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format
of the stack bank selection register.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
suretoinitializethestackbankselectionregisterto100×BNote atthebeginningoftheprogram. WhenusingtheMkIImode,
be sure to initialize it to 000×BNote
Note Set the desired value for ×.
Figure 4-1. Format of Stack Bank Selection Register
.
Address
3
2
1
0
Symbol
F84H SBS3 SBS2 SBS1 SBS0 SBS
Stack area specification
0
0
1
1
0
1
0
1
Memory bank 0
Memory bank 1
Setting prohibited
0
Be sure to enter “0” for bit 2.
Mode selection specification
0
1
Mk II mode
Mk I mode
Caution SBS3 is set to 1 after RESET input, and consequently the CPU operates in the Mk I mode. When using
instructions for the Mk II mode, set SBS3 to 0 and set the Mk II mode before using the instructions.
Data Sheet U11369EJ3V0DS
15
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µPD75P3116
5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108
The µPD75P3116 replaces the internal mask ROM in the µPD753104, 753106, and 753108 with a one-time PROM
andfeaturesexpandedROMcapacity. TheµPD75P3116’sMkImodesupportstheMkImodeintheµPD753104,753106,
and 753108 and the µPD75P3116’s Mk II mode supports the Mk II mode in the µPD753104, 753106, and 753108.
Table 5-1 lists differences between the µPD75P3116 and the µPD753104, 753106, and 753108. Be sure to check the
differences between these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For details of the CPU functions and internal hardware, refer to the User’s Manual.
Table 5-1. Differences Between µPD75P3116 and µPD753104, 753106, and 753108
Item
µPD753104
12 bits
µPD753106
13 bits
µPD753108
µPD75P3116
14 bits
Program counter
Program memory (bytes)
Mask ROM
4096
Mask ROM
6144
Mask ROM
8192
One-time PROM
16384
Data memory (× 4 bits)
512
Mask options
Pull-up resistor for
Port 5
Available
Not available
(Not on chip)
(On chip/not on chip can be specified.)
Split resistor for
LCD driving power supply
Wait time after
RESET
Available
Not available
(Fixed to 215/fX)Note
(Selectable between 217/fX and 215/fX)Note
Feedback resistor
of subsystem clock
Available
(Use/not use can be selected.)
Not available
(Enable)
Pin configuration Pins 5 to 8
Pins 10 to 13
Pins 14 to 17
Pin 21
P30 to P33
P50 to P53
P60/KR0 to P63/KR3
IC
P30/MD0 to P33/MD3
P50/D4 to P53/D7
P60/KR0/D0 to P63/KR3/D3
VPP
Other
Noise resistance and noise radiation may differ due to the different circuit sizes and mask
layouts.
Note 217/fX: 21.8 ms at 6.0 MHz operation, 31.3 ms at 4.19 MHz operation
215/fX: 5.46 ms at 6.0 MHz operation, 7.81 ms at 4.19 MHz operation
Caution There are differences in the amount of noise tolerance and noise radiation between flash memory
versionsandmaskROMversions. Whenconsideringchangingfromaflashmemoryversiontoamask
ROM version during the process from experimental manufacturing to mass production, make sure to
sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM
versions.
Data Sheet U11369EJ3V0DS
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µPD75P3116
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
7
6
5
0
0000H MBE RBE Internal reset start address (higher 6 bits)
Internal reset start address (lower 8 bits)
0002H MBE RBE INTBT/INT4 start address (higher 6 bits)
INTBT/INT4 start address (lower 8 bits)
CALLF
!faddr instruction
entry address
0004H MBE RBE INT0 start address (higher 6 bits)
INT0 start address (lower 8 bits)
0006H MBE RBE INT1 start address (higher 6 bits)
INT1 start address (lower 8 bits)
BRCB
!caddr instruction
branch address
0008H MBE RBE INTCSI start address (higher 6 bits)
INTCSI start address (lower 8 bits)
Branch addresses for
the following instructions
• BR !addr
000AH MBE RBE INTT0 start address (higher 6 bits)
INTT0 start address (lower 8 bits)
• CALL !addr
• BRA !addr1Note
• CALLA !addr1Note
• BR BCDE
000CH MBE RBE INTT1/INTT2 start address (higher 6 bits)
INTT1/INTT2 start address (lower 8 bits)
• BR BCXA
Branch/call
address
by GETI
0020H
Reference table for GETI instruction
007FH
0080H
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
07FFH
0800H
0FFFH
1000H
BRCB
!caddr instruction
branch address
1FFFH
2000H
BRCB
!caddr instruction
branch address
2FFFH
3000H
BRCB
!caddr instruction
branch address
3FFFH
Note Can only be used in the Mk II mode.
Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
to addresses with changes in the PC’s lower 8 bits only.
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µPD75P3116
Figure 6-2. Data Memory Map
Data memory
Memory bank
000H
General-purpose register area
(32 × 4)
01FH
020H
0
256 × 4
(224 × 4)
Stack areaNote
Data area
static RAM
(512 × 4)
0FFH
100H
256 × 4
(224 × 4)
1DFH
1E0H
1
Display data memory
(24 × 4)
1F7H
1F8H
(8 × 4)
1FFH
F80H
Not incorporated
128 × 4
15
Peripheral hardware area
FFFH
Note
Memory bank 0 or 1 can be selected as the stack area.
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18
µPD75P3116
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the
instruction’s operand representations (for further details, refer to the RA75X Assembler Package Language User’s
Manual (U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and
+ or – symbols are keywords that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further details, refer to the
User’s Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation
reg
Coding Format
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
XA, BC, DE, HL
BC, DE, HL
reg1
rp
rp1
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
BC, DE, HL, XA’, BC’, DE’, HL’
HL, HL+, HL–, DE, DL
rp’1
rpa
rpa1
n4
DE, DL
4-bit immediate data or label
n8
8-bit immediate data or label
mem
bit
8-bit immediate data or labelNote
2-bit immediate data or label
fmem
pmem
addr
addr1
caddr
faddr
taddr
PORTn
IE×××
RBn
MBn
FB0H to FBFH, FF0H to FFFH immediate data or label
FC0H to FFFH immediate data or label
0000H to 3FFFH immediate data or label
0000H to 3FFFH immediate data or label (Mk II mode only)
12-bit immediate data or label
11-bit immediate data or label
20H to 7FH immediate data (however, bit 0 = 0) or label
Port 0 to Port 3, Port 5, Port 6, Port 8, Port 9
IEBT, IECSI, IET0 to IET2, IE0 to IE2, IE4, IEW
RB0 to RB3
MB0, MB1, MB15
Note When processing 8-bit data, only even-numbered addresses can be specified.
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µPD75P3116
(2) Operation conventions
A:
A register; 4-bit accumulator
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
X:
X register
XA:
BC:
DE:
HL:
Register pair (XA); 8-bit accumulator
Register pair (BC)
Register pair (DE)
Register pair (HL)
XA’:
BC’:
DE’:
HL’:
PC:
SP:
CY:
PSW:
MBE:
RBE:
PORTn:
IME:
IPS:
IE×××:
RBS:
MBS:
PCC:
.:
Expansion register pair (XA’)
Expansion register pair (BC’)
Expansion register pair (DE’)
Expansion register pair (HL’)
Program counter
Stack pointer
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Register bank enable flag
Port n (n = 0 to 3, 5, 6, 8, 9)
Interrupt master enable flag
Interrupt priority selection register
Interrupt enable flag
Register bank selection register
Memory bank selection register
Processor clock control register
Delimiter for address and bit
Data addressed with ××
Hexadecimal data
(××):
××H:
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µPD75P3116
(3) Description of symbols used in addressing area
MB = MBE • MBS
*1
MBS = 0, 1, 15
MB = 0
*2
*3
MBE = 0:
MB = 0 (000H to 07FH)
MB = 15 (F80Hto FFFH)
MB = MBS
Data memory
addressing
MBE = 1:
MBS = 0, 1, 15
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
*4
*5
*6
addr = 0000H to 3FFFH
addr, addr1 = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
caddr = 0000H to 0FFFH (PC13, 12 = 00B) or
1000H to 1FFFH (PC13, 12 = 01B) or
2000H to 2FFFH (PC13, 12 = 10B) or
3000H to 3FFFH (PC13, 12 = 11B)
*7
Program memory
addressing
*8
faddr = 0000H to 07FFH
*9
*10
*11
taddr = 0020H to 007FH
addr1 = 0000H to 3FFFH (Mk II mode only)
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping skip-specified instructions. The value of S varies as
shown below.
• No skip ..................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction.... S = 1
• Skipped instruction is 3-byte instructionNote .............. S = 2
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1
Caution The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select from among four cycle
times.
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µPD75P3116
Instruction
Group
Mnemonic
MOV
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
Transfer
A, #n4
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
1
1
1
2
2
2
2
1
A ← n4
String-effect A
reg1, #n4
XA, #n8
reg1 ← n4
XA ← n8
HL ← n8
rp2 ← n8
A ← (HL)
String-effect A
String-effect B
HL, #n8
rp2, #n8
A, @HL
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
@HL, A
2+S A ← (HL), then L ← L+1
L = 0
2+S A ← (HL), then L ← L–1
L = FH
1
2
1
2
2
2
2
2
2
2
2
2
1
A ← (rpa1)
XA ← (HL)
(HL) ← A
@HL, XA
A, mem
(HL) ← XA
A ← (mem)
XA ← (mem)
(mem) ← A
(mem) ← XA
A ← reg
XA, mem
mem, A
mem, XA
A, reg
XA, rp’
XA ← rp’
reg1, A
reg1 ← A
rp’1, XA
rp’1 ← XA
A ←→ (HL)
XCH
A, @HL
*1
*1
*1
*2
*1
*3
*3
A, @HL+
A, @HL–
A, @rpa1
XA, @HL
A, mem
2+S A ←→ (HL), then L ← L+1
L = 0
2+S A ←→ (HL), then L ← L–1
L = FH
1
2
2
2
1
2
3
3
3
3
A ←→ (rpa1)
XA ←→ (HL)
A ←→ (mem)
XA, mem
A, reg1
XA ←→ (mem)
A ←→ reg1
XA, rp’
XA ←→ rp’
Table
MOVT
XA, @PCDE
XA, @PCXA
XA, @BCDENote
XA, @BCXANote
XA ← (PC13-8+DE)ROM
XA ← (PC13-8+XA)ROM
XA ← (BCDE)ROM
XA ← (BCXA)ROM
reference
*6
*6
Note Only the lower 3 bits in the B register are valid.
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22
µPD75P3116
Instruction
Group
Mnemonic
MOV1
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
Bit transfer
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1
1
2
2
1
2
2
2
2
2
2
2
CY ← (fmem.bit)
*4
CY ← (pmem7-2+L3-2.bit(L1-0))
CY ← (H+mem3-0.bit)
*5
*1
(fmem.bit) ← CY
*4
(pmem7-2+L3-2.bit(L1-0)) ← CY
(H+mem3-0.bit) ← CY
*5
*1
Arithmetic
ADDS
1+S A ← A+n4
carry
XA, #n8
A, @HL
XA, rp’
2+S XA ← XA+n8
1+S A ← A+(HL)
2+S XA ← XA+rp’
2+S rp’1 ← rp’1+XA
carry
carry
carry
carry
*1
*1
*1
*1
rp’1, XA
A, @HL
XA, rp’
ADDC
SUBS
SUBC
AND
1
2
2
A, CY ← A+(HL)+CY
XA, CY ← XA+rp’+CY
rp’1, XA
A, @HL
XA, rp’
rp’1, CY ← rp’1+XA+CY
1+S A ← A–(HL)
2+S XA ← XA–rp’
2+S rp’1 ← rp’1–XA
borrow
borrow
borrow
rp’1, XA
A, @HL
XA, rp’
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
A, CY ← A–(HL)–CY
XA, CY ← XA–rp’–CY
rp’1, XA
A, #n4
rp’1, CY ← rp’1–XA–CY
A ← A n4
^
A, @HL
XA, rp’
A ← A (HL)
*1
*1
*1
^
XA ← XA rp’
^
rp’1, XA
A, #n4
rp’1 ← rp’1 XA
^
OR
A ← A v n4
A, @HL
XA, rp’
A ← A v (HL)
XA ← XA v rp’
rp’1 ← rp’1 v XA
A ← A v n4
rp’1, XA
A, #n4
XOR
A, @HL
XA, rp’
A ← A v (HL)
XA ← XA v rp’
rp’1 ← rp’1 v XA
CY ← A0, A3 ← CY, An-1 ← An
A ← A
rp’1, XA
A
Accumulator
RORC
manipulation NOT
A
Increment/
decrement
INCS
reg
1+S reg ← reg+1
1+S rp1 ← rp1+1
2+S (HL) ← (HL)+1
2+S (mem) ← (mem)+1
1+S reg ← reg–1
2+S rp’ ← rp’–1
reg = 0
rp1
rp1 = 00H
(HL) = 0
(mem) = 0
reg = FH
rp’ = FFH
@HL
*1
*3
mem
DECS
reg
rp’
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µPD75P3116
Instruction
Group
Mnemonic
SKE
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
Comparison
reg, #n4
2
2
1
2
2
2
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2+S Skip if reg=n4
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
@HL, #n4
A, @HL
2+S Skip if (HL)=n4
1+S Skip if A=(HL)
2+S Skip if XA=(HL)
2+S Skip if A=reg
2+S Skip if XA=rp’
*1
*1
*1
XA, @HL
A, reg
XA, rp’
XA = rp’
Carry flag
SET1
CY
1
1
CY ← 1
manipulation CLR1
CY
CY ← 0
SKT
CY
1+S Skip if CY=1
CY = 1
NOT1
CY
1
2
2
2
2
2
2
2
2
CY ← CY
Memory bit
SET1
CLR1
SKT
mem.bit
(mem.bit) ← 1
(fmem.bit) ← 1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
manipulation
fmem.bit
pmem.@L
@H+mem.bit
mem.bit
(pmem7-2+L3-2.bit(L1-0)) ← 1
(H+mem3-0.bit) ← 1
(mem.bit) ← 0
fmem.bit
(fmem.bit) ← 0
pmem.@L
@H+mem.bit
mem.bit
(pmem7-2+L3-2.bit(L1-0)) ← 0
(H+mem3-0.bit) ← 0
2+S Skip if(mem.bit)=1
(mem.bit) = 1
fmem.bit
2+S Skip if(fmem.bit)=1
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
(mem.bit) = 0
pmem.@L
@H+mem.bit
mem.bit
2+S Skip if(pmem7-2+L3-2.bit(L1-0))=1
2+S Skip if(H+mem3-0.bit)=1
2+S Skip if(mem.bit)=0
SKF
fmem.bit
2+S Skip if(fmem.bit)=0
(fmem.bit) = 0
(pmem.@L) = 0
(@H+mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
pmem.@L
@H+mem.bit
fmem.bit
2+S Skip if(pmem7-2+L3-2.bit(L1-0))=0
2+S Skip if(H+mem3-0.bit)=0
2+S Skip if(fmem.bit)=1 and clear
2+S Skip if(pmem7-2+L3-2.bit(L1-0))=1 and clear
2+S Skip if(H+mem3-0.bit)=1 and clear
SKTCLR
AND1
OR1
pmem.@L
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
2
2
2
2
2
2
2
2
2
CY ← CY (fmem.bit)
^
CY ← CY (pmem7-2+L3-2.bit(L1-0))
^
CY ← CY (H+mem3-0.bit)
^
CY ← CY v (fmem.bit)
CY ← CY v (pmem7-2+L3-2.bit(L1-0))
CY ← CY v (H+mem3-0.bit)
CY ← CY v (fmem.bit)
XOR1
CY ← CY v (pmem7-2+L3-2.bit(L1-0))
CY ← CY v (H+mem3-0.bit)
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µPD75P3116
Instruction
Group
Mnemonic
BRNote 1
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
Branch
addr
—
—
PC13-0 ← addr
*6
Use the assembler to select the
most appropriate instruction
among the following.
• BR !addr
• BRCB !caddr
• BR $addr
addr1
—
—
PC13-0 ← addr1
*11
Use the assembler to select
the most appropriate instruction
among the following.
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
!addr
3
1
1
2
2
2
2
3
2
3
2
2
3
3
3
3
3
2
PC13-0 ← addr
*6
*7
$addr
$addr1
PCDE
PCXA
BCDE
BCXA
PC13-0 ← addr
PC13-0 ← addr1
PC13-0 ← PC13-8+DE
PC13-0 ← PC13-8+XA
PC13-0 ← BCDENote 2
PC13-0 ← BCXANote 2
PC13-0 ← addr1
*6
*6
BRANote 1 !addr1
BRCB !caddr
*11
*8
PC13-0 ← PC13, 12+caddr11-0
Notes 1. The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in
the MK I mode.
2. Only the lower two bits in the B register are valid.
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µPD75P3116
Instruction
Group
Mnemonic
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
Subroutine
CALLANote !addr1
3
3
(SP–6)(SP–3)(SP–4)
←
PC11-0
*11
stack control
(SP–5) ← 0, 0, PC13, 12
(SP–2) ← X, X, MBE, RBE
PC13-0 ← addr1, SP ← SP–6
(SP–4)(SP–1)(SP–2) ← PC11-0
(SP–3) ← MBE, RBE, PC13, 12
PC13-0 ← addr, SP ← SP–4
(SP–6)(SP–3)(SP–4) ← PC11-0
(SP–5) ← 0, 0, PC13, 12
CALLNote
!addr
3
3
4
*6
(SP–2) ← X, X, MBE, RBE
PC13-0 ← addr, SP ← SP–6
(SP–4)(SP–1)(SP–2) ← PC11-0
(SP–3) ← MBE, RBE, PC13, 12
PC13-0 ← 000+faddr, SP ← SP–4
CALLFNote !faddr
2
1
1
2
3
*9
(SP–6)(SP–3)(SP–4)
←
PC11-0
(SP–5) ← 0, 0, PC13, 12
(SP–2) ← X, X, MBE, RBE
PC13-0 ← 000+faddr, SP ← SP–6
MBE, RBE, PC13, 12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4
RETNote
3
X, X, MBE, RBE ← (SP+4)
PC11-0 ← (SP)(SP+3)(SP+2)
0, 0, PC13, 12 ← (SP+1)
SP ← SP+6
RETSNote
3+S MBE, RBE, PC13, 12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4
Unconditional
then skip unconditionally
X, X, MBE, RBE ← (SP+4)
PC11-0 ← (SP)(SP+3)(SP+2)
0, 0, PC13, 12 ← (SP+1)
SP ← SP+6
then skip unconditionally
RETINote
1
3
MBE, RBE, PC13, 12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5)
SP ← SP+6
0, 0, PC13, 12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP+6
Note The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in the Mk I mode.
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µPD75P3116
Instruction
Group
Mnemonic
PUSH
Operand
No. of Machine
Bytes Cycle
Operation
Addressing
Area
Skip
Condition
Subroutine
rp
1
2
1
2
(SP–1)(SP–2) ← rp, SP ← SP–2
stack control
BS
(SP–1) ← MBS, (SP–2) ← RBS,
SP ← SP–2
POP
EI
rp
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
3
rp ← (SP+1)(SP), SP ← SP+2
MBS ← (SP+1), RBS ← (SP), SP ← SP+2
IME(IPS.3) ← 1
BS
Interrupt
control
IE×××
IE××× ← 1
DI
IME(IPS.3) ← 0
IE×××
IE××× ← 0
I/O
INNote 1
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
A ← PORTn (n=0 to 3, 5, 6, 8, 9)
XA ← PORTn+1, PORTn (n=8)
PORTn ← A (n=2 to 3, 5, 6, 8, 9)
PORTn+1, PORTn ← XA (n=8)
Set HALT Mode(PCC.2 ← 1)
Set STOP Mode(PCC.3 ← 1)
No Operation
OUTNote 1
CPU control
Special
HALT
STOP
NOP
SEL
RBn
MBn
RBS ← n (n=0 to 3)
MBS ← n (n=0, 1, 15)
GETINotes 2, 3 taddr
• When using TBR instruction
*10
PC13-0 ← (taddr)5-0+(taddr+1)
- - - - - - - - - - - - - - - - - - - - - - - - - - -
• When using TCALL instruction
- - - - - - - - - - - -
(SP–4)(SP–1)(SP–2) ← PC11-0
(SP–3)
←
MBE, RBE, PC13, 12
PC13-0 ← (taddr)5-0+(taddr+1)
SP ← SP–4
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
Determined by
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr+1) instructions
referenced
instruction
1
3
• When using TBR instruction
*10
PC13-0 ← (taddr)5-0+(taddr+1)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
4
• When using TCALL instruction
(SP–6)(SP–3)(SP–4) ← PC11-0
(SP–5) ← 0, 0, PC13, 12
(SP–2) ← X, X, MBE, RBE
PC13-0 ← (taddr)5-0+(taddr+1)
SP ← SP–6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
Determined by
referenced
3
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr+1) instructions
instruction
Notes 1. Setting MBE = 0 or MBE = 1, MBS = 15 is required during the execution of the IN or OUT instruction.
2. The TBR and TCALL instructions are assembler quasi-directives for the GETI instruction table definitions.
3. The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in
the Mk I mode.
Data Sheet U11369EJ3V0DS
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µPD75P3116
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory contained in the µPD75P3116 is a 16384 × 8-bit one-time PROM that can be electrically written
one time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the
X1 pin is used instead of address input as a method for updating addresses.
Pin
Function
VPP
Pin where program voltage is applied during program memory
write/verify (usually VDD potential)
X1, X2
Clock input pins for address updating during program memory
write/verify. Input the X1 pin’s inverted signal to the X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/verify
8-bit data I/O pins for program memory write/verify
D0/P60 to D3/P63
(lower 4 bits)
D4/P50 to D7/P53
(higher 4 bits)
VDD
Pin where power supply voltage is applied. Apply 1.8 to 5.5 V
in normal operation mode and +6 V for program memory write/
verify.
Caution Pins not used for program memory write/verify should be connected to Vss.
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P3116 enters the program memory write/
verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation Mode Specification
Operation Mode
VPP
VDD
MD0 MD1 MD2 MD3
+12.5 V
+6 V
H
L
L
H
L
×
H
H
H
H
L
Zero-clear program memory address
Write mode
H
H
H
L
Verify mode
H
Program inhibit mode
×: L or H
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28
µPD75P3116
8.2 Program Memory Write Procedure
Program memory can be written at high speed using the following procedure.
(1) Pull down unused pins to Vss via resistors. Set the X1 pin to low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Select the program memory address zero-clear mode.
(5) Supply 6 V to VDD and 12.5 V to VPP.
(6) Write data in the 1 ms write mode.
(7) Select the verify mode. If the data is written, go to (8) and if not, repeat (6) and (7).
(8) Additional write. (X: Number of write operations from (6) and (7)) × 1 ms
(9) Apply four pulses to the X1 pin to increment the program memory address by one.
(10) Repeat (6) to (9) until the end address is reached.
(11) Select the program memory address zero-clear mode.
(12) Return the VDD- and VPP-pin voltages to 5 V.
(13) Turn off the power.
The following figure shows steps (2) to (9).
X repetitions
Address
increment
Additional
write
Write
Verify
VPP
VDD
VPP
VDD
VDD + 1
VDD
X1
D0/P60 to D3/P63
D4/P50 to D7/P53
Data
Data input
Data input
output
MD0/P30
MD1/P31
MD2/P32
MD3/P33
Data Sheet U11369EJ3V0DS
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µPD75P3116
8.3 Program Memory Read Procedure
The µPD75P3116 can read program memory contents using the following procedure.
(1) Pull down unused pins to VSS via resistors. Set the X1 pin to low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Select the program memory address zero-clear mode.
(5) Supply 6 V to VDD and 12.5 V to VPP.
(6) Select the verify mode. Apply four pulses to the X1 pin. The data stored in one address will be output every four
clock pulses.
(7) Select the program memory address zero-clear mode.
(8) Return the VDD- and VPP-pin voltages to 5 V.
(9) Turn off the power.
The following figure shows steps (2) to (7).
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P60 to D3/P63
D4/P50 to D7/P53
Data output
Data output
MD0/P30
MD1/P31
MD2/P32
MD3/P33
“L”
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30
µPD75P3116
8.4 One-Time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
that after the required data is written and the PROM is stored under the temperature and time conditions shown below,
the PROM should be verified via screening.
Storage Temperature
125˚C
Storage Time
24 hours
NECoffersQTOPmicrocontrollersforwhichone-timePROMwriting, marking, screening, andverificationareprovided
at additional cost. For further details, contact an NEC sales representative.
Data Sheet U11369EJ3V0DS
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µPD75P3116
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25˚C)
Parameter
Symbol
VDD
Test Conditions
Rating
Unit
V
Power supply voltage
–0.3 to +7.0
–0.3 to +13.5
PROM power supply
voltage
VPP
V
Input voltage
VI1
VI2
VO
IOH
Except port 5
–0.3 to VDD + 0.3
V
V
Port 5 (N-ch open drain)
–0.3 to +14
Output voltage
–0.3 to VDD + 0.3
V
Output current, high
Per pin
–10
mA
mA
mA
mA
˚C
Total of all pins
Per pin
–30
30
Output current, low
IOL
Total of all pins
220
Operating ambient
temperature
TA
–40 to +85Note
Storage temperature
Tstg
–65 to +150
˚C
Note When LCD is driven in normal mode: TA = –10 to +85˚C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Capacitance (TA = 25˚C, VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
COUT
CIO
15
pF
15
pF
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32
µPD75P3116
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Constant
Parameter
Test Conditions
MIN. TYP. MAX. Unit
Ceramic
Oscillation
1.0
6.0Note 2 MHz
X2
X1
resonator
frequency (fx)Note 1
Oscillation
C1
C2
After VDD reaches oscil-
lation voltage range MIN.
4
ms
stabilization timeNote 3
Oscillation
VDD
Crystal
1.0
6.0Note 2 MHz
X2
X1
resonator
frequency (fx)Note 1
Oscillation
C1
C2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
10
30
ms
stabilization timeNote 3
X1 input
VDD
External
clock
1.0
6.0Note 2 MHz
X1
X2
frequency (fx)Note 1
X1 input
83.3
500
ns
high-/low-level width
(tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. When the power supply voltage is 1.8 V ≤ VDD < 2.7 V and the oscillation frequency is 4.19 MHz < fx
≤ 6.0 MHz, setting the processor clock control register (PCC) to 0011 makes 1 machine cycle less than
the required 0.95 µs. Therefore, set PCC to a value other than 0011.
3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing
the STOP mode.
Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VDD.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Data Sheet U11369EJ3V0DS
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µPD75P3116
Subsystem Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
Recommended Constant
Parameter
Oscillation
Test Conditions
MIN. TYP. MAX. Unit
32 32.768 35
kHz
XT2
XT1
resonator
frequency (fXT)Note 1
Oscillation
R
C3
C4
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
1.0
2
s
stabilization timeNote 2
XT1 input frequency
(fXT)Note 1
10
VDD
External
clock
32
5
100
kHz
µs
XT2
XT1
XT1 input high-/low-level
width (tXTH, tXTL)
15
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD.
Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VDD.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Thesubsystemclockoscillatorisdesignedasalowamplificationcircuittoprovidelowconsumption
current, and is more liable to misoperation by noise than the main system clock oscillator. Special
care should therefore be taken regarding the wiring method when the subsystem clock is used.
Data Sheet U11369EJ3V0DS
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µPD75P3116
DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IOL
Test Conditions
MIN. TYP. MAX. Unit
Output current, low
Per pin
15
150
mA
mA
V
Total of all pins
Ports 2, 3, 8, and 9
Input voltage, high
VIH1
VIH2
VIH3
2.7 ≤ VDD ≤ 5.5 V 0.7VDD
1.8 ≤ VDD < 2.7 V 0.9VDD
2.7 ≤ VDD ≤ 5.5 V 0.8VDD
1.8 ≤ VDD < 2.7 V 0.9VDD
2.7 ≤ VDD ≤ 5.5 V 0.7VDD
1.8 ≤ VDD < 2.7 V 0.9VDD
VDD – 0.1
VDD
VDD
V
Ports 0, 1, 6, RESET
VDD
V
VDD
V
Port 5
13
V
(N-ch open-drain)
X1, XT1
13
V
VIH4
VDD
V
Input voltage, low
VIL1
Ports 2, 3, 5, 8, and 9
2.7 ≤ VDD ≤ 5.5 V
1.8 ≤ VDD < 2.7 V
2.7 ≤ VDD ≤ 5.5 V
1.8 ≤ VDD < 2.7 V
0
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
0
V
VIL2
Ports 0, 1, 6, RESET
X1, XT1
0
V
0
0
V
VIL3
VOH
VOL1
V
Output voltage, high
Output voltage, low
SCK, SO, Ports 2, 3, 6, 8, and 9 IOH = –1.0 mA
VDD – 0.5
V
SCK, SO, Ports 2, 3, 5, 6, 8, and 9 IOL = 15 mA,
0.2
2.0
V
VDD = 4.5 to 5.5 V
IOL = 1.6 mA
When N-ch open-drain
0.4
V
V
VOL2
SB0, SB1
0.2VDD
pull-up resistor ≥ 1 kΩ
Pins other than X1, XT1
X1, XT1
Input leakage
current, high
ILIH1
ILIH2
ILIH3
ILIL1
ILIL2
ILIL3
VIN = VDD
3
20
20
–3
–20
–3
µA
µA
µA
µA
µA
µA
VIN = 13 V
VIN = 0 V
Port 5 (N-ch open-drain)
Pins other than X1, XT1, and Port 5
X1, XT1
Input leakage
current, low
Port 5 (N-ch open-drain)
When another instruction than input
instruction is executed
Port 5
(N-ch open-drain)
When input
instruction is
executed
VDD = 1.8 to 5.5 V
–30
–27
–8
3
µA
µA
µA
µA
µA
µA
VDD = 5.0 V
VDD = 3.0 V
–10
–3
Output leakage
current, high
ILOH1
ILOH2
ILOL
VOUT = VDD
SCK, SO/SB0, SB1, Ports 2, 3, 6, 8, and 9
VOUT = 13 V Port 5 (N-ch open-drain)
VOUT = 0 V
20
–3
Output leakage
current, low
On-chip pull-up resistor RL
VIN = 0 V
Ports 0, 1, 2, 3, 6, 8, and 9
(Excluding P00 pin)
50
100
200
kΩ
Data Sheet U11369EJ3V0DS
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µPD75P3116
DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
VLCD
Test Conditions
TA = –40 to +85°C
TA = –10 to +85°C
MIN. TYP. MAX. Unit
LCD drive voltage
VAC0 = 0
2.7
2.2
1.8
VDD
VDD
VDD
4
V
V
VAC0 = 1
V
VAC currentNote 1
IVAC
VAC0 = 1, VDD = 2.0 V 10%
1
µA
V
LCD output voltage
deviationNote 2 (common)
VODC
lo = 1.0 µA
lo = 0.5 µA
6.00 MHzNote 4
VLCD0 = VLCD
0
0
0.2
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
LCD output voltage
deviationNote 2 (segment)
VODS
0.2
V
1.8 V ≤ VLCD ≤ VDD
Supply currentNote 3
IDD1
VDD = 5.0 V 10%Note 5
3.2
0.55
0.7
0.25
2.5
0.45
0.65
0.22
45
9.5
1.6
2.0
0.8
7.5
1.35
1.8
0.7
130
55
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Crystal oscillation VDD = 3.0 V 10%Note 6
C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 5.0 V 10%Note 5
Crystal oscillation VDD = 3.0 V 10%Note 6
C1 = C2 = 22 pF HALT mode VDD = 5.0 V 10%
VDD = 3.0 V 10%
32.768 kHzNote 7 Low-voltage VDD = 3.0 V 10%
IDD2
IDD1
IDD2
IDD3
4.19 MHzNote 4
Crystal oscillation modeNote 8
VDD = 2.0 V 10%
VDD = 3.0 V, TA = 25˚C
VDD = 3.0 V 10%
VDD = 3.0 V, TA = 25˚C
20
45
90
Low current
consumption
modeNote 9
42
120
85
42
IDD4
HALT mode
VDD = 3.0 V 10%
5.5
2.2
5.5
4.0
4.0
18
Low-
voltage
modeNote 8
VDD = 2.0 V 10%
VDD = 3.0 V, TA = 25˚C
VDD = 3.0 V 10%
7
12
Low
12
current
consump-
VDD = 3.0 V,
8
tion mode
TA = 25˚C
Note 9
IDD5
XT1 = 0 VNote 10 VDD = 5.0 V 10%
0.05
0.02
0.02
10
5
µA
µA
µA
STOP mode
VDD = 3.0 V
10%
TA = –40 to +85˚C
TA = 25˚C
3
Notes 1. Set to VAC0 = 0 when the low current consumption mode and the stop mode are used. If VAC0 = 1
is set, the current increases for approx. 1 µA.
2. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
3. Not including currents flowing through on-chip pull-up resistors.
4. Including oscillation of the subsystem clock.
5. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-
speed mode.
6. When PCC is set to 0000 and the device is operated in the low-speed mode.
7. When the system clock control register (SCC) is set to 1001 and the device is operated on the
subsystem clock, with main system clock oscillation stopped.
8. When the sub-oscillator control register (SOS) is set to 0000.
9. When SOS is set to 0010.
10. When SOS is set to 00×1 and the feedback resistor of the sub-oscillator is not used (×: Don’t care).
Data Sheet U11369EJ3V0DS
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µPD75P3116
AC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
CPU clock cycle
timeNote 1
Symbol
tCY
Test Conditions
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
MIN. TYP. MAX. Unit
Operating on
0.67
0.95
114
64
64
µs
µs
µs
main system clock
(Min. instruction execution
time = 1 machine cycle)
TI0, TI1, TI2 input
frequency
Operating on subsystem clock
122
125
fTI
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
0
1.0
MHz
kHz
µs
275
TI0, TI1, TI2 input
high-/low-level width
Interrupt input high-/
low-level width
tTIH, tTIL
0.48
1.8
Note 2
10
µs
tINTH, tINTL INT0
IM02 = 0
IM02 = 1
µs
µs
INT1, 2, 4
KR0 to KR7
10
µs
10
µs
RESET low-level width
tRSL
10
µs
Notes 1. Thecycletime(minimuminstruction
execution time) of the CPU clock
(Φ) is determined by the oscillation
frequency of the connected
resonator (and external clock), the
systemclockcontrolregister(SCC)
and the processor clock control
register (PCC). The figure on the
right indicates the cycle time tCY
versus supply voltage VDD
characteristicswiththemainsystem
clock operating.
tCY vs. VDD
(Main system clock operation)
64
60
6
5
Guaranteed operation
range
4
3
2
1
2. 2tCY or 128/fx is set by setting the
interrupt mode register (IM0).
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
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µPD75P3116
Serial Transfer Operation
2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
tKCY1
Test Conditions
MIN.
1300
3800
tKCY1/2–50
tKCY1/2–150
150
TYP. MAX. Unit
SCK cycle time
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
RL = 1 kΩ,
ns
ns
ns
ns
ns
ns
ns
ns
SCK high-/low-level
width
tKL1, tKH1
SINote 1 setup time
tSIK1
(to SCK↑)
500
SINote 1 hold time
(from SCK↑)
tKSI1
400
600
SONote 1 output delay
tKSO1
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
ns
ns
time from SCK↓
CL = 100 pFNote 2
0
1000
Notes 1. In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead.
2. RL and CL are the load resistance and load capacitance of the SO output lines, respectively.
2-wire and 3-wire serial I/O mode (SCK...External clock input): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
800
3200
400
1600
100
150
400
600
0
TYP. MAX. Unit
SCK cycle time
tKCY2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
RL = 1 kΩ,
ns
ns
ns
ns
ns
ns
ns
ns
SCK high-/low-level
width
tKL2, tKH2
SINote 1 setup time
(to SCK↑)
tSIK2
SINote 1 hold time
(from SCK↑)
tKSI2
SONote 1 output delay
time from SCK↓
tKSO2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
ns
ns
CL = 100 pFNote 2
0
1000
Notes 1. In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead.
2. RL and CL are the load resistance and load capacitance of the SO output lines, respectively.
Data Sheet U11369EJ3V0DS
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µPD75P3116
SBI mode (SCK...Internal clock output (master)): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
tKCY3
Test Conditions
MIN.
1300
3800
tKCY3/2–50
tKCY3/2–150
150
TYP. MAX. Unit
SCK cycle time
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
ns
ns
ns
ns
ns
ns
ns
SCK high-/low-level
width
tKL3, tKH3
SB0, 1 setup time
(to SCK↑)
tSIK3
500
SB0, 1 hold time (from SCK↑) tKSI3
tKCY3/2
0
SB0, 1 output delay
time from SCK↓
tKSO3
RL = 1 kΩ,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
250
ns
ns
ns
ns
ns
ns
CL = 100 pFNote
0
1000
SB0, 1↓ from SCK↑
SCK↓ from SB0, 1↓
SB0, 1 low-level width
SB0, 1 high-level width
tKSB
tSBK
tSBL
tSBH
tKCY3
tKCY3
tKCY3
tKCY3
Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
SBI mode (SCK...External clock input (slave)): (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
800
3200
400
1600
100
150
tKCY4/2
0
TYP. MAX. Unit
SCK cycle time
tKCY4
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
ns
ns
ns
ns
ns
ns
ns
SCK high-/low-level
width
tKL4, tKH4
SB0, 1 setup time
(to SCK↑)
tSIK4
SB0, 1 hold time (from SCK↑) tKSI4
SB0, 1 output delay
time from SCK↓
tKSO4
RL = 1 kΩ,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
ns
ns
ns
ns
ns
ns
CL = 100 pFNote
0
1000
SB0, 1↓ from SCK↑
SCK↓ from SB0, 1↓
SB0, 1 low-level width
SB0, 1 high-level width
tKSB
tSBK
tSBL
tSBH
tKCY4
tKCY4
tKCY4
tKCY4
Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
Data Sheet U11369EJ3V0DS
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µPD75P3116
AC Timing Test Points (Excluding X1, XT1 Input)
VIH (MIN.)
VIL (MAX.)
VIH (MIN.)
VIL (MAX.)
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Clock Timing
1/fX
tXL
tXH
VDD – 0.1 V
X1 input
0.1 V
1/fXT
tXTL
tXTH
VDD – 0.1 V
XT1 input
0.1 V
TI0, TI1, TI2 Timing
1/fTI
tTIL
tTIH
TI0, TI1, TI2
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40
µPD75P3116
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SI
Input data
tKSO1, 2
SO
Output data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
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41
µPD75P3116
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKH3, 4
tKL3, 4
SCK
tSIK3, 4
tKSI3, 4
tKSB
tSBL
tSBH
tSBK
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tSIK3, 4
tKSB
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4
KR0 to 7
RESET input timing
tRSL
RESET
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42
µPD75P3116
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85˚C)
Parameter
Symbol
tSREL
Test Conditions
MIN. TYP. MAX. Unit
Release signal set time
Oscillation stabilization
wait timeNote 1
0
µs
ms
ms
tWAIT
Release by RESET
Release by interrupt request
215/fX
Note 2
Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the start of oscillation.
2. Depends on the basic interval timer mode register (BTM) settings (see the table below).
BTM3 BTM2 BTM1 BTM0
Wait Time
fx = 4.19 MHz
220/fx (approx. 250 ms)
217/fx (approx. 31.3 ms)
215/fx (approx. 7.81 ms)
213/fx (approx. 1.95 ms)
fx = 6.0 MHz
—
—
—
—
0
0
1
1
0
1
0
1
0
1
1
1
220/fx (approx. 175 ms)
217/fx (approx. 21.8 ms)
215/fx (approx. 5.46 ms)
213/fx (approx. 1.37 ms)
Data Sheet U11369EJ3V0DS
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µPD75P3116
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
Data Sheet U11369EJ3V0DS
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µPD75P3116
DC Programming Characteristics (TA = 25 5˚C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter
Symbol
VIH1
VIH2
VIL1
VIL2
ILI
Test Conditions
Except X1 and X2 pins
X1, X2
MIN.
TYP.
MAX.
VDD
Unit
V
Input voltage, high
0.7VDD
VDD – 0.5
VDD
V
Input voltage, low
Except X1 and X2 pins
X1, X2
0
0
0.3VDD
0.4
V
V
Input leakage current
Output voltage, high
Output voltage, low
VIN = VIL or VIH
IOH = –1 mA
10
µA
V
VOH
VOL
IDD
VDD – 1.0
IOL = 1.6 mA
0.4
30
30
V
VDD power supply current
VPP power supply current
mA
mA
IPP
MD0 = VIL, MD1 = VIH
Cautions 1. Do not exceed +13.5 V for VPP, including the overshoot.
2. VDD must be applied before VPP, and cut after VPP.
AC Programming Characteristics (TA = 25 5˚C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter
Symbol
tAS
Test Conditions
MIN.
TYP.
MAX.
Unit
µs
µs
µs
µs
µs
ns
Address setup timeNote (to MD0↓)
MD1 setup time (to MD0↓)
2
2
tM1S
tDS
Data setup time (to MD0↓)
2
Address hold timeNote (from MD0↑)
Data hold time (from MD0↑)
Data output float delay time from MD0↑
VPP setup time (to MD3↑)
tAH
2
tDH
2
tDF
0
130
tVPS
tVDS
tPW
2
µs
µs
ms
ms
µs
µs
µs
µs
µs
µs
MHz
µs
µs
µs
µs
µs
ns
VDD setup time (to MD3↑)
2
Initial program pulse width
0.95
0.95
2
1.0
1.05
21.0
Additional program pulse width
MD0 setup time (to MD1↑)
tOPW
tM0S
tDV
Data output delay time from MD0↓
MD1 hold time (from MD0↑)
MD1 recovery time (from MD0↓)
Program counter reset time
X1 input high-/low-level width
X1 input frequency
MD0 = MD1 = VIL
1
tM1H
tM1R
tPCR
tXH, tXL
fX
tM1H + tM1R ≥ 50 µs
2
2
10
0.125
4.19
Initial mode set time
tI
2
2
2
2
MD3 setup time (to MD1↑)
tM3S
tM3H
tM3SR
tDAD
tHAD
tM3HR
tDFR
MD3 hold time (from MD1↓)
MD3 setup time (to MD0↓)
Data output delay time from AddressNote
Data output hold time from AddressNote
MD3 hold time (from MD0↑)
Data output float delay time from MD3↓
During program memory read
During program memory read
During program memory read
During program memory read
During program memory read
2
0
2
130
µs
µs
2
Note The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not connected to
a pin.
Data Sheet U11369EJ3V0DS
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µPD75P3116
Program Memory Write Timing
tVPS
VPP
VPP
VDD
tVDS
VDD + 1
VDD
VDD
tXH
X1
tXL
tAH
D0/P60 to D3/P60
D4/P50 to D7/P53
Data input
Data output
Data input
Data input
tDS
tDS
tDH
tI
tDH
tDV
tDF
tAS
MD0/P30
MD1/P31
tPW
tM1R
tM0S
tOPW
tPCR
tM1S
tM1H
MD2/P32
MD3/P33
tM3S
tM3H
Program Memory Read Timing
tVPS
VPP
VDD
VPP
tVDS
VDD + 1
VDD
VDD
tXH
X1
tDAD
tXL
tDV
tHAD
D0/P60 to D3/P60
D4/P50 to D7/P53
Data output
Data output
tDFR
tI
tM3HR
MD0/P30
MD1/P31
tPCR
MD2/P32
MD3/P33
tM3SR
Data Sheet U11369EJ3V0DS
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46
µPD75P3116
10. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 6.0 MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
1.0
0.5
Main system clock
HALT mode + 32 kHz oscillation
0.1
Subsystem clock operation
mode (SOS.1 = 0)
Main system clock STOP
mode + 32 kHz oscillation
(SOS.1 = 0) and
0.05
subsystem clock HALT mode
(SOS.1 = 0)
Main system clock STOP
mode + 32 kHz oscillation
(SOS.1 = 1) and subsystem
clock HALT mode (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
XT2
Crystal resonator
6.0 MHz
Crystal resonator
32.768 kHz
330 kΩ
22 pF
22 pF
22 pF 22 pF
VDD
VDD
0.001
0
1
2
3
4
5
6
7
8
Supply voltage VDD (V)
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47
µPD75P3116
IDD vs VDD (Main System Clock: 4.19 MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
1.0
0.5
PCC = 0000
Main system clock
HALT mode + 32 kHz oscillation
0.1
Subsystem clock operation
mode (SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 0) and
main system clock STOP mode
+ 32 kHz oscillation (SOS.1 = 0)
0.05
Main system clock STOP
mode + 32 kHz oscillation
(SOS.1 = 1)
and subsystem clock HALT
mode (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
XT2
Crystal resonator
4.19 MHz
Crystal resonator
32.768 kHz
330 kΩ
22 pF
22 pF
22 pF 22 pF
VDD
VDD
0.001
0
1
2
3
4
5
6
7
8
Supply voltage VDD (V)
Data Sheet U11369EJ3V0DS
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48
µPD75P3116
11. PACKAGE DRAWINGS
64-PIN PLASTIC QFP (14x14)
A
B
48
49
33
32
detail of lead end
S
C D
Q
R
64
17
16
1
F
P
J
G
M
H
I
K
S
L
N
S
M
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
17.6 0.4
14.0 0.2
14.0 0.2
17.6 0.4
1.0
G
1.0
+0.08
0.37
H
-0.07
I
J
0.15
0.8 (T.P.)
1.8 0.2
0.8 0.2
K
L
+0.08
0.17
M
-0.07
N
P
Q
R
S
0.10
2.55 0.1
0.1 0.1
5° 5°
2.85 MAX.
P64GC-80-AB8-5
Data Sheet U11369EJ3V0DS
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µPD75P3116
64-PIN PLASTIC LQFP (12x12)
A
B
48
49
33
32
detail of lead end
S
C
D
R
Q
64
1
17
16
F
G
J
M
H
I
K
P
S
M
L
N
S
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
14.8 0.4
12.0 0.2
12.0 0.2
14.8 0.4
1.125
1.125
0.32 0.08
0.13
J
0.65 (T.P.)
1.4 0.2
0.6 0.2
K
L
+0.08
0.17
M
-0.07
N
P
Q
R
S
0.10
1.4 0.1
0.125 0.075
5° 5°
1.7 MAX.
P64GK-65-8A8-3
Data Sheet U11369EJ3V0DS
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50
µPD75P3116
64-PIN PLASTIC LQFP (14x14)
A
B
48
49
33
32
detail of lead end
S
P
C
D
T
R
L
64
1
17
16
U
Q
F
G
J
M
H
I
ITEM MILLIMETERS
A
B
C
D
F
17.2 0.2
14.0 0.2
14.0 0.2
17.2 0.2
1.0
K
S
G
1.0
+0.08
0.37
H
-0.07
N
S
M
I
J
0.20
0.8 (T.P.)
1.6 0.2
0.8
K
L
NOTE
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
+0.03
0.17
M
-0.06
N
P
Q
0.10
1.4 0.1
0.127 0.075
+4°
3°
R
-3°
S
T
1.7 MAX.
0.25
U
0.886 0.15
P64GC-80-8BS
Data Sheet U11369EJ3V0DS
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51
µPD75P3116
12. RECOMMENDED SOLDERING CONDITIONS
The µPD75P3116 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD75P3116GC-AB8: 64-pin plastic QFP (14 × 14)
Soldering
Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less
IR35-00-3
VP15-00-3
WS60-00-1
—
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD75P3116GK-8A8: 64-pin plastic LQFP (12 × 12)
Soldering
Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Twice or less
IR35-107-2
VP15-107-2
WS 60-107-1
—
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Twice or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U11369EJ3V0DS
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µPD75P3116
Table 12-1. Surface Mounting Type Soldering Conditions (2/2)
(3) µPD75P3116GC-8BS: 64-pin plastic LQFP (14 × 14)
Soldering
Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Twice or less
IR35-00-2
VP15-00-2
WS60-00-1
—
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Twice or less
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U11369EJ3V0DS
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µPD75P3116
APPENDIX A. LIST OF µPD75308B, 753108, AND 75P3116 FUNCTIONS
Parameter
Program memory
µPD75308B
Mask ROM
0000H to 1F7FH
(8064 × 8 bits)
µPD753108
Mask ROM
0000H to 1FFFH
(8192 × 8 bits)
µPD75P3116
One-time PROM
0000H to 3FFFH
(16384 × 8 bits)
Data memory
CPU
000H to 1FFH
(512 × 4 bits)
75X Standard
75XL CPU
Instruction
execution
time
When main system
clock is selected
0.95, 1.91, 15.3 µs
• 0.95, 1.91, 3.81, 15.3 µs (during 4.19 MHz operation)
(during 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (during 6.0 MHz operation)
When subsystem
clock is selected
122 µs (during 32.768 kHz operation)
Stack
SBS register
None
SBS.3 = 1: Mk I mode selection
SBS.3 = 0: Mk II mode selection
Stack area
000H to 0FFH
000H to 1FFH
Subroutine call instruc- 2-byte stack
tion stack operation
When Mk I mode: 2-byte stack
When Mk II mode: 3-byte stack
Instruction
BRA !addr1
CALLA !addr1
Unavailable
When Mk I mode: Unavailable
When Mk II mode: Available
MOVT XA, @BCDE
MOVT XA, @BCXA
BR BCDE
Available
BR BCXA
CALL !addr
3 machine cycles
2 machine cycles
Mk I mode: 3 machine cycles
Mk II mode: 4 machine cycles
CALLF !faddr
Mk I mode: 2 machine cycles
Mk II mode: 3 machine cycles
I/O ports
CMOS input
CMOS I/O
8
8
16
8
20
0
Bit port output
N-ch open-drain I/O
Total
8
4
40
32
LCD controller/driver
Segment selection: 24/28/32 Segment selection: 16/20/24 segments
(can be changed to CMOS (can be changed to CMOS I/O port in 4-bit units; max. 8)
I/O port in 4-bit units; max.
8)
Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty
(1/3 bias), 1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by
using mask option.
No on-chip split resistor
for LCD driver
Timer
3 channels
5 channels
• Basic interval timer:
1 channel
• 8-bit timer/event counter:
1 channel
• Basic interval timer/watchdog timer: 1 channel
• 8-bit timer/event counter: 3 channels
(can be used as 16-bit timer/event counter)
• Watch timer: 1 channel
• Watch timer: 1 channel
Data Sheet U11369EJ3V0DS
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54
µPD75P3116
Parameter
Clock output (PCL)
µPD75308B
µPD753108
µPD75P3116
Φ, 524, 262, 65.5 kHz
• Φ, 524, 262, 65.5 kHz
(Main system clock:
(Main system clock: during 4.19 MHz operation)
during 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz
(Main system clock: during 6.0 MHz operation)
BUZ output (BUZ)
2 kHz
• 2, 4, 32 kHz
(Main system clock:
during 4.19 MHz operation)
(Main system clock: during 4.19 MHz operation or
subsystem clock: during 32.768 kHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: during 6.0 MHz operation)
Serial interface
SOS register
3 modes are available
• 3-wire serial I/O mode ··· MSB/LSB can be selected for transfer first bit
• 2-wire serial I/O mode
• SBI mode
Feedback resistor
cut flag (SOS.0)
None
Contained
Contained
Sub-oscillator current
cut flag (SOS.1)
None
Register bank selection register (RBS)
Standby release by INT0
Vectored interrupts
None
Yes
No
Yes
External: 3, Internal: 3
VDD = 2.0 to 6.0 V
TA = –40 to +85°C
External: 3, Internal: 5
VDD = 1.8 to 5.5 V
Supply voltage
Operating ambient temperature
Package
• 80-pin plastic QFP
(14 × 20)
• 64-pin plastic QFP
(14 × 14)
• 64-pin plastic QFP
(14 × 14)
• 64-pin plastic LQFP
• 80-pin plastic QFP
• 64-pin plastic LQFP
(14 × 14)
• 80-pin plastic TQFP
(Fine pitch) (12 × 12)
(12 × 12)
• 64-pin plastic TQFP
(12 × 12)
(12 × 12)
• 64-pin plastic LQFP
(14 × 14)
• 64-pin plastic LQFP
(14 × 14)
Data Sheet U11369EJ3V0DS
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55
µPD75P3116
APPENDIX B. DEVELOPMENT TOOLS
The following development tools have been provided for system development using the µPD75P3116.
In the 75XL Series, a common relocatable assembler is used in combination with a device file dedicated to each model.
RA75X relocatable assembler
Host Machine
Part Number
(Product Name)
OS
Supply Medium
3.5" 2HD
PC-9800 Series
MS-DOSTM
µS5A13RA75X
Ver.3.30 to
Ver.6.2Note
IBM PC/AT™
or compatibles
Refer to OS for
IBM PCs
3.5" 2HC
µS7B13RA75X
Device file
Host Machine
Part Number
(Product Name)
OS
Supply Medium
3.5" 2HD
PC-9800 Series
MS-DOS
µS5A13DF753108
Ver.3.30 to
Ver.6.2Note
IBM PC/AT
or compatibles
Refer to OS for
IBM PCs
3.5" 2HC
µS7B13DF753108
Note Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software.
Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described
above.
Data Sheet U11369EJ3V0DS
56
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µPD75P3116
PROM Write Tools
Hardware
PG-1500
This is a PROM writer that can program a single-chip microcontroller with PROM in stand-alone
modeorunderthecontrolofahostmachinewhenconnectedwiththesuppliedaccessoryboard
and optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 Kb to 4 Mb.
PA-75P3116GC
PA-75P3116GK
This is a PROM programmer adapter for the µPD75P3116GC-AB8.
It can be used when connected to the PG-1500.
This is a PROM programmer adapter for the µPD75P3116GK-8A8.
It can be used when connected to the PG-1500.
PA-75P3116GC-8BS This is a PROM programmer adapter for the µPD75P3116GC-8BS.
It can be used when connected to the PG-1500.
Software
PG-1500 controller
Connects the PG-1500 to the host machine via serial and parallel interfaces and controls the
PG-1500 on the host machine.
Host machine
OS
Part number
(Product name)
Supply medium
3.5" 2HD
PC-9800 Series
MS-DOS
µS5A13PG1500
Ver.3.30 to
Ver.6.2Note
IBM PC/AT
Refer to OS for
3.5" 2HD
µS7B13PG1500
or compatible
IBM PCs
Note Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software.
Remark OperationofthePG-1500controllerisguaranteedonlywhenusingthehostmachineandOSdescribedabove.
Data Sheet U11369EJ3V0DS
57
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µPD75P3116
Debugging Tools
An in-circuit emulator (IE-75001-R) is provided as a program debugging tool for the µPD75P3116.
The system configuration using this in-circuit emulator is shown below.
Hardware IE-75001-R
TheIE-75001-Risanin-circuitemulatortobeusedforhardwareandsoftwaredebuggingduring
development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used in combination with an emulation board (IE-75300-R-EM) and
emulation probe (EP-753108GC-R or EP-753108GK-R) (both sold separately).
Highly efficient debugging can be performed when connected to the host machine and PROM
programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems using the µPD75P3116.
It is used in combination with the IE-75001-R.
EP-753108GC-R
This is an emulation probe for the µPD75P3116GC.
When being used, it is connected with the IE-75001-R and the IE-75300-R-EM.
EV-9200GC-64 It includes a 64-pin conversion socket (EV-9200GC-64) to facilitate connection with the target
system.
EP-753108GK-R
This is an emulation probe for the µPD75P3116GK.
When being used, it is connected with the IE-75001-R and the IE-75300-R-EM.
It includes a 64-pin conversion adapter (TGK-064SBW) to facilitate connection with the target
system.
TGK-064SBW
Note 1
Software
IE control program
This program can control the IE-75001-R on a host machine when connected to the IE-75001-R
via an RS-232C or Centronics interface.
Host machine
Part number
(Product name)
OS
Supply medium
3.5" 2HD
PC-9800 Series
MS-DOS
µS5A13IE75X
Ver.3.30 to
Ver.6.2Note 2
IBM PC/AT
Refer to OS for
3.5" 2HC
µS7B13IE75X
or compatible
IBM PCs
Notes 1. This is a product of TOKYO ELETECH CORPORATION.
Contact: Daimaru Kogyo, Ltd. Tokyo Electronic Department (TEL: +81-3-3820-7112)
Osaka Electronic Department (TEL: +81-6-6244-6672)
2. Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software.
Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS
described above.
2. The µPD753104, 753106, 753108, and 75P3116 are generically called the µPD753108 Subseries.
Data Sheet U11369EJ3V0DS
58
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µPD75P3116
OS for IBM PCs
The following operating systems for IBM PCs are supported.
OS
PC DOSTM
Version
Ver.3.1 to 6.3
J6.1/VNote to J6.3/VNote
MS-DOS
Ver.5.0 to 6.2
5.0/VNote to 6.2/VNote
IBM DOSTM
J5.02/VNote
Note Only English mode is supported.
Caution Ver. 5.0 and later include a task swapping function, but this function cannot be used in this software.
Data Sheet U11369EJ3V0DS
59
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µPD75P3116
Package Drawing and Recommended Footprint of Conversion Socket (EV-9200GC-64)
Figure B-1. EV-9200GC-64 Package Drawing (For Reference Only)
A
B
M
N
E
O
F
EV-9200GC-64
1
P
No.1 pin index
G
H
I
EV-9200GC-64-G0E
ITEM
A
MILLIMETERS
18.8
14.1
14.1
18.8
4-C 3.0
0.8
INCHES
0.74
B
0.555
0.555
0.74
C
D
E
4-C 0.118
0.031
0.236
0.622
0.728
0.236
0.622
0.728
0.315
0.307
0.098
0.079
F
G
H
I
6.0
15.8
18.5
6.0
J
K
15.8
18.5
8.0
L
M
N
O
P
7.8
2.5
2.0
Q
R
S
1.35
0.35 0.1
2.3
0.053
+0.004
–0.005
0.014
0.091
0.059
T
1.5
Data Sheet U11369EJ3V0DS
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60
µPD75P3116
Figure B-2. EV-9200GC-64 Recommended Footprint (For Reference Only)
G
J
K
L
C
B
A
EV-9200GC-64-P1E
ITEM
MILLIMETERS
19.5
INCHES
A
B
C
D
E
F
G
H
I
0.768
0.583
14.8
+0.002
+0.003
–0.002
0.8 0.02 × 15=12.0 0.05 0.031
× 0.591=0.472
–0.001
+0.002
–0.001
+0.003
–0.002
0.8 0.02 × 15=12.0 0.05 0.031
× 0.591=0.472
14.8
0.583
0.768
0.236
0.236
0.197
19.5
+0.004
6.00 0.08
6.00 0.08
0.5 0.02
2.36 0.03
2.2 0.1
1.57 0.03
–0.003
+0.004
–0.003
+0.001
–0.002
+0.001
J
0.093
0.087
0.062
–0.002
+0.004
–0.005
K
L
+0.001
–0.002
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
Caution
"SEMICONDUCTOR
DEVICE
MOUNTING
TECHNOLOGY MANUAL" (C10535E).
Data Sheet U11369EJ3V0DS
61
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µPD75P3116
Package Drawing of Conversion Adapter (TGK-064SBW)
Figure B-3. TGK-064SBW Package Drawing (For Reference Only)
A
B
L
K
X
C
M
S
V
Q
G F E D
H
I
J
W
R
N
O
P
a
Z
e
Y
k
j
h
d
i
c
b
g
f
ITEM MILLIMETERS
INCHES
0.724
ITEM MILLIMETERS
INCHES
φ
1.85
3.5
φ
A
B
C
D
E
F
18.4
a
b
c
d
e
f
0.3
0.012
0.65x15=9.75
0.65
0.026x0.591=0.384
0.026
0.073
0.138
0.079
0.154
0.052
0.052
0.232
0.031
0.094
0.106
0.305
2.0
7.75
10.15
12.55
14.95
0.65x15=9.75
11.85
18.4
0.400
3.9
0.494
1.325
1.325
5.9
G
H
I
0.589
g
h
i
0.026x0.591=0.384
0.467
0.8
J
0.724
j
2.4
k
2.7
K
L
C 2.0
12.45
10.25
7.7
C 0.079
0.490
TGK-064SBW-G1E
M
N
O
P
Q
R
S
T
0.404
0.303
10.02
14.92
11.1
0.394
0.587
0.437
1.45
0.057
1.45
0.057
φ
φ
4- 1.3
4- 0.051
U
V
W
X
Y
Z
1.8
5.0
0.071
0.197
φ
φ
5.3
0.209
4-C 1.0
4-C 0.039
φ
φ
φ
φ
3.55
0.9
0.140
0.035
Data Sheet U11369EJ3V0DS
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62
µPD75P3116
Notes on Target System Design
The following shows a diagram of the connection conditions between the emulation probe, conversion connector
and conversion socket or conversion adapter.
Design your system making allowances for conditions such as the form of parts mounted on the target system,
as shown below.
Table B-1. Distance Between In-Circuit Emulator and Conversion Socket
Emulation Probe
Conversion Socket/
Conversion Adapter
Distance Between In-Circuit Emulator
and Conversion Socket or
Conversion Adapter
EP-753108GC-R
EP-753108GK-R
EV-9200GC-64
TGK-064SBW
700 mm
700 mm
Figure B-4. Distance Between In-Circuit Emulator and Conversion Socket or Conversion Adapter (1)
In-circuit emulator
IE-75001-R
700 mm
Target system
Emulation probe
EP-753108GC-R
Conversion socket
EV-9200GC-64
DIN connector
(CN5)
Figure B-5. Distance Between In-Circuit Emulator and Conversion Socket or Conversion Adapter (2)
In-circuit emulator
IE-75001-R
700 mm
Target system
Emulation probe
EP-753108GK-R
Conversion adapter
TGK-064SBW
DIN connector
(CN5)
Data Sheet U11369EJ3V0DS
63
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µPD75P3116
Figure B-6. Connection Conditions of Target System (1)
Ground clip
64-pin GC
EP-753108GC-R
In-circuit emulator
IE-75001-R
External sense clips
8 mm
35 mm
18.5 mm
Conversion socket
EV-9200GC-64
35 mm
18.5 mm
Target system
Figure B-7. Connection Conditions of Target System (2)
Ground clip
64-pin GK
EP-753108GK-R
In-circuit emulator
IE-75001-R
9 mm
External sense clips
Notch
Conversion adapter
TGK-064SBW
13.8 mm
34 mm
18.4 mm
Notch
34 mm
18.4 mm
Target system
Data Sheet U11369EJ3V0DS
64
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µPD75P3116
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
U10086E
µPD753104, 753106, 753108 Data Sheet
µPD75P3116 Data Sheet
This document
U10890E
µPD753108 User’s Manual
75XL Series Selection Guide
U10453E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
Document No.
U12622E
RA75X Assembler Package
Operation
Language
U12385E
Structured Assembler Preprocessor
U12598E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
Document No.
EEU-1455
IE-75000-R, IE-75001-R In-Circuit Emulator
IE-75300-R-EM Emulation Board
U11354E
EP-753108GC-R, EP-753108GK-R Emulation Probe
EEU-1495
Documents Related to PROM Writing (User’s Manuals)
Document Name
Document No.
U11940E
PG-1500 PROM Programmer
PG-1500 Controller
PC-9800 Series (MS-DOS) Based
IBM PC Series (PC DOS) Based
EEU-1291
U10540E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Data Sheet U11369EJ3V0DS
65
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µPD75P3116
Other Related Documents
Document Name
Document No.
X13769E
SEMICONDUCTOR SELECTION GUIDE – Products & Packages –
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C10983E
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Data Sheet U11369EJ3V0DS
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µPD75P3116
[MEMO]
Data Sheet U11369EJ3V0DS
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µPD75P3116
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet U11369EJ3V0DS
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µPD75P3116
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics (France) S.A.
Vélizy-Villacoublay, France
Tel: 01-3067-58-00
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 01-3067-58-99
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Representación en España
Madrid, Spain
Tel: 091-504-27-87
Fax: 091-504-28-60
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 11-6462-6829
NEC Electronics Italiana S.R.L.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 021-6841-1137
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 0211-65 03 327
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
•
Branch The Netherlands
Fax: 02-2719-5951
Eindhoven, The Netherlands
Tel: 040-244 58 45
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 040-244 45 80
•
Branch Sweden
Fax: 250-3583
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
J02.3
Data Sheet U11369EJ3V0DS
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µPD75P3116
QTOP is a trademark of NEC Corporation.
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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