19-3543; Rev 0; 2/05
Dual, 65Msps, 12-Bit, IF/Baseband ADC
General Description
Features
The MAX12527 is a dual 3.3V, 12-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12527 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 620mW while delivering a typical 69.8dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12527 features a 166µW power-
down mode to conserve power during idle periods.
♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance
70.4dB/69.8dB SNR at f = 70MHz/175MHz
IN
84.4dBc/80.2dBc SFDR at f = 70MHz/175MHz
IN
♦ 3.3V Low Power Operation
647mW (Differential Clock Mode)
620mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Adjustable, Internal or External, Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
A flexible reference structure allows the MAX12527 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12527
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
♦ CMOS Outputs in Two’s Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
The MAX12527 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
♦ Small, 68-Pin Thin QFN Package
♦ 14-Bit Compatible Version Available (MAX12557)
♦ Evaluation Kit Available (Order MAX12527 EV Kit)
The MAX12527 features two parallel, 12-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12527 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
Ordering Information
TEMP RANGE PIN-PACKAGE
PART
68 Thin QFN-EP*
(10mm x 10mm x 0.8mm)
MAX12527ETK -40°C to +85°C
*EP = Exposed paddle.
For a 14-bit, pin-compatible version of this ADC, refer to
the MAX12557 data sheet.
Selector Guide
SAMPLING RATE
RESOLUTION
(Bits)
PART
Applications
(Msps)
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
MAX12557
MAX12527
65
65
14
12
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Pin Configuration appears at end of data sheet.
Low-Power Data Acquisition
________________________________________________________________ Maxim Integrated Products
1
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen-
IN
DD
DD
L
tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 65MHz, T = -40°C to
DD
CLK
A
+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= 3MHz at -0.5dBFS
MIN
TYP
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
68.1
70.7
70.4
70.2
69.3
91
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
= 3MHz at -0.5dBFS (Note 2)
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
= 3MHz at -0.5dBFS (Note 2)
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
= 3MHz at -0.5dBFS
Signal-to-Noise Plus Distortion
SINAD
dB
65.9
81.9
86.3
84.4
80.2
-92.6
-84.3
-83.7
-78.9
-98
Spurious-Free Dynamic Range
Total Harmonic Distortion
Second Harmonic
SFDR
THD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
71.1
-82.9
-69.8
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
= 3MHz at -0.5dBFS
-91.7
-94.5
-80.2
-97
HD2
= 32.5MHz at -0.5dBFS
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
-86.3
-84.4
-85.6
Third Harmonic
HD3
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
-89
Two-Tone Intermodulation
Distortion (Note 3)
TTIMD
IM3
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
IN2
-82.2
-92.2
-88.9
90.6
82.9
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
3rd-Order Intermodulation
Distortion
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
IN2
f
f
= 68.5MHz at -7dBFS
= 71.5MHz at -7dBFS
IN1
IN2
Two-Tone Spurious-Free
Dynamic Range
SFDR
TT
f
f
= 172.5MHz at -7dBFS
= 177.5MHz at -7dBFS
IN1
IN2
Full-Power Bandwidth
Aperture Delay
FPBW
Input at -0.2dBFS, -3dB rolloff
Figure 5
750
1.2
MHz
ns
t
AD
Aperture Jitter
t
<0.15
ps
RMS
AJ
INAP = INAN = COMA
INBP = INBN = COMB
Output Noise
n
0.3
LSB
RMS
OUT
_______________________________________________________________________________________
3
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen-
IN
DD
DD
L
tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 65MHz, T = -40°C to
DD
CLK
A
+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
±10% beyond full-scale
MIN
TYP
MAX
UNITS
Clock
cycle
Overdrive Recovery Time
1
INTERCHANNEL CHARACTERISTICS
f
f
or f
or f
= 70MHz at -0.5dBFS
= 175MHz at -0.5dBFS
90
INA
INA
INB
INB
Crosstalk Rejection
dB
85
Gain Matching
±0.01
±0.01
±0.1
dB
Offset Matching
%FSR
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage
V
2.000
2.048
35
2.080
V
REFOUT
REFOUT Load Regulation
REFOUT Temperature Coefficient
-1mA < I
< +1mA
mV/mA
ppm/°C
REFOUT
TC
±50
0.24
2.1
REF
Short to V —sinking
DD
REFOUT Short-Circuit Current
mA
Short to GND—sourcing
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
/V /V and V /V /V are generated internally)
V
REFAP REFAN COMA
REFBP REFBN COMB
REFIN Input Voltage
V
2.048
>50
V
REFIN
REFIN Input Resistance
R
REFIN
MΩ
V
COMA
COM_ Output Voltage
REF_P Output Voltage
REF_N Output Voltage
V
/ 2
1.60
1.65
2.418
0.882
1.536
±25
1.70
V
DD
V
COMB
V
REFAP
V
DD
/ 2 + (V
x 3/8)
x 3/8)
V
REFIN
V
REFBP
V
REFAN
V
DD
/ 2 - (V
V
V
REFIN
V
REFBN
V
V
V
REFA
= V
= V
- V
REFAP REFAN
- V
REFBP REFBN
REFA
Differential Reference Voltage
1.440
1.590
V
REFB
REFB
Differential Reference
Temperature Coefficient
TC
ppm/°C
REF
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
/V
/V
and V
/V
/V
are applied
REFAP REFAN COMA
REFBP REFBN COMB
externally, V
= V
= V
/ 2)
COMA
COMB
DD
V
REFAP
REF_P Input Voltage
V
REF_P
- V
+0.768
V
COM
V
REFBP
V
REFAN
REF_N Input Voltage
COM_ Input Voltage
V
- V
-0.768
1.65
V
V
V
REF_N
COM
V
REFBN
V
V
DD
/ 2
COM
V
V
REFA
Differential Reference Voltage
V
REF_
= V
- V
= V x 3/4
REFIN
1.536
REF_P
REF_N
REFB
4
_______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen-
IN
DD
DD
L
tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 65MHz, T = -40°C to
DD
CLK
A
+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
REF_P Sink Current
SYMBOL
CONDITIONS
= 2.418V
MIN
TYP
MAX
UNITS
I
I
REFAP
REFBP
V
REF_P
1.2
mA
I
I
REFAN
REFBN
REF_N Source Current
COM_ Sink Current
V
= 0.882V
= 1.65V
0.85
0.85
mA
mA
REF_N
I
I
COMA
COMB
V
COM_
C
C
,
REF_P
REF_P, REF_N Capacitance
13
6
pF
pF
REF_N
COM_ Capacitance
C
COM_
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
0.8 x
V
DIFFCLK/SECLK = GND, CLKN = GND
V
V
IH
V
DD
Single-Ended Input Low
Threshold
0.2 x
V
DIFFCLK/SECLK = GND, CLKN = GND
IL
V
DD
Minimum Differential Clock Input
Voltage Swing
DIFFCLK/SECLK = OV
0.2
V
P-P
DD
Differential Input Common-Mode
Voltage
DIFFCLK/SECLK = OV
V
DD
/ 2
V
DD
CLK_ Input Resistance
CLK_ Input Capacitance
R
Each input (Figure 4)
Each input
5
2
kΩ
CLK
C
pF
CLK
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4)
0.8 x
OV
Input High Threshold
Input Low Threshold
V
V
V
IH
DD
0.2 x
OV
V
IL
DD
OV applied to input
DD
±5
Input Leakage Current
µA
pF
Input connected to ground
±5
Digital Input Capacitance
C
5
DIN
DIGITAL OUTPUTS (D0A–D11A, D0B–D11B, DORA, DORB, DAV)
D0A–D11A, D0B–D11B, DORA, DORB:
0.2
0.2
I
= 200µA
Output-Voltage Low
V
OL
V
SINK
DAV: I
= 600µA
SINK
D0A–D11A, D0B–D11B, DORA, DORB:
= 200µA
OV
0.2
-
-
DD
I
SOURCE
Output-Voltage High
V
OH
V
OV
DD
DAV: I
= 600µA
SOURCE
0.2
OV applied to input
DD
±5
±5
Tri-State Leakage Current
(Note 4)
I
µA
LEAK
Input connected to ground
_______________________________________________________________________________________
5
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen-
IN
DD
DD
L
tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 65MHz, T = -40°C to
DD
CLK
A
+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
D0A–D11A, DORA,
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
D0B–D11B and DORB Tri-State
Output Capacitance (Note 4)
C
3
6
pF
OUT
DAV
DAV Tri-State Output
Capacitance (Note 4)
C
pF
POWER REQUIREMENTS
Analog Supply Voltage
V
3.15
1.70
3.30
2.0
3.60
V
V
DD
Digital Output Supply Voltage
OV
V
DD
DD
Normal operating mode
= 175MHz at -0.5dBFS,
single-ended clock
f
IN
188
(DIFFCLK/SECLK = GND)
Normal operating mode
Analog Supply Current
I
mA
VDD
f
= 175MHz at -0.5dBFS
IN
196
0.05
620
215
differential clock
(DIFFCLK/SECLK = OV
)
DD
Power-down mode (PD = OV
clock idle
)
DD
Normal operating mode
f
= 175MHz at -0.5dBFS
IN
single-ended clock
(DIFFCLK/SECLK = GND)
Normal operating mode
Analog Power Dissipation
P
VDD
mW
f
= 175MHz at -0.5dBFS
IN
647
710
differential clock
(DIFFCLK/SECLK = OV
)
DD
Power-down mode (PD = OV
clock idle
)
)
DD
0.165
19.7
Normal operating mode
f
= 175MHz at -0.5dBFS
IN
Digital Output Supply Current
I
mA
OVDD
Power-down mode (PD = OV
clock idle
DD
0.001
6
_______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen-
IN
DD
DD
L
tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f
= 65MHz, T = -40°C to
DD
CLK
A
+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 5)
Clock Pulse-Width High
Clock Pulse-Width Low
Data-Valid Delay
t
7.7
7.7
5.4
ns
ns
ns
CH
t
CL
t
DAV
Data Setup Time Before Rising
Edge of DAV
t
(Note 5)
(Note 5)
7.0
7.0
ns
SETUP
Data Hold Time After Rising Edge
of DAV
t
ns
HOLD
WAKE
Wake-Up Time from Power-Down
t
V
REFIN
= 2.048V
10
ms
Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: Specifications guaranteed by production test for ≥+25°C.
Note 3: Two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input
power of both input tones.
Note 4: During power-down, D0A–D11A, D0B–D11B, DORA, DORB, and DAV are high impedance.
Note 5: Guaranteed by design and characterization.
Typical Operating Characteristics
(V
DD
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS,
IN
DD
L
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
FFT PLOT (16,384-POINT DATA RECORD)
FFT PLOT (32,768-POINT DATA RECORD)
FFT PLOT (32,768-POINT DATA RECORD)
0
-20
0
-10
0
-10
f
f
A
= 65.00352MHz
= 32.40059MHz
= -0.506dBFS
f
= 65.00352MHz
CLK
f
f
A
= 65MHz
= 3.00125MHz
= -0.53dBFS
CLK
IN
IN
CLK
IN
IN
f
IN
= 70.00852MHz
= -0.506dBFS
-20
-20
A
IN
SNR = 70.5dB
SNR = 70.1dB
SNR = 71dB
-30
-30
SINAD = 70.2dB
THD = -86.9dBc
SFDR = 88.7dBc
SINAD = 69.8dB
THD = -82.1dBc
SFDR = 82.4dBc
SINAD = 70.9dB
THD = -94dBc
SFDR = 93.6dBc
-40
-40
-40
-50
-50
-60
-60
-60
-70
-70
HD3
HD2
HD3
-80
-80
-80
HD3
HD2
HD2
-90
-90
-100
-120
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
DD
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS,
IN
DD
L
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
TWO-TONE IMD PLOT
(16,384-POINT DATA RECORD)
TWO-TONE IMD PLOT
(16,384-POINT DATA RECORD)
FFT PLOT (32,768-POINT DATA RECORD)
0
-10
0
-20
0
-20
f
f
A
= 65.00352MHz
= 174.90525MHz
= -0.448dBFS
f
f
f
A
A
= 65.00352MHz
= 68.49889MHz
= 71.49832MHz
= -6.96dBFS
CLK
IN
IN
f
f
= 65.00352MHz
= 172.50293MHz
= -6.99dBFS
= 177.40198MHz
= -7.01dBFS
CLK
IN1
IN2
CLK
IN1
IN1
-20
A
f
SNR = 69.4dB
-30
IN1
IN2
SINAD = 68.9dB
THD = -78.6dBc
SFDR = 81.1dBc
= -7.02dBFS
A
IN2
IN2
f
-40
f
f
IN2
-40
-40
IN1
IN1
IM3 = -92.25dBc
IMD = -89.08dBc
IM3 = -88.88dBc
IMD = -82.24dBc
-50
-60
-60
-60
HD2
f
IN2
f
+ f
IN1 IN2
-70
f
- f
IN2 IN1
2f + f
IN2 IN1
HD3
-80
-80
-80
-90
-100
-110
-120
-100
-120
-100
-120
0
5
10
15
20
25
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SNR, SINAD vs. ANALOG INPUT FREQUENCY
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(f
CLK
= 65.00352MHz, A = -0.5dBFS)
IN
0.5
0.4
72
70
68
66
64
62
60
58
56
54
52
50
0.5
0.4
SNR
f
f
= 65MHz
= 3.00119MHz
CLK
IN
f
f
= 65MHz
CLK
= 3.00119MHz
IN
0.3
0.3
0.2
0.2
0.1
0.1
0
SINAD
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
0
600 1200 1800 2400 3000 3600 4200
DIGITAL OUTPUT CODE
0
50 100 150 200 250 300 350 400
(MHz)
0
600 1200 1800 2400 3000 3600 4200
DIGITAL OUTPUT CODE
f
IN
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
-THD, SFDR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.00352MHz, f = 70MHz)
(f
CLK
= 65.00352MHz, f = 70MHz)
IN
(f
CLK
= 65.00352MHz, A = -0.5dBFS)
IN
IN
95
85
75
65
55
45
35
25
75
65
55
45
35
25
15
95
90
85
80
75
70
65
60
55
50
SNR
SFDR
SFDR
-THD
SINAD
-THD
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
0
50 100 150 200 250 300 350 400
(MHz)
A
IN
A
IN
f
IN
8
_______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
DD
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS,
IN
DD
L
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
SNR, SINAD vs. CLOCK SPEED
(f = 70MHz, A = -0.5dBFS)
(f
CLK
= 65.00352MHz, f = 175MHz)
(f
CLK
= 65.00352MHz, f = 175MHz)
IN
IN
IN
IN
75
65
55
45
35
25
15
95
85
75
65
55
45
35
25
72
70
68
66
64
62
60
SNR
SNR
SFDR
SINAD
-THD
SINAD
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
(dBFS)
0
20 25 30 35 40 45 50 55 60 65
(MHz)
A
A
IN
f
CLK
IN
-THD, SFDR vs. CLOCK SPEED
(f = 70MHz, A = -0.5dBFS)
SNR, SINAD vs. CLOCK SPEED
(f = 175MHz, A = -0.5dBFS)
-THD, SFDR vs. CLOCK SPEED
(f = 175MHz, A = -0.5dBFS)
IN
IN
IN
IN
IN
IN
90
85
80
75
70
65
60
72
70
68
66
64
62
60
90
85
80
75
70
65
60
SFDR
SFDR
SNR
-THD
SINAD
-THD
20 25 30 35 40 45 50 55 60 65
(MHz)
20 25 30 35 40 45 50 55 60 65
(MHz)
20 25 30 35 40 45 50 55 60 65
(MHz)
f
f
f
CLK
CLK
CLK
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
(f = 65.00352MHz, f = 175MHz)
CLK IN
(f
CLK
= 65.00352MHz, f = 70MHz)
(f
CLK
= 65.00352MHz, f = 70MHz)
IN
IN
72
70
68
66
64
62
60
90
85
80
75
70
65
60
72
70
68
66
64
62
60
SNR
SNR
SFDR
SINAD
SINAD
-THD
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
V
V
V
DD
DD
DD
_______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
DD
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS,
IN
DD
L
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(f
= 65.00352MHz, f = 175MHz)
(f
= 65.00352MHz, f = 70MHz)
IN
(f
= 65.00352MHz, f = 70MHz)
CLK
IN
CLK
CLK IN
90
85
80
75
70
65
60
72
70
68
66
64
62
60
90
85
80
75
70
65
60
SNR
SFDR
-THD
SFDR
SINAD
-THD
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
V
OV (V)
DD
OV (V)
DD
DD
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
P
, I
(ANALOG) vs. ANALOG SUPPLY VOLTAGE
= 65.00352MHz, f = 175MHz)
CLK IN
DISS VDD
(f
CLK
= 65.00352MHz, f = 175MHz)
(f
CLK
= 65.00352MHz, f = 175MHz)
(f
IN
IN
72
70
68
66
64
62
60
90
85
80
75
70
65
60
900
800
700
600
500
400
300
200
100
0
SNR
P
DISS
(ANALOG)
SFDR
SINAD
-THD
I
VDD
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
OV (V)
DD
OV (V)
DD
V
DD
SNR, SINAD vs. CLOCK DUTY CYCLE
(f = 70MHz, A = -0.5dBFS)
P
, I
(DIGITAL) vs. DIGITAL SUPPLY VOLTAGE
-THD, SFDR vs. CLOCK DUTY CYCLE
(f = 70MHz, A = -0.5dBFS)
DISS OVDD
(f
= 65.00352MHz, f = 175MHz)
IN
IN
CLK
IN
IN
IN
80
72
70
68
66
64
62
60
90
85
80
75
70
65
60
C ≈ 5pF
L
SNR
SFDR
70
60
50
40
30
20
10
0
SINAD
-THD
P
(DIGITAL)
DISS
I
OVDD
SINGLE-ENDED CLOCK INPUT DRIVE
45 55 65
CLOCK DUTY CYCLE (%)
SINGLE-ENDED CLOCK INPUT DRIVE
45 55 65
CLOCK DUTY CYCLE (%)
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
25
35
75
25
35
75
OV (V)
DD
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(V
DD
= 3.3V, OV
= 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS,
IN
DD
L
DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f
= 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.)
DD
CLK
A
SNR, SINAD vs. TEMPERATURE
-THD, SFDR vs. TEMPERATURE
(f = 175MHz, A = -0.5dBFS)
IN
IN
(f = 175MHz, A = -0.5dBFS)
IN
IN
72
70
68
66
64
62
60
90
85
80
75
70
65
60
SNR
SFDR
SINAD
-THD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0.3
0.2
3
2
1
0.1
0
0
-0.1
-0.2
-0.3
-1
-2
-3
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 9,
13, 14, 17
GND
Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
2
3
6
INAP
INAN
Channel A Positive Analog Input
Channel A Negative Analog Input
COMA
Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V
- V
). Bypass
REFAP
REFAN
REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
7
8
REFAP
REFAN
REFBN
REFBP
Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (V
- V
). Bypass
REFAP
REFAN
REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (V
- V
). Bypass
REFBP
REFBN
REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
10
11
Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (V
- V
). Bypass
REFBP
REFBN
REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
12
15
16
COMB
INBN
INBP
Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
Channel B Negative Analog Input
Channel B Positive Analog Input
Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
DIFFCLK/ input drives.
18
SECLK
CLKN
CLKP
DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
DIFFCLK/SECLK = OV : Selects differential clock input drive.
DD
Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV ), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the
clock signal to CLKP and connect CLKN to GND.
DD
19
20
Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OV ), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the single-ended clock signal to CLKP and connect CLKN to GND.
DD
21
22
DIV2
DIV4
Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
23–26, 61,
62, 63
Analog Power Input. Connect V to a 3.15V to 3.60V power supply. Bypass V to GND with a parallel
DD DD
V
DD
capacitor combination of ≥10µF and 0.1µF. Connect all V pins to the same potential.
DD
Output-Driver Power Input. Connect OV to a 1.7V to V power supply. Bypass OV to GND with a
parallel capacitor combination of ≥10µF and 0.1µF.
DD
DD
DD
27, 43, 60
OV
DD
28, 29, 45,
46
N.C.
No Connection
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Pin Description (continued)
PIN
30
31
32
33
34
35
36
37
38
39
40
41
NAME
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
FUNCTION
Channel B CMOS Digital Output, Bit 0 (LSB)
Channel B CMOS Digital Output, Bit 1
Channel B CMOS Digital Output, Bit 2
Channel B CMOS Digital Output, Bit 3
Channel B CMOS Digital Output, Bit 4
Channel B CMOS Digital Output, Bit 5
Channel B CMOS Digital Output, Bit 6
Channel B CMOS Digital Output, Bit 7
Channel B CMOS Digital Output, Bit 8
Channel B CMOS Digital Output, Bit 9
Channel B CMOS Digital Output, Bit 10
Channel B CMOS Digital Output, Bit 11 (MSB)
Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog
input voltage is out of range.
DORB = 1: Digital outputs exceed full-scale range.
42
DORB
DORB = 0: Digital outputs are within full-scale range.
Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.
The MAX12527 evaluation kit (MAX12557 EV kit) utilizes DAV to latch data into any external back-end
digital logic.
44
DAV
47
48
49
50
51
52
53
54
55
56
57
58
D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
D11A
Channel A CMOS Digital Output, Bit 0 (LSB)
Channel A CMOS Digital Output, Bit 1
Channel A CMOS Digital Output, Bit 2
Channel A CMOS Digital Output, Bit 3
Channel A CMOS Digital Output, Bit 4
Channel A CMOS Digital Output, Bit 5
Channel A CMOS Digital Output, Bit 6
Channel A CMOS Digital Output, Bit 7
Channel A CMOS Digital Output, Bit 8
Channel A CMOS Digital Output, Bit 9
Channel A CMOS Digital Output, Bit 10
Channel A CMOS Digital Output, Bit 11 (MSB)
Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog
input voltage is out of range.
DORA = 1: Digital outputs exceed full-scale range.
59
DORA
DORA = 0: Digital outputs are within full-scale range.
Output Format Select Digital Input.
64
65
G/T
G/T = GND: Two’s-complement output format selected.
G/T = OV : Gray-code output format selected.
DD
Power-Down Digital Input.
PD = GND: ADCs are fully operational.
PD
PD = OV : ADCs are powered down.
DD
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Pin Description (continued)
PIN
NAME
FUNCTION
Shared Reference Digital Input.
SHREF = V : Shared reference enabled.
DD
SHREF = GND: Shared reference disabled.
When sharing the reference, externally connect REFAP and REFBP together to ensure that V
66
SHREF
REFAP
equals V . Similarly, when sharing the reference, externally connect REFAN to REFBN together to
REFBP
ensure that V
= V
.
REFAN
REFBN
Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.
For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from
67
REFOUT REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥0.1µF capacitor.
For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥0.1µF
capacitor.
Single-Ended Reference Analog Input.
For internal reference and buffered external reference operation, apply a 0.7V to 2.3V DC reference
voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor. Within its specified operating voltage,
68
—
REFIN
REFIN has a >50MΩ input impedance, and the differential reference voltage (V
- V
) is
REF_P
REF_N
generated from REFIN. For unbuffered external reference operation, connect REFIN to GND. In this
mode REF_P, REF_N, and COM_ are high-impedance inputs that accept the external reference voltages.
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified
dynamic performance.
EP
+
x2
Σ
MAX12527
−
FLASH
DAC
ADC
IN_P
STAGE 10
END OF PIPELINE
STAGE 1
STAGE 2
STAGE 9
IN_N
DIGITAL ERROR CORRECTION
D0_ THROUGH D11_
Figure 1. Pipeline Architecture—Stage Blocks
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12527 functional diagram.
Detailed Description
The MAX12527 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
CLOCK
12-BIT
PIPELINE
ADC
D0A TO D11A
DORA
DIGITAL
ERROR
CORRECTION
INAP
INAN
OUTPUT
DRIVERS
DATA
FORMAT
REFAP
COMA
REFAN
CHANNEL A
REFERENCE
SYSTEM
MAX12527
G/T
REFIN
REFOUT
SHREF
INTERNAL
REFERENCE
GENERATOR
DAV
OV
DD
REFBP
COMB
REFBN
CHANNEL B
REFERENCE
SYSTEM
12-BIT
PIPELINE
ADC
INBP
INBN
D0B TO D11B
DORB
DIGITAL
ERROR
CORRECTION
OUTPUT
DRIVERS
DATA
FORMAT
CLOCK
V
DD
DIFFCLK/SECLK
CLOCK
POWER
CONTROL
AND
CLKP
CLKN
CLOCK
DIVIDER
DUTY-CYCLE
EQUALIZER
PD
BIAS CIRCUITS
GND
DIV2
DIV4
Figure 2. Functional Diagram
______________________________________________________________________________________ 15
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Table 1. Reference Modes
V
DD
BOND WIRE
INDUCTANCE
1.5nH
V
REFERENCE MODE
REFIN
MAX12527
Internal Reference Mode.
IN_P
REFIN is driven by REFOUT either through a
direct short or a resistive divider.
35% V
REFOUT
*C
4.5pF
C
2pF
SAMPLE
PAR
to 100%
V
COM_
= V / 2
DD
V
REFOUT
V
= V / 2 + 3/8 x V
DD REFIN
= V / 2 - 3/8 x V
DD REFIN
REF_P
V
DD
BOND WIRE
INDUCTANCE
1.5nH
V
REF_N
Buffered External Reference Mode.
An external 0.7V to 2.3V reference voltage is
applied to REFIN.
IN_N
*C
SAMPLE
C
PAR
0.7V to 2.3V
4.5pF
2pF
V
COM_
= V / 2
DD
V
V
= V / 2 + 3/8 x V
DD
REF_P
REFIN
= V / 2 - 3/8 x V
REF_N DD REFIN
SAMPLING
CLOCK
Unbuffered External Reference Mode.
REF_P, REF_N, and COM_ are driven by
external reference sources. The full-scale
<0.5V
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS: R
1
=
IN
f
x C
SAMPLE
analog input range is ±(V
- V ) x 2/3.
REF_N
CLK
REF_P
Figure 3. Internal T/H Circuit
MAX12527. The power-down logic input (PD) enables
and disables the reference circuit. REFOUT has approxi-
mately 17kΩ to GND when the MAX12527 is powered
down. The reference circuit requires 10ms to power up
and settle to its final value when power is applied to the
MAX12527 or when PD transitions from high to low.
Analog Inputs and Input Track-and-Hold
(T/H) Amplifier
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
The internal bandgap reference produces a buffered
reference voltage of 2.048V ±1% at the REFOUT pin
with a ±50ppm/°C temperature coefficient. Connect an
external ≥0.1µF bypass capacitor from REFOUT to
GND for stability. REFOUT sources up to 1mA and
sinks up to 0.1mA for external circuits with a 35mV/mA
supports a V / 2 common-mode input voltage.
DD
The MAX12527 sampling clock controls the switched-
capacitor input T/H architecture (Figure 3) allowing the
analog input signals to be stored as charge on the
sampling capacitors. These switches are closed (track
mode) when the sampling clock is high and open (hold
mode) when the sampling clock is low (Figure 4). The
analog input signal source must be able to provide the
dynamic currents necessary to charge and discharge
the sampling capacitors. To avoid signal degradation,
these capacitors must be charged to one-half LSB
accuracy within one-half of a clock cycle. The analog
input of the MAX12527 supports differential or single-
ended input drive. For optimum performance with dif-
ferential inputs, balance the input impedance of IN_P
and IN_N and set the common-mode voltage to mid-
load regulation. Short-circuit protection limits I
REFOUT
to a 2.1mA source current when shorted to GND and a
0.24mA sink current when shorted to V . Similar to
DD
REFOUT, REFIN should be bypassed with a 4.7µF
capacitor to GND.
Reference Configurations
The MAX12527 full-scale analog input range is ±2/3 x
V
REF
with a V
/ 2 ±0.5V common-mode input range.
DD
V
REF
is the voltage difference between REFAP (REFBP)
and REFAN (REFBN). The MAX12527 provides three
modes of reference operation. The voltage at REFIN
supply (V
/ 2). The MAX12527 provides the optimum
DD
common-mode voltage of V
/ 2 through the COM
DD
(V ) selects the reference operation mode (Table 1).
REFIN
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 9, 10, and 11.
Connect REFOUT to REFIN either with a direct short or
through a resistive divider to enter internal reference
mode. COM_, REF_P, and REF_N are low-impedance
outputs with V
= V
/ 2, V
= V
/ 2 + 3/8 x
COM_
DD
REFP
DD
V
, and V
= V
/ 2 - 3/8 x V
. Bypass
REFIN
REF_N
DD
REFIN
Reference Output
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Bypass REFIN and REFOUT to GND with a 0.1µF capac-
duty-cycle independent. Due to this DLL, the
MAX12527 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
itor. The REFIN input impedance is very large (>50MΩ).
When driving REFIN through a resistive divider, use
resistances ≥10kΩ to avoid loading REFOUT.
Buffered external reference mode is virtually identical to
the internal reference mode except that the reference
source is derived from an external reference and not the
MAX12527’s internal bandgap reference. In buffered
external reference mode, apply a stable reference volt-
age source between 0.7V to 2.3V at REFIN. Pins COM_,
REF_P, and REF_N are low-impedance outputs with
Clock Input and Clock Control Lines
The MAX12527 accepts both differential and single-
ended clock inputs with a wide 25% to 75% input clock
duty cycle. For single-ended clock input operation,
connect DIFFCLK/SECLK and CLKN to GND. Apply an
external single-ended clock signal to CLKP. To reduce
clock jitter, the external single-ended clock must have
sharp falling edges. For differential clock input opera-
V
COM_
= V / 2, V
= V / 2 + 3/8 x V
, and
REFIN
DD
REF_P
DD
tion, connect DIFFCLK/SECLK to OV . Apply an
DD
V
REF_N
= V / 2 - 3/8 x V
. Bypass REF_P, REF_N,
REFIN
DD
external differential clock signal to CLKP and CLKN.
Consider the clock input as an analog input and route it
away from any other analog inputs and digital signal
lines. CLKP and CLKN enter high impedance when the
MAX12527 is powered down (Figure 4).
and COM_ each with a 0.1µF capacitor to GND. Bypass
REF_P to REF_N with a 10µF capacitor.
Connect REFIN to GND to enter unbuffered external ref-
erence mode. Connecting REFIN to GND deactivates
the on-chip reference buffers for COM_, REF_P, and
REF_N. With their buffers deactivated, COM_, REF_P,
and REF_N become high-impedance inputs and must
be driven with separate, external reference sources.
Low clock jitter is required for the specified SNR perfor-
mance of the MAX12527. The analog inputs are sam-
pled on the falling (rising) edge of CLKP (CLKN),
requiring this edge to have the lowest possible jitter.
Jitter limits the maximum SNR performance of any ADC
according to the following relationship:
Drive V
to V
/ 2 ±5%, and drive REF_P and
COM_
DD
REF_N so V
= (V
+ V ) / 2. The analog
REF_N_
COM_
REF_P_
input range is ±(V
- V
) x 2/3. Bypass
REF_P_
REF_N
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.
1
SNR = 20 × log
2 × π × f × t
IN
J
For all reference modes, bypass REFOUT with a 0.1µF
and REFIN with a 4.7µF capacitor to GND.
where f represents the analog input frequency and t
IN
J
The MAX12527 also features a shared reference mode,
in which the user can achieve better channel-to-chan-
nel matching. When sharing the reference (SHREF =
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For instance,
assuming that clock jitter is the only noise source, to
obtain the specified 69.8dB of SNR with an input fre-
quency of 175MHz the system must have less than
0.29ps of clock jitter. However, in reality there are other
noise sources such as thermal noise and quantization
noise that contribute to the system noise requiring the
clock jitter to be less than 0.14ps to obtain the speci-
fied 69.8dB of SNR at 175MHz.
V ), externally connect REFAP and REFBP together to
DD
ensure that V
= V . Similarly, when sharing
REFBP
REFAP
the reference, externally connect REFAN to REFBN
together to ensure that V = V
.
REFBN
REFAN
Connect SHREF to GND to disable the shared refer-
ence mode of the MAX12527. In this independent refer-
ence mode, a better channel-to-channel isolation is
achieved.
Clock-Divider Control Inputs (DIV2, DIV4)
The MAX12527 features three different modes of sam-
pling/clock operation (see Table 2). Pulling both control
lines low, the clock-divider function is disabled and the
converters sample at full clock speed. Pulling DIV4 low
and DIV2 high enables the divide-by-two feature, which
sets the sampling speed to one-half the selected clock
frequency. In divide-by-four mode, the converter sam-
pling speed is set to one-fourth the clock speed of the
MAX12527. Divide-by-four mode is achieved by applying
a high level to DIV4 and a low level to DIV2. The option to
select either one-half or one-fourth of the clock speed for
For detailed circuit suggestions and how to drive the
ADC in buffered/unbuffered external reference mode,
see the Applications Information section.
Clock Duty-Cycle Equalizer
The MAX12527 has an internal clock duty-cycle equaliz-
er, which makes the converter insensitive to the duty
cycle of the signal applied to CLKP and CLKN. The con-
verters allow clock duty-cycle variations from 25% to 75%
without negatively impacting the dynamic performance.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
______________________________________________________________________________________ 17
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Table 2. Clock-Divider Control Inputs
V
DD
DIV4
DIV2
FUNCTION
S
1H
Clock Divider Disabled
MAX12527
0
0
f
= f
CLK
SAMPLE
10kΩ
Divide-by-Two Clock Divider
= f / 2
0
1
f
SAMPLE
CLK
CLKP
Divide-by-Four Clock Divider
= f / 4
1
1
0
1
10kΩ
f
SAMPLE
CLK
DUTY-CYCLE
EQUALIZER
S
2H
Not Allowed
S
1L
10kΩ
cuitry can be latched with the rising edge of the con-
version clock (CLKP - CLKN).
CLKN
10kΩ
SWITCHES S AND S ARE OPEN
DURING POWER-DOWN MAKING
CLKP AND CLKN HIGH IMPEDANCE.
Data-Valid Output
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12527 output data changes on the
falling edge of DAV, and DAV rises once the output
data is valid. The falling edge of DAV is synchronized
to have a 5.4ns delay from the falling edge of the input
clock. Output data at D0A/B–D11A/B and DORA/B are
valid from 7ns before the rising edge of DAV to 7ns
after the rising edge of DAV.
1_
2_
S
2L
SWITCHES S ARE OPEN IN
2_
GND
SINGLE-ENDED CLOCK MODE.
Figure 4. Siimplified Clock Input Circuit
sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.
DAV enters high impedance when the MAX12527 is
powered down (PD = OV ). DAV enters its high-
impedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.
DD
System Timing Requirements
Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sam-
pled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.
DAV is capable of sinking and sourcing 600µA and has
three times the driving capabilities of D0A/B–D11A/B
and DORA/B. DAV is typically used to latch the
MAX12527 output data into an external digital back-end
circuit. Keep the capacitive load on DAV as low as possi-
ble (<15pF) to avoid large digital currents feeding back
into the analog portion of the MAX12527, thereby
degrading its dynamic performance. Buffering DAV
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
N + 4
DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)
N + 5
N + 3
N + 6
(V
(V
- V
- V
) x 2/3
) x 2/3
REF_P
REF_N
N - 3
N - 2
N +2
N + 7
N + 9
N - 1
AD
N
N + 1
N + 8
REF_N
REF_P
t
CLKN
CLKP
t
t
CL
CH
t
DAV
DAV
t
t
HOLD
SETUP
D0_–D11_
DOR
N - 3 N - 2 N - 1
8.0 CLOCK-CYCLE DATA LATENCY
N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9
t
SETUP
t
HOLD
Figure 5. System Timing Diagram
18 ______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
externally isolates it from heavy capacitive loads. Refer
to the MAX12527 EV Kit schematic for recommendations
of how to drive the DAV signal through an external buffer.
the falling edge of DAV and are valid on the rising edge
of DAV.
The MAX12527 output data format is either Gray code
or two’s complement depending on the logic input G/T.
With G/T high, the output data format is Gray code.
With G/T low, the output data format is set to two’s com-
plement. See Figure 8 for a binary-to-Gray and Gray-to-
binary code conversion example.
Data Out-of-Range Indicator
The DORA and DORB digital outputs indicate when the
analog input voltage is out of range. When DOR_ is high,
the analog input is out of range. When DOR_ is low, the
analog input is within range. The valid differential input
The following equations, Table 3, Figure 6, and Figure 7
define the relationship between the digital output and
the analog input.
range is from (V
- V
) x 2/3 to (V
-
REF_P
REF_N
REF_N
V ) x 2/3. Signals outside of this valid differential
REF_P
range cause DOR_ to assert high as shown in Table 1.
Gray Code (G/T = 1):
DOR is synchronized with DAV and transitions along
with the output data D11–D0. There is an 8 clock-cycle
latency in the DOR function as is with the output data
(Figure 5). DOR_ is high impedance when the
MAX12527 is in power-down (PD = high). DOR_ enters
a high-impedance state within 10ns after the rising edge
of PD and becomes active 10ns after PD’s falling edge.
V
IN_P
- V
= 2/3 x (V
- V
) x 2 x
IN_N
REF_P
10
REF_N
(CODE - 2048) / 4096
Two’s Complement (G/T = 0):
- V = 2/3 x (V
V
IN_P
- V
) x 2 x
IN_N
REF_P
10
REF_N
CODE / 4096
where CODE is the decimal equivalent of the digital
10
output code as shown in Table 3.
Digital Output Data and Output Format Selection
The MAX12527 provides two 12-bit, parallel, tri-state
output buses. D0A/B–D11A/B and DORA/B update on
Table 3. Output Codes vs. Input Voltage
GRAY-CODE OUTPUT CODE
TWO’S COMPLEMENT OUTPUT CODE
(G/T = 1)
(G/T = 0)
DECIMAL
HEXADECIMAL
DECIMAL
EQUIVALENT
OF
D11A–D0A
D11B–D0B
V
- V
IN_N
= 2.418V
= 0.882V
IN_P
HEXADECIMAL
EQUIVALENT
OF
D11A–D0A
D11B–D0B
EQUIVALENT
V
V
REF_P
REF_N
BINARY
D11A–D0A
D11B–D0B
EQUIVALENT
OF
D11A–D0A
D11B–D0B
BINARY
D11A–D0A
D11B–D0B
OF
D11A–D0A
D11B–D0B
DOR
1
DOR
1
(CODE
)
(CODE
)
10
10
>+1.0235V
(DATA OUT OF
RANGE)
1000 0000 0000
0x800
+4095
0111 1111 1111
0x7FF
+2047
1000 0000 0000
1000 0000 0001
0
0
0x800
0x801
+4095
+4094
0111 1111 1111
0111 1111 1110
0
0
0x7FF
0x7FE
+2047
+2046
+1.0235V
+1.0230V
1100 0000 0011
1100 0000 0001
1100 0000 0000
0100 0000 0000
0100 0000 0001
0
0
0
0
0
0xC03
0xC01
0xC00
0x400
0x401
+2050
+2049
+2048
+2047
+2046
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
0
0
0
0
0
0x002
0x001
0x000
0xFFF
0xFFE
+2
+1
0
+0.0010V
+0.0005V
+0.0000V
-0.0005V
-0.0010V
-1
-2
0000 0000 0001
0000 0000 0000
0
0
0x001
0x000
+1
0
1000 0000 0001
1000 0000 0000
0
0
0x801
0x800
-2047
-2048
-1.0235V
-1.0240V
<-1.0240V
(DATA OUT OF
RANGE)
0000 0000 0000
1
0x000
0
1000 0000 0000
1
0x800
-2048
______________________________________________________________________________________ 19
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
1 LSB = 4/3 x (V
- V
REFN
) / 4096
1 LSB = 4/3 x (V
- V
REFN
) / 4096
REFP
REFP
2/3 x (V
- V
REFN
)
2/3 x (V
- V
REFN
)
2/3 x (V
- V
REFN
)
2/3 x (V
- V
REFN
)
REFP
REFP
REFP
REFP
0x7FF
0x7FE
0x7FD
0x800
0x801
0x803
0x001
0x000
0xFFF
0xC01
0xC00
0xC00
0x803
0x802
0x801
0x800
0x002
0x003
0x001
0x000
-2047 -2045
-1
0
+1
+2045 +2047
-2047 -2045
-1
0
+1
+2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two’s-Complement Transfer Function (G/T = 0)
Figure 7. Gray-Code Transfer Function (G/T = 1)
The digital outputs D0A/B–D11A/B are high impedance
when the MAX12527 is in power-down (PD = 1) mode.
D0A/B–D11A/B enter this state 10ns after the rising
edge of PD and become active again 10ns after PD
transitions low.
In power-down mode all internal circuits are off, the
analog supply current reduces to less than 50µA, and
the digital supply current reduces to 1µA. The following
list shows the state of the analog inputs and digital out-
puts in power-down mode.
Keep the capacitive load on the MAX12527 digital out-
puts D0A/B–D11A/B as low as possible (<15pF) to
avoid large digital currents feeding back into the ana-
log portion of the MAX12527 and degrading its dynam-
ic performance. Adding external digital buffers on the
digital outputs helps isolate the MAX12527 from heavy
capacitive loads. To improve the dynamic performance
of the MAX12527, add 220Ω resistors in series with the
digital outputs close to the MAX12527. See the
MAX12557 EV kit schematic for guidelines of how to
drive the digital outputs through 220Ω series resistors
and external digital output buffers.
1) INAP/B, INAN/B analog inputs are disconnected
from the internal input amplifier (Figure 3).
2) REFOUT has approximately 17kΩ to GND.
3) REFAP/B, COMA/B, REFAN/B enter a high-imped-
ance state with respect to V
and GND, but there
DD
is an internal 4kΩ resistor between REFAP/B and
COMA/B as well as an internal 4kΩ resistor
between REFAN/B and COMA/B.
4) D0A–D11A, D0B–D11B, DORA, and DORB enter a
high-impedance state.
5) DAV enters a high-impedance state.
6) CLKP, CLKN clock inputs enter a high-impedance
state (Figure 4).
Power-Down Input
The MAX12527 has two power modes that are con-
trolled with a power-down digital input (PD). With PD
low, the MAX12527 is in its normal operating mode.
With PD high, the MAX12527 is in power-down mode.
The wake-up time from power-down mode is dominated
by the time required to charge the capacitors at REF_P,
REF_N, and COM. In internal reference mode and
buffered external reference mode the wake-up time is
typically 10ms. When operating in the unbuffered exter-
nal reference mode the wake-up time is dependent on
the external reference drivers.
The power-down mode allows the MAX12527 to effi-
ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12527 parallel output bus goes high-impedance in
power-down mode, allowing other devices on the bus
to be accessed.
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
BINARY-TO-GRAY CODE CONVERSION
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
D11
D7
D3
D0
0
BIT POSITION
BINARY
D11
D7
D3
D0
0
BIT POSITION
GRAY CODE
0
1
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
0
GRAY CODE
0
BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
+
GRAY = BINARY
BINARY
BINARY = BINARY
+
GRAY
X
X
X
X + 1
X
X+1
+
+
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
WHERE
IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
TABLE BELOW) AND X IS THE BIT POSITION:
+
GRAY = BINARY
BINARY
BINARY = BINARY
+
GRAY
10
10
10
11
10
11
GRAY = 1
+
0
BINARY = 0
+
1
10
10
GRAY = 1
10
BINARY = 1
10
D11
D7
D3
1
D0
0
BIT POSITION
BINARY
D11
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
+
0
0
1
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
+
GRAY CODE
BINARY
3) REPEAT STEP 2 UNTIL COMPLETE:
3) REPEAT STEP 2 UNTIL COMPLETE:
+
GRAY = BINARY
BINARY
10
9
9
+
BINARY = BINARY
GRAY
9
9
10
+
GRAY = 1
1
9
+
BINARY = 1
0
9
GRAY = 0
9
BINARY = 1
9
D11
D7
D3
1
D0
0
BIT POSITION
BINARY
D11
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
0
0
1
1
+
1
1
0
1
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
1
+
0
GRAY CODE
BINARY
4) THE FINAL GRAY-CODE CONVERSION IS:
4) THE FINAL BINARY CONVERSION IS:
D11
0
D7
0
D3
1
D0
0
BIT POSITION
BINARY
D11
0
D7
1
D3
1
D0
0
BIT POSITION
GRAY CODE
1
1
1
0
1
0
1
1
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
GRAY CODE
0
0
1
0
BINARY
EXCLUSIVE OR TRUTH TABLE
FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY
CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT
FORMAT OF THE MAX12527 IS TWO'S-COMPLEMENT BINARY,
HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE
MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT.
A
B
Y
=
A
+
B
0
0
1
1
0
1
0
1
0
1
1
0
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
overall distortion. The configuration of Figure 9 is good
for frequencies up to Nyquist (f / 2).
Applications Information
CLK
Using Transformer Coupling
In general, the MAX12527 provides better SFDR and
THD with fully differential input signals than single-
ended input drive, especially for input frequencies
above 125MHz. In differential input mode, even-order
harmonics are lower as both inputs are balanced, and
each of the ADC inputs only requires half the signal
swing compared to single-ended input mode.
The circuit of Figure 10 converts a single-ended input
signal to fully differential just as Figure 9. However,
Figure 10 utilizes an additional transformer to improve
the common-mode rejection allowing high-frequency
signals beyond the Nyquist frequency. A set of 75Ω
and 113Ω termination resistors provide an equivalent
50Ω termination to the signal source. The second set of
termination resistors connects to COM_ providing the
correct input common-mode voltage. Two 0Ω resistors
in series with the analog inputs allow high IF input fre-
quencies. These 0Ω resistors can be replaced with low-
value resistors to limit the input bandwidth.
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12527
for optimum performance. Connecting the center tap of
the transformer to COM provides a V
/ 2 DC level
DD
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
24.9Ω
IN_P
5.6pF
V
IN
0.1µF
0.1µF
1
5
3
6
2
4
0Ω
MAX12527
V
IN
T1
IN_P
MAX4108
5.6pF
COM_
IN_N
N.C.
24.9Ω
100Ω
MAX12527
0.1µF
COM_
0.1µF
MINICIRCUITS
TT1-6
100Ω
24.9Ω
OR
T1-1T
24.9Ω
IN_N
5.6pF
5.6pF
Figure 9. Transformer-Coupled Input Drive for Input Frequencies
Up to Nyquist
Figure 11. Single-Ended, AC-Coupled Input Drive
0Ω*
IN_P
0.1µF
5.6pF
1
5
3
1
5
3
6
2
4
6
2
4
113Ω
75Ω
V
IN
T1
T2
0.5%
1%
MAX12527
COM_
N.C.
N.C.
N.C.
N.C.
0.1µF
75Ω
1%
113Ω
0.5%
MINICIRCUITS
ADT1-1WT
MINICIRCUITS
ADT1-1WT
0Ω*
IN_N
5.6pF
*0Ω RESISTORS CAN BE REPLACED WITH
LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.
Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist
22 ______________________________________________________________________________________
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
3.3V
0.1µF
2.2µF
V
DD
REF_P
REFIN
2.048V
0.1µF
0.1µF
0.1µF
1
16.2kΩ
1µF
10µF
0.1µF
3
4
5
MAX12527
5
300µF
6V
47Ω
1
REF_N
COM_
MAX4230
MAX6029
(EUK21)
0.1µF
2
2
REFOUT
1.47kΩ
GND
0.1µF
0.1µF
NOTE: ONE FRONT-END REFERENCE CIRCUIT IS
CAPABLE OF SOURCING UP TO 15mA AND
SINKING UP TO 30mA OF OUTPUT CURRENT.
3.3V
0.1µF
2.2µF
V
DD
REF_P
REFIN
0.1µF
10µF
0.1µF
MAX12527
REF_N
COM_
0.1µF
REFOUT
GND
0.1µF
0.1µF
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
The MAX4230 buffers the 2.048V reference and pro-
vides additional 10Hz LP filtering before its output is
applied to the REFIN input of the MAX12527.
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX12527 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is >50MΩ.
Figure 12 shows the MAX6029 precision 2.048V bandgap
reference used as a common reference for multiple con-
verters. The 2.048V output of the MAX6029 passes
through a single-pole 10Hz LP filter to the MAX4230.
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX12527 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal refer-
______________________________________________________________________________________ 23
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
3.3V
3V
0.1µF
2.2µF
0.1µF
1
5
20kΩ
1%
V
DD
REF_P
MAX6029
(EUK30)
REFOUT
0.1µF
0.1µF
0.1µF
0.1µF
20kΩ
10µF
0.1µF
1%
2
MAX12527
2.413V
1
3
REF_N
47Ω
1.47kΩ
47Ω
4
4
4
MAX4230
MAX4230
MAX4230
0.47µF
10µF
330µF
6V
6V
52.3kΩ
1%
COM_
REFIN
GND
1.647V
1
3
3.3V
10µF
6V
330µF
6V
52.3kΩ
1%
1.47kΩ
47Ω
0.1µF
2.2µF
0.880V
1
3
V
DD
REF_P
20kΩ
1%
REFOUT
0.1µF
0.1µF
0.1µF
0.1µF
10µF
6V
330µF
6V
10µF
0.1µF
MAX12527
1.47kΩ
20kΩ
1%
REF_N
20kΩ
1%
COM_
REFIN
GND
Figure 13. External Unbuffered Reference Driving Multiple ADCs
ence, allowing REF_P, REF_N, and COM_ to be driven
directly by a set of external reference sources.
range for the converter to ±1.022V (±[V
x 2/3).
- V
]
REF_P
REF_N
Figure 13 uses a MAX6029 precision 3.000V bandgap
reference as a common reference for multiple convert-
ers. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz LP filter. Three
MAX4230 amplifiers buffer taps along this resistor
chain providing 2.413V, 1.647V, and 0.880V to the
MAX12527 REF_P, REF_N, and COM_ reference
inputs. The feedback around the MAX4230 op amps
provides additional 10Hz LP filtering. Reference volt-
ages 2.413V and 0.880V set the full-scale analog input
Note that one single power supply for all active circuit
components removes any concern regarding power-
supply sequencing when powering up or down.
Grounding, Bypassing, and
Board Layout
The MAX12527 requires high-speed board layout
design techniques. Refer to the MAX12557 EV kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer-
ably on the same side as the ADC, using surface-
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
mount devices for minimum inductance. Bypass V
GND with a 220µF ceramic capacitor in parallel with at
least one 10µF, one 4.7µF, and one 0.1µF ceramic
to
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope of
the ideal transfer function. The slope of the actual trans-
fer function is measured between two data points: posi-
tive full scale and negative full scale. Ideally, the positive
full-scale MAX12527 transition occurs at 1.5 LSBs below
positive full scale, and the negative full-scale transition
occurs at 0.5 LSB above negative full scale. The gain
error is the difference of the measured transition points
minus the difference of the ideal transition points.
DD
capacitor. Bypass OV
to GND with a 220µF ceramic
DD
capacitor in parallel with at least one 10µF, one 4.7µF,
and one 0.1µF ceramic capacitor. High-frequency
bypassing/decoupling capacitors should be located as
close as possible to the converter supply pins.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All grounds
and the exposed backside paddle of the MAX12527
must be connected to the same ground plane. The
MAX12527 relies on the exposed backside paddle con-
nection for a low-inductance ground connection. Isolate
the ground plane from any noisy digital system ground
planes such as a DSP or output buffer ground.
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter,
a small signal is defined as a single tone with an ampli-
tude of -35dBFS. This parameter captures the thermal
and quantization noise characteristics of the data con-
verter and can be used to help calculate the overall
noise figure of a digital receiver signal path.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential, analog input network layout
is symmetric and that all parasitic components are bal-
anced equally. Refer to the MAX12557 EV kit data
sheet for an example of symmetric input layout.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX12527, this
straight line is between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. INL deviations are measured at every step of the
transfer function and the worst-case deviation is report-
ed in the Electrical Characteristics table.
SNR
= 6.02 × N + 1.76
[max]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2 through
HD7), and the DC offset.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX12527, DNL
deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.
SNR = 20 x log (SIGNAL
/ NOISE
)
RMS
RMS
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally, the midscale
MAX12527 transition occurs at 0.5 LSB above mid-
scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
CLKN
CLKP
t
AD
2
2
2
2
2
2
V
+ V + V + V + V + V
ANALOG
INPUT
2
3
4
5
6
7
THD = 20 × log
V
1
t
AJ
SAMPLED
DATA
where V is the fundamental amplitude, and V through
1
2
V are the amplitudes of the 2nd- through 7th-order
7
harmonics (HD2 through HD7).
HOLD
TRACK
HOLD
T/H
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Figure 14. T/H Aperture Timing
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 14).
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones f
individual input tone levels are at -7dBFS. The inter-
modulation products are as follows:
and f . The
IN1
IN2
Full-Power Bandwidth
A large -0.2dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
2nd-Order Intermodulation products (IM2):
f
= f , f
- f
IN1
IN2 IN2 IN1
3rd-Order Intermodulation products (IM3):
2 x f
2 x f
- f , 2 x f
- f , 2 x f
+ f
,
,
IN1 IN2
IN2
IN2 IN1
IN1
IN2
Output Noise (n
)
OUT
+ f
IN1
The output noise (n
) parameter is similar to thermal
OUT
plus quantization noise and is an indication of the con-
verter’s overall noise performance.
4th-Order Intermodulation products (IM4):
3 x f
3 x f
2 x f
- f , 3 x f
- f , 3 x f
+ f
IN1
IN1 IN2
IN2
IN2
IN2 IN1
IN1 IN2
+ f , 2 x f
- 2 x f , 2 x f
+ 2 x f
,
IN1
IN1
IN2
IN2
No fundamental input tone is used to test for n
.
OUT
- 2 x f
IN1
IN_P, IN_N, and COM_ are connected together and
1024k data points are collected. n is computed by
5th-Order Intermodulation products (IM5):
OUT
taking the RMS value of the collected data points after
the mean is removed.
3 x f
3 x f
4 x f
- 2 x f , 3 x f
- 2 x f , 3 x f
+ 2 x f
,
IN1
IN2
IN1
IN2
IN2
IN1
IN1
- f
IN2
+ 2 x f , 4 x f
- f , 4 x f
,
IN1
IN1 IN2
IN2 IN1
+ f , 4 x f
+ f
IN2
IN2
IN1
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12527 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%. The MAX12527 requires one
clock cycle to recover from the overdrive condition.
Note that the two-tone intermodulation distortion is mea-
sured with respect to a single-carrier amplitude and not
the peak-to-average input power of both input tones.
3rd-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation
product to the Nyquist frequency relative to the total
input power of the two input tones f
individual input tone levels are at -7dBFS. The 3rd-
order intermodulation products are 2 x f - f , 2 x
and f . The
IN1
IN2
Crosstalk
Coupling onto one channel being driven by a
(-0.5dBFS) signal when the adjacent interfering channel
is driven by a full-scale signal. Measurement includes
all spurs resulting from both direct coupling and mixing
components.
IN1
IN2
f - f , 2 x f
IN2 IN1
+ f , 2 x f
+ f
.
IN1
IN2
IN2
IN1
Aperture Jitter
Figure 14 shows the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Gain Matching
Gain matching is a figure of merit that indicates how
Pin Configuration
well the gains between the two channels are matched
to each other. The same input signal is applied to both
channels and the maximum deviation in gain is report-
ed (typically in dB) as gain matching.
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND
INAP
1
2
3
4
5
6
7
8
9
51 D4A
50 D3A
49 D2A
48 D1A
47 D0A
46 N.C.
45 N.C.
44 DAV
Offset Matching
Like gain matching, offset matching is a figure of merit
that indicates how well the offsets between the two chan-
nels are matched to each other. The same input signal is
applied to both channels and the maximum deviation in
offset is reported (typically in %FSR) as offset matching.
INAN
GND
GND
COMA
REFAP
REFAN
GND
43 OV
DD
MAX12527
REFBN 10
REFBP 11
COMB 12
GND 13
GND 14
INBN 15
INBP 16
GND 17
42 DORB
41 D11B
40 D10B
39 D9B
38 D8B
37 D7B
36 D6B
35 D5B
EXPOSED PADDLE (GND)
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
THIN QFN
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Dual, 65Msps, 12-Bit, IF/Baseband ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
1
C
21-0142
2
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
2
C
21-0142
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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