EM78P221/2N
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
October 2007
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Contents
Contents
General Description.................................................................................................. 2
Pin Description.......................................................................................................... 4
4.1 EM78P222N.......................................................................................................4
4.2 EM78P221N.......................................................................................................5
Block Diagram........................................................................................................... 6
6.1 Register Configuration........................................................................................7
6.2 Registers Description .........................................................................................8
6.2.1 A (Accumulator)...................................................................................................8
6.2.2 CONT (Control Register).....................................................................................8
6.2.3 R0 (Indirect Addressing Register) ......................................................................9
6.2.4 R1 (Memory Switch Register) .............................................................................9
6.2.5 R2 (Program Counter and Stack)........................................................................9
6.2.6 R3 (Status Register)..........................................................................................10
6.2.7 R4 (Select Indirect Address) .............................................................................11
6.2.8 Bank 0-R5 (Port 5) ............................................................................................11
6.2.9 Bank 0-R6 (Port 6) ............................................................................................11
6.2.10 Bank 0-R7 (Port 7) ............................................................................................11
6.2.11 Bank 0-R8 (Port 8) ............................................................................................11
6.2.12 Bank 0-R9~RD (Reserve) .................................................................................11
6.2.14 Bank 0-RF (Interrupt Status Register)...............................................................12
6.2.15 Bank 1-R5 ~R7 (I/O Port Control Register).......................................................13
6.2.16 Bank 1-R8 (I/O Port Control Register) ..............................................................13
6.2.17 Bank 1-R9 (Reserve).........................................................................................14
6.2.19 Bank 1-RB (Pull-down Control Register)...........................................................15
6.2.20 Bank 1-RC (Open-Drain Control Register) .......................................................15
6.2.21 Bank 1-RD (Pull-high Control Register)............................................................16
6.2.22 Bank 1-RE (WDT Control Register) ..................................................................16
6.2.23 Bank 1-RF (Interrupt Mask Register) ................................................................17
Product Specification (V1.0) 10.19.2007
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Contents
6.2.27 Bank 2-R8 (Operating Mode Control Register).................................................19
6.2.28 Bank 2-R9~RF (Reserve)..................................................................................19
6.2.29 Bank 3-R5 (Timer Clock/Counter).....................................................................19
6.2.30 Bank 3-R6 (IRC Control)-only for ICE...............................................................20
6.2.31 Bank 3-R7 (Noise and LVR Control) - only for ICE...........................................21
6.2.32 Bank 3-R8~RF (Reserve)..................................................................................21
6.2.33 R10 ~ R1F.........................................................................................................21
6.2.34 Banks 0~3 - R20 ~ R3F ....................................................................................21
6.3 TCC/WDT and Prescaler..................................................................................22
6.4 I/O Ports ...........................................................................................................23
6.5 Reset and Wake-up..........................................................................................26
6.5.1 Reset and Wake-up Operation..........................................................................26
6.5.2 The T and P Status under Status Register........................................................35
6.6 Interrupt............................................................................................................36
6.7 Comparator ......................................................................................................38
6.7.1 External Reference Signal ................................................................................38
6.7.2 Comparator Outputs..........................................................................................38
6.7.3 Using a Comparator as an Operation Amplifier.................................................39
6.7.4 Comparator Interrupt.........................................................................................40
6.7.5 Wake-up from Sleep Mode................................................................................40
6.8 Oscillator ..........................................................................................................41
6.8.1 Oscillator Modes................................................................................................41
6.8.2 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................41
6.8.3 External RC Oscillator Mode.............................................................................44
6.8.4 Internal RC Oscillator Mode..............................................................................45
6.9 Power-on Considerations.................................................................................45
6.9.1 External Power-on Reset Circuit.......................................................................45
6.9.2 Residual Voltage Protection..............................................................................46
6.10 Low Voltage Reset ...........................................................................................46
6.11 Code Option .....................................................................................................47
6.11.1 Code Option Register (Word 0).........................................................................47
6.11.2 Code Option Register (Word 1).........................................................................49
6.11.3 Customer ID Register (Word 2).........................................................................50
6.12 Instruction Set ..................................................................................................50
iv •
Product Specification (V1.0) 10.19.2007
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Contents
Absolute Maximum Ratings................................................................................... 53
DC Electrical Characteristics................................................................................. 53
8.1 Comparator (OP) Characteristic....................................................................... 55
AC Electrical Characteristic................................................................................... 55
10 Timing Diagrams ..................................................................................................... 56
Quality Assurance and Reliability ........................................................................ 64
C.1 Address Trap Detect.........................................................................................64
Product Specification (V1.0) 10.19.2007
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Contents
Specification Revision History
Doc. Version
Revision Description
Date
0.9
1.0
Preliminary version
Initial released version
2007/03/20
2007/10/19
vi •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Read Me First !
Comparison between V-Package and U-Package version
This series of microcontrollers comprise of the older V-package version and the newer
U-package version. In the newer U-package version, a Code Option NRM is added
and various features such as Crystal mode Operating frequency range, IRC mode
wake-up time, WDT Time-out time, Comparator function and Pins function have been
modified to favorably meet users’ requirements. The following table is provided for
quick comparison between the two package version and for user convenience in the
choice of the most suitable product for their application.
EM78P221/222N-V
EM78P221/222N-U
DC ~ 12MHz, 4.0V
DC ~ 8MHz, 3.0V
DC ~ 4MHz, 2.1V
DC ~ 16MHz, 4.5V
DC ~ 8MHz, 3.0V
DC ~ 4MHz, 2.1V
Crystal mode Operating
frequency range at 0°C~ 70°C
IRC mode wake-up time
Sleep mode → Normal mode
Condition: 5V, 4MHz
64μs
10μs
P52, P53 Function
Output only
Input / Output
Comparator Function
Comparator only
Comparator / OPA
WDT Time-out time
(Prescaler = 1 : 1)
Condition: VDD = 5V
16.5 ms ± 30 %
15.2 ms ± 30 %
Code Option
Added a Code Option NRM
×
EM78P221/2N-V Package version
EM78P221/2N-U Package version
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
• 1
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
1 General Description
EM78P221N and EM78P222N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS
technology. Each device in the series has as an on-chip 4K×13-bit Electrical One Time Programmable Read Only Memory
(OTP-ROM). Each provides a protection bit to prevent intrusion of user’s OTP memory code. Two Code option bits are
also available to meet user’s requirements.
With its enhanced OTP-ROM features, each device provides a convenient way of developing and verifying user’s
programs. Moreover, this OTP devices offer the advantages of easy and effective program updates, using development
and programming tools. User can avail of the ELAN Writer to easily program his development code.
2 Features
„
CPU configuration
Drift Rate
Voltage
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4K×13 bits on-chip OTP-ROM
Internal RC
Frequency
Temperature
144×8 bits on-chip registers (SRAM)
8-level stacks for subroutine nesting
Process Total
(-40°C+85°C) (2.1V~5.5V)
3 programmable Level Voltage Reset
(LVR) : 4.0V, 3.0V, 2.5V
4MHz
16MHz
1MHz
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±4%
±4%
±4%
±4%
±14%
±14%
±14%
±14%
•
•
•
Less than 1.5 mA at 5V/4MHz
Typically 15 μA, at 3V/32kHz
Typically 2 μA, during sleep mode
455kHz
„
I/O port configuration
All these four main frequencies can be trimmed by
programming with four calibrated bits in the ICE220N
Simulator. OTP is auto trimmed by ELAN Writer
(DWTR).
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•
•
•
•
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4 bidirectional I/O ports: P5, P6, P7 and P8
Wake-up port : P6
26 I/O pins
8 programmable pull-down I/O pins
8 programmable pull-high I/O pins
8 programmable open-drain I/O pins
16 Programmable high sink current I/O pins
8 Programmable high drive current I/O pins
External interrupt : P77, P71
„
„
Fast set-up time requires only 800μs (VDD:5V,
Crystal: 4MHz, C1/C2: 30pF) in HXT2 mode and 10μs in
IRC mode (VDD:5V IRC:4MHz)
Peripheral configuration
•
8-bit real time clock/counter (TCC) with selective
signal sources, trigger edges, and overflow interrupt
„
„
Operating voltage range:
•
One comparator (can act as an OP).
(offset voltage is smaller than 10mV)
•
OTP version:
Operating voltage range: 2.1V~5.5V (commercial)
Operating voltage range: 2.3V~5.5V (industrial)
„
„
Five available interrupts
•
•
TCC overflow interrupt
Operating temperature range:
Input-port status changed interrupt (wake up from
sleep mode)
Operating temperature range: 0°C~70°C
(commercial)
•
•
Two External interrupts
Comparator high/low interrupt
Operating temperature range: -40°C~85°C
(industrial)
Special Features
„
Operating frequency range
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Programmable free running Watchdog Timer
Two clocks per instruction cycle
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Crystal mode:
DC~16MHz/2 clks @ 4.5V; DC~125ns inst. cycle
@ 4.5V
Power-on voltage detector available (1.8 V± 0.1V)
High EFT immunity (better performance at 4MHz or
below
DC ~ 8MHz/2 clks @ 3V; DC~250ns inst. Cycle
@ 3V
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•
•
•
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•
Power saving Sleep mode
ERC mode:
Selectable Oscillation mode
Package Type:
DC ~ 16MHz/2 clks @ 4.5V; DC~125ns inst.
cycle @ 5V
24-pin skinny DIP 300mil : EM78P221NKJ/NKS
DC ~ 8MHz/2 clks @ 3V; DC ~ 250ns inst. Cycle
@ 3V
24 pin SOP 300mil
24 pin SSOP 209mil
: EM78P221NMJ/NMS
: EM78P221NAMJ/NAMS
IRC mode:
28-pin skinny DIP 300mil : EM78P222NKJ/NKS
Oscillation mode: 16MHz, 4 MHz, 1 MHz, 455kHz
Process deviation: Typ ± 3%, Max. ± 5%
Temperature deviation: ± 5% (-40°C~85°C)
28 pin SOP 300mil
28 pin SSOP 209mil
: EM78P222NMJ/NMS
: EM78P222NAMJ/NAMS
2 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
3 Pin Assignment
(1) 28-Pin DIP/SOP/SSOP
(2) 24-Pin DIP/SOP/SSOP
1
2
P81//RESET
P55
28
27
26
25
24
23
22
21
20
19
18
17
P56/TCC
P53/OSCI
P52/OSCO
P70
3
VDD
VSS
1
P81//RESET
P55
24
23
22
21
20
19
18
17
16
4
P56/TCC
2
3
P53/OSCI
P52/OSCO
P70
5
P71/CO/INT1
P72/CIN+
P77/INT0
VDD
VSS
6
P60
P61
P62
4
7
P73/CIN-
P67
5
P71/CO/INT1
P72/CIN+
P77/INT0
8
6
P60
P61
P62
9
P63
P64
P50
P51
P66
P65
7
P73/CIN-
P67
10
11
12
8
P57
P54
9
P63
P64
P50
P51
P66
P65
10
11
12
15
14
13
P74
P75
13
14
P80
P76
16
15
P57
P54
Fig. 3-2 EM78P221NK/M/AM
Fig. 3-1 EM78P222NK/AK/M/AM
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
4 Pin Description
4.1 EM78P222N
Symbol
Pin No. Type
Function
1~2
8-bit General purpose input/output pins
Default value at power-on reset
11~12
17~18
26~27
I/O
I/O
P50~P57
8-bit General purpose input/output pins
Default value at power-on reset
6 ~ 10
19 ~21
P60~P67
P70~ P77
8-bit General purpose input/output pins
Default value at power-on reset.
5
14 ~ 16
22~25
I/O
I/O
P72 and P73 are open drain pins when used as output pins in
ICE220N simulator.
2-bit General purpose input or output pin
Default value at power-on reset
13, 28
P80, P81
P81 is define as General purpose input or output open-drain
pin.
“-“ : input pin of Vin- of the comparator
“+” : input pin of Vin+ of the comparator
Pin CO is the comparator output
CIN-
CIN+
CO
22
23
24
I
I
O
Defined by CMPCON (Bank 1-RA) <3 : 4>
Crystal type: Crystal input terminal
RC type: RC oscillator input pin
27
26
I
OSCI
Crystal type: Output terminal for crystal oscillator.
RC type: Clock output with a duration of one instruction cycle
time.
O
OSCO
External clock signal input.
If it remains at a logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
28
I
/RESET
5, 24
I
-
-
INT0~INT1
VDD
External interrupt pin
Power supply
Ground
3
4
VSS
4 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
4.2 EM78P221N
Symbol
Pin No. Type
Function
1~2
11~14
22~23
8-bit General purpose input/output pins
Default value at power-on reset.
I/O
I/O
P50~P57
8-bit General purpose input/output pins
Default value at power-on reset
6 ~ 10
15~17
P60~P67
5-bit General purpose input/output pins
Default value at power-on reset
P70~P73
P77
5
I/O
I/O
21 ~ 18
P72 and P73 are open drain pins when used as output pins of
the ICE220N simulator.
1-bit General purpose input or output open-drain pin
Default value at power-on reset
24
P81
“-“ : input pin of Vin- of the comparator
“+” : input pin of Vin+ of the comparator
Pin CO is the comparator output
CIN-
CIN+
CO
18
19
20
I
I
O
Defined by CMPCON (Bank 1-RA) <3 : 4>
Crystal type: Crystal input terminal
RC type: RC oscillator input pin
23
22
I
OSCI
Crystal type: Output terminal for crystal oscillator
RC type: Clock output with a duration of one instruction cycle
time.
O
OSCO
External clock signal input.
If it remains at logic low, the device will be reset
Wake-up from sleep mode when pin status changes
Voltage on /RESET must not exceed Vdd during normal mode
24
I
/RESET
5, 20
I
-
-
INT0~INT1
VDD
External interrupt pin
Power supply
Ground
3
4
VSS
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
5 Block Diagram
Ext.
OSC.
Int.
RC
Ext.
RC
PC
ROM
P8
P80
Oscillation
Generation
P81
8-level stack
(13 bit)
Instruction
Register
P7
WDT
TCC
Reset
P70
P71
P72
P73
P74
P75
Instruction
Decoder
TCC
Port 6
Port
change
Mux
.
P76
ALU
P77
P6
R4
P60
P61
P62
P63
P64
P65
RAM
Interrupt
Control
Register
P66
P67
R3 (Status
Reg.)
ACC
LVR
P5
P50
P51
P52
Interrupt
Circuit
Comparator
P53
P54
P55
P56
P57
Cin+ Cin- CO
Ext INT
Fig. 5-1 EM78P221/2N Functional Block Diagram
6 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6 Function Description
6.1 Register Configuration
Address
Bank 0 Registers
Bank 1 Registers
Bank 2 Registers
Bank 3 Registers
00
01
02
03
04
R0 (Indirect Addressing Register)
R1 (Memory switch register)
R2 (Program Counter)
R3 (Status Register)
R4 (Select Indirect Address)
R5 (I/O Port Control
R5 (High Drive Control R5 (Timer Clock /
05
06
07
R5 (Port 5)
R6 (Port 6)
R7 (Port 7)
Register)
Register for Port 6)
Counter)
R6 (I/O Port Control
R6 (High Sink Control
Reserve*
Register)
Register for Port 5)
R7 (I/O Port Control
R7 (High Sink Control
Reserve*
Register)
Register for Port 6
R8 (I/O Port Control
08
09
0A
R8 (Port 8)
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Register)
Reserve
RA (Comparator Control
Reserve
Register)
RB (Pull-down Control
0B
0C
0D
0E
0F
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Register)
RC (Open-drain Control
Register)
RD (Pull-high Control
Register)
RE (Wake-up Control
RE (WDT Control
Register)
Register)
RF (Interrupt Status
RF (Interrupt Mask
Register)
Register)
10
:
General Registers (16×8 bits)
1F
20
:
General Registers
General Registers
(32×8 bits)
General Registers
General Registers
(32×8 bits)
(32×8 bits)
(32×8 bits)
3F
Note: 1. All registers are 8 bits.
2. When using ICE, some registers code options are set. Refer to Section 6.2 for detailed Registers Description.
3. Registers with * can only be used in ICE220N simulator.
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2 Registers Description
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator. The Accumulator is not an
addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Bit 7 (INTE): INT signal edge
0 = interrupt occurs at the rising edge on the INT0 and INT1 pin
1 = interrupt occurs at the falling edge on the INT0 and INT1 pin
Bit 6 (INT): Interrupt enable flag
0 = masked by DISI or hardware interrupt
1 = enabled by the ENI/RETI instructions
This bit is readable only.
Bit 5 (TS):
Bit 4 (TE):
TCC signal source
0 = internal instruction cycle clock. If P56 is used as I/O pin, TS must be 0.
1 = transition on the TCC pin
TCC signal edge
0 = increment if the transition from low to high takes place on the TCC pin
1 = increment if the transition from high to low takes place on the TCC pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1
1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Note: Tcc time-out period [1/Fosc x prescaler x (256 -Tcc cnt) x 1]
Fosc: Oscillator (Crystal, ERC, IRC) frequency
8 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.3 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
6.2.4 R1 (Memory Switch Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
“0”
“0”
“0”
BS1
BS0
Bits 7~2: not used bits, fixed to 0 all the time.
Bits 1~0: used to select Banks 0 ~ 3 for R20~R3F and select Banks 0 ~ 3 for the
control register.
See the table under Section 6.2 Registers Description for the data memory
configuration.
6.2.5 R2 (Program Counter and Stack)
Reset Vector
Interrupt Vector
000H
008H
A11 A10
A9
~
A0
CALL
RET
RETL
RETI
R1(5,4)
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
On-chip Program
Memory
FFFH
Fig. 6-1 Program Counter Organization
R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under
Generates 4K×13 bits on-chip ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a reset condition occurs.
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to jump to any location within a Page (1K).
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the
stack. Thus, the subroutine entry address can be located anywhere within a page (1K).
"LJMP" instruction allows direct loading of the lower 11 program counter bits.
Therefore, "LJMP" allows PC to jump to any location within 2K (212).
"LCALL" instruction loads the lower 11 bits of the PC, and then PC+1 are pushed onto
the stack. Thus, the subroutine entry address can be located anywhere within 2K (212).
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the
top of stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and
above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the
PC, and the ninth and above bits of the PC will remain unchanged.
Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC R2, 6"
etc.) will cause the ninth bit and above bits of the PC to remain unchanged.
All instructions are single instruction cycle (fclk/2) except “LCALL” and “LJMP”
instructions. The “LCALL” and “LJMP” instructions need two instructions cycle.
6.2.6 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
T
P
Z
DC
C
Bits 7~5:
Bit 4 (T):
not used, fixed to 0 all the time.
Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during
power on and reset to 0 by WDT time-out.
Bit 3 (P):
Power-down bit. Set to 1 during power on or by a "WDTC" command
and reset to 0 by a "SLEP" command.
NOTE
Bit 4 & Bit 3 (T & P) are read only.
Bit 2 (Z):
Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
10 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.7 R4 (Select Indirect Address)
Bits 7~6: not used, fixed to 0 all the time.
Bit 5 ~ Bit 0: used to select registers (Address: 00 ~ 3F) in indirect addressing mode.
6.2.8 Bank 0-R5 (Port 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P57
P56
P55
P54
P53
P52
P51
P50
Bits 7 ~ 0 (P57 ~ P50): I/O data bits
6.2.9 Bank 0-R6 (Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P67
P66
P65
P64
P63
P62
P61
P60
Bits 7 ~ 0 (P67 ~ P60): I/O data bits
6.2.10 Bank 0-R7 (Port 7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P77
P76
P75
P74
P73
P72
P71
P70
Bits 7 ~ 0 (P77 ~ P70): I/O data bits
[With Simulator]: P73 ~ P72 are input or open-drain output pins.
[With EM78P221/2N]: P73 ~ P72 are general input or output pins.
6.2.11 Bank 0-R8 (Port 8)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
NREN
0
0
0
P81
P80
Bits 7~6, 4~2, 0: not used, fixed to 0 all the time.
Bit 5 (NREN):
Noise rejection enable
0 = disable noise rejection (Default)
1 = enable noise rejection. However in crystal oscillator mode
(LXT2), the noise rejection circuit is always disabled.
Bits 1 ~0 (P81~P80): I/O data bit.
6.2.12 Bank 0-R9~RD (Reserve)
Bits 7~0: not used, fixed to "0" all the time.
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.13 Bank 0-RE (WUCR: Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EX1IF
0
0
ICWE
0
CMPWE
0
CMPIF
Bit 7 (EX1IF): External interrupt flag. Set by INT1 pin, reset by software.
0 = no interrupt occurs
1 = with interrupt request
Bits 6~5, 3, 1: not used bits, fixed to 0 all the time
Bit 4 (ICWE): Port 6 input change to wake-up status enable bit
0 = Disable Port 6 input change to wake-up status
1 = Enable Port 6 input change wake-up status
When the Port 6 Input Status Change is used to enter interrupt vector or
to wake-up EM78P221N//2N from sleep, the ICWE bit must be set to
“Enable“.
Bit 2 (CMPWE): Comparator wake-up enable bit
0 = Disable Comparator wake-up
1 = Enable Comparator wake-up
When the Comparator output status change is used to enter interrupt
vector or to wake-up from sleep, the CMPWE bit must be set to
“Enable“.
Bit 0 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of
Comparator. Reset by software.
0 = no interrupt occurs
1 = with interrupt request
NOTE
■ Bank 0-RE <7, 0> can be cleared by instruction but cannot be set.
■ Bank1-RE <0> is an interrupt mask register.
■ Interrupt results from "logic AND" of Bank 0-RE <7, 0> and Bank 1-RE <0>, with
instruction “ENI”.
6.2.14 Bank 0-RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
EX0IF
ICIF
TCIF
Bits 7~3: not used bits, fixed to 0 all the time
Bit 2 (EX0IF): External interrupt flag. Set by INT0 pin. Reset by software.
0 = no interrupt occurs
1 = with interrupt request
12 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes.
Reset by software.
0 = no interrupt occurs
1 = with interrupt request
Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software.
0 = no interrupt occurs
1 = with interrupt request
NOTE
■ Bank 0-RF <2, 1, 0> can be cleared by instruction but cannot be set.
■ Bank1-RF <2, 1, 0> is an interrupt mask register.
■ Interrupt results from "logic AND" of Bank 0-RF <2, 1, 0> and Bank 1-RF <2, 1, 0>
with instruction “ENI”.
6.2.15 Bank 1-R5 ~R7 (I/O Port Control Register)
Bits 7~0: 0 = defines the relative I/O pin as output
1 = puts the relative I/O pin into high impedance
Bank 1-R5, R6 and R7 registers are all readable and writable.
6.2.16 Bank 1-R8 (I/O Port Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
C81
C80
Bits 7~2: not used, fixed to 0 all the time
Bits 1~0 (C81~C80): 0 = defines the relative I/O pin as output
1 = puts the relative I/O pin into high impedance
With Simulator]:
P80 and P81 are General I/O pins
[With EM78P221/2N]: P80 is General input or output, but P81 is input or open-drain
output pin.
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.17 Bank 1-R9 (Reserve)
Bits 7~0: not used, fixed to 0 all the time
6.2.18 Bank 1-RA (CMPCON: Comparator Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EIS1
EIS0
CMPOUT CMPCOS1 CMPCOS0
0
0
0
Bit 7 (EIS1): Control bit used to define the function of the P71 (/INT1) pin
0 = P71, normal I/O pin
1 = /INT1, external interrupt pin. In this case, the I/O control bit of P71
(Bit 1 of Bank 1-R7) must be set to "1"
Bit 6 (EIS0):
Control bit used to define the function of the P77 (/INT0) pin
0 = P77, normal I/O pin
1 = /INT0, external interrupt pin. In this case, the I/O control bit of P77
(Bit 7 of Bank 1-R7) must be set to "1"
NOTE
„
When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT
pin can also be read by way of reading Port 7 (Bank 0-R7). Refer to Fig. 6-4 (I/O
Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1) under
Section 6.4 (I/O Ports).
„
„
EIS0 and EIS1 are both readable and writable.
The highest priority of P71/INT1/CO2 is INT1. When EIS1=0, the working type
of P71/INT1/CO is determined by CMPCOS1 and CMPCOS0.
Bit 5 (CMPOUT): The result of the comparator output
Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits
CMPCOS1
CMPCOS0
Function Description
Comparator is not used. P72, P73 and P71 are
normal I/O pins
0
0
P72 and P73 are Comparator input pins and P71
is normal I/O pin
0
1
P72 and P73 are Comparator input pins and P71
is Comparator output pin (CO)
1
1
0
1
Used as OP and P71 is OP output pin (CO)
Bits 2~0: not used, fixed to 0 all the time
14 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.19 Bank 1-RB (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
Bank 1-RB register is both readable and writable
Bit 7 (/PD7): Control bit used to enable the pull-down function of the P67 pin
0 = Enable internal pull-down function
1 = Disable internal pull-down function
Bit 6 (/PD6): Control bit used to enable the pull-down function of the P66 pin.
Bit 5 (/PD5): Control bit used to enable the pull-down function of the P65 pin.
Bit 4 (/PD4): Control bit used to enable the pull-down function of the P64 pin.
Bit 3 (/PD3): Control bit used to enable the pull-down function of the P63 pin.
Bit 2 (/PD2): Control bit used to enable the pull-down function of the P62 pin.
Bit 1 (/PD1): Control bit used to enable the pull-down function of the P61 pin.
Bit 0 (/PD0): Control bit used to enable the pull-down function of the P60 pin.
6.2.20 Bank 1-RC (Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/OD7
/OD6
/OD3
/OD2
/OD5
/OD4
/OD1
/OD0
Bank 1-RC register is both readable and writable.
Bit 7 (OD7): Control bit used to enable the open-drain output of the P57 pin.
0 = Enable open-drain output
1 = Disable open-drain output
Bit 6 (OD6): Control bit used to enable the open-drain output of the P56 pin.
Bit 5 (OD5): Control bit used to enable the open-drain output of the P55 pin.
Bit 4 (OD4): Control bit used to enable the open-drain output of the P54 pin.
Bit 3 (OD3): Control bit used to enable the open-drain output of the P53 pin.
Bit 2 (OD2): Control bit used to enable the open-drain output of the P52 pin.
Bit 1 (OD1): Control bit used to enable the open-drain output of the P51 pin.
Bit 0 (OD0): Control bit used to enable the open-drain output of the P50 pin.
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.21 Bank 1-RD (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Bank 1-RD register is both readable and writable.
Bit 7 (/PH7): Control bit used to enable the pull-high function of the P67 pin.
0 = Enable internal pull-high
1 = Disable internal pull-high
Bit 6 (/PH6): Control bit used to enable the pull-high function of the P66 pin.
Bit 5 (/PH5): Control bit used to enable the pull-high function of the P65 pin.
Bit 4 (/PH4): Control bit used to enable the pull-high function of the P64 pin.
Bit 3 (/PH3): Control bit used to enable the pull-high function of the P53 pin.
Bit 2 (/PH2): Control bit used to enable the pull-high function of the P52 pin.
Bit 1 (/PH1): Control bit used to enable the pull-high function of the P51 pin.
Bit 0 (/PH0): Control bit used to enable the pull-high function of the P50 pin.
6.2.22 Bank 1-RE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
0
PSWE
PSW2
PSW1
PSW0
0
CMPIE
NOTE
Bank 1-RE <0> register is both readable and writable
„
„
Individual interrupt is enabled by setting its associated control bit in the
Bank 1-RF <0 > to "1."
„
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6
(Interrupt).
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable.
Bits 6, 1: not used, fixed to 0 all the time
Bit 5 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit. WDT rate is 1:1
1 = prescaler enable bit. WDT rate is set as Bit 4~Bit 2
16 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bit 4 ~ Bit 2 (PSW2 ~ PSW0): WDT prescaler bits
PSW2
PSW1
PSW0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 0 (CMPIE): CMPIF interrupt enable bit
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter an
interrupt vector or to enter next instruction, the CMPIE bit must be set
to “Enable“. But actually the output of the comparator must be read to
latch the status first. Then the output of the comparator is compared
to this latch to produce the information of output status change.
6.2.23 Bank 1-RF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
EXIE
ICIE
TCIE
NOTE
RF register is both readable and writable.
„
„
„
Individual interrupt is enabled by setting its associated control bit in the RF to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bits 7~3: not used bits, fixed to 0 all the time
Bit 2 (EXIE):
Bit 1 (ICIE):
EX0IF and EX1IF interrupts enable bit
0 = Disable EX0IF and EX1IF interrupts
1 = Enable EX0IF and EX1IF interrupts
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
If Port 6 Input Status Change Interrupt is used to enter an interrupt
vector or to enter next instruction, the ICIE bit must be set to
“Enable“.
Bit 0 (TCIE):
TCIF interrupt enable bit
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.24 Bank 2-R5 (HDCR: High Drive Control Register for Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HD67
HD66
HD65
HD64
HD63
HD62
HD61
HD60
[With Simulator]: function nonexistent
[With EM78P221/2N]: General I/O pins
Bit 7 (HD67): Output High Drive Current Select for P67
Bit 6 (HD66): Output High Drive Current Select for P66
Bit 5 (HD65): Output High Drive Current Select for P65
Bit 4 (HD64): Output High Drive Current Select for P64
Bit 3 (HD63): Output High Drive Current Select for P63
Bit 2 (HD62): Output High Drive Current Select for P62
Bit 1 (HD61): Output High Drive Current Select for P61
Bit 0 (HD60): Output High Drive Current Select for P60
HDxx
VDD = 5V, Drive Current
9mA (in 0.9VDD)
0
1
27mA (in 0.7VDD)
6.2.25 Bank 2-R6 (HSCR1: High Sink Control Register for Port 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HS57
HS56
HS55
HS54
HS53
HS52
HS51
HS50
[With Simulator]: function nonexistent
[With EM78P221/2N]: General I/O pins
Bit 7 (HS57): Output High Sink Current Select for P57
Bit 6 (HS56): Output High Sink Current Select for P56
Bit 5 (HS55): Output High Sink Current Select for P55
Bit 4 (HS54): Output High Sink Current Select for P54
Bit 3 (HS53): Output High Sink Current Select for P53
Bit 2 (HS52): Output High Sink Current Select for P52
Bit 1 (HS51): Output High Sink Current Select for P51
Bit 0 (HS50): Output High Sink Current Select for P50
HDxx
VDD = 5V, Sink Current
18mA (in 0.1VDD)
0
1
75mA (in 0.3VDD)
18 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.26 Bank 2-R7 (HSCR2: High Sink Control Register for Port 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HS67
HS66
HS65
HS64
HS63
HS62
HS61
HS60
[With Simulator]: function nonexistent
[With EM78P221/2N]: General I/O pins.
Bit 7 (HS67): Output High Sink Current Select for P67
Bit 6 (HS66): Output High Sink Current Select for P66
Bit 5 (HS65): Output High Sink Current Select for P65
Bit 4 (HS64): Output High Sink Current Select for P64
Bit 3 (HS63): Output High Sink Current Select for P63
Bit 2 (HS62): Output High Sink Current Select for P62
Bit 1 (HS61): Output High Sink Current Select for P61
Bit 0 (HS60): Output High Sink Current Select for P60
HDxx
VDD = 5V, Sink Current
18 mA (in 0.1VDD)
0
1
75 mA (in 0.3VDD)
6.2.27 Bank 2-R8 (Operating Mode Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
0
0
0
0
0
Bits 7, 4~0:
Bits 6~5:
not used, fixed to "0" all the time.
not used, fixed to "1" all the time.
NOTE
■ If user wants the MCU to work normally, user must set Bit 6 and Bit 5 of the R8
register to “1” and clear Bit 4 of R8 register to “0”.
6.2.28 Bank 2-R9~RF (Reserve)
Bits 7~0: not used, fixed to "0" all the time
6.2.29 Bank 3-R5 (Timer Clock/Counter)
„
Incremented by an external signal edge through the TCC pin, or by the instruction
cycle clock.
„
„
External signal of TCC trigger pulse width must be greater than one instruction.
The signals to increase the counter are determined by Bit 4 and Bit 5 of the CONT
register.
„
Writable and readable as any other registers.
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.30 Bank 3-R6 (IRC Control)-only for ICE
Bit
7
6
5
4
3
2
1
0
EM78P221/2N
ICE220N
‘0’
C3
‘0’
C2
‘0’
C1
‘0’
C0
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
RCM1 RCM0
Bits 7 ~ 2:
[With Simulator (C3~C0, RCM1~RCM0)]: IRC calibration bits in IRC oscillator mode.
In IRC oscillator mode of ICE220N simulator, these are the
IRC mode selection bits and IRC calibration bits.
[With EM78P221/2N]: Unimplemented, read as ‘0’.
Bits 7 ~ 4 (C3 ~ C0): Calibrator of internal RC mode
C3
C2
C1
C0
Frequency (MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
(1-36%) × F
(1-31.5%) × F
(1-27%) × F
(1-22.5%) × F
(1-18%) × F
(1-13.5%) × F
(1-9%) × F
(1-4.5%) × F
F (default)
(1+4.5%) × F
(1+9%) × F
(1+135%) × F
(1+18%) × F
(1+22.5%) × F
(1+27%) × F
(1+31.5%) × F
1. Frequency values shown are theoretical and taken at an instance of
a high frequency mode. Hence, frequency values are shown for
reference only. Definite values depend on the actual process.
2. Similar way of calculation is also applicable to low frequency mode.
Bits 3 ~ 2 (RCM1 ~ RCM0):
IRC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
0
0
1
0
1
0
4 (default)
16
1
455kHz
Bits 1 ~ 0: are not used, fixed to "0" all the time.
20 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.2.31 Bank 3-R7 (Noise and LVR Control) - only for ICE
Bit
7
6
5
4
3
‘0’
2
1
‘0’
0
‘0’
EM78P221/2N
ICE220N
‘0’
“0”
‘0’
“0”
‘0’
“0”
‘0’
“0”
‘0’
NRHL
NRE
LVR1
LVR0
Bits 7 ~ 4: not used, fixed to "0" all the time.
Bits 3 ~ 0:
[With EM78P221/2N]: Unimplemented, read as ‘0’.
[With Simulator]:
Bit 3 (NRHL):
Noise rejection high/low pulses define bit. The INT pin is a falling
edge trigger
0 = Pulses equal to 8/fc [s] are regarded as signal.
1 = Pulses equal to 32/fc [s] are regarded as signal (default)
NOTE
The noise rejection function is turned off in the LXT2 and sleep mode.
Bit 2 (NRE):
Noise rejection enable
0 = disable noise rejection
1 = enable noise rejection (default). However in Low Crystal
oscillator (LXT) mode, the noise rejection circuit is always
disabled.
Bits 1 ~ 0 (LVR1 ~ LVR0): Low Voltage Reset enable bits. If Vdd has crossover at
Vdd reset level as Vdd changes, the system will be reset.
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset) (default)
2.5V
3.0V
4.0V
2.7V
3.2V
4.2V
6.2.32 Bank 3-R8~RF (Reserve)
Bits 7~0: not used, fixed to "0" all the time.
6.2.33 R10 ~ R1F
All of these are 8-bit general-purpose registers.
6.2.34 Banks 0~3 - R20 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT. The
PST0~PST2 bits of the CONT register are used to determine the ratio of the TCC
prescaler, and the PWR0~PWR2 bits of the Bank 1-RE register are used to determine
the WDT prescaler. The prescaler counter is cleared by the instructions each time
such instructions are written into TCC. The WDT and prescaler are cleared by the
“WDTC” and “SLEP” instructions. Fig. 6-2 depicts the block diagram of TCC/WDT.
TCC (Bank 3-R5) is an 8-bit timer/counter. The TCC clock source can be internal clock
(Fosc) or external signal input (edge selectable from the TCC pin). If the TCC signal
source is from an external clock input, TCC will be incremented by 1 at every falling
edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low
level) must be greater than 1CLK. 1 CLK is always Fosc/2..Refer to Fig. 6-2.
NOTE
The internal TCC will stop running when in sleep mode.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during normal mode
through software programming. Refer to WDTE bit of Bank 1-RE register (Section
6.2.10 Bank 1-RE (WDT Control Register). With no prescaler, the WDT time-out
duration is approximately 18ms.1
1
VDD=5V, WDT Time-out period = 15.2ms ± 30%.
VDD=3V, WDT Time-out period = 18ms ± 30%.
22 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
CLK (Fosc)
0
1
Data Bus
TCC (R1)
8-bit Counter
MUX
TCC Pin
8 to 1 MUX
Prescaler
TE (CONT)
TS (CONT)
TCC overflow
Interrupt
PSR2~0
(CONT)
WDT
8-bit Counter
8 to 1 MUX
Prescaler
WDTE (Bank 1-RE)
PSW2~0
(Bank 1-RE)
WDT Time out
Fig. 6-2 TCC and WDT Block Diagram
6.4 I/O Ports
The I/O registers (Port 5, Port 6, Port 7, and Port 8) are bidirectional tri-state I/O ports.
The Pull-high, Pull-down, and Open-drain functions can be set internally by Bank 1-RB,
Bank 1-RC, and Bank 1-RD respectively. The High Drive, and High Sink functions can
be set internally by Bank 2-R5, Bank 2-R6, and Bank 2-R7 respectively. Port 6 features
an input status change interrupt (or wake-up) function. Most I/O pin can be defined as
"input" or "output" pin by the I/O control registers (P52, P53 are only used as output
pins). The I/O registers and I/O control registers are both readable and writable.
However, the initial states of these I/O ports (Port 5, Port 6, Port 7 and Port 8) are
unknown input (high impedance). Then, if the I/O pin is pulled to a level at external
circuit, the pin must induce a voltage. Hence, user must take into consideration
whether the induced voltage causes a wrong action in the system. The I/O interface
circuits for Port 5, Port 6, Port 7, and Port 8 are illustrated in Figures 6-3, 6-4, & 6-5
respectively. Port 6 with Input Change Interrupt/Wake-up is shown in Fig. 6-6.
PCRD
P
R
Q
D
CLK
PCWR
_
C
L
Q
P
R
PORT
D
IOD
Q
CLK
PDWR
_
C
L
Q
PDRD
M
U
X
0
1
Note: Pull-high and Open-drain are not shown in the figure.
Fig. 6-3 I/O Port and I/O Control Register Circuit for Port 5 , Port 7 and Port 8
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
PCRD
P
R
Q
D
CLK
PCWR
_
C
L
Q
P77, /INT0
P71, /INT1
PORT
P
R
Q
D
IOD
CLK
_
PDWR
C
L
Q
EIS1,EIS0
M
U
X
0
1
P
R
D
Q
CLK
_
C
L
Q
PDRD
INT
Note: CO2, Pull-high and Open-drain are not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1)
PCRD
P
R
Q
D
CLK
PCW R
_
C
L
Q
P60 ~ P67
PORT
P
R
IOD
Q
D
CLK
_
PDW R
C
L
Q
M
U
X
0
1
PDRD
TI n
P
R
D
Q
CLK
_
C
L
Q
Note: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 6-5 I/O Port and I/O Control Register Circuit for Port 6
24 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
ICIE
P
R
Q
D
CLK
Interrupt
_
Q
C
L
RE.1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from
SLEEP)
/SLEP
ICWE
Next Instruction
(Wake-up from
SLEEP)
Fig. 6-6 Port 6 Block Diagram with Input Change Interrupt/Wake-up
6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Change Wake-up/Interrupt
(1) Wake-up
(2) Wake-up and Interrupt
(a) Before Sleep
(a) Before Sleep
1. Disable WDT
1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6)
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
3. Execute "ENI" or "DISI"
4. Enable wake-up bit
(Set Bank 0-RE ICWE =1)
4. Enable wake-up bit
(Set Bank 0-RE ICWE =1)
5. Enable interrupt (Set BANK1-RF ICIE
=1)
5. Execute "SLEP" instruction
(b) After wake-up
6. Execute "SLEP" instruction
(b) After wake-up
→ Next instruction
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
(3) Interrupt
(a) Before Port 6 pin change
1. Read I/O Port 6 (MOV R6,R6)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set BANK1-RF ICIE =1)
(b) After Port 6 pin changed (interrupt)
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
• 25
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.5 Reset and Wake-up
6.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
reset is detected. When in LXT mode, the reset time is 500ms. Once a reset occurs,
the following functions are performed (the initial address is 000h):
„
„
„
„
„
„
„
„
„
„
„
„
The oscillator continues running, or will be started (if in sleep mode)
The Program Counter (R2) is set to all "0"
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog Timer and prescaler are cleared
When power is switched On, the Memory switch register (R1) is set to 0
The CONT register bits are set to all "0" except for Bit 6 (INT flag)
The Bank 0-RF register bits are set to all "0"
The Bank 1-RB register bits are set to all "1"
The Bank 1-RC register bits are set to all "1"
The Bank 1-RD register bits are set to all "1"
The Bank 1-RE register bits are set to all "0"
The Bank 1-RF register bits are set to all "0"
Executing the “SLEP” instruction will assert the sleep (power down) mode. While
entering sleep mode, the Oscillator and TCC are stopped. The WDT (if enabled) is
cleared but keeps on running.
The controller can be awakened by:
Case 1 External reset input on /RESET pin
Case 2 WDT time-out (if enabled)
Case 3 Port 6 input status changes (if ICWE is enabled)
Case 4 Comparator output status changes (if CMPWE is enabled)
2
VDD=5V, Setup time period = 16.5ms ± 30%.
VDD=3V, Setup time period = 18ms ± 30%.
26 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
The first two cases (1 & 2) will cause the EM78P221/2N to reset. The T and P flags of
R3 can be used to determine the source of the reset (wake-up). Cases 3 & 4 are
considered the continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) decides whether or not the controller branches to the interrupt
vector following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 0x8 after wake-up. If DISI is executed before SLEP, the
execution will restart from the instruction next to SLEP after wake-up. All sleep mode
wake up time is dependent on the oscillator mode, no matter what the oscillator type or
mode is (except when it’s in LXT2 mode). In LXT2 mode, wake-up time is 2 ~ 3 sec.
Only one of Cases 1 to 4 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P221/2N can be awakened only with Case 1 or Case 2. Refer to the
section on Interrupt (Section 6.6) for further details.
Case [b] If Port 6 Input Status Change is used to wake -up EM78P221/2N and ICWE
bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled.
Hence, the EM78P221/2N can be awakened only with Case 3. Wake-up
time is dependent on the oscillator mode. In RC mode (VDD: 5V, IRC:
4MHz), wake-up time is 10 μs (for stable oscillators). In HXT2 mode (VDD:
5V, Crystal: 4MHz, C1/C2: 30pF), wake-up time is 800μs (for stable
oscillators), and in LXT2 mode, wake-up time is 2 ~ 3 sec.
Case [c] If the Comparator output status change is used to wake-up the EM78P221/ 2N
and the CMPWE bit of the RE register is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P221/2N can be awakened only with
Case 4.
Wake-up time is dependent on the oscillator mode. In RC mode (VDD: 5V,
IRC: 4MHz), wake-up time is 10μs (for stable oscillators). In HXT2 mode
(VDD: 5V, Crystal: 4MHz, C1/C2: 30 pF), wake-up time is 800μs (for stable
oscillators), and in LXT2 mode, wake-up time is 2 ~ 3 sec.
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
If Port 6 Input Status Change Interrupt is used to wake up the EM78P221/2N (as in
Case b above), the following instructions must be executed before SLEP:
MOV
BANK
MOV
A, @000110xxb
1
RE, A
; Select WDT prescaler and disable WDT
WDTC
BANK
MOV
ENI (or DISI)
MOV
; Clear WDT and prescaler
0
R6, R6
; Read Port 6
; Enable (or disable) global interrupt
;EnablePort6inputchangewake-upbit
A, @xxx1xxxxb
MOV
MOV
RE
A, @00000x1xb
; Enable Port 6 input change interrupt
BANK
MOV
SLEP
1
RF, A
; Sleep
Similarly, if the Comparator Interrupt is used to wake up the EM78P221/2N (as in Case
[c] above), the following instructions must be executed before SLEP:
; Select Comparator and P71 functions as
; general I/O pin
MOV
A, @xxx01xxxb
BANK
1
MOV
MOV
MOV
RA, A
A, @000110xxb ; Select WDT prescaler and Disable WDT
RE, A
WDTC
ENI (or DISI)
MOV
; Clear WDT and prescaler
; Enable (or disable) global interrupt
; Enable comparator output status change
; wake-up bit
A, @00000100b
BANK
MOV
0
RE, A
BANK
MOV
1
;EnableComparator1outputstatuschange
; interrupt
A, @0x00000001b
MOV
RE, A
SLEP
; Sleep
6.5.1.1 Wake-up and Interrupt Modes Operation Summary
All categories under Reset, Wake-up and Interrupt modes are summarized below.
Wake-up Signal
Sleep Mode
Normal Mode
Interrupt (if interrupt enable)
or next instruction
External interrupt
x
Interrupt (if interrupt enable)
or next instruction
If enable ICWE bit Wake-up
+ interrupt (if interrupt enable)+ next instruction
Port 6 pin change
Interrupt (if interrupt enable)
or next instruction
Interrupt (if interrupt enable)
or next instruction
TCC overflow interrupt
Comparator interrupt
x
If enable CMPWE bit Wake-up
+ interrupt (if interrupt enable) + next instruction
Reset to Normal mode
Reset to Normal mode
Reset to Normal mode
Reset to Normal mode
WDT Time out
Low Voltage Reset
After wake up:
1. If interrupt enable → interrupt+ next instruction
2. If interrupt disable → next instruction
28 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as
follows:
Signal
Sleep Mode
Normal Mode
DISI + Bank 1-RF (EXIE) Bit 2 = 1
Next Instruction+ Set Bank 0-RF (EX0IF) = 1
or Set Bank 0-RE (EX1IF) = 1
ENI + Bank 1-RF (EXIE) Bit 2 = 1
Interrupt Vector (0x08)+ Set Bank 0-RF
(EX0IF) = 1
INT0
INT1
N/A
Bank 0-RE (ICWE) Bit 4 = 0,
Bank 1-RF (ICIE) Bit 1 = 0
Bank 1-RF (ICIE) Bit 1 = 0
Oscillator, TCC and TCC are stopped.
Port 6 input status changed wake-up is invalid.
Bank 0-RE (ICWE) Bit 4 = 0,
Bank 1-RF (ICIE) Bit 1 = 1
Port 6 input status change interrupt is invalid
N/A
Set Bank 0-RF (ICIF) = 1,
Oscillator and TCC are stopped.
Port 6 input status changed wake-up is invalid.
Bank 0-RE (ICWE) Bit 4 = 1,
Bank 1-RF (ICIE) Bit 1 = 0
N/A
N/A
N/A
Port 6 Input Status Change
Wake-up+ Next Instruction
Oscillator and TCC are stopped.
Bank 0-RE (ICWE) Bit 4 = 1,
DISI + Bank 1-RF (ICIE) Bit 1 = 1
Wake-up+ Next Instruction+ Set Bank 0-RF
(ICIF) = 1
Oscillator and TCC are stopped.
Bank 0-RE (ICWE) Bit 4 = 1,
ENI + Bank 1-RF (ICIE) Bit 1 = 1
Wake-up+ Interrupt Vector (0x08)+ Set Bank
0-RF (ICIF) = 1
DISI + Bank 1-RF (ICIE) Bit 1 = 1
Next Instruction+ Set Bank 0-RF (ICIF) = 1
ENI + Bank 1-RF (ICIE) Bit 1 = 1
Interrupt Vector (0x08)+ Set Bank 0-RF
(ICIF) = 1
Oscillator, TCC and TIMERX are stopped.
DISI + Bank 1-RF (TCIE) Bit 0 = 1
Next Instruction+ Set Bank 0-RF (TCIF) = 1
ENI + Bank 1-RF (TCIE) Bit 0=1
Interrupt Vector (0x08)+ Set Bank 0-RF
(TCIF) = 1
TCC Overflow
N/A
Bank 0-RE (CMPWE) Bit 2 = 0
Bank 1-RE (CMPIE) Bit 0 = 0
Comparator output status changed wake-up is
invalid.
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 0, }
Bank 1-RE (CMPIE) Bit 0 = 1
Set Bank 0-RE (CMPIF) = 1,
Comparator output status changed wake-up is
invalid.
Bank 1-RE (CMPIE) Bit 0 = 0
Comparator output status change interrupt is
invalid.
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 1,
Bank 1-RE (CMPIE) Bit 0 = 0
Wake-up+ Next Instruction,
Comparator
(Comparator Output Status
Change)
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 1,
DISI + Bank 1-RE (CMPIE) Bit 0 =1
Wake-up+ Next Instruction+ Set Bank 0-RE
(CMPIF) Bit 0 =1,
Oscillator and TCC are stopped.
Bank 0-RE (CMPWE) Bit 2 = 1,
ENI + Bank 1-RE (CMPIE) Bit 0 = 1
Wake-up+ Interrupt Vector (0x08)+ Set Bank 0-
RE (CMPIF) Bit 0 = 1,
DISI + Bank 1-RE (CMPIE) Bit 0 = 1
Next Instruction+ Set Bank 0-RE (CMPIF)
Bit 0 = 1
ENI + Bank 1-RE (CMPIE) Bit 0 = 1
Interrupt Vector (0x08)+ Bank 0-RE (CMPIF)
Bit 0 = 1
Oscillator and TCC are stopped.
WDT Time-out
Bank 1-RE (WDTE) Bit 7=1
Wake-up+ Reset (Address 0x00)
Wake-up+ Reset (Address 0x00)
Reset (Address 0x00)
Reset (Address 0x00)
Low Voltage Reset
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.5.1.2 Register Initial Values after Reset
The following table summarizes the registers initialized values.
Address
Name
Reset Type
Bit Name
Bit 7
INTE
0
Bit 6
INT
0
Bit 5
TS
0
Bit 4
TE
0
Bit 3
PSTE
0
Bit 2
PST2
0
Bit 1
PST1
0
Bit 0
PST0
0
Power-on
N/A
CONT
/RESET & WDT
0
0
0
0
0
0
0
0
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0x00
0x01
0x02
0x03
0x04
0x05
0x06
R0 (IAR)
R1 (MSR)
R2 (PC)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
BS1
0
BS
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
/RESET & WDT
0
0
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET & WDT
Wake-up from
Pin Change
Jump to Address 0x08 or continue to execute next instruction
Bit Name
-
-
-
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Power-on
0
0
0
0
0
0
R3 (SR)
/RESET & WDT
P
Wake-up from
Pin Change
P
P
P
t
t
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
U
P
U
P
U
P
U
P
U
P
U
P
R4 (RSR)
Bank 0-R5
Bank 0-R6
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
P57
U
P56
U
P55
U
P54
U
P53
U
P52
U
P51
U
P50
U
Power-on
/RESET & WDT
U
U
U
U
U
U
U
U
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
P67
U
P66
U
P65
U
P64
U
P63
U
P62
U
P61
U
P60
U
Power-on
/RESET & WDT
U
U
U
U
U
U
U
U
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
30 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Reset Type
Bit Name
Address
Name
Bit 7
P77
U
Bit 6
P76
U
Bit 5
P75
U
Bit 4
P74
U
Bit 3
P73
U
Bit 2
P72
U
Bit 1
P71
U
Bit 0
P70
U
Power-on
0x07
Bank 0-R7
/RESET & WDT
U
U
U
U
U
U
U
U
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
NREN
-
-
-
P81
U
P80
U
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0x8
Bank 0-R8
/RESET & WDT
U
U
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Bank 0-
R9~RD
0x9
~
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET & WDT
0XD
(Reserve)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
EX1IF
-
-
ICWE
-
CMPWE
-
CMPIF
Bank 0-
RE
(WUCR)
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xE
0xF
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
EX0IF
ICIF
0
TCIF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0-
/RESET & WDT
0
RF (ISR)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
C57
1
C56
1
C55
1
C54
1
C53
1
C52
1
C51
1
C50
1
Power-on
0x05
0x06
0x07
Bank 1-R5
Bank 1-R6
Bank 1-R7
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
C67
1
C66
1
C65
1
C64
1
C63
1
C62
1
C61
1
C60
1
Power-on
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
C77
1
C76
1
C75
1
C74
1
C73
1
C72
1
C71
1
C70
1
Power-on
/RESET & WDT
1
1
1
1
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICE 211N ICE 211N ICE 211N
220N 212N 220N 212N 220N 212N
Bit Name
-
-
-
C81
C80
Power-on
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0x8
Bank 1-R8
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1-R9
(Reserve)
0x9
0xA
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
-
P
-
P
-
CMP
OUT
CMP
COS1 COS0
CMP
Bit Name
EIS1
EIS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1-RA
(CMPCON)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0xB
0xC
0xD
0xE
Bank 1-RB
Bank 1-RC
Bank 1-RD
Bank 1-RE
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
/OD7
/OD6
/OD5
/OD4
/OD3
/OD2
/OD1
/OD0
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
WDTE
-
PSWE PSW2 PSW1 PSW0
-
CMPIE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
32 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Reset Type
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
-
-
-
-
-
EXIE
ICIE
TCIE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF
Bank 1-RF
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
HD67
HD66
HD65
HD64
HD63
HD62
HD61
HD60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2-R5
(HDCR)
0x05
0x06
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
HS57
HS56
HS55
HS54
HS53
HS52
HS51
HS50
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2-R6
(HSCR1)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
HS67
HS66
HS65
HS64
HS63
HS62
HS61
HS60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2-R7
(HSCR2)
0x07
0x8
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
P
1
1
1
1
1
1
U
P
U
P
U
P
U
P
Bank 2-R8
(OMCR)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0x9
~
0xF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2-R9
(RF)
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 3-R5
(TCC)
0x05
0x06
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
C3
1
C2
1
C1
1
C0
1
RCM1 RCM0
-
-
Bank 3-R6
(IRC)
(only for
ICE)
Power-on
1
1
1
1
U
P
U
P
/RESET & WDT
1
1
1
1
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
• 33
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Reset Type
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
NRHL
1
Bit 2
NRE
1
Bit 1
Bit 0
Bit Name
-
-
-
-
LVR1 LVR0-
Bank 3-R7 Power-on
(only for
U
P
U
P
U
P
U
P
1
1
1
1
0x07
/RESET & WDT
1
1
ICE)
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
0x10 ~
0x1F
R10 ~ R1F
/RESET & WDT
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 0~3
0x20 ~
0x3F
/RESET & WDT
R20 ~ R3F
Wake-up from
Pin Change
P
P
P
P
P
P
P
P
Legend: “×” = not used
“u” = unknown or don’t care
“P” = previous value before reset
“t” = check “Reset Type” Table in Section 6.5.2
6.5.1.3 Controller Reset Block Diagram
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-on Reset
Voltage Detector
WTE
WDT Timeout
WDT
Reset
Setup time
/RESET
Fig. 6-7 Controller Reset Block Diagram
34 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.5.2 The T and P Status under Status Register
A reset condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The values of T and P as listed in the table below, are used to check how the processor
wakes up.
Reset Type
T
1
P
1
Power-on
/RESET during Operating mode
/RESET wake-up during Sleep mode
LVR during Operating mode,
*P
1
*P
0
*P
1
*P
0
LVR wake-up during SLEEP mode
WDT during Operating mode
0
*P
0
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
* P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event
T
1
1
0
1
1
P
1
Power-on
WDTC instruction
WDT time-out
SLEP instruction
1
*P
0
Wake-up on pin changed during Sleep mode
0
* P: Previous value before reset
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.6 Interrupt
The EM78P221/2N has four interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt INT0, INT1
4. When the Comparator 1 output status changes
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV
R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes. Port 6
Input Status Change Interrupt will wake up the EM78P221/2N from sleep mode if it is
enabled prior to going into sleep mode by executing SLEP. When wake-up occurs, the
controller will continue to execute the succeeding program if the global interrupt is
disabled. If enabled, it will branch out to the interrupt vector 008H.
The external interrupt has a built-in digital noise rejection circuit (if the input pulse is
less than 8-system clock time, it is eliminated as noise. Edge selection is possible with
/INT. Refer to Word 1 Bits 8~7 (Section 6.13.2, Code Option Register (Word 1)) for
digital noise rejection definition.
During a power source unstable situation, like during external power noise interference
or EMS test condition, it will cause the power to vibrate fiercely. While Vdd is still
unsettled, the supply voltage may be below working voltage. When the system supply
voltage Vdd is below the working voltage, the IC kernel must automatically keep all
register status.
Bank 0-RE and Bank 0-RF are the interrupt status register that records the interrupt
requests in the relative flags/bits. Bank 1-RE and Bank 1-RF are interrupt mask
registers. The global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction
will be fetched from Address 008H. Once in the interrupt service routine, the source of an
interrupt can be determined by polling the flag bits in Bank 0-RE and Bank 0-RF. The
interrupt flag bit must be cleared by instructions before leaving the interrupt service
routine to avoid recursive interrupts.
When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set
regardless of the ENI execution. Note that the result of Bank 0-RE/RF will be the logic
AND of BANK 0-RE/RF and Bank 1-RE/RF (refer to Fig. 6-8). The RETI instruction
ends the interrupt routine and enables the global interrupt (the ENI execution).
When any interrupt occurs, the contents of ACC, R1 (Bits 5, 4, 1, 0), R3 (Bits 2 ~0), R4
registers are pushed to the corresponding stack (Fig 6-9). After the RETI instruction is
executed, the content of the corresponding stack are popped to ACC, R1 (Bits 5, 4, 1, 0),
R3 (Bits 2 ~0), R4 registers.
36 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
BANK0-RE/RF RD
BANK0-RE/RF
BANK1-RE/RF WR
BANK1-RE/RF
BANK1-RE/RF RD
BANK0-RE/RF WR
Fig. 6-8 Interrupt Input Circuit
Interrupt
ACC
Stack ACC
Interrupt Sources
ENI/DISI
occurs
R1 (5, 4 ,1 ,0)
Stack R1
R3 (2 ~0)
R4
Stack R3
RETI
Stack R4
Fig. 6-9 Interrupt Backup Diagram
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.7 Comparator
The EM78P221/2N has one comparator comprising of two analog inputs and one
output. The comparator can be utilized to wake up the EM78P221/2N from sleep
mode. The comparator circuit diagram is depicted in the figure below.
-
Cin
-
CO
CMP
Cin+
+
10mV
Cin
-
10mV
Cin+
Output
Fig. 6-10 Comparator Circuit Diagram & Operating Mode
6.7.1 External Reference Signal
The analog signal presented at Cin– compares to the signal at Cin+, and the digital
output (CO) of the comparator is adjusted accordingly by taking the following notes into
considerations:
NOTE
■ The reference signal must be between Vss and Vdd.
■ The reference voltage can be applied to either pin of the comparator.
■ Threshold detector applications may be of the same reference.
■ The comparator can operate from the same or different reference sources.
6.7.2 Comparator Outputs
„ The compared result is stored in the CMPOUT of Bank 1-RA.
„ Bits 3 ~ 4 <CMPCOS1, CMPCOS0> of the Bank 1-RA register. See Section 6.2.18,
Bank 1-RA (CMPCON: Comparator Control Register) for Comparator select bits
function description.
38 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
NOTE
■ The highest priority of P71/INT1/CO is INT1. When EIS1=0, the working type of
P71/INT1/CO is determined by CMPCOS1 and CMPCOS2.
■ The CO and P71of the P71/CO pins cannot be used at the same time.
■ The P71/CO pin priority is as follows:
P71/INT1/CO Pin Priority
High
/INT1
Medium
CO
Low
P71
The following figure shows the Comparator Output block diagram.
To C0
From OP I/
O
CMRD
EN
EN
Q
D
Q
D
To CMPOUT
RESET
To
CMPIF
CMRD
From
other
comparator
Fig. 6-11 Comparator Output Configuration
6.7.3 Using a Comparator as an Operation Amplifier
6.7.3.1 Bank 0-RE (WUCR: Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EX1IF
0
0
ICWE
0
CMPWE
0
CMPIF
Bit 2 (CMPWE): Comparator wake-up enable bit
0 = Disable Comparator wake-up
1 = Enable Comparator wake-up
When the Comparator output status change is used to enter an
interrupt vector or to wake-up the EM78P221/2N from sleep, the
CMPWE bit must be set to “Enable“.
Bit 0 (CMPIF):
Comparator interrupt flag. Set when a change occurs in the
Comparator output. Reset by software
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.7.3.2 Bank 1-RA (CMPCON: Comparator Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EIS1
EIS0
CMPOUT CMPCOS1 CMPCOS0
0
0
0
Bit 5 (CMPOUT): The result of the Comparator output
Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits
CMPCOS1 CMPCOS0
Function Description
0
0
0
1
Comparator is not used. P72, P73 and P71 are normal I/O pins
P72 and P73 are Comparator input pins and P71 is normal I/O pin
P72 and P73 are Comparator input pins and P71 is Comparator
output pin (CO)
1
1
0
1
Used as OP and P71 is OP output pin (CO)
6.7.3.3 Bank 1-RE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
0
PSWE
PSW2
PSW1
PSW0
0
CMPIE
Bit 0 (CMPIE): CMPIF interrupt enable bit
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter an
interrupt vector or to enter the next instruction, the CMPIE bit must
be set to “Enable“. But actually the comparator output must be read
to latch the status at first. Then the comparator output is compared
to this latch to produce the information of output status change.
6.7.4 Comparator Interrupt
„
„
„
„
CMPIE must be enabled for the “ENI” instruction to take effect
Interrupt is triggered whenever a change occurs on the comparator output pin
The actual change on the pin can be determined by reading the Bit CMPOUT
CMPIF the comparator interrupt flag, can only be cleared by software
6.7.5 Wake-up from Sleep Mode
„
If enabled, the comparator remains active and the interrupt remains functional, even
in Sleep mode.
„
„
If a mismatch occurs, the interrupt will wake up the device from Sleep mode.
The power consumption should be taken into consideration for the benefit of energy
conservation.
„
If the function is unemployed during Sleep mode, turn off the comparator before
entering sleep mode.
40 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.8 Oscillator
6.8.1 Oscillator Modes
The EM78P221/2N can be operated in six different oscillator modes, such as High
Crystal oscillator mode (HXT 1, 2), Low Crystal oscillator mode (LXT 1, 2), External RC
oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator (IRC). Select
one of such modes by programming the OSC2, OCS1, and OSC0 in the Code Option
register.
The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
Oscillator Modes
OSC2
OSC1
OSC0
ERC1 (External RC oscillator mode); P52/OSCO act as P52
ERC1 (External RC oscillator mode); P52/OSCO act as OSCO
IRC2 (Internal RC oscillator mode); P52/OSCO act as P52
IRC2 (Internal RC oscillator mode); P52/OSCO act as OSCO
LXT13 (Frequency range of XT mode is 1MHz~100kHz)
HXT13 (Frequency range of XT mode is 16MHz~6MHz)
LXT23 (Frequency range of XT mode is 32kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HXT23 (Frequency range of XT mode is 6MHz~1MHz) (Default)
1 In ERC mode, OSCI is used as oscillator pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.
2 In IRC mode, P53 is normal I/O pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.
3 In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.
The maximum operating frequency limit of the crystal/resonator at different VDDs, are
as follows:
Conditions
VDD
2.1
Max. Freq. (MHz)
4
8
Two clocks
3.0
4.5
16
6.8.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P221/2N can be driven by an external clock signal through the OSCO pin as
illustrated below.
OSCI
Ext.
Clock in
OSCO
Clock out
Fig. 6-12 External Clock Input Circuit
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Fig. 6-13 below depicts such a circuit. The
same applies to the HXT 1, 2 modes and the LXT 1, 2 modes.
C1
OSCI
Crystal
OSCO
C2
RS
Fig. 6-13 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each
resonator has its own attribute, user should refer to the resonator specifications for
appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut
crystal or low frequency mode. Fig 6-13-1 is a recommended PCB layout. When the
system works in Crystal mode (16MHz), a 10KΩ is connected between OSCI and
OSCO.
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type
Frequency Mode
Frequency
100kHz
C1 (pF)
67pF
C2 (pF)
67pF
200kHz
30pF
30pF
LXT
(100K~1MHz)
455kHz
30pF
30pF
Ceramic Resonators
1MHz
30pF
30pF
30pF
30pF
20pF
67pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
15pF
30pF
30pF
30pF
30pF
20pF
67pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
30pF
15pF
1.0 MHz
2.0 MHz
4.0 MHz
32.768kHz
100kHz
200kHz
455kHz
1MHz
HXT
(1M~6MHz)
LXT2 (32.768kHz)
LXT1
(100K~1MHz)
455kHz
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
12.0 MHz
16.0 MHz
Crystal Oscillator
HXT2
(1~6MHz)
HXT1
(6~16MHz)
42 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Fig. 6-13-1 Parallel Mode Crystal/Resonator Circuit Diagram
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.8.3 External RC Oscillator Mode
For some applications that do not require
precise timing calculation, the RC
oscillator (Fig. 6-14) could offer a
cost-effective oscillator configuration.
Nevertheless, it should be noted that the
frequency of the RC oscillator is
influenced by the supply voltage, the
values of the resistor (Rext), the capacitor
(Cext), and even by the operation
temperature. Moreover, the frequency
also changes slightly from one chip to
another due to manufacturing process
variations.
Vcc
Rext
OSCI
Cext
Fig. 6-14 External RC Oscillator Mode Circuit
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and the value of Rext should not be greater than 1MΩ. If the frequency
cannot be kept within this range, the frequency can be easily affected by noise,
humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become
unstable because the NMOS cannot discharge the capacitance current correctly.
Based on the above reasons, it must be kept in mind that all the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the PCB is layout, have certain effect on the system frequency.
The RC Oscillator frequencies:
Cext
Rext
3.3k
5.1k
10k
Average Fosc 5V, 25°C
3.5 MHz
Average Fosc 3V, 25°C
3.2 MHz
2.5 MHz
2.3 MHz
20 pF
1.30 MHz
140 kHz
1.25 MHz
140 kHz
100k
3.3k
5.1k
10k
1.27 MHz
850 kHz
1.21 MHz
820 kHz
100 pF
450 kHz
450 kHz
100k
3.3k
5.1k
10k
48 kHz
50 kHz
560 kHz
540 kHz
370 kHz
360 kHz
300 pF
196 kHz
192 kHz
100k
20 kHz
20 kHZ
Note: 1: Measured based on DIP packages.
2: The values are for design reference only.
3: The frequency drift is ± 30%
44 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.8.4 Internal RC Oscillator Mode
The EM78P221/2N offers a versatile internal RC mode with default frequency value of
4MHz. Internal RC oscillator mode has other frequencies (1MHz, 16MHz, and 455kHz)
that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below
describes the EM78P221/2N internal RC drift with the variations on voltage,
temperature, and process.
°
Internal RC Drift Rate (Ta=25 C, VDD=5.0V ± 5%, VSS=0V)
Drift Rate
Internal
RC Frequency
Temperature
Voltage
Process
Total
°
°
(-40 C~+85 C)
(2.1V~5.5V)
4MHz
16MHz
1MHz
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±4%
±4%
±4%
±4%
±14%
±14%
±14%
±14%
455kHz
Theoretical values are for reference only. Actual values may vary depending on actual process.
6.9 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes to a steady state. EM78P221/2N has a built-in Power-on Voltage Detector
(POVD) with detection level range of 1.7V to 1.9V. The circuitry eliminates the extra
external reset circuit. It will work well if Vdd rises quickly enough (50 ms or less).
However, under critical applications, extra devices are still required to assist in solving
power-on problems.
6.9.1 External Power-on Reset Circuit
The circuit shown in the
following figure
VDD
implements an external
RC to produce a reset
pulse. The pulse width
(time constant) should
be kept long enough to
allow Vdd to reach the
minimum operating
/RESET
R
C
D
Rin
voltage. This circuit is
used when the power
Fig. 6-15 External Power on Reset Circuit
supply has a slow power rise time. Since the current leakage from the /RESET pin is
about ±5μA, it is recommended that R should not be greater than 40K. This way, the
voltage at Pin /Reset is held below 0.2V. The diode (D) functions as a short circuit at
power-down. The “C” capacitor is discharged rapidly and fully. Rin, the current-limited
resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing
into Pin /RESET.
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.9.2 Residual Voltage Protection
When the battery is replaced, device power Vdd is removed but residual voltage
remains. The residual voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Fig. 6-16 and Fig. 6-17 show how to
create a protection circuit against residual voltage.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Fig. 6-16 Residual Voltage Protection Circuit 1
VDD
VDD
R1
Q1
/RESET
R2
R3
Fig. 6-17 Residual Voltage Protection Circuit 2
6.10 Low Voltage Reset
Low voltage reset (LVR) is designed for unstable power situation, such as external
power noise interference or in EMS test condition.
When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level
(VRESET) and remains at 10μs, system reset will occur and the system will remain at
reset status. The system will remain at reset status until Vdd voltage rises above Vdd
release level. Refer to Fig 6-18.
46 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
LVR characteristics are set at Code Option Word 0, Bits 10 and 9. Detailed operation
mode is as follows:
Word 0
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PR2 PR1 PR0
TYPE1 TYPE0 LVR1 LVR0 CLKS ENWDTB OSC2 OSC1 OSC0
-
Bits 10~9 (LVR1 ~ LVR0): Low Voltage Reset enable bits. If Vdd has crossover at Vdd
reset level as Vdd changes, the system will reset.
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset) (default)
2.5V
3.0V
4.0V
2.7V
3.2V
4.2V
Vdd
VRESET
Internal Reset
18ms
<LVR Voltage drop
>LVR Voltagedrop
Vdd < Vreset not longer than 10us, thesystem still keepson operati ng
System occur reset
Fig. 6-18 LVR Waveform Situation
6.11 Code Option
EM78P221/2N has two Code Option Words and one Customer ID word that are not a
part of the normal program memory.
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
6.11.1 Code Option Register (Word 0)
Word 0
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PR2 PR1 PR0
TYPE1 TYPE0 LVR1 LVR0 CLKS ENWDTB OSC2 OSC1 OSC0
-
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bits 12 ~ 11 (Type 1, Type 0): Type selection for EM78P221N or EM78P222N
Type 1, Type 0
MCU Type
00
01
10
11
Not for use
Not for use
EM78P221N (24 pins)
EM78P222N (28 pins)
Note: LVR1 and LVR0 are at Bank 3-R7, when using ICE.
Bits 10 ~ 9 (LVR1 ~ LVR0): Low Voltage Reset control bits
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset) (Default)
2.5V
3.0V
4.0V
2.7V
3.2V
4.2V
Bit 8 (CLKS):
Instruction time period option bit
0 = two oscillator time periods
1 = four oscillator time periods (Default)
Refer to Section 6.12 for Instruction Set
Bit 7 (ENWDTB): Watchdog timer enable bit
0 = Enable
1 = Disable (default)
Bits 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Mode Selection bits
Oscillator Modes
OSC2
OSC1
OSC0
ERC1 (External RC oscillator mode); P52/OSCO act as P52
ERC1 (External RC oscillator mode); P52/OSCO act as OSCO
IRC2 (Internal RC oscillator mode); P52/OSCO act as P52
IRC2 (Internal RC oscillator mode); P52/OSCO act as OSCO
LXT13 (Frequency range of XT mode is 1MHz~100kHz)
HXT13 (Frequency range of XT mode is 16MHz~6MHz)
LXT23 (Frequency range of XT mode is 32kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HXT23 (Frequency range of XT mode is 6MHz~1MHz) (Default)
1 In ERC mode, OSCI is used as oscillator pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.
2 In IRC mode, P53 is normal I/O pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.
3 In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot
and should not be defined as normal I/O pins.
Bit 3: Not used (Reserved). This bit is set to 0 all the time
Bits 2 ~ 0 (PR2 ~ PR0): Protect Bits
PR2 ~ PR0 are protect bits. Each protect status is as follows:
PR2
0
PR1
0
PR0
0
Protect
Enable
1
1
1
Disable (Default)
48 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
6.11.2 Code Option Register (Word 1)
Word 1
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
C3 C2 C1 C0 RCM1 RCM0
RESET
-
-
RCOUT NRHL NRE
-
ENB
Bit 12: Not used (reserved), fixed to “1” all the time.
Bit 11: Not used (reserved), fixed to “0” all the time.
Bit 10 (RESETENB): P81/RESET pin select bit
0 = P81 set as /RESET pin
1 = P81 is general purpose input pin or open drain for output port
(Default)
Bit 9 (RCOUT): System clock output enable bit in IRC or ERC mode
0 = OSCO pin is open drain
1 = OSCO output instruction clock (Default)
Bit 8 (NRHL): Noise rejection high/low pulse define bit. INT pin has a falling edge
trigger.
0 = Pulses equal to 8/fc are regarded as signal
1 = Pulses equal to 32/fc are regarded as signal (Default)
NOTE
NRHL and NRE are at Bank 3-R7, when using ICE.
Bit 7 (NRE): Noise rejection enable
0 = disable noise rejection
1 = enable noise rejection (default). However in Low Crystal oscillator
(LXT2) mode, the noise rejection circuit is always disabled.
NOTE
The noise rejection function is turned off in LXT2 and sleep mode.
Bit 6: Not used (Reserved). This bit is set to “1” all the time.
NOTE
C3, C2, C1, C0, RCM1 and RCM0 are at Bank 3-R6, when using ICE.
Bits 5~2 (C3~C0): Internal RC mode Calibration bits. These bits must always be set
to “1” only (auto calibration)
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Bit 1 & Bit 0 (RCM1 & RCM0): RC mode selection bits
RCM 1
RCM 0
Frequency (MHz)
1
1
0
0
1
0
1
0
4 (Default)
16
1
455kHz
6.11.3 Customer ID Register (Word 2)
Word 2
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
NRM ID8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
-
-
-
Bit 12: Not used (reserved), fixed to “0” all the time
Bit 11 (NRM):
0 = Noise reject Mode 2. For multi-time circuit use, such as key scan
and LED output.
1 = Noise reject Mode 1. For General input or output use. (Default)
Bits 10~9: Not used (reserved), fixed to “1” all the time
Bits 8 ~ 0: Customer’s ID code
6.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator time periods). Note the program counter is
changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,
these instructions only need one instruction cycles
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same
instruction can operate on I/O registers.
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
50 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Status
Operation
Binary Instruction
HEX
Mnemonic
Affected
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0 0000 0001 0100
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0000
0001
0002
0003
0004
0010
0011
0012
0013
0014
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
NOP
No Operation
None
C
DAA
Decimal Adjust A
A → CONT
CONTW
SLEP
WDTC
ENI
None
T, P
0 → WDT, Stop oscillator
0 → WDT
T, P
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
None
None
None
DISI
RET
RETI
CONTR
[Top of Stack] → PC, Enable Interrupt None
CONT → A
None
MOV R,A A → R
None
CLRA
0 → A
0 → R
Z
CLR R
Z
SUB A,R R-A → A
SUB R,A R-A → R
Z, C, DC
Z, C, DC
DECA R
DEC R
R-1 → A
Z
R-1 → R
Z
OR A,R
OR R,A
A ∨ VR → A
A ∨ VR → R
Z
Z
AND A,R A & R → A
AND R,A A & R → R
XOR A,R A ⊕ R → A
XOR R,A A ⊕ R → R
ADD A,R A + R → A
ADD R,A A + R → R
MOV A,R R → A
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Z
MOV R,R R → R
COMA R /R → A
COM R
INCA R
/R → R
R+1 → A
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Status
Affected
Binary Instruction
HEX
Mnemonic
Operation
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
05rr
05rr
05rr
06rr
06rr
06rr
06rr
07rr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
INC R
R+1 → R
Z
DJZA R
DJZ R
R-1 → A, skip if zero
None
None
C
R-1 → R, skip if zero
RRCA R
RRC R
RLCA R
RLC R
R(n) → A(n-1), R(0) → C, C → A(7)
R(n) → R(n-1), R(0) → C, C → R(7)
R(n) → A(n+1), R(7) → C, C → A(0)
R(n) → R(n+1), R(7) → C, C → R(0)
C
C
C
SWAPA R R(0-3) → A(4-7), R(4-7) → A(0-3)
SWAP R R(0-3) ↔ R(4-7)
None
None
None
None
None1
None2
None
None
JZA R
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → SP, (lower 10 bits of k ) →
PC
1 00kk kkkk kkkk
1kkk
CALL k
JMP k
None
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1 1100 kkkk kkkk
1 1101 kkkk kkkk
1 1110 1001 kkkk
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E9k
(lower 10 bits of k) → PC
None
None
Z
MOV A,k k → A
OR A,k
A ∨ k → A
AND A,k A & k → A
XOR A,k A ⊕ k → A
Z
Z
RETL k
k → A, [Top of Stack] → PC
None
Z,C,DC
None
SUB A,k k-A → A
BANK k
k → R1(1:0)
Next instruction: k kkkk kkkk kkkk;
1 1110 1010 kkkk
k kkkk kkkk kkkk
1EAk
LCALL k
None
PC+1 → [SP], k → PC
Next instruction: k kkkk kkkk kkkk;
1 1110 1011 kkkk
k kkkk kkkk kkkk
1EBk
1Fkk
LJMP k
None
k → PC
1 1111 kkkk kkkk
ADD A,k k+A → A
Z, C, DC
Note: 1 This instruction is not recommended for RF operation
2 This instruction cannot operate under RF.
52 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
7 Absolute Maximum Ratings
Items
Temperature under bias
Storage temperature
Input voltage
Rating
°
-40°C
-65°C
Vss-0.3V
Vss-0.3V
2.3V
to
to
to
to
to
to
85 C
°
150 C
Vdd+0.5V
Vdd+0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
16MHz
8 DC Electrical Characteristics
°
Ta= 25 C, VDD= 5.0V, VSS= 0V
Symbol
Parameter
Crystal: VDD to 5V
ERC: VDD to 5V
Condition
Two cycles with two clocks
R: 5.1KΩ, C: 100 pF
Min. Typ. Max. Unit
DC
−
16
MHz
FXT
F±30% 850 F±30% kHz
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold Voltage
(Schmitt Trigger)
Input Leakage Current
for input pins
Input High Voltage
(Schmitt Trigger)
Input Low Voltage
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold Voltage
(Schmitt Trigger)
Input High Threshold
Voltage (Schmitt Trigger)
Input Low Threshold Voltage
(Schmitt Trigger)
3.75
1.25
0
VIHRC
VILRC
IIL
OSCI in RC mode
OSCI in RC mode
VIN = VDD, VSS
Ports 5, 6, 7, 8
Ports 5, 6, 7, 8
/RESET
−
−
−
−
V
V
–1.0
−
1.0
−
μA
V
3.75
1.25
1.9
VIH1
VIL1
−
−
V
VIHT1
VILT1
VIHT2
VILT2
−
−
V
1.2
/RESET
−
−
V
3.75
1.25
TCC, INT
−
−
V
TCC, INT
−
−
V
3.75
1.25
VIHX1 Clock Input High Voltage
OSCI in crystal mode
OSCI in crystal mode
−
−
−
−
V
V
VILX1
IOH1
Clock Input Low Voltage
Output High Voltage
(Ports 5, 6, 7, 8)
Output High Voltage
(Ports 6)
VOH = 0.9VDD
VOH = 0.7VDD
VOL = 0.1VDD
VOL = 0.3VDD
−
−
−
−
-9
−
−
−
−
mA
mA
mA
mA
IOH2
IOL1
IOL2
-27
Output Low Voltage
(Ports 5, 6, 7, 8 )
Output Low Voltage
(Ports 5, 6)
16.8
67.2
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
Symbol
Parameter
Pull-high current
(Ports 50~53, 64~67)
Pull-low current
(Ports 60~67)
Condition
Min. Typ. Max. Unit
Pull-high active, input pin at VSS
IPH
50
20
−
−
90
60
μA
μA
Pull-low active, input pin at Vdd
IPL
All input and I/O pins at VDD,
Output pin floating, LVR disabled
WDT disabled,
All input and I/O pins at VDD,
Output pin floating, LVR Disabled
WDT enabled,
All input and I/O pins at VDD,
Output pin floating, LVR enabled
WDT disabled
ISB1
Power down current
Power down current
Power down current
−
−
−
2
−
−
−
μA
μA
μA
ISB2
ISB3
10
4.0
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT disabled, LVR disabled
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled, LVR disabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled, LVR disabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"),
Output pin floating,
Operating supply current
at two clocks (VDD=3V)
ICC1
ICC2
ICC3
ICC4
−
−
−
−
15
15
20
25
μA
μA
Operating supply current
at two clocks (VDD=3V)
Operating supply current
at two clocks (VDD=5V)
1.5
2.8
1.7
3.0
mA
mA
Operating supply current
at two clocks (VDD=5V)
WDT enabled, LVR disabled
°
Internal RC Electrical Characteristics (Ta=25 C, VDD=5 V, VSS=0V)
Drift Rate
Internal RC
Temperature
Voltage
5V
Min.
Typ.
4MHz
Max.
°
4MHz
16MHz
1MHz
25 C
3.84MHZ
15.36MHz
0.96MHz
436.8kHz
4.16MHz
16.64MHz
1.04MHz
473.2kHz
°
25 C
5V
16MHz
1MHz
°
25 C
5V
°
455kHz
25 C
5V
455kHz
°
Internal RC Electrical Characteristics (Ta=-40 ~85 C, VDD=2.1~5.5 V, VSS=0V)
Drift Rate
Internal RC
Temperature
Voltage
2.1~5.5V
2.1~5.5V
2.1~5.5V
2.1~5.5V
Min.
Typ.
4MHz
Max.
°
4MHz
16MHz
1MHz
-40~85 C
3.44MHz
13.76MHz
0.86MHz
391.3kHz
4.56MHz
18.24MHz
1.14MHz
518.7kHz
°
-40~85 C
16MHz
1MHz
°
-40~85 C
°
455kHz
-40~85 C
455kHz
54 •
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
8.1 Comparator (OP) Characteristic
°
Vdd = 5.0V, Vss=0V, Ta=25 C
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VOS
Input Offset Voltage
RL = 5.1K Note1
−
−
10
mV
Input Common-Mode Voltage
Range
Vcm
Note 2
GND
−
VDD-1
V
IOS
IBS
ICO
Input Offset Current
−
−
−
−
−
−
−
50
250
−
nA
nA
μA
Input Bias Current
25
Supply Current of Comparator
300
VREF=1.4V,VRL = 5V,
0.5
−
1.3
300
12
3.5
−
TRS
Response Time
μs
ns
RL = 5.1k, CL=15p, Note 3
TLRS Large Signal Response Time
IOL Output Sink Current
VRL = 5V, RL = 5.1k
Vi (-) =1V, Vi (+) =0V,
Vo = GND+0.5V
mA
−
−
0.2
0.4
5.5
V
V
VSAT Saturation Voltage
VS Operating Range
Vi (-) =1V, Vi (+) =0V, IOL ≤ 4mA
−
−
2.5
−
Note: 1. The output voltage is in the unit gain circuitry and over the full input common-mode range.
2. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V.
The upper end of the common-mode voltage range is VDD-1.
3. The response time specified is a 100mV input step with 5mV overdrive.
9 AC Electrical Characteristic
°
Ta=25 C, VDD=5V±5%, VSS=0V
Symbol
Parameter
Conditions
Min
Type
50
−
Max
55
Unit
%
Dclk
Input CLK Duty Cycle
−
Crystal type
RC type
−
45
100
DC
DC
−
ns
Instruction Cycle Time
(CLKS="0")
Tins
500
−
ns
Ttcc
Tdrh
Trst
TCC Input Time Period
Device Reset Hold Time
/RESET Pulse Width
Watchdog Timer Duration
Input Pin Setup Time
Input Pin Hold Time
Output Pin Delay Time
ERC Delay Time
(Tins+20) × N*
−
ns
°
Ta = 25 C
11.3
2000
11.3
−
16.2
−
21.6
−
ms
ns
°
Ta = 25 C
°
Twdt
Tset
Ta = 25 C
16.2
0
21.6
ms
ns
−
Thold
Tdelay
Tdrc
−
15
20
50
3
25
55
5
ns
Cload=20pF
45
ns
°
Ta = 25 C
1
ns
Note: *N = selected prescaler ratio
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
• 55
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
GND+0.5V
0.75VDD
0.25VDD
0.75VDD
TEST POINTS
0.25VDD
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing
measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
Instruction 1
Executed
NOP
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
56 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Type
OTP MCU
Package Type
Skinny DIP
SOP
Pin Count
24 pins
24 pins
24 pins
28 pins
28 pins
28 pins
Package Size
300mil
EM78P221NKS/NKJ
EM78P221NMS/NMJ
EM78P221NAMS/NAMJ
EM78P222NKS/NKJ
EM78P222NMS/NMJ
EM78P222NAMS/NAMJ
300mil
SSOP
209mil
Skinny DIP
SOP
300mil
300mil
SSOP
209mil
Green products do not contain hazardous substances.
The third edition of Sony SS-00259 standard.
Pb contents should be less than 100ppm
Pb contents comply with Sony specs.
Part No.
Electroplate Type
EM78P221/222/NxS/xJ
Pure Tin
Sn: 100%
232°C
11.4
Ingredient (%)
Melting Point (°C)
Electrical Resistivity (µΩ-cm)
Hardness (hv)
Elongation (%)
8~10
>50%
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
• 57
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
B Packaging Configuration
B.1 24-Lead Plastic Skinny Dual in line (SDIP) — 300 mil
13
24
Symbal Min Normal
A
Max
E
5.334
A1
A2
c
D
E1
E
0.381
3.175
3.302
3.429
0.203
0.254
0.356
31.750 31.801 31.852
6.426
7.370
6.628
7.620
6.830
7.870
12
1
e
B
8.380
8.950
9.520
B
B1
L
0.356
0.457
0.559
1.520
3.302
1.470
3.048
1.630
3.556
e
2.540(TYP)
θ
0
15
e
TITLE:
PDIP-24L SKINNY 300MIL
PACKAGE OUTLINE
DIMENSION
File:
K24
Edtion: A
Unit : mm
Scal e: Free
Material:
Sheet:1 of 1
58 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
B.2 24-Lead Plastic Small Outline (SOP) — 300 mil
Symbal
Min
Normal
Max
A
A1
b
2.350
0.102
2.650
0.300
0.406(TYP)
c
E
H
D
L
0.230
7.400
10.000
15.200
0.630
0.320
7.600
10.650
15.600
1.100
0.838
e
1.27(TYP)
θ
0
8
b
e
c
TITLE:
SOP-24L(300MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
SO24
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Product Specification (V1.0) 10.19.2007
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• 59
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
B.3 24-Lead Plastic Shrink Small Outline (SSOP) — 209 mil
24
13
Symbal
Min
Normal
Max
A
A1
A2
b
-
-
-
2.00
-
0.05
1.65
1.75
1.85
0.22
-
0.38
c
D
E
E1
e
L
L1
θ
0.09
7.90
7.400
-
0.25
8.20
8.50
8.200
7.80
5.30
5.00
5.60
-
0.65
0.75
1.25
-
-
0.55
-
0°
0.95
-
8°
1
12
D
TITLE:
SSOP-24L(209MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
SSO24
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
60 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
B.4 28- Lead Plastic Skinny Dual in line (SDIP) — 300 mil
Symbal Min Normal
Max
A
A1
A2
c
D
E1
E
5.334
0.381
3.175
0.152
3.302
3.429
0.356
0.254
35.204 35.255 35.306
7.213
7.620
8.382
0.356
1.422
3.251
7.315
7.874
7.417
8.128
9.398
0.559
1.626
3.353
e
8.890
B
B1
L
0.457
1.524
3.302
e
2.540(TYP)
θ
0
10
TITLE:
PDIP-28L SKINNY 300MIL
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
K28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Product Specification (V1.0) 10.19.2007
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• 61
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
B.5 28-Lead Plastic Small Outline (SOP) — 300 mil
Symbal
Min
Normal
Max
A
A1
b
2.370
0.102
0.350
2.500
2.630
0.300
0.500
0.406
c
0.254(TYP)
E
7.410
10.000
17.700
0.678
7.500
10.325
17.900
0.881
7.590
10.650
18.100
1.084
E1
D
L
L1
e
1.194
1.397
1.600
1.27(TYP)
θ
0
8
TITLE:
SOP-28L(300MIL)
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
SO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
62 •
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
B.6 28- Lead Plastic Shrink Small Outline (SSOP) — 209 mil
Symbal
Min
Normal
Max
A
A1
A2
b
c
E
E1
D
L
2.130
0.250
1.880
0.380
0.200
8.200
5.600
0.050
1.620
1.750
0.220
0.090
7.400
5.000
9.900
0.630
7.800
5.300
10.200 10.500
0.900
1.030
e
0.650(TYP)
θ
0
4
8
b
e
c
TITLE:
SSOP-28L(209MIL) OUTLINE
PACKAGE PACKA OUTLINE
DIMENSION
File :
Edtion: A
SSO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Product Specification (V1.0) 10.19.2007
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EM78P221/2N
8-Bit Microcontroller with OTP ROM
C Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
°
Solder temperature=245±5 C, for 5 seconds up to the
Solderability
−
stopper using a rosin-type flux
°
°
Step 1: TCT, 65 C (15 mins)~150 C (15 mins), 10 cycles
°
Step 2: Bake at 125 C, TD (endurance)=24 hrs
°
Step 3: Soak at 30 C/60% , TD (endurance)=192 hrs
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
Step 4: IR flow 3 cycles
(Pkg thickness: 2.5mm or
Pkg volume: 350mm ----225±5 C)
3
°
(Pkg thickness: 2.5mm or
3
°
Pkg volume: 350mm ----240±5 C)
°
°
Temperature cycle test
Pressure cooker test
-65 C (15 mins) ~ 150 C (15 mins), 200 cycles
−
−
°
TA =121 C, RH=100%, pressure=2 atm,
TD (endurance)= 96 hrs
High temperature /
High humidity test
°
TA=85 C, RH=85% , TD (endurance)=168, 500 hrs
−
−
High-temperature
storage life
°
TA=150 C, TD (endurance)=500, 1000 hrs
°
High-temperature
operating life
TA=125 C, VCC=Max. Operating Voltage,
−
−
TD (endurance) =168, 500, 1000 hrs
°
Latch-up
TA=25 C, VCC=Max. operating voltage, 150mA/20V
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
°
ESD (HBM)
TA=25 C, ± 3KV
°
ESD (MM)
TA=25 C, ± 300V
VDD-VSS(+),VDD_VS
S (-) mode
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise caused address error is detected, the MCU will repeat execution of the program
until the noise is eliminated. The MCU will then continue to execute the next program.
64 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
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