ꢀꢁꢂꢀ
FUJITSU MICROELECTRONICS EUROPE
Development tools for 16LX Family
CPU Board
User Guide
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What is in This Guide...............................................................................................................................................................................................................2
What is not included in this guide.....................................................................................................................................................................................2
Where to find news, options, OTHER beans, OTHER CPU boards, latest FAQ and support ..............................................................................3
CPU Board Features and Technical Specification ..............................................................................................................................................................4
Features .................................................................................................................................................................................................................................4
Flash It! .....................................................................................................................................................................................................................................5
Overview of the DevKit16 FLASH Programming Tool ...............................................................................................................................................5
CPU Board Description............................................................................................................................................................................................................6
CPU board overview ...........................................................................................................................................................................................................6
Connectors ............................................................................................................................................................................................................................6
Jumpers, buttons and switches.........................................................................................................................................................................................9
Default HW settings...........................................................................................................................................................................................................12
CPU Board Power Supply Requirements.............................................................................................................................................................................13
Warranty and Disclaimer.......................................................................................................................................................................................................14
Revision and Error List ..........................................................................................................................................................................................................15
Appendix ..................................................................................................................................................................................................................................16
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ꢀ
What you’ll find inside this guide and few words about its
organization
PU Board in its interface to the Devkit16 Mainboard is designed in such a way
that it is possible to use different CPU boards (with various members of the
16LX family) with the same Mainboard. This guide describes how to use the
CPU board as a standalone board.
C
provides
necessary technical and operational information
explains how to store final application in DevKit16 CPU or
external FLASH.
provides explanation how to control the CPU
board configuration and detailed description of CPU board including all DIP
switches, jumpers and connectors.
includes schematics of the CPU board and other technical references
This guide is not detailed manual for the CPU, parts and software tools. Please find more
in the following resources:
MCU, Softune Workbench and tools –
FUJITSU Micros CD ROM (Ver 3.0 or higher)
Processor Expert(TM) and tools – DEVKIT16 Software CD ROM
Parts and other HW components – datasheets of their producers
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giveaways. You can also register in order to obtain news by mail.
For MCUs and Fujitsu technologies please visit FUJITSU WEB site
When you need additional CPU personality board please call your nearest FUJITSU
subsidiary or authorised FUJITSU distributor. You should specify:
version of CPU you need
CPU soldered or in socket. Socket version is provided for users who want to
use the FUJITSU emulator
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ꢂ
This chapter introduces features of CPU board and provides
necessary technical and operational information for DevKit16.
he CPU board was designed as a replaceable part of the Devkit16. So, it
contains only few features and the rest is provided by the Devkit16
Mainboard.
T
Position for a PQFP 100 processor or NQPACK socket
connectors for all CPU pins
a Bus Interface connector for main board connection
a Device Bus connector
a power supply supervisor IC with reset generation
RST, HST buttons
DIP switch for setting the CPU mode
High speed (in socket) and low speed quartzes
Serial port connector
power supply regulators 5V or 3.3V, depending on CPU used
power supply connector for external power source and DC power supply circuitry
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ꢄ
If the CPU mounted on the CPU board has a FLASH memory, the
DevKit16 FLASH Programming Tool can be used to program it.
DevKit16
FLASH
Programming
Tool
provides
standard
operations
(check/program/verify) for CPU Internal FLASH memory, Mainboard FLASH or both.
With the standalone CPU board, it is possible to program only the internal FLASH. The
check-box "External bus free ?" should be set to "no" (this tells the SW not to use the
FPGA UART). The Flashtool will guide you to set the proper mode on the CPU board
DIP switches. The communication will run on 9600Bd only, and only CPU FLASH can
be programmed.
For further information, please see the DevKit16 FLASH Programming Tool online
Help.
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ꢅ
This chapter provides detailed description of CPU board including
all DIP switches, jumpers and connectors.
CPU board can work standalone or in connection with the Mainboard. If the Mainboard is
in use, please switch all switches on CPU board configuration DIP to OFF.
CPU board is designed as low cost board, which provides compatibility on Interface Bus
and the Device Bus level for different CPUs. Additionally, headers pin compatible to CPU
pins are provided.
This part contains description of CPU board for MB90F543CPU.
Connectors
Jumpers, buttons and switches
Board layout
This connector serves for connecting the CPU board to the Mainboard.
This connector provides connection to CPU peripherals.
Note: For the pinout of these connectors, please see the attachments section of this
manual.
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AD00 1
MD0 3
2 AD01
4 MD2
6 SIN
SERRES 5
SOT 7
8 SCK
10 GND
VCC 9
The serial interface connector should be used only when the CPU board is not connected
to the mainboard, because mainboard connects its own serial (RS232) interface to the
UART0 and UART1 CPU signals. To be able to use the K7 connector, please refer to the
description of J7, J8, J9 jumpers later in this section.
Warning: if you want to use the K7 connector when Mainboard is
connected to the CPU board, you have to disconnect the serial interface
selected by J7-J9 from the RS232 drivers on the Mainboard. To achieve this,
remove jumpers on positions 3-4, 5-6 from both the J21 and J22 headers on
the Mainboard. Also, when the Async. Serial programming mode is set on
the Mainboard System control DIP switches, the FPGA UART RS232 driver
is connected to UART0 or UART1 (depending on the setting of the
UART0/1 switch) after reset. If you want to use K7 also in that case, remove
the 3-4, 5-6 jumpers on the J23 as well.
GND
+9V
Before applying the power to the Devkit16, check the polarity of your power chord plug –
the GND must be in the center, while the +9V on the shell of the connector. Even thought
the DevKit16 power lines are protected by a diode on the power input, do not ever apply
power with the opposite polarity. Also, make sure that the power supply complies to the
specifications in chapter CPU board Power Supply Requirements.
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INT6 31
ADTG 33
AVR+ 35
AVss 37
AN1 39
32 INT7
34 AVCC
36 AVR-
38 AN0
40 AN2
42 Vss
A16
A18
2 A17
4 A19
A20
6 A21
A22
8 A23
ALE
10 #RD
12 #WRL
14 HRQ
16 RDY
18 SOT0
20 SIN0
22 SCK1
24 SOT1
26 SCK2
AN3 41
GND
AN4 43
44 AN5
46 AN7
48 TOT0
50 MD1
#WRH
#HAK 15
CLK 17
SCK0 19
SIN1 21
FVCC 23
SOT2 25
AN6 45
TIN0 47
MD0 49
MD2 51
IN0 53
52 #HST
54 IN1
SOT2 25
INT4 25
26 SIN2
26 INT5
IN2 54
56 IN3
IN4 57
58 IN5
OUT2/IN6 59
PPG0 61
PPG2 63
OUT0 65
TIN1 67
INT0 69
INT2 71
TX0 73
60 OUT3/IN7
62 PPG1
64 PPG3
66 OUT1
68 TOT1
70 INT1
72 INT3
74 RX0
VSS 81
X1 83
82 X0
84 VCC
AD00 85
AD02 87
AD04 89
AD06 91
AD08 93
AD10 95
AD12 97
AD14 99
86 AD01
88 AD03
90 AD05
92 AD07
94 AD09
96 AD11
98 AD13
100 AD15
TX1 75
76 RX1
RST 77
X1A 79
78 PA0
80 X0A
1: VCC
2: VCC
3: VCC
4: VCC
1: GND
2: GND
3: GND
4: GND
5: GND
6: GND
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When SHORT, the +5V from the voltage regulator is connected to board VCC. This
jumper must be removed when using an external +5V power supply to avoid current
flowing back to the regulator.
When SHORT, the VCC is connected to CPU’s VCC pins. Before removing this jumper,
remove the J3 (AVCC to CPU) jumper as well to completely disconnect the power from
the CPU.
When SHORT, board’s VCC is connected to CPU’s AVcc pin.
When SHORT, board’s GND is connected to CPU’s AGND pin.
When SHORT, board’s VCC is connected to CPU’s AVR+ pin. When removed, the
voltage at the AVR+ pin is set to 4V
When SHORT, board’s GND is connected to CPU’s AVR- pin. When removed, the
voltage at the AVR- pin is set to 0.9V.
These jumpers select, which of the two UART0, UART1 interfaces signals will be
connected to the pins of the K7 connector. If all of these jumpers are in
1-2 position - the UART1 interface signals will be connected to the K7
2-3 position – the UART0 interface signals will be connected to the K7 connector.
Default setting: the UART1 signals are connected to the K7.
Note: The J7 jumper selects between SCK1 and SCK0, J8 between SIN1 and SIN0
and J9 between SOT1 and SOT0
Warning: if you want to use the K7 connector when Mainboard is
connected to the CPU board, you have to disconnect the selected serial
interface (UART0 or UART1) from the RS232 drivers on the Mainboard. To
achieve this, remove jumpers on positions 3-4, 5-6 from both the J21 and J22
headers on the Mainboard. Also, when the Mainboard is connected to the
CPU board and the Async. Serial programming mode is set on the Mainboard
System control DIP switches, the FPGA UART is connected to UART0 or
UART1 (depending on the setting of the UART0/1 switch) after reset. If you
want to use K7 also in that case, remove the 3-4, 5-6 jumpers on the J23.
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These jumpers allow to use Mainboard’s I2C connector/EEPROM memory even in the
case, when CPU itself doesn’t provide the I2C interface. When both of these jumpers are
SHORT, the CPU’s HRQ signal is connected to the Mainboard’s SDA signal (via J19) and
#HAK signal is connected to SCL signal. An user can then program the #HAK, HRQ
signals to behave as I2C interface.
When short, these jumpers connect the 32.768 kHz crystal to the Bus Interface connector
X1A, X0A pins.
When short, these jumpers connect the 4MHz crystal to the Bus Interface connector X0,
X1 pins.
This button can be used for reseting the CPU.
While this button is pressed, the CPU stays in the standby mode (all oscillators are
stopped, all I/O pins are set to high impedance state, special purpose registers such as the
accumulator are reset to their default values, but content of internal RAM is preserved)
1: MD0
8
7
6
5
4
3
2
1
2: MD1
3: MD2
4: S-R
5: S-H
6: H-R
ON
7: AD00 (P00)
8: AD01 (P01)
These switches should be used only when using the CPU board without Mainboard, or
with the FPGA disabled (see the description of J29 in the Mainboard section).
MD2
MD1
MD0 AD00/ AD01
Mode name
Reset vector area
External data
P00
OFF
OFF
OFF
OFF
X
X
ON
X
/P01
OFF
OFF
OFF
OFF
X
X
ON
X
bus witdth
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
External vector mode 0
External vector mode 1
External vector mode 2
Internal vector mode
Reserved
Reserved
Async serial programming
Reserved
External
External
External
Internal
8
16
16
ON
(Mode data)
OFF
OFF
OFF
OFF
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4: S-R – if ON, this switch connects the RES pin of the K7 connector to the CPU’s #RST
signal.
5: S-H – if ON, this switch connects the RES pin of the K7 connector to the CPU’s #HST
signal.
6. H-R – if ON, the #RST and #HST signals are connected together.
7: AD00, 8:AD01 – if ON, the AD00/P00 and AD01/P01 signals are pulled to log. ‘0’
level. This setting must be done for bringing processor to the Serial programming mode.
8
7
6
5
4
3
2
1
ON
Figure 1: CPU board layout and default jumper settings
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These jumpers come in the SHORT position as a default factory setting:
J2: The CPU is connected to the +5V power supply through this jumper
J3: The CPU AVCC supply pin is connected +5V power supply through this jumper
J4: The CPU AGND supply pin is connected to the GND through this jumper
J5: The CPU AVR+ pin is connected to the +5V voltage through this jumper
J6: The CPU AVR- pin is connected to the 0V voltage through this jumper
J7-9: The CPU UART1 signals are connected to the K7 connector
J13: The board is powered from the +5V from the power supply voltage regulator
J19: The CPU HRQ pin is connected to the SDA Mainboard signal
J20: The CPU #HAK pin is connected to the SCL Mainboard signal
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ꢆ
CPU board does not come with power supply, please check, if your
power supply match the requirements before you plug it to the CPU
board!
Power supply voltage: 9V
Power supply current (CPU board MB90F543 with Main board connected):
Single chip CPU mode, no external peripheral connected: 290mA max.
External bus mode, no peripheral connected: 350mA
External bus with:
keyboard connected: 450mA typical, but can vary with the keyboard used
(most of modern AT keyboard uses max. 100mA. User should check his
keyboard current requirements before connecting the keyboard to the
DevKit16 Mainboard).
keyboard and VGA interface connected: 650mA
Warning: If the DevKit16 is powered using the on-board stabilizer, the
supply current must not exceed the 1A limit of the stabilizer. Before
connecting any peripheral to the DevKit16, please check that its power
supply current requirements doesn’t does not cause this limit to be exceeded.
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ꢇ
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH
restricts its warranties and its liability for the DEVKIT16 and all its deliverables (eg. software,
application examples, target boards, evaluation boards, etc.), its performance and any consequential
damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the
Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the
technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent
permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and
liabilities for the performance of the Product and any consequential damages in cases of unauthorised
decompiling and/or reverse engineering and/or disassembling. Note, the DEVKIT16 and all its
deliverables are intended and must only be used in an evaluation laboratory environment.
1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of receipt
by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics
Europe GmbH warrants that the Product will be free from defects in material and workmanship
under use and service as specified in the accompanying written materials for a duration of 1 year
from the date of receipt by the customer.
2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability and
the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s sole
discretion, either return of the purchase price and the license fee, or replacement of the Product or
parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original
packing and without further defects resulting from the customer´s use or the transport. However,
this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu
Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any
other third party not relating to Fujitsu Microelectronics Europe GmbH.
3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s and
its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal injury,
assets of substantial value, loss of profits, interruption of business operation, loss of information,
or any other monetary or pecuniary loss) arising from the use of the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect.
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ꢈ
The following bugs have been found with the board and need to be
observed when working with this tool:
Date
Revisions - Errors
Revised
Version
05.11.1999 Version 1.2 is valid for CPU Board ver. 1.3
V1.2
13.02.2000 The table “Device Bus (K2) and Interface Bus (K1 ) connectors V1.21
pins” (pages 16, 17, 18) was not consistent with the schematics.
Table1: List of found errors and revisions for version V1.2
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ꢉ
Here you will find Interface bus and Device Bus description and CPU
board schematics.
DIN Conn.
PIN
Device Bus
Interface Bus
PIN NO.
CPU Pin Nr.
Function
SOT0
SCK0
SIN0
CPU PIN Nr.
SIGNAL
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
A16
2nd Function
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
A1
B1
C1
A2
B2
C2
A3
B3
C3
A4
B4
C4
A5
B5
C5
A6
B6
C6
A7
B7
C7
A8
B8
C8
A9
B9
C9
A10
B10
18
19
20
24
22
21
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
SOT1
SCK1
SIN1
69
70
71
72
29
30
31
32
25
26
28
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
SOT2
SCK2
SIN2
2
A17
3
A18
4
A19
5
A20
6
A21
7
A22
8
A23
9
ALE
10
12
13
14
\RD
\WRL
\WRH
HRQ
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DIN Conn.
PIN
Device Bus
Interface Bus
PIN NO.
CPU Pin Nr.
Function
CPU PIN Nr.
SIGNAL
\HAK
RDY
2nd Function
P35
C10
A11
B11
C11
A12
B12
C12
A13
B13
C13
A14
B14
C14
A15
B15
C15
A16
B16
C16
A17
C17
C17
A18
B18
C18
A19
B19
C19
C20
A21
C20
A21
B21
C21
A22
B22
C22
A23
B23
C23
A24
B24
C24
A25
B25
C25
A26
B26
C26
A27
B27
C27
15
16
17
47
48
TIN0
TOT0
GND
TIN1
P36
CLK
P37
GND
SOT0
SCK0
SIN0
SOT1
SCK1
SIN1
SOT2
SCK2
SIN2
SDA
GND
P40
67
68
18
19
20
24
22
21
25
26
28
TOT1
P41
P42
P45
53
54
55
56
57
58
59
60
65
66
IN0
IN1
P44
P43
IN2
P46
IN3
P47
IN4
P50
IN5
OUT2/IN6
OUT3/IN7
OUT0
OUT1
VCC
SCL
61
62
67
PPG0
PPG1
TIN1
P80
P81
P86
VCC
59
60
OUT3/IN7
OUT2/IN6
AVCC
33
68
34
35
36
37
38
39
ADTG
TOT1
AVCC
AVR+
AVR-
AGND
AN0
P55
P87
AGND
GND
P60
P61
GND
P62
P63
P64
P65
P66
P67
AN1
GND
AN2
40
41
43
44
45
46
77
52
69
70
71
72
29
30
31
32
53
54
55
56
59
60
AN3
AN4
AN5
AN6
AN7
61
62
63
64
PPG0
PPG1
PPG2
PPG3
\RST
\HST
INT0
P90
P91
P92
P93
P51
P52
P53
P54
P70
P71
P72
P73
P76
P77
INT1
INT2
INT3
73
74
75
76
TX0
RX0
TX1
RX1
INT4
INT5
INT6
INT7
IN0
IN1
IN2
IN3
OUT2/IN6
OUT3/IN7
NC(SGO)
NC(SGA)
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DIN Conn.
PIN
PIN NO.
Device Bus
CPU Pin Nr. Function
Interface Bus
CPU PIN Nr.
SIGNAL
TX0
2nd Function
P94
A28
B28
C28
A29
B29
C29
A30
B30
C30
A31
B31
C31
A32
B32
C32
73
74
75
76
79
80
82
83
RX0
TX1
P95
P96
RX1
X1AJ
X0AJ
X0J
P97
X1J
VCC
GND
VCC
MD0
MD1
NC
49
50
51
MD2
NC
GND
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K2
DIN_41612
K1
DIN_41612
SOUND
J15
JUMPER2
K9
K375A
X0A
X1A
X0
X0AJ
X1AJ
X0J
J19
JUMPER2
J20
JUMPER2
IC1
P00/AD00
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
85
86
87
88
89
90
91
92
18
19
20
21
22
24
25
26
SOT0
SCK0
SIN0
SIN1
SCK1
SOT1
SOT2
SCK2
CH1
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
P45/SOT1
P46/SOT2
P47/SCK2
SDA
HRQ
SCL
J16
JUMPER2
P01/AD01
P02/AD02
P03/AD03
P04/AD04
P05/AD05
P06/AD06
P07/AD07
2
1
#HAK
SK 129 25.4mm
J17
JUMPER2
PL2
+5V
PL3
1
1
2
2
+5V
D4
D6
A
A
K
A
K
J13
J18
JUMPER2
AD08
AD09
AD10
AD11
AD12
AD13
AD14
93
94
95
96
97
98
99
28
29
30
31
32
33
47
48
SIN2
IC3
LM7805
JUMPER2
P10/AD08
P11/AD09
P12/AD10
P13/AD11
P14/AD12
P15/AD13
P16/AD14
P17/AD15
P50/SIN2
P51/INT4
P52/INT5
P53/INT6
P54/INT7
P55/ADTG
P56/TIN0
P57/TOT0
1N4007 SMD
1N4007 SMD
INT4
INT5
INT6
INT7
ADTG
TIN0
TOT0
D5
D7
X1
X1J
K
A
K
IN
OUT
VCC
IN
OUT
1N4007 SMD
2
1N4007 SMD
VCC
C16
100N
C15
100N
C11
100N
GND 1
R15
10K
+5V
C18
100M/25V
AD15 100
J5
C10
10M/25V
IC2
CT
VSC
OUTC
GND
GND PL1
J3
JUMPER2
1
2
3
4
8
7
6
5
#RST
JUMPER2
RESET
VSA
VSB/RESIN
VCC
A16
A17
A18
A19
A20
A21
A22
A23
1
2
3
4
5
6
7
8
34
35
AVCC
AVR+
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
AVcc
VCC
1
GND GND
PWRD
GND
GND
R16
3K6
R1
220R
R3
1K
AVR+
J8 JUMPER3
GND
MB3771
SIN1
36
37
AVR-
GND
1
AVR-
AVss
1
R4
220R
K7
BOXHEADER 5X2
AGND
GND
SIN0
ALE
#RD
#WRL
#WRH 13
HRQ
#HAK
RDY
CLK
9
10
12
38
39
40
41
43
44
45
46
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
R2
1K
K3
K5
P30/ALE
P31/#RD
P32/#WRL/#WR
P33/#WRH
P34/HRQ
P35/#HAK
P36/RDY
P37/CLK
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AD00
MD0
AD01
MD2
J6
JUMPER2
J4
1
3
5
7
9
2
4
6
8
10
A16
A18
A20
A22
ALE
GND
#WRH
#HAK
CLK
SCK0
SIN1
FVCC
SOT2
C
A17
A19
A21
A23
MD2
#HST
IN1
IN3
IN5
OUT3/IN7
PPG1
PPG3
OUT1
TOT1
INT1
INT3
RX0
1
3
5
7
2
4
6
8
1
3
5
7
2
4
6
8
D2
JUMPER2
IN0
IN2
IN4
SERRES
A
K
14
15
16
17
1N4148 SMD
SW1
PB1720
J9 JUMPER3
#RD
OUT2/IN6
PPG0
PPG2
OUT0
TIN1
INT0
INT2
TX0
SCK1
9
10
12
14
16
18
20
22
24
26
28
30
9
10
#WRL
HRQ
RDY
SOT0
SIN0
SCK1
SOT1
SCK2
SIN2
INT5
1
VCC
GND
11
13
15
17
19
21
23
25
27
29
11
13
15
17
19
21
23
25
27
29
12
14
16
18
20
22
24
26
28
30
GND
GND
C12
INT0
INT1
INT2
INT3
TX0
RX0
TX1
RX1
69
70
71
72
73
74
75
76
53
54
55
56
57
58
59
60
IN0
IN1
IN2
IN3
IN4
IN5
OUT2/IN6
OUT3/IN7
P90/INT0
P91/INT1
P92/INT2
P93/INT3
P94/TX0
P95/RX0
P96/TX1
P97/RX1
P70/IN0
P71/IN1
P72/IN2
P73/IN3
P74/IN4
SCK0
J7 JUMPER3
100N
#RST
TX1
#RST
X1A
RX1
PA0
X0A
SOT1
1
P75/IN5
INT4
P76/OUT2/IN6
P77/OUT3/IN7
#HST
HEADER 15X2
HEADER 15X2
SOT0
#RST
PA0
77
78
61
62
63
64
65
66
67
68
PPG0
PPG1
PPG2
PPG3
OUT0
OUT1
TIN1
TOT1
#RST
PA0
P80/PPG0
P81/PPG1
P82/PPG2
P83/PPG3
P84/OUT0
P85/OUT1
P86/TIN1
P87/TOT1
C13
100N
K4
K6
INT6
ADTG
AVR+
AGND
AN1
AN3
AN4
AN6
TIN0
MD0
INT7
AVCC
AVR-
AN0
AN2
GND
AN5
AN7
TOT0
MD1
GND
X1
X0
1
3
5
7
2
4
6
1
3
5
7
2
4
6
FVCC
AD01
AD03
AD05
AD07
AD09
AD11
AD13
AD15
SW2
PB1720
GND
MD0
MD1
MD2
49
50
51
AD00
AD02
AD04
AD06
AD08
AD10
AD12
AD14
MD0
MD1
MD2
8
8
9
10
12
14
16
18
20
9
10
12
14
16
18
20
GND
VCC
11
13
15
17
19
11
13
15
17
19
X1
#HST
X1
52
83
82
VCC
VCC
J11
C1
#HST
X1
C7 22pF 4MHz
27
C
10M/25V
VCC
J10
C
1
2
3
4
5
6
1
R6
1K
C2
100N
GND
GND
1
2
3
4
SW3
23
84
J2
JUMPER2
VCC
VCC
X0
R8 10K
R9 10K
R10 10K
R11 10K
R12 10K
MD0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XO
GND
FVCC
MD1
MD2
#RST
#HST
#HST
AD00
AD01
HEADER 10X2
HEADER 10X2
C6 22pF
X2
HEADER 4
X1A
X0A
79
80
11
42
81
GND
GND
X1A
VSS
VSS
VSS
HEADER 6
SERRES
#RST
GND
GND
X0A
C4
C3
C5
10K
D3
LED 5mm
R13
R14 10K
C9 22pF 32.768KHz
C8 22pF
MB90540
GND 100N 100N 10M/25V
Title
Devkit16 - CPU Board
Number Ver. 1
GND
GND
SW DIP-8
Size
A3
Re3vision
Date:
File:
8-Dec-1999
Sheet of
Drawn By:
D:\Cpuboard13.ddb
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