FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21374-1E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F74UL
■ DESCRIPTION
The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The pin assignments are the same as MB15F78UL. Fast locking is achieved for adopting
the new circuit.
The new package (BCC20) decreases a mount area of MB15F74UL more than 30% comparing with the former
BCC16 (for dual PLL) .
■ FEATURES
• High frequency operation
: RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max
: VCC = 2.7 to 3.6 V
• Low power supply voltage
• Ultra low power supply current : ICC = 9.0 mA Typ
(VCC = Vp = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)
(Continued)
■ PACKAGE
20-pad plastic BCC
(LCC-20P-M05)
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MB15F74UL
■ PIN DESCRIPTION
Pin
name
Pin no.
I/O
Descriptions
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
1
finIF
I
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
2
3
4
XfinIF
GNDIF
VCCIF
Ground pin for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section (except for the charge pump
circuit) , the shift register and the oscillator input buffer.
Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when
the power supply is started up. (Open is prohibited.)
5
PSIF
I
PSIF = “H” ; Normal mode/PSIF = “L” ; Power saving mode
6
7
VpIF
DoIF
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output for the IF-PLL section.
O
O
O
Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The
output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal
8
LD/fout
9
DoRF
Charge pump output for the RF-PLL section.
10
VpRF
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be set at “L” when the
power supply is started up. (Open is prohibited. )
11
PSRF
I
PSRF = “H” ; Normal mode/PSRF = “L” ; Power saving mode
Power supply voltage input pin for the RF-PLL section (except for the charge pump
circuit)
12
13
14
VCCRF
GNDRF
XfinRF
Ground pin for the RF-PLL section
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
I
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
15
16
finRF
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.
LE
I
I
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in a serial data.
17
18
Data
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.
Clock
I
I
The programmable reference divider input pin. TCXO should be connected with an AC
coupling capacitor.
19
20
OSCIN
GND
Ground pin for OSC input buffer and the shift register circuit.
3
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MB15F74UL
■ BLOCK DIAGRAM
VpIF
(6)
VCCIF GNDIF
(4)
(3)
Intermittent
mode control
(IF-PLL)
3 bit latch
PSIF (5)
7 bit latch
Binary 7-bit
11 bit latch
Binary 11-bit
Phase
comp.
(IF-PLL)
Charge
pump
(IF-PLL)
(7)
DoIF
Current
Switch
swallow counter programmable
(IF-PLL)
counter (IF-PLL)
fpIF
(1)
(2)
finIF
Prescaler
(IF-PLL)
(32/33, 64/65)
Lock Det.
(IF-PLL)
XfinIF
2 bit latch
14 bit latch
1 bit latch
LDIF
Binary 14-bit pro-
grammable ref.
counter(IF-PLL)
C/P setting
counter
T1 T2
frIF
Fast
lock
OSCIN (19)
Tuning
Selector
AND
LDRF
frRF
LD
frIF
frRF
fpIF
fpRF
Binary 14-bit pro-
grammable ref.
counter (RF-PLL))
T1 T2
C/P setting
counter
(8) LD/
OR
fout
2 bit latch
14 bit latch
1 bit latch
fpRF
Prescaler
(RF-PLL)
(64/65, 128/129)
finRF
(15)
Lock Det.
(RF-PLL)
(
14
)
XfinRF
Phase
comp.
(RF-PLL)
Charge
pump
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
Current
Switch
(9)
DoRF
Intermittent
mode control
(RF-PLL)
PSRF (11)
fpRF
3 bit latch
7 bit latch
11 bit latch
Schmitt
circuit
LE
(16)
Latch selector
Schmitt
circuit
Schmitt
circuit
C
N
1
C
N
2
Data (17)
23-bit shift register
Clock
(18)
(20)
(12)
(13)
(10)
VpRF
VCCRF GNDRF
GND
4
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MB15F74UL
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
−0.5
VCC
Max
VCC
Vp
4.0
4.0
V
V
Power supply voltage
Input voltage
VI
−0.5
GND
GND
−55
VCC + 0.5
VCC
V
LD/fout
Output voltage
VO
V
DoIF, DoRF
VDO
Tstg
Vp
V
Storage temperature
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remarks
Min
2.7
Typ
3.0
3.0
Max
3.6
VCC
Vp
VI
V
V
VCCRF = VCCIF
Power supply voltage
VCC
3.6
Input voltage
GND
−40
VCC
+85
V
Operating temperature
Ta
°C
Note : • VCCRF, VpRF, VCCIF and VpIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep
them equal.
It is recommended that the non-use PLL is controlled by power saving function.
• Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the following precautions when handling the device.
• When storing and transporting the device, put it in a conductive case.
• Beforehandlingthedevice, confirmthe (jigsand)toolstobeusedhavebeenuncharged(grounded)as
well as yourself. Use a conductive sheet on working bench.
• Before fitting the device into or removing it from the socket, turn the power supply off.
• When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
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MB15F74UL
*
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
Min
Typ
Max
finIF = 2000 MHz
*1
ICCIF
2.1
2.5
3.2
mA
mA
VCCIF = VpIF = 3.0 V
Power supply current
finRF = 2500 MHz
VCCRF = VpRF = 3.0 V
*1
ICCRF
5.7
6.5
8.4
IPSIF
IPSRF
finIF
PSIF = PSRF = “L”
PSIF = PSRF = “L”
IF PLL
0.1*2
0.1*2
10
10
µA
Power saving current
Operating frequency
Input sensitivity
µA
*3
finIF
200
2000
3
2000
4000
40
MHz
MHz
MHz
dBm
dBm
VP−P
*3
finRF
finRF
fOSC
RF PLL
OSCIN
finIF
PfinIF
IF PLL, 50 Ω system
−15
−10
0.5
+2
finRF
PfinRF RF PLL, 50 Ω system
+2
Input available voltage OSCIN
VOSC
VCC
0.7 VCC
+ 0.4
“H” level input voltage
“L” level input voltage
VIH
VIL
Schmitt trigger input
Schmitt trigger input
V
V
Data
LE
Clock
0.3 VCC
− 0.4
“H” level input voltage
“L” level input voltage
VIH
VIL
0.7 VCC
V
V
PSIF
PSRF
0.3 VCC
Data
LE
Clock
PS
*4
“H” level input current
“L” level input current
IIH
−1.0
−1.0
+1.0
µA
µA
*4
IIL
+1.0
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
“H” level output voltage
“L” level output voltage
IIH
0
+100
µA
µA
V
OSCIN
*4
IIL
−100
0
VOH
VOL
VCC = Vp = 3.0 V, IOH = −1 mA
VCC = Vp = 3.0 V, IOL = 1 mA
VCC − 0.4
LD/
fout
0.4
V
VDOH
VDOL
VCC = Vp = 3.0 V, IDOH = −0.5 mA Vp − 0.4
VCC = Vp = 3.0 V, IDOL = 0.5 mA
V
DoIF
DoRF
0.4
2.5
V
High impedance cutoff DoIF
current
VCC = Vp = 3.0 V
VOFF = 0.5 V to Vp − 0.5 V
IOFF
nA
DoRF
*4
“H” level output current
“L” level output current
IOH
VCC = Vp = 3.0 V
−1.0
mA
mA
LD/
fout
IOL
VCC = Vp = 3.0 V
1.0
(Continued)
6
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MB15F74UL
(Continued)
(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
Min
Typ
Max
VCC = Vp = 3.0 V,
CS bit = “H”
CS bit = “L”
CS bit = “H”
CS bit = “L”
−8.2
−6.0
−4.1
mA
mA
mA
mA
*8
“H” level output
current
DoIF
*4
IDOH
VDOH = Vp / 2,
Ta = +25 °C
DoRF
−2.2
4.1
−1.5
6.0
−0.8
8.2
VCC = Vp = 3.0 V,
VDOL = Vp / 2,
Ta = +25 °C
*8
“L” level output
current
DoIF
IDOL
*5
DoRF
0.8
1.5
2.2
IDOL/IDOH IDOMT
VDO = Vp / 2
3
10
15
%
%
*6
*7
Charge pump
current rate
vs VDO
IDOVD
0.5 V ≤ VDO ≤ Vp − 0.5 V
10
−40 °C ≤ Ta ≤ 85 °C,
VDO = Vp / 2
vs Ta
IDOTA
5
10
%
*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state.
*2 : VCCIF = VpIF = VCCRF = VpRF = 3.0 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode.
PSIF = PSRF = GND
VIH = VCC, VIL = GND (at CLK, Data, LE)
*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means the direction of current flow.
*5 : VCC = Vp = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)
*6 : VCC = Vp = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to both lDOL and lDOH)
*7 : VCC = Vp = 3.0 V, [||IDO (+85 °C) | − |IDO (–40 °C) || / 2] / [|IDO (+85 °C) | + |IDO (–40 °C) | / 2] × 100 (%) (Applied to both
IDOL and IDOH)
*8 : When Charge pump current is measured, set LDS = “L” , T1 = “L” and T2 = “H”.
I3
I4
I1
I2
I2
IDOL
IDOH
I1
0.5
Vp/2
Vp − 0.5
Vp
Charge pump output voltage (V)
7
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MB15F74UL
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO = [ (P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P
N
A
: Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL)
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
R
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-
PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
The programmable The programmable
The programmable
The programmable
reference counter reference counter counter and the swallow counter and the swallow
for the IF-PLL
for the RF-PLL
counter for the IF-PLL
counter for the RF-PLL
CN1
CN2
0
0
1
0
0
1
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
X
X
X
CS
: Charge pump current select bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2
CN1, 2
X
: LD/fout output setting bit
: Control bit
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
8
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MB15F74UL
• Programmable Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SWIF/
RF
FCIF/
RF
CN1 CN2 LDS
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
N1 to N11
LDS
SWIF/RF
FCIF/RF
CN1, 2
: Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)
: Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
: Control bit
Note : Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
16383
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting
Divide ratio N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
2047
Note : Divide ratio less than 3 is prohibited
• Binary 7-bit Swallow Counter Data Setting
Divide ratio A7 A6 A5 A4 A3 A2 A1
0
0
0
0
0
0
0
0
1
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
1
•
1
•
1
•
1
•
1
127
9
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MB15F74UL
• Prescaler Data Setting
Divide ratio
SW = “H”
32/33
SW = “L”
64/65
Prescaler divide ratio IF-PLL
Prescaler divide ratio RF-PLL
64/65
128/129
• Charge Pump Current Setting
Current value
±6.0 mA
CS
1
±1.5 mA
0
• LD/fout output Selectable Bit Setting
LD/fout pin state
LD output
frIF
LDS
T1
T2
0
0
0
1
1
0
1
0
1
0
0
0
1
1
0
frRF
fpIF
1
0
fout
output
1
1
fpRF
1
1
• Phase Comparator Phase Switching Data Setting
FCIF, RF = “H”
Phase comparator input
DoIF, RF
FCIF, RF = “L”
DoIF, RF
fr > fp
fr < fp
H
L
L
H
Z
fr = fp
Z
Z : High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = “H”
(2) VCO polarity FC = “L”
VCO Output
Frequency
(2)
Max
LPF Output voltage
Note : Give attention to the polarity for using active type LPF.
10
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MB15F74UL
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PS pin
H
L
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes : • When power (VCC) is first applied, the device must be in standby mode.
• PS pin must be set “L” at Power-ON.
OFF
ON
VCC
tV ≥ 1 µs
Clock
Data
LE
PS
tPS ≥ 100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data at least 1 µs after the power supply becomes stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PSIF, PSRF : “L” → “H”) at least 100 ns later after setting serial data.
11
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MB15F74UL
4. Serial Data Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
1st data
2nd data
Invalid data
Control bit
Data
MSB
LSB
Clock
LE
t1
t2
t3
t6
t7
t4
t5
Parameter Min
Typ
Max
Unit
ns
Parameter
Min
100
20
Typ Max
Unit
ns
t1
t2
t3
t4
20
20
30
30
t5
t6
t7
ns
ns
ns
100
ns
ns
Note : LE should be “L” when the data is transferred into the shift register.
12
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MB15F74UL
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DoIF/RF
Z
L
(FC bit = Low)
H
DoIF/RF
Z
L
• LD Output Logic
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
RF-PLL section
Locking state/Power saving state
Unlocking state
LD output
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes : • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals during locking state are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU ≥ 2/fosc : e.g. tWU ≥ 156.3 ns when fosc = 12.8 MHz
tWU ≤ 4/fosc : e.g. tWL ≤ 312.5 ns when fosc = 12.8 MHz
13
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MB15F74UL
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
Controller
(Divide ratio setting)
S.G.
1000 pF
50 Ω
S.G.
1000 pF
S.G.
1000 pF
50 Ω
GND OSCIN Clock Data
50 Ω
LE
20
16
19
18
finIF
1
2
17
finRF
15
14
13
XfinIF
GNDIF
VCCIF
PSIF
XfinRF
GNDRF
VCCRF
PSRF
1000 pF
3
4
5
6
MB15F74UL
1000 pF
12
11
VCCRF
8
7
9
10
VpIF
VpIF
VCCIF
DoIF LD/fout DoRF VpRF
0.1 µF
VpRF
0.1 µF
0.1 µF
0.1 µF
Oscilloscope
14
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MB15F74UL
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity vs. Input frequency
10
0
SPEC
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−10
−20
−30
−40
−50
1000
1500
2000
2500
3000
3500
finRF [MHz]
4000
4500
5000
5500
6000
IF-PLL input sensitivity vs. Input frequency
10
0
SPEC
−10
−20
−30
−40
−50
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
0
500
1000
1500
2000
2500
3000
3500
finIF [MHz]
15
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MB15F74UL
2. OSCIN input sensitivity
Input sensitivity vs. Input frequency
10
SPEC
0
−10
−20
−30
−40
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−50
0
50
100
150
200
250
300
Input frequency fOSC (MHz)
16
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3. RF-PLL Do output current
• 1.5 mA mode
IDO − VDO
10.0
VCC = Vp = 3.0 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
10.0
VCC = Vp = 3.0 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
17
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MB15F74UL
4. IF-PLL Do output current
• 1.5 mA mode
IDO − VDO
10.0
VCC = Vp = 3.0 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
10.0
VCC = Vp = 3.0 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
18
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MB15F74UL
5. fin input impedance
finIF input impedance
4 : 16.453 Ω
−46.539 Ω
2 000.000 000 MHz
1 : 866.25 Ω
−916.31 Ω
100 MHz
2 :
76.5 Ω
−319.2 Ω
500 MHz
3 : 31.078 Ω
−152.46 Ω
1 GHz
1
2
3
4
START 100.000 000 MHz
STOP 2 000.000 000 MHz
finRF input impedance
4 : 25.791 Ω
34.824 Ω
4 000.000 000 MHz
1 : 35 336
Ω
−151.85 Ω
1 GHz
4
2 : 17.436 Ω
−52.191 Ω
2 GHz
3 : 20.211 Ω
−743.16 mΩ
3 GHz
3
1
2
START 1 000.000 000 MHz
STOP 4 000.000 000 MHz
19
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MB15F74UL
6. OSCIN input impedance
OSCIN input impedance
4 : 049.5 Ω
−1.0414 kΩ
100.000 000 MHz
1 :15.882 kΩ
−11.652 kΩ
3 MHz
2 : 3.924 kΩ
−8.942 kΩ
10 MHz
3 :
286 Ω
−2.5913 kΩ
4
40 MHz
1
2
3
START 3.000 000 MHz
STOP 100.000 000 MHz
20
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MB15F74UL
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
fVCO = 2500 MHz VCC = 3.0 V
Test Circuit
KV = 50 MHz/V
fr = 200 kHz
fOSC = 13 MHz
LPF
Ta = + 25 °C
CP : 6 mA mode
S.G.
OSCIN
Do
LPF
fin
7.5 kΩ
Spectrum
Analyzer
VCO
To VCO
2.7 kΩ
1500 pF
330 pF
15000 pF
• PLL Reference Leakage
ATTEN 10 dB
RL 0 dBm
∆MKR −70.00 dB
200 kHz
10 dB/
∆MKR
200 kHz
−70.00 dB
D
S
CENTER 2.500000 GHz
SPAN 1.000 MHz
SWP 280 ms
∗
RBW 3.0 kHz
VBW 3.0 kHz
• PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
∆MKR −69.01 dB
1.00 kHz
10 dB/
∆MKR
1.00 kHz
−69.01 dB/Hz
D
S
CENTER 2.50000000 GHz
SPAN 10.00 kHz
SWP 1.92 s
∗
RBW 30 Hz
VBW 30 Hz
(Continued)
21
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MB15F74UL
(Continued)
PLL Lock Up time
PLL Lock Up time
2500 MHz→2550 MHz within ± 1 kHz
L ch→H ch 440 µs
2550 MHz→2500 MHz within ± 1 kHz
H ch→L ch
400 µs
A Mkr x: 439.99764 µs
y: 50.0009 MHz
A Mkr x: 400.00146 µs
y: −50.0013 MHz
100.0050
MHz
100.0050
MHz
2.00
2.00
kHz/div
kHz/div
99.99500
MHz
99.99500
MHz
0 s
0 s
2.0000000 ms
2.0000000 ms
22
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MB15F74UL
■ APPLICATION EXAMPLE
1000 pF
TCXO
From controller
GND OSCIN Clock Data
1000 pF
LE
20
16
19
18
finIF
XfinIF
GNDIF
VCCIF
PSIF
1
2
17
1000 pF
finRF
15
14
13
1000 pF
XfinRF
GNDRF
VCCRF
PSRF
3
4
5
6
MB15F74UL
1000 pF
12
11
3.0 V
8
7
9
10
VpIF
3.0 V
3.0 V
0.1 µF
0.1 µF
DoIF LD/fout DoRF VpRF
3.0 V
0.1 µF
0.1 µF
Output
Output
LPF
VCO
Lock Det.
LPF
VCO
Note : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up register
to prevent oscillation when open-circuit in the input) .
23
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MB15F74UL
■ USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep
them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :
• Store and transport devices in conductive containers.
• Use properly grounded workstations, tools, and equipment.
• Turn off power before inserting or removing this device into or from a socket.
• Protect leads with conductive sheet, when transporting a board mounted device
■ ORDERING INFORMATION
Part number
MB15F74ULPVA
Package
Remarks
20-pad plastic BCC
(LCC-20P-M05)
24
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MB15F74UL
■ PACKAGE DIMENSION
20-pad plastic BCC
(LCC-20P-M05)
3.00(.118)TYP
0.25±0.10
3.60±0.10(.142±.004)
0.55±0.05
(.022±.002)
(Mounting height)
(.010±.004)
16
11
11
16
0.50(.020)
TYP
0.25±0.10
(.010±.004)
INDEX AREA
3.40±0.10
(.134±.004)
2.70(.106)
TYP
"D"
"A"
"B"
"C"
1
6
6
1
0.50(.020)
TYP
0.075±0.025
(.003±.001)
(Stand off)
2.80(.110)REF
0.05(.002)
Details of "A" part
Details of "B" part
Details of "C" part
Details of "D" part
0.50±0.10
0.50±0.10
0.50±0.10
0.30±0.10
(.020±.004)
(.020±.004)
(.020±.004)
(.012±.004)
C0.20(.008)
0.60±0.10
(.024±.004)
0.30±0.10
(.012±.004)
0.60±0.10
(.024±.004)
0.40±0.10
(.016±.004)
C
2001 FUJITSU LIMITED C20056S-c-2-1
(
)
Dimensions in mm inches
25
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MB15F74UL
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0210
FUJITSU LIMITED Printed in Japan
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