Fujitsu Microcassette Recorder MB89990 Series User Manual

CM25-10133-2E  
FUJITSU SEMICONDUCTOR  
MICROCONTROLLER MANUAL  
2
F MC-8L FAMILY  
8-BIT MICROCONTROLLER  
MB89990 Series  
HARDWARE MANUAL  
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2
F MC-8L FAMILY  
8-BIT MICROCONTROLLER  
MB89990 Series  
HARDWARE MANUAL  
FUJITSU LIMITED  
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PREFACE  
Preface describes objectives and intended reader.  
Objectives and Intended Reader  
The MB89990 series of microcontrollers are mid-range of microcontroller. They are general-  
purpose and high-speed products in the F2MC-8L Family series of 8-bit single-chip  
microcontrollers operating at low voltages. It has Timer, Remote-control transmission frequency  
generator.  
This manual covers the functions and operations of the MB89990 series of microcontrollers.  
Refer to the F2MC-8L Family Software Manual for instructions.  
i
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1. The contents of this document are subject to change without notice. Customers are advised to consult  
with FUJITSU sales representatives before ordering.  
2. The information and circuit diagrams in this document are presented as examples of semiconductor  
device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is  
unable to assume responsibility for infringement of any patent rights or other rights of third parties  
arising from the use of this information or circuit diagrams.  
3. The contents of this document may not be reproduced or copied without the permission of FUJITSU  
LIMITED.  
4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office  
automation and other office equipments, industrial, communications, and measurement equipments,  
personal or household devices, etc.).  
CAUTION:  
Customers considering the use of our products in special applications where failure or abnormal  
operation may directly affect human lives or cause physical injury or property damage, or where  
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls,  
sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to  
consult with FUJITSU sales representatives before such use. The company will not be responsible for  
damages arising from such use without prior approval.  
5. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,  
damage or loss from such failures by incorporating safety design measures into your facility and  
equipment such as redundancy, fire protection, and prevention of over-current levels and other  
abnormal operating conditions.  
6. If any products described in this document represent goods or technologies subject to certain  
restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior  
authorization by Japanese government should be required for export of those products from Japan.  
©2000 FUJITSU LIMITED Printed in Japan  
ii  
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CONTENTS  
CHAPTER 1 GENARAL ..................................................................................................... 1  
1.1 Features ................................................................................................................................................ 2  
1.2 Product Series ....................................................................................................................................... 3  
1.3 Block Diagram ....................................................................................................................................... 5  
1.4 Pin Assignment ...................................................................................................................................... 6  
1.5 Pin Function Description ........................................................................................................................ 8  
1.6 Handling Devices ................................................................................................................................. 12  
CHAPTER 2 HARDWARE CONFIGRATION ................................................................... 13  
2.1 CPU ..................................................................................................................................................... 14  
2.2 Lock Control Block ............................................................................................................................... 19  
2.3 Interrupt Controller ............................................................................................................................... 25  
2.4 I/O Ports .............................................................................................................................................. 28  
2.5 8/16-bit Timer (Timer 1 and Timer 2) ................................................................................................... 32  
2.6 External Interrupt 1 .............................................................................................................................. 39  
2.7 External Interrupt 2 (Wake Up) ............................................................................................................ 43  
2.8 Remote-control Carrier Frequency Generator ..................................................................................... 45  
2.9 Time-base Timer .................................................................................................................................. 48  
2.10 Watchdog Timer Reset ........................................................................................................................ 51  
CHAPTER 3 OPERATION ............................................................................................... 53  
3.1 Clock Pulse Generator ......................................................................................................................... 54  
3.2 Reset ................................................................................................................................................... 55  
3.2.1 Reset Operation ............................................................................................................................. 56  
3.2.2 Reset Source .................................................................................................................................. 57  
3.3 Interrupt ............................................................................................................................................... 58  
3.4 Low-power Consumption Modes ......................................................................................................... 60  
3.5 Pin States for Sleep, Stop and Reset .................................................................................................. 61  
CHAPTER 4 INSTRUCTIONS .......................................................................................... 63  
4.1 Transfer Instructions ............................................................................................................................ 64  
4.2 Operation Instruction ........................................................................................................................... 66  
4.3 Branch Instructions .............................................................................................................................. 68  
4.4 Other Instructions ................................................................................................................................ 69  
4.5 F2MC-8L Family Instruction Map ......................................................................................................... 70  
CHAPTER 5 MASK OPTIONS ......................................................................................... 71  
5.1 Mask Options ....................................................................................................................................... 72  
APPENDIX ............................................................................................................................ 73  
APPENDIX A I/O Map ................................................................................................................................ 74  
APPENDIX B EPROM Setting for MB89P195 ............................................................................................ 76  
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FIGURES  
Figure 1.4-1  
Figure 1.4-2  
Figure 2.1-1  
Figure 2.1-2  
Figure 2.1-3  
Figure 2.1-4  
Figure 2.1-5  
Figure 2.1-6  
Figure 2.3-1  
Figure 2.4-1  
Figure 2.4-2  
Figure 2.5-1  
Figure 2.5-2  
Figure 2.5-3  
Figure 2.5-4  
Figure 2.5-5  
Figure 2.5-6  
Figure 3.1-1  
Figure 3.2-1  
Figure 3.2-2  
Figure 3.3-1  
Pin Assignment (FPT-28P-M02, DIP-28P-M03) ........................................................................ 6  
Pin Assignment (MQP-48C-P01) ................................................................................................ 7  
Memory Space of MB89990 Series of Microcontrollers ............................................................ 14  
Arrangement of 16 bit Data in Memory ..................................................................................... 16  
Arrangement of 16-bit Data during Execution of Instruction ..................................................... 16  
Structure of Processor Status ................................................................................................... 17  
Rule for Translating Real Addresses at General-purpose Register Area ................................. 17  
Register Bank Configuration ..................................................................................................... 18  
Interrupt-processing Flowchart ................................................................................................. 27  
Ports 00 to 07 and 30 to 37 ...................................................................................................... 30  
Ports 40 to 45 ........................................................................................................................... 31  
8/16-bit Timer Block Diagram ................................................................................................... 32  
Description Diagram for Internal Clock Mode Operation .......................................................... 36  
Flow Diagram for Timer Setting ................................................................................................ 36  
Initialization of Equivalent Circuit .............................................................................................. 37  
External Cock Mode Operation Description Diagram ............................................................... 37  
Operation Diagram when Timer Stop Bit is Used ..................................................................... 38  
Clock Pulse Generator .............................................................................................................. 54  
Outline of Reset Operation ....................................................................................................... 56  
Reset Vector Structure ............................................................................................................. 56  
Interrupt-processing Flowchart ................................................................................................. 58  
iv  
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TABLES  
Table 1.2-1  
Table 1.5-1  
Table 1.5-2  
Table 1.5-3  
Table 2.1-1  
Table 2.2-1  
Table 2.2-2  
Table 2.2-3  
Table 2.4-1  
Table 3.3-1  
Table 3.4-1  
Table 3.5-1  
Table 5.1-1  
Types and Functions of MB89990 Series of Microcontrollers ..................................................... 3  
Pin Function Description .............................................................................................................. 8  
Pins for External ROM ................................................................................................................. 9  
Input/Output Circuit Configurations ........................................................................................... 10  
Table of Reset and Interrupt Vectors ......................................................................................... 15  
Opeating State of Low-power Consumption Modes .................................................................. 21  
Selection of Oscillation Stabilization Time ................................................................................. 22  
Sources of Reset ....................................................................................................................... 24  
List of Port Functions ................................................................................................................. 28  
Interrupt Sources and Interrupt Vectors .................................................................................... 59  
Low-power Consumption Mode at Each Clock Mode ................................................................ 60  
Pin State of MB89990 ............................................................................................................... 61  
Mask Options ............................................................................................................................ 72  
v
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vi  
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CHAPTER 1 GENARAL  
The MB89990 series contains microcontrollers with a full range of resources such as  
2
timers, external interrupts, and remote-control function, as well as the F MC-8L CPU  
core for low-voltage and high-speed operation. This single-chip microcontroller is  
suitable for small devices such as remote controllers incorporating compact packages.  
1.1 Features  
1.2 Product Series  
1.3 Block Diagram  
1.4 Pin Assignment  
1.5 Pin Function Description  
1.6 Handling Devices  
1
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CHAPTER 1 GENARAL  
1.1 Features  
This section describes the features.  
Features  
Minimum instruction execution time: 0.95 µs at 4.2 MHz (VCC = 3 V)  
CPU core common to F2MC-8L CPU  
Instruction set suitable for controller: - Multiply/subtraction instruction, - 16-bit operation,  
- Instruction test and branch instruction, - Bit operation instruction  
Two timers  
8/16-bit timer/counter  
20-bit time-base counter  
External interrupts  
Edge detection: 3 pins (edge direction enabled)  
Low-level interrupt: 8 pins (wake-up)  
Built-in remote-control carrier frequency generator  
Low-power consumption modes  
Stop mode: Almost no power consumption because oscillation stopped  
Sleep mode: 33% of normal power consumption because CPU stopped  
Package: SOP-28, SH-DIP-28 (mask ROM only)  
2
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1.2 Product Series  
1.2 Product Series  
This section describes the product series.  
Product Series  
Table 1.2-1 "Types and Functions of MB89990 Series of Microcontrollers"lists the types and  
functions of the MB89990 series of microcontrollers.  
Table 1.2-1 Types and Functions of MB89990 Series of Microcontrollers  
Model Name  
Classification  
MB89997  
MB89P195*  
MB89PV190*  
Mass-produced product (mask ROM  
product)  
One-time product For evaluation  
and development  
ROM capacity  
32 K × 8 bits  
(internal ROM)  
16 K × 8 bits  
(internal ROM,  
write enable by  
general-purpose  
writer)  
32 K × 8 bits  
(external ROM)  
RAM capacity  
CPU functions  
128 × 8 bits  
256 × 8 bits  
Number of basic instructions  
Instruction bit length  
136 instructions  
8 bits  
Instruction length  
Data bit length  
Minimum instruction execution time  
Interrupt processing time  
1 to 3 bytes  
1, 8, 16 bits  
0.95 µs/4.2 MHz  
8.6 µs/4.2 MHz  
Port  
I/O port (N-ch open drain)  
I/O port (CMOS)  
Total  
6 pins  
16 pins (13 used as resource pins)  
22 pins  
Timer counter  
2 channels 8-bit counter or 1 channel 16-bit counte  
External-interrupt 1  
3 independent channels (edge selection, interrupt vector, interrupt source flag)  
Interrupt mode selectable from rising edge, falling edge, or both edges  
For releasing Stop/Sleep modes (edge detection in Stop mode enabled)  
External-interrupt 2  
(Wake-up)  
8 channels (Low-level interrupt enabled)  
Pulse width and cycle are programmable  
Remote-control  
carrier frequency  
Standby mode  
Process  
Sleep and Stop modes  
CMOS  
Package  
FPT-28P-M02, DIP-28P-M03  
2.2 to 6.0 V**  
FPT-28P-M02  
MQP-48C-P01  
Operating voltage  
2.7V to 6.0 V  
3
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CHAPTER 1 GENARAL  
*
*
The MB89P195 microtroller is the one-time product for the MB89190 series which can be also be used  
for the MB89990 series.  
The MB89PV190 microtroller is the evaluation and development product for the MB89190 series which  
can be also be used for the MB89990 series.  
** Operating voltage varies with conditions such as frequency or others. See the data sheet for details.  
4
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1.3 Block Diagram  
1.3 Block Diagram  
This section describes the block diagram.  
Block Diagram  
Internal Bus  
X0  
Main oscillator  
Remote-control  
carrier frequency  
P34/TO/INT10  
P33 / EC  
circuit  
X1  
8-bit timer/counter  
Clock control  
P30 ~ P32  
RST  
Reset circuit  
8-bit timer/counter  
External Interrupt  
CMOS I/O port  
(WDT)  
P35 / INT11  
P36 / INT12  
P37 / RCO  
Time-base timer  
RAM  
(128 x 8 bits)  
CMOS I/O port  
2
F MC-8L  
P00 / INT20 to  
P07 / INT27  
CPU  
External Interrupt  
(wake-up)  
ROM  
(32K x 8 bits)  
P40 ~ P45  
TEST  
Vcc, Vss  
N-ch open drain I/O port  
5
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CHAPTER 1 GENARAL  
1.4 Pin Assignment  
This section describes the pin assignment.  
Pin Assignment  
Figure 1.4-1 Pin Assignment (FPT-28P-M02, DIP-28P-M03)  
VCC  
P04/INT24  
P05/INT25  
P06/INT26  
P07/INT27  
TEST  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
P03/INT23  
P02/INT22  
P01/INT21  
P00/INT20  
P45  
2
3
4
5
6
RST  
7
X0  
P44  
(TOP VIEW)  
8
X1  
P43  
9
VSS  
P42  
10  
11  
12  
13  
14  
P37/RCO  
P36/INT12  
P35/INT11  
P34/TO/INT10  
P33/EC  
P41  
P40  
P30  
P31  
P32  
6
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1.4 Pin Assignment  
Figure 1.4-2 Pin Assignment (MQP-48C-P01)  
48 47 46 45 44 43 42 41 40 39 38 37  
* 68 67 66 65 64 63 62 61  
P34/TO/INT10  
P33/EC  
P32  
N.C.  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
N.C.  
2
P36/INT12  
P37/RCO  
X1  
3
69  
70  
71  
72  
73  
74  
75  
76  
60  
59  
58  
57  
56  
55  
54  
53  
P31  
4
P30  
5
P40  
X0  
6
(TOP VIEW)  
P41  
RST  
7
P42  
TEST  
8
P43  
P07/INT27  
P06/INT26  
P05/INT25  
P04/INT24  
9
P44  
10  
11  
12  
P45  
P00/INT20  
77 78 79 80 49 50 51 52  
13 14 15 16 17 18 19 20 21 22 23 24  
* Pin assignment on package top (only for piggyback/evaluation product)  
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol  
49  
50  
51  
52  
53  
54  
55  
56  
VPP  
A12  
A7  
A6  
A5  
A4  
A3  
NC  
57  
58  
59  
60  
61  
62  
63  
64  
NC  
A2  
A1  
A0  
01  
02  
03  
GND  
65  
66  
67  
68  
69  
70  
71  
72  
04  
05  
06  
07  
08  
CE  
A10  
NC  
73  
74  
75  
76  
77  
78  
79  
80  
OE  
NC  
A11  
A9  
A8  
A13  
A14  
VCC  
7
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CHAPTER 1 GENARAL  
1.5 Pin Function Description  
This section describes the pin functions.  
Pin Function Description  
Table 1.5-1 "Pin Function Description" and Table 1.5-2 "Pins for External ROM" list the pin  
function and Table 1.5-3 "Input/Output Circuit Configurations" shows the input/output circuit  
configurations.  
Table 1.5-1 Pin Function Description  
Pin No.  
Pin Name  
Circuit type  
Function  
7
8
X0  
X1  
A
Clock oscillator pins  
Test input pin  
5
TEST  
RST  
B
C
These pins are connected directly to VSS  
.
Reset I/O pin  
This pin consists of an N-ch open-drain output with a pull-up  
resistor and hysteresis input. A Low level is output from this  
pin by internal source. The internal circuit is initialized at  
input of a Low level.  
6
P00/INT20  
to  
P03/INT23  
General-purpose I/O port  
These ports also serve as external interrupt input pin.  
The external interrupt input is hysteresis type.  
24 to 27  
1 to 4  
D
D
P04/INT24  
to  
P07/INT27  
General-purpose I/O port  
These ports also serve as external interrupt input pin.  
The external interrupt input is hysteresis type.  
17  
16  
15  
P30  
P31  
P32  
E
E
E
General-purpose I/O port  
General-purpose I/O port  
General-purpose I/O port  
General-purpose I/O port  
This port also serves as an external clock input pin for the 8-  
bit timer/counter. The external clock input is hysteresis type  
with a built-in noise filter.  
14  
13  
P33/EC  
D
D
D
General-purpose I/O port  
This port also serves as an overflow output pin and an  
external interrupt input pin for the 8-bit timer/counter. The  
external interrupt input is hysteresis type with a built-in noise  
filter.  
P34/T0/INT10  
12  
11  
P35/INT11  
P36/INT12  
General-purpose I/O port  
This port also serves as an external interrupt input pin. The  
external interrupt input is hysteresis type with a built-in noise  
filter.  
8
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1.5 Pin Function Description  
Table 1.5-1 Pin Function Description (Continued)  
Pin No.  
Pin Name  
Circuit type  
Function  
General-purpose I/O port  
This port also serves as remote-control output pin.  
N-ch open-drain type I/O port  
Power pin  
10  
P37/RCO  
E
18 to 23  
P40 to P45  
VCC  
F
28  
9
VSS  
Power (GND) pin  
Table 1.5-2 Pins for External ROM  
Pin No.  
Pin Name  
Circuit type  
Output  
Functinon  
High-level output pin  
49  
VPP  
79  
78  
50  
75  
69  
76  
77  
51  
52  
53  
54  
55  
58  
59  
60  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
Output  
Address-output pins  
A4  
A3  
A2  
A1  
A0  
61  
62  
63  
65  
66  
67  
68  
69  
01  
02  
03  
04  
05  
06  
07  
08  
Intput  
Data-input pins  
Chip-enable pin for ROM  
A High level is output in the standby mode.  
70  
73  
CE  
OE  
Output  
Output  
Output-enable pin for ROM  
A Low level is always output.  
80  
64  
VCC  
VSS  
Output  
Output  
Power pin for EPROM  
Power (GND) pin  
9
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CHAPTER 1 GENARAL  
Table 1.5-3 Input/Output Circuit Configurations  
Classification  
Circuit  
Remarks  
Crystal oscillator  
Feedback resistor: About 1 M/5V  
(1 to 5MHz)  
A
X1  
X0  
Standby control signal  
B
CMOS input  
C
Output pull-up resistor (P-ch):  
About 50 k(5 V)  
Hysteresis input  
R
Pch  
Nch  
D
CMOS input/output  
Hysteresis input (resorce input)  
The pull-up resistor is available.  
R
Pch  
Pch  
Nch  
10  
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1.5 Pin Function Description  
Remarks  
Table 1.5-3 Input/Output Circuit Configurations (Continued)  
Classification  
Circuit  
E
CMOS input/output  
The pull-up resistor is available.  
R
Pch  
Pch  
Nch  
F
N-ch open-drain output  
Analog input  
The pull-up resistor is available.  
(MB89990 series only)  
R
Pch  
Nch  
Analog input  
11  
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CHAPTER 1 GENARAL  
1.6 Handling Devices  
This section describes handling devices.  
Handling Devices  
(1) Preventing latch-up  
Latch-up may occur if a voltage higher than VCC or lower than VSS is applied to the input or  
output pins other than middle- and high-level-resistant pins, or if voltage exceeding the rated  
value is applied between VCC and VSS. When latch-up occurs, the supply current increases  
rapidly, sometimes resulting in overheating and destruction. Therefore, no voltage exceeding  
the maximum ratings should be used.  
(2) Handling unused input pins  
Leaving unused input pins open may cause a malfunction. Therefore, these pins should be set  
to pull-up or pull-down.  
(3) Variations in supply voltage  
Although the specified VCC supply voltage operating range is assured, a sudden change in the  
supply voltage within the specified range may cause a malfunction. Therefore, the voltage  
supply to the IC should be kept as constant as possible. The VCC ripple (P-P value) at the  
supply frequency (50 to 60 Hz) should be less than 10% of the typical VCC value, or the  
coefficient of excessive variation should be less than 0.1 V/ms instantaneous change when the  
power supply is switched.  
(4) Precautions for external clocks  
It takes some time for oscillation to stabilize after changing the mode from power-on reset  
(option selection) and stop mode. Consequently, an external clock must be input.  
(5) Recommended screening conditions  
The OPTROM product should be screened by high-temperature aging before mounting.  
Verify program  
High-temperature aging (150°C, 48 H)  
Read  
Mount  
The programming test cannot be performed for all bits of the preprogrammed OPTROM product  
due to its characteristics. Consequently, 100% programming yielding cannot be ensured.  
12  
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CHAPTER 2 HARDWARE CONFIGRATION  
This chapter describes each block of the CPU hardware.  
2.1 CPU  
2.2 Clock Control Block  
2.3 Interrupt Controller  
2.4 I/O Ports  
2.5 8/16-bit Timer (Timer 1 and Timer 2)  
2.6 External Interrupt 1  
2.7 External Interrupt 2 (Wake up)  
2.8 Remote-control Carrier Frequency Generator  
2.9 Time-base Timer  
2.10 Watchdog Timer Reset  
13  
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CHAPTER 2 HARDWARE CONFIGRATION  
2.1 CPU  
• This section describes the memory space and register composing CPU hardware.  
Memory Space  
The MB89990 series of microcontrollers have a memory area of 64K bytes. All I/O, data areas,  
and program areas are located in this space. The I/O area is at the lowest address and the data  
area is immediately above it. The data area may be divided into register, stack, and direct-  
address areas according to the applications. The program area is located near the highest  
address and the tables of interrupt and reset vectors and vector-call instructions are at the  
highest address. Figure 2.1-1 "Memory Space of MB89990 Series of Microcontrollers" shows  
the structure of the memory space for the MB89990 series of microcontrollers.  
Figure 2.1-1 Memory Space of MB89990 Series of Microcontrollers  
MB89P195  
MB89997  
MB89PV190  
0000H  
0080H  
0000H  
0080H  
0000H  
0080H  
I/O  
I/O  
I/O  
Vacant area  
RAM  
RAM  
00C0H  
0100H  
0100H  
0180H  
0100H  
0180H  
RAM  
Register  
Register  
Register  
0140H  
Vacant area  
Vacant area  
Vacant area  
8000H  
8000H  
C000H  
Program PROM  
(Mask ROM)  
External ROM  
Mask ROM  
FFFFH  
FFFFH  
FFFFH  
I/O area  
This area is where various resources such as control and data registers are located. The  
memory map for the I/O area is given in APPENDIX A .  
RAM area  
This area is where the static RAM is located. Addresses from 0100H to 017FH (0100H to  
013FH for the MB89997) are also used as the general-purpose register area.  
ROM area  
This area is where the internal ROM is located. Addresses from FFC0H to FFFFHare also  
14  
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2.1 CPU  
used for the table of reset and vector-call instructions. Table 2.1-1 "Table of Reset and  
Interrupt Vectors " shows the correspondence between each interrupt number or reset  
and the table addresses to be referenced for the MB89990 series of microcontrollers.  
Table 2.1-1 Table of Reset and Interrupt Vectors  
Table address  
Upper data  
FFC0H  
FFC2H  
FFC4H  
FFC6H  
FFC8H  
FFCAH  
FFCCH  
FFCEH  
Lower data  
FFC1H  
FFC3H  
FFC5H  
FFC7H  
FFC9H  
FFCBH  
FFCDH  
FFCFH  
CALLV #0  
CALLV #1  
CALLV #2  
CALLV #3  
CALLV #4  
CALLV #5  
CALLV #6  
CALLV #7  
Table address  
Upper data  
FFE4H  
FFE6H  
FFE8H  
FFEAH  
FFECH  
FFFEH  
FFF0H  
FFF2H  
FFF4H  
FFF6H  
FFF8H  
FFFAH  
– – – –  
FFFEH  
Lower data  
FFE5H  
FFE7H  
FFE9H  
FFEBH  
FFEDH  
FFEFH  
FFF1H  
FFF3H  
FFF5H  
FFF7H  
FFF9H  
FFFBH  
FFFDH  
FFFFH  
Interrupt #11  
Interrupt #10  
Interrupt #9  
Interrupt #8  
Interrupt #7  
Interrupt #6  
Interrupt #5  
Interrupt #4  
Interrupt #3  
Interrupt #2  
Interrupt #1  
Interrupt #0  
Reset mode  
Reset vector  
Note:  
FFFCH is already reserved.  
Set 00H for FFFDH in the Reset mode.  
15  
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CHAPTER 2 HARDWARE CONFIGRATION  
Arrangement of 16-bit Data in Memory  
When the MB89990 series of microcontrollers handle 16-bit data, the data written at the lower  
address is treated as the upper data and that written at the next address is treated as the lower  
data as shown in Figure 2.1-2 "Arrangement of 16 bit Data in Memory".  
Figure 2.1-2 Arrangement of 16 bit Data in Memory  
Memory  
Memory  
Before execution  
After execution  
MOVW ABCDH , A  
ABCFH  
ABCFH  
ABCEH  
ABCDH  
ABCCH  
ABCEH  
ABCDH  
ABCCH  
34H  
12H  
1234H  
1234H  
A
A
This is the same as when 16 bits are specified by the operand during execution of an  
instruction. Bits closer to the OP code are treated as the upper byte and those next to it are  
treated as the lower byte. This is also the same when the memory address or 16-bit immediate  
data is specified by the operand.  
Figure 2.1-3 Arrangement of 16-bit Data during Execution of Instruction  
[Example]  
MOV A, 5678H  
; Extended address  
Assemble  
XXXXH XX XX  
XXXXH 60 56 78 ; Extended address  
XXXXH E4 12 34 ; 16-bit immediate data  
XXXXH XX  
Data saved in the stack by an interrupt is also treated in the same manner.  
Internal Registers in CPU  
The MB89990 series of microcontrollers have dedicated registers specified applications in the  
CPU and general-purpose registers in memory.  
Program counter (PC)  
Accumulator (A)  
16-bit long register indicating location where instructions  
stored  
16-bit long register where results of operations stored  
temporarily. The lower byte is used to execute 8-bit data  
processing instructions.  
Temporary accumulator (T)  
Stack pointer (SP)  
16-bit long register where the operations are performed  
between this register and the accumulator. The lower byte  
is used to execute 8-bit data processing instructions.  
16-bit long register indicating stack area  
16  
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2.1 CPU  
Processor status (PS)  
16-bit long register where register pointers and condition  
codes stored  
Index register (IX)  
Extra pointer (EP)  
16-bit long register for index modification  
16-bit long register for memory addressing  
16 bits  
P C  
A
Program counter  
Accumulator  
T
Temporary accumulator  
Index register  
IX  
EP  
SP  
PS  
Extra pointer  
Stack pointer  
Processor status  
The 16 bits of the processor status (PS) can be divided into 8 upper bits for a register bank  
pointer (RP) and 8 lower bits for a condition code register (CCR). (See Figure 2.1-4 "Structure  
of Processor Status".)  
Figure 2.1-4 Structure of Processor Status  
15  
14  
13  
12  
11  
10  
9
8
7
6
I
5
4
3
2
Z
1
0
Vacant Vacant Vacant  
PS  
RP  
H
IL1, 0  
N
V
C
RP  
CCR  
The RP indicates the address of the current register bank. The contents of the RP and the real  
addresses are translated as shown in Figure 2.1-5 "Rule for Translating Real Addresses at  
General-purpose Register Area" .  
Figure 2.1-5 Rule for Translating Real Addresses at General-purpose Register Area  
R P  
Lower bits of OP code  
'0' '0' '0' '0' '0' '0' '0' '1' R4 R3 R2 R1 R0 b2 b1 b0  
Source address  
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
The CCR has bits indicating the results of operations and transfer data contents, and bits  
controlling the CPU operation when an interrupt occurs.  
- H-flag  
H-flag is set when a carry or a borrow out of bit 3 into bit 4 is generated  
as a result of operations. It is cleared in other cases. This flag is used  
for decimal-correction instructions.  
17  
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CHAPTER 2 HARDWARE CONFIGRATION  
- I-flag  
An interrupt is enabled when this flag is 1 and is disabled when it is 0.  
The I-flag is 0 at reset.  
- IL1 and IL0  
These bits indicate the level of the currently-enabled interrupt. The  
Interrupt Processing executes interrupt processing only when an  
interrupt with a value smaller than the value indicated by this bit is  
requested.  
IL1 IL0 Interrupt level  
High and low  
High  
0
0
1
1
0
1
0
1
1
2
3
Low = No interrupt  
- N-flag  
- Z-flag  
- V-flag  
- C-flag  
The N-flag is set when the most significant bit is 1 as a result of  
operations. It is cleared when the MSB is 0.  
Z-flag is set when the bit is 0 as a result of operations. It is cleared in  
other cases.  
V-flag is set when a twoís complement overflow occurs as a result of  
operations. It is reset when an overflow does not occur.  
C-flag is set when a carry or a borrow out of bit 7 is generated as a  
result of operations. It is cleared in other cases. When the shift  
instruction is executed, the value of the C-flag is shifted out.  
General-purpose registers  
General-purpose registers are 8-bit long registers for storing data.  
The 8-bit long general-purpose registers are in the register banks in memory. One bank has  
eight registers and up to 16 banks are available for the MB89193 (8 banks for the MB89191).  
The register bank pointer (RP) indicates the currently-used bank.  
Figure 2.1-6 Register Bank Configuration  
Address = 0100H + 8 (RP)  
R0  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
16 banks  
Memory area  
18  
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2.2 Lock Control Block  
2.2 Lock Control Block  
• This block controls the standby operation and software reset.  
Machine Clock Control Block Diagram  
STP  
SLP  
SPL  
Pin state  
Stop  
Sleep  
CPU operation clock  
Resource operation clock  
Clock generator  
Clock control  
22/f*  
212/f  
Stop release signal  
From time-  
base timer  
Selector  
Option  
216/f  
218/f  
* f = oscillation  
frequency  
Register List  
8 bit  
Address: 0008H  
STBC  
R/W Stanby control register  
19  
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CHAPTER 2 HARDWARE CONFIGRATION  
Description of Registers  
The detail of each register is described below.  
Standby-control register (STBC)  
Bit 7  
STP  
Bit 6  
SLP  
Bit 5  
SPL  
Bit 4  
RST  
(W)  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Address: 0008  
H
(W)  
(W)  
(R/W)  
Intilial value  
0001XXXX  
B
[Bit 7] STP: Stop bit  
This bit is used to specify switching CPU to the stop mode.  
0
1
No operation  
Stop mode  
This bit is cleared at reset or stop cancellation.  
0 is always read when this bit is read.  
[Bit 6] SLP: Sleep bit  
This bit is used to specify switching the CPU and resources to the sleep mode.  
0
1
No operation  
Sleep mode  
This bit is cleared at reset, sleep or stop cancellation.  
0 is always read when this bit is read.  
[Bit 5] SPL: Pin state specifying bit  
This bit is used to specify the external pin state in the stop mode.  
0
1
Holds state and level immediately before stop mode  
High impedance  
This bit is cleared at resetting.  
[Bit 4] RST: Software reset bit  
This bit is used to specify the software reset.  
0
1
Generates 4-cycle reset signal  
No operation  
1 is always read when this bit is read.  
20  
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2.2 Lock Control Block  
Description of Operation  
Main/sub clock block has normal and low-power consumption mode.  
consumption mode are described below.  
(1) Low-power consumption mode  
The low-power  
This chip has three operation modes. The sleep mode and stop mode in the table below reduce  
the power consumption.  
Table 2.2-1 Opeating State of Low-power Consumption Modes  
Each operating clock pulse  
(4 Mhz clock)  
Clock mode  
of CPU  
Wake-up source  
in each mode  
Clock pulse  
Timebase  
timer  
Each  
resource  
CPU  
RUN  
2.0 MHz  
Various interrupt  
requests  
Oscillates  
2.0 MHz  
2.0 MHz  
Sleep  
Stops  
The SLEEP mode stops only the operating clock pulse of the CPU. Other operations are  
continued.  
The STOP mode stops the oscillation. Data can be held with the lowest power consumption  
in this mode.  
(a) SLEEP state  
• Switching to Sleep State  
Writing 1 at the SLP bit (bit6) of the STBC register switches the mode to SLEEP state.  
The SLEEP state is the mode to stop clock pulse operating the CPU. Only the CPU  
stops and the resources continue to operate.  
If an interrupt is requested when 1 is written at the SLP bit (bit 6), instruction execution  
continues without switching to the SLEEP state.  
In the SLEEP state, the values of registers and RAM immediately before entering the  
SLEEP state are held.  
Cancelling SLEEP state  
The SLEEP state is cancelled by inputting the reset signal and requesting an interrupt.  
When the reset signal is input during the SLEEP state, the CPU is switched to the reset  
state and the SLEEP state is cancelled.  
When an interrupt level higher than 11 is requested from a resource during the SLEEP  
state, the SLEEP state is cancelled.  
When the I flag and IL bit are enabled interrupt like an ordinary interrupt after cancelling,  
the CPU executes the interrupt processing. When they are disabled, the CPU executes  
the interrupt processing from the instruction next to the one before entering the SLEEP  
state.  
(b) STOP state  
Switching to STOP state  
Writing 1 at the STP bit (bit7) of the STBC register switches the mode to STOP state.  
In the STOP state, the clock oscillation, CPU, and all resources are stopped.  
21  
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CHAPTER 2 HARDWARE CONFIGRATION  
The input/output pins and output pins during the STOP state can be controlled by the  
SPL bit (bit5) of the STBC register so that they are held in the state immediately before  
entering the STOP state, or so that they enter in the high-impedance state.  
If an interrupt is requested when 1 is written at the STP bit (bit 7), instruction execution  
continues without switching to the STOP state.  
In the STOP state, the values of registers and RAM immediately before entering the  
STOP state are held.  
Cancelling STOP state  
The STOP state is cancelled either by inputting the reset signal or by requesting an  
interrupt.  
When the reset signal is input during the STOP state, the CPU is switched to the reset  
state and the STOP state is cancelled.  
When an interrupt higher than level 11 is requested from the external interrupt circuit  
during the STOP state, the STOP state is cancelled.  
When the I flag and IL bit are enabled interrupt like an ordinary interrupt after cancelling,  
the CPU executes the interrupt processing. When they are disabled, the CPU executes  
the interrupt processing from the instruction next to the one before entering the STOP  
state.  
The oscillation stabilization time can be selected by the option from any of the four types  
listed in Table 2.2-2 "Selection of Oscillation Stabilization Time".  
If the STOP state is cancelled by inputting the reset signal, the CPU is switched to the  
oscillation stabilization wait state. Therefore, the reset sequence is not executed unless  
the oscillation stabilization time is elapsed. The oscillation stabilization time corresponds  
to the oscillation stabilization time of the main clock selected by the option. However,  
when Power-on Reset is not specified by the mask option, the CPU is not switched to the  
oscillation stabilization wait state even if the STOP state is cancelled by inputting the  
reset signal.  
Table 2.2-2 Selection of Oscillation Stabilization Time  
Ocillation stabilization time  
Ocillation stabilization time with 4 MHz source clock  
218/f*  
216/f*  
212/f*  
22/f*  
Approximate 65.5 ms  
Approximate 16.4 ms  
Approximate 1.2 ms  
Approximate 0 ms  
* f = source clock frequency  
22  
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2.2 Lock Control Block  
(2) State transition diagram at low power consumption mode  
SLEEP  
Clock oscillate  
(h)  
STOP  
(f)  
Clock stop  
(e)  
(d)  
(g)  
RUN  
Clock oscillate  
(c)  
Oscillation  
stabilization waiting  
(a)  
(b)  
Power-on  
(a) When power-on reset option selected  
(b) When power-on reset option not selected  
(c) After oscillation stabilized  
(d) Set STP bit to 1.  
(e) Set SLP bit to 1.  
(f) External reset when power-on reset option not selected  
(g) External reset or interrupt when power-on reset option selected  
(h) External reset or interrupt  
23  
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CHAPTER 2 HARDWARE CONFIGRATION  
Reset Control Section  
Power-on reset  
Watchdog timer reset  
External reset  
Internal reset signal  
Reset control  
Software reset  
Reset  
There are four types of resets as shown in Table 2.2-3 "Sources of Reset".  
Table 2.2-3 Sources of Reset  
Reset name  
Power-on reset  
Description  
Turns power on  
Watchdog reset  
External-pin reset  
Software reset  
Overflows watchdog timer  
Sets external-reset pin to Low  
Writes 0 at RST bit (bit 4) of STBC  
When the power-on reset and reset during the stop state are used, the oscillation stabilization  
time is needed after the oscillator operates because the oscillator stops. The time-base timer  
controls this stabilization time. Consequently, the operation does not start immediately even  
after cancelling the reset.  
However, if the mask option without Power-on Reset is selected, no oscillation stabilization time  
is required in any state after external pins have been released from the reset.  
Note:  
When resetting a product without the power-on reset function, set a longer time than the  
optional oscillation stabilization time.  
characteristics.  
Otherwise, the reset timing matches the AC  
24  
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2.3 Interrupt Controller  
2.3 Interrupt Controller  
2
• The interrupt controller for the F MC-8L family is located between the CPU and each  
resource. This controller receives interrupt requests from the resources, assigns  
priority to them, and transfers the priority to the CPU. It also decides the priority of  
same-level interrupts.  
Block Diagram  
CPU  
F2MC-8L bus  
2
Address decorder  
Test reg-  
ister  
Level  
Resource #1  
Resource #2  
G
L
L
G
G
Level  
deciding  
block  
Same level  
priority order  
deciding block  
Interrupt vec-  
tor generation  
block  
Level  
Level  
G
Resource #n  
G
L
G
Register List  
Interrupt controller consists of interrupt-level registers (ILR1, 2, and 3) and interrupt-test register  
(ITR).  
8 bit  
Address: 007CH  
ILR1  
ILR2  
ILR3  
ITR  
W
W
W
Interrupt level register #1  
Interrupt level register #2  
Interrupt level register #3  
Interrupt test register  
Address: 007DH  
Address: 007EH  
Address: 007FH  
25  
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CHAPTER 2 HARDWARE CONFIGRATION  
Description of Registers  
The detail of each register is described below.  
(1) Interrupt levei setting register (ILR1 to ILR3)  
Bit 7  
L31  
L71  
LB1  
Bit 6  
L30  
L70  
LB0  
Bit 5  
L21  
L61  
LA1  
Bit 4  
L20  
L60  
LA0  
Bit 3  
L11  
L51  
L91  
Bit 2  
L10  
L50  
L90  
Bit 1  
L01  
L41  
L81  
Bit 0  
L00  
L40  
L80  
Address: 007C  
Address: 007D  
Address: 007E  
H
H
H
Intilial value  
11111111  
The ILRX sets the interrupt level of each resource. The digits in the center of each bit  
correspond to the interrupt numbers.  
MB89990 hardware manual  
[Example]  
L3X  
Interrupt Table address  
Interrupt control module  
IR0  
IR1  
IR2  
IR3  
number  
Upper Lower  
#0  
#1  
#2  
#3  
FFFA FFFB  
FFF8 FFF9  
FFF6 FFF7  
FFF4 FFF5  
Interrupt requests  
from resources  
#11  
FFE4 FFE5  
IRB  
When an interrupt is requested from each resource, the interrupt controller transfers the  
interrupt level based on the value set at the 2 bits of the ILRX corresponding to the interrupt to  
the CPU.  
A relation between two bits of the ILRX and the interrupt level required is shown below.  
Lx1  
0
Lx0  
X
Required interrupt level  
1
2
1
0
1
1
3 (None)  
(2) Interrupt test register (ITR)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
*
Bit 0  
*
Address: 007F  
H
The ITR used for testing. Do not access it.  
26  
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2.3 Interrupt Controller  
Description  
The functions of interrupt controllers are described below.  
Interrupt functions  
The MB89990 series of microcontrollers have 4 inputs for interrupt requests from each  
resource. The interrupt level can be set by 2-bit registers corresponding to each input.  
When an interrupt can be requested from a resource, the interrupt controller receives it  
and transfers the contents of the corresponding level register to the CPU. The interrupt to  
the device is processed as follows:  
(a) An interrupt source is generated inside each resource.  
(b) If an interrupt is enabled, an interrupt request is output from each resource to the  
interrupt controller by referring to the interrupt-enable bit inside each resource.  
(c) After receiving this interrupt request, the interrupt controller determines the priority of  
simultaneously-requested interrupts and then transfers the interrupt level for the  
applicable interrupt to the CPU.  
(d) The CPU compares the interrupt level requested from the interrupt controller with the  
IL bit in the processor status register.  
(e) As a result of the comparison, if the priority of the interrupt level is higher than that of  
the current interrupt processing level, the contents of the I-flag in the same processor  
status register are checked.  
(f)  
As a result of the check in step (e), if the I-flag is enabled for an interrupt, the  
contents of the IL bit are set to the required level. As soon as the currently-executing  
instruction is terminated, the CPU performs the interrupt processing and transfers  
control to the interrupt-processing routine.  
(g) When an interrupt source generated in step (a) is cleared by software in the userís  
interrupt processing routine, the CPU terminates the interrupt processing.  
Figure 2.3-1 "Interrupt-processing Flowchart" outlines the interrupt operation for the MB89990  
series of microcontrollers.  
Figure 2.3-1 Interrupt-processing Flowchart  
Internal bus  
Register file  
IPLA  
PS  
I
IL  
IR  
Check  
Comparator  
(f)  
(e)  
(d)  
MB89990  
(c)  
Resource  
Level  
comparator  
Enable FF  
Source FF  
AND  
(b)  
(a)  
(g)  
Resource  
Interrupt controller  
27  
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CHAPTER 2 HARDWARE CONFIGRATION  
2.4 I/O Ports  
• he MB89990 series of microcontrollers have three parallel ports and 22 pins. P00 to  
P07 and P30 to P37 serve as 8-bit I/O ports, P40 to P45 serve as 6-bit I/O ports.  
• Port0 and Port3 are also used as the I/O pin for the resource.  
List of port functions  
Table 2.4-1 List of Port Functions  
Pin  
name  
Input  
type  
Output  
type  
Function  
bit7  
P07  
bit6  
bit5  
bit4  
bit3  
bit2  
bit1  
bit0  
Parallel  
port 00 to  
07  
P06  
P05  
P04  
P03  
P02  
P01  
P00  
CMOS  
push-  
pull  
P00to  
P07  
CMOS  
External  
interrupt 2  
INT27  
P37  
INT26 INT25 INT24 INT23 INT22 INT21 INT20  
Parallel  
port 30 to  
37  
CMOS  
P36  
P35  
P34  
P3  
P32  
P31  
P30  
Cmos  
push-  
pull  
P30to  
P37  
Timer,  
External  
interrupt 1  
TO/  
INT10  
ROC  
INT12 INT11  
EC  
Hysteresis  
N-ch  
open-  
drain  
Parallel  
port 40 to  
45  
P30to  
P37  
P45  
P44  
P43  
P42  
P41  
P40  
CMOS  
Register List  
I/O port consists of the following registers.  
8 bit  
PDR0  
Initial value = XXXXXXXXB  
Initial value = 00000000B  
Initial value = XXXXXXXXB  
Initial value = 00000000B  
Initial value = XX111111B  
Address: 0000H  
Address: 0001H  
Address: 000CH  
Address: 000DH  
Address: 000EH  
R/W Port 00 to 07 data register  
Port 00 to 07 data direction register  
R/W Port 30 to 37 data register  
Port 30 to 37 data direction register  
R/W Port 40 to 47 data register  
DDR0  
PDR3  
DDR3  
PDR4  
W
W
28  
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2.4 I/O Ports  
Description of Functions  
The function of each port is described below.  
(1) P00 to P07:  
P30 to P37:  
CMOS type I/O ports  
(also used as resource input and output)  
CMOS type I/O ports  
(also used as resource input and output)  
Switching input and output  
This port has a data-direction register (DDR) and a port-data register (PDR) for each bit.  
Input and output can be set independently for each bit. The pin with the DDR set to 1 is  
set to output, and the pin with the DDR set to 0 is set to input. When the resource output  
bit is enabled, these ports are set to output irrespective of the DDR setting conditions.  
Operation for output port (DDR = 1)  
The value written at the PDR is output to the pin when the DDR is set to 1. When the  
PDR is read, usually, the value of the pin is read instead of the contents of the output  
latch. However, when the Read Modify Write instruction is executed, the contents of the  
output latch are read irrespective of the DDR setting conditions. Therefore, the bit-  
processing instruction can be used even if input and output are mixed with each other.  
When data is written to the PDR, the written data is held in the output latch irrespective of  
the DDR setting conditions.  
Operation for input port (DDR = 0)  
When used as the input port, the output impedance goes High. Therefore, when the PDR  
is read, the value of the pin is read.  
Resource output operation  
When using as the resource output, setting is performed by the resource output enable  
bit. (See the description of each resource.) Since the resource output enable bit has  
priority in switching input and output, even if the DDR is set to 0, any bit is set as the  
resource output when output is enabled at each resource. Even if the output from each  
resource is enabled, the read parallel port is effective, so the resource output value can  
be checked.  
Resource input operation  
The pin value at a port with the resource input function is always input for the resource  
input (irrespective of the setting of the DDR and resource). Set the DDR to input when  
using an external signal for the resource input.  
State when reset  
When reset, the DDR and the output enable bit for each resource are initialized to 0 and  
the output impedance goes High at all bits. When reset, the PDR is not defined.  
Therefore, set the value of the PDR before setting the DDR to output.  
State when stop  
With the SPL bit of the standby-control register set to 1, in the stop mode, the output  
impedance goes High irrespective of the value of the DDR.  
29  
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CHAPTER 2 HARDWARE CONFIGRATION  
Figure 2.4-1 Ports 00 to 07 and 30 to 37  
External interrupt enable  
Stop mode SPL = 1  
To external interrupt  
To resource input  
Stop mode SPL = 1  
Internal data bus  
Resource Resource  
output output EN  
PDR  
Pull-up resistor (option)  
PDR read  
PDR read  
(when Read Modify Write instruction executed)  
Output latch  
Pch  
PDR write  
Pch  
Nch  
DDR  
Pin  
DDR write  
Stop mode SPL = 1  
(2) P40 to P45: N-ch open-drain-type output ports  
(also used as analog input)  
Operation for output port  
The value written at the PDR is output to the pin. When the PDR is read in this port, the  
contents of the output latch is always read instead of the value of the pin.  
State when reset  
The PDR is initialized to 1 at reset, so the output register is turned off at all bits.  
State in stop mode  
When the SPL bit of the standby-control register is set to 1, in the stop mode, the output  
impedance goes High irrespective of the value of the PDR.  
30  
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2.4 I/O Ports  
Figure 2.4-2 Ports 40 to 45  
Pull-up resistor  
(option)  
PDR  
Internal data bus  
Stop  
PDR read  
Pch  
PDR read  
(when Read Modify Write instruction is executed)  
Output latch  
Pin  
PDR write  
Nch  
Stop mode (SPL = 1)  
31  
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CHAPTER 2 HARDWARE CONFIGRATION  
2.5 8/16-bit Timer (Timer 1 and Timer 2)  
• Three internal clock pulses and one external clock pulse can be selected.  
• Operation in 8-bit 2-ch mode or 16-bit 1-ch mode can be selected.  
• A square-wave output function is included.  
Block Diagram  
Figure 2.5-1 8/16-bit Timer Block Diagram  
Internal data bus  
T1STR T1STP T1CS0 T1CS1 T1OS0 T1OS1 T1IE  
T1IF  
IRQ3  
Square-wave  
output initialization  
pin control  
CLR  
P34/TO  
/INT00  
R.S  
TFF  
1/4  
Q
1/64  
MPX  
CK  
CLR  
CO  
8-bit counter  
Comparator  
1/1024  
Prescaler  
EQ  
CPU clock  
LOAD  
Compare data latch  
Data register  
P33/EC  
Data register  
LOAD  
Compare data latch  
EQ  
Comparator  
CPU clock  
Prescaler  
1/4  
CLR  
CK  
8-bit counter  
1/64  
MPX  
1/1024  
CLR  
IRQ4  
T2STR T2STP T2CS0 T2CS1  
T2IE  
T2IF  
Register List  
8 bit  
T2CR  
T1CR  
T2DR  
T1DR  
R/W Timer-2 control register  
R/W Timer-1 control register  
R/W Timer-2 data register  
R/W Timer-1 data register  
Address: 0018H  
Address: 0019H  
Address: 001AH  
Address: 001BH  
32  
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2.5 8/16-bit Timer (Timer 1 and Timer 2)  
Description of Register Details  
The detail of each register is described below.  
(1) Timer 1 control register (T1CR)  
Bit 7  
T1IF  
Bit 6  
T1IE  
Bit 5  
T1OS1  
(R/W)  
Bit 4  
T1OS0  
(R/W)  
Bit 3  
T1CS1  
(R/W)  
Bit 2  
T1CS0  
(R/W)  
Bit 1  
T1STP  
(R/W)  
Bit 0  
T1STR  
(R/W)  
Address: 0019  
H
(R/W)  
(R/W)  
Intilial value  
X00000X0  
B
[Bit 7] T1IF: Interrupt request flag  
(When write)  
0
1
Interrupt request flag clearing  
No operation  
(When read)  
0
1
No interrupt request  
Interval interrupt request  
1 is always read when the Read Modify Write instruction is executed.  
[Bit 6] T1IE: Interrupt-enable bit  
0
1
Interrupt disabled  
Interrupt enabled  
[Bit 5 and 4] T1OS1, T1OS0: Square-wave output control bit  
T1OS1  
T1OS0  
0
0
1
1
0
1
0
1
Makes square-wave output port (P43) general-purpose port  
Holds data setting square-wave output to Low level  
Holds data setting square-wave output to High level  
Sets square-wave output to held value  
When the T1STR bit is 0, the square-wave output is set to the set value.  
33  
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CHAPTER 2 HARDWARE CONFIGRATION  
[Bit 3 and 2] T1CS1, T1CS0: Clock source select bit  
Clock cycle time  
selected at 4 MHz  
T1CS1  
T1CS0  
Clock cycle time  
0
0
1
1
0
1
0
1
2.0 [µs]  
32.0 [µs]  
× 2 instruction cycle  
× 32 instruction cycle  
× 512 instruction cycle  
512 [µs]  
External clock  
Note:  
When using Timer 1 in the 8-bit mode, the clock source selection bits (T1CS1 and T1CS0) of  
the Timer 2 control register (T2CR) must be set to other than the 16-bit mode.  
[Bit 1] T1STP: Timer-stop bit  
0
1
Counting continued without clearing counter  
Counting suspended  
[Bit 0] T1STR: Timer-start bit)  
0
1
Terminates operation  
Clears counter and starts operation  
(2) Timer 2 control register (T2CR)  
Bit 7  
T21F  
(R/W)  
Bit 6  
T21E  
(R/W)  
Bit 5  
Bit 4  
Bit 3  
T2CS1  
(R/W)  
Bit 2  
T2CS0  
(R/W)  
Bit 1  
T2STP  
(R/W)  
Bit 0  
T2STR  
(R/W)  
Address: 0018  
H
(R/W)  
(R/W)  
Intilial value  
X00000X0  
B
[Bit 7] T2IF: Interrupt request flag bit  
(When write)  
0
1
Interrupt request flag clearing  
No operation  
(When read)  
0
1
No interrupt request  
Interval interrupt request  
1 is always read when the Read Modify Write instruction is executed.  
34  
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2.5 8/16-bit Timer (Timer 1 and Timer 2)  
[Bit 6] T2IE: Interrupt-enable bit  
0
1
Interrupt disabled  
Interrupt enabled  
[Bit 3 and 2]: T2CS1, T2CS0: Clock source select bit  
Clock cycle time  
selected at 4 MHz  
T2CS1  
T2CS0  
Clock cycle time  
0
0
1
1
0
1
0
1
2.0 [µs]  
32.0 [µs]  
512 [µs]  
× 2 instruction cycle  
× 32 instruction cycle  
× 512 instruction cycle  
16 bit mode  
[Bit 1] T2STP: Timer stop bit  
0
1
Operation continued without clearing counter  
Count operation suspended  
[Bit 0] T2STR: Timer start bit  
0
1
Operation stopped  
Operation started after clearing counter  
(3) Timer 1 and 2 data registers (T1DR and T2DR)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Address: 001B  
Address: 001A  
H
H
(R/W)  
(R/W)  
(R/W)  
(R/W)  
(R/W)  
(R/W)  
(R/W)  
(R/W)  
Intilial value  
XXXXXXXX  
B
Write data is the set interval times and read data is the counted times.  
35  
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CHAPTER 2 HARDWARE CONFIGRATION  
Description of Operation  
(1) 8-bit internal clock mode  
In the 8-bit internal clock mode, three internal clock inputs can be selected by setting the clock  
source select bits (T1CS1 and T1CS0, T2CS1 and T2CS0) of the timer control registers (T1CR  
and T2CR). The timer data registers (T1DR and T2DR) serve as interval time setting registers.  
To start the timer, set the interval time as the timer data registers, write 1 at the timer start bits  
(T1STR and T2STR) of the timer control registers to clear the counter to 00H, and load the  
values of the timer data registers into the compare latch. Then, counting starts.  
When the values of the counter agree with those of the timer data registers, the interval interrupt  
request flags (T1IF and T2IF) are set to 1. At this time, the counter is cleared to 00H, the values  
of the timer data registers are reloaded into the compare latch, and counting is continued. If the  
interrupt enable bits (T1IE and T2IE) are set to 1, an interrupt request is output to the CPU.  
Assuming the set value of the timer data register is n and the selected clock is φ, the interval  
time (T) can be calculated as follows.  
T = φ × (n + 1) [µs]  
Figure 2.5-2 Description Diagram for Internal Clock Mode Operation  
Matched  
Matched  
Matched  
Counter clear  
Set data value  
Compare latch  
Count value  
0000H  
T1STR  
T1IF  
T1IF = 0 (W)  
T1IF = 0 (W)  
T1IF = 0 (W)  
TO  
Figure 2.5-3 Flow Diagram for Timer Setting  
Operation mode specification  
Interval time setting  
Timer start  
T1STR = 1, T1IF = 0, T1IE = 1  
T1IF = 1  
Interrupt processing  
T1IF = 0 (W)  
Main program  
36  
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2.5 8/16-bit Timer (Timer 1 and Timer 2)  
(2) Initializing square-wave output  
The square-wave output can be set to any value only when the timer stops (T1STR = 0 and  
T2STR = 0).  
To set, proceed as follows:  
(a) Write the set values (01 and 10) at the initialize bits (T1OS1 and T1OS0, T2OS1 and  
T2OS2, respectively) of the square wave output.  
(b) Write 11 at the same bits. This initializes the square wave output to the set value. If  
the T1STR bit is set to 0, the square wave output of the pin is set to the set value  
during this write cycle.  
Figure 2.5-4 Initialization of Equivalent Circuit  
T1STR, T2STR  
Level latch  
D5  
D
D
D
Q
Q
SET  
RST  
QX  
QX  
D
D4  
Q
Q
QX  
QX  
Write  
(3) 8-bit external clock mode  
In the 8-bit external clock mode, the external clock input can be selected by setting the clock  
source select bits (T1CS1 and T1CS0) of the timer 1 control register (T1CR).  
To start the timer, write 1 at the timer start bit (T1STR) of the T1CR to clear the counter. Then,  
counting starts.  
When the value of the counter agrees with that of the timer data register setting, the interval  
interrupt request flag bit (T1IF) is set to 1. At this time, if an interrupt is enabled (T1IE = 1), an  
interrupt request is output to the CPU.  
Figure 2.5-5 External Cock Mode Operation Description Diagram  
ECK  
Counter clear  
TSTR = 1  
Count value  
Undefined  
00  
00H  
01H  
02H  
FEH  
FFH  
00H  
01H  
T1IF  
FFH  
FFH  
T1DR  
T1IF = 0 (W)  
37  
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CHAPTER 2 HARDWARE CONFIGRATION  
(4) Precautions for use of timer stop bit  
Since an input clock pulse is fixed to High level when the timer is stopped by the timer start bits,  
the count value differs depending on the state of the input clock pulse.  
When writing 00 at the timer stop and timer start bits simultaneously after stopping the timer  
with the timer stop bit, the count may be incremented by 1. Therefore, if the timer is stopped by  
the timer stop bit, read the counter and then write 00 at the timer start bits (See Figure 2.5-6  
"Operation Diagram when Timer Stop Bit is Used".).  
Figure 2.5-6 Operation Diagram when Timer Stop Bit is Used  
When input clock is High  
When input clock is Low  
CK  
CK'  
TSTP  
TSTR  
TSTR'  
Count value  
(5) 16-bit mode  
In the 16-bit mode, each bit of the timer control registers is as shown below.  
Bit 7  
T1IF  
T2IF  
Bit 6  
T1IE  
T2IF  
Bit 5  
T1OS1  
Bit 4  
T1OS0  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Address: 0019  
Address: 0018  
T1CS1  
TECS1  
T1CS0  
TECS0  
T1STP  
T2STP  
T1STR  
T2STR  
H
H
No operation  
Set to 00  
Set to 11  
No operation  
In the 16-bit mode, write 11 at the T2CS1 and T2CS0 bits of the T2CR and set 00 at the T2OS1  
and T2OS0 bits.  
When in the 16-bit mode, the timer is controlled by the T1CR. The timer data registers T2DR  
and T1DR use the upper and lower bytes, respectively.  
The clock source is selected by the T1CS1 and T1CS0 bits of the T1CR. To start the timer,  
write 1 at the T1STR bit of the T1CR to clear the counter.  
If the value of the counter agrees with that of the timer data register, the T1IF bit is set to 1. At  
this time, an interrupt request is output to the CPU if the T1IE bit is 1.  
Note:  
To read the value of the counter in the 16-bit mode, always read the value twice to check  
that it is valid, and then use the data.  
See the 8-bit operation diagram for 16-bit mode operation.  
38  
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2.6 External Interrupt 1  
2.6 External Interrupt 1  
• The edges of three external-interrupt sources (INT10 to INT12) can be detected to  
set the corresponding flag.  
• An interrupt can be generated at the same time the flag is set.  
• The three interrupts can release the STOP or SLEEP mode.  
Block diagram  
P35/INT11  
MUX  
MUX  
P34/TO/  
INT 10  
EIR1  
SL11  
SL10  
EIE1  
EIR0  
SL01  
SL00  
EIE0  
EIC1  
IRQ0  
IRQ1  
P36/INT12  
MUX  
EIR2  
SL21  
SL20  
EIE2  
EIC2  
IRQ2  
Registers  
8 bit  
Address: 0023H  
Address: 0024H  
EIC1  
EIC2  
R/W External-interrupt control register 1  
R/W External-interrupt control register 2  
39  
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CHAPTER 2 HARDWARE CONFIGRATION  
Description of Registers  
(1) External-interrupt control register 1 (EIC1)  
The EIC1 controls interrupts by the INT10 and INT11 pins.  
Bit 7  
EIR1  
(R/W)  
Bit 6  
SL11  
(R/W)  
Bit 5  
SL10  
(R/W)  
Bit 4  
EIE1  
(R/W)  
Bit 3  
EIR0  
(R/W)  
Bit 2  
SL01  
(R/W)  
Bit 1  
SL00  
(R/W)  
Bit 0  
EIE0  
(R/W)  
Address: 0023  
H
Intilial value  
00000000  
B
[Bit 7] EIR1: External-interrupt request flag  
When the edge specified by the SL11 and SL10 bits is input to the INT11 pin, bit 7 is set to 1.  
When the EIE1 bit is 1, an interrupt request (IRQ1) is output if this bit is set.  
The meaning of each bit to be read is as follows:  
0
1
Specified edge not input to INT11 pin  
Specified edge input to INT11 pin (IRQ1 is output.)  
1 is always read when the Read Modify Write instruction is read.  
The meaning of each bit to be written is as follows:  
0
1
This bit is cleared.  
This bit does not change nor affect other bits.  
[Bit 6 and 5] SL11, SL10: Edge-polarity select bit  
This bit is used to control the input edge polarity of the INT11 pin.  
SL11  
SL10  
0
0
1
1
0
1
0
1
No edge detection  
Rising edge  
Falling edge  
Both-edge mode  
[Bit 4] EIE1: Interrupt-enable bit  
This bit is used to enable an external-interrupt request by the INT11 pin.  
0
1
Interrupt request disabled  
Interrupt request enabled by EIR1 setting  
40  
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2.6 External Interrupt 1  
[Bit 3] EIR0: External-interrupt request flag  
When the edge specified by the SL01 and SL00 bits is input to the INT10 pin, bit 3 is set to 1.  
When the EIE0 is 1, an interrupt request (IRQ0) is output if this bit is set.  
The meaning of each bit to be read is as follows:  
0
1
Specified edge not input to INT10 pin  
Specified edge input to INT10 pin (IRQ0 is output.)  
1 is always read when the Read Modify Write instruction is read.  
The meaning of each bit to be written is as follows:  
0
1
This bit is cleared.  
This bit does not change nor affect other bits.  
[Bit 2 and 1] SL01, SL00: Edge-polarity select bit  
This bit is used to control the input edge polarity of the INT10 pin.  
SL01  
SL00  
0
0
1
1
0
1
0
1
No edge detection  
Rising edge  
Falling edge  
Both-edge mode  
[Bit 0] EIE0: Interrupt-enable bit  
Bit 0 is used to enable an external-interrupt request by the INT10 pin.  
0
1
Interrupt request disabled  
Interrupt request enabled by EIR0 setting  
(2) External-interrupt control register 2 (EIC2)  
The EIC2 controls an interrupt by the INT12 pins.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
EIR2  
(R/W)  
Bit 2  
SL21  
(R/W)  
Bit 1  
SL20  
(R/W)  
Bit 0  
EIE2  
(R/W)  
Address: 0024  
H
Intilial value  
----0000B  
41  
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CHAPTER 2 HARDWARE CONFIGRATION  
[Bit 3] EIR2: External-interrupt request flag  
When the edge specified by the SL21 and SL20 bit is input to the INT12 pin, bit 3 is set to 1.  
When the EIE2 bit is 1, an interrupt request (IRQ2) is output if this bit is set.  
The meaning of each bit to be read is as follows:  
0
1
Specified edge not input to INT12 pin  
Specified edge input to INT12 pin (IRQ2 is output.)  
1 is always read when the Read Modify Write instruction is read.  
The meaning of each bit to be written is as follows:  
0
1
This bit is cleared.  
This bit does not change nor affect other bits.  
[Bit 2 and 1] SL21, SL20: Edge-polarity select bit  
This bit is used to control the input edge polarity of the INT12 pin.  
SL21  
SL20  
0
0
1
1
0
1
0
1
No edge detection  
Rising edge  
Falling edge  
Both-edge mode  
[Bit 0] EIE2: Interrupt-enable bit  
This bit is used to enable an external-interrupt request by the INT12 pin.  
0
1
Interrupt request disabled  
Interrupt request enabled by setting of EIR2  
Precautions for External-interrupt Circuit  
When enabling an interrupt after clearing reset, always clear the interrupt flag  
simultaneously. An interrupt request is output immediately when the interrupt flags (EIR2,  
EIR1, EIR0) are set to 1.  
When no edge detection is specified by the edge-polarity select bit, the current input is held  
before the internal edge detection block. If an edge is specified in this state, edge detection  
may be erroneous . Therefore, always clear the flag after an edge is specified.  
42  
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2.7 External Interrupt 2 (Wake Up)  
2.7 External Interrupt 2 (Wake Up)  
• Eight external interrupt input pins  
• An interrupt request is output by Low-level input signals.  
• Also usable as wake-up input  
Block Diagram  
EIF2  
IF20  
EIE2  
7
6
5
4
3
2
1
0
P00/INT20  
P01/INT21  
P02/INT22  
P03/INT23  
P04/INT24  
Interrupt  
IRQA  
P05/INT25  
P06/INT26  
P07/INT27  
Register List  
This external interrupt 2 consists of external interrupt 2 control register (EIE2) and external  
interrupt 2 flag register (EIF2).  
8 bit  
Address: 0032H  
Address: 0033H  
EIE2  
EIF2  
R/W External-interrupt control register 2  
R/W External-interrupt flag register 2  
43  
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CHAPTER 2 HARDWARE CONFIGRATION  
Description of Registers  
The detail of each register is described below.  
(1) External interrupt 2 control register (EIE2)  
Bit 7  
IE27  
(R/W)  
Bit 6  
IE26  
(R/W)  
Bit 5  
IE25  
(R/W)  
Bit 4  
IE24  
(R/W)  
Bit 3  
IE23  
(R/W)  
Bit 2  
IE22  
(R/W)  
Bit 1  
IE21  
(R/W)  
Bit 0  
IE20  
(R/W)  
Address: 0032  
H
Intilial value  
00000000  
B
[Bit 7 to 0] IE27 to IE20: Operation-enable bit  
These bits are used to operation-enable external interrupt of INT27 to INT20.  
0
1
External interrupt operation-disabled  
External interrupt operation-enabled  
(2) External interrupt 2 control register (EIF2)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
IF20  
(R/W)  
Address: 0033  
H
Intilial value  
-------0B  
[Bit 0] IF20: Low-level detect flag bit  
This bit is used to detect LOW level of INT27 to INT20.  
(When write)  
0
1
Clears flag for detecting LOW level  
No operation  
(When read)  
0
1
No LOW level input  
LOW level input detected  
If any of the interrupt enable bits (IE27 to IE20) of the external interrupt 2 control register (EIE2)  
is 1, the Low-level detect flag bit (IF20) is set to 1 and an interrupt request is output to the CPU  
when a Low level is input to the port corresponding to this bit.  
Note:  
Unlike other resources, even if the external interrupt 2 circuit is disabled for an interrupt, it  
keeps generating interrupts until the interrupt source is cleared. Therefore, always clear the  
interrupt source (after disabling an interrupt).  
44  
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2.8 Remote-control Carrier Frequency Generator  
2.8 Remote-control Carrier Frequency Generator  
• This generator is a remote-control circuit for generating remote-control carrier  
frequencies.  
• The 6-bit binary counter is built in.  
• Four internal clock pulses can be selected to set a duty (H width) and cycle.  
Block Diagram  
Internal data bus  
RCK1  
RCK0  
RCOE  
Compare register for duty  
2/1  
P30/BZ/RCO  
CLEAR  
CLK  
1/1  
CPU clock  
Comparator  
0
1/32  
6-bit counter  
1/128  
Compare register for cycle  
Internal data bus  
CPU clock: Halved from source clock  
Register List  
8 bit  
Address: 0014H  
Address: 0015H  
RCR1  
RCR2  
R/W Remote-control register 1  
R/W Remote-control register 2  
45  
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CHAPTER 2 HARDWARE CONFIGRATION  
Description of Registers  
(1) Remote-control register 1 (RCR1)  
This register is used to select the reference clock and set the duty of remote-control carrier  
frequency.  
Bit 7  
RCK1  
(R/W)  
Bit 6  
RCK0  
(R/W)  
Bit 5  
HSC5  
(R/W)  
Bit 4  
HSC4  
(R/W)  
Bit 3  
HSC3  
(R/W)  
Bit 2  
HSC2  
(R/W)  
Bit 1  
HSC1  
(R/W)  
Bit 0  
HSC0  
(R/W)  
Address: 0014  
H
Intilial value  
00000000  
B
[Bits 7 and 6] RCK1 and RCK0: Bits for selecting the reference clock for remote-control  
carrier frequency  
These bits are used to select the reference clock for the remote-control carrier frequency.  
RCR1  
RCR0  
Reference clock at 4 MHz  
2/f (0.5 µs)  
0
0
1
1
0
1
0
1
4/f (1.0 µs)  
32/f (8.0 µs)  
128/f (32.0 µs)  
f = source clock frequency  
[Bits 5 to 0] HSC5 to HSC0: Bits for setting duty of remote-control carrier frequency  
These bits are used for the 6-bit compare register to set the duty of the remote-control carrier  
frequency.  
To set the duty of the remote-control carrier frequency, set the value subtracted 1 from the value  
calculated from the clock in binary at these bits. For example, to set a duty of 26 ms, select  
resource clock = 4/f and set 011001 (1/26 oscillation) at these 6 bits. This enables the selection  
of any duty.  
(2) Remote-control register 2 (RCR2)  
This register is used to enable the output and set the cycle of remote-control carrier frequency.  
Bit 7  
RCEN  
(R/W)  
Bit 6  
Bit 5  
SCL5  
(R/W)  
Bit 4  
SCL4  
(R/W)  
Bit 3  
SCL3  
(R/W)  
Bit 2  
SCL2  
(R/W)  
Bit 1  
SCL1  
(R/W)  
Bit 0  
SCL0  
(R/W)  
Address: 0015  
H
Intilial value  
00000000  
B
[Bit 7] RCEN: Bit for enabling output of remote-control carrier frequency  
This bit is used to enable the output of remote-control carrier frequency to the P37/BZ/RCO pin.  
Setting this bit to 0 enables clearing of the 6-bit counter.  
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2.8 Remote-control Carrier Frequency Generator  
[Bits 5 to 0] SCL5 to SCL0: Bits for setting cycle of remote-control carrier frequency  
These bits are used for the 6-bit compare register to set the cycle of the remote-control carrier  
frequency. To set the cycle of the remote-control carrier frequency, set the value subtracted 1  
from the value calculated from the clock source in binary at these bits. For example, to set a  
cycle of 60 ms, select reference clock = 4/f and set 111011 (1/60 oscillation) at these 6 bits.  
This enables selection of a cycle of 60 µs.  
Description of Operation  
Remote-control registers 1 and 2 (RCR1 and RCR2) control a 6-bit counter to output the  
remote-control carrier frequency to the P37/BZ/RCO pin.  
A usage example is given below.  
<Example>  
Cycle: about 20 kHz  
Duty: 1/3  
Reference clock: 4/f (f = source clock)  
RCR1 set value: 01 010000  
Duty set value (1/22 oscillation)  
Reference clock set value  
RCR2 set value: 1X 110001  
Cycle set value (1/50 oscillation)  
Output enable  
Cycle = 50.0 µs  
Duty = 17 µs  
Note:  
To set the duty and cycle, the cycle set value must always be greater than the set duty  
value.  
47  
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CHAPTER 2 HARDWARE CONFIGRATION  
2.9 Time-base Timer  
• This timer has a 20-bit binary counter and uses a clock pulse with 1/2 oscillation of  
the source clock.  
• Four interval times can be selected.  
• This function cannot be used in the STOP state.  
Block Diagram  
2
3
7
8
4
5
9
10  
1
6
1/2  
TBTC*  
21-bit counter  
12  
16  
17  
13  
14  
18  
19  
11  
15  
20  
1/2  
TBC0  
TBC1  
TBR  
MPX  
TBIE  
TBIF  
Interrupt request  
IRQ7  
*TBTC is a clock pulse with 1/2 oscillation of the souce clock.  
Register List  
The time-base timer has time-base timer control register (TBCR).  
8 bit  
Address: 000AH  
R/W Time-base timer control register  
TBCR  
48  
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2.9 Time-base Timer  
Description of Registers  
The detail of time-base timer control register (TBCR) is described below.  
(1) Timer-base timer control register (TBCR)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
TBIE  
(R/W)  
Bit 3  
TBOF  
(R/W)  
Bit 2  
TBR  
(R/W)  
Bit 1  
TBC1  
(R/W)  
Bit 0  
TBC0  
(R/W)  
Address: 000A  
H
Intilial value  
XXX00000  
B
[Bit 4] TBIE: Interval-timer interrupt enable bit  
This bit is used to enable an interrupt by the interval timer.  
0
1
Interval interrupt disabled  
Interval interrupt enabled  
[Bit 3] TBOF: Interval timer overflow bit  
When writing, this bit is used to clear the interval timer overflow flag.  
0
1
Interval timer overflow flag cleared  
No operation  
When reading, this bit indicates that an interval timer overflow has occurred.  
0
1
Interval timer overflow not occurred  
Interval timer overflow occurred  
1 is read when the Read Modify Write instruction is read. If the TBIF bit is set to 1 when the  
TBIE bit is 1, an interrupt request is output. This bit is cleared upon reset.  
[Bit 2] TBR: Time-base timer clear bit  
This bit is used to clear time-base timer.  
0
1
Time-base timer cleared  
No operation  
1 is always read when this bit is read.  
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CHAPTER 2 HARDWARE CONFIGRATION  
[Bit 1 and 0] TBC1, TBC0: Interval time specification bit  
These bits are used to specify interval timer cycle.  
TBC1  
TBC0  
Interval time  
213/f  
Value at f = 4 MHz  
2.05 [ms]  
0
0
1
1
0
1
0
1
215/f  
8.19 [ms]  
218/f  
65.54 [ms]  
221/f  
524.29 [ms]  
f = clock frequency  
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2.10 Watchdog Timer Reset  
2.10 Watchdog Timer Reset  
• The watchdog timer is reset by using the time-base timer output as a clock.  
Block Diagram  
WTE3 to WTE0  
Start  
CLR  
Time-base timer  
2-bit counter  
Reset control  
RST  
0F  
Registers  
The watchdog timer reset has watchdog timer control register (WDTE).  
8 bit  
Address: 0009H  
WDTE  
R/W Watchdog timer control register  
Description of Register  
The detail of the watchdog timer control register (WDTE) is described below.  
(1) Watchdog timer control register (WDTE)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
WTE3  
(W)  
Bit 2  
Bit 1  
Bit 0  
Address: 0009  
WTE2 WTE1 WTE0  
(W) (W) (W)  
H
(W)  
Intilial value  
XXXXXXXX  
B
[Bits 3 to 0] WTE3 to WTE0: Watchdog timer control bit  
These bits are used to control the watchdog timer.  
First write after reset  
0101  
Watchdog timer started  
No operation  
Other than the above  
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CHAPTER 2 HARDWARE CONFIGRATION  
Second and later write  
0101  
Watchdog timer counter cleared  
No operation  
Other than the above  
The watchdog timer can be stopped only by reset. 1111 is read when these bit are read.  
Description of Operation  
(1) Starting watchdog timer  
The watchdog timer starts when 0101 is written at the watchdog timer control bits.  
(2) Clearing watchdog timer  
When 0101 is written at the watchdog timer control bits after start, the watchdog timer is  
cleared. The counter of the watchdog timer is cleared when changing to the standby mode  
(STOP, SLEEP).  
(3) Watchdog timer reset  
If the watchdog timer is not cleared within the time given in the table below, a watchdog timer  
reset occurs to reset the chip internally.  
Time-base timer cycle  
221/f  
Minimum time  
Maximum time  
Approx. 524 ms  
Approx. 1049 ms  
f : 4MHz  
(4) Stopping watchdog timer  
Once started, the watchdog timer will not stop until a reset occurs.  
52  
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CHAPTER 3 OPERATION  
The operation of MB89990 is described below.  
3.1 Clock Pulse Generator  
3.2 Reset  
3.3 Interrupt  
3.4 Low-power Consumption Modes  
3.5 Pin States for Sleep, Stop and Reset  
53  
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CHAPTER 3 OPERATION  
3.1 Clock Pulse Generator  
This section describes the clock pulse generator.  
Clock Pulse Generator  
The MB89990 series of microcontrollers incorporate the system clock pulse generator. The  
ceramic or crystal oscillator, or CR is connected to the X0 and X1 pins to generate clock pulses.  
Clock pulses can also be supplied internally by inputting externally-generated clock pulses to  
the X0 pin. The X1 pin should be kept open.  
Figure 3.1-1 Clock Pulse Generator  
MB89990  
MB89990  
X0  
X0  
Xtal  
X1  
OPEN  
X1  
C
C
MB89990  
X0  
R
X1  
C
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3.2 Reset  
3.2 Reset  
This section describes reset.  
Reset  
The detail of reset operation and reset sources are described below.  
55  
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CHAPTER 3 OPERATION  
3.2.1 Reset Operation  
The reset operation is described below.  
Reset Operation  
When reset conditions occur, the MB89990 series of microcontrollers suspend the currently-  
executing instruction to enter the reset state. The contents written at the RAM do not change  
before and after reset. However, if a reset occurs during writing of 16-bit long data, data is  
written to the upper bytes and may not be written to lower bytes. If a reset occurs around write  
timing, the contents of the addresses being written are not assured.  
When the reset conditions are cleared, the MB89990 series of microcontrollers are released  
from the reset state and start operation after fetching the mode data from address FFFDH, the  
upper bytes of the reset vectors from address FFFEH, and the lower bytes from address FFFFH,  
in that order. Figure 3.2-1 "Outline of Reset Operation" shows the flowchart for the reset  
operation.  
Figure 3.2-1 Outline of Reset Operation  
Reset clear  
Fetch mode data from address FFFDH.  
Fetch reset vectors from addresses  
FFFEH and FFFFH.  
Fetch instruction codes from reset  
vectors and execute the instruction.  
Execute the next instruction.  
Figure 3.2-2 "Reset Vector Structure" indicates the structure of data to be stored in addresses  
FFFDH, FFFEH, and FFFFH.  
Figure 3.2-2 Reset Vector Structure  
Lower 8 bits of reset vector  
FFFFH  
FFFEH  
FFFDH  
Enter the address where the instruction, which will be executed first  
after reset is cleared, is stored.  
Upper 8 bits of reset vector  
7
6
5
4
3
2
1
0
Mode data  
Reserved; always set 0.  
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3.2 Reset  
3.2.2 Reset Source  
The reset sources are described below.  
Reset Source  
The MB89990 series of microcontrollers have the following reset source.  
(1) External pin  
A Low level is input to the RST pin.  
(2) Specification by software  
0 is written at the RST bit of the standby-control register.  
(3) Power-on  
When the power is turned on when the power-on reset option is selected.  
(4) Watchdog function  
The watchdog function is enabled by the watchdog-control register and reaccess to this register  
is not obtained within the specified time.  
When the stop mode is cleared or when the power-on reset (option selected) is operated, is  
started after elapse of the oscillation stabilization time.  
57  
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CHAPTER 3 OPERATION  
3.3 Interrupt  
This section describes interrupt.  
Interrupt  
If the interrupt controller and CPU are ready to accept interrupts when an interrupt request is  
output from the internal resources or by an external-interrupt input, the CPU temporarily  
suspends the currently-executing instruction and executes the interrupt-processing program.  
Figure 3.3-1 "Interrupt-processing Flowchart" shows the interrupt-processing flowchart.  
Figure 3.3-1 Interrupt-processing Flowchart  
Internal bus  
Interrupt  
Main program  
processing  
Register file  
IPLA  
PS  
I
IL  
(5)  
IL updated  
PC, PS saved  
Reset clear  
IR  
Check  
Comparator  
(4)  
Level  
decided  
(4)  
(4)  
(6) Clear request  
(1) Initialize  
interrupt  
MB89990•CPU  
(8)  
(5)  
(3)  
Interrupt  
generation  
(7) Interrupt  
processing  
(2) Execute  
(4)  
main program  
RAM  
Restore PC, PS  
RETI  
Level  
comparator  
Enable FF  
AND  
(3)  
Source FF  
(1)  
(8)  
(6)  
PC, PS restored  
Interrupt controller  
Resource  
All interrupts are disabled after a reset is cleared. Therefore, initialize interrupts in the main  
program (1). Each resource generating interrupts and the interrupt-level-setting registers (ILR1  
to ILR3) in the interrupt controller corresponding to these interrupts are to be initialized. The  
levels of all interrupts can be set by the interrupt-level-setting registers (ILR1 to ILR3) in the  
interrupt controller. The interrupt level can be set from 1 to 3, where 1 indicates the highest  
level, and 2 the second highest level. Level 3 indicates that no interrupt occurs. The interrupt  
request of level 3 cannot be accepted. After initializing the registers, the main program  
executes various controls (2). Interrupts are generated from the resources (3). The highest-  
priority interrupt requests are identified from those occurring at the same time by the interrupt  
controller and are transferred to the CPU. The CPU then checks the current interrupt level and  
the status of the I-flag (4), and starts the interrupt processing.  
The CPU performs the interrupt processing to save the contents of the current PC and PS in the  
stack (5) and fetches the entry addresses of the interrupt program from the interrupt vectors.  
After updating the IL value in the PS to the required one, the CPU starts executing the interrupt-  
processing routine.  
Clear the interrupt sources (6) and process the interrupts in the user’s interrupt-processing  
routine. Finally, restore the PC and PS values saved by the RETI instruction in the stack (8) to  
return to the interrupted instruction.  
Note:  
Unlike the F2MC-8 family, A and T are not saved in the stack at the interrupt time.  
58  
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3.3 Interrupt  
Table 3.3-1 "Interrupt Sources and Interrupt Vectors" lists the relationships between each  
interrupt source and interrupt vector.  
Table 3.3-1 Interrupt Sources and Interrupt Vectors  
Upper vector  
address  
Lower vector  
address  
Interrupt source  
IRQ0 (External interrupt)  
FFFAH  
FFF8H  
FFF6H  
FFF4H  
FFF2H  
FFF0H  
FFEEH  
FFECH  
FFEAH  
FFE8H  
FFE6H  
FFFBH  
FFF9H  
FFF7H  
FFF5H  
FFE3H  
FFF1H  
FFEFH  
FFEDH  
FFEBH  
FFE9H  
FFE7H  
IRQ1 (External interrupt)  
IRQ2 (External interrupt)  
IRQ3 (8/16-bit timer counter timer 1)  
IRQ4 (8/16-bit timer counter timer 2)  
IRQ5 (Unused)  
IRQ6 (Unused)  
IRQ7 (Interval timer)  
IRQ8 (Unused)  
IRQ9 (Unused)  
IRQA (Wake-up)  
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CHAPTER 3 OPERATION  
3.4 Low-power Consumption Modes  
This section describes low-power consumption modes.  
Low-power Consumption Modes  
The MB89990 series of microcontrollers have two standby modes: sleep and stop to reduce the  
power consumption. Writing to the standby control register (STBC) switches to these two  
standby modes. See 2.1.4 for setting and releasing each mode.  
The MB89990 series of microcontrollers have a double clock module, and the low-power  
consumption modes vary with the main clock and subclock modes. Whether or not an  
oscillation stabilization period is required at release from each low-power consumption mode  
depends on the mask option of the power-on reset (See 2.1.4).  
Table 3.4-1 Low-power Consumption Mode at Each Clock Mode  
Main mode  
Function  
RUN  
SLEEP  
Operate  
Stop  
STOP  
Stop  
Clock oscillation  
Instruction  
ROM  
Operate  
Operate  
Stop  
CPU  
Operate  
Hold  
Hold  
RAM  
I/O  
Operate  
Operate  
Operate  
Operate  
Operate  
Operate  
Operate  
Operate  
Hold  
Hold  
Stop  
Time-base timer  
Operate  
Operate  
Operate  
Operate  
Operate  
Operate  
Stop  
16-bit timer  
8-bit SIO  
Stop  
Stop  
Resource  
ADC  
Stop  
External interrupt  
Buzzer output  
Watchdog timer  
Operate  
Stop  
Stop  
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3.5 Pin States for Sleep, Stop and Reset  
3.5 Pin States for Sleep, Stop and Reset  
This section describes the pin states for sleep, stop, and reset.  
Pin States for Sleep, Stop, and Reset  
The state of each pin of the MB89990 series of microcontrollers at sleep, stop, and reset is as  
follows:  
(1) Sleep  
The pin state immediately before the sleep state is held.  
(2) Stop  
The pin state immediately before the stop state is held when the stop mode is started and bit 5  
of the standby-control register (STBC) is set to 0; the impedance of the output and input/output  
pins goes High when the bit is set to 1.  
(3) Reset  
The impedance of all I/O and resource pins (excluding pins for pull-up option) goes High.  
Table 3.5-1 Pin State of MB89990  
Stop  
SPL = 0  
Stop  
SPL = 1  
Pin name  
Normal  
Sleep  
Reset  
P00/INT20 to  
P07/INT27  
Port/resource  
I/O  
Previous state  
Previous state  
High  
High  
impedance  
impedance*2, *3  
X0  
Input for  
ocillation  
Input for  
ocillation  
High  
impedance  
High  
impedance  
Input for  
ocillation  
X1  
Output for  
ocillation  
Output for  
ocillation  
H output  
H output  
Output for  
ocillation  
TEST  
RST  
Test input  
Test input  
Reset input  
Test input  
Reset input  
Test input  
Test input  
Reset input  
Reset input  
Reset input*1  
P30 to  
P37/RCO  
Port/resource  
I/O  
Previous state  
Previous state  
High  
High  
impedance  
impedance*2, *3  
P40 to P45  
Port  
Previous state  
Previous state  
High  
High  
impedance  
impedance*3  
*1 Reset pin is output in some option setting.  
*2 The internal input level is fixed for port and resource inputs to prevent leakage due to open input.  
However, when external interrupt is enabled, only input is allowed for P00 to P07 and P34 to P36.  
*3 Pins with the pull-up option provided by selecting the mask option are the pull-up state.  
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CHAPTER 3 OPERATION  
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CHAPTER 4 INSTRUCTIONS  
This chapter describes instructions.  
4.1 Transfer Instructions  
4.2 Operation Instruction  
4.3 Branch Instructions  
4.4 Other Instructions  
2
4.5 F MC-8L Family Instruction Map  
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CHAPTER 4 INSTRUCTIONS  
4.1 Transfer Instructions  
This section describes the transfer instructions.  
Transfer Instructions  
Mnemonic  
MOV dir,A  
MOV @IX +off,A  
MOV ext,A  
MOV @EP,A  
MOV Ri,A  
MOV A,#d8  
MOV A,dir  
MOV A,@IX +off  
MOV A,ext  
MOV A,@A  
~
#
Operation  
(A)  
TL  
TH  
AH  
NZVC  
OP code  
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir)  
AL  
AL  
AL  
AL  
AL  
AL  
AL  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
+ + – –  
+ + – –  
+ + – –  
+ + – –  
+ + – –  
+ + – –  
+ + – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
45  
46  
61  
( (IX) +off )  
(A)  
(ext)  
( (EP) )  
(Ri)  
(A)  
(A)  
(A)  
d8  
(dir)  
( (IX) +off)  
(ext)  
( (A) )  
( (EP) )  
(Ri)  
47  
48 to 4F  
04  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(dir)  
05  
06  
60  
92  
MOV A,@EP  
MOV A,Ri  
07  
08 to 0F  
MOV dir,#d8  
MOV @IX +off,#d8  
MOV @EP,#d8  
MOV Ri,#d8  
MOVW dir,A  
MOVW @IX +off,A  
d8  
85  
86  
87  
( (IX) +off )  
( (EP) )  
d8  
d8  
(Ri)  
(dir)  
d8  
(AH),(dir + 1)  
(AH),  
( (IX) +off + 1) (AL)  
88 to 8F  
D5  
(AL)  
( (IX) +off)  
D6  
(ext) (AH),(ext+1) (AL)  
((EP)) (AH),((EP)+1) (AL)  
MOVW ext,A  
MOVW @EP,A  
MOVW EP,A  
MOVW A,#d16  
MOVW A,dir  
5
4
2
3
4
5
3
1
1
3
2
2
AL  
AL  
AL  
AH  
AH  
AH  
dH  
dH  
dH  
– – – –  
– – – –  
– – – –  
+ + – –  
+ + – –  
+ + – –  
D4  
D7  
E3  
E4  
C5  
C6  
(EP)  
(A)  
(A)  
d16  
(AH)  
(AH)  
(AL)  
(dir), (AL)  
((IX) +off),  
( (IX) +off + 1)  
(dir + 1)  
MOVW A,@IX +off  
MOVW A,ext  
MOVW A,@A  
MOVW A,@EP  
MOVW A,EP  
MOVW EP,#d16  
MOVW IX,A  
MOVW A,IX  
MOVW SP,A  
MOVW A,SP  
MOV @A,T  
MOVW @A,T  
MOVW IX,#d16  
MOVW A,PS  
MOVW PS,A  
MOVW SP,#d16  
SWAP  
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(AH) (ext),(AL) (ext+1)  
(AH) ((A)),(AL) ((A))+1)  
(AH) ((EP)),(AL) ((EP)+1)  
AL  
AL  
AL  
AH  
AH  
AH  
dH  
dH  
dH  
dH  
dH  
dH  
dH  
AL  
+ + – –  
+ + – –  
+ + – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
+ + + +  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
C4  
93  
C7  
F3  
E7  
E2  
F2  
E1  
F1  
82  
83  
E6  
70  
71  
E5  
10  
(A)  
(EP)  
d16  
(A)  
(EP)  
(IX)  
(A)  
(IX)  
(SP)  
(A)  
( (A) )  
(A)  
(SP)  
(T)  
((A)) (TH),((A)+1) (TL)  
(IX)  
(A)  
d16  
(PS)  
(A)  
d16  
(AL)  
1
0
(TL)  
(T)  
(PS)  
(SP)  
(AH)  
(dir): b  
(dir): b  
(AL)  
(A)  
SETB dir: b  
CLRB dir: b  
XCH A,T  
A8 to AF  
A0 to A7  
42  
AL  
AL  
AH  
XCHW A,T  
dH  
dH  
dH  
dH  
dH  
43  
F7  
F6  
F5  
XCHW A,EP  
XCHW A,IX  
XCHW A,SP  
MOVW A,PC  
(A)  
(A)  
(A)  
(A)  
(EP)  
(IX)  
(SP)  
(PC)  
F0  
64  
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4.1 Transfer Instructions  
Notes  
1. During byte transfer to A, T <-- A is restricted to low bytes.  
2. Operands in more than one operand instruction must be stored in the order in which their  
mnemonics are written. (Reverse arrangement of F2MC-8 family)  
65  
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CHAPTER 4 INSTRUCTIONS  
4.2 Operation Instruction  
This section describes the operation instructions.  
Operation Instructions  
Mnemonic  
ADDC A,Ri  
ADDC A,#d8  
ADDC A,dir  
ADDC A,@IX +off  
ADDC A,@EP  
ADDCW A  
ADDC A  
SUBC A,Ri  
SUBC A,#d8  
SUBC A,dir  
SUBC A,@IX +off  
SUBC A,@EP  
SUBCW A  
SUBC A  
INC Ri  
INCW EP  
INCW IX  
INCW A  
DEC Ri  
DECW EP  
DECW IX  
DECW A  
MULU A  
DIVU A  
~
#
Operation  
TL  
TH  
AH  
NZVC  
OP code  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(AL)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(AL)  
(Ri)  
(EP)  
(IX)  
(A)  
(Ri)  
(EP)  
(IX)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A) + (Ri) + C  
(A) + d8 + C  
(A) + (dir) + C  
(A) + ( (IX) +off) + C  
(A) + ( (EP) ) + C  
(A) + (T) + C  
(AL) + (TL) + C  
(A) (Ri) C  
(A) d8 C  
(A) (dir) C  
(A) ( (IX) +off) C  
(A) ( (EP) ) C  
(T) (A) C  
(TL) (AL) C  
(Ri) + 1  
28 to 2F  
24  
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19  
21  
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
dL  
00  
dH  
dH  
dH  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + –  
– – – –  
– – – –  
+ + – –  
+ + + –  
– – – –  
– – – –  
+ + – –  
– – – –  
– – – –  
+ + R –  
+ + R –  
+ + R –  
+ + + +  
+ + + +  
+ + – +  
25  
26  
27  
23  
22  
38 to 3F  
34  
35  
36  
37  
33  
32  
C8 to CF  
(EP) + 1  
(IX) + 1  
(A) + 1  
C3  
C2  
C0  
(Ri) 1  
D8 toDF  
D3  
(EP) 1  
(IX) 1  
D2  
D0  
01  
11  
63  
73  
53  
12  
(A) 1  
dH  
dH  
00  
dH  
dH  
dH  
(AL) × (TL)  
(T) / (AL),MOD  
(A) (T)  
(T)  
ANDW A  
ORW A  
XORW A  
CMP A  
CMPW A  
RORC A  
(A) (T)  
(A) (T)  
(TL) (AL)  
(T) (A)  
13  
03  
C
A
02  
ROLC A  
2
1
+ + – +  
C
A
14  
15  
17  
CMP A,#d8  
CMP A,dir  
CMP A,@EP  
CMP A,@IX +off  
CMP A,Ri  
DAA  
DAS  
XOR A  
XOR A,#d8  
XOR A,dir  
XOR A,@EP  
XOR A,@IX +off  
XOR A,Ri  
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
1
2
1
1
1
1
2
2
1
2
1
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
(A) d8  
(A) (dir)  
(A) ( (EP) )  
(A) ( (IX) +off)  
(A) (Ri)  
16  
18 to 1F  
84  
Decimal adjust foraddition  
94  
52  
54  
55  
57  
56  
Decimal adjust forsubtraction  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(AL) (TL)  
(AL) d8  
(AL) (dir)  
(AL) ( (EP) )  
(AL) ( (IX) +off)  
(AL) (Ri)  
58 to 5F  
66  
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4.2 Operation Instruction  
Mnemonic  
AND A  
AND A,#d8  
AND A,dir  
AND A,@EP  
AND A,@IX +off  
AND A,Ri  
OR A  
OR A,#d8  
OR A,dir  
OR A,@EP  
OR A,@IX +off  
OR A,Ri  
CMP dir,#d8  
CMP @EP,#d8  
CMP @IX +off,#d8  
CMP Ri,#d8  
INCW SP  
~
#
Operation  
TL  
TH  
AH  
NZVC  
OP code  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + R –  
+ + + +  
+ + + +  
+ + + +  
+ + + +  
– – – –  
– – – –  
2
2
3
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
2
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
62  
64  
65  
67  
66  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(A)  
(AL) (TL)  
(AL) d8  
(AL) (dir)  
(AL) ( (EP) )  
(AL) ( (IX) +off)  
(AL) (Ri)  
(AL) (TL)  
(AL) d8  
(AL) (dir)  
(AL) ( (EP) )  
(AL) ( (IX) +off)  
(AL) (Ri)  
(dir) – d8  
( (EP) ) – d8  
( (IX) +off) – d8  
(Ri) – d8  
(SP) + 1  
(SP) – 1  
68 to 6F  
72  
74  
75  
77  
76  
78 to 7F  
95  
97  
96  
98 to 9F  
C1  
D1  
(SP)  
(SP)  
DECW SP  
67  
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CHAPTER 4 INSTRUCTIONS  
4.3 Branch Instructions  
This section describes the branch instructions.  
Branch Instructions  
Mnemonic  
BZ/BEQ rel  
BNZ/BNE rel  
BC/BLO rel  
BNC/BHS rel  
BN rel  
BP rel  
BLT rel  
BGE rel  
BBC dir: b,rel  
BBS dir: b,rel  
JMP @A  
JMP ext  
CALLV #vct  
CALL ext  
XCHW A,PC  
RET  
~
#
Operation  
If Z = 1 then PC  
If Z = 0 then PC  
If C = 1 then PC  
If C = 0 then PC  
If N = 1 then PC  
If N = 0 then PC  
If V N=1 then PC PC+rel  
If V N=0 then PC PC+reI  
If(dir:b)=0 then PC PC+rel  
If(dir:b)=1 then PC PC+rel  
TL  
TH  
AH  
NZVC  
OP code  
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
PC + rel  
PC + rel  
PC + rel  
PC + rel  
PC + rel  
PC + rel  
dH  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– + – –  
– + – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
Restore  
FD  
FC  
F9  
F8  
FB  
FA  
FF  
FE  
B0 to B7  
B8 to BF  
E0  
21  
E8 to EF  
31  
(PC)  
(PC)  
(A)  
ext  
Vector call  
Subroutine call  
(PC)  
(A),(A)  
(PC) + 1  
F4  
20  
30  
Return from subrountine  
Return form interrupt  
RETI  
68  
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4.4 Other Instructions  
4.4 Other Instructions  
This section describes the other instructions.  
Other Instructions  
Mnemonic  
PUSHW A  
POPW A  
PUSHW IX  
POPW IX  
NOP  
CLRC  
SETC  
CLRI  
SETI  
~
#
Operation  
TL  
TH  
AH  
NZVC  
OP code  
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
dH  
– – – –  
– – – –  
– – – –  
– – – –  
– – – –  
– – – R  
– – – S  
– – – –  
– – – –  
40  
50  
41  
51  
00  
81  
91  
80  
90  
69  
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CHAPTER 4 INSTRUCTIONS  
4.5 F2MC-8L Family Instruction Map  
2
This section describes the F MC-8L family instruction map.  
F2MC-8L Family Instruction Map  
70  
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CHAPTER 5 MASK OPTIONS  
This chapter describes mask options.  
5.1 Mask Options  
71  
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CHAPTER 5 MASK OPTIONS  
5.1 Mask Options  
This section describes the mask options.  
Mask Options  
Table 5.1-1 Mask Options  
Part number  
MB89997  
MB89P195  
MB89PV190  
Fixed  
Specify when  
ordering  
Specify when  
ordering  
No.  
Specifying procedure  
masking  
masking  
00 to P07  
P30 to P37  
Selectable by pin  
Selectable by pin  
Selectable by pin  
Selectable by pin  
Not available  
Not available  
1
2
Port pull-up resistors  
P00 to P03  
P40 to P45  
Power-on reset selection  
- Power-on reset provided  
- No power-on reset  
Selectable  
Selectable  
Enabled  
Enabled  
Selection of oscillation stabilization wait  
time (at 4.2 MHz)*1  
- 218/FC (approx. 62.4 ms)  
- 216/FC (approx. 15.6 ms)  
- 212/FC (approx. 0.98 ms)  
- 22/FC (approx. 0 ms)  
Fixed to  
216/FC  
3
Selectable  
Reset pin output  
- Reset output provided  
- No reset output  
Output  
enabled  
4
5
Selectable  
Selectable  
Selectable  
Selectable  
Oscillation type of clock  
- 1 ceramic oscillator  
- 2 crystal oscillator  
- 3 CR  
"1" only  
*1: The oscillation stabilization delay time is generated by dividing the original clock oscillation. The time  
described in this item should be used as a guideline since the oscillation cycle is unstable immediately  
after oscillation starts. "f" indicates the original oscillation frequency.  
72  
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APPENDIX  
The appendix describes I/O map and EPROM setting for MB89P195.  
APPENDIX A I/ O Map  
APPENDIX B EPROM Setting for MB89P195  
73  
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APPENDIX A I/O Map  
APPENDIX A I/O Map  
Appendix A describes the I/O map.  
/O Map  
Address  
00H  
Read/write  
(R/W)  
Register name  
PDR0  
Register description  
Port 0 data register  
01H  
(W)  
DDR0  
Port 0 data direction register  
Vacancy  
02H to 07H  
08H  
(R/W)  
(R/W)  
(R/W)  
STBC  
WDTC  
TBTC  
Standby control register  
Watchdog control register  
Time-base timer control register  
Vacancy  
09H  
0AH  
0BH  
0CH  
(R/W)  
(W)  
PDR3  
DDR3  
PDR4  
Port 3 data register  
Port 3 data direction register  
Port 4 data register  
Vacancy  
0DH  
0EH  
(R/W)  
0FH to 13H  
14H  
(R/W)  
(R/W)  
RCR1  
RCR2  
Remote-control register 1  
Remote-control register 2  
Vacancy  
15H  
16H  
17H  
Vacancy  
18H  
(R/W)  
(R/W)  
(R/W)  
(R/W)  
T2CR  
T1CR  
T2DR  
T1DR  
Timer 2 control register  
Timer 1 control register  
Timer 2 data register  
Timer 1 data register  
Vacancy  
19H  
1AH  
1BH  
1CH to 22H  
23H  
(R/W)  
(R/W)  
EIC1  
EIC2  
External interrupt control register 1  
External interrupt control register 2  
Vacancy  
24H  
25H to 31H  
32H  
(R/W)  
(R/W)  
EIE2  
EIF2  
External interrupt 2 enable register  
External interrupt 2 flag register  
Vacancy  
33H  
34H to 7BH  
74  
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APPENDIX A I/O Map  
Address  
7CH  
Read/write  
Register name  
Register description  
Interrupt level setting register 1  
(W)  
(W)  
(W)  
ILR1  
ILR2  
ILR3  
ITR  
7DH  
Interrupt level setting register 2  
Interrupt level setting register 3  
Interrupt test register  
7EH  
7FH  
Note:  
— indicate the vacant area, it is not used.  
75  
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APPENDIX B EPROM Setting for MB89P195  
APPENDIX B EPROM Setting for MB89P195  
Appendix B describes the EPROM setting for MB89P195.  
EPROM Setting for MB89P195  
MB89P195 is provided with the function corresponding to MBM27C256A by EPROM setting.  
The setting can be performed by writing program data with general-purpose EPROM writer  
through adaptor for exclusive use .  
However, the electric signature mode is not supported.  
Setting  
(1) Set the EPROM writer to MBM27C256A.  
(2) Load the program data from address 4000H to address 7FFFH of EPROM writer.  
The data is loaded from address 0C000H to address 0FFFFH in the operation mode, and from  
address 4000H to address 7FFFH in the EPROM mode.)  
(3) Write the data from 0000H with the EPROM writer.  
(Writing to the correct address cannot be performed other than from 0000H.)  
The memory space in the EPROM mode is as follows:  
Address  
0000H  
EPROM mode  
Vacant area  
(Read value: FFH)  
4000H  
Program area  
(PROM)  
7FFFH  
ROM writer adapter (Sun Hayato Co., Ltd.)  
Package  
Model No. of applicable adapter  
ROM-28SOP-28DP-8L  
FPT-28P-M02  
76  
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INDEX  
INDEX  
The index follows on the next page.  
This is listed in alphabetic order.  
77  
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INDEX  
Index  
Numerics  
interrupt.................................................................. 58  
16-bit data in memory, arrangement of..................16  
L
A
list of port function.................................................. 28  
low-power consumption mode ............................... 60  
arrangement of 16-bit data in memory...................16  
M
B
machine clock control block diagram..................... 19  
mask option............................................................ 72  
MB89P195, EPROM setting for ............................. 76  
memory space ....................................................... 14  
block diagram.................5, 25, 32, 39, 43, 45, 48, 51  
branch instruction...................................................68  
C
clock pulse generator.............................................54  
CPU, internal register in.........................................16  
O
objective and intended reader................................... i  
operation instruction............................................... 66  
operation, description of....................... 21, 36, 47, 52  
other instruction ..................................................... 69  
D
description..............................................................27  
description of function ............................................29  
description of operation........................21, 36, 47, 52  
description of register.........20, 26, 40, 44, 46, 49, 51  
description of register detail ...................................33  
P
pin assignment......................................................... 6  
pin function description ............................................ 8  
pin state for sleep, stop and reset.......................... 61  
port function, list of................................................. 28  
precaution for external-interrupt circuit .................. 42  
product series .......................................................... 3  
E
EPROM setting for MB89P195 ..............................76  
external-interrupt circuit, precaution for..................42  
F
R
F2MC-8L family Iinstruction map............................70  
feature......................................................................2  
function, description of ...........................................29  
register............................................................. 39, 51  
register detail, description of.................................. 33  
register list.......................... 19, 25, 28, 32, 43, 45, 48  
register, description of........ 20, 26, 40, 44, 46, 49, 51  
reset control section............................................... 24  
reset operation....................................................... 56  
reset source ........................................................... 57  
H
handling device ......................................................12  
I
I/O map ..................................................................74  
intended readerand objective.................................... i  
internal register in CPU..........................................16  
T
transfer instruction ................................................. 64  
78  
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CM25-10133-2E  
FUJITSU SEMICONDUCTOR • MICROCONTROLLER  
MANUAL  
2
F MC-8L FAMILY  
8-BIT MICROCONTROLLER  
MB89990 Series  
HARDWARE MANUAL  
March 2000 the second edition  
Published FUJITSU LIMITED Electronic Devices  
Edited  
Technical Communication Dept.  
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2
FUJITSU SEMICONDUCTOR  
F MC-8L FAMILY  
8-BIT MICROCONTROLLER  
MB89990 Series  
HARDWARE MANUAL  
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